2 * New driver for Marvell Yukon 2 chipset.
3 * Based on earlier sk98lin, and skge driver.
5 * This driver intentionally does not support all the features
6 * of the original driver such as link fail-over and link management because
7 * those should be done at higher levels.
9 * Copyright (C) 2005 Stephen Hemminger <shemminger@osdl.org>
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License, or
14 * (at your option) any later version.
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
26 #include <linux/config.h>
27 #include <linux/crc32.h>
28 #include <linux/kernel.h>
29 #include <linux/version.h>
30 #include <linux/module.h>
31 #include <linux/netdevice.h>
32 #include <linux/dma-mapping.h>
33 #include <linux/etherdevice.h>
34 #include <linux/ethtool.h>
35 #include <linux/pci.h>
37 #include <linux/tcp.h>
39 #include <linux/delay.h>
40 #include <linux/workqueue.h>
41 #include <linux/if_vlan.h>
42 #include <linux/prefetch.h>
43 #include <linux/mii.h>
47 #if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
48 #define SKY2_VLAN_TAG_USED 1
53 #define DRV_NAME "sky2"
54 #define DRV_VERSION "0.15"
55 #define PFX DRV_NAME " "
58 * The Yukon II chipset takes 64 bit command blocks (called list elements)
59 * that are organized into three (receive, transmit, status) different rings
60 * similar to Tigon3. A transmit can require several elements;
61 * a receive requires one (or two if using 64 bit dma).
64 #define is_ec_a1(hw) \
65 unlikely((hw)->chip_id == CHIP_ID_YUKON_EC && \
66 (hw)->chip_rev == CHIP_REV_YU_EC_A1)
68 #define RX_LE_SIZE 512
69 #define RX_LE_BYTES (RX_LE_SIZE*sizeof(struct sky2_rx_le))
70 #define RX_MAX_PENDING (RX_LE_SIZE/2 - 2)
71 #define RX_DEF_PENDING RX_MAX_PENDING
72 #define RX_SKB_ALIGN 8
74 #define TX_RING_SIZE 512
75 #define TX_DEF_PENDING (TX_RING_SIZE - 1)
76 #define TX_MIN_PENDING 64
77 #define MAX_SKB_TX_LE (4 + 2*MAX_SKB_FRAGS)
79 #define STATUS_RING_SIZE 2048 /* 2 ports * (TX + 2*RX) */
80 #define STATUS_LE_BYTES (STATUS_RING_SIZE*sizeof(struct sky2_status_le))
81 #define ETH_JUMBO_MTU 9000
82 #define TX_WATCHDOG (5 * HZ)
83 #define NAPI_WEIGHT 64
84 #define PHY_RETRIES 1000
86 static const u32 default_msg =
87 NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_LINK
88 | NETIF_MSG_TIMER | NETIF_MSG_TX_ERR | NETIF_MSG_RX_ERR
89 | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN;
91 static int debug = -1; /* defaults above */
92 module_param(debug, int, 0);
93 MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
95 static int copybreak __read_mostly = 256;
96 module_param(copybreak, int, 0);
97 MODULE_PARM_DESC(copybreak, "Receive copy threshold");
99 static int disable_msi = 0;
100 module_param(disable_msi, int, 0);
101 MODULE_PARM_DESC(disable_msi, "Disable Message Signaled Interrupt (MSI)");
103 static const struct pci_device_id sky2_id_table[] = {
104 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, 0x9000) },
105 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, 0x9E00) },
106 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4b00) },
107 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4b01) },
108 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4340) },
109 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4341) },
110 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4342) },
111 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4343) },
112 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4344) },
113 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4345) },
114 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4346) },
115 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4347) },
116 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4350) },
117 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4351) },
118 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4352) },
119 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4360) },
120 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4361) },
121 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4362) },
122 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4363) },
126 MODULE_DEVICE_TABLE(pci, sky2_id_table);
128 /* Avoid conditionals by using array */
129 static const unsigned txqaddr[] = { Q_XA1, Q_XA2 };
130 static const unsigned rxqaddr[] = { Q_R1, Q_R2 };
132 /* This driver supports yukon2 chipset only */
133 static const char *yukon2_name[] = {
135 "EC Ultra", /* 0xb4 */
136 "UNKNOWN", /* 0xb5 */
141 /* Access to external PHY */
142 static int gm_phy_write(struct sky2_hw *hw, unsigned port, u16 reg, u16 val)
146 gma_write16(hw, port, GM_SMI_DATA, val);
147 gma_write16(hw, port, GM_SMI_CTRL,
148 GM_SMI_CT_PHY_AD(PHY_ADDR_MARV) | GM_SMI_CT_REG_AD(reg));
150 for (i = 0; i < PHY_RETRIES; i++) {
151 if (!(gma_read16(hw, port, GM_SMI_CTRL) & GM_SMI_CT_BUSY))
156 printk(KERN_WARNING PFX "%s: phy write timeout\n", hw->dev[port]->name);
160 static int __gm_phy_read(struct sky2_hw *hw, unsigned port, u16 reg, u16 *val)
164 gma_write16(hw, port, GM_SMI_CTRL, GM_SMI_CT_PHY_AD(PHY_ADDR_MARV)
165 | GM_SMI_CT_REG_AD(reg) | GM_SMI_CT_OP_RD);
167 for (i = 0; i < PHY_RETRIES; i++) {
168 if (gma_read16(hw, port, GM_SMI_CTRL) & GM_SMI_CT_RD_VAL) {
169 *val = gma_read16(hw, port, GM_SMI_DATA);
179 static u16 gm_phy_read(struct sky2_hw *hw, unsigned port, u16 reg)
183 if (__gm_phy_read(hw, port, reg, &v) != 0)
184 printk(KERN_WARNING PFX "%s: phy read timeout\n", hw->dev[port]->name);
188 static int sky2_set_power_state(struct sky2_hw *hw, pci_power_t state)
195 pr_debug("sky2_set_power_state %d\n", state);
196 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
198 pci_read_config_word(hw->pdev, hw->pm_cap + PCI_PM_PMC, &power_control);
199 vaux = (sky2_read16(hw, B0_CTST) & Y2_VAUX_AVAIL) &&
200 (power_control & PCI_PM_CAP_PME_D3cold);
202 pci_read_config_word(hw->pdev, hw->pm_cap + PCI_PM_CTRL, &power_control);
204 power_control |= PCI_PM_CTRL_PME_STATUS;
205 power_control &= ~(PCI_PM_CTRL_STATE_MASK);
209 /* switch power to VCC (WA for VAUX problem) */
210 sky2_write8(hw, B0_POWER_CTRL,
211 PC_VAUX_ENA | PC_VCC_ENA | PC_VAUX_OFF | PC_VCC_ON);
213 /* disable Core Clock Division, */
214 sky2_write32(hw, B2_Y2_CLK_CTRL, Y2_CLK_DIV_DIS);
216 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1)
217 /* enable bits are inverted */
218 sky2_write8(hw, B2_Y2_CLK_GATE,
219 Y2_PCI_CLK_LNK1_DIS | Y2_COR_CLK_LNK1_DIS |
220 Y2_CLK_GAT_LNK1_DIS | Y2_PCI_CLK_LNK2_DIS |
221 Y2_COR_CLK_LNK2_DIS | Y2_CLK_GAT_LNK2_DIS);
223 sky2_write8(hw, B2_Y2_CLK_GATE, 0);
225 /* Turn off phy power saving */
226 pci_read_config_dword(hw->pdev, PCI_DEV_REG1, ®1);
227 reg1 &= ~(PCI_Y2_PHY1_POWD | PCI_Y2_PHY2_POWD);
229 /* looks like this XL is back asswards .. */
230 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1) {
231 reg1 |= PCI_Y2_PHY1_COMA;
233 reg1 |= PCI_Y2_PHY2_COMA;
235 pci_write_config_dword(hw->pdev, PCI_DEV_REG1, reg1);
240 /* Turn on phy power saving */
241 pci_read_config_dword(hw->pdev, PCI_DEV_REG1, ®1);
242 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1)
243 reg1 &= ~(PCI_Y2_PHY1_POWD | PCI_Y2_PHY2_POWD);
245 reg1 |= (PCI_Y2_PHY1_POWD | PCI_Y2_PHY2_POWD);
246 pci_write_config_dword(hw->pdev, PCI_DEV_REG1, reg1);
248 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1)
249 sky2_write8(hw, B2_Y2_CLK_GATE, 0);
251 /* enable bits are inverted */
252 sky2_write8(hw, B2_Y2_CLK_GATE,
253 Y2_PCI_CLK_LNK1_DIS | Y2_COR_CLK_LNK1_DIS |
254 Y2_CLK_GAT_LNK1_DIS | Y2_PCI_CLK_LNK2_DIS |
255 Y2_COR_CLK_LNK2_DIS | Y2_CLK_GAT_LNK2_DIS);
257 /* switch power to VAUX */
258 if (vaux && state != PCI_D3cold)
259 sky2_write8(hw, B0_POWER_CTRL,
260 (PC_VAUX_ENA | PC_VCC_ENA |
261 PC_VAUX_ON | PC_VCC_OFF));
264 printk(KERN_ERR PFX "Unknown power state %d\n", state);
268 pci_write_config_byte(hw->pdev, hw->pm_cap + PCI_PM_CTRL, power_control);
269 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
273 static void sky2_phy_reset(struct sky2_hw *hw, unsigned port)
277 /* disable all GMAC IRQ's */
278 sky2_write8(hw, SK_REG(port, GMAC_IRQ_MSK), 0);
279 /* disable PHY IRQs */
280 gm_phy_write(hw, port, PHY_MARV_INT_MASK, 0);
282 gma_write16(hw, port, GM_MC_ADDR_H1, 0); /* clear MC hash */
283 gma_write16(hw, port, GM_MC_ADDR_H2, 0);
284 gma_write16(hw, port, GM_MC_ADDR_H3, 0);
285 gma_write16(hw, port, GM_MC_ADDR_H4, 0);
287 reg = gma_read16(hw, port, GM_RX_CTRL);
288 reg |= GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA;
289 gma_write16(hw, port, GM_RX_CTRL, reg);
292 static void sky2_phy_init(struct sky2_hw *hw, unsigned port)
294 struct sky2_port *sky2 = netdev_priv(hw->dev[port]);
295 u16 ctrl, ct1000, adv, pg, ledctrl, ledover;
297 if (sky2->autoneg == AUTONEG_ENABLE && hw->chip_id != CHIP_ID_YUKON_XL) {
298 u16 ectrl = gm_phy_read(hw, port, PHY_MARV_EXT_CTRL);
300 ectrl &= ~(PHY_M_EC_M_DSC_MSK | PHY_M_EC_S_DSC_MSK |
302 ectrl |= PHY_M_EC_MAC_S(MAC_TX_CLK_25_MHZ);
304 if (hw->chip_id == CHIP_ID_YUKON_EC)
305 ectrl |= PHY_M_EC_DSC_2(2) | PHY_M_EC_DOWN_S_ENA;
307 ectrl |= PHY_M_EC_M_DSC(2) | PHY_M_EC_S_DSC(3);
309 gm_phy_write(hw, port, PHY_MARV_EXT_CTRL, ectrl);
312 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
314 if (hw->chip_id == CHIP_ID_YUKON_FE) {
315 /* enable automatic crossover */
316 ctrl |= PHY_M_PC_MDI_XMODE(PHY_M_PC_ENA_AUTO) >> 1;
318 /* disable energy detect */
319 ctrl &= ~PHY_M_PC_EN_DET_MSK;
321 /* enable automatic crossover */
322 ctrl |= PHY_M_PC_MDI_XMODE(PHY_M_PC_ENA_AUTO);
324 if (sky2->autoneg == AUTONEG_ENABLE &&
325 hw->chip_id == CHIP_ID_YUKON_XL) {
326 ctrl &= ~PHY_M_PC_DSC_MSK;
327 ctrl |= PHY_M_PC_DSC(2) | PHY_M_PC_DOWN_S_ENA;
330 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
332 /* workaround for deviation #4.88 (CRC errors) */
333 /* disable Automatic Crossover */
335 ctrl &= ~PHY_M_PC_MDIX_MSK;
336 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
338 if (hw->chip_id == CHIP_ID_YUKON_XL) {
339 /* Fiber: select 1000BASE-X only mode MAC Specific Ctrl Reg. */
340 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 2);
341 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
342 ctrl &= ~PHY_M_MAC_MD_MSK;
343 ctrl |= PHY_M_MAC_MODE_SEL(PHY_M_MAC_MD_1000BX);
344 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
346 /* select page 1 to access Fiber registers */
347 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 1);
351 ctrl = gm_phy_read(hw, port, PHY_MARV_CTRL);
352 if (sky2->autoneg == AUTONEG_DISABLE)
357 ctrl |= PHY_CT_RESET;
358 gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
364 if (sky2->autoneg == AUTONEG_ENABLE) {
366 if (sky2->advertising & ADVERTISED_1000baseT_Full)
367 ct1000 |= PHY_M_1000C_AFD;
368 if (sky2->advertising & ADVERTISED_1000baseT_Half)
369 ct1000 |= PHY_M_1000C_AHD;
370 if (sky2->advertising & ADVERTISED_100baseT_Full)
371 adv |= PHY_M_AN_100_FD;
372 if (sky2->advertising & ADVERTISED_100baseT_Half)
373 adv |= PHY_M_AN_100_HD;
374 if (sky2->advertising & ADVERTISED_10baseT_Full)
375 adv |= PHY_M_AN_10_FD;
376 if (sky2->advertising & ADVERTISED_10baseT_Half)
377 adv |= PHY_M_AN_10_HD;
378 } else /* special defines for FIBER (88E1011S only) */
379 adv |= PHY_M_AN_1000X_AHD | PHY_M_AN_1000X_AFD;
381 /* Set Flow-control capabilities */
382 if (sky2->tx_pause && sky2->rx_pause)
383 adv |= PHY_AN_PAUSE_CAP; /* symmetric */
384 else if (sky2->rx_pause && !sky2->tx_pause)
385 adv |= PHY_AN_PAUSE_ASYM | PHY_AN_PAUSE_CAP;
386 else if (!sky2->rx_pause && sky2->tx_pause)
387 adv |= PHY_AN_PAUSE_ASYM; /* local */
389 /* Restart Auto-negotiation */
390 ctrl |= PHY_CT_ANE | PHY_CT_RE_CFG;
392 /* forced speed/duplex settings */
393 ct1000 = PHY_M_1000C_MSE;
395 if (sky2->duplex == DUPLEX_FULL)
396 ctrl |= PHY_CT_DUP_MD;
398 switch (sky2->speed) {
400 ctrl |= PHY_CT_SP1000;
403 ctrl |= PHY_CT_SP100;
407 ctrl |= PHY_CT_RESET;
410 if (hw->chip_id != CHIP_ID_YUKON_FE)
411 gm_phy_write(hw, port, PHY_MARV_1000T_CTRL, ct1000);
413 gm_phy_write(hw, port, PHY_MARV_AUNE_ADV, adv);
414 gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
416 /* Setup Phy LED's */
417 ledctrl = PHY_M_LED_PULS_DUR(PULS_170MS);
420 switch (hw->chip_id) {
421 case CHIP_ID_YUKON_FE:
422 /* on 88E3082 these bits are at 11..9 (shifted left) */
423 ledctrl |= PHY_M_LED_BLINK_RT(BLINK_84MS) << 1;
425 ctrl = gm_phy_read(hw, port, PHY_MARV_FE_LED_PAR);
427 /* delete ACT LED control bits */
428 ctrl &= ~PHY_M_FELP_LED1_MSK;
429 /* change ACT LED control to blink mode */
430 ctrl |= PHY_M_FELP_LED1_CTRL(LED_PAR_CTRL_ACT_BL);
431 gm_phy_write(hw, port, PHY_MARV_FE_LED_PAR, ctrl);
434 case CHIP_ID_YUKON_XL:
435 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
437 /* select page 3 to access LED control register */
438 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
440 /* set LED Function Control register */
441 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, (PHY_M_LEDC_LOS_CTRL(1) | /* LINK/ACT */
442 PHY_M_LEDC_INIT_CTRL(7) | /* 10 Mbps */
443 PHY_M_LEDC_STA1_CTRL(7) | /* 100 Mbps */
444 PHY_M_LEDC_STA0_CTRL(7))); /* 1000 Mbps */
446 /* set Polarity Control register */
447 gm_phy_write(hw, port, PHY_MARV_PHY_STAT,
448 (PHY_M_POLC_LS1_P_MIX(4) |
449 PHY_M_POLC_IS0_P_MIX(4) |
450 PHY_M_POLC_LOS_CTRL(2) |
451 PHY_M_POLC_INIT_CTRL(2) |
452 PHY_M_POLC_STA1_CTRL(2) |
453 PHY_M_POLC_STA0_CTRL(2)));
455 /* restore page register */
456 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
460 /* set Tx LED (LED_TX) to blink mode on Rx OR Tx activity */
461 ledctrl |= PHY_M_LED_BLINK_RT(BLINK_84MS) | PHY_M_LEDC_TX_CTRL;
462 /* turn off the Rx LED (LED_RX) */
463 ledover |= PHY_M_LED_MO_RX(MO_LED_OFF);
466 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, ledctrl);
468 if (sky2->autoneg == AUTONEG_DISABLE || sky2->speed == SPEED_100) {
469 /* turn on 100 Mbps LED (LED_LINK100) */
470 ledover |= PHY_M_LED_MO_100(MO_LED_ON);
474 gm_phy_write(hw, port, PHY_MARV_LED_OVER, ledover);
476 /* Enable phy interrupt on auto-negotiation complete (or link up) */
477 if (sky2->autoneg == AUTONEG_ENABLE)
478 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_IS_AN_COMPL);
480 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_DEF_MSK);
483 /* Force a renegotiation */
484 static void sky2_phy_reinit(struct sky2_port *sky2)
486 down(&sky2->phy_sema);
487 sky2_phy_init(sky2->hw, sky2->port);
491 static void sky2_mac_init(struct sky2_hw *hw, unsigned port)
493 struct sky2_port *sky2 = netdev_priv(hw->dev[port]);
496 const u8 *addr = hw->dev[port]->dev_addr;
498 sky2_write32(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET);
499 sky2_write32(hw, SK_REG(port, GPHY_CTRL), GPC_RST_CLR|GPC_ENA_PAUSE);
501 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_CLR);
503 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0 && port == 1) {
504 /* WA DEV_472 -- looks like crossed wires on port 2 */
505 /* clear GMAC 1 Control reset */
506 sky2_write8(hw, SK_REG(0, GMAC_CTRL), GMC_RST_CLR);
508 sky2_write8(hw, SK_REG(1, GMAC_CTRL), GMC_RST_SET);
509 sky2_write8(hw, SK_REG(1, GMAC_CTRL), GMC_RST_CLR);
510 } while (gm_phy_read(hw, 1, PHY_MARV_ID0) != PHY_MARV_ID0_VAL ||
511 gm_phy_read(hw, 1, PHY_MARV_ID1) != PHY_MARV_ID1_Y2 ||
512 gm_phy_read(hw, 1, PHY_MARV_INT_MASK) != 0);
515 if (sky2->autoneg == AUTONEG_DISABLE) {
516 reg = gma_read16(hw, port, GM_GP_CTRL);
517 reg |= GM_GPCR_AU_ALL_DIS;
518 gma_write16(hw, port, GM_GP_CTRL, reg);
519 gma_read16(hw, port, GM_GP_CTRL);
521 switch (sky2->speed) {
523 reg |= GM_GPCR_SPEED_1000;
526 reg |= GM_GPCR_SPEED_100;
529 if (sky2->duplex == DUPLEX_FULL)
530 reg |= GM_GPCR_DUP_FULL;
532 reg = GM_GPCR_SPEED_1000 | GM_GPCR_SPEED_100 | GM_GPCR_DUP_FULL;
534 if (!sky2->tx_pause && !sky2->rx_pause) {
535 sky2_write32(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
537 GM_GPCR_FC_TX_DIS | GM_GPCR_FC_RX_DIS | GM_GPCR_AU_FCT_DIS;
538 } else if (sky2->tx_pause && !sky2->rx_pause) {
539 /* disable Rx flow-control */
540 reg |= GM_GPCR_FC_RX_DIS | GM_GPCR_AU_FCT_DIS;
543 gma_write16(hw, port, GM_GP_CTRL, reg);
545 sky2_read16(hw, SK_REG(port, GMAC_IRQ_SRC));
547 down(&sky2->phy_sema);
548 sky2_phy_init(hw, port);
552 reg = gma_read16(hw, port, GM_PHY_ADDR);
553 gma_write16(hw, port, GM_PHY_ADDR, reg | GM_PAR_MIB_CLR);
555 for (i = 0; i < GM_MIB_CNT_SIZE; i++)
556 gma_read16(hw, port, GM_MIB_CNT_BASE + 8 * i);
557 gma_write16(hw, port, GM_PHY_ADDR, reg);
559 /* transmit control */
560 gma_write16(hw, port, GM_TX_CTRL, TX_COL_THR(TX_COL_DEF));
562 /* receive control reg: unicast + multicast + no FCS */
563 gma_write16(hw, port, GM_RX_CTRL,
564 GM_RXCR_UCF_ENA | GM_RXCR_CRC_DIS | GM_RXCR_MCF_ENA);
566 /* transmit flow control */
567 gma_write16(hw, port, GM_TX_FLOW_CTRL, 0xffff);
569 /* transmit parameter */
570 gma_write16(hw, port, GM_TX_PARAM,
571 TX_JAM_LEN_VAL(TX_JAM_LEN_DEF) |
572 TX_JAM_IPG_VAL(TX_JAM_IPG_DEF) |
573 TX_IPG_JAM_DATA(TX_IPG_JAM_DEF) |
574 TX_BACK_OFF_LIM(TX_BOF_LIM_DEF));
576 /* serial mode register */
577 reg = DATA_BLIND_VAL(DATA_BLIND_DEF) |
578 GM_SMOD_VLAN_ENA | IPG_DATA_VAL(IPG_DATA_DEF);
580 if (hw->dev[port]->mtu > ETH_DATA_LEN)
581 reg |= GM_SMOD_JUMBO_ENA;
583 gma_write16(hw, port, GM_SERIAL_MODE, reg);
585 /* virtual address for data */
586 gma_set_addr(hw, port, GM_SRC_ADDR_2L, addr);
588 /* physical address: used for pause frames */
589 gma_set_addr(hw, port, GM_SRC_ADDR_1L, addr);
591 /* ignore counter overflows */
592 gma_write16(hw, port, GM_TX_IRQ_MSK, 0);
593 gma_write16(hw, port, GM_RX_IRQ_MSK, 0);
594 gma_write16(hw, port, GM_TR_IRQ_MSK, 0);
596 /* Configure Rx MAC FIFO */
597 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_CLR);
598 sky2_write16(hw, SK_REG(port, RX_GMF_CTRL_T),
601 /* Flush Rx MAC FIFO on any flow control or error */
602 sky2_write16(hw, SK_REG(port, RX_GMF_FL_MSK), GMR_FS_ANY_ERR);
604 /* Set threshold to 0xa (64 bytes)
605 * ASF disabled so no need to do WA dev #4.30
607 sky2_write16(hw, SK_REG(port, RX_GMF_FL_THR), RX_GMF_FL_THR_DEF);
609 /* Configure Tx MAC FIFO */
610 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_CLR);
611 sky2_write16(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_OPER_ON);
613 if (hw->chip_id == CHIP_ID_YUKON_EC_U) {
614 sky2_write8(hw, SK_REG(port, RX_GMF_LP_THR), 768/8);
615 sky2_write8(hw, SK_REG(port, RX_GMF_UP_THR), 1024/8);
616 if (hw->dev[port]->mtu > ETH_DATA_LEN) {
617 /* set Tx GMAC FIFO Almost Empty Threshold */
618 sky2_write32(hw, SK_REG(port, TX_GMF_AE_THR), 0x180);
619 /* Disable Store & Forward mode for TX */
620 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T), TX_STFW_DIS);
626 /* Assign Ram Buffer allocation.
627 * start and end are in units of 4k bytes
628 * ram registers are in units of 64bit words
630 static void sky2_ramset(struct sky2_hw *hw, u16 q, u8 startk, u8 endk)
634 start = startk * 4096/8;
635 end = (endk * 4096/8) - 1;
637 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_RST_CLR);
638 sky2_write32(hw, RB_ADDR(q, RB_START), start);
639 sky2_write32(hw, RB_ADDR(q, RB_END), end);
640 sky2_write32(hw, RB_ADDR(q, RB_WP), start);
641 sky2_write32(hw, RB_ADDR(q, RB_RP), start);
643 if (q == Q_R1 || q == Q_R2) {
644 u32 space = (endk - startk) * 4096/8;
645 u32 tp = space - space/4;
647 /* On receive queue's set the thresholds
648 * give receiver priority when > 3/4 full
649 * send pause when down to 2K
651 sky2_write32(hw, RB_ADDR(q, RB_RX_UTHP), tp);
652 sky2_write32(hw, RB_ADDR(q, RB_RX_LTHP), space/2);
655 sky2_write32(hw, RB_ADDR(q, RB_RX_UTPP), tp);
656 sky2_write32(hw, RB_ADDR(q, RB_RX_LTPP), space/4);
658 /* Enable store & forward on Tx queue's because
659 * Tx FIFO is only 1K on Yukon
661 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_STFWD);
664 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_OP_MD);
665 sky2_read8(hw, RB_ADDR(q, RB_CTRL));
668 /* Setup Bus Memory Interface */
669 static void sky2_qset(struct sky2_hw *hw, u16 q)
671 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_CLR_RESET);
672 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_OPER_INIT);
673 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_FIFO_OP_ON);
674 sky2_write32(hw, Q_ADDR(q, Q_WM), BMU_WM_DEFAULT);
677 /* Setup prefetch unit registers. This is the interface between
678 * hardware and driver list elements
680 static void sky2_prefetch_init(struct sky2_hw *hw, u32 qaddr,
683 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_RST_SET);
684 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_RST_CLR);
685 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_ADDR_HI), addr >> 32);
686 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_ADDR_LO), (u32) addr);
687 sky2_write16(hw, Y2_QADDR(qaddr, PREF_UNIT_LAST_IDX), last);
688 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_OP_ON);
690 sky2_read32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL));
693 static inline struct sky2_tx_le *get_tx_le(struct sky2_port *sky2)
695 struct sky2_tx_le *le = sky2->tx_le + sky2->tx_prod;
697 sky2->tx_prod = (sky2->tx_prod + 1) % TX_RING_SIZE;
702 * This is a workaround code taken from SysKonnect sk98lin driver
703 * to deal with chip bug on Yukon EC rev 0 in the wraparound case.
705 static void sky2_put_idx(struct sky2_hw *hw, unsigned q,
706 u16 idx, u16 *last, u16 size)
709 if (is_ec_a1(hw) && idx < *last) {
710 u16 hwget = sky2_read16(hw, Y2_QADDR(q, PREF_UNIT_GET_IDX));
713 /* Start prefetching again */
714 sky2_write8(hw, Y2_QADDR(q, PREF_UNIT_FIFO_WM), 0xe0);
718 if (hwget == size - 1) {
719 /* set watermark to one list element */
720 sky2_write8(hw, Y2_QADDR(q, PREF_UNIT_FIFO_WM), 8);
722 /* set put index to first list element */
723 sky2_write16(hw, Y2_QADDR(q, PREF_UNIT_PUT_IDX), 0);
724 } else /* have hardware go to end of list */
725 sky2_write16(hw, Y2_QADDR(q, PREF_UNIT_PUT_IDX),
729 sky2_write16(hw, Y2_QADDR(q, PREF_UNIT_PUT_IDX), idx);
736 static inline struct sky2_rx_le *sky2_next_rx(struct sky2_port *sky2)
738 struct sky2_rx_le *le = sky2->rx_le + sky2->rx_put;
739 sky2->rx_put = (sky2->rx_put + 1) % RX_LE_SIZE;
743 /* Return high part of DMA address (could be 32 or 64 bit) */
744 static inline u32 high32(dma_addr_t a)
746 return sizeof(a) > sizeof(u32) ? (a >> 16) >> 16 : 0;
749 /* Build description to hardware about buffer */
750 static void sky2_rx_add(struct sky2_port *sky2, dma_addr_t map)
752 struct sky2_rx_le *le;
753 u32 hi = high32(map);
754 u16 len = sky2->rx_bufsize;
756 if (sky2->rx_addr64 != hi) {
757 le = sky2_next_rx(sky2);
758 le->addr = cpu_to_le32(hi);
760 le->opcode = OP_ADDR64 | HW_OWNER;
761 sky2->rx_addr64 = high32(map + len);
764 le = sky2_next_rx(sky2);
765 le->addr = cpu_to_le32((u32) map);
766 le->length = cpu_to_le16(len);
768 le->opcode = OP_PACKET | HW_OWNER;
772 /* Tell chip where to start receive checksum.
773 * Actually has two checksums, but set both same to avoid possible byte
776 static void rx_set_checksum(struct sky2_port *sky2)
778 struct sky2_rx_le *le;
780 le = sky2_next_rx(sky2);
781 le->addr = (ETH_HLEN << 16) | ETH_HLEN;
783 le->opcode = OP_TCPSTART | HW_OWNER;
785 sky2_write32(sky2->hw,
786 Q_ADDR(rxqaddr[sky2->port], Q_CSR),
787 sky2->rx_csum ? BMU_ENA_RX_CHKSUM : BMU_DIS_RX_CHKSUM);
792 * The RX Stop command will not work for Yukon-2 if the BMU does not
793 * reach the end of packet and since we can't make sure that we have
794 * incoming data, we must reset the BMU while it is not doing a DMA
795 * transfer. Since it is possible that the RX path is still active,
796 * the RX RAM buffer will be stopped first, so any possible incoming
797 * data will not trigger a DMA. After the RAM buffer is stopped, the
798 * BMU is polled until any DMA in progress is ended and only then it
801 static void sky2_rx_stop(struct sky2_port *sky2)
803 struct sky2_hw *hw = sky2->hw;
804 unsigned rxq = rxqaddr[sky2->port];
807 /* disable the RAM Buffer receive queue */
808 sky2_write8(hw, RB_ADDR(rxq, RB_CTRL), RB_DIS_OP_MD);
810 for (i = 0; i < 0xffff; i++)
811 if (sky2_read8(hw, RB_ADDR(rxq, Q_RSL))
812 == sky2_read8(hw, RB_ADDR(rxq, Q_RL)))
815 printk(KERN_WARNING PFX "%s: receiver stop failed\n",
818 sky2_write32(hw, Q_ADDR(rxq, Q_CSR), BMU_RST_SET | BMU_FIFO_RST);
820 /* reset the Rx prefetch unit */
821 sky2_write32(hw, Y2_QADDR(rxq, PREF_UNIT_CTRL), PREF_UNIT_RST_SET);
824 /* Clean out receive buffer area, assumes receiver hardware stopped */
825 static void sky2_rx_clean(struct sky2_port *sky2)
829 memset(sky2->rx_le, 0, RX_LE_BYTES);
830 for (i = 0; i < sky2->rx_pending; i++) {
831 struct ring_info *re = sky2->rx_ring + i;
834 pci_unmap_single(sky2->hw->pdev,
835 re->mapaddr, sky2->rx_bufsize,
843 /* Basic MII support */
844 static int sky2_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
846 struct mii_ioctl_data *data = if_mii(ifr);
847 struct sky2_port *sky2 = netdev_priv(dev);
848 struct sky2_hw *hw = sky2->hw;
849 int err = -EOPNOTSUPP;
851 if (!netif_running(dev))
852 return -ENODEV; /* Phy still in reset */
856 data->phy_id = PHY_ADDR_MARV;
862 down(&sky2->phy_sema);
863 err = __gm_phy_read(hw, sky2->port, data->reg_num & 0x1f, &val);
871 if (!capable(CAP_NET_ADMIN))
874 down(&sky2->phy_sema);
875 err = gm_phy_write(hw, sky2->port, data->reg_num & 0x1f,
883 #ifdef SKY2_VLAN_TAG_USED
884 static void sky2_vlan_rx_register(struct net_device *dev, struct vlan_group *grp)
886 struct sky2_port *sky2 = netdev_priv(dev);
887 struct sky2_hw *hw = sky2->hw;
888 u16 port = sky2->port;
890 spin_lock_bh(&sky2->tx_lock);
892 sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T), RX_VLAN_STRIP_ON);
893 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T), TX_VLAN_TAG_ON);
896 spin_unlock_bh(&sky2->tx_lock);
899 static void sky2_vlan_rx_kill_vid(struct net_device *dev, unsigned short vid)
901 struct sky2_port *sky2 = netdev_priv(dev);
902 struct sky2_hw *hw = sky2->hw;
903 u16 port = sky2->port;
905 spin_lock_bh(&sky2->tx_lock);
907 sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T), RX_VLAN_STRIP_OFF);
908 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T), TX_VLAN_TAG_OFF);
910 sky2->vlgrp->vlan_devices[vid] = NULL;
912 spin_unlock_bh(&sky2->tx_lock);
917 * It appears the hardware has a bug in the FIFO logic that
918 * cause it to hang if the FIFO gets overrun and the receive buffer
919 * is not aligned. ALso alloc_skb() won't align properly if slab
920 * debugging is enabled.
922 static inline struct sk_buff *sky2_alloc_skb(unsigned int size, gfp_t gfp_mask)
926 skb = alloc_skb(size + RX_SKB_ALIGN, gfp_mask);
928 unsigned long p = (unsigned long) skb->data;
930 ((p + RX_SKB_ALIGN - 1) & ~(RX_SKB_ALIGN - 1)) - p);
937 * Allocate and setup receiver buffer pool.
938 * In case of 64 bit dma, there are 2X as many list elements
939 * available as ring entries
940 * and need to reserve one list element so we don't wrap around.
942 static int sky2_rx_start(struct sky2_port *sky2)
944 struct sky2_hw *hw = sky2->hw;
945 unsigned rxq = rxqaddr[sky2->port];
948 sky2->rx_put = sky2->rx_next = 0;
950 sky2_prefetch_init(hw, rxq, sky2->rx_le_map, RX_LE_SIZE - 1);
952 rx_set_checksum(sky2);
953 for (i = 0; i < sky2->rx_pending; i++) {
954 struct ring_info *re = sky2->rx_ring + i;
956 re->skb = sky2_alloc_skb(sky2->rx_bufsize, GFP_KERNEL);
960 re->mapaddr = pci_map_single(hw->pdev, re->skb->data,
961 sky2->rx_bufsize, PCI_DMA_FROMDEVICE);
962 sky2_rx_add(sky2, re->mapaddr);
965 /* Tell chip about available buffers */
966 sky2_write16(hw, Y2_QADDR(rxq, PREF_UNIT_PUT_IDX), sky2->rx_put);
967 sky2->rx_last_put = sky2_read16(hw, Y2_QADDR(rxq, PREF_UNIT_PUT_IDX));
974 /* Bring up network interface. */
975 static int sky2_up(struct net_device *dev)
977 struct sky2_port *sky2 = netdev_priv(dev);
978 struct sky2_hw *hw = sky2->hw;
979 unsigned port = sky2->port;
980 u32 ramsize, rxspace;
983 if (netif_msg_ifup(sky2))
984 printk(KERN_INFO PFX "%s: enabling interface\n", dev->name);
986 /* must be power of 2 */
987 sky2->tx_le = pci_alloc_consistent(hw->pdev,
989 sizeof(struct sky2_tx_le),
994 sky2->tx_ring = kcalloc(TX_RING_SIZE, sizeof(struct tx_ring_info),
998 sky2->tx_prod = sky2->tx_cons = 0;
1000 sky2->rx_le = pci_alloc_consistent(hw->pdev, RX_LE_BYTES,
1004 memset(sky2->rx_le, 0, RX_LE_BYTES);
1006 sky2->rx_ring = kcalloc(sky2->rx_pending, sizeof(struct ring_info),
1011 sky2_mac_init(hw, port);
1013 /* Determine available ram buffer space (in 4K blocks).
1014 * Note: not sure about the FE setting below yet
1016 if (hw->chip_id == CHIP_ID_YUKON_FE)
1019 ramsize = sky2_read8(hw, B2_E_0);
1021 /* Give transmitter one third (rounded up) */
1022 rxspace = ramsize - (ramsize + 2) / 3;
1024 sky2_ramset(hw, rxqaddr[port], 0, rxspace);
1025 sky2_ramset(hw, txqaddr[port], rxspace, ramsize);
1027 /* Make sure SyncQ is disabled */
1028 sky2_write8(hw, RB_ADDR(port == 0 ? Q_XS1 : Q_XS2, RB_CTRL),
1031 sky2_qset(hw, txqaddr[port]);
1032 if (hw->chip_id == CHIP_ID_YUKON_EC_U)
1033 sky2_write16(hw, Q_ADDR(txqaddr[port], Q_AL), 0x1a0);
1036 sky2_prefetch_init(hw, txqaddr[port], sky2->tx_le_map,
1039 err = sky2_rx_start(sky2);
1043 /* Enable interrupts from phy/mac for port */
1044 hw->intr_mask |= (port == 0) ? Y2_IS_PORT_1 : Y2_IS_PORT_2;
1045 sky2_write32(hw, B0_IMSK, hw->intr_mask);
1050 pci_free_consistent(hw->pdev, RX_LE_BYTES,
1051 sky2->rx_le, sky2->rx_le_map);
1055 pci_free_consistent(hw->pdev,
1056 TX_RING_SIZE * sizeof(struct sky2_tx_le),
1057 sky2->tx_le, sky2->tx_le_map);
1060 kfree(sky2->tx_ring);
1061 kfree(sky2->rx_ring);
1063 sky2->tx_ring = NULL;
1064 sky2->rx_ring = NULL;
1068 /* Modular subtraction in ring */
1069 static inline int tx_dist(unsigned tail, unsigned head)
1071 return (head - tail) % TX_RING_SIZE;
1074 /* Number of list elements available for next tx */
1075 static inline int tx_avail(const struct sky2_port *sky2)
1077 return sky2->tx_pending - tx_dist(sky2->tx_cons, sky2->tx_prod);
1080 /* Estimate of number of transmit list elements required */
1081 static unsigned tx_le_req(const struct sk_buff *skb)
1085 count = sizeof(dma_addr_t) / sizeof(u32);
1086 count += skb_shinfo(skb)->nr_frags * count;
1088 if (skb_shinfo(skb)->tso_size)
1091 if (skb->ip_summed == CHECKSUM_HW)
1098 * Put one packet in ring for transmit.
1099 * A single packet can generate multiple list elements, and
1100 * the number of ring elements will probably be less than the number
1101 * of list elements used.
1103 * No BH disabling for tx_lock here (like tg3)
1105 static int sky2_xmit_frame(struct sk_buff *skb, struct net_device *dev)
1107 struct sky2_port *sky2 = netdev_priv(dev);
1108 struct sky2_hw *hw = sky2->hw;
1109 struct sky2_tx_le *le = NULL;
1110 struct tx_ring_info *re;
1117 /* No BH disabling for tx_lock here. We are running in BH disabled
1118 * context and TX reclaim runs via poll inside of a software
1119 * interrupt, and no related locks in IRQ processing.
1121 if (!spin_trylock(&sky2->tx_lock))
1122 return NETDEV_TX_LOCKED;
1124 if (unlikely(tx_avail(sky2) < tx_le_req(skb))) {
1125 /* There is a known but harmless race with lockless tx
1126 * and netif_stop_queue.
1128 if (!netif_queue_stopped(dev)) {
1129 netif_stop_queue(dev);
1130 if (net_ratelimit())
1131 printk(KERN_WARNING PFX "%s: ring full when queue awake!\n",
1134 spin_unlock(&sky2->tx_lock);
1136 return NETDEV_TX_BUSY;
1139 if (unlikely(netif_msg_tx_queued(sky2)))
1140 printk(KERN_DEBUG "%s: tx queued, slot %u, len %d\n",
1141 dev->name, sky2->tx_prod, skb->len);
1143 len = skb_headlen(skb);
1144 mapping = pci_map_single(hw->pdev, skb->data, len, PCI_DMA_TODEVICE);
1145 addr64 = high32(mapping);
1147 re = sky2->tx_ring + sky2->tx_prod;
1149 /* Send high bits if changed or crosses boundary */
1150 if (addr64 != sky2->tx_addr64 || high32(mapping + len) != sky2->tx_addr64) {
1151 le = get_tx_le(sky2);
1152 le->tx.addr = cpu_to_le32(addr64);
1154 le->opcode = OP_ADDR64 | HW_OWNER;
1155 sky2->tx_addr64 = high32(mapping + len);
1158 /* Check for TCP Segmentation Offload */
1159 mss = skb_shinfo(skb)->tso_size;
1161 /* just drop the packet if non-linear expansion fails */
1162 if (skb_header_cloned(skb) &&
1163 pskb_expand_head(skb, 0, 0, GFP_ATOMIC)) {
1164 dev_kfree_skb_any(skb);
1168 mss += ((skb->h.th->doff - 5) * 4); /* TCP options */
1169 mss += (skb->nh.iph->ihl * 4) + sizeof(struct tcphdr);
1173 if (mss != sky2->tx_last_mss) {
1174 le = get_tx_le(sky2);
1175 le->tx.tso.size = cpu_to_le16(mss);
1176 le->tx.tso.rsvd = 0;
1177 le->opcode = OP_LRGLEN | HW_OWNER;
1179 sky2->tx_last_mss = mss;
1183 #ifdef SKY2_VLAN_TAG_USED
1184 /* Add VLAN tag, can piggyback on LRGLEN or ADDR64 */
1185 if (sky2->vlgrp && vlan_tx_tag_present(skb)) {
1187 le = get_tx_le(sky2);
1189 le->opcode = OP_VLAN|HW_OWNER;
1192 le->opcode |= OP_VLAN;
1193 le->length = cpu_to_be16(vlan_tx_tag_get(skb));
1198 /* Handle TCP checksum offload */
1199 if (skb->ip_summed == CHECKSUM_HW) {
1200 u16 hdr = skb->h.raw - skb->data;
1201 u16 offset = hdr + skb->csum;
1203 ctrl = CALSUM | WR_SUM | INIT_SUM | LOCK_SUM;
1204 if (skb->nh.iph->protocol == IPPROTO_UDP)
1207 le = get_tx_le(sky2);
1208 le->tx.csum.start = cpu_to_le16(hdr);
1209 le->tx.csum.offset = cpu_to_le16(offset);
1210 le->length = 0; /* initial checksum value */
1211 le->ctrl = 1; /* one packet */
1212 le->opcode = OP_TCPLISW | HW_OWNER;
1215 le = get_tx_le(sky2);
1216 le->tx.addr = cpu_to_le32((u32) mapping);
1217 le->length = cpu_to_le16(len);
1219 le->opcode = mss ? (OP_LARGESEND | HW_OWNER) : (OP_PACKET | HW_OWNER);
1221 /* Record the transmit mapping info */
1223 pci_unmap_addr_set(re, mapaddr, mapping);
1225 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
1226 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
1227 struct tx_ring_info *fre;
1229 mapping = pci_map_page(hw->pdev, frag->page, frag->page_offset,
1230 frag->size, PCI_DMA_TODEVICE);
1231 addr64 = high32(mapping);
1232 if (addr64 != sky2->tx_addr64) {
1233 le = get_tx_le(sky2);
1234 le->tx.addr = cpu_to_le32(addr64);
1236 le->opcode = OP_ADDR64 | HW_OWNER;
1237 sky2->tx_addr64 = addr64;
1240 le = get_tx_le(sky2);
1241 le->tx.addr = cpu_to_le32((u32) mapping);
1242 le->length = cpu_to_le16(frag->size);
1244 le->opcode = OP_BUFFER | HW_OWNER;
1247 + ((re - sky2->tx_ring) + i + 1) % TX_RING_SIZE;
1248 pci_unmap_addr_set(fre, mapaddr, mapping);
1251 re->idx = sky2->tx_prod;
1254 sky2_put_idx(hw, txqaddr[sky2->port], sky2->tx_prod,
1255 &sky2->tx_last_put, TX_RING_SIZE);
1257 if (tx_avail(sky2) <= MAX_SKB_TX_LE)
1258 netif_stop_queue(dev);
1261 spin_unlock(&sky2->tx_lock);
1263 dev->trans_start = jiffies;
1264 return NETDEV_TX_OK;
1268 * Free ring elements from starting at tx_cons until "done"
1270 * NB: the hardware will tell us about partial completion of multi-part
1271 * buffers; these are deferred until completion.
1273 static void sky2_tx_complete(struct sky2_port *sky2, u16 done)
1275 struct net_device *dev = sky2->netdev;
1276 struct pci_dev *pdev = sky2->hw->pdev;
1280 BUG_ON(done >= TX_RING_SIZE);
1282 if (unlikely(netif_msg_tx_done(sky2)))
1283 printk(KERN_DEBUG "%s: tx done, up to %u\n",
1286 for (put = sky2->tx_cons; put != done; put = nxt) {
1287 struct tx_ring_info *re = sky2->tx_ring + put;
1288 struct sk_buff *skb = re->skb;
1291 BUG_ON(nxt >= TX_RING_SIZE);
1292 prefetch(sky2->tx_ring + nxt);
1294 /* Check for partial status */
1295 if (tx_dist(put, done) < tx_dist(put, nxt))
1299 pci_unmap_single(pdev, pci_unmap_addr(re, mapaddr),
1300 skb_headlen(skb), PCI_DMA_TODEVICE);
1302 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
1303 struct tx_ring_info *fre;
1304 fre = sky2->tx_ring + (put + i + 1) % TX_RING_SIZE;
1305 pci_unmap_page(pdev, pci_unmap_addr(fre, mapaddr),
1306 skb_shinfo(skb)->frags[i].size,
1310 dev_kfree_skb_any(skb);
1313 sky2->tx_cons = put;
1314 if (netif_queue_stopped(dev) && tx_avail(sky2) > MAX_SKB_TX_LE)
1315 netif_wake_queue(dev);
1318 /* Cleanup all untransmitted buffers, assume transmitter not running */
1319 static void sky2_tx_clean(struct sky2_port *sky2)
1321 spin_lock_bh(&sky2->tx_lock);
1322 sky2_tx_complete(sky2, sky2->tx_prod);
1323 spin_unlock_bh(&sky2->tx_lock);
1326 /* Network shutdown */
1327 static int sky2_down(struct net_device *dev)
1329 struct sky2_port *sky2 = netdev_priv(dev);
1330 struct sky2_hw *hw = sky2->hw;
1331 unsigned port = sky2->port;
1334 /* Never really got started! */
1338 if (netif_msg_ifdown(sky2))
1339 printk(KERN_INFO PFX "%s: disabling interface\n", dev->name);
1341 /* Stop more packets from being queued */
1342 netif_stop_queue(dev);
1344 /* Disable port IRQ */
1345 local_irq_disable();
1346 hw->intr_mask &= ~((sky2->port == 0) ? Y2_IS_IRQ_PHY1 : Y2_IS_IRQ_PHY2);
1347 sky2_write32(hw, B0_IMSK, hw->intr_mask);
1350 flush_scheduled_work();
1352 sky2_phy_reset(hw, port);
1354 /* Stop transmitter */
1355 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), BMU_STOP);
1356 sky2_read32(hw, Q_ADDR(txqaddr[port], Q_CSR));
1358 sky2_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL),
1359 RB_RST_SET | RB_DIS_OP_MD);
1361 ctrl = gma_read16(hw, port, GM_GP_CTRL);
1362 ctrl &= ~(GM_GPCR_TX_ENA | GM_GPCR_RX_ENA);
1363 gma_write16(hw, port, GM_GP_CTRL, ctrl);
1365 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET);
1367 /* Workaround shared GMAC reset */
1368 if (!(hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0
1369 && port == 0 && hw->dev[1] && netif_running(hw->dev[1])))
1370 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_SET);
1372 /* Disable Force Sync bit and Enable Alloc bit */
1373 sky2_write8(hw, SK_REG(port, TXA_CTRL),
1374 TXA_DIS_FSYNC | TXA_DIS_ALLOC | TXA_STOP_RC);
1376 /* Stop Interval Timer and Limit Counter of Tx Arbiter */
1377 sky2_write32(hw, SK_REG(port, TXA_ITI_INI), 0L);
1378 sky2_write32(hw, SK_REG(port, TXA_LIM_INI), 0L);
1380 /* Reset the PCI FIFO of the async Tx queue */
1381 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR),
1382 BMU_RST_SET | BMU_FIFO_RST);
1384 /* Reset the Tx prefetch units */
1385 sky2_write32(hw, Y2_QADDR(txqaddr[port], PREF_UNIT_CTRL),
1388 sky2_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL), RB_RST_SET);
1392 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_SET);
1393 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_SET);
1395 /* turn off LED's */
1396 sky2_write16(hw, B0_Y2LED, LED_STAT_OFF);
1398 synchronize_irq(hw->pdev->irq);
1400 sky2_tx_clean(sky2);
1401 sky2_rx_clean(sky2);
1403 pci_free_consistent(hw->pdev, RX_LE_BYTES,
1404 sky2->rx_le, sky2->rx_le_map);
1405 kfree(sky2->rx_ring);
1407 pci_free_consistent(hw->pdev,
1408 TX_RING_SIZE * sizeof(struct sky2_tx_le),
1409 sky2->tx_le, sky2->tx_le_map);
1410 kfree(sky2->tx_ring);
1415 sky2->rx_ring = NULL;
1416 sky2->tx_ring = NULL;
1421 static u16 sky2_phy_speed(const struct sky2_hw *hw, u16 aux)
1426 if (hw->chip_id == CHIP_ID_YUKON_FE)
1427 return (aux & PHY_M_PS_SPEED_100) ? SPEED_100 : SPEED_10;
1429 switch (aux & PHY_M_PS_SPEED_MSK) {
1430 case PHY_M_PS_SPEED_1000:
1432 case PHY_M_PS_SPEED_100:
1439 static void sky2_link_up(struct sky2_port *sky2)
1441 struct sky2_hw *hw = sky2->hw;
1442 unsigned port = sky2->port;
1445 /* Enable Transmit FIFO Underrun */
1446 sky2_write8(hw, SK_REG(port, GMAC_IRQ_MSK), GMAC_DEF_MSK);
1448 reg = gma_read16(hw, port, GM_GP_CTRL);
1449 if (sky2->duplex == DUPLEX_FULL || sky2->autoneg == AUTONEG_ENABLE)
1450 reg |= GM_GPCR_DUP_FULL;
1453 reg |= GM_GPCR_RX_ENA | GM_GPCR_TX_ENA;
1454 gma_write16(hw, port, GM_GP_CTRL, reg);
1455 gma_read16(hw, port, GM_GP_CTRL);
1457 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_DEF_MSK);
1459 netif_carrier_on(sky2->netdev);
1460 netif_wake_queue(sky2->netdev);
1462 /* Turn on link LED */
1463 sky2_write8(hw, SK_REG(port, LNK_LED_REG),
1464 LINKLED_ON | LINKLED_BLINK_OFF | LINKLED_LINKSYNC_OFF);
1466 if (hw->chip_id == CHIP_ID_YUKON_XL) {
1467 u16 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
1469 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
1470 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, PHY_M_LEDC_LOS_CTRL(1) | /* LINK/ACT */
1471 PHY_M_LEDC_INIT_CTRL(sky2->speed ==
1473 PHY_M_LEDC_STA1_CTRL(sky2->speed ==
1474 SPEED_100 ? 7 : 0) |
1475 PHY_M_LEDC_STA0_CTRL(sky2->speed ==
1476 SPEED_1000 ? 7 : 0));
1477 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
1480 if (netif_msg_link(sky2))
1481 printk(KERN_INFO PFX
1482 "%s: Link is up at %d Mbps, %s duplex, flow control %s\n",
1483 sky2->netdev->name, sky2->speed,
1484 sky2->duplex == DUPLEX_FULL ? "full" : "half",
1485 (sky2->tx_pause && sky2->rx_pause) ? "both" :
1486 sky2->tx_pause ? "tx" : sky2->rx_pause ? "rx" : "none");
1489 static void sky2_link_down(struct sky2_port *sky2)
1491 struct sky2_hw *hw = sky2->hw;
1492 unsigned port = sky2->port;
1495 gm_phy_write(hw, port, PHY_MARV_INT_MASK, 0);
1497 reg = gma_read16(hw, port, GM_GP_CTRL);
1498 reg &= ~(GM_GPCR_RX_ENA | GM_GPCR_TX_ENA);
1499 gma_write16(hw, port, GM_GP_CTRL, reg);
1500 gma_read16(hw, port, GM_GP_CTRL); /* PCI post */
1502 if (sky2->rx_pause && !sky2->tx_pause) {
1503 /* restore Asymmetric Pause bit */
1504 gm_phy_write(hw, port, PHY_MARV_AUNE_ADV,
1505 gm_phy_read(hw, port, PHY_MARV_AUNE_ADV)
1509 netif_carrier_off(sky2->netdev);
1510 netif_stop_queue(sky2->netdev);
1512 /* Turn on link LED */
1513 sky2_write8(hw, SK_REG(port, LNK_LED_REG), LINKLED_OFF);
1515 if (netif_msg_link(sky2))
1516 printk(KERN_INFO PFX "%s: Link is down.\n", sky2->netdev->name);
1517 sky2_phy_init(hw, port);
1520 static int sky2_autoneg_done(struct sky2_port *sky2, u16 aux)
1522 struct sky2_hw *hw = sky2->hw;
1523 unsigned port = sky2->port;
1526 lpa = gm_phy_read(hw, port, PHY_MARV_AUNE_LP);
1528 if (lpa & PHY_M_AN_RF) {
1529 printk(KERN_ERR PFX "%s: remote fault", sky2->netdev->name);
1533 if (hw->chip_id != CHIP_ID_YUKON_FE &&
1534 gm_phy_read(hw, port, PHY_MARV_1000T_STAT) & PHY_B_1000S_MSF) {
1535 printk(KERN_ERR PFX "%s: master/slave fault",
1536 sky2->netdev->name);
1540 if (!(aux & PHY_M_PS_SPDUP_RES)) {
1541 printk(KERN_ERR PFX "%s: speed/duplex mismatch",
1542 sky2->netdev->name);
1546 sky2->duplex = (aux & PHY_M_PS_FULL_DUP) ? DUPLEX_FULL : DUPLEX_HALF;
1548 sky2->speed = sky2_phy_speed(hw, aux);
1550 /* Pause bits are offset (9..8) */
1551 if (hw->chip_id == CHIP_ID_YUKON_XL)
1554 sky2->rx_pause = (aux & PHY_M_PS_RX_P_EN) != 0;
1555 sky2->tx_pause = (aux & PHY_M_PS_TX_P_EN) != 0;
1557 if ((sky2->tx_pause || sky2->rx_pause)
1558 && !(sky2->speed < SPEED_1000 && sky2->duplex == DUPLEX_HALF))
1559 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON);
1561 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
1567 * Interrupt from PHY are handled outside of interrupt context
1568 * because accessing phy registers requires spin wait which might
1569 * cause excess interrupt latency.
1571 static void sky2_phy_task(void *arg)
1573 struct sky2_port *sky2 = arg;
1574 struct sky2_hw *hw = sky2->hw;
1575 u16 istatus, phystat;
1577 down(&sky2->phy_sema);
1578 istatus = gm_phy_read(hw, sky2->port, PHY_MARV_INT_STAT);
1579 phystat = gm_phy_read(hw, sky2->port, PHY_MARV_PHY_STAT);
1581 if (netif_msg_intr(sky2))
1582 printk(KERN_INFO PFX "%s: phy interrupt status 0x%x 0x%x\n",
1583 sky2->netdev->name, istatus, phystat);
1585 if (istatus & PHY_M_IS_AN_COMPL) {
1586 if (sky2_autoneg_done(sky2, phystat) == 0)
1591 if (istatus & PHY_M_IS_LSP_CHANGE)
1592 sky2->speed = sky2_phy_speed(hw, phystat);
1594 if (istatus & PHY_M_IS_DUP_CHANGE)
1596 (phystat & PHY_M_PS_FULL_DUP) ? DUPLEX_FULL : DUPLEX_HALF;
1598 if (istatus & PHY_M_IS_LST_CHANGE) {
1599 if (phystat & PHY_M_PS_LINK_UP)
1602 sky2_link_down(sky2);
1605 up(&sky2->phy_sema);
1607 local_irq_disable();
1608 hw->intr_mask |= (sky2->port == 0) ? Y2_IS_IRQ_PHY1 : Y2_IS_IRQ_PHY2;
1609 sky2_write32(hw, B0_IMSK, hw->intr_mask);
1614 /* Transmit timeout is only called if we are running, carries is up
1615 * and tx queue is full (stopped).
1617 static void sky2_tx_timeout(struct net_device *dev)
1619 struct sky2_port *sky2 = netdev_priv(dev);
1620 struct sky2_hw *hw = sky2->hw;
1621 unsigned txq = txqaddr[sky2->port];
1624 /* Maybe we just missed an status interrupt */
1625 spin_lock(&sky2->tx_lock);
1626 ridx = sky2_read16(hw,
1627 sky2->port == 0 ? STAT_TXA1_RIDX : STAT_TXA2_RIDX);
1628 sky2_tx_complete(sky2, ridx);
1629 spin_unlock(&sky2->tx_lock);
1631 if (!netif_queue_stopped(dev)) {
1632 if (net_ratelimit())
1633 pr_info(PFX "transmit interrupt missed? recovered\n");
1637 if (netif_msg_timer(sky2))
1638 printk(KERN_ERR PFX "%s: tx timeout\n", dev->name);
1640 sky2_write32(hw, Q_ADDR(txq, Q_CSR), BMU_STOP);
1641 sky2_write32(hw, Y2_QADDR(txq, PREF_UNIT_CTRL), PREF_UNIT_RST_SET);
1643 sky2_tx_clean(sky2);
1646 sky2_prefetch_init(hw, txq, sky2->tx_le_map, TX_RING_SIZE - 1);
1650 #define roundup(x, y) ((((x)+((y)-1))/(y))*(y))
1651 /* Want receive buffer size to be multiple of 64 bits, and incl room for vlan */
1652 static inline unsigned sky2_buf_size(int mtu)
1654 return roundup(mtu + ETH_HLEN + 4, 8);
1657 static int sky2_change_mtu(struct net_device *dev, int new_mtu)
1659 struct sky2_port *sky2 = netdev_priv(dev);
1660 struct sky2_hw *hw = sky2->hw;
1664 if (new_mtu < ETH_ZLEN || new_mtu > ETH_JUMBO_MTU)
1667 if (hw->chip_id == CHIP_ID_YUKON_EC_U && new_mtu > ETH_DATA_LEN)
1670 if (!netif_running(dev)) {
1675 sky2_write32(hw, B0_IMSK, 0);
1677 dev->trans_start = jiffies; /* prevent tx timeout */
1678 netif_stop_queue(dev);
1679 netif_poll_disable(hw->dev[0]);
1681 ctl = gma_read16(hw, sky2->port, GM_GP_CTRL);
1682 gma_write16(hw, sky2->port, GM_GP_CTRL, ctl & ~GM_GPCR_RX_ENA);
1684 sky2_rx_clean(sky2);
1687 sky2->rx_bufsize = sky2_buf_size(new_mtu);
1688 mode = DATA_BLIND_VAL(DATA_BLIND_DEF) |
1689 GM_SMOD_VLAN_ENA | IPG_DATA_VAL(IPG_DATA_DEF);
1691 if (dev->mtu > ETH_DATA_LEN)
1692 mode |= GM_SMOD_JUMBO_ENA;
1694 gma_write16(hw, sky2->port, GM_SERIAL_MODE, mode);
1696 sky2_write8(hw, RB_ADDR(rxqaddr[sky2->port], RB_CTRL), RB_ENA_OP_MD);
1698 err = sky2_rx_start(sky2);
1699 sky2_write32(hw, B0_IMSK, hw->intr_mask);
1704 gma_write16(hw, sky2->port, GM_GP_CTRL, ctl);
1706 netif_poll_enable(hw->dev[0]);
1707 netif_wake_queue(dev);
1714 * Receive one packet.
1715 * For small packets or errors, just reuse existing skb.
1716 * For larger packets, get new buffer.
1718 static struct sk_buff *sky2_receive(struct sky2_port *sky2,
1719 u16 length, u32 status)
1721 struct ring_info *re = sky2->rx_ring + sky2->rx_next;
1722 struct sk_buff *skb = NULL;
1724 if (unlikely(netif_msg_rx_status(sky2)))
1725 printk(KERN_DEBUG PFX "%s: rx slot %u status 0x%x len %d\n",
1726 sky2->netdev->name, sky2->rx_next, status, length);
1728 sky2->rx_next = (sky2->rx_next + 1) % sky2->rx_pending;
1729 prefetch(sky2->rx_ring + sky2->rx_next);
1731 if (status & GMR_FS_ANY_ERR)
1734 if (!(status & GMR_FS_RX_OK))
1737 if ((status >> 16) != length || length > sky2->rx_bufsize)
1740 if (length < copybreak) {
1741 skb = alloc_skb(length + 2, GFP_ATOMIC);
1745 skb_reserve(skb, 2);
1746 pci_dma_sync_single_for_cpu(sky2->hw->pdev, re->mapaddr,
1747 length, PCI_DMA_FROMDEVICE);
1748 memcpy(skb->data, re->skb->data, length);
1749 skb->ip_summed = re->skb->ip_summed;
1750 skb->csum = re->skb->csum;
1751 pci_dma_sync_single_for_device(sky2->hw->pdev, re->mapaddr,
1752 length, PCI_DMA_FROMDEVICE);
1754 struct sk_buff *nskb;
1756 nskb = sky2_alloc_skb(sky2->rx_bufsize, GFP_ATOMIC);
1762 pci_unmap_single(sky2->hw->pdev, re->mapaddr,
1763 sky2->rx_bufsize, PCI_DMA_FROMDEVICE);
1764 prefetch(skb->data);
1766 re->mapaddr = pci_map_single(sky2->hw->pdev, nskb->data,
1767 sky2->rx_bufsize, PCI_DMA_FROMDEVICE);
1770 skb_put(skb, length);
1772 re->skb->ip_summed = CHECKSUM_NONE;
1773 sky2_rx_add(sky2, re->mapaddr);
1775 /* Tell receiver about new buffers. */
1776 sky2_put_idx(sky2->hw, rxqaddr[sky2->port], sky2->rx_put,
1777 &sky2->rx_last_put, RX_LE_SIZE);
1782 ++sky2->net_stats.rx_over_errors;
1786 ++sky2->net_stats.rx_errors;
1788 if (netif_msg_rx_err(sky2) && net_ratelimit())
1789 printk(KERN_INFO PFX "%s: rx error, status 0x%x length %d\n",
1790 sky2->netdev->name, status, length);
1792 if (status & (GMR_FS_LONG_ERR | GMR_FS_UN_SIZE))
1793 sky2->net_stats.rx_length_errors++;
1794 if (status & GMR_FS_FRAGMENT)
1795 sky2->net_stats.rx_frame_errors++;
1796 if (status & GMR_FS_CRC_ERR)
1797 sky2->net_stats.rx_crc_errors++;
1798 if (status & GMR_FS_RX_FF_OV)
1799 sky2->net_stats.rx_fifo_errors++;
1805 * Check for transmit complete
1807 #define TX_NO_STATUS 0xffff
1809 static void sky2_tx_check(struct sky2_hw *hw, int port, u16 last)
1811 if (last != TX_NO_STATUS) {
1812 struct net_device *dev = hw->dev[port];
1813 if (dev && netif_running(dev)) {
1814 struct sky2_port *sky2 = netdev_priv(dev);
1816 spin_lock(&sky2->tx_lock);
1817 sky2_tx_complete(sky2, last);
1818 spin_unlock(&sky2->tx_lock);
1824 * Both ports share the same status interrupt, therefore there is only
1827 static int sky2_poll(struct net_device *dev0, int *budget)
1829 struct sky2_hw *hw = ((struct sky2_port *) netdev_priv(dev0))->hw;
1830 unsigned int to_do = min(dev0->quota, *budget);
1831 unsigned int work_done = 0;
1833 u16 tx_done[2] = { TX_NO_STATUS, TX_NO_STATUS };
1835 sky2_write32(hw, STAT_CTRL, SC_STAT_CLR_IRQ);
1837 hwidx = sky2_read16(hw, STAT_PUT_IDX);
1838 BUG_ON(hwidx >= STATUS_RING_SIZE);
1841 while (hwidx != hw->st_idx) {
1842 struct sky2_status_le *le = hw->st_le + hw->st_idx;
1843 struct net_device *dev;
1844 struct sky2_port *sky2;
1845 struct sk_buff *skb;
1849 le = hw->st_le + hw->st_idx;
1850 hw->st_idx = (hw->st_idx + 1) % STATUS_RING_SIZE;
1851 prefetch(hw->st_le + hw->st_idx);
1853 BUG_ON(le->link >= 2);
1854 dev = hw->dev[le->link];
1855 if (dev == NULL || !netif_running(dev))
1858 sky2 = netdev_priv(dev);
1859 status = le32_to_cpu(le->status);
1860 length = le16_to_cpu(le->length);
1862 switch (le->opcode & ~HW_OWNER) {
1864 skb = sky2_receive(sky2, length, status);
1869 skb->protocol = eth_type_trans(skb, dev);
1870 dev->last_rx = jiffies;
1872 #ifdef SKY2_VLAN_TAG_USED
1873 if (sky2->vlgrp && (status & GMR_FS_VLAN)) {
1874 vlan_hwaccel_receive_skb(skb,
1876 be16_to_cpu(sky2->rx_tag));
1879 netif_receive_skb(skb);
1881 if (++work_done >= to_do)
1885 #ifdef SKY2_VLAN_TAG_USED
1887 sky2->rx_tag = length;
1891 sky2->rx_tag = length;
1895 skb = sky2->rx_ring[sky2->rx_next].skb;
1896 skb->ip_summed = CHECKSUM_HW;
1897 skb->csum = le16_to_cpu(status);
1901 /* TX index reports status for both ports */
1902 tx_done[0] = status & 0xffff;
1903 tx_done[1] = ((status >> 24) & 0xff)
1904 | (u16)(length & 0xf) << 8;
1908 if (net_ratelimit())
1909 printk(KERN_WARNING PFX
1910 "unknown status opcode 0x%x\n", le->opcode);
1916 sky2_tx_check(hw, 0, tx_done[0]);
1917 sky2_tx_check(hw, 1, tx_done[1]);
1919 if (likely(work_done < to_do)) {
1920 /* need to restart TX timer */
1922 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_STOP);
1923 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_START);
1926 netif_rx_complete(dev0);
1927 hw->intr_mask |= Y2_IS_STAT_BMU;
1928 sky2_write32(hw, B0_IMSK, hw->intr_mask);
1931 *budget -= work_done;
1932 dev0->quota -= work_done;
1937 static void sky2_hw_error(struct sky2_hw *hw, unsigned port, u32 status)
1939 struct net_device *dev = hw->dev[port];
1941 if (net_ratelimit())
1942 printk(KERN_INFO PFX "%s: hw error interrupt status 0x%x\n",
1945 if (status & Y2_IS_PAR_RD1) {
1946 if (net_ratelimit())
1947 printk(KERN_ERR PFX "%s: ram data read parity error\n",
1950 sky2_write16(hw, RAM_BUFFER(port, B3_RI_CTRL), RI_CLR_RD_PERR);
1953 if (status & Y2_IS_PAR_WR1) {
1954 if (net_ratelimit())
1955 printk(KERN_ERR PFX "%s: ram data write parity error\n",
1958 sky2_write16(hw, RAM_BUFFER(port, B3_RI_CTRL), RI_CLR_WR_PERR);
1961 if (status & Y2_IS_PAR_MAC1) {
1962 if (net_ratelimit())
1963 printk(KERN_ERR PFX "%s: MAC parity error\n", dev->name);
1964 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_CLI_TX_PE);
1967 if (status & Y2_IS_PAR_RX1) {
1968 if (net_ratelimit())
1969 printk(KERN_ERR PFX "%s: RX parity error\n", dev->name);
1970 sky2_write32(hw, Q_ADDR(rxqaddr[port], Q_CSR), BMU_CLR_IRQ_PAR);
1973 if (status & Y2_IS_TCP_TXA1) {
1974 if (net_ratelimit())
1975 printk(KERN_ERR PFX "%s: TCP segmentation error\n",
1977 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), BMU_CLR_IRQ_TCP);
1981 static void sky2_hw_intr(struct sky2_hw *hw)
1983 u32 status = sky2_read32(hw, B0_HWE_ISRC);
1985 if (status & Y2_IS_TIST_OV)
1986 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ);
1988 if (status & (Y2_IS_MST_ERR | Y2_IS_IRQ_STAT)) {
1991 pci_read_config_word(hw->pdev, PCI_STATUS, &pci_err);
1992 if (net_ratelimit())
1993 printk(KERN_ERR PFX "%s: pci hw error (0x%x)\n",
1994 pci_name(hw->pdev), pci_err);
1996 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
1997 pci_write_config_word(hw->pdev, PCI_STATUS,
1998 pci_err | PCI_STATUS_ERROR_BITS);
1999 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
2002 if (status & Y2_IS_PCI_EXP) {
2003 /* PCI-Express uncorrectable Error occurred */
2006 pci_read_config_dword(hw->pdev, PEX_UNC_ERR_STAT, &pex_err);
2008 if (net_ratelimit())
2009 printk(KERN_ERR PFX "%s: pci express error (0x%x)\n",
2010 pci_name(hw->pdev), pex_err);
2012 /* clear the interrupt */
2013 sky2_write32(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
2014 pci_write_config_dword(hw->pdev, PEX_UNC_ERR_STAT,
2016 sky2_write32(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
2018 if (pex_err & PEX_FATAL_ERRORS) {
2019 u32 hwmsk = sky2_read32(hw, B0_HWE_IMSK);
2020 hwmsk &= ~Y2_IS_PCI_EXP;
2021 sky2_write32(hw, B0_HWE_IMSK, hwmsk);
2025 if (status & Y2_HWE_L1_MASK)
2026 sky2_hw_error(hw, 0, status);
2028 if (status & Y2_HWE_L1_MASK)
2029 sky2_hw_error(hw, 1, status);
2032 static void sky2_mac_intr(struct sky2_hw *hw, unsigned port)
2034 struct net_device *dev = hw->dev[port];
2035 struct sky2_port *sky2 = netdev_priv(dev);
2036 u8 status = sky2_read8(hw, SK_REG(port, GMAC_IRQ_SRC));
2038 if (netif_msg_intr(sky2))
2039 printk(KERN_INFO PFX "%s: mac interrupt status 0x%x\n",
2042 if (status & GM_IS_RX_FF_OR) {
2043 ++sky2->net_stats.rx_fifo_errors;
2044 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_CLI_RX_FO);
2047 if (status & GM_IS_TX_FF_UR) {
2048 ++sky2->net_stats.tx_fifo_errors;
2049 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_CLI_TX_FU);
2053 static void sky2_phy_intr(struct sky2_hw *hw, unsigned port)
2055 struct net_device *dev = hw->dev[port];
2056 struct sky2_port *sky2 = netdev_priv(dev);
2058 hw->intr_mask &= ~(port == 0 ? Y2_IS_IRQ_PHY1 : Y2_IS_IRQ_PHY2);
2059 sky2_write32(hw, B0_IMSK, hw->intr_mask);
2060 schedule_work(&sky2->phy_task);
2063 static irqreturn_t sky2_intr(int irq, void *dev_id, struct pt_regs *regs)
2065 struct sky2_hw *hw = dev_id;
2066 struct net_device *dev0 = hw->dev[0];
2069 status = sky2_read32(hw, B0_Y2_SP_ISRC2);
2070 if (status == 0 || status == ~0)
2073 if (status & Y2_IS_HW_ERR)
2076 /* Do NAPI for Rx and Tx status */
2077 if (status & Y2_IS_STAT_BMU) {
2078 hw->intr_mask &= ~Y2_IS_STAT_BMU;
2079 sky2_write32(hw, B0_IMSK, hw->intr_mask);
2081 if (likely(__netif_rx_schedule_prep(dev0))) {
2082 prefetch(&hw->st_le[hw->st_idx]);
2083 __netif_rx_schedule(dev0);
2087 if (status & Y2_IS_IRQ_PHY1)
2088 sky2_phy_intr(hw, 0);
2090 if (status & Y2_IS_IRQ_PHY2)
2091 sky2_phy_intr(hw, 1);
2093 if (status & Y2_IS_IRQ_MAC1)
2094 sky2_mac_intr(hw, 0);
2096 if (status & Y2_IS_IRQ_MAC2)
2097 sky2_mac_intr(hw, 1);
2099 sky2_write32(hw, B0_Y2_SP_ICR, 2);
2101 sky2_read32(hw, B0_IMSK);
2106 #ifdef CONFIG_NET_POLL_CONTROLLER
2107 static void sky2_netpoll(struct net_device *dev)
2109 struct sky2_port *sky2 = netdev_priv(dev);
2111 sky2_intr(sky2->hw->pdev->irq, sky2->hw, NULL);
2115 /* Chip internal frequency for clock calculations */
2116 static inline u32 sky2_mhz(const struct sky2_hw *hw)
2118 switch (hw->chip_id) {
2119 case CHIP_ID_YUKON_EC:
2120 case CHIP_ID_YUKON_EC_U:
2121 return 125; /* 125 Mhz */
2122 case CHIP_ID_YUKON_FE:
2123 return 100; /* 100 Mhz */
2124 default: /* YUKON_XL */
2125 return 156; /* 156 Mhz */
2129 static inline u32 sky2_us2clk(const struct sky2_hw *hw, u32 us)
2131 return sky2_mhz(hw) * us;
2134 static inline u32 sky2_clk2us(const struct sky2_hw *hw, u32 clk)
2136 return clk / sky2_mhz(hw);
2140 static int sky2_reset(struct sky2_hw *hw)
2146 sky2_write8(hw, B0_CTST, CS_RST_CLR);
2148 hw->chip_id = sky2_read8(hw, B2_CHIP_ID);
2149 if (hw->chip_id < CHIP_ID_YUKON_XL || hw->chip_id > CHIP_ID_YUKON_FE) {
2150 printk(KERN_ERR PFX "%s: unsupported chip type 0x%x\n",
2151 pci_name(hw->pdev), hw->chip_id);
2156 if (hw->chip_id <= CHIP_ID_YUKON_EC) {
2157 sky2_write8(hw, B28_Y2_ASF_STAT_CMD, Y2_ASF_RESET);
2158 sky2_write16(hw, B0_CTST, Y2_ASF_DISABLE);
2162 sky2_write8(hw, B0_CTST, CS_RST_SET);
2163 sky2_write8(hw, B0_CTST, CS_RST_CLR);
2165 /* clear PCI errors, if any */
2166 err = pci_read_config_word(hw->pdev, PCI_STATUS, &status);
2170 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
2171 err = pci_write_config_word(hw->pdev, PCI_STATUS,
2172 status | PCI_STATUS_ERROR_BITS);
2176 sky2_write8(hw, B0_CTST, CS_MRST_CLR);
2178 /* clear any PEX errors */
2179 if (pci_find_capability(hw->pdev, PCI_CAP_ID_EXP)) {
2180 err = pci_write_config_dword(hw->pdev, PEX_UNC_ERR_STAT,
2186 pmd_type = sky2_read8(hw, B2_PMD_TYP);
2187 hw->copper = !(pmd_type == 'L' || pmd_type == 'S');
2190 t8 = sky2_read8(hw, B2_Y2_HW_RES);
2191 if ((t8 & CFG_DUAL_MAC_MSK) == CFG_DUAL_MAC_MSK) {
2192 if (!(sky2_read8(hw, B2_Y2_CLK_GATE) & Y2_STATUS_LNK2_INAC))
2195 hw->chip_rev = (sky2_read8(hw, B2_MAC_CFG) & CFG_CHIP_R_MSK) >> 4;
2197 sky2_set_power_state(hw, PCI_D0);
2199 for (i = 0; i < hw->ports; i++) {
2200 sky2_write8(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_SET);
2201 sky2_write8(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_CLR);
2204 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
2206 /* Clear I2C IRQ noise */
2207 sky2_write32(hw, B2_I2C_IRQ, 1);
2209 /* turn off hardware timer (unused) */
2210 sky2_write8(hw, B2_TI_CTRL, TIM_STOP);
2211 sky2_write8(hw, B2_TI_CTRL, TIM_CLR_IRQ);
2213 sky2_write8(hw, B0_Y2LED, LED_STAT_ON);
2215 /* Turn off descriptor polling */
2216 sky2_write32(hw, B28_DPT_CTRL, DPT_STOP);
2218 /* Turn off receive timestamp */
2219 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_STOP);
2220 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ);
2222 /* enable the Tx Arbiters */
2223 for (i = 0; i < hw->ports; i++)
2224 sky2_write8(hw, SK_REG(i, TXA_CTRL), TXA_ENA_ARB);
2226 /* Initialize ram interface */
2227 for (i = 0; i < hw->ports; i++) {
2228 sky2_write8(hw, RAM_BUFFER(i, B3_RI_CTRL), RI_RST_CLR);
2230 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_R1), SK_RI_TO_53);
2231 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XA1), SK_RI_TO_53);
2232 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XS1), SK_RI_TO_53);
2233 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_R1), SK_RI_TO_53);
2234 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XA1), SK_RI_TO_53);
2235 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XS1), SK_RI_TO_53);
2236 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_R2), SK_RI_TO_53);
2237 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XA2), SK_RI_TO_53);
2238 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XS2), SK_RI_TO_53);
2239 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_R2), SK_RI_TO_53);
2240 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XA2), SK_RI_TO_53);
2241 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XS2), SK_RI_TO_53);
2244 sky2_write32(hw, B0_HWE_IMSK, Y2_HWE_ALL_MASK);
2246 for (i = 0; i < hw->ports; i++)
2247 sky2_phy_reset(hw, i);
2249 memset(hw->st_le, 0, STATUS_LE_BYTES);
2252 sky2_write32(hw, STAT_CTRL, SC_STAT_RST_SET);
2253 sky2_write32(hw, STAT_CTRL, SC_STAT_RST_CLR);
2255 sky2_write32(hw, STAT_LIST_ADDR_LO, hw->st_dma);
2256 sky2_write32(hw, STAT_LIST_ADDR_HI, (u64) hw->st_dma >> 32);
2258 /* Set the list last index */
2259 sky2_write16(hw, STAT_LAST_IDX, STATUS_RING_SIZE - 1);
2261 /* These status setup values are copied from SysKonnect's driver */
2263 /* WA for dev. #4.3 */
2264 sky2_write16(hw, STAT_TX_IDX_TH, 0xfff); /* Tx Threshold */
2266 /* set Status-FIFO watermark */
2267 sky2_write8(hw, STAT_FIFO_WM, 0x21); /* WA for dev. #4.18 */
2269 /* set Status-FIFO ISR watermark */
2270 sky2_write8(hw, STAT_FIFO_ISR_WM, 0x07); /* WA for dev. #4.18 */
2271 sky2_write32(hw, STAT_TX_TIMER_INI, sky2_us2clk(hw, 10000));
2273 sky2_write16(hw, STAT_TX_IDX_TH, 10);
2274 sky2_write8(hw, STAT_FIFO_WM, 16);
2276 /* set Status-FIFO ISR watermark */
2277 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0)
2278 sky2_write8(hw, STAT_FIFO_ISR_WM, 4);
2280 sky2_write8(hw, STAT_FIFO_ISR_WM, 16);
2282 sky2_write32(hw, STAT_TX_TIMER_INI, sky2_us2clk(hw, 1000));
2283 sky2_write32(hw, STAT_LEV_TIMER_INI, sky2_us2clk(hw, 100));
2284 sky2_write32(hw, STAT_ISR_TIMER_INI, sky2_us2clk(hw, 20));
2287 /* enable status unit */
2288 sky2_write32(hw, STAT_CTRL, SC_STAT_OP_ON);
2290 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_START);
2291 sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_START);
2292 sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_START);
2297 /* This is to catch a BIOS bug workaround where
2298 * mmconfig table doesn't have other buses.
2300 printk(KERN_ERR PFX "%s: can't access PCI config space\n",
2301 pci_name(hw->pdev));
2305 static u32 sky2_supported_modes(const struct sky2_hw *hw)
2309 modes = SUPPORTED_10baseT_Half
2310 | SUPPORTED_10baseT_Full
2311 | SUPPORTED_100baseT_Half
2312 | SUPPORTED_100baseT_Full
2313 | SUPPORTED_Autoneg | SUPPORTED_TP;
2315 if (hw->chip_id != CHIP_ID_YUKON_FE)
2316 modes |= SUPPORTED_1000baseT_Half
2317 | SUPPORTED_1000baseT_Full;
2319 modes = SUPPORTED_1000baseT_Full | SUPPORTED_FIBRE
2320 | SUPPORTED_Autoneg;
2324 static int sky2_get_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
2326 struct sky2_port *sky2 = netdev_priv(dev);
2327 struct sky2_hw *hw = sky2->hw;
2329 ecmd->transceiver = XCVR_INTERNAL;
2330 ecmd->supported = sky2_supported_modes(hw);
2331 ecmd->phy_address = PHY_ADDR_MARV;
2333 ecmd->supported = SUPPORTED_10baseT_Half
2334 | SUPPORTED_10baseT_Full
2335 | SUPPORTED_100baseT_Half
2336 | SUPPORTED_100baseT_Full
2337 | SUPPORTED_1000baseT_Half
2338 | SUPPORTED_1000baseT_Full
2339 | SUPPORTED_Autoneg | SUPPORTED_TP;
2340 ecmd->port = PORT_TP;
2342 ecmd->port = PORT_FIBRE;
2344 ecmd->advertising = sky2->advertising;
2345 ecmd->autoneg = sky2->autoneg;
2346 ecmd->speed = sky2->speed;
2347 ecmd->duplex = sky2->duplex;
2351 static int sky2_set_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
2353 struct sky2_port *sky2 = netdev_priv(dev);
2354 const struct sky2_hw *hw = sky2->hw;
2355 u32 supported = sky2_supported_modes(hw);
2357 if (ecmd->autoneg == AUTONEG_ENABLE) {
2358 ecmd->advertising = supported;
2364 switch (ecmd->speed) {
2366 if (ecmd->duplex == DUPLEX_FULL)
2367 setting = SUPPORTED_1000baseT_Full;
2368 else if (ecmd->duplex == DUPLEX_HALF)
2369 setting = SUPPORTED_1000baseT_Half;
2374 if (ecmd->duplex == DUPLEX_FULL)
2375 setting = SUPPORTED_100baseT_Full;
2376 else if (ecmd->duplex == DUPLEX_HALF)
2377 setting = SUPPORTED_100baseT_Half;
2383 if (ecmd->duplex == DUPLEX_FULL)
2384 setting = SUPPORTED_10baseT_Full;
2385 else if (ecmd->duplex == DUPLEX_HALF)
2386 setting = SUPPORTED_10baseT_Half;
2394 if ((setting & supported) == 0)
2397 sky2->speed = ecmd->speed;
2398 sky2->duplex = ecmd->duplex;
2401 sky2->autoneg = ecmd->autoneg;
2402 sky2->advertising = ecmd->advertising;
2404 if (netif_running(dev))
2405 sky2_phy_reinit(sky2);
2410 static void sky2_get_drvinfo(struct net_device *dev,
2411 struct ethtool_drvinfo *info)
2413 struct sky2_port *sky2 = netdev_priv(dev);
2415 strcpy(info->driver, DRV_NAME);
2416 strcpy(info->version, DRV_VERSION);
2417 strcpy(info->fw_version, "N/A");
2418 strcpy(info->bus_info, pci_name(sky2->hw->pdev));
2421 static const struct sky2_stat {
2422 char name[ETH_GSTRING_LEN];
2425 { "tx_bytes", GM_TXO_OK_HI },
2426 { "rx_bytes", GM_RXO_OK_HI },
2427 { "tx_broadcast", GM_TXF_BC_OK },
2428 { "rx_broadcast", GM_RXF_BC_OK },
2429 { "tx_multicast", GM_TXF_MC_OK },
2430 { "rx_multicast", GM_RXF_MC_OK },
2431 { "tx_unicast", GM_TXF_UC_OK },
2432 { "rx_unicast", GM_RXF_UC_OK },
2433 { "tx_mac_pause", GM_TXF_MPAUSE },
2434 { "rx_mac_pause", GM_RXF_MPAUSE },
2435 { "collisions", GM_TXF_SNG_COL },
2436 { "late_collision",GM_TXF_LAT_COL },
2437 { "aborted", GM_TXF_ABO_COL },
2438 { "multi_collisions", GM_TXF_MUL_COL },
2439 { "fifo_underrun", GM_TXE_FIFO_UR },
2440 { "fifo_overflow", GM_RXE_FIFO_OV },
2441 { "rx_toolong", GM_RXF_LNG_ERR },
2442 { "rx_jabber", GM_RXF_JAB_PKT },
2443 { "rx_runt", GM_RXE_FRAG },
2444 { "rx_too_long", GM_RXF_LNG_ERR },
2445 { "rx_fcs_error", GM_RXF_FCS_ERR },
2448 static u32 sky2_get_rx_csum(struct net_device *dev)
2450 struct sky2_port *sky2 = netdev_priv(dev);
2452 return sky2->rx_csum;
2455 static int sky2_set_rx_csum(struct net_device *dev, u32 data)
2457 struct sky2_port *sky2 = netdev_priv(dev);
2459 sky2->rx_csum = data;
2461 sky2_write32(sky2->hw, Q_ADDR(rxqaddr[sky2->port], Q_CSR),
2462 data ? BMU_ENA_RX_CHKSUM : BMU_DIS_RX_CHKSUM);
2467 static u32 sky2_get_msglevel(struct net_device *netdev)
2469 struct sky2_port *sky2 = netdev_priv(netdev);
2470 return sky2->msg_enable;
2473 static int sky2_nway_reset(struct net_device *dev)
2475 struct sky2_port *sky2 = netdev_priv(dev);
2477 if (sky2->autoneg != AUTONEG_ENABLE)
2480 sky2_phy_reinit(sky2);
2485 static void sky2_phy_stats(struct sky2_port *sky2, u64 * data, unsigned count)
2487 struct sky2_hw *hw = sky2->hw;
2488 unsigned port = sky2->port;
2491 data[0] = (u64) gma_read32(hw, port, GM_TXO_OK_HI) << 32
2492 | (u64) gma_read32(hw, port, GM_TXO_OK_LO);
2493 data[1] = (u64) gma_read32(hw, port, GM_RXO_OK_HI) << 32
2494 | (u64) gma_read32(hw, port, GM_RXO_OK_LO);
2496 for (i = 2; i < count; i++)
2497 data[i] = (u64) gma_read32(hw, port, sky2_stats[i].offset);
2500 static void sky2_set_msglevel(struct net_device *netdev, u32 value)
2502 struct sky2_port *sky2 = netdev_priv(netdev);
2503 sky2->msg_enable = value;
2506 static int sky2_get_stats_count(struct net_device *dev)
2508 return ARRAY_SIZE(sky2_stats);
2511 static void sky2_get_ethtool_stats(struct net_device *dev,
2512 struct ethtool_stats *stats, u64 * data)
2514 struct sky2_port *sky2 = netdev_priv(dev);
2516 sky2_phy_stats(sky2, data, ARRAY_SIZE(sky2_stats));
2519 static void sky2_get_strings(struct net_device *dev, u32 stringset, u8 * data)
2523 switch (stringset) {
2525 for (i = 0; i < ARRAY_SIZE(sky2_stats); i++)
2526 memcpy(data + i * ETH_GSTRING_LEN,
2527 sky2_stats[i].name, ETH_GSTRING_LEN);
2532 /* Use hardware MIB variables for critical path statistics and
2533 * transmit feedback not reported at interrupt.
2534 * Other errors are accounted for in interrupt handler.
2536 static struct net_device_stats *sky2_get_stats(struct net_device *dev)
2538 struct sky2_port *sky2 = netdev_priv(dev);
2541 sky2_phy_stats(sky2, data, ARRAY_SIZE(data));
2543 sky2->net_stats.tx_bytes = data[0];
2544 sky2->net_stats.rx_bytes = data[1];
2545 sky2->net_stats.tx_packets = data[2] + data[4] + data[6];
2546 sky2->net_stats.rx_packets = data[3] + data[5] + data[7];
2547 sky2->net_stats.multicast = data[5] + data[7];
2548 sky2->net_stats.collisions = data[10];
2549 sky2->net_stats.tx_aborted_errors = data[12];
2551 return &sky2->net_stats;
2554 static int sky2_set_mac_address(struct net_device *dev, void *p)
2556 struct sky2_port *sky2 = netdev_priv(dev);
2557 struct sky2_hw *hw = sky2->hw;
2558 unsigned port = sky2->port;
2559 const struct sockaddr *addr = p;
2561 if (!is_valid_ether_addr(addr->sa_data))
2562 return -EADDRNOTAVAIL;
2564 memcpy(dev->dev_addr, addr->sa_data, ETH_ALEN);
2565 memcpy_toio(hw->regs + B2_MAC_1 + port * 8,
2566 dev->dev_addr, ETH_ALEN);
2567 memcpy_toio(hw->regs + B2_MAC_2 + port * 8,
2568 dev->dev_addr, ETH_ALEN);
2570 /* virtual address for data */
2571 gma_set_addr(hw, port, GM_SRC_ADDR_2L, dev->dev_addr);
2573 /* physical address: used for pause frames */
2574 gma_set_addr(hw, port, GM_SRC_ADDR_1L, dev->dev_addr);
2579 static void sky2_set_multicast(struct net_device *dev)
2581 struct sky2_port *sky2 = netdev_priv(dev);
2582 struct sky2_hw *hw = sky2->hw;
2583 unsigned port = sky2->port;
2584 struct dev_mc_list *list = dev->mc_list;
2588 memset(filter, 0, sizeof(filter));
2590 reg = gma_read16(hw, port, GM_RX_CTRL);
2591 reg |= GM_RXCR_UCF_ENA;
2593 if (dev->flags & IFF_PROMISC) /* promiscuous */
2594 reg &= ~(GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA);
2595 else if ((dev->flags & IFF_ALLMULTI) || dev->mc_count > 16) /* all multicast */
2596 memset(filter, 0xff, sizeof(filter));
2597 else if (dev->mc_count == 0) /* no multicast */
2598 reg &= ~GM_RXCR_MCF_ENA;
2601 reg |= GM_RXCR_MCF_ENA;
2603 for (i = 0; list && i < dev->mc_count; i++, list = list->next) {
2604 u32 bit = ether_crc(ETH_ALEN, list->dmi_addr) & 0x3f;
2605 filter[bit / 8] |= 1 << (bit % 8);
2609 gma_write16(hw, port, GM_MC_ADDR_H1,
2610 (u16) filter[0] | ((u16) filter[1] << 8));
2611 gma_write16(hw, port, GM_MC_ADDR_H2,
2612 (u16) filter[2] | ((u16) filter[3] << 8));
2613 gma_write16(hw, port, GM_MC_ADDR_H3,
2614 (u16) filter[4] | ((u16) filter[5] << 8));
2615 gma_write16(hw, port, GM_MC_ADDR_H4,
2616 (u16) filter[6] | ((u16) filter[7] << 8));
2618 gma_write16(hw, port, GM_RX_CTRL, reg);
2621 /* Can have one global because blinking is controlled by
2622 * ethtool and that is always under RTNL mutex
2624 static void sky2_led(struct sky2_hw *hw, unsigned port, int on)
2628 switch (hw->chip_id) {
2629 case CHIP_ID_YUKON_XL:
2630 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
2631 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
2632 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
2633 on ? (PHY_M_LEDC_LOS_CTRL(1) |
2634 PHY_M_LEDC_INIT_CTRL(7) |
2635 PHY_M_LEDC_STA1_CTRL(7) |
2636 PHY_M_LEDC_STA0_CTRL(7))
2639 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
2643 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, 0);
2644 gm_phy_write(hw, port, PHY_MARV_LED_OVER,
2645 on ? PHY_M_LED_MO_DUP(MO_LED_ON) |
2646 PHY_M_LED_MO_10(MO_LED_ON) |
2647 PHY_M_LED_MO_100(MO_LED_ON) |
2648 PHY_M_LED_MO_1000(MO_LED_ON) |
2649 PHY_M_LED_MO_RX(MO_LED_ON)
2650 : PHY_M_LED_MO_DUP(MO_LED_OFF) |
2651 PHY_M_LED_MO_10(MO_LED_OFF) |
2652 PHY_M_LED_MO_100(MO_LED_OFF) |
2653 PHY_M_LED_MO_1000(MO_LED_OFF) |
2654 PHY_M_LED_MO_RX(MO_LED_OFF));
2659 /* blink LED's for finding board */
2660 static int sky2_phys_id(struct net_device *dev, u32 data)
2662 struct sky2_port *sky2 = netdev_priv(dev);
2663 struct sky2_hw *hw = sky2->hw;
2664 unsigned port = sky2->port;
2665 u16 ledctrl, ledover = 0;
2670 if (!data || data > (u32) (MAX_SCHEDULE_TIMEOUT / HZ))
2671 ms = jiffies_to_msecs(MAX_SCHEDULE_TIMEOUT);
2675 /* save initial values */
2676 down(&sky2->phy_sema);
2677 if (hw->chip_id == CHIP_ID_YUKON_XL) {
2678 u16 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
2679 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
2680 ledctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
2681 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
2683 ledctrl = gm_phy_read(hw, port, PHY_MARV_LED_CTRL);
2684 ledover = gm_phy_read(hw, port, PHY_MARV_LED_OVER);
2688 while (!interrupted && ms > 0) {
2689 sky2_led(hw, port, onoff);
2692 up(&sky2->phy_sema);
2693 interrupted = msleep_interruptible(250);
2694 down(&sky2->phy_sema);
2699 /* resume regularly scheduled programming */
2700 if (hw->chip_id == CHIP_ID_YUKON_XL) {
2701 u16 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
2702 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
2703 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ledctrl);
2704 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
2706 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, ledctrl);
2707 gm_phy_write(hw, port, PHY_MARV_LED_OVER, ledover);
2709 up(&sky2->phy_sema);
2714 static void sky2_get_pauseparam(struct net_device *dev,
2715 struct ethtool_pauseparam *ecmd)
2717 struct sky2_port *sky2 = netdev_priv(dev);
2719 ecmd->tx_pause = sky2->tx_pause;
2720 ecmd->rx_pause = sky2->rx_pause;
2721 ecmd->autoneg = sky2->autoneg;
2724 static int sky2_set_pauseparam(struct net_device *dev,
2725 struct ethtool_pauseparam *ecmd)
2727 struct sky2_port *sky2 = netdev_priv(dev);
2730 sky2->autoneg = ecmd->autoneg;
2731 sky2->tx_pause = ecmd->tx_pause != 0;
2732 sky2->rx_pause = ecmd->rx_pause != 0;
2734 sky2_phy_reinit(sky2);
2740 static void sky2_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
2742 struct sky2_port *sky2 = netdev_priv(dev);
2744 wol->supported = WAKE_MAGIC;
2745 wol->wolopts = sky2->wol ? WAKE_MAGIC : 0;
2748 static int sky2_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
2750 struct sky2_port *sky2 = netdev_priv(dev);
2751 struct sky2_hw *hw = sky2->hw;
2753 if (wol->wolopts != WAKE_MAGIC && wol->wolopts != 0)
2756 sky2->wol = wol->wolopts == WAKE_MAGIC;
2759 memcpy_toio(hw->regs + WOL_MAC_ADDR, dev->dev_addr, ETH_ALEN);
2761 sky2_write16(hw, WOL_CTRL_STAT,
2762 WOL_CTL_ENA_PME_ON_MAGIC_PKT |
2763 WOL_CTL_ENA_MAGIC_PKT_UNIT);
2765 sky2_write16(hw, WOL_CTRL_STAT, WOL_CTL_DEFAULT);
2771 static int sky2_get_coalesce(struct net_device *dev,
2772 struct ethtool_coalesce *ecmd)
2774 struct sky2_port *sky2 = netdev_priv(dev);
2775 struct sky2_hw *hw = sky2->hw;
2777 if (sky2_read8(hw, STAT_TX_TIMER_CTRL) == TIM_STOP)
2778 ecmd->tx_coalesce_usecs = 0;
2780 u32 clks = sky2_read32(hw, STAT_TX_TIMER_INI);
2781 ecmd->tx_coalesce_usecs = sky2_clk2us(hw, clks);
2783 ecmd->tx_max_coalesced_frames = sky2_read16(hw, STAT_TX_IDX_TH);
2785 if (sky2_read8(hw, STAT_LEV_TIMER_CTRL) == TIM_STOP)
2786 ecmd->rx_coalesce_usecs = 0;
2788 u32 clks = sky2_read32(hw, STAT_LEV_TIMER_INI);
2789 ecmd->rx_coalesce_usecs = sky2_clk2us(hw, clks);
2791 ecmd->rx_max_coalesced_frames = sky2_read8(hw, STAT_FIFO_WM);
2793 if (sky2_read8(hw, STAT_ISR_TIMER_CTRL) == TIM_STOP)
2794 ecmd->rx_coalesce_usecs_irq = 0;
2796 u32 clks = sky2_read32(hw, STAT_ISR_TIMER_INI);
2797 ecmd->rx_coalesce_usecs_irq = sky2_clk2us(hw, clks);
2800 ecmd->rx_max_coalesced_frames_irq = sky2_read8(hw, STAT_FIFO_ISR_WM);
2805 /* Note: this affect both ports */
2806 static int sky2_set_coalesce(struct net_device *dev,
2807 struct ethtool_coalesce *ecmd)
2809 struct sky2_port *sky2 = netdev_priv(dev);
2810 struct sky2_hw *hw = sky2->hw;
2811 const u32 tmin = sky2_clk2us(hw, 1);
2812 const u32 tmax = 5000;
2814 if (ecmd->tx_coalesce_usecs != 0 &&
2815 (ecmd->tx_coalesce_usecs < tmin || ecmd->tx_coalesce_usecs > tmax))
2818 if (ecmd->rx_coalesce_usecs != 0 &&
2819 (ecmd->rx_coalesce_usecs < tmin || ecmd->rx_coalesce_usecs > tmax))
2822 if (ecmd->rx_coalesce_usecs_irq != 0 &&
2823 (ecmd->rx_coalesce_usecs_irq < tmin || ecmd->rx_coalesce_usecs_irq > tmax))
2826 if (ecmd->tx_max_coalesced_frames > 0xffff)
2828 if (ecmd->rx_max_coalesced_frames > 0xff)
2830 if (ecmd->rx_max_coalesced_frames_irq > 0xff)
2833 if (ecmd->tx_coalesce_usecs == 0)
2834 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_STOP);
2836 sky2_write32(hw, STAT_TX_TIMER_INI,
2837 sky2_us2clk(hw, ecmd->tx_coalesce_usecs));
2838 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_START);
2840 sky2_write16(hw, STAT_TX_IDX_TH, ecmd->tx_max_coalesced_frames);
2842 if (ecmd->rx_coalesce_usecs == 0)
2843 sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_STOP);
2845 sky2_write32(hw, STAT_LEV_TIMER_INI,
2846 sky2_us2clk(hw, ecmd->rx_coalesce_usecs));
2847 sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_START);
2849 sky2_write8(hw, STAT_FIFO_WM, ecmd->rx_max_coalesced_frames);
2851 if (ecmd->rx_coalesce_usecs_irq == 0)
2852 sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_STOP);
2854 sky2_write32(hw, STAT_ISR_TIMER_INI,
2855 sky2_us2clk(hw, ecmd->rx_coalesce_usecs_irq));
2856 sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_START);
2858 sky2_write8(hw, STAT_FIFO_ISR_WM, ecmd->rx_max_coalesced_frames_irq);
2862 static void sky2_get_ringparam(struct net_device *dev,
2863 struct ethtool_ringparam *ering)
2865 struct sky2_port *sky2 = netdev_priv(dev);
2867 ering->rx_max_pending = RX_MAX_PENDING;
2868 ering->rx_mini_max_pending = 0;
2869 ering->rx_jumbo_max_pending = 0;
2870 ering->tx_max_pending = TX_RING_SIZE - 1;
2872 ering->rx_pending = sky2->rx_pending;
2873 ering->rx_mini_pending = 0;
2874 ering->rx_jumbo_pending = 0;
2875 ering->tx_pending = sky2->tx_pending;
2878 static int sky2_set_ringparam(struct net_device *dev,
2879 struct ethtool_ringparam *ering)
2881 struct sky2_port *sky2 = netdev_priv(dev);
2884 if (ering->rx_pending > RX_MAX_PENDING ||
2885 ering->rx_pending < 8 ||
2886 ering->tx_pending < MAX_SKB_TX_LE ||
2887 ering->tx_pending > TX_RING_SIZE - 1)
2890 if (netif_running(dev))
2893 sky2->rx_pending = ering->rx_pending;
2894 sky2->tx_pending = ering->tx_pending;
2896 if (netif_running(dev)) {
2901 sky2_set_multicast(dev);
2907 static int sky2_get_regs_len(struct net_device *dev)
2913 * Returns copy of control register region
2914 * Note: access to the RAM address register set will cause timeouts.
2916 static void sky2_get_regs(struct net_device *dev, struct ethtool_regs *regs,
2919 const struct sky2_port *sky2 = netdev_priv(dev);
2920 const void __iomem *io = sky2->hw->regs;
2922 BUG_ON(regs->len < B3_RI_WTO_R1);
2924 memset(p, 0, regs->len);
2926 memcpy_fromio(p, io, B3_RAM_ADDR);
2928 memcpy_fromio(p + B3_RI_WTO_R1,
2930 regs->len - B3_RI_WTO_R1);
2933 static struct ethtool_ops sky2_ethtool_ops = {
2934 .get_settings = sky2_get_settings,
2935 .set_settings = sky2_set_settings,
2936 .get_drvinfo = sky2_get_drvinfo,
2937 .get_msglevel = sky2_get_msglevel,
2938 .set_msglevel = sky2_set_msglevel,
2939 .nway_reset = sky2_nway_reset,
2940 .get_regs_len = sky2_get_regs_len,
2941 .get_regs = sky2_get_regs,
2942 .get_link = ethtool_op_get_link,
2943 .get_sg = ethtool_op_get_sg,
2944 .set_sg = ethtool_op_set_sg,
2945 .get_tx_csum = ethtool_op_get_tx_csum,
2946 .set_tx_csum = ethtool_op_set_tx_csum,
2947 .get_tso = ethtool_op_get_tso,
2948 .set_tso = ethtool_op_set_tso,
2949 .get_rx_csum = sky2_get_rx_csum,
2950 .set_rx_csum = sky2_set_rx_csum,
2951 .get_strings = sky2_get_strings,
2952 .get_coalesce = sky2_get_coalesce,
2953 .set_coalesce = sky2_set_coalesce,
2954 .get_ringparam = sky2_get_ringparam,
2955 .set_ringparam = sky2_set_ringparam,
2956 .get_pauseparam = sky2_get_pauseparam,
2957 .set_pauseparam = sky2_set_pauseparam,
2959 .get_wol = sky2_get_wol,
2960 .set_wol = sky2_set_wol,
2962 .phys_id = sky2_phys_id,
2963 .get_stats_count = sky2_get_stats_count,
2964 .get_ethtool_stats = sky2_get_ethtool_stats,
2965 .get_perm_addr = ethtool_op_get_perm_addr,
2968 /* Initialize network device */
2969 static __devinit struct net_device *sky2_init_netdev(struct sky2_hw *hw,
2970 unsigned port, int highmem)
2972 struct sky2_port *sky2;
2973 struct net_device *dev = alloc_etherdev(sizeof(*sky2));
2976 printk(KERN_ERR "sky2 etherdev alloc failed");
2980 SET_MODULE_OWNER(dev);
2981 SET_NETDEV_DEV(dev, &hw->pdev->dev);
2982 dev->irq = hw->pdev->irq;
2983 dev->open = sky2_up;
2984 dev->stop = sky2_down;
2985 dev->do_ioctl = sky2_ioctl;
2986 dev->hard_start_xmit = sky2_xmit_frame;
2987 dev->get_stats = sky2_get_stats;
2988 dev->set_multicast_list = sky2_set_multicast;
2989 dev->set_mac_address = sky2_set_mac_address;
2990 dev->change_mtu = sky2_change_mtu;
2991 SET_ETHTOOL_OPS(dev, &sky2_ethtool_ops);
2992 dev->tx_timeout = sky2_tx_timeout;
2993 dev->watchdog_timeo = TX_WATCHDOG;
2995 dev->poll = sky2_poll;
2996 dev->weight = NAPI_WEIGHT;
2997 #ifdef CONFIG_NET_POLL_CONTROLLER
2998 dev->poll_controller = sky2_netpoll;
3001 sky2 = netdev_priv(dev);
3004 sky2->msg_enable = netif_msg_init(debug, default_msg);
3006 spin_lock_init(&sky2->tx_lock);
3007 /* Auto speed and flow control */
3008 sky2->autoneg = AUTONEG_ENABLE;
3013 sky2->advertising = sky2_supported_modes(hw);
3015 /* Receive checksum disabled for Yukon XL
3016 * because of observed problems with incorrect
3017 * values when multiple packets are received in one interrupt
3019 sky2->rx_csum = (hw->chip_id != CHIP_ID_YUKON_XL);
3021 INIT_WORK(&sky2->phy_task, sky2_phy_task, sky2);
3022 init_MUTEX(&sky2->phy_sema);
3023 sky2->tx_pending = TX_DEF_PENDING;
3024 sky2->rx_pending = is_ec_a1(hw) ? 8 : RX_DEF_PENDING;
3025 sky2->rx_bufsize = sky2_buf_size(ETH_DATA_LEN);
3027 hw->dev[port] = dev;
3031 dev->features |= NETIF_F_LLTX;
3032 if (hw->chip_id != CHIP_ID_YUKON_EC_U)
3033 dev->features |= NETIF_F_TSO;
3035 dev->features |= NETIF_F_HIGHDMA;
3036 dev->features |= NETIF_F_IP_CSUM | NETIF_F_SG;
3038 #ifdef SKY2_VLAN_TAG_USED
3039 dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
3040 dev->vlan_rx_register = sky2_vlan_rx_register;
3041 dev->vlan_rx_kill_vid = sky2_vlan_rx_kill_vid;
3044 /* read the mac address */
3045 memcpy_fromio(dev->dev_addr, hw->regs + B2_MAC_1 + port * 8, ETH_ALEN);
3046 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
3048 /* device is off until link detection */
3049 netif_carrier_off(dev);
3050 netif_stop_queue(dev);
3055 static void __devinit sky2_show_addr(struct net_device *dev)
3057 const struct sky2_port *sky2 = netdev_priv(dev);
3059 if (netif_msg_probe(sky2))
3060 printk(KERN_INFO PFX "%s: addr %02x:%02x:%02x:%02x:%02x:%02x\n",
3062 dev->dev_addr[0], dev->dev_addr[1], dev->dev_addr[2],
3063 dev->dev_addr[3], dev->dev_addr[4], dev->dev_addr[5]);
3066 /* Handle software interrupt used during MSI test */
3067 static irqreturn_t __devinit sky2_test_intr(int irq, void *dev_id,
3068 struct pt_regs *regs)
3070 struct sky2_hw *hw = dev_id;
3071 u32 status = sky2_read32(hw, B0_Y2_SP_ISRC2);
3076 if (status & Y2_IS_IRQ_SW) {
3077 sky2_write8(hw, B0_CTST, CS_CL_SW_IRQ);
3080 sky2_write32(hw, B0_Y2_SP_ICR, 2);
3082 sky2_read32(hw, B0_IMSK);
3086 /* Test interrupt path by forcing a a software IRQ */
3087 static int __devinit sky2_test_msi(struct sky2_hw *hw)
3089 struct pci_dev *pdev = hw->pdev;
3092 sky2_write32(hw, B0_IMSK, Y2_IS_IRQ_SW);
3094 err = request_irq(pdev->irq, sky2_test_intr, SA_SHIRQ, DRV_NAME, hw);
3096 printk(KERN_ERR PFX "%s: cannot assign irq %d\n",
3097 pci_name(pdev), pdev->irq);
3101 sky2_write8(hw, B0_CTST, CS_ST_SW_IRQ);
3104 for (i = 0; i < 10; i++) {
3112 sky2_write8(hw, B0_CTST, CS_CL_SW_IRQ);
3114 sky2_write32(hw, B0_IMSK, 0);
3116 free_irq(pdev->irq, hw);
3121 static int __devinit sky2_probe(struct pci_dev *pdev,
3122 const struct pci_device_id *ent)
3124 struct net_device *dev, *dev1 = NULL;
3126 int err, pm_cap, using_dac = 0;
3128 err = pci_enable_device(pdev);
3130 printk(KERN_ERR PFX "%s cannot enable PCI device\n",
3135 err = pci_request_regions(pdev, DRV_NAME);
3137 printk(KERN_ERR PFX "%s cannot obtain PCI resources\n",
3142 pci_set_master(pdev);
3144 /* Find power-management capability. */
3145 pm_cap = pci_find_capability(pdev, PCI_CAP_ID_PM);
3147 printk(KERN_ERR PFX "Cannot find PowerManagement capability, "
3150 goto err_out_free_regions;
3153 if (sizeof(dma_addr_t) > sizeof(u32) &&
3154 !(err = pci_set_dma_mask(pdev, DMA_64BIT_MASK))) {
3156 err = pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK);
3158 printk(KERN_ERR PFX "%s unable to obtain 64 bit DMA "
3159 "for consistent allocations\n", pci_name(pdev));
3160 goto err_out_free_regions;
3164 err = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
3166 printk(KERN_ERR PFX "%s no usable DMA configuration\n",
3168 goto err_out_free_regions;
3173 /* byte swap descriptors in hardware */
3177 pci_read_config_dword(pdev, PCI_DEV_REG2, ®);
3178 reg |= PCI_REV_DESC;
3179 pci_write_config_dword(pdev, PCI_DEV_REG2, reg);
3184 hw = kzalloc(sizeof(*hw), GFP_KERNEL);
3186 printk(KERN_ERR PFX "%s: cannot allocate hardware struct\n",
3188 goto err_out_free_regions;
3193 hw->regs = ioremap_nocache(pci_resource_start(pdev, 0), 0x4000);
3195 printk(KERN_ERR PFX "%s: cannot map device registers\n",
3197 goto err_out_free_hw;
3199 hw->pm_cap = pm_cap;
3201 /* ring for status responses */
3202 hw->st_le = pci_alloc_consistent(hw->pdev, STATUS_LE_BYTES,
3205 goto err_out_iounmap;
3207 err = sky2_reset(hw);
3209 goto err_out_iounmap;
3211 printk(KERN_INFO PFX "v%s addr 0x%lx irq %d Yukon-%s (0x%x) rev %d\n",
3212 DRV_VERSION, pci_resource_start(pdev, 0), pdev->irq,
3213 yukon2_name[hw->chip_id - CHIP_ID_YUKON_XL],
3214 hw->chip_id, hw->chip_rev);
3216 dev = sky2_init_netdev(hw, 0, using_dac);
3218 goto err_out_free_pci;
3220 err = register_netdev(dev);
3222 printk(KERN_ERR PFX "%s: cannot register net device\n",
3224 goto err_out_free_netdev;
3227 sky2_show_addr(dev);
3229 if (hw->ports > 1 && (dev1 = sky2_init_netdev(hw, 1, using_dac))) {
3230 if (register_netdev(dev1) == 0)
3231 sky2_show_addr(dev1);
3233 /* Failure to register second port need not be fatal */
3234 printk(KERN_WARNING PFX
3235 "register of second port failed\n");
3241 if (!disable_msi && pci_enable_msi(pdev) == 0) {
3242 err = sky2_test_msi(hw);
3243 if (err == -EOPNOTSUPP) {
3244 /* MSI test failed, go back to INTx mode */
3245 printk(KERN_WARNING PFX "%s: No interrupt was generated using MSI, "
3246 "switching to INTx mode. Please report this failure to "
3247 "the PCI maintainer and include system chipset information.\n",
3249 pci_disable_msi(pdev);
3252 goto err_out_unregister;
3255 err = request_irq(pdev->irq, sky2_intr, SA_SHIRQ | SA_SAMPLE_RANDOM,
3258 printk(KERN_ERR PFX "%s: cannot assign irq %d\n",
3259 pci_name(pdev), pdev->irq);
3260 goto err_out_unregister;
3263 hw->intr_mask = Y2_IS_BASE;
3264 sky2_write32(hw, B0_IMSK, hw->intr_mask);
3266 pci_set_drvdata(pdev, hw);
3272 pci_disable_msi(pdev);
3274 unregister_netdev(dev1);
3277 unregister_netdev(dev);
3278 err_out_free_netdev:
3281 sky2_write8(hw, B0_CTST, CS_RST_SET);
3282 pci_free_consistent(hw->pdev, STATUS_LE_BYTES, hw->st_le, hw->st_dma);
3287 err_out_free_regions:
3288 pci_release_regions(pdev);
3289 pci_disable_device(pdev);
3294 static void __devexit sky2_remove(struct pci_dev *pdev)
3296 struct sky2_hw *hw = pci_get_drvdata(pdev);
3297 struct net_device *dev0, *dev1;
3305 unregister_netdev(dev1);
3306 unregister_netdev(dev0);
3308 sky2_write32(hw, B0_IMSK, 0);
3309 sky2_set_power_state(hw, PCI_D3hot);
3310 sky2_write16(hw, B0_Y2LED, LED_STAT_OFF);
3311 sky2_write8(hw, B0_CTST, CS_RST_SET);
3312 sky2_read8(hw, B0_CTST);
3314 free_irq(pdev->irq, hw);
3316 pci_disable_msi(pdev);
3317 pci_free_consistent(pdev, STATUS_LE_BYTES, hw->st_le, hw->st_dma);
3318 pci_release_regions(pdev);
3319 pci_disable_device(pdev);
3327 pci_set_drvdata(pdev, NULL);
3331 static int sky2_suspend(struct pci_dev *pdev, pm_message_t state)
3333 struct sky2_hw *hw = pci_get_drvdata(pdev);
3336 for (i = 0; i < 2; i++) {
3337 struct net_device *dev = hw->dev[i];
3340 if (!netif_running(dev))
3344 netif_device_detach(dev);
3348 return sky2_set_power_state(hw, pci_choose_state(pdev, state));
3351 static int sky2_resume(struct pci_dev *pdev)
3353 struct sky2_hw *hw = pci_get_drvdata(pdev);
3356 pci_restore_state(pdev);
3357 pci_enable_wake(pdev, PCI_D0, 0);
3358 err = sky2_set_power_state(hw, PCI_D0);
3362 err = sky2_reset(hw);
3366 for (i = 0; i < 2; i++) {
3367 struct net_device *dev = hw->dev[i];
3368 if (dev && netif_running(dev)) {
3369 netif_device_attach(dev);
3372 printk(KERN_ERR PFX "%s: could not up: %d\n",
3384 static struct pci_driver sky2_driver = {
3386 .id_table = sky2_id_table,
3387 .probe = sky2_probe,
3388 .remove = __devexit_p(sky2_remove),
3390 .suspend = sky2_suspend,
3391 .resume = sky2_resume,
3395 static int __init sky2_init_module(void)
3397 return pci_register_driver(&sky2_driver);
3400 static void __exit sky2_cleanup_module(void)
3402 pci_unregister_driver(&sky2_driver);
3405 module_init(sky2_init_module);
3406 module_exit(sky2_cleanup_module);
3408 MODULE_DESCRIPTION("Marvell Yukon 2 Gigabit Ethernet driver");
3409 MODULE_AUTHOR("Stephen Hemminger <shemminger@osdl.org>");
3410 MODULE_LICENSE("GPL");
3411 MODULE_VERSION(DRV_VERSION);