2 * New driver for Marvell Yukon 2 chipset.
3 * Based on earlier sk98lin, and skge driver.
5 * This driver intentionally does not support all the features
6 * of the original driver such as link fail-over and link management because
7 * those should be done at higher levels.
9 * Copyright (C) 2005 Stephen Hemminger <shemminger@osdl.org>
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License, or
14 * (at your option) any later version.
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
28 * - coalescing setting?
32 * - variable ring size
38 #include <linux/config.h>
39 #include <linux/crc32.h>
40 #include <linux/kernel.h>
41 #include <linux/version.h>
42 #include <linux/module.h>
43 #include <linux/netdevice.h>
44 #include <linux/etherdevice.h>
45 #include <linux/ethtool.h>
46 #include <linux/pci.h>
48 #include <linux/tcp.h>
50 #include <linux/delay.h>
56 #define DRV_NAME "sky2"
57 #define DRV_VERSION "0.5"
58 #define PFX DRV_NAME " "
61 * The Yukon II chipset takes 64 bit command blocks (called list elements)
62 * that are organized into three (receive, transmit, status) different rings
63 * similar to Tigon3. A transmit can require several elements;
64 * a receive requires one (or two if using 64 bit dma).
67 #ifdef CONFIG_SKY2_EC_A1
68 #define is_ec_a1(hw) \
69 ((hw)->chip_id == CHIP_ID_YUKON_EC && \
70 (hw)->chip_rev == CHIP_REV_YU_EC_A1)
72 #define is_ec_a1(hw) 0
75 #define RX_LE_SIZE 256
76 #define RX_LE_BYTES (RX_LE_SIZE*sizeof(struct sky2_rx_le))
77 #define RX_MAX_PENDING (RX_LE_SIZE/2 - 1)
78 #define RX_DEF_PENDING 128
79 #define RX_COPY_THRESHOLD 256
81 #define TX_RING_SIZE 512
82 #define TX_DEF_PENDING (TX_RING_SIZE - 1)
83 #define TX_MIN_PENDING 64
84 #define MAX_SKB_TX_LE (4 + 2*MAX_SKB_FRAGS)
86 #define STATUS_RING_SIZE 2048 /* 2 ports * (TX + 2*RX) */
87 #define STATUS_LE_BYTES (STATUS_RING_SIZE*sizeof(struct sky2_status_le))
88 #define ETH_JUMBO_MTU 9000
89 #define TX_WATCHDOG (5 * HZ)
90 #define NAPI_WEIGHT 64
91 #define PHY_RETRIES 1000
93 static const u32 default_msg =
94 NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_LINK
95 | NETIF_MSG_TIMER | NETIF_MSG_TX_ERR | NETIF_MSG_RX_ERR
96 | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN | NETIF_MSG_INTR;
98 static int debug = -1; /* defaults above */
99 module_param(debug, int, 0);
100 MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
102 static const struct pci_device_id sky2_id_table[] = {
103 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, 0x9000) },
104 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, 0x9E00) },
105 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4b00) },
106 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4b01) },
107 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4340) },
108 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4341) },
109 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4342) },
110 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4343) },
111 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4344) },
112 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4345) },
113 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4346) },
114 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4347) },
115 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4350) },
116 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4351) },
117 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4360) },
118 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4361) },
119 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4362) },
123 MODULE_DEVICE_TABLE(pci, sky2_id_table);
125 /* Avoid conditionals by using array */
126 static const unsigned txqaddr[] = { Q_XA1, Q_XA2 };
127 static const unsigned rxqaddr[] = { Q_R1, Q_R2 };
129 static const char *yukon_name[] = {
130 [CHIP_ID_YUKON_LITE - CHIP_ID_YUKON] = "Lite", /* 0xb0 */
131 [CHIP_ID_YUKON_LP - CHIP_ID_YUKON] = "LP", /* 0xb2 */
132 [CHIP_ID_YUKON_XL - CHIP_ID_YUKON] = "XL", /* 0xb3 */
134 [CHIP_ID_YUKON_EC - CHIP_ID_YUKON] = "EC", /* 0xb6 */
135 [CHIP_ID_YUKON_FE - CHIP_ID_YUKON] = "FE", /* 0xb7 */
139 /* Access to external PHY */
140 static void gm_phy_write(struct sky2_hw *hw, unsigned port, u16 reg, u16 val)
144 gma_write16(hw, port, GM_SMI_DATA, val);
145 gma_write16(hw, port, GM_SMI_CTRL,
146 GM_SMI_CT_PHY_AD(PHY_ADDR_MARV) | GM_SMI_CT_REG_AD(reg));
148 for (i = 0; i < PHY_RETRIES; i++) {
149 if (!(gma_read16(hw, port, GM_SMI_CTRL) & GM_SMI_CT_BUSY))
153 printk(KERN_WARNING PFX "%s: phy write timeout\n", hw->dev[port]->name);
156 static u16 gm_phy_read(struct sky2_hw *hw, unsigned port, u16 reg)
160 gma_write16(hw, port, GM_SMI_CTRL, GM_SMI_CT_PHY_AD(PHY_ADDR_MARV)
161 | GM_SMI_CT_REG_AD(reg) | GM_SMI_CT_OP_RD);
163 for (i = 0; i < PHY_RETRIES; i++) {
164 if (gma_read16(hw, port, GM_SMI_CTRL) & GM_SMI_CT_RD_VAL)
169 printk(KERN_WARNING PFX "%s: phy read timeout\n", hw->dev[port]->name);
171 return gma_read16(hw, port, GM_SMI_DATA);
174 static void sky2_phy_reset(struct sky2_hw *hw, unsigned port)
178 /* disable all GMAC IRQ's */
179 sky2_write8(hw, SK_REG(port, GMAC_IRQ_MSK), 0);
180 /* disable PHY IRQs */
181 gm_phy_write(hw, port, PHY_MARV_INT_MASK, 0);
183 gma_write16(hw, port, GM_MC_ADDR_H1, 0); /* clear MC hash */
184 gma_write16(hw, port, GM_MC_ADDR_H2, 0);
185 gma_write16(hw, port, GM_MC_ADDR_H3, 0);
186 gma_write16(hw, port, GM_MC_ADDR_H4, 0);
188 reg = gma_read16(hw, port, GM_RX_CTRL);
189 reg |= GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA;
190 gma_write16(hw, port, GM_RX_CTRL, reg);
193 static void sky2_phy_init(struct sky2_hw *hw, unsigned port)
195 struct sky2_port *sky2 = netdev_priv(hw->dev[port]);
196 u16 ctrl, ct1000, adv, pg, ledctrl, ledover;
198 if (sky2->autoneg == AUTONEG_ENABLE && hw->chip_id != CHIP_ID_YUKON_XL) {
199 u16 ectrl = gm_phy_read(hw, port, PHY_MARV_EXT_CTRL);
201 ectrl &= ~(PHY_M_EC_M_DSC_MSK | PHY_M_EC_S_DSC_MSK |
203 ectrl |= PHY_M_EC_MAC_S(MAC_TX_CLK_25_MHZ);
205 if (hw->chip_id == CHIP_ID_YUKON_EC)
206 ectrl |= PHY_M_EC_DSC_2(2) | PHY_M_EC_DOWN_S_ENA;
208 ectrl |= PHY_M_EC_M_DSC(2) | PHY_M_EC_S_DSC(3);
210 gm_phy_write(hw, port, PHY_MARV_EXT_CTRL, ectrl);
213 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
215 if (hw->chip_id == CHIP_ID_YUKON_FE) {
216 /* enable automatic crossover */
217 ctrl |= PHY_M_PC_MDI_XMODE(PHY_M_PC_ENA_AUTO) >> 1;
219 /* disable energy detect */
220 ctrl &= ~PHY_M_PC_EN_DET_MSK;
222 /* enable automatic crossover */
223 ctrl |= PHY_M_PC_MDI_XMODE(PHY_M_PC_ENA_AUTO);
225 if (sky2->autoneg == AUTONEG_ENABLE &&
226 hw->chip_id == CHIP_ID_YUKON_XL) {
227 ctrl &= ~PHY_M_PC_DSC_MSK;
228 ctrl |= PHY_M_PC_DSC(2) | PHY_M_PC_DOWN_S_ENA;
231 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
233 /* workaround for deviation #4.88 (CRC errors) */
234 /* disable Automatic Crossover */
236 ctrl &= ~PHY_M_PC_MDIX_MSK;
237 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
239 if (hw->chip_id == CHIP_ID_YUKON_XL) {
240 /* Fiber: select 1000BASE-X only mode MAC Specific Ctrl Reg. */
241 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 2);
242 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
243 ctrl &= ~PHY_M_MAC_MD_MSK;
244 ctrl |= PHY_M_MAC_MODE_SEL(PHY_M_MAC_MD_1000BX);
245 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
247 /* select page 1 to access Fiber registers */
248 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 1);
252 ctrl = gm_phy_read(hw, port, PHY_MARV_CTRL);
253 if (sky2->autoneg == AUTONEG_DISABLE)
258 ctrl |= PHY_CT_RESET;
259 gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
265 if (sky2->autoneg == AUTONEG_ENABLE) {
267 if (sky2->advertising & ADVERTISED_1000baseT_Full)
268 ct1000 |= PHY_M_1000C_AFD;
269 if (sky2->advertising & ADVERTISED_1000baseT_Half)
270 ct1000 |= PHY_M_1000C_AHD;
271 if (sky2->advertising & ADVERTISED_100baseT_Full)
272 adv |= PHY_M_AN_100_FD;
273 if (sky2->advertising & ADVERTISED_100baseT_Half)
274 adv |= PHY_M_AN_100_HD;
275 if (sky2->advertising & ADVERTISED_10baseT_Full)
276 adv |= PHY_M_AN_10_FD;
277 if (sky2->advertising & ADVERTISED_10baseT_Half)
278 adv |= PHY_M_AN_10_HD;
279 } else /* special defines for FIBER (88E1011S only) */
280 adv |= PHY_M_AN_1000X_AHD | PHY_M_AN_1000X_AFD;
282 /* Set Flow-control capabilities */
283 if (sky2->tx_pause && sky2->rx_pause)
284 adv |= PHY_AN_PAUSE_CAP; /* symmetric */
285 else if (sky2->rx_pause && !sky2->tx_pause)
286 adv |= PHY_AN_PAUSE_ASYM | PHY_AN_PAUSE_CAP;
287 else if (!sky2->rx_pause && sky2->tx_pause)
288 adv |= PHY_AN_PAUSE_ASYM; /* local */
290 /* Restart Auto-negotiation */
291 ctrl |= PHY_CT_ANE | PHY_CT_RE_CFG;
293 /* forced speed/duplex settings */
294 ct1000 = PHY_M_1000C_MSE;
296 if (sky2->duplex == DUPLEX_FULL)
297 ctrl |= PHY_CT_DUP_MD;
299 switch (sky2->speed) {
301 ctrl |= PHY_CT_SP1000;
304 ctrl |= PHY_CT_SP100;
308 ctrl |= PHY_CT_RESET;
311 if (hw->chip_id != CHIP_ID_YUKON_FE)
312 gm_phy_write(hw, port, PHY_MARV_1000T_CTRL, ct1000);
314 gm_phy_write(hw, port, PHY_MARV_AUNE_ADV, adv);
315 gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
317 /* Setup Phy LED's */
318 ledctrl = PHY_M_LED_PULS_DUR(PULS_170MS);
321 switch (hw->chip_id) {
322 case CHIP_ID_YUKON_FE:
323 /* on 88E3082 these bits are at 11..9 (shifted left) */
324 ledctrl |= PHY_M_LED_BLINK_RT(BLINK_84MS) << 1;
326 ctrl = gm_phy_read(hw, port, PHY_MARV_FE_LED_PAR);
328 /* delete ACT LED control bits */
329 ctrl &= ~PHY_M_FELP_LED1_MSK;
330 /* change ACT LED control to blink mode */
331 ctrl |= PHY_M_FELP_LED1_CTRL(LED_PAR_CTRL_ACT_BL);
332 gm_phy_write(hw, port, PHY_MARV_FE_LED_PAR, ctrl);
335 case CHIP_ID_YUKON_XL:
336 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
338 /* select page 3 to access LED control register */
339 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
341 /* set LED Function Control register */
342 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, (PHY_M_LEDC_LOS_CTRL(1) | /* LINK/ACT */
343 PHY_M_LEDC_INIT_CTRL(7) | /* 10 Mbps */
344 PHY_M_LEDC_STA1_CTRL(7) | /* 100 Mbps */
345 PHY_M_LEDC_STA0_CTRL(7))); /* 1000 Mbps */
347 /* set Polarity Control register */
348 gm_phy_write(hw, port, PHY_MARV_PHY_STAT,
349 (PHY_M_POLC_LS1_P_MIX(4) |
350 PHY_M_POLC_IS0_P_MIX(4) |
351 PHY_M_POLC_LOS_CTRL(2) |
352 PHY_M_POLC_INIT_CTRL(2) |
353 PHY_M_POLC_STA1_CTRL(2) |
354 PHY_M_POLC_STA0_CTRL(2)));
356 /* restore page register */
357 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
361 /* set Tx LED (LED_TX) to blink mode on Rx OR Tx activity */
362 ledctrl |= PHY_M_LED_BLINK_RT(BLINK_84MS) | PHY_M_LEDC_TX_CTRL;
363 /* turn off the Rx LED (LED_RX) */
364 ledover |= PHY_M_LED_MO_RX(MO_LED_OFF);
367 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, ledctrl);
369 if (sky2->autoneg == AUTONEG_DISABLE || sky2->speed == SPEED_100) {
370 /* turn on 100 Mbps LED (LED_LINK100) */
371 ledover |= PHY_M_LED_MO_100(MO_LED_ON);
375 gm_phy_write(hw, port, PHY_MARV_LED_OVER, ledover);
377 /* Enable phy interrupt on autonegotiation complete (or link up) */
378 if (sky2->autoneg == AUTONEG_ENABLE)
379 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_IS_AN_COMPL);
381 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_DEF_MSK);
384 static void sky2_mac_init(struct sky2_hw *hw, unsigned port)
386 struct sky2_port *sky2 = netdev_priv(hw->dev[port]);
389 const u8 *addr = hw->dev[port]->dev_addr;
391 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET);
392 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_CLR);
394 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_CLR);
396 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0 && port == 1) {
397 /* WA DEV_472 -- looks like crossed wires on port 2 */
398 /* clear GMAC 1 Control reset */
399 sky2_write8(hw, SK_REG(0, GMAC_CTRL), GMC_RST_CLR);
401 sky2_write8(hw, SK_REG(1, GMAC_CTRL), GMC_RST_SET);
402 sky2_write8(hw, SK_REG(1, GMAC_CTRL), GMC_RST_CLR);
403 } while (gm_phy_read(hw, 1, PHY_MARV_ID0) != PHY_MARV_ID0_VAL ||
404 gm_phy_read(hw, 1, PHY_MARV_ID1) != PHY_MARV_ID1_Y2 ||
405 gm_phy_read(hw, 1, PHY_MARV_INT_MASK) != 0);
408 if (sky2->autoneg == AUTONEG_DISABLE) {
409 reg = gma_read16(hw, port, GM_GP_CTRL);
410 reg |= GM_GPCR_AU_ALL_DIS;
411 gma_write16(hw, port, GM_GP_CTRL, reg);
412 gma_read16(hw, port, GM_GP_CTRL);
414 switch (sky2->speed) {
416 reg |= GM_GPCR_SPEED_1000;
419 reg |= GM_GPCR_SPEED_100;
422 if (sky2->duplex == DUPLEX_FULL)
423 reg |= GM_GPCR_DUP_FULL;
425 reg = GM_GPCR_SPEED_1000 | GM_GPCR_SPEED_100 | GM_GPCR_DUP_FULL;
427 if (!sky2->tx_pause && !sky2->rx_pause) {
428 sky2_write32(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
430 GM_GPCR_FC_TX_DIS | GM_GPCR_FC_RX_DIS | GM_GPCR_AU_FCT_DIS;
431 } else if (sky2->tx_pause && !sky2->rx_pause) {
432 /* disable Rx flow-control */
433 reg |= GM_GPCR_FC_RX_DIS | GM_GPCR_AU_FCT_DIS;
436 gma_write16(hw, port, GM_GP_CTRL, reg);
438 sky2_read16(hw, SK_REG(port, GMAC_IRQ_SRC));
440 spin_lock_bh(&hw->phy_lock);
441 sky2_phy_init(hw, port);
442 spin_unlock_bh(&hw->phy_lock);
445 reg = gma_read16(hw, port, GM_PHY_ADDR);
446 gma_write16(hw, port, GM_PHY_ADDR, reg | GM_PAR_MIB_CLR);
448 for (i = 0; i < GM_MIB_CNT_SIZE; i++)
449 gma_read16(hw, port, GM_MIB_CNT_BASE + 8 * i);
450 gma_write16(hw, port, GM_PHY_ADDR, reg);
452 /* transmit control */
453 gma_write16(hw, port, GM_TX_CTRL, TX_COL_THR(TX_COL_DEF));
455 /* receive control reg: unicast + multicast + no FCS */
456 gma_write16(hw, port, GM_RX_CTRL,
457 GM_RXCR_UCF_ENA | GM_RXCR_CRC_DIS | GM_RXCR_MCF_ENA);
459 /* transmit flow control */
460 gma_write16(hw, port, GM_TX_FLOW_CTRL, 0xffff);
462 /* transmit parameter */
463 gma_write16(hw, port, GM_TX_PARAM,
464 TX_JAM_LEN_VAL(TX_JAM_LEN_DEF) |
465 TX_JAM_IPG_VAL(TX_JAM_IPG_DEF) |
466 TX_IPG_JAM_DATA(TX_IPG_JAM_DEF) |
467 TX_BACK_OFF_LIM(TX_BOF_LIM_DEF));
469 /* serial mode register */
470 reg = DATA_BLIND_VAL(DATA_BLIND_DEF) |
471 GM_SMOD_VLAN_ENA | IPG_DATA_VAL(IPG_DATA_DEF);
473 if (hw->dev[port]->mtu > ETH_DATA_LEN)
474 reg |= GM_SMOD_JUMBO_ENA;
476 gma_write16(hw, port, GM_SERIAL_MODE, reg);
478 /* virtual address for data */
479 gma_set_addr(hw, port, GM_SRC_ADDR_2L, addr);
481 /* physical address: used for pause frames */
482 gma_set_addr(hw, port, GM_SRC_ADDR_1L, addr);
484 /* ignore counter overflows */
485 gma_write16(hw, port, GM_TX_IRQ_MSK, 0);
486 gma_write16(hw, port, GM_RX_IRQ_MSK, 0);
487 gma_write16(hw, port, GM_TR_IRQ_MSK, 0);
489 /* Configure Rx MAC FIFO */
490 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_CLR);
491 sky2_write16(hw, SK_REG(port, RX_GMF_CTRL_T),
492 GMF_OPER_ON | GMF_RX_F_FL_ON);
494 /* Flush Rx MAC FIFO on any flowcontrol or error */
495 reg = GMR_FS_ANY_ERR;
496 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev <= 1)
497 reg = 0; /* WA Dev #4115 */
499 sky2_write16(hw, SK_REG(port, RX_GMF_FL_MSK), reg);
500 /* Set threshold to 0xa (64 bytes)
501 * ASF disabled so no need to do WA dev #4.30
503 sky2_write16(hw, SK_REG(port, RX_GMF_FL_THR), RX_GMF_FL_THR_DEF);
505 /* Configure Tx MAC FIFO */
506 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_CLR);
507 sky2_write16(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_OPER_ON);
510 static void sky2_ramset(struct sky2_hw *hw, u16 q, u32 start, size_t len)
516 end = start + len - 1;
518 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_RST_CLR);
519 sky2_write32(hw, RB_ADDR(q, RB_START), start);
520 sky2_write32(hw, RB_ADDR(q, RB_END), end);
521 sky2_write32(hw, RB_ADDR(q, RB_WP), start);
522 sky2_write32(hw, RB_ADDR(q, RB_RP), start);
524 if (q == Q_R1 || q == Q_R2) {
530 /* Set thresholds on receive queue's */
531 sky2_write32(hw, RB_ADDR(q, RB_RX_UTPP), rxup);
532 sky2_write32(hw, RB_ADDR(q, RB_RX_LTPP), rxlo);
534 /* Enable store & forward on Tx queue's because
535 * Tx FIFO is only 1K on Yukon
537 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_STFWD);
540 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_OP_MD);
541 sky2_read8(hw, RB_ADDR(q, RB_CTRL));
544 /* Setup Bus Memory Interface */
545 static void sky2_qset(struct sky2_hw *hw, u16 q, u32 wm)
547 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_CLR_RESET);
548 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_OPER_INIT);
549 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_FIFO_OP_ON);
550 sky2_write32(hw, Q_ADDR(q, Q_WM), wm);
553 /* Setup prefetch unit registers. This is the interface between
554 * hardware and driver list elements
556 static inline void sky2_prefetch_init(struct sky2_hw *hw, u32 qaddr,
559 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_RST_SET);
560 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_RST_CLR);
561 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_ADDR_HI), addr >> 32);
562 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_ADDR_LO), (u32) addr);
563 sky2_write16(hw, Y2_QADDR(qaddr, PREF_UNIT_LAST_IDX), last);
564 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_OP_ON);
566 sky2_read32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL));
569 static inline struct sky2_tx_le *get_tx_le(struct sky2_port *sky2)
571 struct sky2_tx_le *le = sky2->tx_le + sky2->tx_prod;
573 sky2->tx_prod = (sky2->tx_prod + 1) % TX_RING_SIZE;
578 * This is a workaround code taken from syskonnect sk98lin driver
579 * to deal with chip bug on Yukon EC rev 0 in the wraparound case.
581 static inline void sky2_put_idx(struct sky2_hw *hw, unsigned q,
582 u16 idx, u16 *last, u16 size)
584 if (is_ec_a1(hw) && idx < *last) {
585 u16 hwget = sky2_read16(hw, Y2_QADDR(q, PREF_UNIT_GET_IDX));
588 /* Start prefetching again */
589 sky2_write8(hw, Y2_QADDR(q, PREF_UNIT_FIFO_WM), 0xe0);
593 if (hwget == size - 1) {
594 /* set watermark to one list element */
595 sky2_write8(hw, Y2_QADDR(q, PREF_UNIT_FIFO_WM), 8);
597 /* set put index to first list element */
598 sky2_write16(hw, Y2_QADDR(q, PREF_UNIT_PUT_IDX), 0);
599 } else /* have hardware go to end of list */
600 sky2_write16(hw, Y2_QADDR(q, PREF_UNIT_PUT_IDX),
604 sky2_write16(hw, Y2_QADDR(q, PREF_UNIT_PUT_IDX), idx);
606 *last = sky2_read16(hw, Y2_QADDR(q, PREF_UNIT_PUT_IDX));
610 static inline struct sky2_rx_le *sky2_next_rx(struct sky2_port *sky2)
612 struct sky2_rx_le *le = sky2->rx_le + sky2->rx_put;
613 sky2->rx_put = (sky2->rx_put + 1) % RX_LE_SIZE;
617 /* Build description to hardware about buffer */
618 static inline void sky2_rx_add(struct sky2_port *sky2, struct ring_info *re)
620 struct sky2_rx_le *le;
621 u32 hi = (re->mapaddr >> 16) >> 16;
623 re->idx = sky2->rx_put;
624 if (sky2->rx_addr64 != hi) {
625 le = sky2_next_rx(sky2);
626 le->addr = cpu_to_le32(hi);
628 le->opcode = OP_ADDR64 | HW_OWNER;
629 sky2->rx_addr64 = hi;
632 le = sky2_next_rx(sky2);
633 le->addr = cpu_to_le32((u32) re->mapaddr);
634 le->length = cpu_to_le16(re->maplen);
636 le->opcode = OP_PACKET | HW_OWNER;
639 /* Tell receiver about new buffers. */
640 static inline void rx_set_put(struct net_device *dev)
642 struct sky2_port *sky2 = netdev_priv(dev);
644 if (sky2->rx_last_put != sky2->rx_put)
645 sky2_put_idx(sky2->hw, rxqaddr[sky2->port], sky2->rx_put,
646 &sky2->rx_last_put, RX_LE_SIZE);
649 /* Tell chip where to start receive checksum.
650 * Actually has two checksums, but set both same to avoid possible byte
653 static void rx_set_checksum(struct sky2_port *sky2)
655 struct sky2_rx_le *le;
657 le = sky2_next_rx(sky2);
658 le->addr = (ETH_HLEN << 16) | ETH_HLEN;
660 le->opcode = OP_TCPSTART | HW_OWNER;
662 sky2_write32(sky2->hw,
663 Q_ADDR(rxqaddr[sky2->port], Q_CSR),
664 sky2->rx_csum ? BMU_ENA_RX_CHKSUM : BMU_DIS_RX_CHKSUM);
669 * The RX Stop command will not work for Yukon-2 if the BMU does not
670 * reach the end of packet and since we can't make sure that we have
671 * incoming data, we must reset the BMU while it is not doing a DMA
672 * transfer. Since it is possible that the RX path is still active,
673 * the RX RAM buffer will be stopped first, so any possible incoming
674 * data will not trigger a DMA. After the RAM buffer is stopped, the
675 * BMU is polled until any DMA in progress is ended and only then it
678 static void sky2_rx_stop(struct sky2_port *sky2)
680 struct sky2_hw *hw = sky2->hw;
681 unsigned rxq = rxqaddr[sky2->port];
684 /* disable the RAM Buffer receive queue */
685 sky2_write8(hw, RB_ADDR(rxq, RB_CTRL), RB_DIS_OP_MD);
687 for (i = 0; i < 0xffff; i++)
688 if (sky2_read8(hw, RB_ADDR(rxq, Q_RSL))
689 == sky2_read8(hw, RB_ADDR(rxq, Q_RL)))
692 printk(KERN_WARNING PFX "%s: receiver stop failed\n",
695 sky2_write32(hw, Q_ADDR(rxq, Q_CSR), BMU_RST_SET | BMU_FIFO_RST);
697 /* reset the Rx prefetch unit */
698 sky2_write32(hw, Y2_QADDR(rxq, PREF_UNIT_CTRL), PREF_UNIT_RST_SET);
701 /* Cleanout receive buffer area, assumes receiver hardware stopped */
702 static void sky2_rx_clean(struct sky2_port *sky2)
706 memset(sky2->rx_le, 0, RX_LE_BYTES);
707 for (i = 0; i < sky2->rx_pending; i++) {
708 struct ring_info *re = sky2->rx_ring + i;
711 pci_unmap_single(sky2->hw->pdev,
712 re->mapaddr, re->maplen,
720 #define roundup(x, y) ((((x)+((y)-1))/(y))*(y))
721 static inline unsigned rx_size(const struct sky2_port *sky2)
723 return roundup(sky2->netdev->mtu + ETH_HLEN + 4, 8);
727 * Allocate and setup receiver buffer pool.
728 * In case of 64 bit dma, there are 2X as many list elements
729 * available as ring entries
730 * and need to reserve one list element so we don't wrap around.
732 * It appears the hardware has a bug in the FIFO logic that
733 * cause it to hang if the FIFO gets overrun and the receive buffer
734 * is not aligned. This means we can't use skb_reserve to align
737 static int sky2_rx_start(struct sky2_port *sky2)
739 struct sky2_hw *hw = sky2->hw;
740 unsigned size = rx_size(sky2);
741 unsigned rxq = rxqaddr[sky2->port];
744 sky2->rx_put = sky2->rx_next = 0;
745 sky2_qset(hw, rxq, is_pciex(hw) ? 0x80 : 0x600);
746 sky2_prefetch_init(hw, rxq, sky2->rx_le_map, RX_LE_SIZE - 1);
748 rx_set_checksum(sky2);
749 for (i = 0; i < sky2->rx_pending; i++) {
750 struct ring_info *re = sky2->rx_ring + i;
752 re->skb = dev_alloc_skb(size);
756 re->mapaddr = pci_map_single(hw->pdev, re->skb->data,
757 size, PCI_DMA_FROMDEVICE);
759 sky2_rx_add(sky2, re);
762 /* Tell chip about available buffers */
763 sky2_write16(hw, Y2_QADDR(rxq, PREF_UNIT_PUT_IDX), sky2->rx_put);
764 sky2->rx_last_put = sky2_read16(hw, Y2_QADDR(rxq, PREF_UNIT_PUT_IDX));
771 /* Bring up network interface. */
772 static int sky2_up(struct net_device *dev)
774 struct sky2_port *sky2 = netdev_priv(dev);
775 struct sky2_hw *hw = sky2->hw;
776 unsigned port = sky2->port;
777 u32 ramsize, rxspace;
780 if (netif_msg_ifup(sky2))
781 printk(KERN_INFO PFX "%s: enabling interface\n", dev->name);
783 /* must be power of 2 */
784 sky2->tx_le = pci_alloc_consistent(hw->pdev,
786 sizeof(struct sky2_tx_le),
791 sky2->tx_ring = kmalloc(TX_RING_SIZE * sizeof(struct ring_info),
795 sky2->tx_prod = sky2->tx_cons = 0;
796 memset(sky2->tx_ring, 0, TX_RING_SIZE * sizeof(struct ring_info));
798 sky2->rx_le = pci_alloc_consistent(hw->pdev, RX_LE_BYTES,
802 memset(sky2->rx_le, 0, RX_LE_BYTES);
804 sky2->rx_ring = kmalloc(sky2->rx_pending * sizeof(struct ring_info),
809 sky2_mac_init(hw, port);
811 /* Configure RAM buffers */
812 if (hw->chip_id == CHIP_ID_YUKON_FE ||
813 (hw->chip_id == CHIP_ID_YUKON_EC && hw->chip_rev == 2))
816 u8 e0 = sky2_read8(hw, B2_E_0);
817 ramsize = (e0 == 0) ? (128 * 1024) : (e0 * 4096);
821 rxspace = (2 * ramsize) / 3;
822 sky2_ramset(hw, rxqaddr[port], 0, rxspace);
823 sky2_ramset(hw, txqaddr[port], rxspace, ramsize - rxspace);
825 /* Make sure SyncQ is disabled */
826 sky2_write8(hw, RB_ADDR(port == 0 ? Q_XS1 : Q_XS2, RB_CTRL),
829 sky2_qset(hw, txqaddr[port], 0x600);
830 sky2_prefetch_init(hw, txqaddr[port], sky2->tx_le_map,
833 err = sky2_rx_start(sky2);
837 /* Enable interrupts from phy/mac for port */
838 hw->intr_mask |= (port == 0) ? Y2_IS_PORT_1 : Y2_IS_PORT_2;
839 sky2_write32(hw, B0_IMSK, hw->intr_mask);
844 pci_free_consistent(hw->pdev, RX_LE_BYTES,
845 sky2->rx_le, sky2->rx_le_map);
847 pci_free_consistent(hw->pdev,
848 TX_RING_SIZE * sizeof(struct sky2_tx_le),
849 sky2->tx_le, sky2->tx_le_map);
851 kfree(sky2->tx_ring);
853 kfree(sky2->rx_ring);
858 /* Modular subtraction in ring */
859 static inline int tx_dist(unsigned tail, unsigned head)
861 return (head >= tail ? head : head + TX_RING_SIZE) - tail;
864 /* Number of list elements available for next tx */
865 static inline int tx_avail(const struct sky2_port *sky2)
867 return sky2->tx_pending - tx_dist(sky2->tx_cons, sky2->tx_prod);
870 /* Estimate of number of transmit list elements required */
871 static inline unsigned tx_le_req(const struct sk_buff *skb)
875 count = sizeof(dma_addr_t) / sizeof(u32);
876 count += skb_shinfo(skb)->nr_frags * count;
878 if (skb_shinfo(skb)->tso_size)
888 * Put one packet in ring for transmit.
889 * A single packet can generate multiple list elements, and
890 * the number of ring elements will probably be less than the number
891 * of list elements used.
893 static int sky2_xmit_frame(struct sk_buff *skb, struct net_device *dev)
895 struct sky2_port *sky2 = netdev_priv(dev);
896 struct sky2_hw *hw = sky2->hw;
897 struct sky2_tx_le *le;
898 struct ring_info *re;
906 local_irq_save(flags);
907 if (!spin_trylock(&sky2->tx_lock)) {
908 local_irq_restore(flags);
909 return NETDEV_TX_LOCKED;
912 if (unlikely(tx_avail(sky2) < tx_le_req(skb))) {
913 netif_stop_queue(dev);
914 spin_unlock_irqrestore(&sky2->tx_lock, flags);
916 printk(KERN_WARNING PFX "%s: ring full when queue awake!\n",
918 return NETDEV_TX_BUSY;
921 if (unlikely(netif_msg_tx_queued(sky2)))
922 printk(KERN_DEBUG "%s: tx queued, slot %u, len %d\n",
923 dev->name, sky2->tx_prod, skb->len);
925 len = skb_headlen(skb);
926 mapping = pci_map_single(hw->pdev, skb->data, len, PCI_DMA_TODEVICE);
927 addr64 = (mapping >> 16) >> 16;
929 re = sky2->tx_ring + sky2->tx_prod;
931 /* Send high bits if changed */
932 if (addr64 != sky2->tx_addr64) {
933 le = get_tx_le(sky2);
934 le->tx.addr = cpu_to_le32(addr64);
936 le->opcode = OP_ADDR64 | HW_OWNER;
937 sky2->tx_addr64 = addr64;
940 /* Check for TCP Segmentation Offload */
941 mss = skb_shinfo(skb)->tso_size;
943 /* just drop the packet if non-linear expansion fails */
944 if (skb_header_cloned(skb) &&
945 pskb_expand_head(skb, 0, 0, GFP_ATOMIC)) {
946 dev_kfree_skb_any(skb);
950 mss += ((skb->h.th->doff - 5) * 4); /* TCP options */
951 mss += (skb->nh.iph->ihl * 4) + sizeof(struct tcphdr);
955 if (mss != sky2->tx_last_mss) {
956 le = get_tx_le(sky2);
957 le->tx.tso.size = cpu_to_le16(mss);
959 le->opcode = OP_LRGLEN | HW_OWNER;
961 sky2->tx_last_mss = mss;
964 /* Handle TCP checksum offload */
966 if (skb->ip_summed == CHECKSUM_HW) {
967 u16 hdr = skb->h.raw - skb->data;
968 u16 offset = hdr + skb->csum;
970 ctrl = CALSUM | WR_SUM | INIT_SUM | LOCK_SUM;
971 if (skb->nh.iph->protocol == IPPROTO_UDP)
974 le = get_tx_le(sky2);
975 le->tx.csum.start = cpu_to_le16(hdr);
976 le->tx.csum.offset = cpu_to_le16(offset);
977 le->length = 0; /* initial checksum value */
978 le->ctrl = 1; /* one packet */
979 le->opcode = OP_TCPLISW | HW_OWNER;
982 le = get_tx_le(sky2);
983 le->tx.addr = cpu_to_le32((u32) mapping);
984 le->length = cpu_to_le16(len);
986 le->opcode = mss ? (OP_LARGESEND | HW_OWNER) : (OP_PACKET | HW_OWNER);
988 /* Record the transmit mapping info */
990 re->mapaddr = mapping;
993 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
994 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
995 struct ring_info *fre;
997 mapping = pci_map_page(hw->pdev, frag->page, frag->page_offset,
998 frag->size, PCI_DMA_TODEVICE);
999 addr64 = (mapping >> 16) >> 16;
1000 if (addr64 != sky2->tx_addr64) {
1001 le = get_tx_le(sky2);
1002 le->tx.addr = cpu_to_le32(addr64);
1004 le->opcode = OP_ADDR64 | HW_OWNER;
1005 sky2->tx_addr64 = addr64;
1008 le = get_tx_le(sky2);
1009 le->tx.addr = cpu_to_le32((u32) mapping);
1010 le->length = cpu_to_le16(frag->size);
1012 le->opcode = OP_BUFFER | HW_OWNER;
1015 + ((re - sky2->tx_ring) + i + 1) % TX_RING_SIZE;
1017 fre->mapaddr = mapping;
1018 fre->maplen = frag->size;
1020 re->idx = sky2->tx_prod;
1023 sky2_put_idx(sky2->hw, txqaddr[sky2->port], sky2->tx_prod,
1024 &sky2->tx_last_put, TX_RING_SIZE);
1026 if (tx_avail(sky2) < MAX_SKB_TX_LE + 1)
1027 netif_stop_queue(dev);
1031 spin_unlock_irqrestore(&sky2->tx_lock, flags);
1033 dev->trans_start = jiffies;
1034 return NETDEV_TX_OK;
1038 * Free ring elements from starting at tx_cons until "done"
1040 * NB: the hardware will tell us about partial completion of multi-part
1041 * buffers; these are defered until completion.
1043 static void sky2_tx_complete(struct sky2_port *sky2, u16 done)
1045 struct net_device *dev = sky2->netdev;
1048 if (unlikely(netif_msg_tx_done(sky2)))
1049 printk(KERN_DEBUG "%s: tx done, upto %u\n",
1052 spin_lock(&sky2->tx_lock);
1054 while (sky2->tx_cons != done) {
1055 struct ring_info *re = sky2->tx_ring + sky2->tx_cons;
1056 struct sk_buff *skb;
1058 /* Check for partial status */
1059 if (tx_dist(sky2->tx_cons, done)
1060 < tx_dist(sky2->tx_cons, re->idx))
1064 pci_unmap_single(sky2->hw->pdev,
1065 re->mapaddr, re->maplen, PCI_DMA_TODEVICE);
1067 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
1068 struct ring_info *fre;
1070 sky2->tx_ring + (sky2->tx_cons + i +
1072 pci_unmap_page(sky2->hw->pdev, fre->mapaddr,
1073 fre->maplen, PCI_DMA_TODEVICE);
1076 dev_kfree_skb_any(skb);
1078 sky2->tx_cons = re->idx;
1082 if (netif_queue_stopped(dev) && tx_avail(sky2) > MAX_SKB_TX_LE)
1083 netif_wake_queue(dev);
1084 spin_unlock(&sky2->tx_lock);
1087 /* Cleanup all untransmitted buffers, assume transmitter not running */
1088 static inline void sky2_tx_clean(struct sky2_port *sky2)
1090 sky2_tx_complete(sky2, sky2->tx_prod);
1093 /* Network shutdown */
1094 static int sky2_down(struct net_device *dev)
1096 struct sky2_port *sky2 = netdev_priv(dev);
1097 struct sky2_hw *hw = sky2->hw;
1098 unsigned port = sky2->port;
1101 if (netif_msg_ifdown(sky2))
1102 printk(KERN_INFO PFX "%s: disabling interface\n", dev->name);
1104 netif_stop_queue(dev);
1106 sky2_phy_reset(hw, port);
1108 /* Stop transmitter */
1109 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), BMU_STOP);
1110 sky2_read32(hw, Q_ADDR(txqaddr[port], Q_CSR));
1112 sky2_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL),
1113 RB_RST_SET | RB_DIS_OP_MD);
1115 ctrl = gma_read16(hw, port, GM_GP_CTRL);
1116 ctrl &= ~(GM_GPCR_TX_ENA | GM_GPCR_RX_ENA);
1117 gma_write16(hw, port, GM_GP_CTRL, ctrl);
1119 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET);
1121 /* Workaround shared GMAC reset */
1122 if (!(hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0
1123 && port == 0 && hw->dev[1] && netif_running(hw->dev[1])))
1124 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_SET);
1126 /* Disable Force Sync bit and Enable Alloc bit */
1127 sky2_write8(hw, SK_REG(port, TXA_CTRL),
1128 TXA_DIS_FSYNC | TXA_DIS_ALLOC | TXA_STOP_RC);
1130 /* Stop Interval Timer and Limit Counter of Tx Arbiter */
1131 sky2_write32(hw, SK_REG(port, TXA_ITI_INI), 0L);
1132 sky2_write32(hw, SK_REG(port, TXA_LIM_INI), 0L);
1134 /* Reset the PCI FIFO of the async Tx queue */
1135 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR),
1136 BMU_RST_SET | BMU_FIFO_RST);
1138 /* Reset the Tx prefetch units */
1139 sky2_write32(hw, Y2_QADDR(txqaddr[port], PREF_UNIT_CTRL),
1142 sky2_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL), RB_RST_SET);
1146 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_SET);
1147 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_SET);
1149 /* turn off led's */
1150 sky2_write16(hw, B0_Y2LED, LED_STAT_OFF);
1152 sky2_tx_clean(sky2);
1153 sky2_rx_clean(sky2);
1155 pci_free_consistent(hw->pdev, RX_LE_BYTES,
1156 sky2->rx_le, sky2->rx_le_map);
1157 kfree(sky2->rx_ring);
1159 pci_free_consistent(hw->pdev,
1160 TX_RING_SIZE * sizeof(struct sky2_tx_le),
1161 sky2->tx_le, sky2->tx_le_map);
1162 kfree(sky2->tx_ring);
1167 static u16 sky2_phy_speed(const struct sky2_hw *hw, u16 aux)
1172 if (hw->chip_id == CHIP_ID_YUKON_FE)
1173 return (aux & PHY_M_PS_SPEED_100) ? SPEED_100 : SPEED_10;
1175 switch (aux & PHY_M_PS_SPEED_MSK) {
1176 case PHY_M_PS_SPEED_1000:
1178 case PHY_M_PS_SPEED_100:
1185 static void sky2_link_up(struct sky2_port *sky2)
1187 struct sky2_hw *hw = sky2->hw;
1188 unsigned port = sky2->port;
1191 /* disable Rx GMAC FIFO flush mode */
1192 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RX_F_FL_OFF);
1194 /* Enable Transmit FIFO Underrun */
1195 sky2_write8(hw, SK_REG(port, GMAC_IRQ_MSK), GMAC_DEF_MSK);
1197 reg = gma_read16(hw, port, GM_GP_CTRL);
1198 if (sky2->duplex == DUPLEX_FULL || sky2->autoneg == AUTONEG_ENABLE)
1199 reg |= GM_GPCR_DUP_FULL;
1202 reg |= GM_GPCR_RX_ENA | GM_GPCR_TX_ENA;
1203 gma_write16(hw, port, GM_GP_CTRL, reg);
1204 gma_read16(hw, port, GM_GP_CTRL);
1206 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_DEF_MSK);
1208 netif_carrier_on(sky2->netdev);
1209 netif_wake_queue(sky2->netdev);
1211 /* Turn on link LED */
1212 sky2_write8(hw, SK_REG(port, LNK_LED_REG),
1213 LINKLED_ON | LINKLED_BLINK_OFF | LINKLED_LINKSYNC_OFF);
1215 if (hw->chip_id == CHIP_ID_YUKON_XL) {
1216 u16 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
1218 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
1219 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, PHY_M_LEDC_LOS_CTRL(1) | /* LINK/ACT */
1220 PHY_M_LEDC_INIT_CTRL(sky2->speed ==
1222 PHY_M_LEDC_STA1_CTRL(sky2->speed ==
1223 SPEED_100 ? 7 : 0) |
1224 PHY_M_LEDC_STA0_CTRL(sky2->speed ==
1225 SPEED_1000 ? 7 : 0));
1226 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
1229 if (netif_msg_link(sky2))
1230 printk(KERN_INFO PFX
1231 "%s: Link is up at %d Mbps, %s duplex, flowcontrol %s\n",
1232 sky2->netdev->name, sky2->speed,
1233 sky2->duplex == DUPLEX_FULL ? "full" : "half",
1234 (sky2->tx_pause && sky2->rx_pause) ? "both" :
1235 sky2->tx_pause ? "tx" : sky2->rx_pause ? "rx" : "none");
1238 static void sky2_link_down(struct sky2_port *sky2)
1240 struct sky2_hw *hw = sky2->hw;
1241 unsigned port = sky2->port;
1244 gm_phy_write(hw, port, PHY_MARV_INT_MASK, 0);
1246 reg = gma_read16(hw, port, GM_GP_CTRL);
1247 reg &= ~(GM_GPCR_RX_ENA | GM_GPCR_TX_ENA);
1248 gma_write16(hw, port, GM_GP_CTRL, reg);
1249 gma_read16(hw, port, GM_GP_CTRL); /* PCI post */
1251 if (sky2->rx_pause && !sky2->tx_pause) {
1252 /* restore Asymmetric Pause bit */
1253 gm_phy_write(hw, port, PHY_MARV_AUNE_ADV,
1254 gm_phy_read(hw, port, PHY_MARV_AUNE_ADV)
1258 sky2_phy_reset(hw, port);
1260 netif_carrier_off(sky2->netdev);
1261 netif_stop_queue(sky2->netdev);
1263 /* Turn on link LED */
1264 sky2_write8(hw, SK_REG(port, LNK_LED_REG), LINKLED_OFF);
1266 if (netif_msg_link(sky2))
1267 printk(KERN_INFO PFX "%s: Link is down.\n", sky2->netdev->name);
1268 sky2_phy_init(hw, port);
1271 static int sky2_autoneg_done(struct sky2_port *sky2, u16 aux)
1273 struct sky2_hw *hw = sky2->hw;
1274 unsigned port = sky2->port;
1277 lpa = gm_phy_read(hw, port, PHY_MARV_AUNE_LP);
1279 if (lpa & PHY_M_AN_RF) {
1280 printk(KERN_ERR PFX "%s: remote fault", sky2->netdev->name);
1284 if (hw->chip_id != CHIP_ID_YUKON_FE &&
1285 gm_phy_read(hw, port, PHY_MARV_1000T_STAT) & PHY_B_1000S_MSF) {
1286 printk(KERN_ERR PFX "%s: master/slave fault",
1287 sky2->netdev->name);
1291 if (!(aux & PHY_M_PS_SPDUP_RES)) {
1292 printk(KERN_ERR PFX "%s: speed/duplex mismatch",
1293 sky2->netdev->name);
1297 sky2->duplex = (aux & PHY_M_PS_FULL_DUP) ? DUPLEX_FULL : DUPLEX_HALF;
1299 sky2->speed = sky2_phy_speed(hw, aux);
1301 /* Pause bits are offset (9..8) */
1302 if (hw->chip_id == CHIP_ID_YUKON_XL)
1305 sky2->rx_pause = (aux & PHY_M_PS_RX_P_EN) != 0;
1306 sky2->tx_pause = (aux & PHY_M_PS_TX_P_EN) != 0;
1308 if ((sky2->tx_pause || sky2->rx_pause)
1309 && !(sky2->speed < SPEED_1000 && sky2->duplex == DUPLEX_HALF))
1310 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON);
1312 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
1318 * Interrrupt from PHY are handled in tasklet (soft irq)
1319 * because accessing phy registers requires spin wait which might
1320 * cause excess interrupt latency.
1322 static void sky2_phy_task(unsigned long data)
1324 struct sky2_port *sky2 = (struct sky2_port *)data;
1325 struct sky2_hw *hw = sky2->hw;
1326 u16 istatus, phystat;
1328 spin_lock(&hw->phy_lock);
1329 istatus = gm_phy_read(hw, sky2->port, PHY_MARV_INT_STAT);
1330 phystat = gm_phy_read(hw, sky2->port, PHY_MARV_PHY_STAT);
1332 if (netif_msg_intr(sky2))
1333 printk(KERN_INFO PFX "%s: phy interrupt status 0x%x 0x%x\n",
1334 sky2->netdev->name, istatus, phystat);
1336 if (istatus & PHY_M_IS_AN_COMPL) {
1337 if (sky2_autoneg_done(sky2, phystat) == 0)
1342 if (istatus & PHY_M_IS_LSP_CHANGE)
1343 sky2->speed = sky2_phy_speed(hw, phystat);
1345 if (istatus & PHY_M_IS_DUP_CHANGE)
1347 (phystat & PHY_M_PS_FULL_DUP) ? DUPLEX_FULL : DUPLEX_HALF;
1349 if (istatus & PHY_M_IS_LST_CHANGE) {
1350 if (phystat & PHY_M_PS_LINK_UP)
1353 sky2_link_down(sky2);
1356 spin_unlock(&hw->phy_lock);
1358 local_irq_disable();
1359 hw->intr_mask |= (sky2->port == 0) ? Y2_IS_IRQ_PHY1 : Y2_IS_IRQ_PHY2;
1360 sky2_write32(hw, B0_IMSK, hw->intr_mask);
1364 static void sky2_tx_timeout(struct net_device *dev)
1366 struct sky2_port *sky2 = netdev_priv(dev);
1368 if (netif_msg_timer(sky2))
1369 printk(KERN_ERR PFX "%s: tx timeout\n", dev->name);
1371 sky2_write32(sky2->hw, Q_ADDR(txqaddr[sky2->port], Q_CSR), BMU_STOP);
1372 sky2_read32(sky2->hw, Q_ADDR(txqaddr[sky2->port], Q_CSR));
1374 sky2_tx_clean(sky2);
1377 static int sky2_change_mtu(struct net_device *dev, int new_mtu)
1379 struct sky2_port *sky2 = netdev_priv(dev);
1380 struct sky2_hw *hw = sky2->hw;
1384 if (new_mtu < ETH_ZLEN || new_mtu > ETH_JUMBO_MTU)
1387 if (!netif_running(dev)) {
1392 local_irq_disable();
1393 sky2_write32(hw, B0_IMSK, 0);
1395 ctl = gma_read16(hw, sky2->port, GM_GP_CTRL);
1396 gma_write16(hw, sky2->port, GM_GP_CTRL, ctl & ~GM_GPCR_RX_ENA);
1398 sky2_rx_clean(sky2);
1401 mode = DATA_BLIND_VAL(DATA_BLIND_DEF) |
1402 GM_SMOD_VLAN_ENA | IPG_DATA_VAL(IPG_DATA_DEF);
1404 if (dev->mtu > ETH_DATA_LEN)
1405 mode |= GM_SMOD_JUMBO_ENA;
1407 gma_write16(hw, sky2->port, GM_SERIAL_MODE, mode);
1409 sky2_write8(hw, RB_ADDR(rxqaddr[sky2->port], RB_CTRL), RB_ENA_OP_MD);
1411 err = sky2_rx_start(sky2);
1412 gma_write16(hw, sky2->port, GM_GP_CTRL, ctl);
1414 sky2_write32(hw, B0_IMSK, hw->intr_mask);
1415 sky2_read32(hw, B0_IMSK);
1421 * Receive one packet.
1422 * For small packets or errors, just reuse existing skb.
1423 * For larger pakects, get new buffer.
1425 static struct sk_buff *sky2_receive(struct sky2_port *sky2,
1426 u16 length, u32 status)
1428 struct ring_info *re = sky2->rx_ring + sky2->rx_next;
1429 struct sk_buff *skb = NULL;
1430 struct net_device *dev;
1431 const unsigned int bufsize = rx_size(sky2);
1433 if (unlikely(netif_msg_rx_status(sky2)))
1434 printk(KERN_DEBUG PFX "%s: rx slot %u status 0x%x len %d\n",
1435 sky2->netdev->name, sky2->rx_next, status, length);
1437 sky2->rx_next = (sky2->rx_next + 1) % sky2->rx_pending;
1439 if (!(status & GMR_FS_RX_OK)
1440 || (status & GMR_FS_ANY_ERR)
1441 || (length << 16) != (status & GMR_FS_LEN)
1442 || length > bufsize)
1445 if (length < RX_COPY_THRESHOLD) {
1446 skb = alloc_skb(length + 2, GFP_ATOMIC);
1450 skb_reserve(skb, 2);
1451 pci_dma_sync_single_for_cpu(sky2->hw->pdev, re->mapaddr,
1452 length, PCI_DMA_FROMDEVICE);
1453 memcpy(skb->data, re->skb->data, length);
1454 skb->ip_summed = re->skb->ip_summed;
1455 skb->csum = re->skb->csum;
1456 pci_dma_sync_single_for_device(sky2->hw->pdev, re->mapaddr,
1457 length, PCI_DMA_FROMDEVICE);
1459 struct sk_buff *nskb;
1461 nskb = dev_alloc_skb(bufsize);
1467 pci_unmap_single(sky2->hw->pdev, re->mapaddr,
1468 re->maplen, PCI_DMA_FROMDEVICE);
1469 prefetch(skb->data);
1471 re->mapaddr = pci_map_single(sky2->hw->pdev, nskb->data,
1472 bufsize, PCI_DMA_FROMDEVICE);
1473 re->maplen = bufsize;
1476 skb_put(skb, length);
1479 skb->protocol = eth_type_trans(skb, dev);
1480 dev->last_rx = jiffies;
1483 re->skb->ip_summed = CHECKSUM_NONE;
1484 sky2_rx_add(sky2, re);
1489 if (status & GMR_FS_GOOD_FC)
1492 if (netif_msg_rx_err(sky2))
1493 printk(KERN_INFO PFX "%s: rx error, status 0x%x length %d\n",
1494 sky2->netdev->name, status, length);
1496 if (status & (GMR_FS_LONG_ERR | GMR_FS_UN_SIZE))
1497 sky2->net_stats.rx_length_errors++;
1498 if (status & GMR_FS_FRAGMENT)
1499 sky2->net_stats.rx_frame_errors++;
1500 if (status & GMR_FS_CRC_ERR)
1501 sky2->net_stats.rx_crc_errors++;
1502 if (status & GMR_FS_RX_FF_OV)
1503 sky2->net_stats.rx_fifo_errors++;
1508 /* Transmit ring index in reported status block is encoded as:
1510 * | TXS2 | TXA2 | TXS1 | TXA1
1512 static inline u16 tx_index(u8 port, u32 status, u16 len)
1515 return status & 0xfff;
1517 return ((status >> 24) & 0xff) | (len & 0xf) << 8;
1521 * Both ports share the same status interrupt, therefore there is only
1524 static int sky2_poll(struct net_device *dev0, int *budget)
1526 struct sky2_hw *hw = ((struct sky2_port *) netdev_priv(dev0))->hw;
1527 unsigned int to_do = min(dev0->quota, *budget);
1528 unsigned int work_done = 0;
1531 hwidx = sky2_read16(hw, STAT_PUT_IDX);
1532 BUG_ON(hwidx >= STATUS_RING_SIZE);
1534 while (hw->st_idx != hwidx && work_done < to_do) {
1535 struct sky2_status_le *le = hw->st_le + hw->st_idx;
1536 struct sky2_port *sky2;
1537 struct sk_buff *skb;
1541 BUG_ON(le->link >= hw->ports);
1542 sky2 = netdev_priv(hw->dev[le->link]);
1543 status = le32_to_cpu(le->status);
1544 length = le16_to_cpu(le->length);
1546 switch (le->opcode & ~HW_OWNER) {
1548 skb = sky2_receive(sky2, length, status);
1550 netif_receive_skb(skb);
1556 skb = sky2->rx_ring[sky2->rx_next].skb;
1557 skb->ip_summed = CHECKSUM_HW;
1558 skb->csum = le16_to_cpu(status);
1562 sky2_tx_complete(sky2,
1563 tx_index(sky2->port, status, length));
1566 case OP_RXTIMESTAMP:
1570 if (net_ratelimit())
1571 printk(KERN_WARNING PFX
1572 "unknown status opcode 0x%x\n",
1577 hw->st_idx = (hw->st_idx + 1) % STATUS_RING_SIZE;
1578 if (hw->st_idx == hwidx) {
1579 hwidx = sky2_read16(hw, STAT_PUT_IDX);
1587 rx_set_put(hw->dev[0]);
1590 rx_set_put(hw->dev[1]);
1592 *budget -= work_done;
1593 dev0->quota -= work_done;
1594 if (work_done < to_do) {
1596 * Another chip workaround, need to restart TX timer if status
1597 * LE was handled. WA_DEV_43_418
1600 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_STOP);
1601 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_START);
1604 hw->intr_mask |= Y2_IS_STAT_BMU;
1605 sky2_write32(hw, B0_IMSK, hw->intr_mask);
1606 sky2_read32(hw, B0_IMSK);
1607 netif_rx_complete(dev0);
1610 return work_done >= to_do;
1614 static void sky2_hw_error(struct sky2_hw *hw, unsigned port, u32 status)
1616 struct net_device *dev = hw->dev[port];
1618 printk(KERN_INFO PFX "%s: hw error interrupt status 0x%x\n",
1621 if (status & Y2_IS_PAR_RD1) {
1622 printk(KERN_ERR PFX "%s: ram data read parity error\n",
1625 sky2_write16(hw, RAM_BUFFER(port, B3_RI_CTRL), RI_CLR_RD_PERR);
1628 if (status & Y2_IS_PAR_WR1) {
1629 printk(KERN_ERR PFX "%s: ram data write parity error\n",
1632 sky2_write16(hw, RAM_BUFFER(port, B3_RI_CTRL), RI_CLR_WR_PERR);
1635 if (status & Y2_IS_PAR_MAC1) {
1636 printk(KERN_ERR PFX "%s: MAC parity error\n", dev->name);
1637 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_CLI_TX_PE);
1640 if (status & Y2_IS_PAR_RX1) {
1641 printk(KERN_ERR PFX "%s: RX parity error\n", dev->name);
1642 sky2_write32(hw, Q_ADDR(rxqaddr[port], Q_CSR), BMU_CLR_IRQ_PAR);
1645 if (status & Y2_IS_TCP_TXA1) {
1646 printk(KERN_ERR PFX "%s: TCP segmentation error\n", dev->name);
1647 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), BMU_CLR_IRQ_TCP);
1651 static void sky2_hw_intr(struct sky2_hw *hw)
1653 u32 status = sky2_read32(hw, B0_HWE_ISRC);
1655 if (status & Y2_IS_TIST_OV)
1656 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ);
1658 if (status & (Y2_IS_MST_ERR | Y2_IS_IRQ_STAT)) {
1661 pci_read_config_word(hw->pdev, PCI_STATUS, &pci_err);
1662 printk(KERN_ERR PFX "%s: pci hw error (0x%x)\n",
1663 pci_name(hw->pdev), pci_err);
1665 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
1666 pci_write_config_word(hw->pdev, PCI_STATUS,
1667 pci_err | PCI_STATUS_ERROR_BITS);
1668 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
1671 if (status & Y2_IS_PCI_EXP) {
1672 /* PCI-Express uncorrectable Error occured */
1675 pci_read_config_dword(hw->pdev, PEX_UNC_ERR_STAT, &pex_err);
1677 printk(KERN_ERR PFX "%s: pci express error (0x%x)\n",
1678 pci_name(hw->pdev), pex_err);
1680 /* clear the interrupt */
1681 sky2_write32(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
1682 pci_write_config_dword(hw->pdev, PEX_UNC_ERR_STAT,
1684 sky2_write32(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
1686 if (pex_err & PEX_FATAL_ERRORS) {
1687 u32 hwmsk = sky2_read32(hw, B0_HWE_IMSK);
1688 hwmsk &= ~Y2_IS_PCI_EXP;
1689 sky2_write32(hw, B0_HWE_IMSK, hwmsk);
1693 if (status & Y2_HWE_L1_MASK)
1694 sky2_hw_error(hw, 0, status);
1696 if (status & Y2_HWE_L1_MASK)
1697 sky2_hw_error(hw, 1, status);
1700 static void sky2_mac_intr(struct sky2_hw *hw, unsigned port)
1702 struct net_device *dev = hw->dev[port];
1703 struct sky2_port *sky2 = netdev_priv(dev);
1704 u8 status = sky2_read8(hw, SK_REG(port, GMAC_IRQ_SRC));
1706 if (netif_msg_intr(sky2))
1707 printk(KERN_INFO PFX "%s: mac interrupt status 0x%x\n",
1710 if (status & GM_IS_RX_FF_OR) {
1711 ++sky2->net_stats.rx_fifo_errors;
1712 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_CLI_RX_FO);
1715 if (status & GM_IS_TX_FF_UR) {
1716 ++sky2->net_stats.tx_fifo_errors;
1717 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_CLI_TX_FU);
1721 static void sky2_phy_intr(struct sky2_hw *hw, unsigned port)
1723 struct net_device *dev = hw->dev[port];
1724 struct sky2_port *sky2 = netdev_priv(dev);
1726 hw->intr_mask &= ~(port == 0 ? Y2_IS_IRQ_PHY1 : Y2_IS_IRQ_PHY2);
1727 sky2_write32(hw, B0_IMSK, hw->intr_mask);
1728 tasklet_schedule(&sky2->phy_task);
1731 static irqreturn_t sky2_intr(int irq, void *dev_id, struct pt_regs *regs)
1733 struct sky2_hw *hw = dev_id;
1736 status = sky2_read32(hw, B0_Y2_SP_ISRC2);
1737 if (status == 0 || status == ~0)
1740 if (status & Y2_IS_HW_ERR)
1743 /* Do NAPI for Rx and Tx status */
1744 if ((status & Y2_IS_STAT_BMU) && netif_rx_schedule_test(hw->dev[0])) {
1745 sky2_write32(hw, STAT_CTRL, SC_STAT_CLR_IRQ);
1747 hw->intr_mask &= ~Y2_IS_STAT_BMU;
1748 sky2_write32(hw, B0_IMSK, hw->intr_mask);
1749 __netif_rx_schedule(hw->dev[0]);
1752 if (status & Y2_IS_IRQ_PHY1)
1753 sky2_phy_intr(hw, 0);
1755 if (status & Y2_IS_IRQ_PHY2)
1756 sky2_phy_intr(hw, 1);
1758 if (status & Y2_IS_IRQ_MAC1)
1759 sky2_mac_intr(hw, 0);
1761 if (status & Y2_IS_IRQ_MAC2)
1762 sky2_mac_intr(hw, 1);
1764 sky2_write32(hw, B0_Y2_SP_ICR, 2);
1766 sky2_read32(hw, B0_IMSK);
1771 #ifdef CONFIG_NET_POLL_CONTROLLER
1772 static void sky2_netpoll(struct net_device *dev)
1774 struct sky2_port *sky2 = netdev_priv(dev);
1776 sky2_intr(sky2->hw->pdev->irq, sky2->hw, NULL);
1780 /* Chip internal frequency for clock calculations */
1781 static inline u32 sky2_khz(const struct sky2_hw *hw)
1783 switch (hw->chip_id) {
1784 case CHIP_ID_YUKON_EC:
1785 return 125000; /* 125 Mhz */
1786 case CHIP_ID_YUKON_FE:
1787 return 100000; /* 100 Mhz */
1788 default: /* YUKON_XL */
1789 return 156000; /* 156 Mhz */
1793 static inline u32 sky2_ms2clk(const struct sky2_hw *hw, u32 ms)
1795 return sky2_khz(hw) * ms;
1798 static inline u32 sky2_us2clk(const struct sky2_hw *hw, u32 us)
1800 return (sky2_khz(hw) * us) / 1000;
1803 static int sky2_reset(struct sky2_hw *hw)
1810 ctst = sky2_read32(hw, B0_CTST);
1812 sky2_write8(hw, B0_CTST, CS_RST_CLR);
1813 hw->chip_id = sky2_read8(hw, B2_CHIP_ID);
1814 if (hw->chip_id < CHIP_ID_YUKON_XL || hw->chip_id > CHIP_ID_YUKON_FE) {
1815 printk(KERN_ERR PFX "%s: unsupported chip type 0x%x\n",
1816 pci_name(hw->pdev), hw->chip_id);
1820 /* ring for status responses */
1821 hw->st_le = pci_alloc_consistent(hw->pdev, STATUS_LE_BYTES,
1827 if (hw->chip_id <= CHIP_ID_YUKON_EC) {
1828 sky2_write8(hw, B28_Y2_ASF_STAT_CMD, Y2_ASF_RESET);
1829 sky2_write16(hw, B0_CTST, Y2_ASF_DISABLE);
1833 sky2_write8(hw, B0_CTST, CS_RST_SET);
1834 sky2_write8(hw, B0_CTST, CS_RST_CLR);
1836 /* clear PCI errors, if any */
1837 pci_read_config_word(hw->pdev, PCI_STATUS, &status);
1838 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
1839 pci_write_config_word(hw->pdev, PCI_STATUS,
1840 status | PCI_STATUS_ERROR_BITS);
1842 sky2_write8(hw, B0_CTST, CS_MRST_CLR);
1844 /* clear any PEX errors */
1847 pci_write_config_dword(hw->pdev, PEX_UNC_ERR_STAT,
1849 pci_read_config_word(hw->pdev, PEX_LNK_STAT, &lstat);
1852 pmd_type = sky2_read8(hw, B2_PMD_TYP);
1853 hw->copper = !(pmd_type == 'L' || pmd_type == 'S');
1856 t8 = sky2_read8(hw, B2_Y2_HW_RES);
1857 if ((t8 & CFG_DUAL_MAC_MSK) == CFG_DUAL_MAC_MSK) {
1858 if (!(sky2_read8(hw, B2_Y2_CLK_GATE) & Y2_STATUS_LNK2_INAC))
1861 hw->chip_rev = (sky2_read8(hw, B2_MAC_CFG) & CFG_CHIP_R_MSK) >> 4;
1863 /* switch power to VCC (WA for VAUX problem) */
1864 sky2_write8(hw, B0_POWER_CTRL,
1865 PC_VAUX_ENA | PC_VCC_ENA | PC_VAUX_OFF | PC_VCC_ON);
1867 /* disable Core Clock Division, */
1868 sky2_write32(hw, B2_Y2_CLK_CTRL, Y2_CLK_DIV_DIS);
1870 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1)
1871 /* enable bits are inverted */
1872 sky2_write8(hw, B2_Y2_CLK_GATE,
1873 Y2_PCI_CLK_LNK1_DIS | Y2_COR_CLK_LNK1_DIS |
1874 Y2_CLK_GAT_LNK1_DIS | Y2_PCI_CLK_LNK2_DIS |
1875 Y2_COR_CLK_LNK2_DIS | Y2_CLK_GAT_LNK2_DIS);
1877 sky2_write8(hw, B2_Y2_CLK_GATE, 0);
1879 /* Turn off phy power saving */
1880 pci_read_config_dword(hw->pdev, PCI_DEV_REG1, &power);
1881 power &= ~(PCI_Y2_PHY1_POWD | PCI_Y2_PHY2_POWD);
1883 /* looks like this xl is back asswards .. */
1884 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1) {
1885 power |= PCI_Y2_PHY1_COMA;
1887 power |= PCI_Y2_PHY2_COMA;
1889 pci_write_config_dword(hw->pdev, PCI_DEV_REG1, power);
1891 for (i = 0; i < hw->ports; i++) {
1892 sky2_write8(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_SET);
1893 sky2_write8(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_CLR);
1896 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
1898 /* Clear I2C IRQ noise */
1899 sky2_write32(hw, B2_I2C_IRQ, 1);
1901 /* turn off hardware timer (unused) */
1902 sky2_write8(hw, B2_TI_CTRL, TIM_STOP);
1903 sky2_write8(hw, B2_TI_CTRL, TIM_CLR_IRQ);
1905 sky2_write8(hw, B0_Y2LED, LED_STAT_ON);
1907 /* Turn on descriptor polling (every 75us) */
1908 sky2_write32(hw, B28_DPT_INI, sky2_us2clk(hw, 75));
1909 sky2_write8(hw, B28_DPT_CTRL, DPT_START);
1911 /* Turn off receive timestamp */
1912 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_STOP);
1913 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ);
1915 /* enable the Tx Arbiters */
1916 for (i = 0; i < hw->ports; i++)
1917 sky2_write8(hw, SK_REG(i, TXA_CTRL), TXA_ENA_ARB);
1919 /* Initialize ram interface */
1920 for (i = 0; i < hw->ports; i++) {
1921 sky2_write8(hw, RAM_BUFFER(i, B3_RI_CTRL), RI_RST_CLR);
1923 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_R1), SK_RI_TO_53);
1924 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XA1), SK_RI_TO_53);
1925 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XS1), SK_RI_TO_53);
1926 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_R1), SK_RI_TO_53);
1927 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XA1), SK_RI_TO_53);
1928 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XS1), SK_RI_TO_53);
1929 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_R2), SK_RI_TO_53);
1930 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XA2), SK_RI_TO_53);
1931 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XS2), SK_RI_TO_53);
1932 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_R2), SK_RI_TO_53);
1933 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XA2), SK_RI_TO_53);
1934 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XS2), SK_RI_TO_53);
1940 /* change Max. Read Request Size to 2048 bytes */
1941 pci_read_config_word(hw->pdev, PEX_DEV_CTRL, &pctrl);
1942 pctrl &= ~PEX_DC_MAX_RRS_MSK;
1943 pctrl |= PEX_DC_MAX_RD_RQ_SIZE(4);
1946 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
1947 pci_write_config_word(hw->pdev, PEX_DEV_CTRL, pctrl);
1948 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
1951 sky2_write32(hw, B0_HWE_IMSK, Y2_HWE_ALL_MASK);
1953 spin_lock_bh(&hw->phy_lock);
1954 for (i = 0; i < hw->ports; i++)
1955 sky2_phy_reset(hw, i);
1956 spin_unlock_bh(&hw->phy_lock);
1958 memset(hw->st_le, 0, STATUS_LE_BYTES);
1961 sky2_write32(hw, STAT_CTRL, SC_STAT_RST_SET);
1962 sky2_write32(hw, STAT_CTRL, SC_STAT_RST_CLR);
1964 sky2_write32(hw, STAT_LIST_ADDR_LO, hw->st_dma);
1965 sky2_write32(hw, STAT_LIST_ADDR_HI, (u64) hw->st_dma >> 32);
1967 /* Set the list last index */
1968 sky2_write16(hw, STAT_LAST_IDX, STATUS_RING_SIZE - 1);
1970 sky2_write32(hw, STAT_TX_TIMER_INI, sky2_ms2clk(hw, 10));
1972 /* These status setup values are copied from SysKonnect's driver */
1974 /* WA for dev. #4.3 */
1975 sky2_write16(hw, STAT_TX_IDX_TH, 0xfff); /* Tx Threshold */
1977 /* set Status-FIFO watermark */
1978 sky2_write8(hw, STAT_FIFO_WM, 0x21); /* WA for dev. #4.18 */
1980 /* set Status-FIFO ISR watermark */
1981 sky2_write8(hw, STAT_FIFO_ISR_WM, 0x07); /* WA for dev. #4.18 */
1984 sky2_write16(hw, STAT_TX_IDX_TH, 0x000a);
1986 /* set Status-FIFO watermark */
1987 sky2_write8(hw, STAT_FIFO_WM, 0x10);
1989 /* set Status-FIFO ISR watermark */
1990 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0)
1991 sky2_write8(hw, STAT_FIFO_ISR_WM, 0x10);
1994 sky2_write8(hw, STAT_FIFO_ISR_WM, 0x04);
1996 sky2_write32(hw, STAT_ISR_TIMER_INI, 0x0190);
1999 /* enable status unit */
2000 sky2_write32(hw, STAT_CTRL, SC_STAT_OP_ON);
2002 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_START);
2003 sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_START);
2004 sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_START);
2009 static inline u32 sky2_supported_modes(const struct sky2_hw *hw)
2013 modes = SUPPORTED_10baseT_Half
2014 | SUPPORTED_10baseT_Full
2015 | SUPPORTED_100baseT_Half
2016 | SUPPORTED_100baseT_Full
2017 | SUPPORTED_Autoneg | SUPPORTED_TP;
2019 if (hw->chip_id != CHIP_ID_YUKON_FE)
2020 modes |= SUPPORTED_1000baseT_Half
2021 | SUPPORTED_1000baseT_Full;
2023 modes = SUPPORTED_1000baseT_Full | SUPPORTED_FIBRE
2024 | SUPPORTED_Autoneg;
2028 static int sky2_get_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
2030 struct sky2_port *sky2 = netdev_priv(dev);
2031 struct sky2_hw *hw = sky2->hw;
2033 ecmd->transceiver = XCVR_INTERNAL;
2034 ecmd->supported = sky2_supported_modes(hw);
2035 ecmd->phy_address = PHY_ADDR_MARV;
2037 ecmd->supported = SUPPORTED_10baseT_Half
2038 | SUPPORTED_10baseT_Full
2039 | SUPPORTED_100baseT_Half
2040 | SUPPORTED_100baseT_Full
2041 | SUPPORTED_1000baseT_Half
2042 | SUPPORTED_1000baseT_Full
2043 | SUPPORTED_Autoneg | SUPPORTED_TP;
2044 ecmd->port = PORT_TP;
2046 ecmd->port = PORT_FIBRE;
2048 ecmd->advertising = sky2->advertising;
2049 ecmd->autoneg = sky2->autoneg;
2050 ecmd->speed = sky2->speed;
2051 ecmd->duplex = sky2->duplex;
2055 static int sky2_set_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
2057 struct sky2_port *sky2 = netdev_priv(dev);
2058 const struct sky2_hw *hw = sky2->hw;
2059 u32 supported = sky2_supported_modes(hw);
2061 if (ecmd->autoneg == AUTONEG_ENABLE) {
2062 ecmd->advertising = supported;
2068 switch (ecmd->speed) {
2070 if (ecmd->duplex == DUPLEX_FULL)
2071 setting = SUPPORTED_1000baseT_Full;
2072 else if (ecmd->duplex == DUPLEX_HALF)
2073 setting = SUPPORTED_1000baseT_Half;
2078 if (ecmd->duplex == DUPLEX_FULL)
2079 setting = SUPPORTED_100baseT_Full;
2080 else if (ecmd->duplex == DUPLEX_HALF)
2081 setting = SUPPORTED_100baseT_Half;
2087 if (ecmd->duplex == DUPLEX_FULL)
2088 setting = SUPPORTED_10baseT_Full;
2089 else if (ecmd->duplex == DUPLEX_HALF)
2090 setting = SUPPORTED_10baseT_Half;
2098 if ((setting & supported) == 0)
2101 sky2->speed = ecmd->speed;
2102 sky2->duplex = ecmd->duplex;
2105 sky2->autoneg = ecmd->autoneg;
2106 sky2->advertising = ecmd->advertising;
2108 if (netif_running(dev)) {
2116 static void sky2_get_drvinfo(struct net_device *dev,
2117 struct ethtool_drvinfo *info)
2119 struct sky2_port *sky2 = netdev_priv(dev);
2121 strcpy(info->driver, DRV_NAME);
2122 strcpy(info->version, DRV_VERSION);
2123 strcpy(info->fw_version, "N/A");
2124 strcpy(info->bus_info, pci_name(sky2->hw->pdev));
2127 static const struct sky2_stat {
2128 char name[ETH_GSTRING_LEN];
2131 { "tx_bytes", GM_TXO_OK_HI },
2132 { "rx_bytes", GM_RXO_OK_HI },
2133 { "tx_broadcast", GM_TXF_BC_OK },
2134 { "rx_broadcast", GM_RXF_BC_OK },
2135 { "tx_multicast", GM_TXF_MC_OK },
2136 { "rx_multicast", GM_RXF_MC_OK },
2137 { "tx_unicast", GM_TXF_UC_OK },
2138 { "rx_unicast", GM_RXF_UC_OK },
2139 { "tx_mac_pause", GM_TXF_MPAUSE },
2140 { "rx_mac_pause", GM_RXF_MPAUSE },
2141 { "collisions", GM_TXF_SNG_COL },
2142 { "late_collision",GM_TXF_LAT_COL },
2143 { "aborted", GM_TXF_ABO_COL },
2144 { "multi_collisions", GM_TXF_MUL_COL },
2145 { "fifo_underrun", GM_TXE_FIFO_UR },
2146 { "fifo_overflow", GM_RXE_FIFO_OV },
2147 { "rx_toolong", GM_RXF_LNG_ERR },
2148 { "rx_jabber", GM_RXF_JAB_PKT },
2149 { "rx_runt", GM_RXE_FRAG },
2150 { "rx_too_long", GM_RXF_LNG_ERR },
2151 { "rx_fcs_error", GM_RXF_FCS_ERR },
2154 static u32 sky2_get_rx_csum(struct net_device *dev)
2156 struct sky2_port *sky2 = netdev_priv(dev);
2158 return sky2->rx_csum;
2161 static int sky2_set_rx_csum(struct net_device *dev, u32 data)
2163 struct sky2_port *sky2 = netdev_priv(dev);
2165 sky2->rx_csum = data;
2167 sky2_write32(sky2->hw, Q_ADDR(rxqaddr[sky2->port], Q_CSR),
2168 data ? BMU_ENA_RX_CHKSUM : BMU_DIS_RX_CHKSUM);
2173 static u32 sky2_get_msglevel(struct net_device *netdev)
2175 struct sky2_port *sky2 = netdev_priv(netdev);
2176 return sky2->msg_enable;
2179 static void sky2_phy_stats(struct sky2_port *sky2, u64 * data, unsigned count)
2181 struct sky2_hw *hw = sky2->hw;
2182 unsigned port = sky2->port;
2185 data[0] = (u64) gma_read32(hw, port, GM_TXO_OK_HI) << 32
2186 | (u64) gma_read32(hw, port, GM_TXO_OK_LO);
2187 data[1] = (u64) gma_read32(hw, port, GM_RXO_OK_HI) << 32
2188 | (u64) gma_read32(hw, port, GM_RXO_OK_LO);
2190 for (i = 2; i < count; i++)
2191 data[i] = (u64) gma_read32(hw, port, sky2_stats[i].offset);
2194 static void sky2_set_msglevel(struct net_device *netdev, u32 value)
2196 struct sky2_port *sky2 = netdev_priv(netdev);
2197 sky2->msg_enable = value;
2200 static int sky2_get_stats_count(struct net_device *dev)
2202 return ARRAY_SIZE(sky2_stats);
2205 static void sky2_get_ethtool_stats(struct net_device *dev,
2206 struct ethtool_stats *stats, u64 * data)
2208 struct sky2_port *sky2 = netdev_priv(dev);
2210 sky2_phy_stats(sky2, data, ARRAY_SIZE(sky2_stats));
2213 static void sky2_get_strings(struct net_device *dev, u32 stringset, u8 * data)
2217 switch (stringset) {
2219 for (i = 0; i < ARRAY_SIZE(sky2_stats); i++)
2220 memcpy(data + i * ETH_GSTRING_LEN,
2221 sky2_stats[i].name, ETH_GSTRING_LEN);
2226 /* Use hardware MIB variables for critical path statistics and
2227 * transmit feedback not reported at interrupt.
2228 * Other errors are accounted for in interrupt handler.
2230 static struct net_device_stats *sky2_get_stats(struct net_device *dev)
2232 struct sky2_port *sky2 = netdev_priv(dev);
2235 sky2_phy_stats(sky2, data, ARRAY_SIZE(data));
2237 sky2->net_stats.tx_bytes = data[0];
2238 sky2->net_stats.rx_bytes = data[1];
2239 sky2->net_stats.tx_packets = data[2] + data[4] + data[6];
2240 sky2->net_stats.rx_packets = data[3] + data[5] + data[7];
2241 sky2->net_stats.multicast = data[5] + data[7];
2242 sky2->net_stats.collisions = data[10];
2243 sky2->net_stats.tx_aborted_errors = data[12];
2245 return &sky2->net_stats;
2248 static int sky2_set_mac_address(struct net_device *dev, void *p)
2250 struct sky2_port *sky2 = netdev_priv(dev);
2251 struct sockaddr *addr = p;
2254 if (!is_valid_ether_addr(addr->sa_data))
2255 return -EADDRNOTAVAIL;
2258 memcpy(dev->dev_addr, addr->sa_data, ETH_ALEN);
2259 memcpy_toio(sky2->hw->regs + B2_MAC_1 + sky2->port * 8,
2260 dev->dev_addr, ETH_ALEN);
2261 memcpy_toio(sky2->hw->regs + B2_MAC_2 + sky2->port * 8,
2262 dev->dev_addr, ETH_ALEN);
2263 if (dev->flags & IFF_UP)
2268 static void sky2_set_multicast(struct net_device *dev)
2270 struct sky2_port *sky2 = netdev_priv(dev);
2271 struct sky2_hw *hw = sky2->hw;
2272 unsigned port = sky2->port;
2273 struct dev_mc_list *list = dev->mc_list;
2277 memset(filter, 0, sizeof(filter));
2279 reg = gma_read16(hw, port, GM_RX_CTRL);
2280 reg |= GM_RXCR_UCF_ENA;
2282 if (dev->flags & IFF_PROMISC) /* promiscious */
2283 reg &= ~(GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA);
2284 else if ((dev->flags & IFF_ALLMULTI) || dev->mc_count > 16) /* all multicast */
2285 memset(filter, 0xff, sizeof(filter));
2286 else if (dev->mc_count == 0) /* no multicast */
2287 reg &= ~GM_RXCR_MCF_ENA;
2290 reg |= GM_RXCR_MCF_ENA;
2292 for (i = 0; list && i < dev->mc_count; i++, list = list->next) {
2293 u32 bit = ether_crc(ETH_ALEN, list->dmi_addr) & 0x3f;
2294 filter[bit / 8] |= 1 << (bit % 8);
2298 gma_write16(hw, port, GM_MC_ADDR_H1,
2299 (u16) filter[0] | ((u16) filter[1] << 8));
2300 gma_write16(hw, port, GM_MC_ADDR_H2,
2301 (u16) filter[2] | ((u16) filter[3] << 8));
2302 gma_write16(hw, port, GM_MC_ADDR_H3,
2303 (u16) filter[4] | ((u16) filter[5] << 8));
2304 gma_write16(hw, port, GM_MC_ADDR_H4,
2305 (u16) filter[6] | ((u16) filter[7] << 8));
2307 gma_write16(hw, port, GM_RX_CTRL, reg);
2310 /* Can have one global because blinking is controlled by
2311 * ethtool and that is always under RTNL mutex
2313 static inline void sky2_led(struct sky2_hw *hw, unsigned port, int on)
2317 spin_lock_bh(&hw->phy_lock);
2318 switch (hw->chip_id) {
2319 case CHIP_ID_YUKON_XL:
2320 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
2321 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
2322 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
2323 on ? (PHY_M_LEDC_LOS_CTRL(1) |
2324 PHY_M_LEDC_INIT_CTRL(7) |
2325 PHY_M_LEDC_STA1_CTRL(7) |
2326 PHY_M_LEDC_STA0_CTRL(7))
2329 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
2333 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, 0);
2334 gm_phy_write(hw, port, PHY_MARV_LED_OVER,
2335 on ? PHY_M_LED_MO_DUP(MO_LED_ON) |
2336 PHY_M_LED_MO_10(MO_LED_ON) |
2337 PHY_M_LED_MO_100(MO_LED_ON) |
2338 PHY_M_LED_MO_1000(MO_LED_ON) |
2339 PHY_M_LED_MO_RX(MO_LED_ON)
2340 : PHY_M_LED_MO_DUP(MO_LED_OFF) |
2341 PHY_M_LED_MO_10(MO_LED_OFF) |
2342 PHY_M_LED_MO_100(MO_LED_OFF) |
2343 PHY_M_LED_MO_1000(MO_LED_OFF) |
2344 PHY_M_LED_MO_RX(MO_LED_OFF));
2347 spin_unlock_bh(&hw->phy_lock);
2350 /* blink LED's for finding board */
2351 static int sky2_phys_id(struct net_device *dev, u32 data)
2353 struct sky2_port *sky2 = netdev_priv(dev);
2354 struct sky2_hw *hw = sky2->hw;
2355 unsigned port = sky2->port;
2356 u16 ledctrl, ledover = 0;
2360 if (!data || data > (u32) (MAX_SCHEDULE_TIMEOUT / HZ))
2361 ms = jiffies_to_msecs(MAX_SCHEDULE_TIMEOUT);
2365 /* save initial values */
2366 spin_lock_bh(&hw->phy_lock);
2367 if (hw->chip_id == CHIP_ID_YUKON_XL) {
2368 u16 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
2369 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
2370 ledctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
2371 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
2373 ledctrl = gm_phy_read(hw, port, PHY_MARV_LED_CTRL);
2374 ledover = gm_phy_read(hw, port, PHY_MARV_LED_OVER);
2376 spin_unlock_bh(&hw->phy_lock);
2379 sky2_led(hw, port, onoff);
2382 if (msleep_interruptible(250))
2383 break; /* interrupted */
2387 /* resume regularly scheduled programming */
2388 spin_lock_bh(&hw->phy_lock);
2389 if (hw->chip_id == CHIP_ID_YUKON_XL) {
2390 u16 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
2391 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
2392 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ledctrl);
2393 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
2395 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, ledctrl);
2396 gm_phy_write(hw, port, PHY_MARV_LED_OVER, ledover);
2398 spin_unlock_bh(&hw->phy_lock);
2403 static void sky2_get_pauseparam(struct net_device *dev,
2404 struct ethtool_pauseparam *ecmd)
2406 struct sky2_port *sky2 = netdev_priv(dev);
2408 ecmd->tx_pause = sky2->tx_pause;
2409 ecmd->rx_pause = sky2->rx_pause;
2410 ecmd->autoneg = sky2->autoneg;
2413 static int sky2_set_pauseparam(struct net_device *dev,
2414 struct ethtool_pauseparam *ecmd)
2416 struct sky2_port *sky2 = netdev_priv(dev);
2419 sky2->autoneg = ecmd->autoneg;
2420 sky2->tx_pause = ecmd->tx_pause != 0;
2421 sky2->rx_pause = ecmd->rx_pause != 0;
2423 if (netif_running(dev)) {
2432 static void sky2_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
2434 struct sky2_port *sky2 = netdev_priv(dev);
2436 wol->supported = WAKE_MAGIC;
2437 wol->wolopts = sky2->wol ? WAKE_MAGIC : 0;
2440 static int sky2_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
2442 struct sky2_port *sky2 = netdev_priv(dev);
2443 struct sky2_hw *hw = sky2->hw;
2445 if (wol->wolopts != WAKE_MAGIC && wol->wolopts != 0)
2448 sky2->wol = wol->wolopts == WAKE_MAGIC;
2451 memcpy_toio(hw->regs + WOL_MAC_ADDR, dev->dev_addr, ETH_ALEN);
2453 sky2_write16(hw, WOL_CTRL_STAT,
2454 WOL_CTL_ENA_PME_ON_MAGIC_PKT |
2455 WOL_CTL_ENA_MAGIC_PKT_UNIT);
2457 sky2_write16(hw, WOL_CTRL_STAT, WOL_CTL_DEFAULT);
2463 static void sky2_get_ringparam(struct net_device *dev,
2464 struct ethtool_ringparam *ering)
2466 struct sky2_port *sky2 = netdev_priv(dev);
2468 ering->rx_max_pending = RX_MAX_PENDING;
2469 ering->rx_mini_max_pending = 0;
2470 ering->rx_jumbo_max_pending = 0;
2471 ering->tx_max_pending = TX_RING_SIZE - 1;
2473 ering->rx_pending = sky2->rx_pending;
2474 ering->rx_mini_pending = 0;
2475 ering->rx_jumbo_pending = 0;
2476 ering->tx_pending = sky2->tx_pending;
2479 static int sky2_set_ringparam(struct net_device *dev,
2480 struct ethtool_ringparam *ering)
2482 struct sky2_port *sky2 = netdev_priv(dev);
2485 if (ering->rx_pending > RX_MAX_PENDING ||
2486 ering->rx_pending < 8 ||
2487 ering->tx_pending < MAX_SKB_TX_LE ||
2488 ering->tx_pending > TX_RING_SIZE - 1)
2491 if (netif_running(dev))
2494 sky2->rx_pending = ering->rx_pending;
2495 sky2->tx_pending = ering->tx_pending;
2497 if (netif_running(dev))
2503 static int sky2_get_regs_len(struct net_device *dev)
2509 * Returns copy of control register region
2510 * Note: access to the RAM address register set will cause timeouts.
2512 static void sky2_get_regs(struct net_device *dev, struct ethtool_regs *regs,
2515 const struct sky2_port *sky2 = netdev_priv(dev);
2516 const void __iomem *io = sky2->hw->regs;
2518 BUG_ON(regs->len < B3_RI_WTO_R1);
2520 memset(p, 0, regs->len);
2522 memcpy_fromio(p, io, B3_RAM_ADDR);
2524 memcpy_fromio(p + B3_RI_WTO_R1,
2526 regs->len - B3_RI_WTO_R1);
2529 static struct ethtool_ops sky2_ethtool_ops = {
2530 .get_settings = sky2_get_settings,
2531 .set_settings = sky2_set_settings,
2532 .get_drvinfo = sky2_get_drvinfo,
2533 .get_msglevel = sky2_get_msglevel,
2534 .set_msglevel = sky2_set_msglevel,
2535 .get_regs_len = sky2_get_regs_len,
2536 .get_regs = sky2_get_regs,
2537 .get_link = ethtool_op_get_link,
2538 .get_sg = ethtool_op_get_sg,
2539 .set_sg = ethtool_op_set_sg,
2540 .get_tx_csum = ethtool_op_get_tx_csum,
2541 .set_tx_csum = ethtool_op_set_tx_csum,
2542 .get_tso = ethtool_op_get_tso,
2543 .set_tso = ethtool_op_set_tso,
2544 .get_rx_csum = sky2_get_rx_csum,
2545 .set_rx_csum = sky2_set_rx_csum,
2546 .get_strings = sky2_get_strings,
2547 .get_ringparam = sky2_get_ringparam,
2548 .set_ringparam = sky2_set_ringparam,
2549 .get_pauseparam = sky2_get_pauseparam,
2550 .set_pauseparam = sky2_set_pauseparam,
2552 .get_wol = sky2_get_wol,
2553 .set_wol = sky2_set_wol,
2555 .phys_id = sky2_phys_id,
2556 .get_stats_count = sky2_get_stats_count,
2557 .get_ethtool_stats = sky2_get_ethtool_stats,
2560 /* Initialize network device */
2561 static __devinit struct net_device *sky2_init_netdev(struct sky2_hw *hw,
2562 unsigned port, int highmem)
2564 struct sky2_port *sky2;
2565 struct net_device *dev = alloc_etherdev(sizeof(*sky2));
2568 printk(KERN_ERR "sky2 etherdev alloc failed");
2572 SET_MODULE_OWNER(dev);
2573 SET_NETDEV_DEV(dev, &hw->pdev->dev);
2574 dev->open = sky2_up;
2575 dev->stop = sky2_down;
2576 dev->hard_start_xmit = sky2_xmit_frame;
2577 dev->get_stats = sky2_get_stats;
2578 dev->set_multicast_list = sky2_set_multicast;
2579 dev->set_mac_address = sky2_set_mac_address;
2580 dev->change_mtu = sky2_change_mtu;
2581 SET_ETHTOOL_OPS(dev, &sky2_ethtool_ops);
2582 dev->tx_timeout = sky2_tx_timeout;
2583 dev->watchdog_timeo = TX_WATCHDOG;
2585 dev->poll = sky2_poll;
2586 dev->weight = NAPI_WEIGHT;
2587 #ifdef CONFIG_NET_POLL_CONTROLLER
2588 dev->poll_controller = sky2_netpoll;
2591 sky2 = netdev_priv(dev);
2594 sky2->msg_enable = netif_msg_init(debug, default_msg);
2596 spin_lock_init(&sky2->tx_lock);
2597 /* Auto speed and flow control */
2598 sky2->autoneg = AUTONEG_ENABLE;
2603 sky2->advertising = sky2_supported_modes(hw);
2605 tasklet_init(&sky2->phy_task, sky2_phy_task, (unsigned long)sky2);
2606 sky2->tx_pending = TX_DEF_PENDING;
2607 sky2->rx_pending = is_ec_a1(hw) ? 8 : RX_DEF_PENDING;
2609 hw->dev[port] = dev;
2613 dev->features |= NETIF_F_LLTX | NETIF_F_TSO;
2615 dev->features |= NETIF_F_HIGHDMA;
2616 dev->features |= NETIF_F_IP_CSUM | NETIF_F_SG;
2618 /* read the mac address */
2619 memcpy_fromio(dev->dev_addr, hw->regs + B2_MAC_1 + port * 8, ETH_ALEN);
2621 /* device is off until link detection */
2622 netif_carrier_off(dev);
2623 netif_stop_queue(dev);
2628 static inline void sky2_show_addr(struct net_device *dev)
2630 const struct sky2_port *sky2 = netdev_priv(dev);
2632 if (netif_msg_probe(sky2))
2633 printk(KERN_INFO PFX "%s: addr %02x:%02x:%02x:%02x:%02x:%02x\n",
2635 dev->dev_addr[0], dev->dev_addr[1], dev->dev_addr[2],
2636 dev->dev_addr[3], dev->dev_addr[4], dev->dev_addr[5]);
2639 static int __devinit sky2_probe(struct pci_dev *pdev,
2640 const struct pci_device_id *ent)
2642 struct net_device *dev, *dev1 = NULL;
2644 int err, using_dac = 0;
2646 err = pci_enable_device(pdev);
2648 printk(KERN_ERR PFX "%s cannot enable PCI device\n",
2653 err = pci_request_regions(pdev, DRV_NAME);
2655 printk(KERN_ERR PFX "%s cannot obtain PCI resources\n",
2660 pci_set_master(pdev);
2662 if (sizeof(dma_addr_t) > sizeof(u32)) {
2663 err = pci_set_dma_mask(pdev, DMA_64BIT_MASK);
2669 err = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
2671 printk(KERN_ERR PFX "%s no usable DMA configuration\n",
2673 goto err_out_free_regions;
2677 /* byte swap decriptors in hardware */
2681 pci_read_config_dword(pdev, PCI_DEV_REG2, ®);
2682 reg |= PCI_REV_DESC;
2683 pci_write_config_dword(pdev, PCI_DEV_REG2, reg);
2688 hw = kmalloc(sizeof(*hw), GFP_KERNEL);
2690 printk(KERN_ERR PFX "%s: cannot allocate hardware struct\n",
2692 goto err_out_free_regions;
2695 memset(hw, 0, sizeof(*hw));
2697 spin_lock_init(&hw->phy_lock);
2699 hw->regs = ioremap_nocache(pci_resource_start(pdev, 0), 0x4000);
2701 printk(KERN_ERR PFX "%s: cannot map device registers\n",
2703 goto err_out_free_hw;
2706 err = sky2_reset(hw);
2708 goto err_out_iounmap;
2710 printk(KERN_INFO PFX "addr 0x%lx irq %d Yukon-%s (0x%x) rev %d\n",
2711 pci_resource_start(pdev, 0), pdev->irq,
2712 yukon_name[hw->chip_id - CHIP_ID_YUKON],
2713 hw->chip_id, hw->chip_rev);
2715 dev = sky2_init_netdev(hw, 0, using_dac);
2717 goto err_out_free_pci;
2719 err = register_netdev(dev);
2721 printk(KERN_ERR PFX "%s: cannot register net device\n",
2723 goto err_out_free_netdev;
2726 sky2_show_addr(dev);
2728 if (hw->ports > 1 && (dev1 = sky2_init_netdev(hw, 1, using_dac))) {
2729 if (register_netdev(dev1) == 0)
2730 sky2_show_addr(dev1);
2732 /* Failure to register second port need not be fatal */
2733 printk(KERN_WARNING PFX
2734 "register of second port failed\n");
2740 err = request_irq(pdev->irq, sky2_intr, SA_SHIRQ, DRV_NAME, hw);
2742 printk(KERN_ERR PFX "%s: cannot assign irq %d\n",
2743 pci_name(pdev), pdev->irq);
2744 goto err_out_unregister;
2747 hw->intr_mask = Y2_IS_BASE;
2748 sky2_write32(hw, B0_IMSK, hw->intr_mask);
2750 pci_set_drvdata(pdev, hw);
2756 unregister_netdev(dev1);
2759 unregister_netdev(dev);
2760 err_out_free_netdev:
2763 sky2_write8(hw, B0_CTST, CS_RST_SET);
2764 pci_free_consistent(hw->pdev, STATUS_LE_BYTES, hw->st_le, hw->st_dma);
2769 err_out_free_regions:
2770 pci_release_regions(pdev);
2771 pci_disable_device(pdev);
2776 static void __devexit sky2_remove(struct pci_dev *pdev)
2778 struct sky2_hw *hw = pci_get_drvdata(pdev);
2779 struct net_device *dev0, *dev1;
2787 unregister_netdev(dev1);
2788 unregister_netdev(dev0);
2790 sky2_write32(hw, B0_IMSK, 0);
2791 sky2_write16(hw, B0_Y2LED, LED_STAT_OFF);
2792 sky2_write8(hw, B0_CTST, CS_RST_SET);
2794 free_irq(pdev->irq, hw);
2795 pci_free_consistent(pdev, STATUS_LE_BYTES, hw->st_le, hw->st_dma);
2796 pci_release_regions(pdev);
2797 pci_disable_device(pdev);
2804 pci_set_drvdata(pdev, NULL);
2808 static int sky2_suspend(struct pci_dev *pdev, pm_message_t state)
2810 struct sky2_hw *hw = pci_get_drvdata(pdev);
2813 for (i = 0; i < 2; i++) {
2814 struct net_device *dev = hw->dev[i];
2817 struct sky2_port *sky2 = netdev_priv(dev);
2818 if (netif_running(dev)) {
2819 netif_carrier_off(dev);
2822 netif_device_detach(dev);
2827 pci_save_state(pdev);
2828 pci_enable_wake(pdev, pci_choose_state(pdev, state), wol);
2829 pci_disable_device(pdev);
2830 pci_set_power_state(pdev, pci_choose_state(pdev, state));
2835 static int sky2_resume(struct pci_dev *pdev)
2837 struct sky2_hw *hw = pci_get_drvdata(pdev);
2840 pci_set_power_state(pdev, PCI_D0);
2841 pci_restore_state(pdev);
2842 pci_enable_wake(pdev, PCI_D0, 0);
2846 for (i = 0; i < 2; i++) {
2847 struct net_device *dev = hw->dev[i];
2849 netif_device_attach(dev);
2850 if (netif_running(dev))
2858 static struct pci_driver sky2_driver = {
2860 .id_table = sky2_id_table,
2861 .probe = sky2_probe,
2862 .remove = __devexit_p(sky2_remove),
2864 .suspend = sky2_suspend,
2865 .resume = sky2_resume,
2869 static int __init sky2_init_module(void)
2871 return pci_module_init(&sky2_driver);
2874 static void __exit sky2_cleanup_module(void)
2876 pci_unregister_driver(&sky2_driver);
2879 module_init(sky2_init_module);
2880 module_exit(sky2_cleanup_module);
2882 MODULE_DESCRIPTION("Marvell Yukon 2 Gigabit Ethernet driver");
2883 MODULE_AUTHOR("Stephen Hemminger <shemminger@osdl.org>");
2884 MODULE_LICENSE("GPL");