2 * New driver for Marvell Yukon 2 chipset.
3 * Based on earlier sk98lin, and skge driver.
5 * This driver intentionally does not support all the features
6 * of the original driver such as link fail-over and link management because
7 * those should be done at higher levels.
9 * Copyright (C) 2005 Stephen Hemminger <shemminger@osdl.org>
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License, or
14 * (at your option) any later version.
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
26 #include <linux/crc32.h>
27 #include <linux/kernel.h>
28 #include <linux/version.h>
29 #include <linux/module.h>
30 #include <linux/netdevice.h>
31 #include <linux/dma-mapping.h>
32 #include <linux/etherdevice.h>
33 #include <linux/ethtool.h>
34 #include <linux/pci.h>
36 #include <linux/tcp.h>
38 #include <linux/delay.h>
39 #include <linux/workqueue.h>
40 #include <linux/if_vlan.h>
41 #include <linux/prefetch.h>
42 #include <linux/mii.h>
46 #if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
47 #define SKY2_VLAN_TAG_USED 1
52 #define DRV_NAME "sky2"
53 #define DRV_VERSION "1.7"
54 #define PFX DRV_NAME " "
57 * The Yukon II chipset takes 64 bit command blocks (called list elements)
58 * that are organized into three (receive, transmit, status) different rings
59 * similar to Tigon3. A transmit can require several elements;
60 * a receive requires one (or two if using 64 bit dma).
63 #define RX_LE_SIZE 512
64 #define RX_LE_BYTES (RX_LE_SIZE*sizeof(struct sky2_rx_le))
65 #define RX_MAX_PENDING (RX_LE_SIZE/2 - 2)
66 #define RX_DEF_PENDING RX_MAX_PENDING
67 #define RX_SKB_ALIGN 8
68 #define RX_BUF_WRITE 16
70 #define TX_RING_SIZE 512
71 #define TX_DEF_PENDING (TX_RING_SIZE - 1)
72 #define TX_MIN_PENDING 64
73 #define MAX_SKB_TX_LE (4 + (sizeof(dma_addr_t)/sizeof(u32))*MAX_SKB_FRAGS)
75 #define STATUS_RING_SIZE 2048 /* 2 ports * (TX + 2*RX) */
76 #define STATUS_LE_BYTES (STATUS_RING_SIZE*sizeof(struct sky2_status_le))
77 #define ETH_JUMBO_MTU 9000
78 #define TX_WATCHDOG (5 * HZ)
79 #define NAPI_WEIGHT 64
80 #define PHY_RETRIES 1000
82 #define RING_NEXT(x,s) (((x)+1) & ((s)-1))
84 static const u32 default_msg =
85 NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_LINK
86 | NETIF_MSG_TIMER | NETIF_MSG_TX_ERR | NETIF_MSG_RX_ERR
87 | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN;
89 static int debug = -1; /* defaults above */
90 module_param(debug, int, 0);
91 MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
93 static int copybreak __read_mostly = 256;
94 module_param(copybreak, int, 0);
95 MODULE_PARM_DESC(copybreak, "Receive copy threshold");
97 static int disable_msi = 0;
98 module_param(disable_msi, int, 0);
99 MODULE_PARM_DESC(disable_msi, "Disable Message Signaled Interrupt (MSI)");
101 static int idle_timeout = 100;
102 module_param(idle_timeout, int, 0);
103 MODULE_PARM_DESC(idle_timeout, "Idle timeout workaround for lost interrupts (ms)");
105 static const struct pci_device_id sky2_id_table[] = {
106 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, 0x9000) },
107 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, 0x9E00) },
108 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4b00) }, /* DGE-560T */
109 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4001) }, /* DGE-550SX */
110 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4340) },
111 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4341) },
112 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4342) },
113 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4343) },
114 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4344) },
115 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4345) },
116 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4346) },
117 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4347) },
118 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4350) },
119 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4351) },
120 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4352) },
121 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4353) },
122 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4360) },
123 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4361) },
124 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4362) },
125 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4363) },
126 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4364) },
127 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4365) },
128 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4366) },
129 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4367) },
130 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4368) },
131 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4369) },
135 MODULE_DEVICE_TABLE(pci, sky2_id_table);
137 /* Avoid conditionals by using array */
138 static const unsigned txqaddr[] = { Q_XA1, Q_XA2 };
139 static const unsigned rxqaddr[] = { Q_R1, Q_R2 };
140 static const u32 portirq_msk[] = { Y2_IS_PORT_1, Y2_IS_PORT_2 };
142 /* This driver supports yukon2 chipset only */
143 static const char *yukon2_name[] = {
145 "EC Ultra", /* 0xb4 */
146 "UNKNOWN", /* 0xb5 */
151 /* Access to external PHY */
152 static int gm_phy_write(struct sky2_hw *hw, unsigned port, u16 reg, u16 val)
156 gma_write16(hw, port, GM_SMI_DATA, val);
157 gma_write16(hw, port, GM_SMI_CTRL,
158 GM_SMI_CT_PHY_AD(PHY_ADDR_MARV) | GM_SMI_CT_REG_AD(reg));
160 for (i = 0; i < PHY_RETRIES; i++) {
161 if (!(gma_read16(hw, port, GM_SMI_CTRL) & GM_SMI_CT_BUSY))
166 printk(KERN_WARNING PFX "%s: phy write timeout\n", hw->dev[port]->name);
170 static int __gm_phy_read(struct sky2_hw *hw, unsigned port, u16 reg, u16 *val)
174 gma_write16(hw, port, GM_SMI_CTRL, GM_SMI_CT_PHY_AD(PHY_ADDR_MARV)
175 | GM_SMI_CT_REG_AD(reg) | GM_SMI_CT_OP_RD);
177 for (i = 0; i < PHY_RETRIES; i++) {
178 if (gma_read16(hw, port, GM_SMI_CTRL) & GM_SMI_CT_RD_VAL) {
179 *val = gma_read16(hw, port, GM_SMI_DATA);
189 static u16 gm_phy_read(struct sky2_hw *hw, unsigned port, u16 reg)
193 if (__gm_phy_read(hw, port, reg, &v) != 0)
194 printk(KERN_WARNING PFX "%s: phy read timeout\n", hw->dev[port]->name);
198 static void sky2_set_power_state(struct sky2_hw *hw, pci_power_t state)
203 pr_debug("sky2_set_power_state %d\n", state);
204 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
206 power_control = sky2_pci_read16(hw, hw->pm_cap + PCI_PM_PMC);
207 vaux = (sky2_read16(hw, B0_CTST) & Y2_VAUX_AVAIL) &&
208 (power_control & PCI_PM_CAP_PME_D3cold);
210 power_control = sky2_pci_read16(hw, hw->pm_cap + PCI_PM_CTRL);
212 power_control |= PCI_PM_CTRL_PME_STATUS;
213 power_control &= ~(PCI_PM_CTRL_STATE_MASK);
217 /* switch power to VCC (WA for VAUX problem) */
218 sky2_write8(hw, B0_POWER_CTRL,
219 PC_VAUX_ENA | PC_VCC_ENA | PC_VAUX_OFF | PC_VCC_ON);
221 /* disable Core Clock Division, */
222 sky2_write32(hw, B2_Y2_CLK_CTRL, Y2_CLK_DIV_DIS);
224 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1)
225 /* enable bits are inverted */
226 sky2_write8(hw, B2_Y2_CLK_GATE,
227 Y2_PCI_CLK_LNK1_DIS | Y2_COR_CLK_LNK1_DIS |
228 Y2_CLK_GAT_LNK1_DIS | Y2_PCI_CLK_LNK2_DIS |
229 Y2_COR_CLK_LNK2_DIS | Y2_CLK_GAT_LNK2_DIS);
231 sky2_write8(hw, B2_Y2_CLK_GATE, 0);
233 if (hw->chip_id == CHIP_ID_YUKON_EC_U) {
236 sky2_pci_write32(hw, PCI_DEV_REG3, 0);
237 reg1 = sky2_pci_read32(hw, PCI_DEV_REG4);
238 reg1 &= P_ASPM_CONTROL_MSK;
239 sky2_pci_write32(hw, PCI_DEV_REG4, reg1);
240 sky2_pci_write32(hw, PCI_DEV_REG5, 0);
247 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1)
248 sky2_write8(hw, B2_Y2_CLK_GATE, 0);
250 /* enable bits are inverted */
251 sky2_write8(hw, B2_Y2_CLK_GATE,
252 Y2_PCI_CLK_LNK1_DIS | Y2_COR_CLK_LNK1_DIS |
253 Y2_CLK_GAT_LNK1_DIS | Y2_PCI_CLK_LNK2_DIS |
254 Y2_COR_CLK_LNK2_DIS | Y2_CLK_GAT_LNK2_DIS);
256 /* switch power to VAUX */
257 if (vaux && state != PCI_D3cold)
258 sky2_write8(hw, B0_POWER_CTRL,
259 (PC_VAUX_ENA | PC_VCC_ENA |
260 PC_VAUX_ON | PC_VCC_OFF));
263 printk(KERN_ERR PFX "Unknown power state %d\n", state);
266 sky2_pci_write16(hw, hw->pm_cap + PCI_PM_CTRL, power_control);
267 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
270 static void sky2_gmac_reset(struct sky2_hw *hw, unsigned port)
274 /* disable all GMAC IRQ's */
275 sky2_write8(hw, SK_REG(port, GMAC_IRQ_MSK), 0);
276 /* disable PHY IRQs */
277 gm_phy_write(hw, port, PHY_MARV_INT_MASK, 0);
279 gma_write16(hw, port, GM_MC_ADDR_H1, 0); /* clear MC hash */
280 gma_write16(hw, port, GM_MC_ADDR_H2, 0);
281 gma_write16(hw, port, GM_MC_ADDR_H3, 0);
282 gma_write16(hw, port, GM_MC_ADDR_H4, 0);
284 reg = gma_read16(hw, port, GM_RX_CTRL);
285 reg |= GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA;
286 gma_write16(hw, port, GM_RX_CTRL, reg);
289 static void sky2_phy_init(struct sky2_hw *hw, unsigned port)
291 struct sky2_port *sky2 = netdev_priv(hw->dev[port]);
292 u16 ctrl, ct1000, adv, pg, ledctrl, ledover, reg;
294 if (sky2->autoneg == AUTONEG_ENABLE &&
295 !(hw->chip_id == CHIP_ID_YUKON_XL || hw->chip_id == CHIP_ID_YUKON_EC_U)) {
296 u16 ectrl = gm_phy_read(hw, port, PHY_MARV_EXT_CTRL);
298 ectrl &= ~(PHY_M_EC_M_DSC_MSK | PHY_M_EC_S_DSC_MSK |
300 ectrl |= PHY_M_EC_MAC_S(MAC_TX_CLK_25_MHZ);
302 if (hw->chip_id == CHIP_ID_YUKON_EC)
303 ectrl |= PHY_M_EC_DSC_2(2) | PHY_M_EC_DOWN_S_ENA;
305 ectrl |= PHY_M_EC_M_DSC(2) | PHY_M_EC_S_DSC(3);
307 gm_phy_write(hw, port, PHY_MARV_EXT_CTRL, ectrl);
310 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
311 if (sky2_is_copper(hw)) {
312 if (hw->chip_id == CHIP_ID_YUKON_FE) {
313 /* enable automatic crossover */
314 ctrl |= PHY_M_PC_MDI_XMODE(PHY_M_PC_ENA_AUTO) >> 1;
316 /* disable energy detect */
317 ctrl &= ~PHY_M_PC_EN_DET_MSK;
319 /* enable automatic crossover */
320 ctrl |= PHY_M_PC_MDI_XMODE(PHY_M_PC_ENA_AUTO);
322 if (sky2->autoneg == AUTONEG_ENABLE &&
323 (hw->chip_id == CHIP_ID_YUKON_XL || hw->chip_id == CHIP_ID_YUKON_EC_U)) {
324 ctrl &= ~PHY_M_PC_DSC_MSK;
325 ctrl |= PHY_M_PC_DSC(2) | PHY_M_PC_DOWN_S_ENA;
329 /* workaround for deviation #4.88 (CRC errors) */
330 /* disable Automatic Crossover */
332 ctrl &= ~PHY_M_PC_MDIX_MSK;
335 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
337 /* special setup for PHY 88E1112 Fiber */
338 if (hw->chip_id == CHIP_ID_YUKON_XL && !sky2_is_copper(hw)) {
339 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
341 /* Fiber: select 1000BASE-X only mode MAC Specific Ctrl Reg. */
342 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 2);
343 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
344 ctrl &= ~PHY_M_MAC_MD_MSK;
345 ctrl |= PHY_M_MAC_MODE_SEL(PHY_M_MAC_MD_1000BX);
346 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
348 if (hw->pmd_type == 'P') {
349 /* select page 1 to access Fiber registers */
350 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 1);
352 /* for SFP-module set SIGDET polarity to low */
353 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
354 ctrl |= PHY_M_FIB_SIGD_POL;
355 gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
358 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
361 ctrl = gm_phy_read(hw, port, PHY_MARV_CTRL);
362 if (sky2->autoneg == AUTONEG_DISABLE)
367 ctrl |= PHY_CT_RESET;
368 gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
375 if (sky2->autoneg == AUTONEG_ENABLE) {
376 if (sky2_is_copper(hw)) {
377 if (sky2->advertising & ADVERTISED_1000baseT_Full)
378 ct1000 |= PHY_M_1000C_AFD;
379 if (sky2->advertising & ADVERTISED_1000baseT_Half)
380 ct1000 |= PHY_M_1000C_AHD;
381 if (sky2->advertising & ADVERTISED_100baseT_Full)
382 adv |= PHY_M_AN_100_FD;
383 if (sky2->advertising & ADVERTISED_100baseT_Half)
384 adv |= PHY_M_AN_100_HD;
385 if (sky2->advertising & ADVERTISED_10baseT_Full)
386 adv |= PHY_M_AN_10_FD;
387 if (sky2->advertising & ADVERTISED_10baseT_Half)
388 adv |= PHY_M_AN_10_HD;
389 } else { /* special defines for FIBER (88E1040S only) */
390 if (sky2->advertising & ADVERTISED_1000baseT_Full)
391 adv |= PHY_M_AN_1000X_AFD;
392 if (sky2->advertising & ADVERTISED_1000baseT_Half)
393 adv |= PHY_M_AN_1000X_AHD;
396 /* Set Flow-control capabilities */
397 if (sky2->tx_pause && sky2->rx_pause)
398 adv |= PHY_AN_PAUSE_CAP; /* symmetric */
399 else if (sky2->rx_pause && !sky2->tx_pause)
400 adv |= PHY_AN_PAUSE_ASYM | PHY_AN_PAUSE_CAP;
401 else if (!sky2->rx_pause && sky2->tx_pause)
402 adv |= PHY_AN_PAUSE_ASYM; /* local */
404 /* Restart Auto-negotiation */
405 ctrl |= PHY_CT_ANE | PHY_CT_RE_CFG;
407 /* forced speed/duplex settings */
408 ct1000 = PHY_M_1000C_MSE;
410 /* Disable auto update for duplex flow control and speed */
411 reg |= GM_GPCR_AU_ALL_DIS;
413 switch (sky2->speed) {
415 ctrl |= PHY_CT_SP1000;
416 reg |= GM_GPCR_SPEED_1000;
419 ctrl |= PHY_CT_SP100;
420 reg |= GM_GPCR_SPEED_100;
424 if (sky2->duplex == DUPLEX_FULL) {
425 reg |= GM_GPCR_DUP_FULL;
426 ctrl |= PHY_CT_DUP_MD;
427 } else if (sky2->speed != SPEED_1000 && hw->chip_id != CHIP_ID_YUKON_EC_U) {
428 /* Turn off flow control for 10/100mbps */
434 reg |= GM_GPCR_FC_RX_DIS;
437 reg |= GM_GPCR_FC_TX_DIS;
439 /* Forward pause packets to GMAC? */
440 if (sky2->tx_pause || sky2->rx_pause)
441 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON);
443 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
445 ctrl |= PHY_CT_RESET;
448 gma_write16(hw, port, GM_GP_CTRL, reg);
450 if (hw->chip_id != CHIP_ID_YUKON_FE)
451 gm_phy_write(hw, port, PHY_MARV_1000T_CTRL, ct1000);
453 gm_phy_write(hw, port, PHY_MARV_AUNE_ADV, adv);
454 gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
456 /* Setup Phy LED's */
457 ledctrl = PHY_M_LED_PULS_DUR(PULS_170MS);
460 switch (hw->chip_id) {
461 case CHIP_ID_YUKON_FE:
462 /* on 88E3082 these bits are at 11..9 (shifted left) */
463 ledctrl |= PHY_M_LED_BLINK_RT(BLINK_84MS) << 1;
465 ctrl = gm_phy_read(hw, port, PHY_MARV_FE_LED_PAR);
467 /* delete ACT LED control bits */
468 ctrl &= ~PHY_M_FELP_LED1_MSK;
469 /* change ACT LED control to blink mode */
470 ctrl |= PHY_M_FELP_LED1_CTRL(LED_PAR_CTRL_ACT_BL);
471 gm_phy_write(hw, port, PHY_MARV_FE_LED_PAR, ctrl);
474 case CHIP_ID_YUKON_XL:
475 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
477 /* select page 3 to access LED control register */
478 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
480 /* set LED Function Control register */
481 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
482 (PHY_M_LEDC_LOS_CTRL(1) | /* LINK/ACT */
483 PHY_M_LEDC_INIT_CTRL(7) | /* 10 Mbps */
484 PHY_M_LEDC_STA1_CTRL(7) | /* 100 Mbps */
485 PHY_M_LEDC_STA0_CTRL(7))); /* 1000 Mbps */
487 /* set Polarity Control register */
488 gm_phy_write(hw, port, PHY_MARV_PHY_STAT,
489 (PHY_M_POLC_LS1_P_MIX(4) |
490 PHY_M_POLC_IS0_P_MIX(4) |
491 PHY_M_POLC_LOS_CTRL(2) |
492 PHY_M_POLC_INIT_CTRL(2) |
493 PHY_M_POLC_STA1_CTRL(2) |
494 PHY_M_POLC_STA0_CTRL(2)));
496 /* restore page register */
497 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
499 case CHIP_ID_YUKON_EC_U:
500 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
502 /* select page 3 to access LED control register */
503 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
505 /* set LED Function Control register */
506 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
507 (PHY_M_LEDC_LOS_CTRL(1) | /* LINK/ACT */
508 PHY_M_LEDC_INIT_CTRL(8) | /* 10 Mbps */
509 PHY_M_LEDC_STA1_CTRL(7) | /* 100 Mbps */
510 PHY_M_LEDC_STA0_CTRL(7)));/* 1000 Mbps */
512 /* set Blink Rate in LED Timer Control Register */
513 gm_phy_write(hw, port, PHY_MARV_INT_MASK,
514 ledctrl | PHY_M_LED_BLINK_RT(BLINK_84MS));
515 /* restore page register */
516 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
520 /* set Tx LED (LED_TX) to blink mode on Rx OR Tx activity */
521 ledctrl |= PHY_M_LED_BLINK_RT(BLINK_84MS) | PHY_M_LEDC_TX_CTRL;
522 /* turn off the Rx LED (LED_RX) */
523 ledover |= PHY_M_LED_MO_RX(MO_LED_OFF);
526 if (hw->chip_id == CHIP_ID_YUKON_EC_U && hw->chip_rev == CHIP_REV_YU_EC_A1) {
527 /* apply fixes in PHY AFE */
528 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
529 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 255);
531 /* increase differential signal amplitude in 10BASE-T */
532 gm_phy_write(hw, port, 0x18, 0xaa99);
533 gm_phy_write(hw, port, 0x17, 0x2011);
535 /* fix for IEEE A/B Symmetry failure in 1000BASE-T */
536 gm_phy_write(hw, port, 0x18, 0xa204);
537 gm_phy_write(hw, port, 0x17, 0x2002);
539 /* set page register to 0 */
540 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
542 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, ledctrl);
544 if (sky2->autoneg == AUTONEG_DISABLE || sky2->speed == SPEED_100) {
545 /* turn on 100 Mbps LED (LED_LINK100) */
546 ledover |= PHY_M_LED_MO_100(MO_LED_ON);
550 gm_phy_write(hw, port, PHY_MARV_LED_OVER, ledover);
554 /* Enable phy interrupt on auto-negotiation complete (or link up) */
555 if (sky2->autoneg == AUTONEG_ENABLE)
556 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_IS_AN_COMPL);
558 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_DEF_MSK);
561 static void sky2_phy_power(struct sky2_hw *hw, unsigned port, int onoff)
564 static const u32 phy_power[]
565 = { PCI_Y2_PHY1_POWD, PCI_Y2_PHY2_POWD };
567 /* looks like this XL is back asswards .. */
568 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1)
571 reg1 = sky2_pci_read32(hw, PCI_DEV_REG1);
574 /* Turn off phy power saving */
575 reg1 &= ~phy_power[port];
577 reg1 |= phy_power[port];
579 sky2_pci_write32(hw, PCI_DEV_REG1, reg1);
580 sky2_pci_read32(hw, PCI_DEV_REG1);
584 /* Force a renegotiation */
585 static void sky2_phy_reinit(struct sky2_port *sky2)
587 spin_lock_bh(&sky2->phy_lock);
588 sky2_phy_init(sky2->hw, sky2->port);
589 spin_unlock_bh(&sky2->phy_lock);
592 static void sky2_mac_init(struct sky2_hw *hw, unsigned port)
594 struct sky2_port *sky2 = netdev_priv(hw->dev[port]);
597 const u8 *addr = hw->dev[port]->dev_addr;
599 sky2_write32(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET);
600 sky2_write32(hw, SK_REG(port, GPHY_CTRL), GPC_RST_CLR|GPC_ENA_PAUSE);
602 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_CLR);
604 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0 && port == 1) {
605 /* WA DEV_472 -- looks like crossed wires on port 2 */
606 /* clear GMAC 1 Control reset */
607 sky2_write8(hw, SK_REG(0, GMAC_CTRL), GMC_RST_CLR);
609 sky2_write8(hw, SK_REG(1, GMAC_CTRL), GMC_RST_SET);
610 sky2_write8(hw, SK_REG(1, GMAC_CTRL), GMC_RST_CLR);
611 } while (gm_phy_read(hw, 1, PHY_MARV_ID0) != PHY_MARV_ID0_VAL ||
612 gm_phy_read(hw, 1, PHY_MARV_ID1) != PHY_MARV_ID1_Y2 ||
613 gm_phy_read(hw, 1, PHY_MARV_INT_MASK) != 0);
616 sky2_read16(hw, SK_REG(port, GMAC_IRQ_SRC));
618 /* Enable Transmit FIFO Underrun */
619 sky2_write8(hw, SK_REG(port, GMAC_IRQ_MSK), GMAC_DEF_MSK);
621 spin_lock_bh(&sky2->phy_lock);
622 sky2_phy_init(hw, port);
623 spin_unlock_bh(&sky2->phy_lock);
626 reg = gma_read16(hw, port, GM_PHY_ADDR);
627 gma_write16(hw, port, GM_PHY_ADDR, reg | GM_PAR_MIB_CLR);
629 for (i = GM_MIB_CNT_BASE; i <= GM_MIB_CNT_END; i += 4)
630 gma_read16(hw, port, i);
631 gma_write16(hw, port, GM_PHY_ADDR, reg);
633 /* transmit control */
634 gma_write16(hw, port, GM_TX_CTRL, TX_COL_THR(TX_COL_DEF));
636 /* receive control reg: unicast + multicast + no FCS */
637 gma_write16(hw, port, GM_RX_CTRL,
638 GM_RXCR_UCF_ENA | GM_RXCR_CRC_DIS | GM_RXCR_MCF_ENA);
640 /* transmit flow control */
641 gma_write16(hw, port, GM_TX_FLOW_CTRL, 0xffff);
643 /* transmit parameter */
644 gma_write16(hw, port, GM_TX_PARAM,
645 TX_JAM_LEN_VAL(TX_JAM_LEN_DEF) |
646 TX_JAM_IPG_VAL(TX_JAM_IPG_DEF) |
647 TX_IPG_JAM_DATA(TX_IPG_JAM_DEF) |
648 TX_BACK_OFF_LIM(TX_BOF_LIM_DEF));
650 /* serial mode register */
651 reg = DATA_BLIND_VAL(DATA_BLIND_DEF) |
652 GM_SMOD_VLAN_ENA | IPG_DATA_VAL(IPG_DATA_DEF);
654 if (hw->dev[port]->mtu > ETH_DATA_LEN)
655 reg |= GM_SMOD_JUMBO_ENA;
657 gma_write16(hw, port, GM_SERIAL_MODE, reg);
659 /* virtual address for data */
660 gma_set_addr(hw, port, GM_SRC_ADDR_2L, addr);
662 /* physical address: used for pause frames */
663 gma_set_addr(hw, port, GM_SRC_ADDR_1L, addr);
665 /* ignore counter overflows */
666 gma_write16(hw, port, GM_TX_IRQ_MSK, 0);
667 gma_write16(hw, port, GM_RX_IRQ_MSK, 0);
668 gma_write16(hw, port, GM_TR_IRQ_MSK, 0);
670 /* Configure Rx MAC FIFO */
671 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_CLR);
672 sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T),
673 GMF_OPER_ON | GMF_RX_F_FL_ON);
675 /* Flush Rx MAC FIFO on any flow control or error */
676 sky2_write16(hw, SK_REG(port, RX_GMF_FL_MSK), GMR_FS_ANY_ERR);
678 /* Set threshold to 0xa (64 bytes)
679 * ASF disabled so no need to do WA dev #4.30
681 sky2_write16(hw, SK_REG(port, RX_GMF_FL_THR), RX_GMF_FL_THR_DEF);
683 /* Configure Tx MAC FIFO */
684 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_CLR);
685 sky2_write16(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_OPER_ON);
687 if (hw->chip_id == CHIP_ID_YUKON_EC_U) {
688 sky2_write8(hw, SK_REG(port, RX_GMF_LP_THR), 768/8);
689 sky2_write8(hw, SK_REG(port, RX_GMF_UP_THR), 1024/8);
690 if (hw->dev[port]->mtu > ETH_DATA_LEN) {
691 /* set Tx GMAC FIFO Almost Empty Threshold */
692 sky2_write32(hw, SK_REG(port, TX_GMF_AE_THR), 0x180);
693 /* Disable Store & Forward mode for TX */
694 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T), TX_STFW_DIS);
700 /* Assign Ram Buffer allocation.
701 * start and end are in units of 4k bytes
702 * ram registers are in units of 64bit words
704 static void sky2_ramset(struct sky2_hw *hw, u16 q, u8 startk, u8 endk)
708 start = startk * 4096/8;
709 end = (endk * 4096/8) - 1;
711 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_RST_CLR);
712 sky2_write32(hw, RB_ADDR(q, RB_START), start);
713 sky2_write32(hw, RB_ADDR(q, RB_END), end);
714 sky2_write32(hw, RB_ADDR(q, RB_WP), start);
715 sky2_write32(hw, RB_ADDR(q, RB_RP), start);
717 if (q == Q_R1 || q == Q_R2) {
718 u32 space = (endk - startk) * 4096/8;
719 u32 tp = space - space/4;
721 /* On receive queue's set the thresholds
722 * give receiver priority when > 3/4 full
723 * send pause when down to 2K
725 sky2_write32(hw, RB_ADDR(q, RB_RX_UTHP), tp);
726 sky2_write32(hw, RB_ADDR(q, RB_RX_LTHP), space/2);
729 sky2_write32(hw, RB_ADDR(q, RB_RX_UTPP), tp);
730 sky2_write32(hw, RB_ADDR(q, RB_RX_LTPP), space/4);
732 /* Enable store & forward on Tx queue's because
733 * Tx FIFO is only 1K on Yukon
735 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_STFWD);
738 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_OP_MD);
739 sky2_read8(hw, RB_ADDR(q, RB_CTRL));
742 /* Setup Bus Memory Interface */
743 static void sky2_qset(struct sky2_hw *hw, u16 q)
745 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_CLR_RESET);
746 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_OPER_INIT);
747 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_FIFO_OP_ON);
748 sky2_write32(hw, Q_ADDR(q, Q_WM), BMU_WM_DEFAULT);
751 /* Setup prefetch unit registers. This is the interface between
752 * hardware and driver list elements
754 static void sky2_prefetch_init(struct sky2_hw *hw, u32 qaddr,
757 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_RST_SET);
758 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_RST_CLR);
759 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_ADDR_HI), addr >> 32);
760 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_ADDR_LO), (u32) addr);
761 sky2_write16(hw, Y2_QADDR(qaddr, PREF_UNIT_LAST_IDX), last);
762 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_OP_ON);
764 sky2_read32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL));
767 static inline struct sky2_tx_le *get_tx_le(struct sky2_port *sky2)
769 struct sky2_tx_le *le = sky2->tx_le + sky2->tx_prod;
771 sky2->tx_prod = RING_NEXT(sky2->tx_prod, TX_RING_SIZE);
775 /* Update chip's next pointer */
776 static inline void sky2_put_idx(struct sky2_hw *hw, unsigned q, u16 idx)
778 q = Y2_QADDR(q, PREF_UNIT_PUT_IDX);
780 sky2_write16(hw, q, idx);
785 static inline struct sky2_rx_le *sky2_next_rx(struct sky2_port *sky2)
787 struct sky2_rx_le *le = sky2->rx_le + sky2->rx_put;
788 sky2->rx_put = RING_NEXT(sky2->rx_put, RX_LE_SIZE);
792 /* Return high part of DMA address (could be 32 or 64 bit) */
793 static inline u32 high32(dma_addr_t a)
795 return sizeof(a) > sizeof(u32) ? (a >> 16) >> 16 : 0;
798 /* Build description to hardware about buffer */
799 static void sky2_rx_add(struct sky2_port *sky2, dma_addr_t map)
801 struct sky2_rx_le *le;
802 u32 hi = high32(map);
803 u16 len = sky2->rx_bufsize;
805 if (sky2->rx_addr64 != hi) {
806 le = sky2_next_rx(sky2);
807 le->addr = cpu_to_le32(hi);
809 le->opcode = OP_ADDR64 | HW_OWNER;
810 sky2->rx_addr64 = high32(map + len);
813 le = sky2_next_rx(sky2);
814 le->addr = cpu_to_le32((u32) map);
815 le->length = cpu_to_le16(len);
817 le->opcode = OP_PACKET | HW_OWNER;
821 /* Tell chip where to start receive checksum.
822 * Actually has two checksums, but set both same to avoid possible byte
825 static void rx_set_checksum(struct sky2_port *sky2)
827 struct sky2_rx_le *le;
829 le = sky2_next_rx(sky2);
830 le->addr = cpu_to_le32((ETH_HLEN << 16) | ETH_HLEN);
832 le->opcode = OP_TCPSTART | HW_OWNER;
834 sky2_write32(sky2->hw,
835 Q_ADDR(rxqaddr[sky2->port], Q_CSR),
836 sky2->rx_csum ? BMU_ENA_RX_CHKSUM : BMU_DIS_RX_CHKSUM);
841 * The RX Stop command will not work for Yukon-2 if the BMU does not
842 * reach the end of packet and since we can't make sure that we have
843 * incoming data, we must reset the BMU while it is not doing a DMA
844 * transfer. Since it is possible that the RX path is still active,
845 * the RX RAM buffer will be stopped first, so any possible incoming
846 * data will not trigger a DMA. After the RAM buffer is stopped, the
847 * BMU is polled until any DMA in progress is ended and only then it
850 static void sky2_rx_stop(struct sky2_port *sky2)
852 struct sky2_hw *hw = sky2->hw;
853 unsigned rxq = rxqaddr[sky2->port];
856 /* disable the RAM Buffer receive queue */
857 sky2_write8(hw, RB_ADDR(rxq, RB_CTRL), RB_DIS_OP_MD);
859 for (i = 0; i < 0xffff; i++)
860 if (sky2_read8(hw, RB_ADDR(rxq, Q_RSL))
861 == sky2_read8(hw, RB_ADDR(rxq, Q_RL)))
864 printk(KERN_WARNING PFX "%s: receiver stop failed\n",
867 sky2_write32(hw, Q_ADDR(rxq, Q_CSR), BMU_RST_SET | BMU_FIFO_RST);
869 /* reset the Rx prefetch unit */
870 sky2_write32(hw, Y2_QADDR(rxq, PREF_UNIT_CTRL), PREF_UNIT_RST_SET);
873 /* Clean out receive buffer area, assumes receiver hardware stopped */
874 static void sky2_rx_clean(struct sky2_port *sky2)
878 memset(sky2->rx_le, 0, RX_LE_BYTES);
879 for (i = 0; i < sky2->rx_pending; i++) {
880 struct ring_info *re = sky2->rx_ring + i;
883 pci_unmap_single(sky2->hw->pdev,
884 re->mapaddr, sky2->rx_bufsize,
892 /* Basic MII support */
893 static int sky2_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
895 struct mii_ioctl_data *data = if_mii(ifr);
896 struct sky2_port *sky2 = netdev_priv(dev);
897 struct sky2_hw *hw = sky2->hw;
898 int err = -EOPNOTSUPP;
900 if (!netif_running(dev))
901 return -ENODEV; /* Phy still in reset */
905 data->phy_id = PHY_ADDR_MARV;
911 spin_lock_bh(&sky2->phy_lock);
912 err = __gm_phy_read(hw, sky2->port, data->reg_num & 0x1f, &val);
913 spin_unlock_bh(&sky2->phy_lock);
920 if (!capable(CAP_NET_ADMIN))
923 spin_lock_bh(&sky2->phy_lock);
924 err = gm_phy_write(hw, sky2->port, data->reg_num & 0x1f,
926 spin_unlock_bh(&sky2->phy_lock);
932 #ifdef SKY2_VLAN_TAG_USED
933 static void sky2_vlan_rx_register(struct net_device *dev, struct vlan_group *grp)
935 struct sky2_port *sky2 = netdev_priv(dev);
936 struct sky2_hw *hw = sky2->hw;
937 u16 port = sky2->port;
939 spin_lock_bh(&sky2->tx_lock);
941 sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T), RX_VLAN_STRIP_ON);
942 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T), TX_VLAN_TAG_ON);
945 spin_unlock_bh(&sky2->tx_lock);
948 static void sky2_vlan_rx_kill_vid(struct net_device *dev, unsigned short vid)
950 struct sky2_port *sky2 = netdev_priv(dev);
951 struct sky2_hw *hw = sky2->hw;
952 u16 port = sky2->port;
954 spin_lock_bh(&sky2->tx_lock);
956 sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T), RX_VLAN_STRIP_OFF);
957 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T), TX_VLAN_TAG_OFF);
959 sky2->vlgrp->vlan_devices[vid] = NULL;
961 spin_unlock_bh(&sky2->tx_lock);
966 * It appears the hardware has a bug in the FIFO logic that
967 * cause it to hang if the FIFO gets overrun and the receive buffer
968 * is not 64 byte aligned. The buffer returned from netdev_alloc_skb is
969 * aligned except if slab debugging is enabled.
971 static inline struct sk_buff *sky2_alloc_skb(struct net_device *dev,
977 skb = __netdev_alloc_skb(dev, length + RX_SKB_ALIGN, gfp_mask);
979 unsigned long p = (unsigned long) skb->data;
980 skb_reserve(skb, ALIGN(p, RX_SKB_ALIGN) - p);
987 * Allocate and setup receiver buffer pool.
988 * In case of 64 bit dma, there are 2X as many list elements
989 * available as ring entries
990 * and need to reserve one list element so we don't wrap around.
992 static int sky2_rx_start(struct sky2_port *sky2)
994 struct sky2_hw *hw = sky2->hw;
995 unsigned rxq = rxqaddr[sky2->port];
999 sky2->rx_put = sky2->rx_next = 0;
1002 if (hw->chip_id == CHIP_ID_YUKON_EC_U && hw->chip_rev >= 2) {
1003 /* MAC Rx RAM Read is controlled by hardware */
1004 sky2_write32(hw, Q_ADDR(rxq, Q_F), F_M_RX_RAM_DIS);
1007 sky2_prefetch_init(hw, rxq, sky2->rx_le_map, RX_LE_SIZE - 1);
1009 rx_set_checksum(sky2);
1010 for (i = 0; i < sky2->rx_pending; i++) {
1011 struct ring_info *re = sky2->rx_ring + i;
1013 re->skb = sky2_alloc_skb(sky2->netdev, sky2->rx_bufsize,
1018 re->mapaddr = pci_map_single(hw->pdev, re->skb->data,
1019 sky2->rx_bufsize, PCI_DMA_FROMDEVICE);
1020 sky2_rx_add(sky2, re->mapaddr);
1025 * The receiver hangs if it receives frames larger than the
1026 * packet buffer. As a workaround, truncate oversize frames, but
1027 * the register is limited to 9 bits, so if you do frames > 2052
1028 * you better get the MTU right!
1030 thresh = (sky2->rx_bufsize - 8) / sizeof(u32);
1032 sky2_write32(hw, SK_REG(sky2->port, RX_GMF_CTRL_T), RX_TRUNC_OFF);
1034 sky2_write16(hw, SK_REG(sky2->port, RX_GMF_TR_THR), thresh);
1035 sky2_write32(hw, SK_REG(sky2->port, RX_GMF_CTRL_T), RX_TRUNC_ON);
1039 /* Tell chip about available buffers */
1040 sky2_write16(hw, Y2_QADDR(rxq, PREF_UNIT_PUT_IDX), sky2->rx_put);
1043 sky2_rx_clean(sky2);
1047 /* Bring up network interface. */
1048 static int sky2_up(struct net_device *dev)
1050 struct sky2_port *sky2 = netdev_priv(dev);
1051 struct sky2_hw *hw = sky2->hw;
1052 unsigned port = sky2->port;
1053 u32 ramsize, rxspace, imask;
1054 int cap, err = -ENOMEM;
1055 struct net_device *otherdev = hw->dev[sky2->port^1];
1058 * On dual port PCI-X card, there is an problem where status
1059 * can be received out of order due to split transactions
1061 if (otherdev && netif_running(otherdev) &&
1062 (cap = pci_find_capability(hw->pdev, PCI_CAP_ID_PCIX))) {
1063 struct sky2_port *osky2 = netdev_priv(otherdev);
1066 cmd = sky2_pci_read16(hw, cap + PCI_X_CMD);
1067 cmd &= ~PCI_X_CMD_MAX_SPLIT;
1068 sky2_pci_write16(hw, cap + PCI_X_CMD, cmd);
1074 if (netif_msg_ifup(sky2))
1075 printk(KERN_INFO PFX "%s: enabling interface\n", dev->name);
1077 /* must be power of 2 */
1078 sky2->tx_le = pci_alloc_consistent(hw->pdev,
1080 sizeof(struct sky2_tx_le),
1085 sky2->tx_ring = kcalloc(TX_RING_SIZE, sizeof(struct tx_ring_info),
1089 sky2->tx_prod = sky2->tx_cons = 0;
1091 sky2->rx_le = pci_alloc_consistent(hw->pdev, RX_LE_BYTES,
1095 memset(sky2->rx_le, 0, RX_LE_BYTES);
1097 sky2->rx_ring = kcalloc(sky2->rx_pending, sizeof(struct ring_info),
1102 sky2_phy_power(hw, port, 1);
1104 sky2_mac_init(hw, port);
1106 /* Determine available ram buffer space (in 4K blocks).
1107 * Note: not sure about the FE setting below yet
1109 if (hw->chip_id == CHIP_ID_YUKON_FE)
1112 ramsize = sky2_read8(hw, B2_E_0);
1114 /* Give transmitter one third (rounded up) */
1115 rxspace = ramsize - (ramsize + 2) / 3;
1117 sky2_ramset(hw, rxqaddr[port], 0, rxspace);
1118 sky2_ramset(hw, txqaddr[port], rxspace, ramsize);
1120 /* Make sure SyncQ is disabled */
1121 sky2_write8(hw, RB_ADDR(port == 0 ? Q_XS1 : Q_XS2, RB_CTRL),
1124 sky2_qset(hw, txqaddr[port]);
1126 /* Set almost empty threshold */
1127 if (hw->chip_id == CHIP_ID_YUKON_EC_U
1128 && hw->chip_rev == CHIP_REV_YU_EC_U_A0)
1129 sky2_write16(hw, Q_ADDR(txqaddr[port], Q_AL), 0x1a0);
1131 sky2_prefetch_init(hw, txqaddr[port], sky2->tx_le_map,
1134 err = sky2_rx_start(sky2);
1138 /* Enable interrupts from phy/mac for port */
1139 imask = sky2_read32(hw, B0_IMSK);
1140 imask |= portirq_msk[port];
1141 sky2_write32(hw, B0_IMSK, imask);
1147 pci_free_consistent(hw->pdev, RX_LE_BYTES,
1148 sky2->rx_le, sky2->rx_le_map);
1152 pci_free_consistent(hw->pdev,
1153 TX_RING_SIZE * sizeof(struct sky2_tx_le),
1154 sky2->tx_le, sky2->tx_le_map);
1157 kfree(sky2->tx_ring);
1158 kfree(sky2->rx_ring);
1160 sky2->tx_ring = NULL;
1161 sky2->rx_ring = NULL;
1165 /* Modular subtraction in ring */
1166 static inline int tx_dist(unsigned tail, unsigned head)
1168 return (head - tail) & (TX_RING_SIZE - 1);
1171 /* Number of list elements available for next tx */
1172 static inline int tx_avail(const struct sky2_port *sky2)
1174 return sky2->tx_pending - tx_dist(sky2->tx_cons, sky2->tx_prod);
1177 /* Estimate of number of transmit list elements required */
1178 static unsigned tx_le_req(const struct sk_buff *skb)
1182 count = sizeof(dma_addr_t) / sizeof(u32);
1183 count += skb_shinfo(skb)->nr_frags * count;
1185 if (skb_is_gso(skb))
1188 if (skb->ip_summed == CHECKSUM_PARTIAL)
1195 * Put one packet in ring for transmit.
1196 * A single packet can generate multiple list elements, and
1197 * the number of ring elements will probably be less than the number
1198 * of list elements used.
1200 * No BH disabling for tx_lock here (like tg3)
1202 static int sky2_xmit_frame(struct sk_buff *skb, struct net_device *dev)
1204 struct sky2_port *sky2 = netdev_priv(dev);
1205 struct sky2_hw *hw = sky2->hw;
1206 struct sky2_tx_le *le = NULL;
1207 struct tx_ring_info *re;
1214 /* No BH disabling for tx_lock here. We are running in BH disabled
1215 * context and TX reclaim runs via poll inside of a software
1216 * interrupt, and no related locks in IRQ processing.
1218 if (!spin_trylock(&sky2->tx_lock))
1219 return NETDEV_TX_LOCKED;
1221 if (unlikely(tx_avail(sky2) < tx_le_req(skb))) {
1222 /* There is a known but harmless race with lockless tx
1223 * and netif_stop_queue.
1225 if (!netif_queue_stopped(dev)) {
1226 netif_stop_queue(dev);
1227 if (net_ratelimit())
1228 printk(KERN_WARNING PFX "%s: ring full when queue awake!\n",
1231 spin_unlock(&sky2->tx_lock);
1233 return NETDEV_TX_BUSY;
1236 if (unlikely(netif_msg_tx_queued(sky2)))
1237 printk(KERN_DEBUG "%s: tx queued, slot %u, len %d\n",
1238 dev->name, sky2->tx_prod, skb->len);
1240 len = skb_headlen(skb);
1241 mapping = pci_map_single(hw->pdev, skb->data, len, PCI_DMA_TODEVICE);
1242 addr64 = high32(mapping);
1244 re = sky2->tx_ring + sky2->tx_prod;
1246 /* Send high bits if changed or crosses boundary */
1247 if (addr64 != sky2->tx_addr64 || high32(mapping + len) != sky2->tx_addr64) {
1248 le = get_tx_le(sky2);
1249 le->addr = cpu_to_le32(addr64);
1251 le->opcode = OP_ADDR64 | HW_OWNER;
1252 sky2->tx_addr64 = high32(mapping + len);
1255 /* Check for TCP Segmentation Offload */
1256 mss = skb_shinfo(skb)->gso_size;
1258 mss += ((skb->h.th->doff - 5) * 4); /* TCP options */
1259 mss += (skb->nh.iph->ihl * 4) + sizeof(struct tcphdr);
1262 if (mss != sky2->tx_last_mss) {
1263 le = get_tx_le(sky2);
1264 le->addr = cpu_to_le32(mss);
1265 le->opcode = OP_LRGLEN | HW_OWNER;
1267 sky2->tx_last_mss = mss;
1272 #ifdef SKY2_VLAN_TAG_USED
1273 /* Add VLAN tag, can piggyback on LRGLEN or ADDR64 */
1274 if (sky2->vlgrp && vlan_tx_tag_present(skb)) {
1276 le = get_tx_le(sky2);
1278 le->opcode = OP_VLAN|HW_OWNER;
1281 le->opcode |= OP_VLAN;
1282 le->length = cpu_to_be16(vlan_tx_tag_get(skb));
1287 /* Handle TCP checksum offload */
1288 if (skb->ip_summed == CHECKSUM_PARTIAL) {
1289 unsigned offset = skb->h.raw - skb->data;
1292 tcpsum = offset << 16; /* sum start */
1293 tcpsum |= offset + skb->csum; /* sum write */
1295 ctrl = CALSUM | WR_SUM | INIT_SUM | LOCK_SUM;
1296 if (skb->nh.iph->protocol == IPPROTO_UDP)
1299 if (tcpsum != sky2->tx_tcpsum) {
1300 sky2->tx_tcpsum = tcpsum;
1302 le = get_tx_le(sky2);
1303 le->addr = cpu_to_le32(tcpsum);
1304 le->length = 0; /* initial checksum value */
1305 le->ctrl = 1; /* one packet */
1306 le->opcode = OP_TCPLISW | HW_OWNER;
1310 le = get_tx_le(sky2);
1311 le->addr = cpu_to_le32((u32) mapping);
1312 le->length = cpu_to_le16(len);
1314 le->opcode = mss ? (OP_LARGESEND | HW_OWNER) : (OP_PACKET | HW_OWNER);
1316 /* Record the transmit mapping info */
1318 pci_unmap_addr_set(re, mapaddr, mapping);
1320 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
1321 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
1322 struct tx_ring_info *fre;
1324 mapping = pci_map_page(hw->pdev, frag->page, frag->page_offset,
1325 frag->size, PCI_DMA_TODEVICE);
1326 addr64 = high32(mapping);
1327 if (addr64 != sky2->tx_addr64) {
1328 le = get_tx_le(sky2);
1329 le->addr = cpu_to_le32(addr64);
1331 le->opcode = OP_ADDR64 | HW_OWNER;
1332 sky2->tx_addr64 = addr64;
1335 le = get_tx_le(sky2);
1336 le->addr = cpu_to_le32((u32) mapping);
1337 le->length = cpu_to_le16(frag->size);
1339 le->opcode = OP_BUFFER | HW_OWNER;
1342 + RING_NEXT((re - sky2->tx_ring) + i, TX_RING_SIZE);
1343 pci_unmap_addr_set(fre, mapaddr, mapping);
1346 re->idx = sky2->tx_prod;
1349 if (tx_avail(sky2) <= MAX_SKB_TX_LE)
1350 netif_stop_queue(dev);
1352 sky2_put_idx(hw, txqaddr[sky2->port], sky2->tx_prod);
1354 spin_unlock(&sky2->tx_lock);
1356 dev->trans_start = jiffies;
1357 return NETDEV_TX_OK;
1361 * Free ring elements from starting at tx_cons until "done"
1363 * NB: the hardware will tell us about partial completion of multi-part
1364 * buffers; these are deferred until completion.
1366 static void sky2_tx_complete(struct sky2_port *sky2, u16 done)
1368 struct net_device *dev = sky2->netdev;
1369 struct pci_dev *pdev = sky2->hw->pdev;
1373 BUG_ON(done >= TX_RING_SIZE);
1375 if (unlikely(netif_msg_tx_done(sky2)))
1376 printk(KERN_DEBUG "%s: tx done, up to %u\n",
1379 for (put = sky2->tx_cons; put != done; put = nxt) {
1380 struct tx_ring_info *re = sky2->tx_ring + put;
1381 struct sk_buff *skb = re->skb;
1384 BUG_ON(nxt >= TX_RING_SIZE);
1385 prefetch(sky2->tx_ring + nxt);
1387 /* Check for partial status */
1388 if (tx_dist(put, done) < tx_dist(put, nxt))
1392 pci_unmap_single(pdev, pci_unmap_addr(re, mapaddr),
1393 skb_headlen(skb), PCI_DMA_TODEVICE);
1395 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
1396 struct tx_ring_info *fre;
1397 fre = sky2->tx_ring + RING_NEXT(put + i, TX_RING_SIZE);
1398 pci_unmap_page(pdev, pci_unmap_addr(fre, mapaddr),
1399 skb_shinfo(skb)->frags[i].size,
1406 sky2->tx_cons = put;
1407 if (tx_avail(sky2) > MAX_SKB_TX_LE + 4)
1408 netif_wake_queue(dev);
1411 /* Cleanup all untransmitted buffers, assume transmitter not running */
1412 static void sky2_tx_clean(struct sky2_port *sky2)
1414 spin_lock_bh(&sky2->tx_lock);
1415 sky2_tx_complete(sky2, sky2->tx_prod);
1416 spin_unlock_bh(&sky2->tx_lock);
1419 /* Network shutdown */
1420 static int sky2_down(struct net_device *dev)
1422 struct sky2_port *sky2 = netdev_priv(dev);
1423 struct sky2_hw *hw = sky2->hw;
1424 unsigned port = sky2->port;
1428 /* Never really got started! */
1432 if (netif_msg_ifdown(sky2))
1433 printk(KERN_INFO PFX "%s: disabling interface\n", dev->name);
1435 /* Stop more packets from being queued */
1436 netif_stop_queue(dev);
1438 sky2_gmac_reset(hw, port);
1440 /* Stop transmitter */
1441 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), BMU_STOP);
1442 sky2_read32(hw, Q_ADDR(txqaddr[port], Q_CSR));
1444 sky2_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL),
1445 RB_RST_SET | RB_DIS_OP_MD);
1447 /* WA for dev. #4.209 */
1448 if (hw->chip_id == CHIP_ID_YUKON_EC_U
1449 && hw->chip_rev == CHIP_REV_YU_EC_U_A1)
1450 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T),
1451 sky2->speed != SPEED_1000 ?
1452 TX_STFW_ENA : TX_STFW_DIS);
1454 ctrl = gma_read16(hw, port, GM_GP_CTRL);
1455 ctrl &= ~(GM_GPCR_TX_ENA | GM_GPCR_RX_ENA);
1456 gma_write16(hw, port, GM_GP_CTRL, ctrl);
1458 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET);
1460 /* Workaround shared GMAC reset */
1461 if (!(hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0
1462 && port == 0 && hw->dev[1] && netif_running(hw->dev[1])))
1463 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_SET);
1465 /* Disable Force Sync bit and Enable Alloc bit */
1466 sky2_write8(hw, SK_REG(port, TXA_CTRL),
1467 TXA_DIS_FSYNC | TXA_DIS_ALLOC | TXA_STOP_RC);
1469 /* Stop Interval Timer and Limit Counter of Tx Arbiter */
1470 sky2_write32(hw, SK_REG(port, TXA_ITI_INI), 0L);
1471 sky2_write32(hw, SK_REG(port, TXA_LIM_INI), 0L);
1473 /* Reset the PCI FIFO of the async Tx queue */
1474 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR),
1475 BMU_RST_SET | BMU_FIFO_RST);
1477 /* Reset the Tx prefetch units */
1478 sky2_write32(hw, Y2_QADDR(txqaddr[port], PREF_UNIT_CTRL),
1481 sky2_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL), RB_RST_SET);
1485 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_SET);
1486 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_SET);
1488 /* Disable port IRQ */
1489 imask = sky2_read32(hw, B0_IMSK);
1490 imask &= ~portirq_msk[port];
1491 sky2_write32(hw, B0_IMSK, imask);
1493 sky2_phy_power(hw, port, 0);
1495 /* turn off LED's */
1496 sky2_write16(hw, B0_Y2LED, LED_STAT_OFF);
1498 synchronize_irq(hw->pdev->irq);
1500 sky2_tx_clean(sky2);
1501 sky2_rx_clean(sky2);
1503 pci_free_consistent(hw->pdev, RX_LE_BYTES,
1504 sky2->rx_le, sky2->rx_le_map);
1505 kfree(sky2->rx_ring);
1507 pci_free_consistent(hw->pdev,
1508 TX_RING_SIZE * sizeof(struct sky2_tx_le),
1509 sky2->tx_le, sky2->tx_le_map);
1510 kfree(sky2->tx_ring);
1515 sky2->rx_ring = NULL;
1516 sky2->tx_ring = NULL;
1521 static u16 sky2_phy_speed(const struct sky2_hw *hw, u16 aux)
1523 if (!sky2_is_copper(hw))
1526 if (hw->chip_id == CHIP_ID_YUKON_FE)
1527 return (aux & PHY_M_PS_SPEED_100) ? SPEED_100 : SPEED_10;
1529 switch (aux & PHY_M_PS_SPEED_MSK) {
1530 case PHY_M_PS_SPEED_1000:
1532 case PHY_M_PS_SPEED_100:
1539 static void sky2_link_up(struct sky2_port *sky2)
1541 struct sky2_hw *hw = sky2->hw;
1542 unsigned port = sky2->port;
1546 reg = gma_read16(hw, port, GM_GP_CTRL);
1547 reg |= GM_GPCR_RX_ENA | GM_GPCR_TX_ENA;
1548 gma_write16(hw, port, GM_GP_CTRL, reg);
1550 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_DEF_MSK);
1552 netif_carrier_on(sky2->netdev);
1553 netif_wake_queue(sky2->netdev);
1555 /* Turn on link LED */
1556 sky2_write8(hw, SK_REG(port, LNK_LED_REG),
1557 LINKLED_ON | LINKLED_BLINK_OFF | LINKLED_LINKSYNC_OFF);
1559 if (hw->chip_id == CHIP_ID_YUKON_XL || hw->chip_id == CHIP_ID_YUKON_EC_U) {
1560 u16 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
1561 u16 led = PHY_M_LEDC_LOS_CTRL(1); /* link active */
1563 switch(sky2->speed) {
1565 led |= PHY_M_LEDC_INIT_CTRL(7);
1569 led |= PHY_M_LEDC_STA1_CTRL(7);
1573 led |= PHY_M_LEDC_STA0_CTRL(7);
1577 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
1578 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, led);
1579 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
1582 if (netif_msg_link(sky2))
1583 printk(KERN_INFO PFX
1584 "%s: Link is up at %d Mbps, %s duplex, flow control %s\n",
1585 sky2->netdev->name, sky2->speed,
1586 sky2->duplex == DUPLEX_FULL ? "full" : "half",
1587 (sky2->tx_pause && sky2->rx_pause) ? "both" :
1588 sky2->tx_pause ? "tx" : sky2->rx_pause ? "rx" : "none");
1591 static void sky2_link_down(struct sky2_port *sky2)
1593 struct sky2_hw *hw = sky2->hw;
1594 unsigned port = sky2->port;
1597 gm_phy_write(hw, port, PHY_MARV_INT_MASK, 0);
1599 reg = gma_read16(hw, port, GM_GP_CTRL);
1600 reg &= ~(GM_GPCR_RX_ENA | GM_GPCR_TX_ENA);
1601 gma_write16(hw, port, GM_GP_CTRL, reg);
1603 if (sky2->rx_pause && !sky2->tx_pause) {
1604 /* restore Asymmetric Pause bit */
1605 gm_phy_write(hw, port, PHY_MARV_AUNE_ADV,
1606 gm_phy_read(hw, port, PHY_MARV_AUNE_ADV)
1610 netif_carrier_off(sky2->netdev);
1611 netif_stop_queue(sky2->netdev);
1613 /* Turn on link LED */
1614 sky2_write8(hw, SK_REG(port, LNK_LED_REG), LINKLED_OFF);
1616 if (netif_msg_link(sky2))
1617 printk(KERN_INFO PFX "%s: Link is down.\n", sky2->netdev->name);
1619 sky2_phy_init(hw, port);
1622 static int sky2_autoneg_done(struct sky2_port *sky2, u16 aux)
1624 struct sky2_hw *hw = sky2->hw;
1625 unsigned port = sky2->port;
1628 lpa = gm_phy_read(hw, port, PHY_MARV_AUNE_LP);
1630 if (lpa & PHY_M_AN_RF) {
1631 printk(KERN_ERR PFX "%s: remote fault", sky2->netdev->name);
1635 if (!(aux & PHY_M_PS_SPDUP_RES)) {
1636 printk(KERN_ERR PFX "%s: speed/duplex mismatch",
1637 sky2->netdev->name);
1641 sky2->speed = sky2_phy_speed(hw, aux);
1642 if (sky2->speed == SPEED_1000) {
1643 u16 ctl2 = gm_phy_read(hw, port, PHY_MARV_1000T_CTRL);
1644 u16 lpa2 = gm_phy_read(hw, port, PHY_MARV_1000T_STAT);
1645 if (lpa2 & PHY_B_1000S_MSF) {
1646 printk(KERN_ERR PFX "%s: master/slave fault",
1647 sky2->netdev->name);
1651 if ((ctl2 & PHY_M_1000C_AFD) && (lpa2 & PHY_B_1000S_LP_FD))
1652 sky2->duplex = DUPLEX_FULL;
1654 sky2->duplex = DUPLEX_HALF;
1656 u16 adv = gm_phy_read(hw, port, PHY_MARV_AUNE_ADV);
1657 if ((aux & adv) & PHY_AN_FULL)
1658 sky2->duplex = DUPLEX_FULL;
1660 sky2->duplex = DUPLEX_HALF;
1663 /* Pause bits are offset (9..8) */
1664 if (hw->chip_id == CHIP_ID_YUKON_XL || hw->chip_id == CHIP_ID_YUKON_EC_U)
1667 sky2->rx_pause = (aux & PHY_M_PS_RX_P_EN) != 0;
1668 sky2->tx_pause = (aux & PHY_M_PS_TX_P_EN) != 0;
1670 if (sky2->duplex == DUPLEX_HALF && sky2->speed != SPEED_1000
1671 && hw->chip_id != CHIP_ID_YUKON_EC_U)
1672 sky2->rx_pause = sky2->tx_pause = 0;
1674 if (sky2->rx_pause || sky2->tx_pause)
1675 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON);
1677 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
1682 /* Interrupt from PHY */
1683 static void sky2_phy_intr(struct sky2_hw *hw, unsigned port)
1685 struct net_device *dev = hw->dev[port];
1686 struct sky2_port *sky2 = netdev_priv(dev);
1687 u16 istatus, phystat;
1689 spin_lock(&sky2->phy_lock);
1690 istatus = gm_phy_read(hw, port, PHY_MARV_INT_STAT);
1691 phystat = gm_phy_read(hw, port, PHY_MARV_PHY_STAT);
1693 if (!netif_running(dev))
1696 if (netif_msg_intr(sky2))
1697 printk(KERN_INFO PFX "%s: phy interrupt status 0x%x 0x%x\n",
1698 sky2->netdev->name, istatus, phystat);
1700 if (sky2->autoneg == AUTONEG_ENABLE && (istatus & PHY_M_IS_AN_COMPL)) {
1701 if (sky2_autoneg_done(sky2, phystat) == 0)
1706 if (istatus & PHY_M_IS_LSP_CHANGE)
1707 sky2->speed = sky2_phy_speed(hw, phystat);
1709 if (istatus & PHY_M_IS_DUP_CHANGE)
1711 (phystat & PHY_M_PS_FULL_DUP) ? DUPLEX_FULL : DUPLEX_HALF;
1713 if (istatus & PHY_M_IS_LST_CHANGE) {
1714 if (phystat & PHY_M_PS_LINK_UP)
1717 sky2_link_down(sky2);
1720 spin_unlock(&sky2->phy_lock);
1724 /* Transmit timeout is only called if we are running, carries is up
1725 * and tx queue is full (stopped).
1727 static void sky2_tx_timeout(struct net_device *dev)
1729 struct sky2_port *sky2 = netdev_priv(dev);
1730 struct sky2_hw *hw = sky2->hw;
1731 unsigned txq = txqaddr[sky2->port];
1734 if (netif_msg_timer(sky2))
1735 printk(KERN_ERR PFX "%s: tx timeout\n", dev->name);
1737 report = sky2_read16(hw, sky2->port == 0 ? STAT_TXA1_RIDX : STAT_TXA2_RIDX);
1738 done = sky2_read16(hw, Q_ADDR(txq, Q_DONE));
1740 printk(KERN_DEBUG PFX "%s: transmit ring %u .. %u report=%u done=%u\n",
1742 sky2->tx_cons, sky2->tx_prod, report, done);
1744 if (report != done) {
1745 printk(KERN_INFO PFX "status burst pending (irq moderation?)\n");
1747 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_STOP);
1748 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_START);
1749 } else if (report != sky2->tx_cons) {
1750 printk(KERN_INFO PFX "status report lost?\n");
1752 spin_lock_bh(&sky2->tx_lock);
1753 sky2_tx_complete(sky2, report);
1754 spin_unlock_bh(&sky2->tx_lock);
1756 printk(KERN_INFO PFX "hardware hung? flushing\n");
1758 sky2_write32(hw, Q_ADDR(txq, Q_CSR), BMU_STOP);
1759 sky2_write32(hw, Y2_QADDR(txq, PREF_UNIT_CTRL), PREF_UNIT_RST_SET);
1761 sky2_tx_clean(sky2);
1764 sky2_prefetch_init(hw, txq, sky2->tx_le_map, TX_RING_SIZE - 1);
1769 /* Want receive buffer size to be multiple of 64 bits
1770 * and incl room for vlan and truncation
1772 static inline unsigned sky2_buf_size(int mtu)
1774 return ALIGN(mtu + ETH_HLEN + VLAN_HLEN, 8) + 8;
1777 static int sky2_change_mtu(struct net_device *dev, int new_mtu)
1779 struct sky2_port *sky2 = netdev_priv(dev);
1780 struct sky2_hw *hw = sky2->hw;
1785 if (new_mtu < ETH_ZLEN || new_mtu > ETH_JUMBO_MTU)
1788 if (hw->chip_id == CHIP_ID_YUKON_EC_U && new_mtu > ETH_DATA_LEN)
1791 if (!netif_running(dev)) {
1796 imask = sky2_read32(hw, B0_IMSK);
1797 sky2_write32(hw, B0_IMSK, 0);
1799 dev->trans_start = jiffies; /* prevent tx timeout */
1800 netif_stop_queue(dev);
1801 netif_poll_disable(hw->dev[0]);
1803 synchronize_irq(hw->pdev->irq);
1805 ctl = gma_read16(hw, sky2->port, GM_GP_CTRL);
1806 gma_write16(hw, sky2->port, GM_GP_CTRL, ctl & ~GM_GPCR_RX_ENA);
1808 sky2_rx_clean(sky2);
1811 sky2->rx_bufsize = sky2_buf_size(new_mtu);
1812 mode = DATA_BLIND_VAL(DATA_BLIND_DEF) |
1813 GM_SMOD_VLAN_ENA | IPG_DATA_VAL(IPG_DATA_DEF);
1815 if (dev->mtu > ETH_DATA_LEN)
1816 mode |= GM_SMOD_JUMBO_ENA;
1818 gma_write16(hw, sky2->port, GM_SERIAL_MODE, mode);
1820 sky2_write8(hw, RB_ADDR(rxqaddr[sky2->port], RB_CTRL), RB_ENA_OP_MD);
1822 err = sky2_rx_start(sky2);
1823 sky2_write32(hw, B0_IMSK, imask);
1828 gma_write16(hw, sky2->port, GM_GP_CTRL, ctl);
1830 netif_poll_enable(hw->dev[0]);
1831 netif_wake_queue(dev);
1838 * Receive one packet.
1839 * For small packets or errors, just reuse existing skb.
1840 * For larger packets, get new buffer.
1842 static struct sk_buff *sky2_receive(struct net_device *dev,
1843 u16 length, u32 status)
1845 struct sky2_port *sky2 = netdev_priv(dev);
1846 struct ring_info *re = sky2->rx_ring + sky2->rx_next;
1847 struct sk_buff *skb = NULL;
1849 if (unlikely(netif_msg_rx_status(sky2)))
1850 printk(KERN_DEBUG PFX "%s: rx slot %u status 0x%x len %d\n",
1851 dev->name, sky2->rx_next, status, length);
1853 sky2->rx_next = (sky2->rx_next + 1) % sky2->rx_pending;
1854 prefetch(sky2->rx_ring + sky2->rx_next);
1856 if (status & GMR_FS_ANY_ERR)
1859 if (!(status & GMR_FS_RX_OK))
1862 if (length > dev->mtu + ETH_HLEN)
1865 if (length < copybreak) {
1866 skb = netdev_alloc_skb(dev, length + 2);
1870 skb_reserve(skb, 2);
1871 pci_dma_sync_single_for_cpu(sky2->hw->pdev, re->mapaddr,
1872 length, PCI_DMA_FROMDEVICE);
1873 memcpy(skb->data, re->skb->data, length);
1874 skb->ip_summed = re->skb->ip_summed;
1875 skb->csum = re->skb->csum;
1876 pci_dma_sync_single_for_device(sky2->hw->pdev, re->mapaddr,
1877 length, PCI_DMA_FROMDEVICE);
1879 struct sk_buff *nskb;
1881 nskb = sky2_alloc_skb(dev, sky2->rx_bufsize, GFP_ATOMIC);
1887 pci_unmap_single(sky2->hw->pdev, re->mapaddr,
1888 sky2->rx_bufsize, PCI_DMA_FROMDEVICE);
1889 prefetch(skb->data);
1891 re->mapaddr = pci_map_single(sky2->hw->pdev, nskb->data,
1892 sky2->rx_bufsize, PCI_DMA_FROMDEVICE);
1895 skb_put(skb, length);
1897 re->skb->ip_summed = CHECKSUM_NONE;
1898 sky2_rx_add(sky2, re->mapaddr);
1903 ++sky2->net_stats.rx_over_errors;
1907 ++sky2->net_stats.rx_errors;
1909 if (netif_msg_rx_err(sky2) && net_ratelimit())
1910 printk(KERN_INFO PFX "%s: rx error, status 0x%x length %d\n",
1911 dev->name, status, length);
1913 if (status & (GMR_FS_LONG_ERR | GMR_FS_UN_SIZE))
1914 sky2->net_stats.rx_length_errors++;
1915 if (status & GMR_FS_FRAGMENT)
1916 sky2->net_stats.rx_frame_errors++;
1917 if (status & GMR_FS_CRC_ERR)
1918 sky2->net_stats.rx_crc_errors++;
1919 if (status & GMR_FS_RX_FF_OV)
1920 sky2->net_stats.rx_fifo_errors++;
1925 /* Transmit complete */
1926 static inline void sky2_tx_done(struct net_device *dev, u16 last)
1928 struct sky2_port *sky2 = netdev_priv(dev);
1930 if (netif_running(dev)) {
1931 spin_lock(&sky2->tx_lock);
1932 sky2_tx_complete(sky2, last);
1933 spin_unlock(&sky2->tx_lock);
1937 /* Process status response ring */
1938 static int sky2_status_intr(struct sky2_hw *hw, int to_do)
1940 struct sky2_port *sky2;
1942 unsigned buf_write[2] = { 0, 0 };
1943 u16 hwidx = sky2_read16(hw, STAT_PUT_IDX);
1947 while (hw->st_idx != hwidx) {
1948 struct sky2_status_le *le = hw->st_le + hw->st_idx;
1949 struct net_device *dev;
1950 struct sk_buff *skb;
1954 hw->st_idx = RING_NEXT(hw->st_idx, STATUS_RING_SIZE);
1956 BUG_ON(le->link >= 2);
1957 dev = hw->dev[le->link];
1959 sky2 = netdev_priv(dev);
1960 length = le16_to_cpu(le->length);
1961 status = le32_to_cpu(le->status);
1963 switch (le->opcode & ~HW_OWNER) {
1965 skb = sky2_receive(dev, length, status);
1969 skb->protocol = eth_type_trans(skb, dev);
1970 dev->last_rx = jiffies;
1972 #ifdef SKY2_VLAN_TAG_USED
1973 if (sky2->vlgrp && (status & GMR_FS_VLAN)) {
1974 vlan_hwaccel_receive_skb(skb,
1976 be16_to_cpu(sky2->rx_tag));
1979 netif_receive_skb(skb);
1981 /* Update receiver after 16 frames */
1982 if (++buf_write[le->link] == RX_BUF_WRITE) {
1983 sky2_put_idx(hw, rxqaddr[le->link],
1985 buf_write[le->link] = 0;
1988 /* Stop after net poll weight */
1989 if (++work_done >= to_do)
1993 #ifdef SKY2_VLAN_TAG_USED
1995 sky2->rx_tag = length;
1999 sky2->rx_tag = length;
2003 skb = sky2->rx_ring[sky2->rx_next].skb;
2004 skb->ip_summed = CHECKSUM_COMPLETE;
2005 skb->csum = status & 0xffff;
2009 /* TX index reports status for both ports */
2010 BUILD_BUG_ON(TX_RING_SIZE > 0x1000);
2011 sky2_tx_done(hw->dev[0], status & 0xfff);
2013 sky2_tx_done(hw->dev[1],
2014 ((status >> 24) & 0xff)
2015 | (u16)(length & 0xf) << 8);
2019 if (net_ratelimit())
2020 printk(KERN_WARNING PFX
2021 "unknown status opcode 0x%x\n", le->opcode);
2026 /* Fully processed status ring so clear irq */
2027 sky2_write32(hw, STAT_CTRL, SC_STAT_CLR_IRQ);
2031 sky2 = netdev_priv(hw->dev[0]);
2032 sky2_put_idx(hw, Q_R1, sky2->rx_put);
2036 sky2 = netdev_priv(hw->dev[1]);
2037 sky2_put_idx(hw, Q_R2, sky2->rx_put);
2043 static void sky2_hw_error(struct sky2_hw *hw, unsigned port, u32 status)
2045 struct net_device *dev = hw->dev[port];
2047 if (net_ratelimit())
2048 printk(KERN_INFO PFX "%s: hw error interrupt status 0x%x\n",
2051 if (status & Y2_IS_PAR_RD1) {
2052 if (net_ratelimit())
2053 printk(KERN_ERR PFX "%s: ram data read parity error\n",
2056 sky2_write16(hw, RAM_BUFFER(port, B3_RI_CTRL), RI_CLR_RD_PERR);
2059 if (status & Y2_IS_PAR_WR1) {
2060 if (net_ratelimit())
2061 printk(KERN_ERR PFX "%s: ram data write parity error\n",
2064 sky2_write16(hw, RAM_BUFFER(port, B3_RI_CTRL), RI_CLR_WR_PERR);
2067 if (status & Y2_IS_PAR_MAC1) {
2068 if (net_ratelimit())
2069 printk(KERN_ERR PFX "%s: MAC parity error\n", dev->name);
2070 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_CLI_TX_PE);
2073 if (status & Y2_IS_PAR_RX1) {
2074 if (net_ratelimit())
2075 printk(KERN_ERR PFX "%s: RX parity error\n", dev->name);
2076 sky2_write32(hw, Q_ADDR(rxqaddr[port], Q_CSR), BMU_CLR_IRQ_PAR);
2079 if (status & Y2_IS_TCP_TXA1) {
2080 if (net_ratelimit())
2081 printk(KERN_ERR PFX "%s: TCP segmentation error\n",
2083 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), BMU_CLR_IRQ_TCP);
2087 static void sky2_hw_intr(struct sky2_hw *hw)
2089 u32 status = sky2_read32(hw, B0_HWE_ISRC);
2091 if (status & Y2_IS_TIST_OV)
2092 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ);
2094 if (status & (Y2_IS_MST_ERR | Y2_IS_IRQ_STAT)) {
2097 pci_err = sky2_pci_read16(hw, PCI_STATUS);
2098 if (net_ratelimit())
2099 printk(KERN_ERR PFX "%s: pci hw error (0x%x)\n",
2100 pci_name(hw->pdev), pci_err);
2102 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
2103 sky2_pci_write16(hw, PCI_STATUS,
2104 pci_err | PCI_STATUS_ERROR_BITS);
2105 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
2108 if (status & Y2_IS_PCI_EXP) {
2109 /* PCI-Express uncorrectable Error occurred */
2112 pex_err = sky2_pci_read32(hw,
2113 hw->err_cap + PCI_ERR_UNCOR_STATUS);
2115 if (net_ratelimit())
2116 printk(KERN_ERR PFX "%s: pci express error (0x%x)\n",
2117 pci_name(hw->pdev), pex_err);
2119 /* clear the interrupt */
2120 sky2_write32(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
2121 sky2_pci_write32(hw,
2122 hw->err_cap + PCI_ERR_UNCOR_STATUS,
2124 sky2_write32(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
2127 /* In case of fatal error mask off to keep from getting stuck */
2128 if (pex_err & (PCI_ERR_UNC_POISON_TLP | PCI_ERR_UNC_FCP
2129 | PCI_ERR_UNC_DLP)) {
2130 u32 hwmsk = sky2_read32(hw, B0_HWE_IMSK);
2131 hwmsk &= ~Y2_IS_PCI_EXP;
2132 sky2_write32(hw, B0_HWE_IMSK, hwmsk);
2137 if (status & Y2_HWE_L1_MASK)
2138 sky2_hw_error(hw, 0, status);
2140 if (status & Y2_HWE_L1_MASK)
2141 sky2_hw_error(hw, 1, status);
2144 static void sky2_mac_intr(struct sky2_hw *hw, unsigned port)
2146 struct net_device *dev = hw->dev[port];
2147 struct sky2_port *sky2 = netdev_priv(dev);
2148 u8 status = sky2_read8(hw, SK_REG(port, GMAC_IRQ_SRC));
2150 if (netif_msg_intr(sky2))
2151 printk(KERN_INFO PFX "%s: mac interrupt status 0x%x\n",
2154 if (status & GM_IS_RX_FF_OR) {
2155 ++sky2->net_stats.rx_fifo_errors;
2156 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_CLI_RX_FO);
2159 if (status & GM_IS_TX_FF_UR) {
2160 ++sky2->net_stats.tx_fifo_errors;
2161 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_CLI_TX_FU);
2165 /* This should never happen it is a fatal situation */
2166 static void sky2_descriptor_error(struct sky2_hw *hw, unsigned port,
2167 const char *rxtx, u32 mask)
2169 struct net_device *dev = hw->dev[port];
2170 struct sky2_port *sky2 = netdev_priv(dev);
2173 printk(KERN_ERR PFX "%s: %s descriptor error (hardware problem)\n",
2174 dev ? dev->name : "<not registered>", rxtx);
2176 imask = sky2_read32(hw, B0_IMSK);
2178 sky2_write32(hw, B0_IMSK, imask);
2181 spin_lock(&sky2->phy_lock);
2182 sky2_link_down(sky2);
2183 spin_unlock(&sky2->phy_lock);
2187 /* If idle then force a fake soft NAPI poll once a second
2188 * to work around cases where sharing an edge triggered interrupt.
2190 static inline void sky2_idle_start(struct sky2_hw *hw)
2192 if (idle_timeout > 0)
2193 mod_timer(&hw->idle_timer,
2194 jiffies + msecs_to_jiffies(idle_timeout));
2197 static void sky2_idle(unsigned long arg)
2199 struct sky2_hw *hw = (struct sky2_hw *) arg;
2200 struct net_device *dev = hw->dev[0];
2202 if (__netif_rx_schedule_prep(dev))
2203 __netif_rx_schedule(dev);
2205 mod_timer(&hw->idle_timer, jiffies + msecs_to_jiffies(idle_timeout));
2209 static int sky2_poll(struct net_device *dev0, int *budget)
2211 struct sky2_hw *hw = ((struct sky2_port *) netdev_priv(dev0))->hw;
2212 int work_limit = min(dev0->quota, *budget);
2214 u32 status = sky2_read32(hw, B0_Y2_SP_EISR);
2216 if (status & Y2_IS_HW_ERR)
2219 if (status & Y2_IS_IRQ_PHY1)
2220 sky2_phy_intr(hw, 0);
2222 if (status & Y2_IS_IRQ_PHY2)
2223 sky2_phy_intr(hw, 1);
2225 if (status & Y2_IS_IRQ_MAC1)
2226 sky2_mac_intr(hw, 0);
2228 if (status & Y2_IS_IRQ_MAC2)
2229 sky2_mac_intr(hw, 1);
2231 if (status & Y2_IS_CHK_RX1)
2232 sky2_descriptor_error(hw, 0, "receive", Y2_IS_CHK_RX1);
2234 if (status & Y2_IS_CHK_RX2)
2235 sky2_descriptor_error(hw, 1, "receive", Y2_IS_CHK_RX2);
2237 if (status & Y2_IS_CHK_TXA1)
2238 sky2_descriptor_error(hw, 0, "transmit", Y2_IS_CHK_TXA1);
2240 if (status & Y2_IS_CHK_TXA2)
2241 sky2_descriptor_error(hw, 1, "transmit", Y2_IS_CHK_TXA2);
2243 work_done = sky2_status_intr(hw, work_limit);
2244 if (work_done < work_limit) {
2245 netif_rx_complete(dev0);
2247 sky2_read32(hw, B0_Y2_SP_LISR);
2250 *budget -= work_done;
2251 dev0->quota -= work_done;
2256 static irqreturn_t sky2_intr(int irq, void *dev_id, struct pt_regs *regs)
2258 struct sky2_hw *hw = dev_id;
2259 struct net_device *dev0 = hw->dev[0];
2262 /* Reading this mask interrupts as side effect */
2263 status = sky2_read32(hw, B0_Y2_SP_ISRC2);
2264 if (status == 0 || status == ~0)
2267 prefetch(&hw->st_le[hw->st_idx]);
2268 if (likely(__netif_rx_schedule_prep(dev0)))
2269 __netif_rx_schedule(dev0);
2274 #ifdef CONFIG_NET_POLL_CONTROLLER
2275 static void sky2_netpoll(struct net_device *dev)
2277 struct sky2_port *sky2 = netdev_priv(dev);
2278 struct net_device *dev0 = sky2->hw->dev[0];
2280 if (netif_running(dev) && __netif_rx_schedule_prep(dev0))
2281 __netif_rx_schedule(dev0);
2285 /* Chip internal frequency for clock calculations */
2286 static inline u32 sky2_mhz(const struct sky2_hw *hw)
2288 switch (hw->chip_id) {
2289 case CHIP_ID_YUKON_EC:
2290 case CHIP_ID_YUKON_EC_U:
2291 return 125; /* 125 Mhz */
2292 case CHIP_ID_YUKON_FE:
2293 return 100; /* 100 Mhz */
2294 default: /* YUKON_XL */
2295 return 156; /* 156 Mhz */
2299 static inline u32 sky2_us2clk(const struct sky2_hw *hw, u32 us)
2301 return sky2_mhz(hw) * us;
2304 static inline u32 sky2_clk2us(const struct sky2_hw *hw, u32 clk)
2306 return clk / sky2_mhz(hw);
2310 static int sky2_reset(struct sky2_hw *hw)
2317 sky2_write8(hw, B0_CTST, CS_RST_CLR);
2319 hw->chip_id = sky2_read8(hw, B2_CHIP_ID);
2320 if (hw->chip_id < CHIP_ID_YUKON_XL || hw->chip_id > CHIP_ID_YUKON_FE) {
2321 printk(KERN_ERR PFX "%s: unsupported chip type 0x%x\n",
2322 pci_name(hw->pdev), hw->chip_id);
2326 hw->chip_rev = (sky2_read8(hw, B2_MAC_CFG) & CFG_CHIP_R_MSK) >> 4;
2328 /* This rev is really old, and requires untested workarounds */
2329 if (hw->chip_id == CHIP_ID_YUKON_EC && hw->chip_rev == CHIP_REV_YU_EC_A1) {
2330 printk(KERN_ERR PFX "%s: unsupported revision Yukon-%s (0x%x) rev %d\n",
2331 pci_name(hw->pdev), yukon2_name[hw->chip_id - CHIP_ID_YUKON_XL],
2332 hw->chip_id, hw->chip_rev);
2337 if (hw->chip_id <= CHIP_ID_YUKON_EC) {
2338 sky2_write8(hw, B28_Y2_ASF_STAT_CMD, Y2_ASF_RESET);
2339 sky2_write16(hw, B0_CTST, Y2_ASF_DISABLE);
2343 sky2_write8(hw, B0_CTST, CS_RST_SET);
2344 sky2_write8(hw, B0_CTST, CS_RST_CLR);
2346 /* clear PCI errors, if any */
2347 status = sky2_pci_read16(hw, PCI_STATUS);
2349 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
2350 sky2_pci_write16(hw, PCI_STATUS, status | PCI_STATUS_ERROR_BITS);
2353 sky2_write8(hw, B0_CTST, CS_MRST_CLR);
2355 /* clear any PEX errors */
2356 if (pci_find_capability(hw->pdev, PCI_CAP_ID_EXP)) {
2357 hw->err_cap = pci_find_ext_capability(hw->pdev, PCI_EXT_CAP_ID_ERR);
2359 sky2_pci_write32(hw,
2360 hw->err_cap + PCI_ERR_UNCOR_STATUS,
2364 hw->pmd_type = sky2_read8(hw, B2_PMD_TYP);
2366 t8 = sky2_read8(hw, B2_Y2_HW_RES);
2367 if ((t8 & CFG_DUAL_MAC_MSK) == CFG_DUAL_MAC_MSK) {
2368 if (!(sky2_read8(hw, B2_Y2_CLK_GATE) & Y2_STATUS_LNK2_INAC))
2372 sky2_set_power_state(hw, PCI_D0);
2374 for (i = 0; i < hw->ports; i++) {
2375 sky2_write8(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_SET);
2376 sky2_write8(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_CLR);
2379 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
2381 /* Clear I2C IRQ noise */
2382 sky2_write32(hw, B2_I2C_IRQ, 1);
2384 /* turn off hardware timer (unused) */
2385 sky2_write8(hw, B2_TI_CTRL, TIM_STOP);
2386 sky2_write8(hw, B2_TI_CTRL, TIM_CLR_IRQ);
2388 sky2_write8(hw, B0_Y2LED, LED_STAT_ON);
2390 /* Turn off descriptor polling */
2391 sky2_write32(hw, B28_DPT_CTRL, DPT_STOP);
2393 /* Turn off receive timestamp */
2394 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_STOP);
2395 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ);
2397 /* enable the Tx Arbiters */
2398 for (i = 0; i < hw->ports; i++)
2399 sky2_write8(hw, SK_REG(i, TXA_CTRL), TXA_ENA_ARB);
2401 /* Initialize ram interface */
2402 for (i = 0; i < hw->ports; i++) {
2403 sky2_write8(hw, RAM_BUFFER(i, B3_RI_CTRL), RI_RST_CLR);
2405 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_R1), SK_RI_TO_53);
2406 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XA1), SK_RI_TO_53);
2407 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XS1), SK_RI_TO_53);
2408 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_R1), SK_RI_TO_53);
2409 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XA1), SK_RI_TO_53);
2410 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XS1), SK_RI_TO_53);
2411 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_R2), SK_RI_TO_53);
2412 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XA2), SK_RI_TO_53);
2413 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XS2), SK_RI_TO_53);
2414 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_R2), SK_RI_TO_53);
2415 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XA2), SK_RI_TO_53);
2416 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XS2), SK_RI_TO_53);
2419 msk = Y2_HWE_ALL_MASK;
2421 msk &= ~Y2_IS_PCI_EXP;
2422 sky2_write32(hw, B0_HWE_IMSK, msk);
2424 for (i = 0; i < hw->ports; i++)
2425 sky2_gmac_reset(hw, i);
2427 memset(hw->st_le, 0, STATUS_LE_BYTES);
2430 sky2_write32(hw, STAT_CTRL, SC_STAT_RST_SET);
2431 sky2_write32(hw, STAT_CTRL, SC_STAT_RST_CLR);
2433 sky2_write32(hw, STAT_LIST_ADDR_LO, hw->st_dma);
2434 sky2_write32(hw, STAT_LIST_ADDR_HI, (u64) hw->st_dma >> 32);
2436 /* Set the list last index */
2437 sky2_write16(hw, STAT_LAST_IDX, STATUS_RING_SIZE - 1);
2439 sky2_write16(hw, STAT_TX_IDX_TH, 10);
2440 sky2_write8(hw, STAT_FIFO_WM, 16);
2442 /* set Status-FIFO ISR watermark */
2443 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0)
2444 sky2_write8(hw, STAT_FIFO_ISR_WM, 4);
2446 sky2_write8(hw, STAT_FIFO_ISR_WM, 16);
2448 sky2_write32(hw, STAT_TX_TIMER_INI, sky2_us2clk(hw, 1000));
2449 sky2_write32(hw, STAT_ISR_TIMER_INI, sky2_us2clk(hw, 20));
2450 sky2_write32(hw, STAT_LEV_TIMER_INI, sky2_us2clk(hw, 100));
2452 /* enable status unit */
2453 sky2_write32(hw, STAT_CTRL, SC_STAT_OP_ON);
2455 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_START);
2456 sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_START);
2457 sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_START);
2462 static u32 sky2_supported_modes(const struct sky2_hw *hw)
2464 if (sky2_is_copper(hw)) {
2465 u32 modes = SUPPORTED_10baseT_Half
2466 | SUPPORTED_10baseT_Full
2467 | SUPPORTED_100baseT_Half
2468 | SUPPORTED_100baseT_Full
2469 | SUPPORTED_Autoneg | SUPPORTED_TP;
2471 if (hw->chip_id != CHIP_ID_YUKON_FE)
2472 modes |= SUPPORTED_1000baseT_Half
2473 | SUPPORTED_1000baseT_Full;
2476 return SUPPORTED_1000baseT_Half
2477 | SUPPORTED_1000baseT_Full
2482 static int sky2_get_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
2484 struct sky2_port *sky2 = netdev_priv(dev);
2485 struct sky2_hw *hw = sky2->hw;
2487 ecmd->transceiver = XCVR_INTERNAL;
2488 ecmd->supported = sky2_supported_modes(hw);
2489 ecmd->phy_address = PHY_ADDR_MARV;
2490 if (sky2_is_copper(hw)) {
2491 ecmd->supported = SUPPORTED_10baseT_Half
2492 | SUPPORTED_10baseT_Full
2493 | SUPPORTED_100baseT_Half
2494 | SUPPORTED_100baseT_Full
2495 | SUPPORTED_1000baseT_Half
2496 | SUPPORTED_1000baseT_Full
2497 | SUPPORTED_Autoneg | SUPPORTED_TP;
2498 ecmd->port = PORT_TP;
2499 ecmd->speed = sky2->speed;
2501 ecmd->speed = SPEED_1000;
2502 ecmd->port = PORT_FIBRE;
2505 ecmd->advertising = sky2->advertising;
2506 ecmd->autoneg = sky2->autoneg;
2507 ecmd->duplex = sky2->duplex;
2511 static int sky2_set_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
2513 struct sky2_port *sky2 = netdev_priv(dev);
2514 const struct sky2_hw *hw = sky2->hw;
2515 u32 supported = sky2_supported_modes(hw);
2517 if (ecmd->autoneg == AUTONEG_ENABLE) {
2518 ecmd->advertising = supported;
2524 switch (ecmd->speed) {
2526 if (ecmd->duplex == DUPLEX_FULL)
2527 setting = SUPPORTED_1000baseT_Full;
2528 else if (ecmd->duplex == DUPLEX_HALF)
2529 setting = SUPPORTED_1000baseT_Half;
2534 if (ecmd->duplex == DUPLEX_FULL)
2535 setting = SUPPORTED_100baseT_Full;
2536 else if (ecmd->duplex == DUPLEX_HALF)
2537 setting = SUPPORTED_100baseT_Half;
2543 if (ecmd->duplex == DUPLEX_FULL)
2544 setting = SUPPORTED_10baseT_Full;
2545 else if (ecmd->duplex == DUPLEX_HALF)
2546 setting = SUPPORTED_10baseT_Half;
2554 if ((setting & supported) == 0)
2557 sky2->speed = ecmd->speed;
2558 sky2->duplex = ecmd->duplex;
2561 sky2->autoneg = ecmd->autoneg;
2562 sky2->advertising = ecmd->advertising;
2564 if (netif_running(dev))
2565 sky2_phy_reinit(sky2);
2570 static void sky2_get_drvinfo(struct net_device *dev,
2571 struct ethtool_drvinfo *info)
2573 struct sky2_port *sky2 = netdev_priv(dev);
2575 strcpy(info->driver, DRV_NAME);
2576 strcpy(info->version, DRV_VERSION);
2577 strcpy(info->fw_version, "N/A");
2578 strcpy(info->bus_info, pci_name(sky2->hw->pdev));
2581 static const struct sky2_stat {
2582 char name[ETH_GSTRING_LEN];
2585 { "tx_bytes", GM_TXO_OK_HI },
2586 { "rx_bytes", GM_RXO_OK_HI },
2587 { "tx_broadcast", GM_TXF_BC_OK },
2588 { "rx_broadcast", GM_RXF_BC_OK },
2589 { "tx_multicast", GM_TXF_MC_OK },
2590 { "rx_multicast", GM_RXF_MC_OK },
2591 { "tx_unicast", GM_TXF_UC_OK },
2592 { "rx_unicast", GM_RXF_UC_OK },
2593 { "tx_mac_pause", GM_TXF_MPAUSE },
2594 { "rx_mac_pause", GM_RXF_MPAUSE },
2595 { "collisions", GM_TXF_COL },
2596 { "late_collision",GM_TXF_LAT_COL },
2597 { "aborted", GM_TXF_ABO_COL },
2598 { "single_collisions", GM_TXF_SNG_COL },
2599 { "multi_collisions", GM_TXF_MUL_COL },
2601 { "rx_short", GM_RXF_SHT },
2602 { "rx_runt", GM_RXE_FRAG },
2603 { "rx_64_byte_packets", GM_RXF_64B },
2604 { "rx_65_to_127_byte_packets", GM_RXF_127B },
2605 { "rx_128_to_255_byte_packets", GM_RXF_255B },
2606 { "rx_256_to_511_byte_packets", GM_RXF_511B },
2607 { "rx_512_to_1023_byte_packets", GM_RXF_1023B },
2608 { "rx_1024_to_1518_byte_packets", GM_RXF_1518B },
2609 { "rx_1518_to_max_byte_packets", GM_RXF_MAX_SZ },
2610 { "rx_too_long", GM_RXF_LNG_ERR },
2611 { "rx_fifo_overflow", GM_RXE_FIFO_OV },
2612 { "rx_jabber", GM_RXF_JAB_PKT },
2613 { "rx_fcs_error", GM_RXF_FCS_ERR },
2615 { "tx_64_byte_packets", GM_TXF_64B },
2616 { "tx_65_to_127_byte_packets", GM_TXF_127B },
2617 { "tx_128_to_255_byte_packets", GM_TXF_255B },
2618 { "tx_256_to_511_byte_packets", GM_TXF_511B },
2619 { "tx_512_to_1023_byte_packets", GM_TXF_1023B },
2620 { "tx_1024_to_1518_byte_packets", GM_TXF_1518B },
2621 { "tx_1519_to_max_byte_packets", GM_TXF_MAX_SZ },
2622 { "tx_fifo_underrun", GM_TXE_FIFO_UR },
2625 static u32 sky2_get_rx_csum(struct net_device *dev)
2627 struct sky2_port *sky2 = netdev_priv(dev);
2629 return sky2->rx_csum;
2632 static int sky2_set_rx_csum(struct net_device *dev, u32 data)
2634 struct sky2_port *sky2 = netdev_priv(dev);
2636 sky2->rx_csum = data;
2638 sky2_write32(sky2->hw, Q_ADDR(rxqaddr[sky2->port], Q_CSR),
2639 data ? BMU_ENA_RX_CHKSUM : BMU_DIS_RX_CHKSUM);
2644 static u32 sky2_get_msglevel(struct net_device *netdev)
2646 struct sky2_port *sky2 = netdev_priv(netdev);
2647 return sky2->msg_enable;
2650 static int sky2_nway_reset(struct net_device *dev)
2652 struct sky2_port *sky2 = netdev_priv(dev);
2654 if (sky2->autoneg != AUTONEG_ENABLE)
2657 sky2_phy_reinit(sky2);
2662 static void sky2_phy_stats(struct sky2_port *sky2, u64 * data, unsigned count)
2664 struct sky2_hw *hw = sky2->hw;
2665 unsigned port = sky2->port;
2668 data[0] = (u64) gma_read32(hw, port, GM_TXO_OK_HI) << 32
2669 | (u64) gma_read32(hw, port, GM_TXO_OK_LO);
2670 data[1] = (u64) gma_read32(hw, port, GM_RXO_OK_HI) << 32
2671 | (u64) gma_read32(hw, port, GM_RXO_OK_LO);
2673 for (i = 2; i < count; i++)
2674 data[i] = (u64) gma_read32(hw, port, sky2_stats[i].offset);
2677 static void sky2_set_msglevel(struct net_device *netdev, u32 value)
2679 struct sky2_port *sky2 = netdev_priv(netdev);
2680 sky2->msg_enable = value;
2683 static int sky2_get_stats_count(struct net_device *dev)
2685 return ARRAY_SIZE(sky2_stats);
2688 static void sky2_get_ethtool_stats(struct net_device *dev,
2689 struct ethtool_stats *stats, u64 * data)
2691 struct sky2_port *sky2 = netdev_priv(dev);
2693 sky2_phy_stats(sky2, data, ARRAY_SIZE(sky2_stats));
2696 static void sky2_get_strings(struct net_device *dev, u32 stringset, u8 * data)
2700 switch (stringset) {
2702 for (i = 0; i < ARRAY_SIZE(sky2_stats); i++)
2703 memcpy(data + i * ETH_GSTRING_LEN,
2704 sky2_stats[i].name, ETH_GSTRING_LEN);
2709 /* Use hardware MIB variables for critical path statistics and
2710 * transmit feedback not reported at interrupt.
2711 * Other errors are accounted for in interrupt handler.
2713 static struct net_device_stats *sky2_get_stats(struct net_device *dev)
2715 struct sky2_port *sky2 = netdev_priv(dev);
2718 sky2_phy_stats(sky2, data, ARRAY_SIZE(data));
2720 sky2->net_stats.tx_bytes = data[0];
2721 sky2->net_stats.rx_bytes = data[1];
2722 sky2->net_stats.tx_packets = data[2] + data[4] + data[6];
2723 sky2->net_stats.rx_packets = data[3] + data[5] + data[7];
2724 sky2->net_stats.multicast = data[3] + data[5];
2725 sky2->net_stats.collisions = data[10];
2726 sky2->net_stats.tx_aborted_errors = data[12];
2728 return &sky2->net_stats;
2731 static int sky2_set_mac_address(struct net_device *dev, void *p)
2733 struct sky2_port *sky2 = netdev_priv(dev);
2734 struct sky2_hw *hw = sky2->hw;
2735 unsigned port = sky2->port;
2736 const struct sockaddr *addr = p;
2738 if (!is_valid_ether_addr(addr->sa_data))
2739 return -EADDRNOTAVAIL;
2741 memcpy(dev->dev_addr, addr->sa_data, ETH_ALEN);
2742 memcpy_toio(hw->regs + B2_MAC_1 + port * 8,
2743 dev->dev_addr, ETH_ALEN);
2744 memcpy_toio(hw->regs + B2_MAC_2 + port * 8,
2745 dev->dev_addr, ETH_ALEN);
2747 /* virtual address for data */
2748 gma_set_addr(hw, port, GM_SRC_ADDR_2L, dev->dev_addr);
2750 /* physical address: used for pause frames */
2751 gma_set_addr(hw, port, GM_SRC_ADDR_1L, dev->dev_addr);
2756 static void sky2_set_multicast(struct net_device *dev)
2758 struct sky2_port *sky2 = netdev_priv(dev);
2759 struct sky2_hw *hw = sky2->hw;
2760 unsigned port = sky2->port;
2761 struct dev_mc_list *list = dev->mc_list;
2765 memset(filter, 0, sizeof(filter));
2767 reg = gma_read16(hw, port, GM_RX_CTRL);
2768 reg |= GM_RXCR_UCF_ENA;
2770 if (dev->flags & IFF_PROMISC) /* promiscuous */
2771 reg &= ~(GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA);
2772 else if ((dev->flags & IFF_ALLMULTI) || dev->mc_count > 16) /* all multicast */
2773 memset(filter, 0xff, sizeof(filter));
2774 else if (dev->mc_count == 0) /* no multicast */
2775 reg &= ~GM_RXCR_MCF_ENA;
2778 reg |= GM_RXCR_MCF_ENA;
2780 for (i = 0; list && i < dev->mc_count; i++, list = list->next) {
2781 u32 bit = ether_crc(ETH_ALEN, list->dmi_addr) & 0x3f;
2782 filter[bit / 8] |= 1 << (bit % 8);
2786 gma_write16(hw, port, GM_MC_ADDR_H1,
2787 (u16) filter[0] | ((u16) filter[1] << 8));
2788 gma_write16(hw, port, GM_MC_ADDR_H2,
2789 (u16) filter[2] | ((u16) filter[3] << 8));
2790 gma_write16(hw, port, GM_MC_ADDR_H3,
2791 (u16) filter[4] | ((u16) filter[5] << 8));
2792 gma_write16(hw, port, GM_MC_ADDR_H4,
2793 (u16) filter[6] | ((u16) filter[7] << 8));
2795 gma_write16(hw, port, GM_RX_CTRL, reg);
2798 /* Can have one global because blinking is controlled by
2799 * ethtool and that is always under RTNL mutex
2801 static void sky2_led(struct sky2_hw *hw, unsigned port, int on)
2805 switch (hw->chip_id) {
2806 case CHIP_ID_YUKON_XL:
2807 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
2808 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
2809 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
2810 on ? (PHY_M_LEDC_LOS_CTRL(1) |
2811 PHY_M_LEDC_INIT_CTRL(7) |
2812 PHY_M_LEDC_STA1_CTRL(7) |
2813 PHY_M_LEDC_STA0_CTRL(7))
2816 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
2820 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, 0);
2821 gm_phy_write(hw, port, PHY_MARV_LED_OVER,
2822 on ? PHY_M_LED_MO_DUP(MO_LED_ON) |
2823 PHY_M_LED_MO_10(MO_LED_ON) |
2824 PHY_M_LED_MO_100(MO_LED_ON) |
2825 PHY_M_LED_MO_1000(MO_LED_ON) |
2826 PHY_M_LED_MO_RX(MO_LED_ON)
2827 : PHY_M_LED_MO_DUP(MO_LED_OFF) |
2828 PHY_M_LED_MO_10(MO_LED_OFF) |
2829 PHY_M_LED_MO_100(MO_LED_OFF) |
2830 PHY_M_LED_MO_1000(MO_LED_OFF) |
2831 PHY_M_LED_MO_RX(MO_LED_OFF));
2836 /* blink LED's for finding board */
2837 static int sky2_phys_id(struct net_device *dev, u32 data)
2839 struct sky2_port *sky2 = netdev_priv(dev);
2840 struct sky2_hw *hw = sky2->hw;
2841 unsigned port = sky2->port;
2842 u16 ledctrl, ledover = 0;
2847 if (!data || data > (u32) (MAX_SCHEDULE_TIMEOUT / HZ))
2848 ms = jiffies_to_msecs(MAX_SCHEDULE_TIMEOUT);
2852 /* save initial values */
2853 spin_lock_bh(&sky2->phy_lock);
2854 if (hw->chip_id == CHIP_ID_YUKON_XL) {
2855 u16 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
2856 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
2857 ledctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
2858 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
2860 ledctrl = gm_phy_read(hw, port, PHY_MARV_LED_CTRL);
2861 ledover = gm_phy_read(hw, port, PHY_MARV_LED_OVER);
2865 while (!interrupted && ms > 0) {
2866 sky2_led(hw, port, onoff);
2869 spin_unlock_bh(&sky2->phy_lock);
2870 interrupted = msleep_interruptible(250);
2871 spin_lock_bh(&sky2->phy_lock);
2876 /* resume regularly scheduled programming */
2877 if (hw->chip_id == CHIP_ID_YUKON_XL) {
2878 u16 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
2879 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
2880 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ledctrl);
2881 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
2883 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, ledctrl);
2884 gm_phy_write(hw, port, PHY_MARV_LED_OVER, ledover);
2886 spin_unlock_bh(&sky2->phy_lock);
2891 static void sky2_get_pauseparam(struct net_device *dev,
2892 struct ethtool_pauseparam *ecmd)
2894 struct sky2_port *sky2 = netdev_priv(dev);
2896 ecmd->tx_pause = sky2->tx_pause;
2897 ecmd->rx_pause = sky2->rx_pause;
2898 ecmd->autoneg = sky2->autoneg;
2901 static int sky2_set_pauseparam(struct net_device *dev,
2902 struct ethtool_pauseparam *ecmd)
2904 struct sky2_port *sky2 = netdev_priv(dev);
2906 sky2->autoneg = ecmd->autoneg;
2907 sky2->tx_pause = ecmd->tx_pause != 0;
2908 sky2->rx_pause = ecmd->rx_pause != 0;
2910 sky2_phy_reinit(sky2);
2915 static int sky2_get_coalesce(struct net_device *dev,
2916 struct ethtool_coalesce *ecmd)
2918 struct sky2_port *sky2 = netdev_priv(dev);
2919 struct sky2_hw *hw = sky2->hw;
2921 if (sky2_read8(hw, STAT_TX_TIMER_CTRL) == TIM_STOP)
2922 ecmd->tx_coalesce_usecs = 0;
2924 u32 clks = sky2_read32(hw, STAT_TX_TIMER_INI);
2925 ecmd->tx_coalesce_usecs = sky2_clk2us(hw, clks);
2927 ecmd->tx_max_coalesced_frames = sky2_read16(hw, STAT_TX_IDX_TH);
2929 if (sky2_read8(hw, STAT_LEV_TIMER_CTRL) == TIM_STOP)
2930 ecmd->rx_coalesce_usecs = 0;
2932 u32 clks = sky2_read32(hw, STAT_LEV_TIMER_INI);
2933 ecmd->rx_coalesce_usecs = sky2_clk2us(hw, clks);
2935 ecmd->rx_max_coalesced_frames = sky2_read8(hw, STAT_FIFO_WM);
2937 if (sky2_read8(hw, STAT_ISR_TIMER_CTRL) == TIM_STOP)
2938 ecmd->rx_coalesce_usecs_irq = 0;
2940 u32 clks = sky2_read32(hw, STAT_ISR_TIMER_INI);
2941 ecmd->rx_coalesce_usecs_irq = sky2_clk2us(hw, clks);
2944 ecmd->rx_max_coalesced_frames_irq = sky2_read8(hw, STAT_FIFO_ISR_WM);
2949 /* Note: this affect both ports */
2950 static int sky2_set_coalesce(struct net_device *dev,
2951 struct ethtool_coalesce *ecmd)
2953 struct sky2_port *sky2 = netdev_priv(dev);
2954 struct sky2_hw *hw = sky2->hw;
2955 const u32 tmax = sky2_clk2us(hw, 0x0ffffff);
2957 if (ecmd->tx_coalesce_usecs > tmax ||
2958 ecmd->rx_coalesce_usecs > tmax ||
2959 ecmd->rx_coalesce_usecs_irq > tmax)
2962 if (ecmd->tx_max_coalesced_frames >= TX_RING_SIZE-1)
2964 if (ecmd->rx_max_coalesced_frames > RX_MAX_PENDING)
2966 if (ecmd->rx_max_coalesced_frames_irq >RX_MAX_PENDING)
2969 if (ecmd->tx_coalesce_usecs == 0)
2970 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_STOP);
2972 sky2_write32(hw, STAT_TX_TIMER_INI,
2973 sky2_us2clk(hw, ecmd->tx_coalesce_usecs));
2974 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_START);
2976 sky2_write16(hw, STAT_TX_IDX_TH, ecmd->tx_max_coalesced_frames);
2978 if (ecmd->rx_coalesce_usecs == 0)
2979 sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_STOP);
2981 sky2_write32(hw, STAT_LEV_TIMER_INI,
2982 sky2_us2clk(hw, ecmd->rx_coalesce_usecs));
2983 sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_START);
2985 sky2_write8(hw, STAT_FIFO_WM, ecmd->rx_max_coalesced_frames);
2987 if (ecmd->rx_coalesce_usecs_irq == 0)
2988 sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_STOP);
2990 sky2_write32(hw, STAT_ISR_TIMER_INI,
2991 sky2_us2clk(hw, ecmd->rx_coalesce_usecs_irq));
2992 sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_START);
2994 sky2_write8(hw, STAT_FIFO_ISR_WM, ecmd->rx_max_coalesced_frames_irq);
2998 static void sky2_get_ringparam(struct net_device *dev,
2999 struct ethtool_ringparam *ering)
3001 struct sky2_port *sky2 = netdev_priv(dev);
3003 ering->rx_max_pending = RX_MAX_PENDING;
3004 ering->rx_mini_max_pending = 0;
3005 ering->rx_jumbo_max_pending = 0;
3006 ering->tx_max_pending = TX_RING_SIZE - 1;
3008 ering->rx_pending = sky2->rx_pending;
3009 ering->rx_mini_pending = 0;
3010 ering->rx_jumbo_pending = 0;
3011 ering->tx_pending = sky2->tx_pending;
3014 static int sky2_set_ringparam(struct net_device *dev,
3015 struct ethtool_ringparam *ering)
3017 struct sky2_port *sky2 = netdev_priv(dev);
3020 if (ering->rx_pending > RX_MAX_PENDING ||
3021 ering->rx_pending < 8 ||
3022 ering->tx_pending < MAX_SKB_TX_LE ||
3023 ering->tx_pending > TX_RING_SIZE - 1)
3026 if (netif_running(dev))
3029 sky2->rx_pending = ering->rx_pending;
3030 sky2->tx_pending = ering->tx_pending;
3032 if (netif_running(dev)) {
3037 sky2_set_multicast(dev);
3043 static int sky2_get_regs_len(struct net_device *dev)
3049 * Returns copy of control register region
3050 * Note: access to the RAM address register set will cause timeouts.
3052 static void sky2_get_regs(struct net_device *dev, struct ethtool_regs *regs,
3055 const struct sky2_port *sky2 = netdev_priv(dev);
3056 const void __iomem *io = sky2->hw->regs;
3058 BUG_ON(regs->len < B3_RI_WTO_R1);
3060 memset(p, 0, regs->len);
3062 memcpy_fromio(p, io, B3_RAM_ADDR);
3064 memcpy_fromio(p + B3_RI_WTO_R1,
3066 regs->len - B3_RI_WTO_R1);
3069 static const struct ethtool_ops sky2_ethtool_ops = {
3070 .get_settings = sky2_get_settings,
3071 .set_settings = sky2_set_settings,
3072 .get_drvinfo = sky2_get_drvinfo,
3073 .get_msglevel = sky2_get_msglevel,
3074 .set_msglevel = sky2_set_msglevel,
3075 .nway_reset = sky2_nway_reset,
3076 .get_regs_len = sky2_get_regs_len,
3077 .get_regs = sky2_get_regs,
3078 .get_link = ethtool_op_get_link,
3079 .get_sg = ethtool_op_get_sg,
3080 .set_sg = ethtool_op_set_sg,
3081 .get_tx_csum = ethtool_op_get_tx_csum,
3082 .set_tx_csum = ethtool_op_set_tx_csum,
3083 .get_tso = ethtool_op_get_tso,
3084 .set_tso = ethtool_op_set_tso,
3085 .get_rx_csum = sky2_get_rx_csum,
3086 .set_rx_csum = sky2_set_rx_csum,
3087 .get_strings = sky2_get_strings,
3088 .get_coalesce = sky2_get_coalesce,
3089 .set_coalesce = sky2_set_coalesce,
3090 .get_ringparam = sky2_get_ringparam,
3091 .set_ringparam = sky2_set_ringparam,
3092 .get_pauseparam = sky2_get_pauseparam,
3093 .set_pauseparam = sky2_set_pauseparam,
3094 .phys_id = sky2_phys_id,
3095 .get_stats_count = sky2_get_stats_count,
3096 .get_ethtool_stats = sky2_get_ethtool_stats,
3097 .get_perm_addr = ethtool_op_get_perm_addr,
3100 /* Initialize network device */
3101 static __devinit struct net_device *sky2_init_netdev(struct sky2_hw *hw,
3102 unsigned port, int highmem)
3104 struct sky2_port *sky2;
3105 struct net_device *dev = alloc_etherdev(sizeof(*sky2));
3108 printk(KERN_ERR "sky2 etherdev alloc failed");
3112 SET_MODULE_OWNER(dev);
3113 SET_NETDEV_DEV(dev, &hw->pdev->dev);
3114 dev->irq = hw->pdev->irq;
3115 dev->open = sky2_up;
3116 dev->stop = sky2_down;
3117 dev->do_ioctl = sky2_ioctl;
3118 dev->hard_start_xmit = sky2_xmit_frame;
3119 dev->get_stats = sky2_get_stats;
3120 dev->set_multicast_list = sky2_set_multicast;
3121 dev->set_mac_address = sky2_set_mac_address;
3122 dev->change_mtu = sky2_change_mtu;
3123 SET_ETHTOOL_OPS(dev, &sky2_ethtool_ops);
3124 dev->tx_timeout = sky2_tx_timeout;
3125 dev->watchdog_timeo = TX_WATCHDOG;
3127 dev->poll = sky2_poll;
3128 dev->weight = NAPI_WEIGHT;
3129 #ifdef CONFIG_NET_POLL_CONTROLLER
3130 dev->poll_controller = sky2_netpoll;
3133 sky2 = netdev_priv(dev);
3136 sky2->msg_enable = netif_msg_init(debug, default_msg);
3138 spin_lock_init(&sky2->tx_lock);
3139 /* Auto speed and flow control */
3140 sky2->autoneg = AUTONEG_ENABLE;
3145 sky2->advertising = sky2_supported_modes(hw);
3148 spin_lock_init(&sky2->phy_lock);
3149 sky2->tx_pending = TX_DEF_PENDING;
3150 sky2->rx_pending = RX_DEF_PENDING;
3151 sky2->rx_bufsize = sky2_buf_size(ETH_DATA_LEN);
3153 hw->dev[port] = dev;
3157 dev->features |= NETIF_F_LLTX;
3158 if (hw->chip_id != CHIP_ID_YUKON_EC_U)
3159 dev->features |= NETIF_F_TSO;
3161 dev->features |= NETIF_F_HIGHDMA;
3162 dev->features |= NETIF_F_IP_CSUM | NETIF_F_SG;
3164 #ifdef SKY2_VLAN_TAG_USED
3165 dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
3166 dev->vlan_rx_register = sky2_vlan_rx_register;
3167 dev->vlan_rx_kill_vid = sky2_vlan_rx_kill_vid;
3170 /* read the mac address */
3171 memcpy_fromio(dev->dev_addr, hw->regs + B2_MAC_1 + port * 8, ETH_ALEN);
3172 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
3174 /* device is off until link detection */
3175 netif_carrier_off(dev);
3176 netif_stop_queue(dev);
3181 static void __devinit sky2_show_addr(struct net_device *dev)
3183 const struct sky2_port *sky2 = netdev_priv(dev);
3185 if (netif_msg_probe(sky2))
3186 printk(KERN_INFO PFX "%s: addr %02x:%02x:%02x:%02x:%02x:%02x\n",
3188 dev->dev_addr[0], dev->dev_addr[1], dev->dev_addr[2],
3189 dev->dev_addr[3], dev->dev_addr[4], dev->dev_addr[5]);
3192 /* Handle software interrupt used during MSI test */
3193 static irqreturn_t __devinit sky2_test_intr(int irq, void *dev_id,
3194 struct pt_regs *regs)
3196 struct sky2_hw *hw = dev_id;
3197 u32 status = sky2_read32(hw, B0_Y2_SP_ISRC2);
3202 if (status & Y2_IS_IRQ_SW) {
3203 hw->msi_detected = 1;
3204 wake_up(&hw->msi_wait);
3205 sky2_write8(hw, B0_CTST, CS_CL_SW_IRQ);
3207 sky2_write32(hw, B0_Y2_SP_ICR, 2);
3212 /* Test interrupt path by forcing a a software IRQ */
3213 static int __devinit sky2_test_msi(struct sky2_hw *hw)
3215 struct pci_dev *pdev = hw->pdev;
3218 init_waitqueue_head (&hw->msi_wait);
3220 sky2_write32(hw, B0_IMSK, Y2_IS_IRQ_SW);
3222 err = request_irq(pdev->irq, sky2_test_intr, IRQF_SHARED, DRV_NAME, hw);
3224 printk(KERN_ERR PFX "%s: cannot assign irq %d\n",
3225 pci_name(pdev), pdev->irq);
3229 sky2_write8(hw, B0_CTST, CS_ST_SW_IRQ);
3230 sky2_read8(hw, B0_CTST);
3232 wait_event_timeout(hw->msi_wait, hw->msi_detected, HZ/10);
3234 if (!hw->msi_detected) {
3235 /* MSI test failed, go back to INTx mode */
3236 printk(KERN_WARNING PFX "%s: No interrupt was generated using MSI, "
3237 "switching to INTx mode. Please report this failure to "
3238 "the PCI maintainer and include system chipset information.\n",
3242 sky2_write8(hw, B0_CTST, CS_CL_SW_IRQ);
3245 sky2_write32(hw, B0_IMSK, 0);
3247 free_irq(pdev->irq, hw);
3252 static int __devinit sky2_probe(struct pci_dev *pdev,
3253 const struct pci_device_id *ent)
3255 struct net_device *dev, *dev1 = NULL;
3257 int err, pm_cap, using_dac = 0;
3259 err = pci_enable_device(pdev);
3261 printk(KERN_ERR PFX "%s cannot enable PCI device\n",
3266 err = pci_request_regions(pdev, DRV_NAME);
3268 printk(KERN_ERR PFX "%s cannot obtain PCI resources\n",
3273 pci_set_master(pdev);
3275 /* Find power-management capability. */
3276 pm_cap = pci_find_capability(pdev, PCI_CAP_ID_PM);
3278 printk(KERN_ERR PFX "Cannot find PowerManagement capability, "
3281 goto err_out_free_regions;
3284 if (sizeof(dma_addr_t) > sizeof(u32) &&
3285 !(err = pci_set_dma_mask(pdev, DMA_64BIT_MASK))) {
3287 err = pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK);
3289 printk(KERN_ERR PFX "%s unable to obtain 64 bit DMA "
3290 "for consistent allocations\n", pci_name(pdev));
3291 goto err_out_free_regions;
3295 err = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
3297 printk(KERN_ERR PFX "%s no usable DMA configuration\n",
3299 goto err_out_free_regions;
3304 hw = kzalloc(sizeof(*hw), GFP_KERNEL);
3306 printk(KERN_ERR PFX "%s: cannot allocate hardware struct\n",
3308 goto err_out_free_regions;
3313 hw->regs = ioremap_nocache(pci_resource_start(pdev, 0), 0x4000);
3315 printk(KERN_ERR PFX "%s: cannot map device registers\n",
3317 goto err_out_free_hw;
3319 hw->pm_cap = pm_cap;
3322 /* The sk98lin vendor driver uses hardware byte swapping but
3323 * this driver uses software swapping.
3327 reg = sky2_pci_read32(hw, PCI_DEV_REG2);
3328 reg &= ~PCI_REV_DESC;
3329 sky2_pci_write32(hw, PCI_DEV_REG2, reg);
3333 /* ring for status responses */
3334 hw->st_le = pci_alloc_consistent(hw->pdev, STATUS_LE_BYTES,
3337 goto err_out_iounmap;
3339 err = sky2_reset(hw);
3341 goto err_out_iounmap;
3343 printk(KERN_INFO PFX "v%s addr 0x%llx irq %d Yukon-%s (0x%x) rev %d\n",
3344 DRV_VERSION, (unsigned long long)pci_resource_start(pdev, 0),
3345 pdev->irq, yukon2_name[hw->chip_id - CHIP_ID_YUKON_XL],
3346 hw->chip_id, hw->chip_rev);
3348 dev = sky2_init_netdev(hw, 0, using_dac);
3350 goto err_out_free_pci;
3352 err = register_netdev(dev);
3354 printk(KERN_ERR PFX "%s: cannot register net device\n",
3356 goto err_out_free_netdev;
3359 sky2_show_addr(dev);
3361 if (hw->ports > 1 && (dev1 = sky2_init_netdev(hw, 1, using_dac))) {
3362 if (register_netdev(dev1) == 0)
3363 sky2_show_addr(dev1);
3365 /* Failure to register second port need not be fatal */
3366 printk(KERN_WARNING PFX
3367 "register of second port failed\n");
3373 if (!disable_msi && pci_enable_msi(pdev) == 0) {
3374 err = sky2_test_msi(hw);
3375 if (err == -EOPNOTSUPP)
3376 pci_disable_msi(pdev);
3378 goto err_out_unregister;
3381 err = request_irq(pdev->irq, sky2_intr, IRQF_SHARED, DRV_NAME, hw);
3383 printk(KERN_ERR PFX "%s: cannot assign irq %d\n",
3384 pci_name(pdev), pdev->irq);
3385 goto err_out_unregister;
3388 sky2_write32(hw, B0_IMSK, Y2_IS_BASE);
3390 setup_timer(&hw->idle_timer, sky2_idle, (unsigned long) hw);
3391 sky2_idle_start(hw);
3393 pci_set_drvdata(pdev, hw);
3398 pci_disable_msi(pdev);
3400 unregister_netdev(dev1);
3403 unregister_netdev(dev);
3404 err_out_free_netdev:
3407 sky2_write8(hw, B0_CTST, CS_RST_SET);
3408 pci_free_consistent(hw->pdev, STATUS_LE_BYTES, hw->st_le, hw->st_dma);
3413 err_out_free_regions:
3414 pci_release_regions(pdev);
3415 pci_disable_device(pdev);
3420 static void __devexit sky2_remove(struct pci_dev *pdev)
3422 struct sky2_hw *hw = pci_get_drvdata(pdev);
3423 struct net_device *dev0, *dev1;
3428 del_timer_sync(&hw->idle_timer);
3430 sky2_write32(hw, B0_IMSK, 0);
3431 synchronize_irq(hw->pdev->irq);
3436 unregister_netdev(dev1);
3437 unregister_netdev(dev0);
3439 sky2_set_power_state(hw, PCI_D3hot);
3440 sky2_write16(hw, B0_Y2LED, LED_STAT_OFF);
3441 sky2_write8(hw, B0_CTST, CS_RST_SET);
3442 sky2_read8(hw, B0_CTST);
3444 free_irq(pdev->irq, hw);
3445 pci_disable_msi(pdev);
3446 pci_free_consistent(pdev, STATUS_LE_BYTES, hw->st_le, hw->st_dma);
3447 pci_release_regions(pdev);
3448 pci_disable_device(pdev);
3456 pci_set_drvdata(pdev, NULL);
3460 static int sky2_suspend(struct pci_dev *pdev, pm_message_t state)
3462 struct sky2_hw *hw = pci_get_drvdata(pdev);
3464 pci_power_t pstate = pci_choose_state(pdev, state);
3466 if (!(pstate == PCI_D3hot || pstate == PCI_D3cold))
3469 del_timer_sync(&hw->idle_timer);
3470 netif_poll_disable(hw->dev[0]);
3472 for (i = 0; i < hw->ports; i++) {
3473 struct net_device *dev = hw->dev[i];
3475 if (netif_running(dev)) {
3477 netif_device_detach(dev);
3481 sky2_write32(hw, B0_IMSK, 0);
3482 pci_save_state(pdev);
3483 sky2_set_power_state(hw, pstate);
3487 static int sky2_resume(struct pci_dev *pdev)
3489 struct sky2_hw *hw = pci_get_drvdata(pdev);
3492 pci_restore_state(pdev);
3493 pci_enable_wake(pdev, PCI_D0, 0);
3494 sky2_set_power_state(hw, PCI_D0);
3496 err = sky2_reset(hw);
3500 sky2_write32(hw, B0_IMSK, Y2_IS_BASE);
3502 for (i = 0; i < hw->ports; i++) {
3503 struct net_device *dev = hw->dev[i];
3504 if (netif_running(dev)) {
3505 netif_device_attach(dev);
3509 printk(KERN_ERR PFX "%s: could not up: %d\n",
3517 netif_poll_enable(hw->dev[0]);
3518 sky2_idle_start(hw);
3524 static struct pci_driver sky2_driver = {
3526 .id_table = sky2_id_table,
3527 .probe = sky2_probe,
3528 .remove = __devexit_p(sky2_remove),
3530 .suspend = sky2_suspend,
3531 .resume = sky2_resume,
3535 static int __init sky2_init_module(void)
3537 return pci_register_driver(&sky2_driver);
3540 static void __exit sky2_cleanup_module(void)
3542 pci_unregister_driver(&sky2_driver);
3545 module_init(sky2_init_module);
3546 module_exit(sky2_cleanup_module);
3548 MODULE_DESCRIPTION("Marvell Yukon 2 Gigabit Ethernet driver");
3549 MODULE_AUTHOR("Stephen Hemminger <shemminger@osdl.org>");
3550 MODULE_LICENSE("GPL");
3551 MODULE_VERSION(DRV_VERSION);