2 * New driver for Marvell Yukon 2 chipset.
3 * Based on earlier sk98lin, and skge driver.
5 * This driver intentionally does not support all the features
6 * of the original driver such as link fail-over and link management because
7 * those should be done at higher levels.
9 * Copyright (C) 2005 Stephen Hemminger <shemminger@osdl.org>
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License, or
14 * (at your option) any later version.
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
28 * - coalescing setting?
32 * - variable ring size
38 #include <linux/config.h>
39 #include <linux/crc32.h>
40 #include <linux/kernel.h>
41 #include <linux/version.h>
42 #include <linux/module.h>
43 #include <linux/netdevice.h>
44 #include <linux/etherdevice.h>
45 #include <linux/ethtool.h>
46 #include <linux/pci.h>
48 #include <linux/tcp.h>
50 #include <linux/delay.h>
56 #define DRV_NAME "sky2"
57 #define DRV_VERSION "0.4"
58 #define PFX DRV_NAME " "
61 * The Yukon II chipset takes 64 bit command blocks (called list elements)
62 * that are organized into three (receive, transmit, status) different rings
63 * similar to Tigon3. A transmit can require several elements;
64 * a receive requires one (or two if using 64 bit dma).
67 #ifdef CONFIG_SKY2_EC_A1
68 #define is_ec_a1(hw) \
69 ((hw)->chip_id == CHIP_ID_YUKON_EC && \
70 (hw)->chip_rev == CHIP_REV_YU_EC_A1)
72 #define is_ec_a1(hw) 0
75 #define RX_LE_SIZE 256
76 #define RX_LE_BYTES (RX_LE_SIZE*sizeof(struct sky2_rx_le))
77 #define RX_MAX_PENDING (RX_LE_SIZE/2 - 1)
78 #define RX_DEF_PENDING 128
79 #define RX_COPY_THRESHOLD 256
81 #define TX_RING_SIZE 512
82 #define TX_DEF_PENDING (TX_RING_SIZE - 1)
83 #define TX_MIN_PENDING 64
84 #define MAX_SKB_TX_LE (4 + 2*MAX_SKB_FRAGS)
86 #define STATUS_RING_SIZE 2048 /* 2 ports * (TX + 2*RX) */
87 #define STATUS_LE_BYTES (STATUS_RING_SIZE*sizeof(struct sky2_status_le))
88 #define ETH_JUMBO_MTU 9000
89 #define TX_WATCHDOG (5 * HZ)
90 #define NAPI_WEIGHT 64
91 #define PHY_RETRIES 1000
93 static const u32 default_msg =
94 NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_LINK
95 | NETIF_MSG_TIMER | NETIF_MSG_TX_ERR | NETIF_MSG_RX_ERR
96 | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN | NETIF_MSG_INTR;
98 static int debug = -1; /* defaults above */
99 module_param(debug, int, 0);
100 MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
102 static const struct pci_device_id sky2_id_table[] = {
103 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, 0x9000) },
104 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, 0x9E00) },
105 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4b00) },
106 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4b01) },
107 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4340) },
108 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4341) },
109 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4342) },
110 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4343) },
111 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4344) },
112 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4345) },
113 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4346) },
114 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4347) },
115 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4350) },
116 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4351) },
117 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4360) },
118 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4361) },
119 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4362) },
123 MODULE_DEVICE_TABLE(pci, sky2_id_table);
125 /* Avoid conditionals by using array */
126 static const unsigned txqaddr[] = { Q_XA1, Q_XA2 };
127 static const unsigned rxqaddr[] = { Q_R1, Q_R2 };
129 static const char *yukon_name[] = {
130 [CHIP_ID_YUKON_LITE - CHIP_ID_YUKON] = "Lite", /* 0xb0 */
131 [CHIP_ID_YUKON_LP - CHIP_ID_YUKON] = "LP", /* 0xb2 */
132 [CHIP_ID_YUKON_XL - CHIP_ID_YUKON] = "XL", /* 0xb3 */
134 [CHIP_ID_YUKON_EC - CHIP_ID_YUKON] = "EC", /* 0xb6 */
135 [CHIP_ID_YUKON_FE - CHIP_ID_YUKON] = "FE", /* 0xb7 */
139 /* Access to external PHY */
140 static void gm_phy_write(struct sky2_hw *hw, unsigned port, u16 reg, u16 val)
144 gma_write16(hw, port, GM_SMI_DATA, val);
145 gma_write16(hw, port, GM_SMI_CTRL,
146 GM_SMI_CT_PHY_AD(PHY_ADDR_MARV) | GM_SMI_CT_REG_AD(reg));
148 for (i = 0; i < PHY_RETRIES; i++) {
149 if (!(gma_read16(hw, port, GM_SMI_CTRL) & GM_SMI_CT_BUSY))
153 printk(KERN_WARNING PFX "%s: phy write timeout\n", hw->dev[port]->name);
156 static u16 gm_phy_read(struct sky2_hw *hw, unsigned port, u16 reg)
160 gma_write16(hw, port, GM_SMI_CTRL, GM_SMI_CT_PHY_AD(PHY_ADDR_MARV)
161 | GM_SMI_CT_REG_AD(reg) | GM_SMI_CT_OP_RD);
163 for (i = 0; i < PHY_RETRIES; i++) {
164 if (gma_read16(hw, port, GM_SMI_CTRL) & GM_SMI_CT_RD_VAL)
169 printk(KERN_WARNING PFX "%s: phy read timeout\n", hw->dev[port]->name);
171 return gma_read16(hw, port, GM_SMI_DATA);
174 static void sky2_phy_reset(struct sky2_hw *hw, unsigned port)
178 /* disable all GMAC IRQ's */
179 sky2_write8(hw, SK_REG(port, GMAC_IRQ_MSK), 0);
180 /* disable PHY IRQs */
181 gm_phy_write(hw, port, PHY_MARV_INT_MASK, 0);
183 gma_write16(hw, port, GM_MC_ADDR_H1, 0); /* clear MC hash */
184 gma_write16(hw, port, GM_MC_ADDR_H2, 0);
185 gma_write16(hw, port, GM_MC_ADDR_H3, 0);
186 gma_write16(hw, port, GM_MC_ADDR_H4, 0);
188 reg = gma_read16(hw, port, GM_RX_CTRL);
189 reg |= GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA;
190 gma_write16(hw, port, GM_RX_CTRL, reg);
193 static void sky2_phy_init(struct sky2_hw *hw, unsigned port)
195 struct sky2_port *sky2 = netdev_priv(hw->dev[port]);
196 u16 ctrl, ct1000, adv, pg, ledctrl, ledover;
198 if (sky2->autoneg == AUTONEG_ENABLE && hw->chip_id != CHIP_ID_YUKON_XL) {
199 u16 ectrl = gm_phy_read(hw, port, PHY_MARV_EXT_CTRL);
201 ectrl &= ~(PHY_M_EC_M_DSC_MSK | PHY_M_EC_S_DSC_MSK |
203 ectrl |= PHY_M_EC_MAC_S(MAC_TX_CLK_25_MHZ);
205 if (hw->chip_id == CHIP_ID_YUKON_EC)
206 ectrl |= PHY_M_EC_DSC_2(2) | PHY_M_EC_DOWN_S_ENA;
208 ectrl |= PHY_M_EC_M_DSC(2) | PHY_M_EC_S_DSC(3);
210 gm_phy_write(hw, port, PHY_MARV_EXT_CTRL, ectrl);
213 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
215 if (hw->chip_id == CHIP_ID_YUKON_FE) {
216 /* enable automatic crossover */
217 ctrl |= PHY_M_PC_MDI_XMODE(PHY_M_PC_ENA_AUTO) >> 1;
219 /* disable energy detect */
220 ctrl &= ~PHY_M_PC_EN_DET_MSK;
222 /* enable automatic crossover */
223 ctrl |= PHY_M_PC_MDI_XMODE(PHY_M_PC_ENA_AUTO);
225 if (sky2->autoneg == AUTONEG_ENABLE &&
226 hw->chip_id == CHIP_ID_YUKON_XL) {
227 ctrl &= ~PHY_M_PC_DSC_MSK;
228 ctrl |= PHY_M_PC_DSC(2) | PHY_M_PC_DOWN_S_ENA;
231 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
233 /* workaround for deviation #4.88 (CRC errors) */
234 /* disable Automatic Crossover */
236 ctrl &= ~PHY_M_PC_MDIX_MSK;
237 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
239 if (hw->chip_id == CHIP_ID_YUKON_XL) {
240 /* Fiber: select 1000BASE-X only mode MAC Specific Ctrl Reg. */
241 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 2);
242 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
243 ctrl &= ~PHY_M_MAC_MD_MSK;
244 ctrl |= PHY_M_MAC_MODE_SEL(PHY_M_MAC_MD_1000BX);
245 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
247 /* select page 1 to access Fiber registers */
248 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 1);
252 ctrl = gm_phy_read(hw, port, PHY_MARV_CTRL);
253 if (sky2->autoneg == AUTONEG_DISABLE)
258 ctrl |= PHY_CT_RESET;
259 gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
265 if (sky2->autoneg == AUTONEG_ENABLE) {
267 if (sky2->advertising & ADVERTISED_1000baseT_Full)
268 ct1000 |= PHY_M_1000C_AFD;
269 if (sky2->advertising & ADVERTISED_1000baseT_Half)
270 ct1000 |= PHY_M_1000C_AHD;
271 if (sky2->advertising & ADVERTISED_100baseT_Full)
272 adv |= PHY_M_AN_100_FD;
273 if (sky2->advertising & ADVERTISED_100baseT_Half)
274 adv |= PHY_M_AN_100_HD;
275 if (sky2->advertising & ADVERTISED_10baseT_Full)
276 adv |= PHY_M_AN_10_FD;
277 if (sky2->advertising & ADVERTISED_10baseT_Half)
278 adv |= PHY_M_AN_10_HD;
279 } else /* special defines for FIBER (88E1011S only) */
280 adv |= PHY_M_AN_1000X_AHD | PHY_M_AN_1000X_AFD;
282 /* Set Flow-control capabilities */
283 if (sky2->tx_pause && sky2->rx_pause)
284 adv |= PHY_AN_PAUSE_CAP; /* symmetric */
285 else if (sky2->rx_pause && !sky2->tx_pause)
286 adv |= PHY_AN_PAUSE_ASYM | PHY_AN_PAUSE_CAP;
287 else if (!sky2->rx_pause && sky2->tx_pause)
288 adv |= PHY_AN_PAUSE_ASYM; /* local */
290 /* Restart Auto-negotiation */
291 ctrl |= PHY_CT_ANE | PHY_CT_RE_CFG;
293 /* forced speed/duplex settings */
294 ct1000 = PHY_M_1000C_MSE;
296 if (sky2->duplex == DUPLEX_FULL)
297 ctrl |= PHY_CT_DUP_MD;
299 switch (sky2->speed) {
301 ctrl |= PHY_CT_SP1000;
304 ctrl |= PHY_CT_SP100;
308 ctrl |= PHY_CT_RESET;
311 if (hw->chip_id != CHIP_ID_YUKON_FE)
312 gm_phy_write(hw, port, PHY_MARV_1000T_CTRL, ct1000);
314 gm_phy_write(hw, port, PHY_MARV_AUNE_ADV, adv);
315 gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
317 /* Setup Phy LED's */
318 ledctrl = PHY_M_LED_PULS_DUR(PULS_170MS);
321 switch (hw->chip_id) {
322 case CHIP_ID_YUKON_FE:
323 /* on 88E3082 these bits are at 11..9 (shifted left) */
324 ledctrl |= PHY_M_LED_BLINK_RT(BLINK_84MS) << 1;
326 ctrl = gm_phy_read(hw, port, PHY_MARV_FE_LED_PAR);
328 /* delete ACT LED control bits */
329 ctrl &= ~PHY_M_FELP_LED1_MSK;
330 /* change ACT LED control to blink mode */
331 ctrl |= PHY_M_FELP_LED1_CTRL(LED_PAR_CTRL_ACT_BL);
332 gm_phy_write(hw, port, PHY_MARV_FE_LED_PAR, ctrl);
335 case CHIP_ID_YUKON_XL:
336 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
338 /* select page 3 to access LED control register */
339 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
341 /* set LED Function Control register */
342 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, (PHY_M_LEDC_LOS_CTRL(1) | /* LINK/ACT */
343 PHY_M_LEDC_INIT_CTRL(7) | /* 10 Mbps */
344 PHY_M_LEDC_STA1_CTRL(7) | /* 100 Mbps */
345 PHY_M_LEDC_STA0_CTRL(7))); /* 1000 Mbps */
347 /* set Polarity Control register */
348 gm_phy_write(hw, port, PHY_MARV_PHY_STAT,
349 (PHY_M_POLC_LS1_P_MIX(4) |
350 PHY_M_POLC_IS0_P_MIX(4) |
351 PHY_M_POLC_LOS_CTRL(2) |
352 PHY_M_POLC_INIT_CTRL(2) |
353 PHY_M_POLC_STA1_CTRL(2) |
354 PHY_M_POLC_STA0_CTRL(2)));
356 /* restore page register */
357 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
361 /* set Tx LED (LED_TX) to blink mode on Rx OR Tx activity */
362 ledctrl |= PHY_M_LED_BLINK_RT(BLINK_84MS) | PHY_M_LEDC_TX_CTRL;
363 /* turn off the Rx LED (LED_RX) */
364 ledover |= PHY_M_LED_MO_RX(MO_LED_OFF);
367 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, ledctrl);
369 if (sky2->autoneg == AUTONEG_DISABLE || sky2->speed == SPEED_100) {
370 /* turn on 100 Mbps LED (LED_LINK100) */
371 ledover |= PHY_M_LED_MO_100(MO_LED_ON);
375 gm_phy_write(hw, port, PHY_MARV_LED_OVER, ledover);
377 /* Enable phy interrupt on autonegotiation complete (or link up) */
378 if (sky2->autoneg == AUTONEG_ENABLE)
379 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_IS_AN_COMPL);
381 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_DEF_MSK);
384 static void sky2_mac_init(struct sky2_hw *hw, unsigned port)
386 struct sky2_port *sky2 = netdev_priv(hw->dev[port]);
389 const u8 *addr = hw->dev[port]->dev_addr;
391 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET);
392 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_CLR);
394 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_CLR);
396 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0 && port == 1) {
397 /* WA DEV_472 -- looks like crossed wires on port 2 */
398 /* clear GMAC 1 Control reset */
399 sky2_write8(hw, SK_REG(0, GMAC_CTRL), GMC_RST_CLR);
401 sky2_write8(hw, SK_REG(1, GMAC_CTRL), GMC_RST_SET);
402 sky2_write8(hw, SK_REG(1, GMAC_CTRL), GMC_RST_CLR);
403 } while (gm_phy_read(hw, 1, PHY_MARV_ID0) != PHY_MARV_ID0_VAL ||
404 gm_phy_read(hw, 1, PHY_MARV_ID1) != PHY_MARV_ID1_Y2 ||
405 gm_phy_read(hw, 1, PHY_MARV_INT_MASK) != 0);
408 if (sky2->autoneg == AUTONEG_DISABLE) {
409 reg = gma_read16(hw, port, GM_GP_CTRL);
410 reg |= GM_GPCR_AU_ALL_DIS;
411 gma_write16(hw, port, GM_GP_CTRL, reg);
412 gma_read16(hw, port, GM_GP_CTRL);
414 switch (sky2->speed) {
416 reg |= GM_GPCR_SPEED_1000;
419 reg |= GM_GPCR_SPEED_100;
422 if (sky2->duplex == DUPLEX_FULL)
423 reg |= GM_GPCR_DUP_FULL;
425 reg = GM_GPCR_SPEED_1000 | GM_GPCR_SPEED_100 | GM_GPCR_DUP_FULL;
427 if (!sky2->tx_pause && !sky2->rx_pause) {
428 sky2_write32(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
430 GM_GPCR_FC_TX_DIS | GM_GPCR_FC_RX_DIS | GM_GPCR_AU_FCT_DIS;
431 } else if (sky2->tx_pause && !sky2->rx_pause) {
432 /* disable Rx flow-control */
433 reg |= GM_GPCR_FC_RX_DIS | GM_GPCR_AU_FCT_DIS;
436 gma_write16(hw, port, GM_GP_CTRL, reg);
438 sky2_read16(hw, SK_REG(port, GMAC_IRQ_SRC));
440 spin_lock_bh(&hw->phy_lock);
441 sky2_phy_init(hw, port);
442 spin_unlock_bh(&hw->phy_lock);
445 reg = gma_read16(hw, port, GM_PHY_ADDR);
446 gma_write16(hw, port, GM_PHY_ADDR, reg | GM_PAR_MIB_CLR);
448 for (i = 0; i < GM_MIB_CNT_SIZE; i++)
449 gma_read16(hw, port, GM_MIB_CNT_BASE + 8 * i);
450 gma_write16(hw, port, GM_PHY_ADDR, reg);
452 /* transmit control */
453 gma_write16(hw, port, GM_TX_CTRL, TX_COL_THR(TX_COL_DEF));
455 /* receive control reg: unicast + multicast + no FCS */
456 gma_write16(hw, port, GM_RX_CTRL,
457 GM_RXCR_UCF_ENA | GM_RXCR_CRC_DIS | GM_RXCR_MCF_ENA);
459 /* transmit flow control */
460 gma_write16(hw, port, GM_TX_FLOW_CTRL, 0xffff);
462 /* transmit parameter */
463 gma_write16(hw, port, GM_TX_PARAM,
464 TX_JAM_LEN_VAL(TX_JAM_LEN_DEF) |
465 TX_JAM_IPG_VAL(TX_JAM_IPG_DEF) |
466 TX_IPG_JAM_DATA(TX_IPG_JAM_DEF) |
467 TX_BACK_OFF_LIM(TX_BOF_LIM_DEF));
469 /* serial mode register */
470 reg = DATA_BLIND_VAL(DATA_BLIND_DEF) |
471 GM_SMOD_VLAN_ENA | IPG_DATA_VAL(IPG_DATA_DEF);
473 if (hw->dev[port]->mtu > 1500)
474 reg |= GM_SMOD_JUMBO_ENA;
476 gma_write16(hw, port, GM_SERIAL_MODE, reg);
478 /* virtual address for data */
479 gma_set_addr(hw, port, GM_SRC_ADDR_2L, addr);
481 /* physical address: used for pause frames */
482 gma_set_addr(hw, port, GM_SRC_ADDR_1L, addr);
484 /* ignore counter overflows */
485 gma_write16(hw, port, GM_TX_IRQ_MSK, 0);
486 gma_write16(hw, port, GM_RX_IRQ_MSK, 0);
487 gma_write16(hw, port, GM_TR_IRQ_MSK, 0);
489 /* Configure Rx MAC FIFO */
490 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_CLR);
491 sky2_write16(hw, SK_REG(port, RX_GMF_CTRL_T),
492 GMF_OPER_ON | GMF_RX_F_FL_ON);
494 /* Flush Rx MAC FIFO on any flowcontrol or error */
495 reg = GMR_FS_ANY_ERR;
496 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev <= 1)
497 reg = 0; /* WA Dev #4115 */
499 sky2_write16(hw, SK_REG(port, RX_GMF_FL_MSK), reg);
500 /* Set threshold to 0xa (64 bytes)
501 * ASF disabled so no need to do WA dev #4.30
503 sky2_write16(hw, SK_REG(port, RX_GMF_FL_THR), RX_GMF_FL_THR_DEF);
505 /* Configure Tx MAC FIFO */
506 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_CLR);
507 sky2_write16(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_OPER_ON);
510 static void sky2_ramset(struct sky2_hw *hw, u16 q, u32 start, size_t len)
516 end = start + len - 1;
518 pr_debug("sky2_ramset start=%d end=%d\n", start, end);
520 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_RST_CLR);
521 sky2_write32(hw, RB_ADDR(q, RB_START), start);
522 sky2_write32(hw, RB_ADDR(q, RB_END), end);
523 sky2_write32(hw, RB_ADDR(q, RB_WP), start);
524 sky2_write32(hw, RB_ADDR(q, RB_RP), start);
526 if (q == Q_R1 || q == Q_R2) {
531 pr_debug(" utpp=%d ltpp=%d\n", rxup, rxlo);
533 /* Set thresholds on receive queue's */
534 sky2_write32(hw, RB_ADDR(q, RB_RX_UTPP), rxup);
535 sky2_write32(hw, RB_ADDR(q, RB_RX_LTPP), rxlo);
537 /* Enable store & forward on Tx queue's because
538 * Tx FIFO is only 1K on Yukon
540 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_STFWD);
543 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_OP_MD);
544 sky2_read8(hw, RB_ADDR(q, RB_CTRL));
547 /* Setup Bus Memory Interface */
548 static void sky2_qset(struct sky2_hw *hw, u16 q, u32 wm)
550 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_CLR_RESET);
551 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_OPER_INIT);
552 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_FIFO_OP_ON);
553 sky2_write32(hw, Q_ADDR(q, Q_WM), wm);
556 /* Setup prefetch unit registers. This is the interface between
557 * hardware and driver list elements
559 static inline void sky2_prefetch_init(struct sky2_hw *hw, u32 qaddr,
562 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_RST_SET);
563 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_RST_CLR);
564 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_ADDR_HI), addr >> 32);
565 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_ADDR_LO), (u32) addr);
566 sky2_write16(hw, Y2_QADDR(qaddr, PREF_UNIT_LAST_IDX), last);
567 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_OP_ON);
569 sky2_read32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL));
572 static inline struct sky2_tx_le *get_tx_le(struct sky2_port *sky2)
574 struct sky2_tx_le *le = sky2->tx_le + sky2->tx_prod;
576 sky2->tx_prod = (sky2->tx_prod + 1) % TX_RING_SIZE;
581 * This is a workaround code taken from syskonnect sk98lin driver
582 * to deal with chip bug on Yukon EC rev 0 in the wraparound case.
584 static inline void sky2_put_idx(struct sky2_hw *hw, unsigned q,
585 u16 idx, u16 *last, u16 size)
587 if (is_ec_a1(hw) && idx < *last) {
588 u16 hwget = sky2_read16(hw, Y2_QADDR(q, PREF_UNIT_GET_IDX));
591 /* Start prefetching again */
592 sky2_write8(hw, Y2_QADDR(q, PREF_UNIT_FIFO_WM), 0xe0);
596 if (hwget == size - 1) {
597 /* set watermark to one list element */
598 sky2_write8(hw, Y2_QADDR(q, PREF_UNIT_FIFO_WM), 8);
600 /* set put index to first list element */
601 sky2_write16(hw, Y2_QADDR(q, PREF_UNIT_PUT_IDX), 0);
602 } else /* have hardware go to end of list */
603 sky2_write16(hw, Y2_QADDR(q, PREF_UNIT_PUT_IDX),
607 sky2_write16(hw, Y2_QADDR(q, PREF_UNIT_PUT_IDX), idx);
609 *last = sky2_read16(hw, Y2_QADDR(q, PREF_UNIT_PUT_IDX));
613 static inline struct sky2_rx_le *sky2_next_rx(struct sky2_port *sky2)
615 struct sky2_rx_le *le = sky2->rx_le + sky2->rx_put;
616 sky2->rx_put = (sky2->rx_put + 1) % RX_LE_SIZE;
620 /* Build description to hardware about buffer */
621 static inline void sky2_rx_add(struct sky2_port *sky2, struct ring_info *re)
623 struct sky2_rx_le *le;
624 u32 hi = (re->mapaddr >> 16) >> 16;
626 re->idx = sky2->rx_put;
627 if (sky2->rx_addr64 != hi) {
628 le = sky2_next_rx(sky2);
629 le->addr = cpu_to_le32(hi);
631 le->opcode = OP_ADDR64 | HW_OWNER;
632 sky2->rx_addr64 = hi;
635 le = sky2_next_rx(sky2);
636 le->addr = cpu_to_le32((u32) re->mapaddr);
637 le->length = cpu_to_le16(re->maplen);
639 le->opcode = OP_PACKET | HW_OWNER;
642 /* Tell receiver about new buffers. */
643 static inline void rx_set_put(struct net_device *dev)
645 struct sky2_port *sky2 = netdev_priv(dev);
647 if (sky2->rx_last_put != sky2->rx_put)
648 sky2_put_idx(sky2->hw, rxqaddr[sky2->port], sky2->rx_put,
649 &sky2->rx_last_put, RX_LE_SIZE);
652 /* Tell chip where to start receive checksum.
653 * Actually has two checksums, but set both same to avoid possible byte
656 static void rx_set_checksum(struct sky2_port *sky2)
658 struct sky2_rx_le *le;
660 le = sky2_next_rx(sky2);
661 le->addr = (ETH_HLEN << 16) | ETH_HLEN;
663 le->opcode = OP_TCPSTART | HW_OWNER;
665 sky2_write16(sky2->hw, Y2_QADDR(rxqaddr[sky2->port],
666 PREF_UNIT_PUT_IDX), sky2->rx_put);
667 sky2_read16(sky2->hw, Y2_QADDR(rxqaddr[sky2->port], PREF_UNIT_PUT_IDX));
669 sky2_write32(sky2->hw,
670 Q_ADDR(rxqaddr[sky2->port], Q_CSR),
671 sky2->rx_csum ? BMU_ENA_RX_CHKSUM : BMU_DIS_RX_CHKSUM);
676 /* Cleanout receive buffer area, assumes receiver hardware stopped */
677 static void sky2_rx_clean(struct sky2_port *sky2)
681 memset(sky2->rx_le, 0, RX_LE_BYTES);
682 for (i = 0; i < sky2->rx_pending; i++) {
683 struct ring_info *re = sky2->rx_ring + i;
686 pci_unmap_single(sky2->hw->pdev,
687 re->mapaddr, re->maplen,
695 #define roundup(x, y) ((((x)+((y)-1))/(y))*(y))
696 static inline unsigned sky2_rx_size(const struct sky2_port *sky2)
698 return roundup(sky2->netdev->mtu + ETH_HLEN + 4, 8);
702 * Allocate and setup receiver buffer pool.
703 * In case of 64 bit dma, there are 2X as many list elements
704 * available as ring entries
705 * and need to reserve one list element so we don't wrap around.
707 * It appears the hardware has a bug in the FIFO logic that
708 * cause it to hang if the FIFO gets overrun and the receive buffer
709 * is not aligned. This means we can't use skb_reserve to align
712 static int sky2_rx_fill(struct sky2_port *sky2)
715 unsigned size = sky2_rx_size(sky2);
717 pr_debug("rx_fill size=%d\n", size);
718 for (i = 0; i < sky2->rx_pending; i++) {
719 struct ring_info *re = sky2->rx_ring + i;
721 re->skb = dev_alloc_skb(size);
725 re->mapaddr = pci_map_single(sky2->hw->pdev, re->skb->data,
726 size, PCI_DMA_FROMDEVICE);
728 sky2_rx_add(sky2, re);
737 /* Bring up network interface. */
738 static int sky2_up(struct net_device *dev)
740 struct sky2_port *sky2 = netdev_priv(dev);
741 struct sky2_hw *hw = sky2->hw;
742 unsigned port = sky2->port;
743 u32 ramsize, rxspace;
746 if (netif_msg_ifup(sky2))
747 printk(KERN_INFO PFX "%s: enabling interface\n", dev->name);
749 /* must be power of 2 */
750 sky2->tx_le = pci_alloc_consistent(hw->pdev,
752 sizeof(struct sky2_tx_le),
757 sky2->tx_ring = kmalloc(TX_RING_SIZE * sizeof(struct ring_info),
761 sky2->tx_prod = sky2->tx_cons = 0;
762 memset(sky2->tx_ring, 0, TX_RING_SIZE * sizeof(struct ring_info));
764 sky2->rx_le = pci_alloc_consistent(hw->pdev, RX_LE_BYTES,
768 memset(sky2->rx_le, 0, RX_LE_BYTES);
770 sky2->rx_ring = kmalloc(sky2->rx_pending * sizeof(struct ring_info),
775 sky2_mac_init(hw, port);
777 /* Configure RAM buffers */
778 if (hw->chip_id == CHIP_ID_YUKON_FE ||
779 (hw->chip_id == CHIP_ID_YUKON_EC && hw->chip_rev == 2))
782 u8 e0 = sky2_read8(hw, B2_E_0);
783 ramsize = (e0 == 0) ? (128 * 1024) : (e0 * 4096);
787 rxspace = (2 * ramsize) / 3;
788 sky2_ramset(hw, rxqaddr[port], 0, rxspace);
789 sky2_ramset(hw, txqaddr[port], rxspace, ramsize - rxspace);
791 /* Make sure SyncQ is disabled */
792 sky2_write8(hw, RB_ADDR(port == 0 ? Q_XS1 : Q_XS2, RB_CTRL),
795 sky2_qset(hw, rxqaddr[port], is_pciex(hw) ? 0x80 : 0x600);
796 sky2_qset(hw, txqaddr[port], 0x600);
798 sky2->rx_put = sky2->rx_next = 0;
799 sky2_prefetch_init(hw, rxqaddr[port], sky2->rx_le_map, RX_LE_SIZE - 1);
801 rx_set_checksum(sky2);
803 err = sky2_rx_fill(sky2);
807 /* Give buffers to receiver */
808 sky2_write16(sky2->hw, Y2_QADDR(rxqaddr[port], PREF_UNIT_PUT_IDX),
810 sky2->rx_last_put = sky2_read16(sky2->hw,
811 Y2_QADDR(rxqaddr[port],
814 sky2_prefetch_init(hw, txqaddr[port], sky2->tx_le_map,
817 /* Enable interrupts from phy/mac for port */
818 hw->intr_mask |= (port == 0) ? Y2_IS_PORT_1 : Y2_IS_PORT_2;
819 sky2_write32(hw, B0_IMSK, hw->intr_mask);
824 pci_free_consistent(hw->pdev, RX_LE_BYTES,
825 sky2->rx_le, sky2->rx_le_map);
827 pci_free_consistent(hw->pdev,
828 TX_RING_SIZE * sizeof(struct sky2_tx_le),
829 sky2->tx_le, sky2->tx_le_map);
831 kfree(sky2->tx_ring);
833 kfree(sky2->rx_ring);
838 /* Modular subtraction in ring */
839 static inline int tx_dist(unsigned tail, unsigned head)
841 return (head >= tail ? head : head + TX_RING_SIZE) - tail;
844 /* Number of list elements available for next tx */
845 static inline int tx_avail(const struct sky2_port *sky2)
847 return sky2->tx_pending - tx_dist(sky2->tx_cons, sky2->tx_prod);
850 /* Estimate of number of transmit list elements required */
851 static inline unsigned tx_le_req(const struct sk_buff *skb)
855 count = sizeof(dma_addr_t) / sizeof(u32);
856 count += skb_shinfo(skb)->nr_frags * count;
858 if (skb_shinfo(skb)->tso_size)
868 * Put one packet in ring for transmit.
869 * A single packet can generate multiple list elements, and
870 * the number of ring elements will probably be less than the number
871 * of list elements used.
873 static int sky2_xmit_frame(struct sk_buff *skb, struct net_device *dev)
875 struct sky2_port *sky2 = netdev_priv(dev);
876 struct sky2_hw *hw = sky2->hw;
877 struct sky2_tx_le *le;
878 struct ring_info *re;
886 local_irq_save(flags);
887 if (!spin_trylock(&sky2->tx_lock)) {
888 local_irq_restore(flags);
889 return NETDEV_TX_LOCKED;
892 if (unlikely(tx_avail(sky2) < tx_le_req(skb))) {
893 netif_stop_queue(dev);
894 spin_unlock_irqrestore(&sky2->tx_lock, flags);
896 printk(KERN_WARNING PFX "%s: ring full when queue awake!\n",
898 return NETDEV_TX_BUSY;
901 if (unlikely(netif_msg_tx_queued(sky2)))
902 printk(KERN_DEBUG "%s: tx queued, slot %u, len %d\n",
903 dev->name, sky2->tx_prod, skb->len);
905 len = skb_headlen(skb);
906 mapping = pci_map_single(hw->pdev, skb->data, len, PCI_DMA_TODEVICE);
907 addr64 = (mapping >> 16) >> 16;
909 re = sky2->tx_ring + sky2->tx_prod;
911 /* Send high bits if changed */
912 if (addr64 != sky2->tx_addr64) {
913 le = get_tx_le(sky2);
914 le->tx.addr = cpu_to_le32(addr64);
916 le->opcode = OP_ADDR64 | HW_OWNER;
917 sky2->tx_addr64 = addr64;
920 /* Check for TCP Segmentation Offload */
921 mss = skb_shinfo(skb)->tso_size;
923 /* just drop the packet if non-linear expansion fails */
924 if (skb_header_cloned(skb) &&
925 pskb_expand_head(skb, 0, 0, GFP_ATOMIC)) {
926 dev_kfree_skb_any(skb);
930 mss += ((skb->h.th->doff - 5) * 4); /* TCP options */
931 mss += (skb->nh.iph->ihl * 4) + sizeof(struct tcphdr);
935 if (mss != sky2->tx_last_mss) {
936 le = get_tx_le(sky2);
937 le->tx.tso.size = cpu_to_le16(mss);
939 le->opcode = OP_LRGLEN | HW_OWNER;
941 sky2->tx_last_mss = mss;
944 /* Handle TCP checksum offload */
946 if (skb->ip_summed == CHECKSUM_HW) {
947 u16 hdr = skb->h.raw - skb->data;
948 u16 offset = hdr + skb->csum;
950 ctrl = CALSUM | WR_SUM | INIT_SUM | LOCK_SUM;
951 if (skb->nh.iph->protocol == IPPROTO_UDP)
954 le = get_tx_le(sky2);
955 le->tx.csum.start = cpu_to_le16(hdr);
956 le->tx.csum.offset = cpu_to_le16(offset);
957 le->length = 0; /* initial checksum value */
958 le->ctrl = 1; /* one packet */
959 le->opcode = OP_TCPLISW | HW_OWNER;
962 le = get_tx_le(sky2);
963 le->tx.addr = cpu_to_le32((u32) mapping);
964 le->length = cpu_to_le16(len);
966 le->opcode = mss ? (OP_LARGESEND | HW_OWNER) : (OP_PACKET | HW_OWNER);
968 /* Record the transmit mapping info */
970 re->mapaddr = mapping;
973 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
974 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
975 struct ring_info *fre;
977 mapping = pci_map_page(hw->pdev, frag->page, frag->page_offset,
978 frag->size, PCI_DMA_TODEVICE);
979 addr64 = (mapping >> 16) >> 16;
980 if (addr64 != sky2->tx_addr64) {
981 le = get_tx_le(sky2);
982 le->tx.addr = cpu_to_le32(addr64);
984 le->opcode = OP_ADDR64 | HW_OWNER;
985 sky2->tx_addr64 = addr64;
988 le = get_tx_le(sky2);
989 le->tx.addr = cpu_to_le32((u32) mapping);
990 le->length = cpu_to_le16(frag->size);
992 le->opcode = OP_BUFFER | HW_OWNER;
995 + ((re - sky2->tx_ring) + i + 1) % TX_RING_SIZE;
997 fre->mapaddr = mapping;
998 fre->maplen = frag->size;
1000 re->idx = sky2->tx_prod;
1003 sky2_put_idx(sky2->hw, txqaddr[sky2->port], sky2->tx_prod,
1004 &sky2->tx_last_put, TX_RING_SIZE);
1006 if (tx_avail(sky2) < MAX_SKB_TX_LE + 1)
1007 netif_stop_queue(dev);
1011 spin_unlock_irqrestore(&sky2->tx_lock, flags);
1013 dev->trans_start = jiffies;
1014 return NETDEV_TX_OK;
1018 * Free ring elements from starting at tx_cons until "done"
1020 * NB: the hardware will tell us about partial completion of multi-part
1021 * buffers; these are defered until completion.
1023 static void sky2_tx_complete(struct net_device *dev, u16 done)
1025 struct sky2_port *sky2 = netdev_priv(dev);
1028 if (netif_msg_tx_done(sky2))
1029 printk(KERN_DEBUG "%s: tx done, upto %u\n", dev->name, done);
1031 spin_lock(&sky2->tx_lock);
1033 while (sky2->tx_cons != done) {
1034 struct ring_info *re = sky2->tx_ring + sky2->tx_cons;
1035 struct sk_buff *skb;
1037 /* Check for partial status */
1038 if (tx_dist(sky2->tx_cons, done)
1039 < tx_dist(sky2->tx_cons, re->idx))
1043 pci_unmap_single(sky2->hw->pdev,
1044 re->mapaddr, re->maplen, PCI_DMA_TODEVICE);
1046 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
1047 struct ring_info *fre;
1049 sky2->tx_ring + (sky2->tx_cons + i +
1051 pci_unmap_page(sky2->hw->pdev, fre->mapaddr,
1052 fre->maplen, PCI_DMA_TODEVICE);
1055 dev_kfree_skb_any(skb);
1057 sky2->tx_cons = re->idx;
1061 if (netif_queue_stopped(dev) && tx_avail(sky2) > MAX_SKB_TX_LE)
1062 netif_wake_queue(dev);
1063 spin_unlock(&sky2->tx_lock);
1066 /* Cleanup all untransmitted buffers, assume transmitter not running */
1067 static inline void sky2_tx_clean(struct sky2_port *sky2)
1069 sky2_tx_complete(sky2->netdev, sky2->tx_prod);
1072 /* Network shutdown */
1073 static int sky2_down(struct net_device *dev)
1075 struct sky2_port *sky2 = netdev_priv(dev);
1076 struct sky2_hw *hw = sky2->hw;
1077 unsigned port = sky2->port;
1081 if (netif_msg_ifdown(sky2))
1082 printk(KERN_INFO PFX "%s: disabling interface\n", dev->name);
1084 netif_stop_queue(dev);
1086 sky2_phy_reset(hw, port);
1088 /* Stop transmitter */
1089 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), BMU_STOP);
1090 sky2_read32(hw, Q_ADDR(txqaddr[port], Q_CSR));
1092 sky2_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL),
1093 RB_RST_SET | RB_DIS_OP_MD);
1095 ctrl = gma_read16(hw, port, GM_GP_CTRL);
1096 ctrl &= ~(GM_GPCR_TX_ENA | GM_GPCR_RX_ENA);
1097 gma_write16(hw, port, GM_GP_CTRL, ctrl);
1099 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET);
1101 /* Workaround shared GMAC reset */
1102 if (!(hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0
1103 && port == 0 && hw->dev[1] && netif_running(hw->dev[1])))
1104 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_SET);
1106 /* Disable Force Sync bit and Enable Alloc bit */
1107 sky2_write8(hw, SK_REG(port, TXA_CTRL),
1108 TXA_DIS_FSYNC | TXA_DIS_ALLOC | TXA_STOP_RC);
1110 /* Stop Interval Timer and Limit Counter of Tx Arbiter */
1111 sky2_write32(hw, SK_REG(port, TXA_ITI_INI), 0L);
1112 sky2_write32(hw, SK_REG(port, TXA_LIM_INI), 0L);
1114 /* Reset the PCI FIFO of the async Tx queue */
1115 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR),
1116 BMU_RST_SET | BMU_FIFO_RST);
1118 /* Reset the Tx prefetch units */
1119 sky2_write32(hw, Y2_QADDR(txqaddr[port], PREF_UNIT_CTRL),
1122 sky2_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL), RB_RST_SET);
1125 * The RX Stop command will not work for Yukon-2 if the BMU does not
1126 * reach the end of packet and since we can't make sure that we have
1127 * incoming data, we must reset the BMU while it is not doing a DMA
1128 * transfer. Since it is possible that the RX path is still active,
1129 * the RX RAM buffer will be stopped first, so any possible incoming
1130 * data will not trigger a DMA. After the RAM buffer is stopped, the
1131 * BMU is polled until any DMA in progress is ended and only then it
1135 /* disable the RAM Buffer receive queue */
1136 sky2_write8(hw, RB_ADDR(rxqaddr[port], RB_CTRL), RB_DIS_OP_MD);
1138 for (i = 0; i < 0xffff; i++)
1139 if (sky2_read8(hw, RB_ADDR(rxqaddr[port], Q_RSL))
1140 == sky2_read8(hw, RB_ADDR(rxqaddr[port], Q_RL)))
1143 sky2_write32(hw, Q_ADDR(rxqaddr[port], Q_CSR),
1144 BMU_RST_SET | BMU_FIFO_RST);
1145 /* reset the Rx prefetch unit */
1146 sky2_write32(hw, Y2_QADDR(rxqaddr[port], PREF_UNIT_CTRL),
1149 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_SET);
1150 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_SET);
1152 /* turn off led's */
1153 sky2_write16(hw, B0_Y2LED, LED_STAT_OFF);
1155 sky2_tx_clean(sky2);
1156 sky2_rx_clean(sky2);
1158 pci_free_consistent(hw->pdev, RX_LE_BYTES,
1159 sky2->rx_le, sky2->rx_le_map);
1160 kfree(sky2->rx_ring);
1162 pci_free_consistent(hw->pdev,
1163 TX_RING_SIZE * sizeof(struct sky2_tx_le),
1164 sky2->tx_le, sky2->tx_le_map);
1165 kfree(sky2->tx_ring);
1170 static u16 sky2_phy_speed(const struct sky2_hw *hw, u16 aux)
1175 if (hw->chip_id == CHIP_ID_YUKON_FE)
1176 return (aux & PHY_M_PS_SPEED_100) ? SPEED_100 : SPEED_10;
1178 switch (aux & PHY_M_PS_SPEED_MSK) {
1179 case PHY_M_PS_SPEED_1000:
1181 case PHY_M_PS_SPEED_100:
1188 static void sky2_link_up(struct sky2_port *sky2)
1190 struct sky2_hw *hw = sky2->hw;
1191 unsigned port = sky2->port;
1194 /* disable Rx GMAC FIFO flush mode */
1195 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RX_F_FL_OFF);
1197 /* Enable Transmit FIFO Underrun */
1198 sky2_write8(hw, SK_REG(port, GMAC_IRQ_MSK), GMAC_DEF_MSK);
1200 reg = gma_read16(hw, port, GM_GP_CTRL);
1201 if (sky2->duplex == DUPLEX_FULL || sky2->autoneg == AUTONEG_ENABLE)
1202 reg |= GM_GPCR_DUP_FULL;
1205 reg |= GM_GPCR_RX_ENA | GM_GPCR_TX_ENA;
1206 gma_write16(hw, port, GM_GP_CTRL, reg);
1207 gma_read16(hw, port, GM_GP_CTRL);
1209 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_DEF_MSK);
1211 netif_carrier_on(sky2->netdev);
1212 netif_wake_queue(sky2->netdev);
1214 /* Turn on link LED */
1215 sky2_write8(hw, SK_REG(port, LNK_LED_REG),
1216 LINKLED_ON | LINKLED_BLINK_OFF | LINKLED_LINKSYNC_OFF);
1218 if (hw->chip_id == CHIP_ID_YUKON_XL) {
1219 u16 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
1221 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
1222 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, PHY_M_LEDC_LOS_CTRL(1) | /* LINK/ACT */
1223 PHY_M_LEDC_INIT_CTRL(sky2->speed ==
1225 PHY_M_LEDC_STA1_CTRL(sky2->speed ==
1226 SPEED_100 ? 7 : 0) |
1227 PHY_M_LEDC_STA0_CTRL(sky2->speed ==
1228 SPEED_1000 ? 7 : 0));
1229 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
1232 if (netif_msg_link(sky2))
1233 printk(KERN_INFO PFX
1234 "%s: Link is up at %d Mbps, %s duplex, flowcontrol %s\n",
1235 sky2->netdev->name, sky2->speed,
1236 sky2->duplex == DUPLEX_FULL ? "full" : "half",
1237 (sky2->tx_pause && sky2->rx_pause) ? "both" :
1238 sky2->tx_pause ? "tx" : sky2->rx_pause ? "rx" : "none");
1241 static void sky2_link_down(struct sky2_port *sky2)
1243 struct sky2_hw *hw = sky2->hw;
1244 unsigned port = sky2->port;
1247 gm_phy_write(hw, port, PHY_MARV_INT_MASK, 0);
1249 reg = gma_read16(hw, port, GM_GP_CTRL);
1250 reg &= ~(GM_GPCR_RX_ENA | GM_GPCR_TX_ENA);
1251 gma_write16(hw, port, GM_GP_CTRL, reg);
1252 gma_read16(hw, port, GM_GP_CTRL); /* PCI post */
1254 if (sky2->rx_pause && !sky2->tx_pause) {
1255 /* restore Asymmetric Pause bit */
1256 gm_phy_write(hw, port, PHY_MARV_AUNE_ADV,
1257 gm_phy_read(hw, port, PHY_MARV_AUNE_ADV)
1261 sky2_phy_reset(hw, port);
1263 netif_carrier_off(sky2->netdev);
1264 netif_stop_queue(sky2->netdev);
1266 /* Turn on link LED */
1267 sky2_write8(hw, SK_REG(port, LNK_LED_REG), LINKLED_OFF);
1269 if (netif_msg_link(sky2))
1270 printk(KERN_INFO PFX "%s: Link is down.\n", sky2->netdev->name);
1271 sky2_phy_init(hw, port);
1274 static int sky2_autoneg_done(struct sky2_port *sky2, u16 aux)
1276 struct sky2_hw *hw = sky2->hw;
1277 unsigned port = sky2->port;
1280 lpa = gm_phy_read(hw, port, PHY_MARV_AUNE_LP);
1282 if (lpa & PHY_M_AN_RF) {
1283 printk(KERN_ERR PFX "%s: remote fault", sky2->netdev->name);
1287 if (hw->chip_id != CHIP_ID_YUKON_FE &&
1288 gm_phy_read(hw, port, PHY_MARV_1000T_STAT) & PHY_B_1000S_MSF) {
1289 printk(KERN_ERR PFX "%s: master/slave fault",
1290 sky2->netdev->name);
1294 if (!(aux & PHY_M_PS_SPDUP_RES)) {
1295 printk(KERN_ERR PFX "%s: speed/duplex mismatch",
1296 sky2->netdev->name);
1300 sky2->duplex = (aux & PHY_M_PS_FULL_DUP) ? DUPLEX_FULL : DUPLEX_HALF;
1302 sky2->speed = sky2_phy_speed(hw, aux);
1304 /* Pause bits are offset (9..8) */
1305 if (hw->chip_id == CHIP_ID_YUKON_XL)
1308 sky2->rx_pause = (aux & PHY_M_PS_RX_P_EN) != 0;
1309 sky2->tx_pause = (aux & PHY_M_PS_TX_P_EN) != 0;
1311 if ((sky2->tx_pause || sky2->rx_pause)
1312 && !(sky2->speed < SPEED_1000 && sky2->duplex == DUPLEX_HALF))
1313 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON);
1315 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
1321 * Interrrupt from PHY are handled in tasklet (soft irq)
1322 * because accessing phy registers requires spin wait which might
1323 * cause excess interrupt latency.
1325 static void sky2_phy_task(unsigned long data)
1327 struct sky2_port *sky2 = (struct sky2_port *)data;
1328 struct sky2_hw *hw = sky2->hw;
1329 u16 istatus, phystat;
1331 spin_lock(&hw->phy_lock);
1332 istatus = gm_phy_read(hw, sky2->port, PHY_MARV_INT_STAT);
1333 phystat = gm_phy_read(hw, sky2->port, PHY_MARV_PHY_STAT);
1335 if (netif_msg_intr(sky2))
1336 printk(KERN_INFO PFX "%s: phy interrupt status 0x%x 0x%x\n",
1337 sky2->netdev->name, istatus, phystat);
1339 if (istatus & PHY_M_IS_AN_COMPL) {
1340 if (sky2_autoneg_done(sky2, phystat) == 0)
1345 if (istatus & PHY_M_IS_LSP_CHANGE)
1346 sky2->speed = sky2_phy_speed(hw, phystat);
1348 if (istatus & PHY_M_IS_DUP_CHANGE)
1350 (phystat & PHY_M_PS_FULL_DUP) ? DUPLEX_FULL : DUPLEX_HALF;
1352 if (istatus & PHY_M_IS_LST_CHANGE) {
1353 if (phystat & PHY_M_PS_LINK_UP)
1356 sky2_link_down(sky2);
1359 spin_unlock(&hw->phy_lock);
1361 local_irq_disable();
1362 hw->intr_mask |= (sky2->port == 0) ? Y2_IS_IRQ_PHY1 : Y2_IS_IRQ_PHY2;
1363 sky2_write32(hw, B0_IMSK, hw->intr_mask);
1367 static void sky2_tx_timeout(struct net_device *dev)
1369 struct sky2_port *sky2 = netdev_priv(dev);
1371 if (netif_msg_timer(sky2))
1372 printk(KERN_ERR PFX "%s: tx timeout\n", dev->name);
1374 sky2_write32(sky2->hw, Q_ADDR(txqaddr[sky2->port], Q_CSR), BMU_STOP);
1375 sky2_read32(sky2->hw, Q_ADDR(txqaddr[sky2->port], Q_CSR));
1377 sky2_tx_clean(sky2);
1380 static int sky2_change_mtu(struct net_device *dev, int new_mtu)
1384 if (new_mtu < ETH_ZLEN || new_mtu > ETH_JUMBO_MTU)
1387 if (netif_running(dev))
1392 if (netif_running(dev))
1399 * Receive one packet.
1400 * For small packets or errors, just reuse existing skb.
1401 * For larger pakects, get new buffer.
1403 static struct sk_buff *sky2_receive(struct sky2_hw *hw, unsigned port,
1404 u16 length, u32 status)
1406 struct net_device *dev = hw->dev[port];
1407 struct sky2_port *sky2 = netdev_priv(dev);
1408 struct ring_info *re = sky2->rx_ring + sky2->rx_next;
1409 struct sk_buff *skb = NULL;
1410 const unsigned int bufsize = sky2_rx_size(sky2);
1412 if (unlikely(netif_msg_rx_status(sky2)))
1413 printk(KERN_DEBUG PFX "%s: rx slot %u status 0x%x len %d\n",
1414 dev->name, sky2->rx_next, status, length);
1416 sky2->rx_next = (sky2->rx_next + 1) % sky2->rx_pending;
1418 if (!(status & GMR_FS_RX_OK)
1419 || (status & GMR_FS_ANY_ERR)
1420 || (length << 16) != (status & GMR_FS_LEN)
1421 || length > bufsize)
1424 if (length < RX_COPY_THRESHOLD) {
1425 skb = alloc_skb(length + 2, GFP_ATOMIC);
1429 skb_reserve(skb, 2);
1430 pci_dma_sync_single_for_cpu(sky2->hw->pdev, re->mapaddr,
1431 length, PCI_DMA_FROMDEVICE);
1432 memcpy(skb->data, re->skb->data, length);
1433 pci_dma_sync_single_for_device(sky2->hw->pdev, re->mapaddr,
1434 length, PCI_DMA_FROMDEVICE);
1436 struct sk_buff *nskb;
1438 nskb = dev_alloc_skb(bufsize);
1444 pci_unmap_single(sky2->hw->pdev, re->mapaddr,
1445 re->maplen, PCI_DMA_FROMDEVICE);
1446 prefetch(skb->data);
1448 re->mapaddr = pci_map_single(sky2->hw->pdev, nskb->data,
1449 bufsize, PCI_DMA_FROMDEVICE);
1450 re->maplen = bufsize;
1454 skb_put(skb, length);
1455 skb->protocol = eth_type_trans(skb, dev);
1456 dev->last_rx = jiffies;
1459 sky2_rx_add(sky2, re);
1464 if (status & GMR_FS_GOOD_FC)
1467 if (netif_msg_rx_err(sky2))
1468 printk(KERN_INFO PFX "%s: rx error, status 0x%x length %d\n",
1469 sky2->netdev->name, status, length);
1471 if (status & (GMR_FS_LONG_ERR | GMR_FS_UN_SIZE))
1472 sky2->net_stats.rx_length_errors++;
1473 if (status & GMR_FS_FRAGMENT)
1474 sky2->net_stats.rx_frame_errors++;
1475 if (status & GMR_FS_CRC_ERR)
1476 sky2->net_stats.rx_crc_errors++;
1477 if (status & GMR_FS_RX_FF_OV)
1478 sky2->net_stats.rx_fifo_errors++;
1483 /* Transmit ring index in reported status block is encoded as:
1485 * | TXS2 | TXA2 | TXS1 | TXA1
1487 static inline u16 tx_index(u8 port, u32 status, u16 len)
1490 return status & 0xfff;
1492 return ((status >> 24) & 0xff) | (len & 0xf) << 8;
1496 * Both ports share the same status interrupt, therefore there is only
1499 static int sky2_poll(struct net_device *dev, int *budget)
1501 struct sky2_port *sky2 = netdev_priv(dev);
1502 struct sky2_hw *hw = sky2->hw;
1503 unsigned int to_do = min(dev->quota, *budget);
1504 unsigned int work_done = 0;
1506 unsigned char summed[2] = { CHECKSUM_NONE, CHECKSUM_NONE };
1507 unsigned int csum[2];
1509 hwidx = sky2_read16(hw, STAT_PUT_IDX);
1510 BUG_ON(hwidx >= STATUS_RING_SIZE);
1512 while (hw->st_idx != hwidx && work_done < to_do) {
1513 struct sky2_status_le *le = hw->st_le + hw->st_idx;
1514 struct sk_buff *skb;
1519 status = le32_to_cpu(le->status);
1520 length = le16_to_cpu(le->length);
1523 BUG_ON(port >= hw->ports || hw->dev[port] == NULL);
1525 switch (le->opcode & ~HW_OWNER) {
1527 skb = sky2_receive(hw, port, length, status);
1529 /* Add hw checksum if available */
1530 skb->ip_summed = summed[port];
1531 skb->csum = csum[port];
1533 netif_receive_skb(skb);
1537 /* Clear for next packet */
1539 summed[port] = CHECKSUM_NONE;
1544 /* Save computed checksum for next rx */
1545 csum[port] = le16_to_cpu(status & 0xffff);
1546 summed[port] = CHECKSUM_HW;
1550 sky2_tx_complete(hw->dev[port],
1551 tx_index(port, status, length));
1554 case OP_RXTIMESTAMP:
1558 if (net_ratelimit())
1559 printk(KERN_WARNING PFX
1560 "unknown status opcode 0x%x\n",
1565 hw->st_idx = (hw->st_idx + 1) % STATUS_RING_SIZE;
1566 if (hw->st_idx == hwidx) {
1567 hwidx = sky2_read16(hw, STAT_PUT_IDX);
1575 rx_set_put(hw->dev[0]);
1578 rx_set_put(hw->dev[1]);
1580 *budget -= work_done;
1581 dev->quota -= work_done;
1582 if (work_done < to_do) {
1584 * Another chip workaround, need to restart TX timer if status
1585 * LE was handled. WA_DEV_43_418
1588 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_STOP);
1589 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_START);
1592 hw->intr_mask |= Y2_IS_STAT_BMU;
1593 sky2_write32(hw, B0_IMSK, hw->intr_mask);
1594 sky2_read32(hw, B0_IMSK);
1595 netif_rx_complete(dev);
1598 return work_done >= to_do;
1602 static void sky2_hw_error(struct sky2_hw *hw, unsigned port, u32 status)
1604 struct net_device *dev = hw->dev[port];
1606 printk(KERN_INFO PFX "%s: hw error interrupt status 0x%x\n",
1609 if (status & Y2_IS_PAR_RD1) {
1610 printk(KERN_ERR PFX "%s: ram data read parity error\n",
1613 sky2_write16(hw, RAM_BUFFER(port, B3_RI_CTRL), RI_CLR_RD_PERR);
1616 if (status & Y2_IS_PAR_WR1) {
1617 printk(KERN_ERR PFX "%s: ram data write parity error\n",
1620 sky2_write16(hw, RAM_BUFFER(port, B3_RI_CTRL), RI_CLR_WR_PERR);
1623 if (status & Y2_IS_PAR_MAC1) {
1624 printk(KERN_ERR PFX "%s: MAC parity error\n", dev->name);
1625 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_CLI_TX_PE);
1628 if (status & Y2_IS_PAR_RX1) {
1629 printk(KERN_ERR PFX "%s: RX parity error\n", dev->name);
1630 sky2_write32(hw, Q_ADDR(rxqaddr[port], Q_CSR), BMU_CLR_IRQ_PAR);
1633 if (status & Y2_IS_TCP_TXA1) {
1634 printk(KERN_ERR PFX "%s: TCP segmentation error\n", dev->name);
1635 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), BMU_CLR_IRQ_TCP);
1639 static void sky2_hw_intr(struct sky2_hw *hw)
1641 u32 status = sky2_read32(hw, B0_HWE_ISRC);
1643 if (status & Y2_IS_TIST_OV)
1644 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ);
1646 if (status & (Y2_IS_MST_ERR | Y2_IS_IRQ_STAT)) {
1649 pci_read_config_word(hw->pdev, PCI_STATUS, &pci_err);
1650 printk(KERN_ERR PFX "%s: pci hw error (0x%x)\n",
1651 pci_name(hw->pdev), pci_err);
1653 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
1654 pci_write_config_word(hw->pdev, PCI_STATUS,
1655 pci_err | PCI_STATUS_ERROR_BITS);
1656 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
1659 if (status & Y2_IS_PCI_EXP) {
1660 /* PCI-Express uncorrectable Error occured */
1663 pci_read_config_dword(hw->pdev, PEX_UNC_ERR_STAT, &pex_err);
1665 printk(KERN_ERR PFX "%s: pci express error (0x%x)\n",
1666 pci_name(hw->pdev), pex_err);
1668 /* clear the interrupt */
1669 sky2_write32(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
1670 pci_write_config_dword(hw->pdev, PEX_UNC_ERR_STAT,
1672 sky2_write32(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
1674 if (pex_err & PEX_FATAL_ERRORS) {
1675 u32 hwmsk = sky2_read32(hw, B0_HWE_IMSK);
1676 hwmsk &= ~Y2_IS_PCI_EXP;
1677 sky2_write32(hw, B0_HWE_IMSK, hwmsk);
1681 if (status & Y2_HWE_L1_MASK)
1682 sky2_hw_error(hw, 0, status);
1684 if (status & Y2_HWE_L1_MASK)
1685 sky2_hw_error(hw, 1, status);
1688 static void sky2_mac_intr(struct sky2_hw *hw, unsigned port)
1690 struct net_device *dev = hw->dev[port];
1691 struct sky2_port *sky2 = netdev_priv(dev);
1692 u8 status = sky2_read8(hw, SK_REG(port, GMAC_IRQ_SRC));
1694 if (netif_msg_intr(sky2))
1695 printk(KERN_INFO PFX "%s: mac interrupt status 0x%x\n",
1698 if (status & GM_IS_RX_FF_OR) {
1699 ++sky2->net_stats.rx_fifo_errors;
1700 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_CLI_RX_FO);
1703 if (status & GM_IS_TX_FF_UR) {
1704 ++sky2->net_stats.tx_fifo_errors;
1705 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_CLI_TX_FU);
1709 static void sky2_phy_intr(struct sky2_hw *hw, unsigned port)
1711 struct net_device *dev = hw->dev[port];
1712 struct sky2_port *sky2 = netdev_priv(dev);
1714 hw->intr_mask &= ~(port == 0 ? Y2_IS_IRQ_PHY1 : Y2_IS_IRQ_PHY2);
1715 sky2_write32(hw, B0_IMSK, hw->intr_mask);
1716 tasklet_schedule(&sky2->phy_task);
1719 static irqreturn_t sky2_intr(int irq, void *dev_id, struct pt_regs *regs)
1721 struct sky2_hw *hw = dev_id;
1724 status = sky2_read32(hw, B0_Y2_SP_ISRC2);
1725 if (status == 0 || status == ~0)
1728 if (status & Y2_IS_HW_ERR)
1731 /* Do NAPI for Rx and Tx status */
1732 if ((status & Y2_IS_STAT_BMU) && netif_rx_schedule_test(hw->dev[0])) {
1733 sky2_write32(hw, STAT_CTRL, SC_STAT_CLR_IRQ);
1735 hw->intr_mask &= ~Y2_IS_STAT_BMU;
1736 sky2_write32(hw, B0_IMSK, hw->intr_mask);
1737 __netif_rx_schedule(hw->dev[0]);
1740 if (status & Y2_IS_IRQ_PHY1)
1741 sky2_phy_intr(hw, 0);
1743 if (status & Y2_IS_IRQ_PHY2)
1744 sky2_phy_intr(hw, 1);
1746 if (status & Y2_IS_IRQ_MAC1)
1747 sky2_mac_intr(hw, 0);
1749 if (status & Y2_IS_IRQ_MAC2)
1750 sky2_mac_intr(hw, 1);
1752 sky2_write32(hw, B0_Y2_SP_ICR, 2);
1754 sky2_read32(hw, B0_IMSK);
1759 #ifdef CONFIG_NET_POLL_CONTROLLER
1760 static void sky2_netpoll(struct net_device *dev)
1762 struct sky2_port *sky2 = netdev_priv(dev);
1764 sky2_intr(sky2->hw->pdev->irq, sky2->hw, NULL);
1768 /* Chip internal frequency for clock calculations */
1769 static inline u32 sky2_khz(const struct sky2_hw *hw)
1771 switch (hw->chip_id) {
1772 case CHIP_ID_YUKON_EC:
1773 return 125000; /* 125 Mhz */
1774 case CHIP_ID_YUKON_FE:
1775 return 100000; /* 100 Mhz */
1776 default: /* YUKON_XL */
1777 return 156000; /* 156 Mhz */
1781 static inline u32 sky2_ms2clk(const struct sky2_hw *hw, u32 ms)
1783 return sky2_khz(hw) * ms;
1786 static inline u32 sky2_us2clk(const struct sky2_hw *hw, u32 us)
1788 return (sky2_khz(hw) * us) / 1000;
1791 static int sky2_reset(struct sky2_hw *hw)
1798 ctst = sky2_read32(hw, B0_CTST);
1800 sky2_write8(hw, B0_CTST, CS_RST_CLR);
1801 hw->chip_id = sky2_read8(hw, B2_CHIP_ID);
1802 if (hw->chip_id < CHIP_ID_YUKON_XL || hw->chip_id > CHIP_ID_YUKON_FE) {
1803 printk(KERN_ERR PFX "%s: unsupported chip type 0x%x\n",
1804 pci_name(hw->pdev), hw->chip_id);
1808 /* ring for status responses */
1809 hw->st_le = pci_alloc_consistent(hw->pdev, STATUS_LE_BYTES,
1815 if (hw->chip_id <= CHIP_ID_YUKON_EC) {
1816 sky2_write8(hw, B28_Y2_ASF_STAT_CMD, Y2_ASF_RESET);
1817 sky2_write16(hw, B0_CTST, Y2_ASF_DISABLE);
1821 sky2_write8(hw, B0_CTST, CS_RST_SET);
1822 sky2_write8(hw, B0_CTST, CS_RST_CLR);
1824 /* clear PCI errors, if any */
1825 pci_read_config_word(hw->pdev, PCI_STATUS, &status);
1826 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
1827 pci_write_config_word(hw->pdev, PCI_STATUS,
1828 status | PCI_STATUS_ERROR_BITS);
1830 sky2_write8(hw, B0_CTST, CS_MRST_CLR);
1832 /* clear any PEX errors */
1835 pci_write_config_dword(hw->pdev, PEX_UNC_ERR_STAT,
1837 pci_read_config_word(hw->pdev, PEX_LNK_STAT, &lstat);
1840 pmd_type = sky2_read8(hw, B2_PMD_TYP);
1841 hw->copper = !(pmd_type == 'L' || pmd_type == 'S');
1844 t8 = sky2_read8(hw, B2_Y2_HW_RES);
1845 if ((t8 & CFG_DUAL_MAC_MSK) == CFG_DUAL_MAC_MSK) {
1846 if (!(sky2_read8(hw, B2_Y2_CLK_GATE) & Y2_STATUS_LNK2_INAC))
1849 hw->chip_rev = (sky2_read8(hw, B2_MAC_CFG) & CFG_CHIP_R_MSK) >> 4;
1851 /* switch power to VCC (WA for VAUX problem) */
1852 sky2_write8(hw, B0_POWER_CTRL,
1853 PC_VAUX_ENA | PC_VCC_ENA | PC_VAUX_OFF | PC_VCC_ON);
1855 /* disable Core Clock Division, */
1856 sky2_write32(hw, B2_Y2_CLK_CTRL, Y2_CLK_DIV_DIS);
1858 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1)
1859 /* enable bits are inverted */
1860 sky2_write8(hw, B2_Y2_CLK_GATE,
1861 Y2_PCI_CLK_LNK1_DIS | Y2_COR_CLK_LNK1_DIS |
1862 Y2_CLK_GAT_LNK1_DIS | Y2_PCI_CLK_LNK2_DIS |
1863 Y2_COR_CLK_LNK2_DIS | Y2_CLK_GAT_LNK2_DIS);
1865 sky2_write8(hw, B2_Y2_CLK_GATE, 0);
1867 /* Turn off phy power saving */
1868 pci_read_config_dword(hw->pdev, PCI_DEV_REG1, &power);
1869 power &= ~(PCI_Y2_PHY1_POWD | PCI_Y2_PHY2_POWD);
1871 /* looks like this xl is back asswards .. */
1872 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1) {
1873 power |= PCI_Y2_PHY1_COMA;
1875 power |= PCI_Y2_PHY2_COMA;
1877 pci_write_config_dword(hw->pdev, PCI_DEV_REG1, power);
1879 for (i = 0; i < hw->ports; i++) {
1880 sky2_write8(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_SET);
1881 sky2_write8(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_CLR);
1884 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
1886 /* Clear I2C IRQ noise */
1887 sky2_write32(hw, B2_I2C_IRQ, 1);
1889 /* turn off hardware timer (unused) */
1890 sky2_write8(hw, B2_TI_CTRL, TIM_STOP);
1891 sky2_write8(hw, B2_TI_CTRL, TIM_CLR_IRQ);
1893 sky2_write8(hw, B0_Y2LED, LED_STAT_ON);
1895 /* Turn on descriptor polling (every 75us) */
1896 sky2_write32(hw, B28_DPT_INI, sky2_us2clk(hw, 75));
1897 sky2_write8(hw, B28_DPT_CTRL, DPT_START);
1899 /* Turn off receive timestamp */
1900 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_STOP);
1901 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ);
1903 /* enable the Tx Arbiters */
1904 for (i = 0; i < hw->ports; i++)
1905 sky2_write8(hw, SK_REG(i, TXA_CTRL), TXA_ENA_ARB);
1907 /* Initialize ram interface */
1908 for (i = 0; i < hw->ports; i++) {
1909 sky2_write8(hw, RAM_BUFFER(i, B3_RI_CTRL), RI_RST_CLR);
1911 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_R1), SK_RI_TO_53);
1912 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XA1), SK_RI_TO_53);
1913 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XS1), SK_RI_TO_53);
1914 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_R1), SK_RI_TO_53);
1915 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XA1), SK_RI_TO_53);
1916 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XS1), SK_RI_TO_53);
1917 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_R2), SK_RI_TO_53);
1918 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XA2), SK_RI_TO_53);
1919 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XS2), SK_RI_TO_53);
1920 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_R2), SK_RI_TO_53);
1921 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XA2), SK_RI_TO_53);
1922 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XS2), SK_RI_TO_53);
1928 /* change Max. Read Request Size to 2048 bytes */
1929 pci_read_config_word(hw->pdev, PEX_DEV_CTRL, &pctrl);
1930 pctrl &= ~PEX_DC_MAX_RRS_MSK;
1931 pctrl |= PEX_DC_MAX_RD_RQ_SIZE(4);
1934 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
1935 pci_write_config_word(hw->pdev, PEX_DEV_CTRL, pctrl);
1936 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
1939 sky2_write32(hw, B0_HWE_IMSK, Y2_HWE_ALL_MASK);
1941 spin_lock_bh(&hw->phy_lock);
1942 for (i = 0; i < hw->ports; i++)
1943 sky2_phy_reset(hw, i);
1944 spin_unlock_bh(&hw->phy_lock);
1946 memset(hw->st_le, 0, STATUS_LE_BYTES);
1949 sky2_write32(hw, STAT_CTRL, SC_STAT_RST_SET);
1950 sky2_write32(hw, STAT_CTRL, SC_STAT_RST_CLR);
1952 sky2_write32(hw, STAT_LIST_ADDR_LO, hw->st_dma);
1953 sky2_write32(hw, STAT_LIST_ADDR_HI, (u64) hw->st_dma >> 32);
1955 /* Set the list last index */
1956 sky2_write16(hw, STAT_LAST_IDX, STATUS_RING_SIZE - 1);
1958 sky2_write32(hw, STAT_TX_TIMER_INI, sky2_ms2clk(hw, 10));
1960 /* These status setup values are copied from SysKonnect's driver */
1962 /* WA for dev. #4.3 */
1963 sky2_write16(hw, STAT_TX_IDX_TH, 0xfff); /* Tx Threshold */
1965 /* set Status-FIFO watermark */
1966 sky2_write8(hw, STAT_FIFO_WM, 0x21); /* WA for dev. #4.18 */
1968 /* set Status-FIFO ISR watermark */
1969 sky2_write8(hw, STAT_FIFO_ISR_WM, 0x07); /* WA for dev. #4.18 */
1972 sky2_write16(hw, STAT_TX_IDX_TH, 0x000a);
1974 /* set Status-FIFO watermark */
1975 sky2_write8(hw, STAT_FIFO_WM, 0x10);
1977 /* set Status-FIFO ISR watermark */
1978 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0)
1979 sky2_write8(hw, STAT_FIFO_ISR_WM, 0x10);
1982 sky2_write8(hw, STAT_FIFO_ISR_WM, 0x04);
1984 sky2_write32(hw, STAT_ISR_TIMER_INI, 0x0190);
1987 /* enable status unit */
1988 sky2_write32(hw, STAT_CTRL, SC_STAT_OP_ON);
1990 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_START);
1991 sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_START);
1992 sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_START);
1997 static inline u32 sky2_supported_modes(const struct sky2_hw *hw)
2001 modes = SUPPORTED_10baseT_Half
2002 | SUPPORTED_10baseT_Full
2003 | SUPPORTED_100baseT_Half
2004 | SUPPORTED_100baseT_Full
2005 | SUPPORTED_Autoneg | SUPPORTED_TP;
2007 if (hw->chip_id != CHIP_ID_YUKON_FE)
2008 modes |= SUPPORTED_1000baseT_Half
2009 | SUPPORTED_1000baseT_Full;
2011 modes = SUPPORTED_1000baseT_Full | SUPPORTED_FIBRE
2012 | SUPPORTED_Autoneg;
2016 static int sky2_get_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
2018 struct sky2_port *sky2 = netdev_priv(dev);
2019 struct sky2_hw *hw = sky2->hw;
2021 ecmd->transceiver = XCVR_INTERNAL;
2022 ecmd->supported = sky2_supported_modes(hw);
2023 ecmd->phy_address = PHY_ADDR_MARV;
2025 ecmd->supported = SUPPORTED_10baseT_Half
2026 | SUPPORTED_10baseT_Full
2027 | SUPPORTED_100baseT_Half
2028 | SUPPORTED_100baseT_Full
2029 | SUPPORTED_1000baseT_Half
2030 | SUPPORTED_1000baseT_Full
2031 | SUPPORTED_Autoneg | SUPPORTED_TP;
2032 ecmd->port = PORT_TP;
2034 ecmd->port = PORT_FIBRE;
2036 ecmd->advertising = sky2->advertising;
2037 ecmd->autoneg = sky2->autoneg;
2038 ecmd->speed = sky2->speed;
2039 ecmd->duplex = sky2->duplex;
2043 static int sky2_set_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
2045 struct sky2_port *sky2 = netdev_priv(dev);
2046 const struct sky2_hw *hw = sky2->hw;
2047 u32 supported = sky2_supported_modes(hw);
2049 if (ecmd->autoneg == AUTONEG_ENABLE) {
2050 ecmd->advertising = supported;
2056 switch (ecmd->speed) {
2058 if (ecmd->duplex == DUPLEX_FULL)
2059 setting = SUPPORTED_1000baseT_Full;
2060 else if (ecmd->duplex == DUPLEX_HALF)
2061 setting = SUPPORTED_1000baseT_Half;
2066 if (ecmd->duplex == DUPLEX_FULL)
2067 setting = SUPPORTED_100baseT_Full;
2068 else if (ecmd->duplex == DUPLEX_HALF)
2069 setting = SUPPORTED_100baseT_Half;
2075 if (ecmd->duplex == DUPLEX_FULL)
2076 setting = SUPPORTED_10baseT_Full;
2077 else if (ecmd->duplex == DUPLEX_HALF)
2078 setting = SUPPORTED_10baseT_Half;
2086 if ((setting & supported) == 0)
2089 sky2->speed = ecmd->speed;
2090 sky2->duplex = ecmd->duplex;
2093 sky2->autoneg = ecmd->autoneg;
2094 sky2->advertising = ecmd->advertising;
2096 if (netif_running(dev)) {
2104 static void sky2_get_drvinfo(struct net_device *dev,
2105 struct ethtool_drvinfo *info)
2107 struct sky2_port *sky2 = netdev_priv(dev);
2109 strcpy(info->driver, DRV_NAME);
2110 strcpy(info->version, DRV_VERSION);
2111 strcpy(info->fw_version, "N/A");
2112 strcpy(info->bus_info, pci_name(sky2->hw->pdev));
2115 static const struct sky2_stat {
2116 char name[ETH_GSTRING_LEN];
2119 { "tx_bytes", GM_TXO_OK_HI },
2120 { "rx_bytes", GM_RXO_OK_HI },
2121 { "tx_broadcast", GM_TXF_BC_OK },
2122 { "rx_broadcast", GM_RXF_BC_OK },
2123 { "tx_multicast", GM_TXF_MC_OK },
2124 { "rx_multicast", GM_RXF_MC_OK },
2125 { "tx_unicast", GM_TXF_UC_OK },
2126 { "rx_unicast", GM_RXF_UC_OK },
2127 { "tx_mac_pause", GM_TXF_MPAUSE },
2128 { "rx_mac_pause", GM_RXF_MPAUSE },
2129 { "collisions", GM_TXF_SNG_COL },
2130 { "late_collision",GM_TXF_LAT_COL },
2131 { "aborted", GM_TXF_ABO_COL },
2132 { "multi_collisions", GM_TXF_MUL_COL },
2133 { "fifo_underrun", GM_TXE_FIFO_UR },
2134 { "fifo_overflow", GM_RXE_FIFO_OV },
2135 { "rx_toolong", GM_RXF_LNG_ERR },
2136 { "rx_jabber", GM_RXF_JAB_PKT },
2137 { "rx_runt", GM_RXE_FRAG },
2138 { "rx_too_long", GM_RXF_LNG_ERR },
2139 { "rx_fcs_error", GM_RXF_FCS_ERR },
2142 static u32 sky2_get_rx_csum(struct net_device *dev)
2144 struct sky2_port *sky2 = netdev_priv(dev);
2146 return sky2->rx_csum;
2149 static int sky2_set_rx_csum(struct net_device *dev, u32 data)
2151 struct sky2_port *sky2 = netdev_priv(dev);
2153 sky2->rx_csum = data;
2155 sky2_write32(sky2->hw, Q_ADDR(rxqaddr[sky2->port], Q_CSR),
2156 data ? BMU_ENA_RX_CHKSUM : BMU_DIS_RX_CHKSUM);
2161 static u32 sky2_get_msglevel(struct net_device *netdev)
2163 struct sky2_port *sky2 = netdev_priv(netdev);
2164 return sky2->msg_enable;
2167 static void sky2_phy_stats(struct sky2_port *sky2, u64 * data, unsigned count)
2169 struct sky2_hw *hw = sky2->hw;
2170 unsigned port = sky2->port;
2173 data[0] = (u64) gma_read32(hw, port, GM_TXO_OK_HI) << 32
2174 | (u64) gma_read32(hw, port, GM_TXO_OK_LO);
2175 data[1] = (u64) gma_read32(hw, port, GM_RXO_OK_HI) << 32
2176 | (u64) gma_read32(hw, port, GM_RXO_OK_LO);
2178 for (i = 2; i < count; i++)
2179 data[i] = (u64) gma_read32(hw, port, sky2_stats[i].offset);
2182 static void sky2_set_msglevel(struct net_device *netdev, u32 value)
2184 struct sky2_port *sky2 = netdev_priv(netdev);
2185 sky2->msg_enable = value;
2188 static int sky2_get_stats_count(struct net_device *dev)
2190 return ARRAY_SIZE(sky2_stats);
2193 static void sky2_get_ethtool_stats(struct net_device *dev,
2194 struct ethtool_stats *stats, u64 * data)
2196 struct sky2_port *sky2 = netdev_priv(dev);
2198 sky2_phy_stats(sky2, data, ARRAY_SIZE(sky2_stats));
2201 static void sky2_get_strings(struct net_device *dev, u32 stringset, u8 * data)
2205 switch (stringset) {
2207 for (i = 0; i < ARRAY_SIZE(sky2_stats); i++)
2208 memcpy(data + i * ETH_GSTRING_LEN,
2209 sky2_stats[i].name, ETH_GSTRING_LEN);
2214 /* Use hardware MIB variables for critical path statistics and
2215 * transmit feedback not reported at interrupt.
2216 * Other errors are accounted for in interrupt handler.
2218 static struct net_device_stats *sky2_get_stats(struct net_device *dev)
2220 struct sky2_port *sky2 = netdev_priv(dev);
2223 sky2_phy_stats(sky2, data, ARRAY_SIZE(data));
2225 sky2->net_stats.tx_bytes = data[0];
2226 sky2->net_stats.rx_bytes = data[1];
2227 sky2->net_stats.tx_packets = data[2] + data[4] + data[6];
2228 sky2->net_stats.rx_packets = data[3] + data[5] + data[7];
2229 sky2->net_stats.multicast = data[5] + data[7];
2230 sky2->net_stats.collisions = data[10];
2231 sky2->net_stats.tx_aborted_errors = data[12];
2233 return &sky2->net_stats;
2236 static int sky2_set_mac_address(struct net_device *dev, void *p)
2238 struct sky2_port *sky2 = netdev_priv(dev);
2239 struct sockaddr *addr = p;
2242 if (!is_valid_ether_addr(addr->sa_data))
2243 return -EADDRNOTAVAIL;
2246 memcpy(dev->dev_addr, addr->sa_data, ETH_ALEN);
2247 memcpy_toio(sky2->hw->regs + B2_MAC_1 + sky2->port * 8,
2248 dev->dev_addr, ETH_ALEN);
2249 memcpy_toio(sky2->hw->regs + B2_MAC_2 + sky2->port * 8,
2250 dev->dev_addr, ETH_ALEN);
2251 if (dev->flags & IFF_UP)
2256 static void sky2_set_multicast(struct net_device *dev)
2258 struct sky2_port *sky2 = netdev_priv(dev);
2259 struct sky2_hw *hw = sky2->hw;
2260 unsigned port = sky2->port;
2261 struct dev_mc_list *list = dev->mc_list;
2265 memset(filter, 0, sizeof(filter));
2267 reg = gma_read16(hw, port, GM_RX_CTRL);
2268 reg |= GM_RXCR_UCF_ENA;
2270 if (dev->flags & IFF_PROMISC) /* promiscious */
2271 reg &= ~(GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA);
2272 else if ((dev->flags & IFF_ALLMULTI) || dev->mc_count > 16) /* all multicast */
2273 memset(filter, 0xff, sizeof(filter));
2274 else if (dev->mc_count == 0) /* no multicast */
2275 reg &= ~GM_RXCR_MCF_ENA;
2278 reg |= GM_RXCR_MCF_ENA;
2280 for (i = 0; list && i < dev->mc_count; i++, list = list->next) {
2281 u32 bit = ether_crc(ETH_ALEN, list->dmi_addr) & 0x3f;
2282 filter[bit / 8] |= 1 << (bit % 8);
2286 gma_write16(hw, port, GM_MC_ADDR_H1,
2287 (u16) filter[0] | ((u16) filter[1] << 8));
2288 gma_write16(hw, port, GM_MC_ADDR_H2,
2289 (u16) filter[2] | ((u16) filter[3] << 8));
2290 gma_write16(hw, port, GM_MC_ADDR_H3,
2291 (u16) filter[4] | ((u16) filter[5] << 8));
2292 gma_write16(hw, port, GM_MC_ADDR_H4,
2293 (u16) filter[6] | ((u16) filter[7] << 8));
2295 gma_write16(hw, port, GM_RX_CTRL, reg);
2298 /* Can have one global because blinking is controlled by
2299 * ethtool and that is always under RTNL mutex
2301 static inline void sky2_led(struct sky2_hw *hw, unsigned port, int on)
2305 spin_lock_bh(&hw->phy_lock);
2306 switch (hw->chip_id) {
2307 case CHIP_ID_YUKON_XL:
2308 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
2309 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
2310 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
2311 on ? (PHY_M_LEDC_LOS_CTRL(1) |
2312 PHY_M_LEDC_INIT_CTRL(7) |
2313 PHY_M_LEDC_STA1_CTRL(7) |
2314 PHY_M_LEDC_STA0_CTRL(7))
2317 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
2321 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, 0);
2322 gm_phy_write(hw, port, PHY_MARV_LED_OVER,
2323 on ? PHY_M_LED_MO_DUP(MO_LED_ON) |
2324 PHY_M_LED_MO_10(MO_LED_ON) |
2325 PHY_M_LED_MO_100(MO_LED_ON) |
2326 PHY_M_LED_MO_1000(MO_LED_ON) |
2327 PHY_M_LED_MO_RX(MO_LED_ON)
2328 : PHY_M_LED_MO_DUP(MO_LED_OFF) |
2329 PHY_M_LED_MO_10(MO_LED_OFF) |
2330 PHY_M_LED_MO_100(MO_LED_OFF) |
2331 PHY_M_LED_MO_1000(MO_LED_OFF) |
2332 PHY_M_LED_MO_RX(MO_LED_OFF));
2335 spin_unlock_bh(&hw->phy_lock);
2338 /* blink LED's for finding board */
2339 static int sky2_phys_id(struct net_device *dev, u32 data)
2341 struct sky2_port *sky2 = netdev_priv(dev);
2342 struct sky2_hw *hw = sky2->hw;
2343 unsigned port = sky2->port;
2344 u16 ledctrl, ledover = 0;
2348 if (!data || data > (u32) (MAX_SCHEDULE_TIMEOUT / HZ))
2349 ms = jiffies_to_msecs(MAX_SCHEDULE_TIMEOUT);
2353 /* save initial values */
2354 spin_lock_bh(&hw->phy_lock);
2355 if (hw->chip_id == CHIP_ID_YUKON_XL) {
2356 u16 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
2357 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
2358 ledctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
2359 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
2361 ledctrl = gm_phy_read(hw, port, PHY_MARV_LED_CTRL);
2362 ledover = gm_phy_read(hw, port, PHY_MARV_LED_OVER);
2364 spin_unlock_bh(&hw->phy_lock);
2367 sky2_led(hw, port, onoff);
2370 if (msleep_interruptible(250))
2371 break; /* interrupted */
2375 /* resume regularly scheduled programming */
2376 spin_lock_bh(&hw->phy_lock);
2377 if (hw->chip_id == CHIP_ID_YUKON_XL) {
2378 u16 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
2379 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
2380 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ledctrl);
2381 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
2383 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, ledctrl);
2384 gm_phy_write(hw, port, PHY_MARV_LED_OVER, ledover);
2386 spin_unlock_bh(&hw->phy_lock);
2391 static void sky2_get_pauseparam(struct net_device *dev,
2392 struct ethtool_pauseparam *ecmd)
2394 struct sky2_port *sky2 = netdev_priv(dev);
2396 ecmd->tx_pause = sky2->tx_pause;
2397 ecmd->rx_pause = sky2->rx_pause;
2398 ecmd->autoneg = sky2->autoneg;
2401 static int sky2_set_pauseparam(struct net_device *dev,
2402 struct ethtool_pauseparam *ecmd)
2404 struct sky2_port *sky2 = netdev_priv(dev);
2407 sky2->autoneg = ecmd->autoneg;
2408 sky2->tx_pause = ecmd->tx_pause != 0;
2409 sky2->rx_pause = ecmd->rx_pause != 0;
2411 if (netif_running(dev)) {
2420 static void sky2_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
2422 struct sky2_port *sky2 = netdev_priv(dev);
2424 wol->supported = WAKE_MAGIC;
2425 wol->wolopts = sky2->wol ? WAKE_MAGIC : 0;
2428 static int sky2_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
2430 struct sky2_port *sky2 = netdev_priv(dev);
2431 struct sky2_hw *hw = sky2->hw;
2433 if (wol->wolopts != WAKE_MAGIC && wol->wolopts != 0)
2436 sky2->wol = wol->wolopts == WAKE_MAGIC;
2439 memcpy_toio(hw->regs + WOL_MAC_ADDR, dev->dev_addr, ETH_ALEN);
2441 sky2_write16(hw, WOL_CTRL_STAT,
2442 WOL_CTL_ENA_PME_ON_MAGIC_PKT |
2443 WOL_CTL_ENA_MAGIC_PKT_UNIT);
2445 sky2_write16(hw, WOL_CTRL_STAT, WOL_CTL_DEFAULT);
2451 static void sky2_get_ringparam(struct net_device *dev,
2452 struct ethtool_ringparam *ering)
2454 struct sky2_port *sky2 = netdev_priv(dev);
2456 ering->rx_max_pending = RX_MAX_PENDING;
2457 ering->rx_mini_max_pending = 0;
2458 ering->rx_jumbo_max_pending = 0;
2459 ering->tx_max_pending = TX_RING_SIZE - 1;
2461 ering->rx_pending = sky2->rx_pending;
2462 ering->rx_mini_pending = 0;
2463 ering->rx_jumbo_pending = 0;
2464 ering->tx_pending = sky2->tx_pending;
2467 static int sky2_set_ringparam(struct net_device *dev,
2468 struct ethtool_ringparam *ering)
2470 struct sky2_port *sky2 = netdev_priv(dev);
2473 if (ering->rx_pending > RX_MAX_PENDING ||
2474 ering->rx_pending < 8 ||
2475 ering->tx_pending < MAX_SKB_TX_LE ||
2476 ering->tx_pending > TX_RING_SIZE - 1)
2479 if (netif_running(dev))
2482 sky2->rx_pending = ering->rx_pending;
2483 sky2->tx_pending = ering->tx_pending;
2485 if (netif_running(dev))
2491 static int sky2_get_regs_len(struct net_device *dev)
2497 * Returns copy of control register region
2498 * Note: access to the RAM address register set will cause timeouts.
2500 static void sky2_get_regs(struct net_device *dev, struct ethtool_regs *regs,
2503 const struct sky2_port *sky2 = netdev_priv(dev);
2504 const void __iomem *io = sky2->hw->regs;
2506 BUG_ON(regs->len < B3_RI_WTO_R1);
2508 memset(p, 0, regs->len);
2510 memcpy_fromio(p, io, B3_RAM_ADDR);
2512 memcpy_fromio(p + B3_RI_WTO_R1,
2514 regs->len - B3_RI_WTO_R1);
2517 static struct ethtool_ops sky2_ethtool_ops = {
2518 .get_settings = sky2_get_settings,
2519 .set_settings = sky2_set_settings,
2520 .get_drvinfo = sky2_get_drvinfo,
2521 .get_msglevel = sky2_get_msglevel,
2522 .set_msglevel = sky2_set_msglevel,
2523 .get_regs_len = sky2_get_regs_len,
2524 .get_regs = sky2_get_regs,
2525 .get_link = ethtool_op_get_link,
2526 .get_sg = ethtool_op_get_sg,
2527 .set_sg = ethtool_op_set_sg,
2528 .get_tx_csum = ethtool_op_get_tx_csum,
2529 .set_tx_csum = ethtool_op_set_tx_csum,
2530 .get_tso = ethtool_op_get_tso,
2531 .set_tso = ethtool_op_set_tso,
2532 .get_rx_csum = sky2_get_rx_csum,
2533 .set_rx_csum = sky2_set_rx_csum,
2534 .get_strings = sky2_get_strings,
2535 .get_ringparam = sky2_get_ringparam,
2536 .set_ringparam = sky2_set_ringparam,
2537 .get_pauseparam = sky2_get_pauseparam,
2538 .set_pauseparam = sky2_set_pauseparam,
2540 .get_wol = sky2_get_wol,
2541 .set_wol = sky2_set_wol,
2543 .phys_id = sky2_phys_id,
2544 .get_stats_count = sky2_get_stats_count,
2545 .get_ethtool_stats = sky2_get_ethtool_stats,
2548 /* Initialize network device */
2549 static __devinit struct net_device *sky2_init_netdev(struct sky2_hw *hw,
2550 unsigned port, int highmem)
2552 struct sky2_port *sky2;
2553 struct net_device *dev = alloc_etherdev(sizeof(*sky2));
2556 printk(KERN_ERR "sky2 etherdev alloc failed");
2560 SET_MODULE_OWNER(dev);
2561 SET_NETDEV_DEV(dev, &hw->pdev->dev);
2562 dev->open = sky2_up;
2563 dev->stop = sky2_down;
2564 dev->hard_start_xmit = sky2_xmit_frame;
2565 dev->get_stats = sky2_get_stats;
2566 dev->set_multicast_list = sky2_set_multicast;
2567 dev->set_mac_address = sky2_set_mac_address;
2568 dev->change_mtu = sky2_change_mtu;
2569 SET_ETHTOOL_OPS(dev, &sky2_ethtool_ops);
2570 dev->tx_timeout = sky2_tx_timeout;
2571 dev->watchdog_timeo = TX_WATCHDOG;
2573 dev->poll = sky2_poll;
2574 dev->weight = NAPI_WEIGHT;
2575 #ifdef CONFIG_NET_POLL_CONTROLLER
2576 dev->poll_controller = sky2_netpoll;
2579 sky2 = netdev_priv(dev);
2582 sky2->msg_enable = netif_msg_init(debug, default_msg);
2584 spin_lock_init(&sky2->tx_lock);
2585 /* Auto speed and flow control */
2586 sky2->autoneg = AUTONEG_ENABLE;
2591 sky2->advertising = sky2_supported_modes(hw);
2593 tasklet_init(&sky2->phy_task, sky2_phy_task, (unsigned long)sky2);
2594 sky2->tx_pending = TX_DEF_PENDING;
2595 sky2->rx_pending = is_ec_a1(hw) ? 8 : RX_DEF_PENDING;
2597 hw->dev[port] = dev;
2601 dev->features |= NETIF_F_LLTX | NETIF_F_TSO;
2603 dev->features |= NETIF_F_HIGHDMA;
2604 dev->features |= NETIF_F_IP_CSUM | NETIF_F_SG;
2606 /* read the mac address */
2607 memcpy_fromio(dev->dev_addr, hw->regs + B2_MAC_1 + port * 8, ETH_ALEN);
2609 /* device is off until link detection */
2610 netif_carrier_off(dev);
2611 netif_stop_queue(dev);
2616 static inline void sky2_show_addr(struct net_device *dev)
2618 const struct sky2_port *sky2 = netdev_priv(dev);
2620 if (netif_msg_probe(sky2))
2621 printk(KERN_INFO PFX "%s: addr %02x:%02x:%02x:%02x:%02x:%02x\n",
2623 dev->dev_addr[0], dev->dev_addr[1], dev->dev_addr[2],
2624 dev->dev_addr[3], dev->dev_addr[4], dev->dev_addr[5]);
2627 static int __devinit sky2_probe(struct pci_dev *pdev,
2628 const struct pci_device_id *ent)
2630 struct net_device *dev, *dev1 = NULL;
2632 int err, using_dac = 0;
2634 err = pci_enable_device(pdev);
2636 printk(KERN_ERR PFX "%s cannot enable PCI device\n",
2641 err = pci_request_regions(pdev, DRV_NAME);
2643 printk(KERN_ERR PFX "%s cannot obtain PCI resources\n",
2648 pci_set_master(pdev);
2650 if (sizeof(dma_addr_t) > sizeof(u32)) {
2651 err = pci_set_dma_mask(pdev, DMA_64BIT_MASK);
2657 err = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
2659 printk(KERN_ERR PFX "%s no usable DMA configuration\n",
2661 goto err_out_free_regions;
2665 /* byte swap decriptors in hardware */
2669 pci_read_config_dword(pdev, PCI_DEV_REG2, ®);
2670 reg |= PCI_REV_DESC;
2671 pci_write_config_dword(pdev, PCI_DEV_REG2, reg);
2676 hw = kmalloc(sizeof(*hw), GFP_KERNEL);
2678 printk(KERN_ERR PFX "%s: cannot allocate hardware struct\n",
2680 goto err_out_free_regions;
2683 memset(hw, 0, sizeof(*hw));
2685 spin_lock_init(&hw->phy_lock);
2687 hw->regs = ioremap_nocache(pci_resource_start(pdev, 0), 0x4000);
2689 printk(KERN_ERR PFX "%s: cannot map device registers\n",
2691 goto err_out_free_hw;
2694 err = sky2_reset(hw);
2696 goto err_out_iounmap;
2698 printk(KERN_INFO PFX "addr 0x%lx irq %d Yukon-%s (0x%x) rev %d\n",
2699 pci_resource_start(pdev, 0), pdev->irq,
2700 yukon_name[hw->chip_id - CHIP_ID_YUKON],
2701 hw->chip_id, hw->chip_rev);
2703 dev = sky2_init_netdev(hw, 0, using_dac);
2705 goto err_out_free_pci;
2707 err = register_netdev(dev);
2709 printk(KERN_ERR PFX "%s: cannot register net device\n",
2711 goto err_out_free_netdev;
2714 sky2_show_addr(dev);
2716 if (hw->ports > 1 && (dev1 = sky2_init_netdev(hw, 1, using_dac))) {
2717 if (register_netdev(dev1) == 0)
2718 sky2_show_addr(dev1);
2720 /* Failure to register second port need not be fatal */
2721 printk(KERN_WARNING PFX
2722 "register of second port failed\n");
2728 err = request_irq(pdev->irq, sky2_intr, SA_SHIRQ, DRV_NAME, hw);
2730 printk(KERN_ERR PFX "%s: cannot assign irq %d\n",
2731 pci_name(pdev), pdev->irq);
2732 goto err_out_unregister;
2735 hw->intr_mask = Y2_IS_BASE;
2736 sky2_write32(hw, B0_IMSK, hw->intr_mask);
2738 pci_set_drvdata(pdev, hw);
2744 unregister_netdev(dev1);
2747 unregister_netdev(dev);
2748 err_out_free_netdev:
2751 sky2_write8(hw, B0_CTST, CS_RST_SET);
2752 pci_free_consistent(hw->pdev, STATUS_LE_BYTES, hw->st_le, hw->st_dma);
2757 err_out_free_regions:
2758 pci_release_regions(pdev);
2759 pci_disable_device(pdev);
2764 static void __devexit sky2_remove(struct pci_dev *pdev)
2766 struct sky2_hw *hw = pci_get_drvdata(pdev);
2767 struct net_device *dev0, *dev1;
2775 unregister_netdev(dev1);
2776 unregister_netdev(dev0);
2778 sky2_write32(hw, B0_IMSK, 0);
2779 sky2_write16(hw, B0_Y2LED, LED_STAT_OFF);
2780 sky2_write8(hw, B0_CTST, CS_RST_SET);
2782 free_irq(pdev->irq, hw);
2783 pci_free_consistent(pdev, STATUS_LE_BYTES, hw->st_le, hw->st_dma);
2784 pci_release_regions(pdev);
2785 pci_disable_device(pdev);
2792 pci_set_drvdata(pdev, NULL);
2796 static int sky2_suspend(struct pci_dev *pdev, pm_message_t state)
2798 struct sky2_hw *hw = pci_get_drvdata(pdev);
2801 for (i = 0; i < 2; i++) {
2802 struct net_device *dev = hw->dev[i];
2805 struct sky2_port *sky2 = netdev_priv(dev);
2806 if (netif_running(dev)) {
2807 netif_carrier_off(dev);
2810 netif_device_detach(dev);
2815 pci_save_state(pdev);
2816 pci_enable_wake(pdev, pci_choose_state(pdev, state), wol);
2817 pci_disable_device(pdev);
2818 pci_set_power_state(pdev, pci_choose_state(pdev, state));
2823 static int sky2_resume(struct pci_dev *pdev)
2825 struct sky2_hw *hw = pci_get_drvdata(pdev);
2828 pci_set_power_state(pdev, PCI_D0);
2829 pci_restore_state(pdev);
2830 pci_enable_wake(pdev, PCI_D0, 0);
2834 for (i = 0; i < 2; i++) {
2835 struct net_device *dev = hw->dev[i];
2837 netif_device_attach(dev);
2838 if (netif_running(dev))
2846 static struct pci_driver sky2_driver = {
2848 .id_table = sky2_id_table,
2849 .probe = sky2_probe,
2850 .remove = __devexit_p(sky2_remove),
2852 .suspend = sky2_suspend,
2853 .resume = sky2_resume,
2857 static int __init sky2_init_module(void)
2859 return pci_module_init(&sky2_driver);
2862 static void __exit sky2_cleanup_module(void)
2864 pci_unregister_driver(&sky2_driver);
2867 module_init(sky2_init_module);
2868 module_exit(sky2_cleanup_module);
2870 MODULE_DESCRIPTION("Marvell Yukon 2 Gigabit Ethernet driver");
2871 MODULE_AUTHOR("Stephen Hemminger <shemminger@osdl.org>");
2872 MODULE_LICENSE("GPL");