2 * New driver for Marvell Yukon 2 chipset.
3 * Based on earlier sk98lin, and skge driver.
5 * This driver intentionally does not support all the features
6 * of the original driver such as link fail-over and link management because
7 * those should be done at higher levels.
9 * Copyright (C) 2005 Stephen Hemminger <shemminger@osdl.org>
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License.
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
25 #include <linux/crc32.h>
26 #include <linux/kernel.h>
27 #include <linux/version.h>
28 #include <linux/module.h>
29 #include <linux/netdevice.h>
30 #include <linux/dma-mapping.h>
31 #include <linux/etherdevice.h>
32 #include <linux/ethtool.h>
33 #include <linux/pci.h>
35 #include <linux/tcp.h>
37 #include <linux/delay.h>
38 #include <linux/workqueue.h>
39 #include <linux/if_vlan.h>
40 #include <linux/prefetch.h>
41 #include <linux/mii.h>
45 #if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
46 #define SKY2_VLAN_TAG_USED 1
51 #define DRV_NAME "sky2"
52 #define DRV_VERSION "1.10"
53 #define PFX DRV_NAME " "
56 * The Yukon II chipset takes 64 bit command blocks (called list elements)
57 * that are organized into three (receive, transmit, status) different rings
61 #define RX_LE_SIZE 1024
62 #define RX_LE_BYTES (RX_LE_SIZE*sizeof(struct sky2_rx_le))
63 #define RX_MAX_PENDING (RX_LE_SIZE/6 - 2)
64 #define RX_DEF_PENDING RX_MAX_PENDING
65 #define RX_SKB_ALIGN 8
66 #define RX_BUF_WRITE 16
68 #define TX_RING_SIZE 512
69 #define TX_DEF_PENDING (TX_RING_SIZE - 1)
70 #define TX_MIN_PENDING 64
71 #define MAX_SKB_TX_LE (4 + (sizeof(dma_addr_t)/sizeof(u32))*MAX_SKB_FRAGS)
73 #define STATUS_RING_SIZE 2048 /* 2 ports * (TX + 2*RX) */
74 #define STATUS_LE_BYTES (STATUS_RING_SIZE*sizeof(struct sky2_status_le))
75 #define TX_WATCHDOG (5 * HZ)
76 #define NAPI_WEIGHT 64
77 #define PHY_RETRIES 1000
79 #define RING_NEXT(x,s) (((x)+1) & ((s)-1))
81 static const u32 default_msg =
82 NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_LINK
83 | NETIF_MSG_TIMER | NETIF_MSG_TX_ERR | NETIF_MSG_RX_ERR
84 | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN;
86 static int debug = -1; /* defaults above */
87 module_param(debug, int, 0);
88 MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
90 static int copybreak __read_mostly = 128;
91 module_param(copybreak, int, 0);
92 MODULE_PARM_DESC(copybreak, "Receive copy threshold");
94 static int disable_msi = 0;
95 module_param(disable_msi, int, 0);
96 MODULE_PARM_DESC(disable_msi, "Disable Message Signaled Interrupt (MSI)");
98 static int idle_timeout = 0;
99 module_param(idle_timeout, int, 0);
100 MODULE_PARM_DESC(idle_timeout, "Watchdog timer for lost interrupts (ms)");
102 static const struct pci_device_id sky2_id_table[] = {
103 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, 0x9000) },
104 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, 0x9E00) },
105 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4b00) }, /* DGE-560T */
106 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4001) }, /* DGE-550SX */
107 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4B02) }, /* DGE-560SX */
108 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4340) },
109 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4341) },
110 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4342) },
111 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4343) },
112 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4344) },
113 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4345) },
114 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4346) },
115 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4347) },
116 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4350) },
117 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4351) },
118 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4352) },
119 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4353) },
120 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4356) },
121 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4360) },
122 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4361) },
123 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4362) },
124 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4363) },
125 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4364) },
126 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4365) },
127 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4366) },
128 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4367) },
129 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4368) },
130 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4369) },
134 MODULE_DEVICE_TABLE(pci, sky2_id_table);
136 /* Avoid conditionals by using array */
137 static const unsigned txqaddr[] = { Q_XA1, Q_XA2 };
138 static const unsigned rxqaddr[] = { Q_R1, Q_R2 };
139 static const u32 portirq_msk[] = { Y2_IS_PORT_1, Y2_IS_PORT_2 };
141 /* This driver supports yukon2 chipset only */
142 static const char *yukon2_name[] = {
144 "EC Ultra", /* 0xb4 */
145 "UNKNOWN", /* 0xb5 */
150 /* Access to external PHY */
151 static int gm_phy_write(struct sky2_hw *hw, unsigned port, u16 reg, u16 val)
155 gma_write16(hw, port, GM_SMI_DATA, val);
156 gma_write16(hw, port, GM_SMI_CTRL,
157 GM_SMI_CT_PHY_AD(PHY_ADDR_MARV) | GM_SMI_CT_REG_AD(reg));
159 for (i = 0; i < PHY_RETRIES; i++) {
160 if (!(gma_read16(hw, port, GM_SMI_CTRL) & GM_SMI_CT_BUSY))
165 printk(KERN_WARNING PFX "%s: phy write timeout\n", hw->dev[port]->name);
169 static int __gm_phy_read(struct sky2_hw *hw, unsigned port, u16 reg, u16 *val)
173 gma_write16(hw, port, GM_SMI_CTRL, GM_SMI_CT_PHY_AD(PHY_ADDR_MARV)
174 | GM_SMI_CT_REG_AD(reg) | GM_SMI_CT_OP_RD);
176 for (i = 0; i < PHY_RETRIES; i++) {
177 if (gma_read16(hw, port, GM_SMI_CTRL) & GM_SMI_CT_RD_VAL) {
178 *val = gma_read16(hw, port, GM_SMI_DATA);
188 static u16 gm_phy_read(struct sky2_hw *hw, unsigned port, u16 reg)
192 if (__gm_phy_read(hw, port, reg, &v) != 0)
193 printk(KERN_WARNING PFX "%s: phy read timeout\n", hw->dev[port]->name);
197 static void sky2_set_power_state(struct sky2_hw *hw, pci_power_t state)
202 pr_debug("sky2_set_power_state %d\n", state);
203 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
205 power_control = sky2_pci_read16(hw, hw->pm_cap + PCI_PM_PMC);
206 vaux = (sky2_read16(hw, B0_CTST) & Y2_VAUX_AVAIL) &&
207 (power_control & PCI_PM_CAP_PME_D3cold);
209 power_control = sky2_pci_read16(hw, hw->pm_cap + PCI_PM_CTRL);
211 power_control |= PCI_PM_CTRL_PME_STATUS;
212 power_control &= ~(PCI_PM_CTRL_STATE_MASK);
216 /* switch power to VCC (WA for VAUX problem) */
217 sky2_write8(hw, B0_POWER_CTRL,
218 PC_VAUX_ENA | PC_VCC_ENA | PC_VAUX_OFF | PC_VCC_ON);
220 /* disable Core Clock Division, */
221 sky2_write32(hw, B2_Y2_CLK_CTRL, Y2_CLK_DIV_DIS);
223 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1)
224 /* enable bits are inverted */
225 sky2_write8(hw, B2_Y2_CLK_GATE,
226 Y2_PCI_CLK_LNK1_DIS | Y2_COR_CLK_LNK1_DIS |
227 Y2_CLK_GAT_LNK1_DIS | Y2_PCI_CLK_LNK2_DIS |
228 Y2_COR_CLK_LNK2_DIS | Y2_CLK_GAT_LNK2_DIS);
230 sky2_write8(hw, B2_Y2_CLK_GATE, 0);
232 if (hw->chip_id == CHIP_ID_YUKON_EC_U) {
235 sky2_pci_write32(hw, PCI_DEV_REG3, 0);
236 reg1 = sky2_pci_read32(hw, PCI_DEV_REG4);
237 reg1 &= P_ASPM_CONTROL_MSK;
238 sky2_pci_write32(hw, PCI_DEV_REG4, reg1);
239 sky2_pci_write32(hw, PCI_DEV_REG5, 0);
246 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1)
247 sky2_write8(hw, B2_Y2_CLK_GATE, 0);
249 /* enable bits are inverted */
250 sky2_write8(hw, B2_Y2_CLK_GATE,
251 Y2_PCI_CLK_LNK1_DIS | Y2_COR_CLK_LNK1_DIS |
252 Y2_CLK_GAT_LNK1_DIS | Y2_PCI_CLK_LNK2_DIS |
253 Y2_COR_CLK_LNK2_DIS | Y2_CLK_GAT_LNK2_DIS);
255 /* switch power to VAUX */
256 if (vaux && state != PCI_D3cold)
257 sky2_write8(hw, B0_POWER_CTRL,
258 (PC_VAUX_ENA | PC_VCC_ENA |
259 PC_VAUX_ON | PC_VCC_OFF));
262 printk(KERN_ERR PFX "Unknown power state %d\n", state);
265 sky2_pci_write16(hw, hw->pm_cap + PCI_PM_CTRL, power_control);
266 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
269 static void sky2_gmac_reset(struct sky2_hw *hw, unsigned port)
273 /* disable all GMAC IRQ's */
274 sky2_write8(hw, SK_REG(port, GMAC_IRQ_MSK), 0);
275 /* disable PHY IRQs */
276 gm_phy_write(hw, port, PHY_MARV_INT_MASK, 0);
278 gma_write16(hw, port, GM_MC_ADDR_H1, 0); /* clear MC hash */
279 gma_write16(hw, port, GM_MC_ADDR_H2, 0);
280 gma_write16(hw, port, GM_MC_ADDR_H3, 0);
281 gma_write16(hw, port, GM_MC_ADDR_H4, 0);
283 reg = gma_read16(hw, port, GM_RX_CTRL);
284 reg |= GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA;
285 gma_write16(hw, port, GM_RX_CTRL, reg);
288 /* flow control to advertise bits */
289 static const u16 copper_fc_adv[] = {
291 [FC_TX] = PHY_M_AN_ASP,
292 [FC_RX] = PHY_M_AN_PC,
293 [FC_BOTH] = PHY_M_AN_PC | PHY_M_AN_ASP,
296 /* flow control to advertise bits when using 1000BaseX */
297 static const u16 fiber_fc_adv[] = {
298 [FC_BOTH] = PHY_M_P_BOTH_MD_X,
299 [FC_TX] = PHY_M_P_ASYM_MD_X,
300 [FC_RX] = PHY_M_P_SYM_MD_X,
301 [FC_NONE] = PHY_M_P_NO_PAUSE_X,
304 /* flow control to GMA disable bits */
305 static const u16 gm_fc_disable[] = {
306 [FC_NONE] = GM_GPCR_FC_RX_DIS | GM_GPCR_FC_TX_DIS,
307 [FC_TX] = GM_GPCR_FC_RX_DIS,
308 [FC_RX] = GM_GPCR_FC_TX_DIS,
313 static void sky2_phy_init(struct sky2_hw *hw, unsigned port)
315 struct sky2_port *sky2 = netdev_priv(hw->dev[port]);
316 u16 ctrl, ct1000, adv, pg, ledctrl, ledover, reg;
318 if (sky2->autoneg == AUTONEG_ENABLE &&
319 !(hw->chip_id == CHIP_ID_YUKON_XL || hw->chip_id == CHIP_ID_YUKON_EC_U)) {
320 u16 ectrl = gm_phy_read(hw, port, PHY_MARV_EXT_CTRL);
322 ectrl &= ~(PHY_M_EC_M_DSC_MSK | PHY_M_EC_S_DSC_MSK |
324 ectrl |= PHY_M_EC_MAC_S(MAC_TX_CLK_25_MHZ);
326 if (hw->chip_id == CHIP_ID_YUKON_EC)
327 ectrl |= PHY_M_EC_DSC_2(2) | PHY_M_EC_DOWN_S_ENA;
329 ectrl |= PHY_M_EC_M_DSC(2) | PHY_M_EC_S_DSC(3);
331 gm_phy_write(hw, port, PHY_MARV_EXT_CTRL, ectrl);
334 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
335 if (sky2_is_copper(hw)) {
336 if (hw->chip_id == CHIP_ID_YUKON_FE) {
337 /* enable automatic crossover */
338 ctrl |= PHY_M_PC_MDI_XMODE(PHY_M_PC_ENA_AUTO) >> 1;
340 /* disable energy detect */
341 ctrl &= ~PHY_M_PC_EN_DET_MSK;
343 /* enable automatic crossover */
344 ctrl |= PHY_M_PC_MDI_XMODE(PHY_M_PC_ENA_AUTO);
346 if (sky2->autoneg == AUTONEG_ENABLE &&
347 (hw->chip_id == CHIP_ID_YUKON_XL || hw->chip_id == CHIP_ID_YUKON_EC_U)) {
348 ctrl &= ~PHY_M_PC_DSC_MSK;
349 ctrl |= PHY_M_PC_DSC(2) | PHY_M_PC_DOWN_S_ENA;
353 /* workaround for deviation #4.88 (CRC errors) */
354 /* disable Automatic Crossover */
356 ctrl &= ~PHY_M_PC_MDIX_MSK;
359 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
361 /* special setup for PHY 88E1112 Fiber */
362 if (hw->chip_id == CHIP_ID_YUKON_XL && !sky2_is_copper(hw)) {
363 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
365 /* Fiber: select 1000BASE-X only mode MAC Specific Ctrl Reg. */
366 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 2);
367 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
368 ctrl &= ~PHY_M_MAC_MD_MSK;
369 ctrl |= PHY_M_MAC_MODE_SEL(PHY_M_MAC_MD_1000BX);
370 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
372 if (hw->pmd_type == 'P') {
373 /* select page 1 to access Fiber registers */
374 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 1);
376 /* for SFP-module set SIGDET polarity to low */
377 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
378 ctrl |= PHY_M_FIB_SIGD_POL;
379 gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
382 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
390 if (sky2->autoneg == AUTONEG_ENABLE) {
391 if (sky2_is_copper(hw)) {
392 if (sky2->advertising & ADVERTISED_1000baseT_Full)
393 ct1000 |= PHY_M_1000C_AFD;
394 if (sky2->advertising & ADVERTISED_1000baseT_Half)
395 ct1000 |= PHY_M_1000C_AHD;
396 if (sky2->advertising & ADVERTISED_100baseT_Full)
397 adv |= PHY_M_AN_100_FD;
398 if (sky2->advertising & ADVERTISED_100baseT_Half)
399 adv |= PHY_M_AN_100_HD;
400 if (sky2->advertising & ADVERTISED_10baseT_Full)
401 adv |= PHY_M_AN_10_FD;
402 if (sky2->advertising & ADVERTISED_10baseT_Half)
403 adv |= PHY_M_AN_10_HD;
405 adv |= copper_fc_adv[sky2->flow_mode];
406 } else { /* special defines for FIBER (88E1040S only) */
407 if (sky2->advertising & ADVERTISED_1000baseT_Full)
408 adv |= PHY_M_AN_1000X_AFD;
409 if (sky2->advertising & ADVERTISED_1000baseT_Half)
410 adv |= PHY_M_AN_1000X_AHD;
412 adv |= fiber_fc_adv[sky2->flow_mode];
415 /* Restart Auto-negotiation */
416 ctrl |= PHY_CT_ANE | PHY_CT_RE_CFG;
418 /* forced speed/duplex settings */
419 ct1000 = PHY_M_1000C_MSE;
421 /* Disable auto update for duplex flow control and speed */
422 reg |= GM_GPCR_AU_ALL_DIS;
424 switch (sky2->speed) {
426 ctrl |= PHY_CT_SP1000;
427 reg |= GM_GPCR_SPEED_1000;
430 ctrl |= PHY_CT_SP100;
431 reg |= GM_GPCR_SPEED_100;
435 if (sky2->duplex == DUPLEX_FULL) {
436 reg |= GM_GPCR_DUP_FULL;
437 ctrl |= PHY_CT_DUP_MD;
438 } else if (sky2->speed < SPEED_1000)
439 sky2->flow_mode = FC_NONE;
442 reg |= gm_fc_disable[sky2->flow_mode];
444 /* Forward pause packets to GMAC? */
445 if (sky2->flow_mode & FC_RX)
446 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON);
448 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
451 gma_write16(hw, port, GM_GP_CTRL, reg);
453 if (hw->chip_id != CHIP_ID_YUKON_FE)
454 gm_phy_write(hw, port, PHY_MARV_1000T_CTRL, ct1000);
456 gm_phy_write(hw, port, PHY_MARV_AUNE_ADV, adv);
457 gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
459 /* Setup Phy LED's */
460 ledctrl = PHY_M_LED_PULS_DUR(PULS_170MS);
463 switch (hw->chip_id) {
464 case CHIP_ID_YUKON_FE:
465 /* on 88E3082 these bits are at 11..9 (shifted left) */
466 ledctrl |= PHY_M_LED_BLINK_RT(BLINK_84MS) << 1;
468 ctrl = gm_phy_read(hw, port, PHY_MARV_FE_LED_PAR);
470 /* delete ACT LED control bits */
471 ctrl &= ~PHY_M_FELP_LED1_MSK;
472 /* change ACT LED control to blink mode */
473 ctrl |= PHY_M_FELP_LED1_CTRL(LED_PAR_CTRL_ACT_BL);
474 gm_phy_write(hw, port, PHY_MARV_FE_LED_PAR, ctrl);
477 case CHIP_ID_YUKON_XL:
478 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
480 /* select page 3 to access LED control register */
481 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
483 /* set LED Function Control register */
484 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
485 (PHY_M_LEDC_LOS_CTRL(1) | /* LINK/ACT */
486 PHY_M_LEDC_INIT_CTRL(7) | /* 10 Mbps */
487 PHY_M_LEDC_STA1_CTRL(7) | /* 100 Mbps */
488 PHY_M_LEDC_STA0_CTRL(7))); /* 1000 Mbps */
490 /* set Polarity Control register */
491 gm_phy_write(hw, port, PHY_MARV_PHY_STAT,
492 (PHY_M_POLC_LS1_P_MIX(4) |
493 PHY_M_POLC_IS0_P_MIX(4) |
494 PHY_M_POLC_LOS_CTRL(2) |
495 PHY_M_POLC_INIT_CTRL(2) |
496 PHY_M_POLC_STA1_CTRL(2) |
497 PHY_M_POLC_STA0_CTRL(2)));
499 /* restore page register */
500 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
502 case CHIP_ID_YUKON_EC_U:
503 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
505 /* select page 3 to access LED control register */
506 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
508 /* set LED Function Control register */
509 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
510 (PHY_M_LEDC_LOS_CTRL(1) | /* LINK/ACT */
511 PHY_M_LEDC_INIT_CTRL(8) | /* 10 Mbps */
512 PHY_M_LEDC_STA1_CTRL(7) | /* 100 Mbps */
513 PHY_M_LEDC_STA0_CTRL(7)));/* 1000 Mbps */
515 /* set Blink Rate in LED Timer Control Register */
516 gm_phy_write(hw, port, PHY_MARV_INT_MASK,
517 ledctrl | PHY_M_LED_BLINK_RT(BLINK_84MS));
518 /* restore page register */
519 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
523 /* set Tx LED (LED_TX) to blink mode on Rx OR Tx activity */
524 ledctrl |= PHY_M_LED_BLINK_RT(BLINK_84MS) | PHY_M_LEDC_TX_CTRL;
525 /* turn off the Rx LED (LED_RX) */
526 ledover |= PHY_M_LED_MO_RX(MO_LED_OFF);
529 if (hw->chip_id == CHIP_ID_YUKON_EC_U && hw->chip_rev == CHIP_REV_YU_EC_A1) {
530 /* apply fixes in PHY AFE */
531 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
532 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 255);
534 /* increase differential signal amplitude in 10BASE-T */
535 gm_phy_write(hw, port, 0x18, 0xaa99);
536 gm_phy_write(hw, port, 0x17, 0x2011);
538 /* fix for IEEE A/B Symmetry failure in 1000BASE-T */
539 gm_phy_write(hw, port, 0x18, 0xa204);
540 gm_phy_write(hw, port, 0x17, 0x2002);
542 /* set page register to 0 */
543 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
545 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, ledctrl);
547 if (sky2->autoneg == AUTONEG_DISABLE || sky2->speed == SPEED_100) {
548 /* turn on 100 Mbps LED (LED_LINK100) */
549 ledover |= PHY_M_LED_MO_100(MO_LED_ON);
553 gm_phy_write(hw, port, PHY_MARV_LED_OVER, ledover);
557 /* Enable phy interrupt on auto-negotiation complete (or link up) */
558 if (sky2->autoneg == AUTONEG_ENABLE)
559 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_IS_AN_COMPL);
561 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_DEF_MSK);
564 static void sky2_phy_power(struct sky2_hw *hw, unsigned port, int onoff)
567 static const u32 phy_power[]
568 = { PCI_Y2_PHY1_POWD, PCI_Y2_PHY2_POWD };
570 /* looks like this XL is back asswards .. */
571 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1)
574 reg1 = sky2_pci_read32(hw, PCI_DEV_REG1);
577 /* Turn off phy power saving */
578 reg1 &= ~phy_power[port];
580 reg1 |= phy_power[port];
582 sky2_pci_write32(hw, PCI_DEV_REG1, reg1);
583 sky2_pci_read32(hw, PCI_DEV_REG1);
587 /* Force a renegotiation */
588 static void sky2_phy_reinit(struct sky2_port *sky2)
590 spin_lock_bh(&sky2->phy_lock);
591 sky2_phy_init(sky2->hw, sky2->port);
592 spin_unlock_bh(&sky2->phy_lock);
595 static void sky2_mac_init(struct sky2_hw *hw, unsigned port)
597 struct sky2_port *sky2 = netdev_priv(hw->dev[port]);
600 const u8 *addr = hw->dev[port]->dev_addr;
602 sky2_write32(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET);
603 sky2_write32(hw, SK_REG(port, GPHY_CTRL), GPC_RST_CLR|GPC_ENA_PAUSE);
605 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_CLR);
607 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0 && port == 1) {
608 /* WA DEV_472 -- looks like crossed wires on port 2 */
609 /* clear GMAC 1 Control reset */
610 sky2_write8(hw, SK_REG(0, GMAC_CTRL), GMC_RST_CLR);
612 sky2_write8(hw, SK_REG(1, GMAC_CTRL), GMC_RST_SET);
613 sky2_write8(hw, SK_REG(1, GMAC_CTRL), GMC_RST_CLR);
614 } while (gm_phy_read(hw, 1, PHY_MARV_ID0) != PHY_MARV_ID0_VAL ||
615 gm_phy_read(hw, 1, PHY_MARV_ID1) != PHY_MARV_ID1_Y2 ||
616 gm_phy_read(hw, 1, PHY_MARV_INT_MASK) != 0);
619 sky2_read16(hw, SK_REG(port, GMAC_IRQ_SRC));
621 /* Enable Transmit FIFO Underrun */
622 sky2_write8(hw, SK_REG(port, GMAC_IRQ_MSK), GMAC_DEF_MSK);
624 spin_lock_bh(&sky2->phy_lock);
625 sky2_phy_init(hw, port);
626 spin_unlock_bh(&sky2->phy_lock);
629 reg = gma_read16(hw, port, GM_PHY_ADDR);
630 gma_write16(hw, port, GM_PHY_ADDR, reg | GM_PAR_MIB_CLR);
632 for (i = GM_MIB_CNT_BASE; i <= GM_MIB_CNT_END; i += 4)
633 gma_read16(hw, port, i);
634 gma_write16(hw, port, GM_PHY_ADDR, reg);
636 /* transmit control */
637 gma_write16(hw, port, GM_TX_CTRL, TX_COL_THR(TX_COL_DEF));
639 /* receive control reg: unicast + multicast + no FCS */
640 gma_write16(hw, port, GM_RX_CTRL,
641 GM_RXCR_UCF_ENA | GM_RXCR_CRC_DIS | GM_RXCR_MCF_ENA);
643 /* transmit flow control */
644 gma_write16(hw, port, GM_TX_FLOW_CTRL, 0xffff);
646 /* transmit parameter */
647 gma_write16(hw, port, GM_TX_PARAM,
648 TX_JAM_LEN_VAL(TX_JAM_LEN_DEF) |
649 TX_JAM_IPG_VAL(TX_JAM_IPG_DEF) |
650 TX_IPG_JAM_DATA(TX_IPG_JAM_DEF) |
651 TX_BACK_OFF_LIM(TX_BOF_LIM_DEF));
653 /* serial mode register */
654 reg = DATA_BLIND_VAL(DATA_BLIND_DEF) |
655 GM_SMOD_VLAN_ENA | IPG_DATA_VAL(IPG_DATA_DEF);
657 if (hw->dev[port]->mtu > ETH_DATA_LEN)
658 reg |= GM_SMOD_JUMBO_ENA;
660 gma_write16(hw, port, GM_SERIAL_MODE, reg);
662 /* virtual address for data */
663 gma_set_addr(hw, port, GM_SRC_ADDR_2L, addr);
665 /* physical address: used for pause frames */
666 gma_set_addr(hw, port, GM_SRC_ADDR_1L, addr);
668 /* ignore counter overflows */
669 gma_write16(hw, port, GM_TX_IRQ_MSK, 0);
670 gma_write16(hw, port, GM_RX_IRQ_MSK, 0);
671 gma_write16(hw, port, GM_TR_IRQ_MSK, 0);
673 /* Configure Rx MAC FIFO */
674 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_CLR);
675 sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T),
676 GMF_OPER_ON | GMF_RX_F_FL_ON);
678 /* Flush Rx MAC FIFO on any flow control or error */
679 sky2_write16(hw, SK_REG(port, RX_GMF_FL_MSK), GMR_FS_ANY_ERR);
681 /* Set threshold to 0xa (64 bytes) + 1 to workaround pause bug */
682 sky2_write16(hw, SK_REG(port, RX_GMF_FL_THR), RX_GMF_FL_THR_DEF+1);
684 /* Configure Tx MAC FIFO */
685 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_CLR);
686 sky2_write16(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_OPER_ON);
688 if (hw->chip_id == CHIP_ID_YUKON_EC_U) {
689 sky2_write8(hw, SK_REG(port, RX_GMF_LP_THR), 768/8);
690 sky2_write8(hw, SK_REG(port, RX_GMF_UP_THR), 1024/8);
691 if (hw->dev[port]->mtu > ETH_DATA_LEN) {
692 /* set Tx GMAC FIFO Almost Empty Threshold */
693 sky2_write32(hw, SK_REG(port, TX_GMF_AE_THR), 0x180);
694 /* Disable Store & Forward mode for TX */
695 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T), TX_STFW_DIS);
701 /* Assign Ram Buffer allocation in units of 64bit (8 bytes) */
702 static void sky2_ramset(struct sky2_hw *hw, u16 q, u32 start, u32 end)
704 pr_debug(PFX "q %d %#x %#x\n", q, start, end);
706 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_RST_CLR);
707 sky2_write32(hw, RB_ADDR(q, RB_START), start);
708 sky2_write32(hw, RB_ADDR(q, RB_END), end);
709 sky2_write32(hw, RB_ADDR(q, RB_WP), start);
710 sky2_write32(hw, RB_ADDR(q, RB_RP), start);
712 if (q == Q_R1 || q == Q_R2) {
713 u32 space = end - start + 1;
714 u32 tp = space - space/4;
716 /* On receive queue's set the thresholds
717 * give receiver priority when > 3/4 full
718 * send pause when down to 2K
720 sky2_write32(hw, RB_ADDR(q, RB_RX_UTHP), tp);
721 sky2_write32(hw, RB_ADDR(q, RB_RX_LTHP), space/2);
724 sky2_write32(hw, RB_ADDR(q, RB_RX_UTPP), tp);
725 sky2_write32(hw, RB_ADDR(q, RB_RX_LTPP), space/4);
727 /* Enable store & forward on Tx queue's because
728 * Tx FIFO is only 1K on Yukon
730 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_STFWD);
733 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_OP_MD);
734 sky2_read8(hw, RB_ADDR(q, RB_CTRL));
737 /* Setup Bus Memory Interface */
738 static void sky2_qset(struct sky2_hw *hw, u16 q)
740 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_CLR_RESET);
741 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_OPER_INIT);
742 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_FIFO_OP_ON);
743 sky2_write32(hw, Q_ADDR(q, Q_WM), BMU_WM_DEFAULT);
746 /* Setup prefetch unit registers. This is the interface between
747 * hardware and driver list elements
749 static void sky2_prefetch_init(struct sky2_hw *hw, u32 qaddr,
752 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_RST_SET);
753 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_RST_CLR);
754 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_ADDR_HI), addr >> 32);
755 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_ADDR_LO), (u32) addr);
756 sky2_write16(hw, Y2_QADDR(qaddr, PREF_UNIT_LAST_IDX), last);
757 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_OP_ON);
759 sky2_read32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL));
762 static inline struct sky2_tx_le *get_tx_le(struct sky2_port *sky2)
764 struct sky2_tx_le *le = sky2->tx_le + sky2->tx_prod;
766 sky2->tx_prod = RING_NEXT(sky2->tx_prod, TX_RING_SIZE);
771 static inline struct tx_ring_info *tx_le_re(struct sky2_port *sky2,
772 struct sky2_tx_le *le)
774 return sky2->tx_ring + (le - sky2->tx_le);
777 /* Update chip's next pointer */
778 static inline void sky2_put_idx(struct sky2_hw *hw, unsigned q, u16 idx)
780 q = Y2_QADDR(q, PREF_UNIT_PUT_IDX);
782 sky2_write16(hw, q, idx);
787 static inline struct sky2_rx_le *sky2_next_rx(struct sky2_port *sky2)
789 struct sky2_rx_le *le = sky2->rx_le + sky2->rx_put;
790 sky2->rx_put = RING_NEXT(sky2->rx_put, RX_LE_SIZE);
795 /* Return high part of DMA address (could be 32 or 64 bit) */
796 static inline u32 high32(dma_addr_t a)
798 return sizeof(a) > sizeof(u32) ? (a >> 16) >> 16 : 0;
801 /* Build description to hardware for one receive segment */
802 static void sky2_rx_add(struct sky2_port *sky2, u8 op,
803 dma_addr_t map, unsigned len)
805 struct sky2_rx_le *le;
806 u32 hi = high32(map);
808 if (sky2->rx_addr64 != hi) {
809 le = sky2_next_rx(sky2);
810 le->addr = cpu_to_le32(hi);
811 le->opcode = OP_ADDR64 | HW_OWNER;
812 sky2->rx_addr64 = high32(map + len);
815 le = sky2_next_rx(sky2);
816 le->addr = cpu_to_le32((u32) map);
817 le->length = cpu_to_le16(len);
818 le->opcode = op | HW_OWNER;
821 /* Build description to hardware for one possibly fragmented skb */
822 static void sky2_rx_submit(struct sky2_port *sky2,
823 const struct rx_ring_info *re)
827 sky2_rx_add(sky2, OP_PACKET, re->data_addr, sky2->rx_data_size);
829 for (i = 0; i < skb_shinfo(re->skb)->nr_frags; i++)
830 sky2_rx_add(sky2, OP_BUFFER, re->frag_addr[i], PAGE_SIZE);
834 static void sky2_rx_map_skb(struct pci_dev *pdev, struct rx_ring_info *re,
837 struct sk_buff *skb = re->skb;
840 re->data_addr = pci_map_single(pdev, skb->data, size, PCI_DMA_FROMDEVICE);
841 pci_unmap_len_set(re, data_size, size);
843 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++)
844 re->frag_addr[i] = pci_map_page(pdev,
845 skb_shinfo(skb)->frags[i].page,
846 skb_shinfo(skb)->frags[i].page_offset,
847 skb_shinfo(skb)->frags[i].size,
851 static void sky2_rx_unmap_skb(struct pci_dev *pdev, struct rx_ring_info *re)
853 struct sk_buff *skb = re->skb;
856 pci_unmap_single(pdev, re->data_addr, pci_unmap_len(re, data_size),
859 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++)
860 pci_unmap_page(pdev, re->frag_addr[i],
861 skb_shinfo(skb)->frags[i].size,
865 /* Tell chip where to start receive checksum.
866 * Actually has two checksums, but set both same to avoid possible byte
869 static void rx_set_checksum(struct sky2_port *sky2)
871 struct sky2_rx_le *le;
873 le = sky2_next_rx(sky2);
874 le->addr = cpu_to_le32((ETH_HLEN << 16) | ETH_HLEN);
876 le->opcode = OP_TCPSTART | HW_OWNER;
878 sky2_write32(sky2->hw,
879 Q_ADDR(rxqaddr[sky2->port], Q_CSR),
880 sky2->rx_csum ? BMU_ENA_RX_CHKSUM : BMU_DIS_RX_CHKSUM);
885 * The RX Stop command will not work for Yukon-2 if the BMU does not
886 * reach the end of packet and since we can't make sure that we have
887 * incoming data, we must reset the BMU while it is not doing a DMA
888 * transfer. Since it is possible that the RX path is still active,
889 * the RX RAM buffer will be stopped first, so any possible incoming
890 * data will not trigger a DMA. After the RAM buffer is stopped, the
891 * BMU is polled until any DMA in progress is ended and only then it
894 static void sky2_rx_stop(struct sky2_port *sky2)
896 struct sky2_hw *hw = sky2->hw;
897 unsigned rxq = rxqaddr[sky2->port];
900 /* disable the RAM Buffer receive queue */
901 sky2_write8(hw, RB_ADDR(rxq, RB_CTRL), RB_DIS_OP_MD);
903 for (i = 0; i < 0xffff; i++)
904 if (sky2_read8(hw, RB_ADDR(rxq, Q_RSL))
905 == sky2_read8(hw, RB_ADDR(rxq, Q_RL)))
908 printk(KERN_WARNING PFX "%s: receiver stop failed\n",
911 sky2_write32(hw, Q_ADDR(rxq, Q_CSR), BMU_RST_SET | BMU_FIFO_RST);
913 /* reset the Rx prefetch unit */
914 sky2_write32(hw, Y2_QADDR(rxq, PREF_UNIT_CTRL), PREF_UNIT_RST_SET);
917 /* Clean out receive buffer area, assumes receiver hardware stopped */
918 static void sky2_rx_clean(struct sky2_port *sky2)
922 memset(sky2->rx_le, 0, RX_LE_BYTES);
923 for (i = 0; i < sky2->rx_pending; i++) {
924 struct rx_ring_info *re = sky2->rx_ring + i;
927 sky2_rx_unmap_skb(sky2->hw->pdev, re);
934 /* Basic MII support */
935 static int sky2_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
937 struct mii_ioctl_data *data = if_mii(ifr);
938 struct sky2_port *sky2 = netdev_priv(dev);
939 struct sky2_hw *hw = sky2->hw;
940 int err = -EOPNOTSUPP;
942 if (!netif_running(dev))
943 return -ENODEV; /* Phy still in reset */
947 data->phy_id = PHY_ADDR_MARV;
953 spin_lock_bh(&sky2->phy_lock);
954 err = __gm_phy_read(hw, sky2->port, data->reg_num & 0x1f, &val);
955 spin_unlock_bh(&sky2->phy_lock);
962 if (!capable(CAP_NET_ADMIN))
965 spin_lock_bh(&sky2->phy_lock);
966 err = gm_phy_write(hw, sky2->port, data->reg_num & 0x1f,
968 spin_unlock_bh(&sky2->phy_lock);
974 #ifdef SKY2_VLAN_TAG_USED
975 static void sky2_vlan_rx_register(struct net_device *dev, struct vlan_group *grp)
977 struct sky2_port *sky2 = netdev_priv(dev);
978 struct sky2_hw *hw = sky2->hw;
979 u16 port = sky2->port;
981 netif_tx_lock_bh(dev);
983 sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T), RX_VLAN_STRIP_ON);
984 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T), TX_VLAN_TAG_ON);
987 netif_tx_unlock_bh(dev);
990 static void sky2_vlan_rx_kill_vid(struct net_device *dev, unsigned short vid)
992 struct sky2_port *sky2 = netdev_priv(dev);
993 struct sky2_hw *hw = sky2->hw;
994 u16 port = sky2->port;
996 netif_tx_lock_bh(dev);
998 sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T), RX_VLAN_STRIP_OFF);
999 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T), TX_VLAN_TAG_OFF);
1001 sky2->vlgrp->vlan_devices[vid] = NULL;
1003 netif_tx_unlock_bh(dev);
1008 * Allocate an skb for receiving. If the MTU is large enough
1009 * make the skb non-linear with a fragment list of pages.
1011 * It appears the hardware has a bug in the FIFO logic that
1012 * cause it to hang if the FIFO gets overrun and the receive buffer
1013 * is not 64 byte aligned. The buffer returned from netdev_alloc_skb is
1014 * aligned except if slab debugging is enabled.
1016 static struct sk_buff *sky2_rx_alloc(struct sky2_port *sky2)
1018 struct sk_buff *skb;
1022 skb = netdev_alloc_skb(sky2->netdev, sky2->rx_data_size + RX_SKB_ALIGN);
1026 p = (unsigned long) skb->data;
1027 skb_reserve(skb, ALIGN(p, RX_SKB_ALIGN) - p);
1029 for (i = 0; i < sky2->rx_nfrags; i++) {
1030 struct page *page = alloc_page(GFP_ATOMIC);
1034 skb_fill_page_desc(skb, i, page, 0, PAGE_SIZE);
1045 * Allocate and setup receiver buffer pool.
1046 * Normal case this ends up creating one list element for skb
1047 * in the receive ring. Worst case if using large MTU and each
1048 * allocation falls on a different 64 bit region, that results
1049 * in 6 list elements per ring entry.
1050 * One element is used for checksum enable/disable, and one
1051 * extra to avoid wrap.
1053 static int sky2_rx_start(struct sky2_port *sky2)
1055 struct sky2_hw *hw = sky2->hw;
1056 struct rx_ring_info *re;
1057 unsigned rxq = rxqaddr[sky2->port];
1058 unsigned i, size, space, thresh;
1060 sky2->rx_put = sky2->rx_next = 0;
1063 if (hw->chip_id == CHIP_ID_YUKON_EC_U &&
1064 (hw->chip_rev == CHIP_REV_YU_EC_U_A1 || hw->chip_rev == CHIP_REV_YU_EC_U_B0)) {
1065 /* MAC Rx RAM Read is controlled by hardware */
1066 sky2_write32(hw, Q_ADDR(rxq, Q_F), F_M_RX_RAM_DIS);
1069 sky2_prefetch_init(hw, rxq, sky2->rx_le_map, RX_LE_SIZE - 1);
1071 rx_set_checksum(sky2);
1073 /* Space needed for frame data + headers rounded up */
1074 size = ALIGN(sky2->netdev->mtu + ETH_HLEN + VLAN_HLEN, 8)
1077 /* Stopping point for hardware truncation */
1078 thresh = (size - 8) / sizeof(u32);
1080 /* Account for overhead of skb - to avoid order > 0 allocation */
1081 space = SKB_DATA_ALIGN(size) + NET_SKB_PAD
1082 + sizeof(struct skb_shared_info);
1084 sky2->rx_nfrags = space >> PAGE_SHIFT;
1085 BUG_ON(sky2->rx_nfrags > ARRAY_SIZE(re->frag_addr));
1087 if (sky2->rx_nfrags != 0) {
1088 /* Compute residue after pages */
1089 space = sky2->rx_nfrags << PAGE_SHIFT;
1096 /* Optimize to handle small packets and headers */
1097 if (size < copybreak)
1099 if (size < ETH_HLEN)
1102 sky2->rx_data_size = size;
1105 for (i = 0; i < sky2->rx_pending; i++) {
1106 re = sky2->rx_ring + i;
1108 re->skb = sky2_rx_alloc(sky2);
1112 sky2_rx_map_skb(hw->pdev, re, sky2->rx_data_size);
1113 sky2_rx_submit(sky2, re);
1117 * The receiver hangs if it receives frames larger than the
1118 * packet buffer. As a workaround, truncate oversize frames, but
1119 * the register is limited to 9 bits, so if you do frames > 2052
1120 * you better get the MTU right!
1123 sky2_write32(hw, SK_REG(sky2->port, RX_GMF_CTRL_T), RX_TRUNC_OFF);
1125 sky2_write16(hw, SK_REG(sky2->port, RX_GMF_TR_THR), thresh);
1126 sky2_write32(hw, SK_REG(sky2->port, RX_GMF_CTRL_T), RX_TRUNC_ON);
1129 /* Tell chip about available buffers */
1130 sky2_write16(hw, Y2_QADDR(rxq, PREF_UNIT_PUT_IDX), sky2->rx_put);
1133 sky2_rx_clean(sky2);
1137 /* Bring up network interface. */
1138 static int sky2_up(struct net_device *dev)
1140 struct sky2_port *sky2 = netdev_priv(dev);
1141 struct sky2_hw *hw = sky2->hw;
1142 unsigned port = sky2->port;
1143 u32 ramsize, rxspace, imask;
1144 int cap, err = -ENOMEM;
1145 struct net_device *otherdev = hw->dev[sky2->port^1];
1148 * On dual port PCI-X card, there is an problem where status
1149 * can be received out of order due to split transactions
1151 if (otherdev && netif_running(otherdev) &&
1152 (cap = pci_find_capability(hw->pdev, PCI_CAP_ID_PCIX))) {
1153 struct sky2_port *osky2 = netdev_priv(otherdev);
1156 cmd = sky2_pci_read16(hw, cap + PCI_X_CMD);
1157 cmd &= ~PCI_X_CMD_MAX_SPLIT;
1158 sky2_pci_write16(hw, cap + PCI_X_CMD, cmd);
1164 if (netif_msg_ifup(sky2))
1165 printk(KERN_INFO PFX "%s: enabling interface\n", dev->name);
1167 /* must be power of 2 */
1168 sky2->tx_le = pci_alloc_consistent(hw->pdev,
1170 sizeof(struct sky2_tx_le),
1175 sky2->tx_ring = kcalloc(TX_RING_SIZE, sizeof(struct tx_ring_info),
1179 sky2->tx_prod = sky2->tx_cons = 0;
1181 sky2->rx_le = pci_alloc_consistent(hw->pdev, RX_LE_BYTES,
1185 memset(sky2->rx_le, 0, RX_LE_BYTES);
1187 sky2->rx_ring = kcalloc(sky2->rx_pending, sizeof(struct rx_ring_info),
1192 sky2_phy_power(hw, port, 1);
1194 sky2_mac_init(hw, port);
1196 /* Determine available ram buffer space in qwords. */
1197 ramsize = sky2_read8(hw, B2_E_0) * 4096/8;
1199 if (ramsize > 6*1024/8)
1200 rxspace = ramsize - (ramsize + 2) / 3;
1202 rxspace = ramsize / 2;
1204 sky2_ramset(hw, rxqaddr[port], 0, rxspace-1);
1205 sky2_ramset(hw, txqaddr[port], rxspace, ramsize-1);
1207 /* Make sure SyncQ is disabled */
1208 sky2_write8(hw, RB_ADDR(port == 0 ? Q_XS1 : Q_XS2, RB_CTRL),
1211 sky2_qset(hw, txqaddr[port]);
1213 /* Set almost empty threshold */
1214 if (hw->chip_id == CHIP_ID_YUKON_EC_U
1215 && hw->chip_rev == CHIP_REV_YU_EC_U_A0)
1216 sky2_write16(hw, Q_ADDR(txqaddr[port], Q_AL), 0x1a0);
1218 sky2_prefetch_init(hw, txqaddr[port], sky2->tx_le_map,
1221 err = sky2_rx_start(sky2);
1225 /* Enable interrupts from phy/mac for port */
1226 imask = sky2_read32(hw, B0_IMSK);
1227 imask |= portirq_msk[port];
1228 sky2_write32(hw, B0_IMSK, imask);
1234 pci_free_consistent(hw->pdev, RX_LE_BYTES,
1235 sky2->rx_le, sky2->rx_le_map);
1239 pci_free_consistent(hw->pdev,
1240 TX_RING_SIZE * sizeof(struct sky2_tx_le),
1241 sky2->tx_le, sky2->tx_le_map);
1244 kfree(sky2->tx_ring);
1245 kfree(sky2->rx_ring);
1247 sky2->tx_ring = NULL;
1248 sky2->rx_ring = NULL;
1252 /* Modular subtraction in ring */
1253 static inline int tx_dist(unsigned tail, unsigned head)
1255 return (head - tail) & (TX_RING_SIZE - 1);
1258 /* Number of list elements available for next tx */
1259 static inline int tx_avail(const struct sky2_port *sky2)
1261 return sky2->tx_pending - tx_dist(sky2->tx_cons, sky2->tx_prod);
1264 /* Estimate of number of transmit list elements required */
1265 static unsigned tx_le_req(const struct sk_buff *skb)
1269 count = sizeof(dma_addr_t) / sizeof(u32);
1270 count += skb_shinfo(skb)->nr_frags * count;
1272 if (skb_is_gso(skb))
1275 if (skb->ip_summed == CHECKSUM_PARTIAL)
1282 * Put one packet in ring for transmit.
1283 * A single packet can generate multiple list elements, and
1284 * the number of ring elements will probably be less than the number
1285 * of list elements used.
1287 static int sky2_xmit_frame(struct sk_buff *skb, struct net_device *dev)
1289 struct sky2_port *sky2 = netdev_priv(dev);
1290 struct sky2_hw *hw = sky2->hw;
1291 struct sky2_tx_le *le = NULL;
1292 struct tx_ring_info *re;
1299 if (unlikely(tx_avail(sky2) < tx_le_req(skb)))
1300 return NETDEV_TX_BUSY;
1302 if (unlikely(netif_msg_tx_queued(sky2)))
1303 printk(KERN_DEBUG "%s: tx queued, slot %u, len %d\n",
1304 dev->name, sky2->tx_prod, skb->len);
1306 len = skb_headlen(skb);
1307 mapping = pci_map_single(hw->pdev, skb->data, len, PCI_DMA_TODEVICE);
1308 addr64 = high32(mapping);
1310 /* Send high bits if changed or crosses boundary */
1311 if (addr64 != sky2->tx_addr64 || high32(mapping + len) != sky2->tx_addr64) {
1312 le = get_tx_le(sky2);
1313 le->addr = cpu_to_le32(addr64);
1314 le->opcode = OP_ADDR64 | HW_OWNER;
1315 sky2->tx_addr64 = high32(mapping + len);
1318 /* Check for TCP Segmentation Offload */
1319 mss = skb_shinfo(skb)->gso_size;
1321 mss += ((skb->h.th->doff - 5) * 4); /* TCP options */
1322 mss += (skb->nh.iph->ihl * 4) + sizeof(struct tcphdr);
1325 if (mss != sky2->tx_last_mss) {
1326 le = get_tx_le(sky2);
1327 le->addr = cpu_to_le32(mss);
1328 le->opcode = OP_LRGLEN | HW_OWNER;
1329 sky2->tx_last_mss = mss;
1334 #ifdef SKY2_VLAN_TAG_USED
1335 /* Add VLAN tag, can piggyback on LRGLEN or ADDR64 */
1336 if (sky2->vlgrp && vlan_tx_tag_present(skb)) {
1338 le = get_tx_le(sky2);
1340 le->opcode = OP_VLAN|HW_OWNER;
1342 le->opcode |= OP_VLAN;
1343 le->length = cpu_to_be16(vlan_tx_tag_get(skb));
1348 /* Handle TCP checksum offload */
1349 if (skb->ip_summed == CHECKSUM_PARTIAL) {
1350 unsigned offset = skb->h.raw - skb->data;
1353 tcpsum = offset << 16; /* sum start */
1354 tcpsum |= offset + skb->csum_offset; /* sum write */
1356 ctrl = CALSUM | WR_SUM | INIT_SUM | LOCK_SUM;
1357 if (skb->nh.iph->protocol == IPPROTO_UDP)
1360 if (tcpsum != sky2->tx_tcpsum) {
1361 sky2->tx_tcpsum = tcpsum;
1363 le = get_tx_le(sky2);
1364 le->addr = cpu_to_le32(tcpsum);
1365 le->length = 0; /* initial checksum value */
1366 le->ctrl = 1; /* one packet */
1367 le->opcode = OP_TCPLISW | HW_OWNER;
1371 le = get_tx_le(sky2);
1372 le->addr = cpu_to_le32((u32) mapping);
1373 le->length = cpu_to_le16(len);
1375 le->opcode = mss ? (OP_LARGESEND | HW_OWNER) : (OP_PACKET | HW_OWNER);
1377 re = tx_le_re(sky2, le);
1379 pci_unmap_addr_set(re, mapaddr, mapping);
1380 pci_unmap_len_set(re, maplen, len);
1382 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
1383 const skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
1385 mapping = pci_map_page(hw->pdev, frag->page, frag->page_offset,
1386 frag->size, PCI_DMA_TODEVICE);
1387 addr64 = high32(mapping);
1388 if (addr64 != sky2->tx_addr64) {
1389 le = get_tx_le(sky2);
1390 le->addr = cpu_to_le32(addr64);
1392 le->opcode = OP_ADDR64 | HW_OWNER;
1393 sky2->tx_addr64 = addr64;
1396 le = get_tx_le(sky2);
1397 le->addr = cpu_to_le32((u32) mapping);
1398 le->length = cpu_to_le16(frag->size);
1400 le->opcode = OP_BUFFER | HW_OWNER;
1402 re = tx_le_re(sky2, le);
1404 pci_unmap_addr_set(re, mapaddr, mapping);
1405 pci_unmap_len_set(re, maplen, frag->size);
1410 if (tx_avail(sky2) <= MAX_SKB_TX_LE)
1411 netif_stop_queue(dev);
1413 sky2_put_idx(hw, txqaddr[sky2->port], sky2->tx_prod);
1415 dev->trans_start = jiffies;
1416 return NETDEV_TX_OK;
1420 * Free ring elements from starting at tx_cons until "done"
1422 * NB: the hardware will tell us about partial completion of multi-part
1423 * buffers so make sure not to free skb to early.
1425 static void sky2_tx_complete(struct sky2_port *sky2, u16 done)
1427 struct net_device *dev = sky2->netdev;
1428 struct pci_dev *pdev = sky2->hw->pdev;
1431 BUG_ON(done >= TX_RING_SIZE);
1433 for (idx = sky2->tx_cons; idx != done;
1434 idx = RING_NEXT(idx, TX_RING_SIZE)) {
1435 struct sky2_tx_le *le = sky2->tx_le + idx;
1436 struct tx_ring_info *re = sky2->tx_ring + idx;
1438 switch(le->opcode & ~HW_OWNER) {
1441 pci_unmap_single(pdev,
1442 pci_unmap_addr(re, mapaddr),
1443 pci_unmap_len(re, maplen),
1447 pci_unmap_page(pdev, pci_unmap_addr(re, mapaddr),
1448 pci_unmap_len(re, maplen),
1453 if (le->ctrl & EOP) {
1454 if (unlikely(netif_msg_tx_done(sky2)))
1455 printk(KERN_DEBUG "%s: tx done %u\n",
1457 dev_kfree_skb_any(re->skb);
1460 le->opcode = 0; /* paranoia */
1463 sky2->tx_cons = idx;
1464 if (tx_avail(sky2) > MAX_SKB_TX_LE + 4)
1465 netif_wake_queue(dev);
1468 /* Cleanup all untransmitted buffers, assume transmitter not running */
1469 static void sky2_tx_clean(struct net_device *dev)
1471 struct sky2_port *sky2 = netdev_priv(dev);
1473 netif_tx_lock_bh(dev);
1474 sky2_tx_complete(sky2, sky2->tx_prod);
1475 netif_tx_unlock_bh(dev);
1478 /* Network shutdown */
1479 static int sky2_down(struct net_device *dev)
1481 struct sky2_port *sky2 = netdev_priv(dev);
1482 struct sky2_hw *hw = sky2->hw;
1483 unsigned port = sky2->port;
1487 /* Never really got started! */
1491 if (netif_msg_ifdown(sky2))
1492 printk(KERN_INFO PFX "%s: disabling interface\n", dev->name);
1494 /* Stop more packets from being queued */
1495 netif_stop_queue(dev);
1497 /* Disable port IRQ */
1498 imask = sky2_read32(hw, B0_IMSK);
1499 imask &= ~portirq_msk[port];
1500 sky2_write32(hw, B0_IMSK, imask);
1502 sky2_gmac_reset(hw, port);
1504 /* Stop transmitter */
1505 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), BMU_STOP);
1506 sky2_read32(hw, Q_ADDR(txqaddr[port], Q_CSR));
1508 sky2_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL),
1509 RB_RST_SET | RB_DIS_OP_MD);
1511 /* WA for dev. #4.209 */
1512 if (hw->chip_id == CHIP_ID_YUKON_EC_U
1513 && (hw->chip_rev == CHIP_REV_YU_EC_U_A1 || hw->chip_rev == CHIP_REV_YU_EC_U_B0))
1514 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T),
1515 sky2->speed != SPEED_1000 ?
1516 TX_STFW_ENA : TX_STFW_DIS);
1518 ctrl = gma_read16(hw, port, GM_GP_CTRL);
1519 ctrl &= ~(GM_GPCR_TX_ENA | GM_GPCR_RX_ENA);
1520 gma_write16(hw, port, GM_GP_CTRL, ctrl);
1522 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET);
1524 /* Workaround shared GMAC reset */
1525 if (!(hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0
1526 && port == 0 && hw->dev[1] && netif_running(hw->dev[1])))
1527 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_SET);
1529 /* Disable Force Sync bit and Enable Alloc bit */
1530 sky2_write8(hw, SK_REG(port, TXA_CTRL),
1531 TXA_DIS_FSYNC | TXA_DIS_ALLOC | TXA_STOP_RC);
1533 /* Stop Interval Timer and Limit Counter of Tx Arbiter */
1534 sky2_write32(hw, SK_REG(port, TXA_ITI_INI), 0L);
1535 sky2_write32(hw, SK_REG(port, TXA_LIM_INI), 0L);
1537 /* Reset the PCI FIFO of the async Tx queue */
1538 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR),
1539 BMU_RST_SET | BMU_FIFO_RST);
1541 /* Reset the Tx prefetch units */
1542 sky2_write32(hw, Y2_QADDR(txqaddr[port], PREF_UNIT_CTRL),
1545 sky2_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL), RB_RST_SET);
1549 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_SET);
1550 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_SET);
1552 sky2_phy_power(hw, port, 0);
1554 /* turn off LED's */
1555 sky2_write16(hw, B0_Y2LED, LED_STAT_OFF);
1557 synchronize_irq(hw->pdev->irq);
1560 sky2_rx_clean(sky2);
1562 pci_free_consistent(hw->pdev, RX_LE_BYTES,
1563 sky2->rx_le, sky2->rx_le_map);
1564 kfree(sky2->rx_ring);
1566 pci_free_consistent(hw->pdev,
1567 TX_RING_SIZE * sizeof(struct sky2_tx_le),
1568 sky2->tx_le, sky2->tx_le_map);
1569 kfree(sky2->tx_ring);
1574 sky2->rx_ring = NULL;
1575 sky2->tx_ring = NULL;
1580 static u16 sky2_phy_speed(const struct sky2_hw *hw, u16 aux)
1582 if (!sky2_is_copper(hw))
1585 if (hw->chip_id == CHIP_ID_YUKON_FE)
1586 return (aux & PHY_M_PS_SPEED_100) ? SPEED_100 : SPEED_10;
1588 switch (aux & PHY_M_PS_SPEED_MSK) {
1589 case PHY_M_PS_SPEED_1000:
1591 case PHY_M_PS_SPEED_100:
1598 static void sky2_link_up(struct sky2_port *sky2)
1600 struct sky2_hw *hw = sky2->hw;
1601 unsigned port = sky2->port;
1603 static const char *fc_name[] = {
1611 reg = gma_read16(hw, port, GM_GP_CTRL);
1612 reg |= GM_GPCR_RX_ENA | GM_GPCR_TX_ENA;
1613 gma_write16(hw, port, GM_GP_CTRL, reg);
1615 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_DEF_MSK);
1617 netif_carrier_on(sky2->netdev);
1618 netif_wake_queue(sky2->netdev);
1620 /* Turn on link LED */
1621 sky2_write8(hw, SK_REG(port, LNK_LED_REG),
1622 LINKLED_ON | LINKLED_BLINK_OFF | LINKLED_LINKSYNC_OFF);
1624 if (hw->chip_id == CHIP_ID_YUKON_XL || hw->chip_id == CHIP_ID_YUKON_EC_U) {
1625 u16 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
1626 u16 led = PHY_M_LEDC_LOS_CTRL(1); /* link active */
1628 switch(sky2->speed) {
1630 led |= PHY_M_LEDC_INIT_CTRL(7);
1634 led |= PHY_M_LEDC_STA1_CTRL(7);
1638 led |= PHY_M_LEDC_STA0_CTRL(7);
1642 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
1643 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, led);
1644 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
1647 if (netif_msg_link(sky2))
1648 printk(KERN_INFO PFX
1649 "%s: Link is up at %d Mbps, %s duplex, flow control %s\n",
1650 sky2->netdev->name, sky2->speed,
1651 sky2->duplex == DUPLEX_FULL ? "full" : "half",
1652 fc_name[sky2->flow_status]);
1655 static void sky2_link_down(struct sky2_port *sky2)
1657 struct sky2_hw *hw = sky2->hw;
1658 unsigned port = sky2->port;
1661 gm_phy_write(hw, port, PHY_MARV_INT_MASK, 0);
1663 reg = gma_read16(hw, port, GM_GP_CTRL);
1664 reg &= ~(GM_GPCR_RX_ENA | GM_GPCR_TX_ENA);
1665 gma_write16(hw, port, GM_GP_CTRL, reg);
1667 if (sky2->flow_status == FC_RX) {
1668 /* restore Asymmetric Pause bit */
1669 gm_phy_write(hw, port, PHY_MARV_AUNE_ADV,
1670 gm_phy_read(hw, port, PHY_MARV_AUNE_ADV)
1674 netif_carrier_off(sky2->netdev);
1675 netif_stop_queue(sky2->netdev);
1677 /* Turn on link LED */
1678 sky2_write8(hw, SK_REG(port, LNK_LED_REG), LINKLED_OFF);
1680 if (netif_msg_link(sky2))
1681 printk(KERN_INFO PFX "%s: Link is down.\n", sky2->netdev->name);
1683 sky2_phy_init(hw, port);
1686 static enum flow_control sky2_flow(int rx, int tx)
1689 return tx ? FC_BOTH : FC_RX;
1691 return tx ? FC_TX : FC_NONE;
1694 static int sky2_autoneg_done(struct sky2_port *sky2, u16 aux)
1696 struct sky2_hw *hw = sky2->hw;
1697 unsigned port = sky2->port;
1700 lpa = gm_phy_read(hw, port, PHY_MARV_AUNE_LP);
1702 if (lpa & PHY_M_AN_RF) {
1703 printk(KERN_ERR PFX "%s: remote fault", sky2->netdev->name);
1707 if (!(aux & PHY_M_PS_SPDUP_RES)) {
1708 printk(KERN_ERR PFX "%s: speed/duplex mismatch",
1709 sky2->netdev->name);
1713 sky2->speed = sky2_phy_speed(hw, aux);
1714 sky2->duplex = (aux & PHY_M_PS_FULL_DUP) ? DUPLEX_FULL : DUPLEX_HALF;
1716 /* Pause bits are offset (9..8) */
1717 if (hw->chip_id == CHIP_ID_YUKON_XL || hw->chip_id == CHIP_ID_YUKON_EC_U)
1720 sky2->flow_status = sky2_flow(aux & PHY_M_PS_RX_P_EN,
1721 aux & PHY_M_PS_TX_P_EN);
1723 if (sky2->duplex == DUPLEX_HALF && sky2->speed < SPEED_1000
1724 && hw->chip_id != CHIP_ID_YUKON_EC_U)
1725 sky2->flow_status = FC_NONE;
1727 if (aux & PHY_M_PS_RX_P_EN)
1728 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON);
1730 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
1735 /* Interrupt from PHY */
1736 static void sky2_phy_intr(struct sky2_hw *hw, unsigned port)
1738 struct net_device *dev = hw->dev[port];
1739 struct sky2_port *sky2 = netdev_priv(dev);
1740 u16 istatus, phystat;
1742 if (!netif_running(dev))
1745 spin_lock(&sky2->phy_lock);
1746 istatus = gm_phy_read(hw, port, PHY_MARV_INT_STAT);
1747 phystat = gm_phy_read(hw, port, PHY_MARV_PHY_STAT);
1749 if (netif_msg_intr(sky2))
1750 printk(KERN_INFO PFX "%s: phy interrupt status 0x%x 0x%x\n",
1751 sky2->netdev->name, istatus, phystat);
1753 if (sky2->autoneg == AUTONEG_ENABLE && (istatus & PHY_M_IS_AN_COMPL)) {
1754 if (sky2_autoneg_done(sky2, phystat) == 0)
1759 if (istatus & PHY_M_IS_LSP_CHANGE)
1760 sky2->speed = sky2_phy_speed(hw, phystat);
1762 if (istatus & PHY_M_IS_DUP_CHANGE)
1764 (phystat & PHY_M_PS_FULL_DUP) ? DUPLEX_FULL : DUPLEX_HALF;
1766 if (istatus & PHY_M_IS_LST_CHANGE) {
1767 if (phystat & PHY_M_PS_LINK_UP)
1770 sky2_link_down(sky2);
1773 spin_unlock(&sky2->phy_lock);
1777 /* Transmit timeout is only called if we are running, carries is up
1778 * and tx queue is full (stopped).
1780 static void sky2_tx_timeout(struct net_device *dev)
1782 struct sky2_port *sky2 = netdev_priv(dev);
1783 struct sky2_hw *hw = sky2->hw;
1784 unsigned txq = txqaddr[sky2->port];
1787 if (netif_msg_timer(sky2))
1788 printk(KERN_ERR PFX "%s: tx timeout\n", dev->name);
1790 report = sky2_read16(hw, sky2->port == 0 ? STAT_TXA1_RIDX : STAT_TXA2_RIDX);
1791 done = sky2_read16(hw, Q_ADDR(txq, Q_DONE));
1793 printk(KERN_DEBUG PFX "%s: transmit ring %u .. %u report=%u done=%u\n",
1795 sky2->tx_cons, sky2->tx_prod, report, done);
1797 if (report != done) {
1798 printk(KERN_INFO PFX "status burst pending (irq moderation?)\n");
1800 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_STOP);
1801 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_START);
1802 } else if (report != sky2->tx_cons) {
1803 printk(KERN_INFO PFX "status report lost?\n");
1805 netif_tx_lock_bh(dev);
1806 sky2_tx_complete(sky2, report);
1807 netif_tx_unlock_bh(dev);
1809 printk(KERN_INFO PFX "hardware hung? flushing\n");
1811 sky2_write32(hw, Q_ADDR(txq, Q_CSR), BMU_STOP);
1812 sky2_write32(hw, Y2_QADDR(txq, PREF_UNIT_CTRL), PREF_UNIT_RST_SET);
1817 sky2_prefetch_init(hw, txq, sky2->tx_le_map, TX_RING_SIZE - 1);
1821 static int sky2_change_mtu(struct net_device *dev, int new_mtu)
1823 struct sky2_port *sky2 = netdev_priv(dev);
1824 struct sky2_hw *hw = sky2->hw;
1829 if (new_mtu < ETH_ZLEN || new_mtu > ETH_JUMBO_MTU)
1832 if (hw->chip_id == CHIP_ID_YUKON_EC_U && new_mtu > ETH_DATA_LEN)
1835 if (!netif_running(dev)) {
1840 imask = sky2_read32(hw, B0_IMSK);
1841 sky2_write32(hw, B0_IMSK, 0);
1843 dev->trans_start = jiffies; /* prevent tx timeout */
1844 netif_stop_queue(dev);
1845 netif_poll_disable(hw->dev[0]);
1847 synchronize_irq(hw->pdev->irq);
1849 ctl = gma_read16(hw, sky2->port, GM_GP_CTRL);
1850 gma_write16(hw, sky2->port, GM_GP_CTRL, ctl & ~GM_GPCR_RX_ENA);
1852 sky2_rx_clean(sky2);
1856 mode = DATA_BLIND_VAL(DATA_BLIND_DEF) |
1857 GM_SMOD_VLAN_ENA | IPG_DATA_VAL(IPG_DATA_DEF);
1859 if (dev->mtu > ETH_DATA_LEN)
1860 mode |= GM_SMOD_JUMBO_ENA;
1862 gma_write16(hw, sky2->port, GM_SERIAL_MODE, mode);
1864 sky2_write8(hw, RB_ADDR(rxqaddr[sky2->port], RB_CTRL), RB_ENA_OP_MD);
1866 err = sky2_rx_start(sky2);
1867 sky2_write32(hw, B0_IMSK, imask);
1872 gma_write16(hw, sky2->port, GM_GP_CTRL, ctl);
1874 netif_poll_enable(hw->dev[0]);
1875 netif_wake_queue(dev);
1881 /* For small just reuse existing skb for next receive */
1882 static struct sk_buff *receive_copy(struct sky2_port *sky2,
1883 const struct rx_ring_info *re,
1886 struct sk_buff *skb;
1888 skb = netdev_alloc_skb(sky2->netdev, length + 2);
1890 skb_reserve(skb, 2);
1891 pci_dma_sync_single_for_cpu(sky2->hw->pdev, re->data_addr,
1892 length, PCI_DMA_FROMDEVICE);
1893 memcpy(skb->data, re->skb->data, length);
1894 skb->ip_summed = re->skb->ip_summed;
1895 skb->csum = re->skb->csum;
1896 pci_dma_sync_single_for_device(sky2->hw->pdev, re->data_addr,
1897 length, PCI_DMA_FROMDEVICE);
1898 re->skb->ip_summed = CHECKSUM_NONE;
1899 skb_put(skb, length);
1904 /* Adjust length of skb with fragments to match received data */
1905 static void skb_put_frags(struct sk_buff *skb, unsigned int hdr_space,
1906 unsigned int length)
1911 /* put header into skb */
1912 size = min(length, hdr_space);
1917 num_frags = skb_shinfo(skb)->nr_frags;
1918 for (i = 0; i < num_frags; i++) {
1919 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
1922 /* don't need this page */
1923 __free_page(frag->page);
1924 --skb_shinfo(skb)->nr_frags;
1926 size = min(length, (unsigned) PAGE_SIZE);
1929 skb->data_len += size;
1930 skb->truesize += size;
1937 /* Normal packet - take skb from ring element and put in a new one */
1938 static struct sk_buff *receive_new(struct sky2_port *sky2,
1939 struct rx_ring_info *re,
1940 unsigned int length)
1942 struct sk_buff *skb, *nskb;
1943 unsigned hdr_space = sky2->rx_data_size;
1945 pr_debug(PFX "receive new length=%d\n", length);
1947 /* Don't be tricky about reusing pages (yet) */
1948 nskb = sky2_rx_alloc(sky2);
1949 if (unlikely(!nskb))
1953 sky2_rx_unmap_skb(sky2->hw->pdev, re);
1955 prefetch(skb->data);
1957 sky2_rx_map_skb(sky2->hw->pdev, re, hdr_space);
1959 if (skb_shinfo(skb)->nr_frags)
1960 skb_put_frags(skb, hdr_space, length);
1962 skb_put(skb, length);
1967 * Receive one packet.
1968 * For larger packets, get new buffer.
1970 static struct sk_buff *sky2_receive(struct net_device *dev,
1971 u16 length, u32 status)
1973 struct sky2_port *sky2 = netdev_priv(dev);
1974 struct rx_ring_info *re = sky2->rx_ring + sky2->rx_next;
1975 struct sk_buff *skb = NULL;
1977 if (unlikely(netif_msg_rx_status(sky2)))
1978 printk(KERN_DEBUG PFX "%s: rx slot %u status 0x%x len %d\n",
1979 dev->name, sky2->rx_next, status, length);
1981 sky2->rx_next = (sky2->rx_next + 1) % sky2->rx_pending;
1982 prefetch(sky2->rx_ring + sky2->rx_next);
1984 if (status & GMR_FS_ANY_ERR)
1987 if (!(status & GMR_FS_RX_OK))
1990 if (length > dev->mtu + ETH_HLEN)
1993 if (length < copybreak)
1994 skb = receive_copy(sky2, re, length);
1996 skb = receive_new(sky2, re, length);
1998 sky2_rx_submit(sky2, re);
2003 ++sky2->net_stats.rx_over_errors;
2007 ++sky2->net_stats.rx_errors;
2008 if (status & GMR_FS_RX_FF_OV) {
2009 sky2->net_stats.rx_fifo_errors++;
2013 if (netif_msg_rx_err(sky2) && net_ratelimit())
2014 printk(KERN_INFO PFX "%s: rx error, status 0x%x length %d\n",
2015 dev->name, status, length);
2017 if (status & (GMR_FS_LONG_ERR | GMR_FS_UN_SIZE))
2018 sky2->net_stats.rx_length_errors++;
2019 if (status & GMR_FS_FRAGMENT)
2020 sky2->net_stats.rx_frame_errors++;
2021 if (status & GMR_FS_CRC_ERR)
2022 sky2->net_stats.rx_crc_errors++;
2027 /* Transmit complete */
2028 static inline void sky2_tx_done(struct net_device *dev, u16 last)
2030 struct sky2_port *sky2 = netdev_priv(dev);
2032 if (netif_running(dev)) {
2034 sky2_tx_complete(sky2, last);
2035 netif_tx_unlock(dev);
2039 /* Process status response ring */
2040 static int sky2_status_intr(struct sky2_hw *hw, int to_do)
2042 struct sky2_port *sky2;
2044 unsigned buf_write[2] = { 0, 0 };
2045 u16 hwidx = sky2_read16(hw, STAT_PUT_IDX);
2049 while (hw->st_idx != hwidx) {
2050 struct sky2_status_le *le = hw->st_le + hw->st_idx;
2051 struct net_device *dev;
2052 struct sk_buff *skb;
2056 hw->st_idx = RING_NEXT(hw->st_idx, STATUS_RING_SIZE);
2058 BUG_ON(le->link >= 2);
2059 dev = hw->dev[le->link];
2061 sky2 = netdev_priv(dev);
2062 length = le16_to_cpu(le->length);
2063 status = le32_to_cpu(le->status);
2065 switch (le->opcode & ~HW_OWNER) {
2067 skb = sky2_receive(dev, length, status);
2071 skb->protocol = eth_type_trans(skb, dev);
2072 dev->last_rx = jiffies;
2074 #ifdef SKY2_VLAN_TAG_USED
2075 if (sky2->vlgrp && (status & GMR_FS_VLAN)) {
2076 vlan_hwaccel_receive_skb(skb,
2078 be16_to_cpu(sky2->rx_tag));
2081 netif_receive_skb(skb);
2083 /* Update receiver after 16 frames */
2084 if (++buf_write[le->link] == RX_BUF_WRITE) {
2086 sky2_put_idx(hw, rxqaddr[le->link], sky2->rx_put);
2087 buf_write[le->link] = 0;
2090 /* Stop after net poll weight */
2091 if (++work_done >= to_do)
2095 #ifdef SKY2_VLAN_TAG_USED
2097 sky2->rx_tag = length;
2101 sky2->rx_tag = length;
2105 skb = sky2->rx_ring[sky2->rx_next].skb;
2106 skb->ip_summed = CHECKSUM_COMPLETE;
2107 skb->csum = status & 0xffff;
2111 /* TX index reports status for both ports */
2112 BUILD_BUG_ON(TX_RING_SIZE > 0x1000);
2113 sky2_tx_done(hw->dev[0], status & 0xfff);
2115 sky2_tx_done(hw->dev[1],
2116 ((status >> 24) & 0xff)
2117 | (u16)(length & 0xf) << 8);
2121 if (net_ratelimit())
2122 printk(KERN_WARNING PFX
2123 "unknown status opcode 0x%x\n", le->opcode);
2128 /* Fully processed status ring so clear irq */
2129 sky2_write32(hw, STAT_CTRL, SC_STAT_CLR_IRQ);
2133 sky2 = netdev_priv(hw->dev[0]);
2134 sky2_put_idx(hw, Q_R1, sky2->rx_put);
2138 sky2 = netdev_priv(hw->dev[1]);
2139 sky2_put_idx(hw, Q_R2, sky2->rx_put);
2145 static void sky2_hw_error(struct sky2_hw *hw, unsigned port, u32 status)
2147 struct net_device *dev = hw->dev[port];
2149 if (net_ratelimit())
2150 printk(KERN_INFO PFX "%s: hw error interrupt status 0x%x\n",
2153 if (status & Y2_IS_PAR_RD1) {
2154 if (net_ratelimit())
2155 printk(KERN_ERR PFX "%s: ram data read parity error\n",
2158 sky2_write16(hw, RAM_BUFFER(port, B3_RI_CTRL), RI_CLR_RD_PERR);
2161 if (status & Y2_IS_PAR_WR1) {
2162 if (net_ratelimit())
2163 printk(KERN_ERR PFX "%s: ram data write parity error\n",
2166 sky2_write16(hw, RAM_BUFFER(port, B3_RI_CTRL), RI_CLR_WR_PERR);
2169 if (status & Y2_IS_PAR_MAC1) {
2170 if (net_ratelimit())
2171 printk(KERN_ERR PFX "%s: MAC parity error\n", dev->name);
2172 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_CLI_TX_PE);
2175 if (status & Y2_IS_PAR_RX1) {
2176 if (net_ratelimit())
2177 printk(KERN_ERR PFX "%s: RX parity error\n", dev->name);
2178 sky2_write32(hw, Q_ADDR(rxqaddr[port], Q_CSR), BMU_CLR_IRQ_PAR);
2181 if (status & Y2_IS_TCP_TXA1) {
2182 if (net_ratelimit())
2183 printk(KERN_ERR PFX "%s: TCP segmentation error\n",
2185 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), BMU_CLR_IRQ_TCP);
2189 static void sky2_hw_intr(struct sky2_hw *hw)
2191 u32 status = sky2_read32(hw, B0_HWE_ISRC);
2193 if (status & Y2_IS_TIST_OV)
2194 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ);
2196 if (status & (Y2_IS_MST_ERR | Y2_IS_IRQ_STAT)) {
2199 pci_err = sky2_pci_read16(hw, PCI_STATUS);
2200 if (net_ratelimit())
2201 printk(KERN_ERR PFX "%s: pci hw error (0x%x)\n",
2202 pci_name(hw->pdev), pci_err);
2204 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
2205 sky2_pci_write16(hw, PCI_STATUS,
2206 pci_err | PCI_STATUS_ERROR_BITS);
2207 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
2210 if (status & Y2_IS_PCI_EXP) {
2211 /* PCI-Express uncorrectable Error occurred */
2214 pex_err = sky2_pci_read32(hw, PEX_UNC_ERR_STAT);
2216 if (net_ratelimit())
2217 printk(KERN_ERR PFX "%s: pci express error (0x%x)\n",
2218 pci_name(hw->pdev), pex_err);
2220 /* clear the interrupt */
2221 sky2_write32(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
2222 sky2_pci_write32(hw, PEX_UNC_ERR_STAT,
2224 sky2_write32(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
2226 if (pex_err & PEX_FATAL_ERRORS) {
2227 u32 hwmsk = sky2_read32(hw, B0_HWE_IMSK);
2228 hwmsk &= ~Y2_IS_PCI_EXP;
2229 sky2_write32(hw, B0_HWE_IMSK, hwmsk);
2233 if (status & Y2_HWE_L1_MASK)
2234 sky2_hw_error(hw, 0, status);
2236 if (status & Y2_HWE_L1_MASK)
2237 sky2_hw_error(hw, 1, status);
2240 static void sky2_mac_intr(struct sky2_hw *hw, unsigned port)
2242 struct net_device *dev = hw->dev[port];
2243 struct sky2_port *sky2 = netdev_priv(dev);
2244 u8 status = sky2_read8(hw, SK_REG(port, GMAC_IRQ_SRC));
2246 if (netif_msg_intr(sky2))
2247 printk(KERN_INFO PFX "%s: mac interrupt status 0x%x\n",
2250 if (status & GM_IS_RX_FF_OR) {
2251 ++sky2->net_stats.rx_fifo_errors;
2252 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_CLI_RX_FO);
2255 if (status & GM_IS_TX_FF_UR) {
2256 ++sky2->net_stats.tx_fifo_errors;
2257 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_CLI_TX_FU);
2261 /* This should never happen it is a fatal situation */
2262 static void sky2_descriptor_error(struct sky2_hw *hw, unsigned port,
2263 const char *rxtx, u32 mask)
2265 struct net_device *dev = hw->dev[port];
2266 struct sky2_port *sky2 = netdev_priv(dev);
2269 printk(KERN_ERR PFX "%s: %s descriptor error (hardware problem)\n",
2270 dev ? dev->name : "<not registered>", rxtx);
2272 imask = sky2_read32(hw, B0_IMSK);
2274 sky2_write32(hw, B0_IMSK, imask);
2277 spin_lock(&sky2->phy_lock);
2278 sky2_link_down(sky2);
2279 spin_unlock(&sky2->phy_lock);
2283 /* If idle then force a fake soft NAPI poll once a second
2284 * to work around cases where sharing an edge triggered interrupt.
2286 static inline void sky2_idle_start(struct sky2_hw *hw)
2288 if (idle_timeout > 0)
2289 mod_timer(&hw->idle_timer,
2290 jiffies + msecs_to_jiffies(idle_timeout));
2293 static void sky2_idle(unsigned long arg)
2295 struct sky2_hw *hw = (struct sky2_hw *) arg;
2296 struct net_device *dev = hw->dev[0];
2298 if (__netif_rx_schedule_prep(dev))
2299 __netif_rx_schedule(dev);
2301 mod_timer(&hw->idle_timer, jiffies + msecs_to_jiffies(idle_timeout));
2305 static int sky2_poll(struct net_device *dev0, int *budget)
2307 struct sky2_hw *hw = ((struct sky2_port *) netdev_priv(dev0))->hw;
2308 int work_limit = min(dev0->quota, *budget);
2310 u32 status = sky2_read32(hw, B0_Y2_SP_EISR);
2312 if (status & Y2_IS_HW_ERR)
2315 if (status & Y2_IS_IRQ_PHY1)
2316 sky2_phy_intr(hw, 0);
2318 if (status & Y2_IS_IRQ_PHY2)
2319 sky2_phy_intr(hw, 1);
2321 if (status & Y2_IS_IRQ_MAC1)
2322 sky2_mac_intr(hw, 0);
2324 if (status & Y2_IS_IRQ_MAC2)
2325 sky2_mac_intr(hw, 1);
2327 if (status & Y2_IS_CHK_RX1)
2328 sky2_descriptor_error(hw, 0, "receive", Y2_IS_CHK_RX1);
2330 if (status & Y2_IS_CHK_RX2)
2331 sky2_descriptor_error(hw, 1, "receive", Y2_IS_CHK_RX2);
2333 if (status & Y2_IS_CHK_TXA1)
2334 sky2_descriptor_error(hw, 0, "transmit", Y2_IS_CHK_TXA1);
2336 if (status & Y2_IS_CHK_TXA2)
2337 sky2_descriptor_error(hw, 1, "transmit", Y2_IS_CHK_TXA2);
2339 work_done = sky2_status_intr(hw, work_limit);
2340 if (work_done < work_limit) {
2341 netif_rx_complete(dev0);
2343 sky2_read32(hw, B0_Y2_SP_LISR);
2346 *budget -= work_done;
2347 dev0->quota -= work_done;
2352 static irqreturn_t sky2_intr(int irq, void *dev_id)
2354 struct sky2_hw *hw = dev_id;
2355 struct net_device *dev0 = hw->dev[0];
2358 /* Reading this mask interrupts as side effect */
2359 status = sky2_read32(hw, B0_Y2_SP_ISRC2);
2360 if (status == 0 || status == ~0)
2363 prefetch(&hw->st_le[hw->st_idx]);
2364 if (likely(__netif_rx_schedule_prep(dev0)))
2365 __netif_rx_schedule(dev0);
2370 #ifdef CONFIG_NET_POLL_CONTROLLER
2371 static void sky2_netpoll(struct net_device *dev)
2373 struct sky2_port *sky2 = netdev_priv(dev);
2374 struct net_device *dev0 = sky2->hw->dev[0];
2376 if (netif_running(dev) && __netif_rx_schedule_prep(dev0))
2377 __netif_rx_schedule(dev0);
2381 /* Chip internal frequency for clock calculations */
2382 static inline u32 sky2_mhz(const struct sky2_hw *hw)
2384 switch (hw->chip_id) {
2385 case CHIP_ID_YUKON_EC:
2386 case CHIP_ID_YUKON_EC_U:
2387 return 125; /* 125 Mhz */
2388 case CHIP_ID_YUKON_FE:
2389 return 100; /* 100 Mhz */
2390 default: /* YUKON_XL */
2391 return 156; /* 156 Mhz */
2395 static inline u32 sky2_us2clk(const struct sky2_hw *hw, u32 us)
2397 return sky2_mhz(hw) * us;
2400 static inline u32 sky2_clk2us(const struct sky2_hw *hw, u32 clk)
2402 return clk / sky2_mhz(hw);
2406 static int sky2_reset(struct sky2_hw *hw)
2412 sky2_write8(hw, B0_CTST, CS_RST_CLR);
2414 hw->chip_id = sky2_read8(hw, B2_CHIP_ID);
2415 if (hw->chip_id < CHIP_ID_YUKON_XL || hw->chip_id > CHIP_ID_YUKON_FE) {
2416 printk(KERN_ERR PFX "%s: unsupported chip type 0x%x\n",
2417 pci_name(hw->pdev), hw->chip_id);
2421 hw->chip_rev = (sky2_read8(hw, B2_MAC_CFG) & CFG_CHIP_R_MSK) >> 4;
2423 /* This rev is really old, and requires untested workarounds */
2424 if (hw->chip_id == CHIP_ID_YUKON_EC && hw->chip_rev == CHIP_REV_YU_EC_A1) {
2425 printk(KERN_ERR PFX "%s: unsupported revision Yukon-%s (0x%x) rev %d\n",
2426 pci_name(hw->pdev), yukon2_name[hw->chip_id - CHIP_ID_YUKON_XL],
2427 hw->chip_id, hw->chip_rev);
2432 if (hw->chip_id <= CHIP_ID_YUKON_EC) {
2433 sky2_write8(hw, B28_Y2_ASF_STAT_CMD, Y2_ASF_RESET);
2434 sky2_write16(hw, B0_CTST, Y2_ASF_DISABLE);
2438 sky2_write8(hw, B0_CTST, CS_RST_SET);
2439 sky2_write8(hw, B0_CTST, CS_RST_CLR);
2441 /* clear PCI errors, if any */
2442 status = sky2_pci_read16(hw, PCI_STATUS);
2444 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
2445 sky2_pci_write16(hw, PCI_STATUS, status | PCI_STATUS_ERROR_BITS);
2448 sky2_write8(hw, B0_CTST, CS_MRST_CLR);
2450 /* clear any PEX errors */
2451 if (pci_find_capability(hw->pdev, PCI_CAP_ID_EXP))
2452 sky2_pci_write32(hw, PEX_UNC_ERR_STAT, 0xffffffffUL);
2455 hw->pmd_type = sky2_read8(hw, B2_PMD_TYP);
2457 t8 = sky2_read8(hw, B2_Y2_HW_RES);
2458 if ((t8 & CFG_DUAL_MAC_MSK) == CFG_DUAL_MAC_MSK) {
2459 if (!(sky2_read8(hw, B2_Y2_CLK_GATE) & Y2_STATUS_LNK2_INAC))
2463 sky2_set_power_state(hw, PCI_D0);
2465 for (i = 0; i < hw->ports; i++) {
2466 sky2_write8(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_SET);
2467 sky2_write8(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_CLR);
2470 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
2472 /* Clear I2C IRQ noise */
2473 sky2_write32(hw, B2_I2C_IRQ, 1);
2475 /* turn off hardware timer (unused) */
2476 sky2_write8(hw, B2_TI_CTRL, TIM_STOP);
2477 sky2_write8(hw, B2_TI_CTRL, TIM_CLR_IRQ);
2479 sky2_write8(hw, B0_Y2LED, LED_STAT_ON);
2481 /* Turn off descriptor polling */
2482 sky2_write32(hw, B28_DPT_CTRL, DPT_STOP);
2484 /* Turn off receive timestamp */
2485 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_STOP);
2486 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ);
2488 /* enable the Tx Arbiters */
2489 for (i = 0; i < hw->ports; i++)
2490 sky2_write8(hw, SK_REG(i, TXA_CTRL), TXA_ENA_ARB);
2492 /* Initialize ram interface */
2493 for (i = 0; i < hw->ports; i++) {
2494 sky2_write8(hw, RAM_BUFFER(i, B3_RI_CTRL), RI_RST_CLR);
2496 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_R1), SK_RI_TO_53);
2497 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XA1), SK_RI_TO_53);
2498 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XS1), SK_RI_TO_53);
2499 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_R1), SK_RI_TO_53);
2500 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XA1), SK_RI_TO_53);
2501 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XS1), SK_RI_TO_53);
2502 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_R2), SK_RI_TO_53);
2503 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XA2), SK_RI_TO_53);
2504 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XS2), SK_RI_TO_53);
2505 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_R2), SK_RI_TO_53);
2506 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XA2), SK_RI_TO_53);
2507 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XS2), SK_RI_TO_53);
2510 sky2_write32(hw, B0_HWE_IMSK, Y2_HWE_ALL_MASK);
2512 for (i = 0; i < hw->ports; i++)
2513 sky2_gmac_reset(hw, i);
2515 memset(hw->st_le, 0, STATUS_LE_BYTES);
2518 sky2_write32(hw, STAT_CTRL, SC_STAT_RST_SET);
2519 sky2_write32(hw, STAT_CTRL, SC_STAT_RST_CLR);
2521 sky2_write32(hw, STAT_LIST_ADDR_LO, hw->st_dma);
2522 sky2_write32(hw, STAT_LIST_ADDR_HI, (u64) hw->st_dma >> 32);
2524 /* Set the list last index */
2525 sky2_write16(hw, STAT_LAST_IDX, STATUS_RING_SIZE - 1);
2527 sky2_write16(hw, STAT_TX_IDX_TH, 10);
2528 sky2_write8(hw, STAT_FIFO_WM, 16);
2530 /* set Status-FIFO ISR watermark */
2531 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0)
2532 sky2_write8(hw, STAT_FIFO_ISR_WM, 4);
2534 sky2_write8(hw, STAT_FIFO_ISR_WM, 16);
2536 sky2_write32(hw, STAT_TX_TIMER_INI, sky2_us2clk(hw, 1000));
2537 sky2_write32(hw, STAT_ISR_TIMER_INI, sky2_us2clk(hw, 20));
2538 sky2_write32(hw, STAT_LEV_TIMER_INI, sky2_us2clk(hw, 100));
2540 /* enable status unit */
2541 sky2_write32(hw, STAT_CTRL, SC_STAT_OP_ON);
2543 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_START);
2544 sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_START);
2545 sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_START);
2550 static u32 sky2_supported_modes(const struct sky2_hw *hw)
2552 if (sky2_is_copper(hw)) {
2553 u32 modes = SUPPORTED_10baseT_Half
2554 | SUPPORTED_10baseT_Full
2555 | SUPPORTED_100baseT_Half
2556 | SUPPORTED_100baseT_Full
2557 | SUPPORTED_Autoneg | SUPPORTED_TP;
2559 if (hw->chip_id != CHIP_ID_YUKON_FE)
2560 modes |= SUPPORTED_1000baseT_Half
2561 | SUPPORTED_1000baseT_Full;
2564 return SUPPORTED_1000baseT_Half
2565 | SUPPORTED_1000baseT_Full
2570 static int sky2_get_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
2572 struct sky2_port *sky2 = netdev_priv(dev);
2573 struct sky2_hw *hw = sky2->hw;
2575 ecmd->transceiver = XCVR_INTERNAL;
2576 ecmd->supported = sky2_supported_modes(hw);
2577 ecmd->phy_address = PHY_ADDR_MARV;
2578 if (sky2_is_copper(hw)) {
2579 ecmd->supported = SUPPORTED_10baseT_Half
2580 | SUPPORTED_10baseT_Full
2581 | SUPPORTED_100baseT_Half
2582 | SUPPORTED_100baseT_Full
2583 | SUPPORTED_1000baseT_Half
2584 | SUPPORTED_1000baseT_Full
2585 | SUPPORTED_Autoneg | SUPPORTED_TP;
2586 ecmd->port = PORT_TP;
2587 ecmd->speed = sky2->speed;
2589 ecmd->speed = SPEED_1000;
2590 ecmd->port = PORT_FIBRE;
2593 ecmd->advertising = sky2->advertising;
2594 ecmd->autoneg = sky2->autoneg;
2595 ecmd->duplex = sky2->duplex;
2599 static int sky2_set_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
2601 struct sky2_port *sky2 = netdev_priv(dev);
2602 const struct sky2_hw *hw = sky2->hw;
2603 u32 supported = sky2_supported_modes(hw);
2605 if (ecmd->autoneg == AUTONEG_ENABLE) {
2606 ecmd->advertising = supported;
2612 switch (ecmd->speed) {
2614 if (ecmd->duplex == DUPLEX_FULL)
2615 setting = SUPPORTED_1000baseT_Full;
2616 else if (ecmd->duplex == DUPLEX_HALF)
2617 setting = SUPPORTED_1000baseT_Half;
2622 if (ecmd->duplex == DUPLEX_FULL)
2623 setting = SUPPORTED_100baseT_Full;
2624 else if (ecmd->duplex == DUPLEX_HALF)
2625 setting = SUPPORTED_100baseT_Half;
2631 if (ecmd->duplex == DUPLEX_FULL)
2632 setting = SUPPORTED_10baseT_Full;
2633 else if (ecmd->duplex == DUPLEX_HALF)
2634 setting = SUPPORTED_10baseT_Half;
2642 if ((setting & supported) == 0)
2645 sky2->speed = ecmd->speed;
2646 sky2->duplex = ecmd->duplex;
2649 sky2->autoneg = ecmd->autoneg;
2650 sky2->advertising = ecmd->advertising;
2652 if (netif_running(dev))
2653 sky2_phy_reinit(sky2);
2658 static void sky2_get_drvinfo(struct net_device *dev,
2659 struct ethtool_drvinfo *info)
2661 struct sky2_port *sky2 = netdev_priv(dev);
2663 strcpy(info->driver, DRV_NAME);
2664 strcpy(info->version, DRV_VERSION);
2665 strcpy(info->fw_version, "N/A");
2666 strcpy(info->bus_info, pci_name(sky2->hw->pdev));
2669 static const struct sky2_stat {
2670 char name[ETH_GSTRING_LEN];
2673 { "tx_bytes", GM_TXO_OK_HI },
2674 { "rx_bytes", GM_RXO_OK_HI },
2675 { "tx_broadcast", GM_TXF_BC_OK },
2676 { "rx_broadcast", GM_RXF_BC_OK },
2677 { "tx_multicast", GM_TXF_MC_OK },
2678 { "rx_multicast", GM_RXF_MC_OK },
2679 { "tx_unicast", GM_TXF_UC_OK },
2680 { "rx_unicast", GM_RXF_UC_OK },
2681 { "tx_mac_pause", GM_TXF_MPAUSE },
2682 { "rx_mac_pause", GM_RXF_MPAUSE },
2683 { "collisions", GM_TXF_COL },
2684 { "late_collision",GM_TXF_LAT_COL },
2685 { "aborted", GM_TXF_ABO_COL },
2686 { "single_collisions", GM_TXF_SNG_COL },
2687 { "multi_collisions", GM_TXF_MUL_COL },
2689 { "rx_short", GM_RXF_SHT },
2690 { "rx_runt", GM_RXE_FRAG },
2691 { "rx_64_byte_packets", GM_RXF_64B },
2692 { "rx_65_to_127_byte_packets", GM_RXF_127B },
2693 { "rx_128_to_255_byte_packets", GM_RXF_255B },
2694 { "rx_256_to_511_byte_packets", GM_RXF_511B },
2695 { "rx_512_to_1023_byte_packets", GM_RXF_1023B },
2696 { "rx_1024_to_1518_byte_packets", GM_RXF_1518B },
2697 { "rx_1518_to_max_byte_packets", GM_RXF_MAX_SZ },
2698 { "rx_too_long", GM_RXF_LNG_ERR },
2699 { "rx_fifo_overflow", GM_RXE_FIFO_OV },
2700 { "rx_jabber", GM_RXF_JAB_PKT },
2701 { "rx_fcs_error", GM_RXF_FCS_ERR },
2703 { "tx_64_byte_packets", GM_TXF_64B },
2704 { "tx_65_to_127_byte_packets", GM_TXF_127B },
2705 { "tx_128_to_255_byte_packets", GM_TXF_255B },
2706 { "tx_256_to_511_byte_packets", GM_TXF_511B },
2707 { "tx_512_to_1023_byte_packets", GM_TXF_1023B },
2708 { "tx_1024_to_1518_byte_packets", GM_TXF_1518B },
2709 { "tx_1519_to_max_byte_packets", GM_TXF_MAX_SZ },
2710 { "tx_fifo_underrun", GM_TXE_FIFO_UR },
2713 static u32 sky2_get_rx_csum(struct net_device *dev)
2715 struct sky2_port *sky2 = netdev_priv(dev);
2717 return sky2->rx_csum;
2720 static int sky2_set_rx_csum(struct net_device *dev, u32 data)
2722 struct sky2_port *sky2 = netdev_priv(dev);
2724 sky2->rx_csum = data;
2726 sky2_write32(sky2->hw, Q_ADDR(rxqaddr[sky2->port], Q_CSR),
2727 data ? BMU_ENA_RX_CHKSUM : BMU_DIS_RX_CHKSUM);
2732 static u32 sky2_get_msglevel(struct net_device *netdev)
2734 struct sky2_port *sky2 = netdev_priv(netdev);
2735 return sky2->msg_enable;
2738 static int sky2_nway_reset(struct net_device *dev)
2740 struct sky2_port *sky2 = netdev_priv(dev);
2742 if (!netif_running(dev) || sky2->autoneg != AUTONEG_ENABLE)
2745 sky2_phy_reinit(sky2);
2750 static void sky2_phy_stats(struct sky2_port *sky2, u64 * data, unsigned count)
2752 struct sky2_hw *hw = sky2->hw;
2753 unsigned port = sky2->port;
2756 data[0] = (u64) gma_read32(hw, port, GM_TXO_OK_HI) << 32
2757 | (u64) gma_read32(hw, port, GM_TXO_OK_LO);
2758 data[1] = (u64) gma_read32(hw, port, GM_RXO_OK_HI) << 32
2759 | (u64) gma_read32(hw, port, GM_RXO_OK_LO);
2761 for (i = 2; i < count; i++)
2762 data[i] = (u64) gma_read32(hw, port, sky2_stats[i].offset);
2765 static void sky2_set_msglevel(struct net_device *netdev, u32 value)
2767 struct sky2_port *sky2 = netdev_priv(netdev);
2768 sky2->msg_enable = value;
2771 static int sky2_get_stats_count(struct net_device *dev)
2773 return ARRAY_SIZE(sky2_stats);
2776 static void sky2_get_ethtool_stats(struct net_device *dev,
2777 struct ethtool_stats *stats, u64 * data)
2779 struct sky2_port *sky2 = netdev_priv(dev);
2781 sky2_phy_stats(sky2, data, ARRAY_SIZE(sky2_stats));
2784 static void sky2_get_strings(struct net_device *dev, u32 stringset, u8 * data)
2788 switch (stringset) {
2790 for (i = 0; i < ARRAY_SIZE(sky2_stats); i++)
2791 memcpy(data + i * ETH_GSTRING_LEN,
2792 sky2_stats[i].name, ETH_GSTRING_LEN);
2797 /* Use hardware MIB variables for critical path statistics and
2798 * transmit feedback not reported at interrupt.
2799 * Other errors are accounted for in interrupt handler.
2801 static struct net_device_stats *sky2_get_stats(struct net_device *dev)
2803 struct sky2_port *sky2 = netdev_priv(dev);
2806 sky2_phy_stats(sky2, data, ARRAY_SIZE(data));
2808 sky2->net_stats.tx_bytes = data[0];
2809 sky2->net_stats.rx_bytes = data[1];
2810 sky2->net_stats.tx_packets = data[2] + data[4] + data[6];
2811 sky2->net_stats.rx_packets = data[3] + data[5] + data[7];
2812 sky2->net_stats.multicast = data[3] + data[5];
2813 sky2->net_stats.collisions = data[10];
2814 sky2->net_stats.tx_aborted_errors = data[12];
2816 return &sky2->net_stats;
2819 static int sky2_set_mac_address(struct net_device *dev, void *p)
2821 struct sky2_port *sky2 = netdev_priv(dev);
2822 struct sky2_hw *hw = sky2->hw;
2823 unsigned port = sky2->port;
2824 const struct sockaddr *addr = p;
2826 if (!is_valid_ether_addr(addr->sa_data))
2827 return -EADDRNOTAVAIL;
2829 memcpy(dev->dev_addr, addr->sa_data, ETH_ALEN);
2830 memcpy_toio(hw->regs + B2_MAC_1 + port * 8,
2831 dev->dev_addr, ETH_ALEN);
2832 memcpy_toio(hw->regs + B2_MAC_2 + port * 8,
2833 dev->dev_addr, ETH_ALEN);
2835 /* virtual address for data */
2836 gma_set_addr(hw, port, GM_SRC_ADDR_2L, dev->dev_addr);
2838 /* physical address: used for pause frames */
2839 gma_set_addr(hw, port, GM_SRC_ADDR_1L, dev->dev_addr);
2844 static void inline sky2_add_filter(u8 filter[8], const u8 *addr)
2848 bit = ether_crc(ETH_ALEN, addr) & 63;
2849 filter[bit >> 3] |= 1 << (bit & 7);
2852 static void sky2_set_multicast(struct net_device *dev)
2854 struct sky2_port *sky2 = netdev_priv(dev);
2855 struct sky2_hw *hw = sky2->hw;
2856 unsigned port = sky2->port;
2857 struct dev_mc_list *list = dev->mc_list;
2861 static const u8 pause_mc_addr[ETH_ALEN] = { 0x1, 0x80, 0xc2, 0x0, 0x0, 0x1 };
2863 rx_pause = (sky2->flow_status == FC_RX || sky2->flow_status == FC_BOTH);
2864 memset(filter, 0, sizeof(filter));
2866 reg = gma_read16(hw, port, GM_RX_CTRL);
2867 reg |= GM_RXCR_UCF_ENA;
2869 if (dev->flags & IFF_PROMISC) /* promiscuous */
2870 reg &= ~(GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA);
2871 else if (dev->flags & IFF_ALLMULTI)
2872 memset(filter, 0xff, sizeof(filter));
2873 else if (dev->mc_count == 0 && !rx_pause)
2874 reg &= ~GM_RXCR_MCF_ENA;
2877 reg |= GM_RXCR_MCF_ENA;
2880 sky2_add_filter(filter, pause_mc_addr);
2882 for (i = 0; list && i < dev->mc_count; i++, list = list->next)
2883 sky2_add_filter(filter, list->dmi_addr);
2886 gma_write16(hw, port, GM_MC_ADDR_H1,
2887 (u16) filter[0] | ((u16) filter[1] << 8));
2888 gma_write16(hw, port, GM_MC_ADDR_H2,
2889 (u16) filter[2] | ((u16) filter[3] << 8));
2890 gma_write16(hw, port, GM_MC_ADDR_H3,
2891 (u16) filter[4] | ((u16) filter[5] << 8));
2892 gma_write16(hw, port, GM_MC_ADDR_H4,
2893 (u16) filter[6] | ((u16) filter[7] << 8));
2895 gma_write16(hw, port, GM_RX_CTRL, reg);
2898 /* Can have one global because blinking is controlled by
2899 * ethtool and that is always under RTNL mutex
2901 static void sky2_led(struct sky2_hw *hw, unsigned port, int on)
2905 switch (hw->chip_id) {
2906 case CHIP_ID_YUKON_XL:
2907 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
2908 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
2909 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
2910 on ? (PHY_M_LEDC_LOS_CTRL(1) |
2911 PHY_M_LEDC_INIT_CTRL(7) |
2912 PHY_M_LEDC_STA1_CTRL(7) |
2913 PHY_M_LEDC_STA0_CTRL(7))
2916 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
2920 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, 0);
2921 gm_phy_write(hw, port, PHY_MARV_LED_OVER,
2922 on ? PHY_M_LED_MO_DUP(MO_LED_ON) |
2923 PHY_M_LED_MO_10(MO_LED_ON) |
2924 PHY_M_LED_MO_100(MO_LED_ON) |
2925 PHY_M_LED_MO_1000(MO_LED_ON) |
2926 PHY_M_LED_MO_RX(MO_LED_ON)
2927 : PHY_M_LED_MO_DUP(MO_LED_OFF) |
2928 PHY_M_LED_MO_10(MO_LED_OFF) |
2929 PHY_M_LED_MO_100(MO_LED_OFF) |
2930 PHY_M_LED_MO_1000(MO_LED_OFF) |
2931 PHY_M_LED_MO_RX(MO_LED_OFF));
2936 /* blink LED's for finding board */
2937 static int sky2_phys_id(struct net_device *dev, u32 data)
2939 struct sky2_port *sky2 = netdev_priv(dev);
2940 struct sky2_hw *hw = sky2->hw;
2941 unsigned port = sky2->port;
2942 u16 ledctrl, ledover = 0;
2947 if (!data || data > (u32) (MAX_SCHEDULE_TIMEOUT / HZ))
2948 ms = jiffies_to_msecs(MAX_SCHEDULE_TIMEOUT);
2952 /* save initial values */
2953 spin_lock_bh(&sky2->phy_lock);
2954 if (hw->chip_id == CHIP_ID_YUKON_XL) {
2955 u16 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
2956 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
2957 ledctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
2958 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
2960 ledctrl = gm_phy_read(hw, port, PHY_MARV_LED_CTRL);
2961 ledover = gm_phy_read(hw, port, PHY_MARV_LED_OVER);
2965 while (!interrupted && ms > 0) {
2966 sky2_led(hw, port, onoff);
2969 spin_unlock_bh(&sky2->phy_lock);
2970 interrupted = msleep_interruptible(250);
2971 spin_lock_bh(&sky2->phy_lock);
2976 /* resume regularly scheduled programming */
2977 if (hw->chip_id == CHIP_ID_YUKON_XL) {
2978 u16 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
2979 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
2980 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ledctrl);
2981 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
2983 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, ledctrl);
2984 gm_phy_write(hw, port, PHY_MARV_LED_OVER, ledover);
2986 spin_unlock_bh(&sky2->phy_lock);
2991 static void sky2_get_pauseparam(struct net_device *dev,
2992 struct ethtool_pauseparam *ecmd)
2994 struct sky2_port *sky2 = netdev_priv(dev);
2996 switch (sky2->flow_mode) {
2998 ecmd->tx_pause = ecmd->rx_pause = 0;
3001 ecmd->tx_pause = 1, ecmd->rx_pause = 0;
3004 ecmd->tx_pause = 0, ecmd->rx_pause = 1;
3007 ecmd->tx_pause = ecmd->rx_pause = 1;
3010 ecmd->autoneg = sky2->autoneg;
3013 static int sky2_set_pauseparam(struct net_device *dev,
3014 struct ethtool_pauseparam *ecmd)
3016 struct sky2_port *sky2 = netdev_priv(dev);
3018 sky2->autoneg = ecmd->autoneg;
3019 sky2->flow_mode = sky2_flow(ecmd->rx_pause, ecmd->tx_pause);
3021 if (netif_running(dev))
3022 sky2_phy_reinit(sky2);
3027 static int sky2_get_coalesce(struct net_device *dev,
3028 struct ethtool_coalesce *ecmd)
3030 struct sky2_port *sky2 = netdev_priv(dev);
3031 struct sky2_hw *hw = sky2->hw;
3033 if (sky2_read8(hw, STAT_TX_TIMER_CTRL) == TIM_STOP)
3034 ecmd->tx_coalesce_usecs = 0;
3036 u32 clks = sky2_read32(hw, STAT_TX_TIMER_INI);
3037 ecmd->tx_coalesce_usecs = sky2_clk2us(hw, clks);
3039 ecmd->tx_max_coalesced_frames = sky2_read16(hw, STAT_TX_IDX_TH);
3041 if (sky2_read8(hw, STAT_LEV_TIMER_CTRL) == TIM_STOP)
3042 ecmd->rx_coalesce_usecs = 0;
3044 u32 clks = sky2_read32(hw, STAT_LEV_TIMER_INI);
3045 ecmd->rx_coalesce_usecs = sky2_clk2us(hw, clks);
3047 ecmd->rx_max_coalesced_frames = sky2_read8(hw, STAT_FIFO_WM);
3049 if (sky2_read8(hw, STAT_ISR_TIMER_CTRL) == TIM_STOP)
3050 ecmd->rx_coalesce_usecs_irq = 0;
3052 u32 clks = sky2_read32(hw, STAT_ISR_TIMER_INI);
3053 ecmd->rx_coalesce_usecs_irq = sky2_clk2us(hw, clks);
3056 ecmd->rx_max_coalesced_frames_irq = sky2_read8(hw, STAT_FIFO_ISR_WM);
3061 /* Note: this affect both ports */
3062 static int sky2_set_coalesce(struct net_device *dev,
3063 struct ethtool_coalesce *ecmd)
3065 struct sky2_port *sky2 = netdev_priv(dev);
3066 struct sky2_hw *hw = sky2->hw;
3067 const u32 tmax = sky2_clk2us(hw, 0x0ffffff);
3069 if (ecmd->tx_coalesce_usecs > tmax ||
3070 ecmd->rx_coalesce_usecs > tmax ||
3071 ecmd->rx_coalesce_usecs_irq > tmax)
3074 if (ecmd->tx_max_coalesced_frames >= TX_RING_SIZE-1)
3076 if (ecmd->rx_max_coalesced_frames > RX_MAX_PENDING)
3078 if (ecmd->rx_max_coalesced_frames_irq >RX_MAX_PENDING)
3081 if (ecmd->tx_coalesce_usecs == 0)
3082 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_STOP);
3084 sky2_write32(hw, STAT_TX_TIMER_INI,
3085 sky2_us2clk(hw, ecmd->tx_coalesce_usecs));
3086 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_START);
3088 sky2_write16(hw, STAT_TX_IDX_TH, ecmd->tx_max_coalesced_frames);
3090 if (ecmd->rx_coalesce_usecs == 0)
3091 sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_STOP);
3093 sky2_write32(hw, STAT_LEV_TIMER_INI,
3094 sky2_us2clk(hw, ecmd->rx_coalesce_usecs));
3095 sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_START);
3097 sky2_write8(hw, STAT_FIFO_WM, ecmd->rx_max_coalesced_frames);
3099 if (ecmd->rx_coalesce_usecs_irq == 0)
3100 sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_STOP);
3102 sky2_write32(hw, STAT_ISR_TIMER_INI,
3103 sky2_us2clk(hw, ecmd->rx_coalesce_usecs_irq));
3104 sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_START);
3106 sky2_write8(hw, STAT_FIFO_ISR_WM, ecmd->rx_max_coalesced_frames_irq);
3110 static void sky2_get_ringparam(struct net_device *dev,
3111 struct ethtool_ringparam *ering)
3113 struct sky2_port *sky2 = netdev_priv(dev);
3115 ering->rx_max_pending = RX_MAX_PENDING;
3116 ering->rx_mini_max_pending = 0;
3117 ering->rx_jumbo_max_pending = 0;
3118 ering->tx_max_pending = TX_RING_SIZE - 1;
3120 ering->rx_pending = sky2->rx_pending;
3121 ering->rx_mini_pending = 0;
3122 ering->rx_jumbo_pending = 0;
3123 ering->tx_pending = sky2->tx_pending;
3126 static int sky2_set_ringparam(struct net_device *dev,
3127 struct ethtool_ringparam *ering)
3129 struct sky2_port *sky2 = netdev_priv(dev);
3132 if (ering->rx_pending > RX_MAX_PENDING ||
3133 ering->rx_pending < 8 ||
3134 ering->tx_pending < MAX_SKB_TX_LE ||
3135 ering->tx_pending > TX_RING_SIZE - 1)
3138 if (netif_running(dev))
3141 sky2->rx_pending = ering->rx_pending;
3142 sky2->tx_pending = ering->tx_pending;
3144 if (netif_running(dev)) {
3149 sky2_set_multicast(dev);
3155 static int sky2_get_regs_len(struct net_device *dev)
3161 * Returns copy of control register region
3162 * Note: access to the RAM address register set will cause timeouts.
3164 static void sky2_get_regs(struct net_device *dev, struct ethtool_regs *regs,
3167 const struct sky2_port *sky2 = netdev_priv(dev);
3168 const void __iomem *io = sky2->hw->regs;
3170 BUG_ON(regs->len < B3_RI_WTO_R1);
3172 memset(p, 0, regs->len);
3174 memcpy_fromio(p, io, B3_RAM_ADDR);
3176 memcpy_fromio(p + B3_RI_WTO_R1,
3178 regs->len - B3_RI_WTO_R1);
3181 static const struct ethtool_ops sky2_ethtool_ops = {
3182 .get_settings = sky2_get_settings,
3183 .set_settings = sky2_set_settings,
3184 .get_drvinfo = sky2_get_drvinfo,
3185 .get_msglevel = sky2_get_msglevel,
3186 .set_msglevel = sky2_set_msglevel,
3187 .nway_reset = sky2_nway_reset,
3188 .get_regs_len = sky2_get_regs_len,
3189 .get_regs = sky2_get_regs,
3190 .get_link = ethtool_op_get_link,
3191 .get_sg = ethtool_op_get_sg,
3192 .set_sg = ethtool_op_set_sg,
3193 .get_tx_csum = ethtool_op_get_tx_csum,
3194 .set_tx_csum = ethtool_op_set_tx_csum,
3195 .get_tso = ethtool_op_get_tso,
3196 .set_tso = ethtool_op_set_tso,
3197 .get_rx_csum = sky2_get_rx_csum,
3198 .set_rx_csum = sky2_set_rx_csum,
3199 .get_strings = sky2_get_strings,
3200 .get_coalesce = sky2_get_coalesce,
3201 .set_coalesce = sky2_set_coalesce,
3202 .get_ringparam = sky2_get_ringparam,
3203 .set_ringparam = sky2_set_ringparam,
3204 .get_pauseparam = sky2_get_pauseparam,
3205 .set_pauseparam = sky2_set_pauseparam,
3206 .phys_id = sky2_phys_id,
3207 .get_stats_count = sky2_get_stats_count,
3208 .get_ethtool_stats = sky2_get_ethtool_stats,
3209 .get_perm_addr = ethtool_op_get_perm_addr,
3212 /* Initialize network device */
3213 static __devinit struct net_device *sky2_init_netdev(struct sky2_hw *hw,
3214 unsigned port, int highmem)
3216 struct sky2_port *sky2;
3217 struct net_device *dev = alloc_etherdev(sizeof(*sky2));
3220 printk(KERN_ERR "sky2 etherdev alloc failed");
3224 SET_MODULE_OWNER(dev);
3225 SET_NETDEV_DEV(dev, &hw->pdev->dev);
3226 dev->irq = hw->pdev->irq;
3227 dev->open = sky2_up;
3228 dev->stop = sky2_down;
3229 dev->do_ioctl = sky2_ioctl;
3230 dev->hard_start_xmit = sky2_xmit_frame;
3231 dev->get_stats = sky2_get_stats;
3232 dev->set_multicast_list = sky2_set_multicast;
3233 dev->set_mac_address = sky2_set_mac_address;
3234 dev->change_mtu = sky2_change_mtu;
3235 SET_ETHTOOL_OPS(dev, &sky2_ethtool_ops);
3236 dev->tx_timeout = sky2_tx_timeout;
3237 dev->watchdog_timeo = TX_WATCHDOG;
3239 dev->poll = sky2_poll;
3240 dev->weight = NAPI_WEIGHT;
3241 #ifdef CONFIG_NET_POLL_CONTROLLER
3242 /* Network console (only works on port 0)
3243 * because netpoll makes assumptions about NAPI
3246 dev->poll_controller = sky2_netpoll;
3249 sky2 = netdev_priv(dev);
3252 sky2->msg_enable = netif_msg_init(debug, default_msg);
3254 /* Auto speed and flow control */
3255 sky2->autoneg = AUTONEG_ENABLE;
3256 sky2->flow_mode = FC_BOTH;
3260 sky2->advertising = sky2_supported_modes(hw);
3263 spin_lock_init(&sky2->phy_lock);
3264 sky2->tx_pending = TX_DEF_PENDING;
3265 sky2->rx_pending = RX_DEF_PENDING;
3267 hw->dev[port] = dev;
3271 if (hw->chip_id != CHIP_ID_YUKON_EC_U)
3272 dev->features |= NETIF_F_TSO;
3274 dev->features |= NETIF_F_HIGHDMA;
3275 dev->features |= NETIF_F_IP_CSUM | NETIF_F_SG;
3277 #ifdef SKY2_VLAN_TAG_USED
3278 dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
3279 dev->vlan_rx_register = sky2_vlan_rx_register;
3280 dev->vlan_rx_kill_vid = sky2_vlan_rx_kill_vid;
3283 /* read the mac address */
3284 memcpy_fromio(dev->dev_addr, hw->regs + B2_MAC_1 + port * 8, ETH_ALEN);
3285 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
3287 /* device is off until link detection */
3288 netif_carrier_off(dev);
3289 netif_stop_queue(dev);
3294 static void __devinit sky2_show_addr(struct net_device *dev)
3296 const struct sky2_port *sky2 = netdev_priv(dev);
3298 if (netif_msg_probe(sky2))
3299 printk(KERN_INFO PFX "%s: addr %02x:%02x:%02x:%02x:%02x:%02x\n",
3301 dev->dev_addr[0], dev->dev_addr[1], dev->dev_addr[2],
3302 dev->dev_addr[3], dev->dev_addr[4], dev->dev_addr[5]);
3305 /* Handle software interrupt used during MSI test */
3306 static irqreturn_t __devinit sky2_test_intr(int irq, void *dev_id)
3308 struct sky2_hw *hw = dev_id;
3309 u32 status = sky2_read32(hw, B0_Y2_SP_ISRC2);
3314 if (status & Y2_IS_IRQ_SW) {
3316 wake_up(&hw->msi_wait);
3317 sky2_write8(hw, B0_CTST, CS_CL_SW_IRQ);
3319 sky2_write32(hw, B0_Y2_SP_ICR, 2);
3324 /* Test interrupt path by forcing a a software IRQ */
3325 static int __devinit sky2_test_msi(struct sky2_hw *hw)
3327 struct pci_dev *pdev = hw->pdev;
3330 init_waitqueue_head (&hw->msi_wait);
3332 sky2_write32(hw, B0_IMSK, Y2_IS_IRQ_SW);
3334 err = request_irq(pdev->irq, sky2_test_intr, 0, DRV_NAME, hw);
3336 printk(KERN_ERR PFX "%s: cannot assign irq %d\n",
3337 pci_name(pdev), pdev->irq);
3341 sky2_write8(hw, B0_CTST, CS_ST_SW_IRQ);
3342 sky2_read8(hw, B0_CTST);
3344 wait_event_timeout(hw->msi_wait, hw->msi, HZ/10);
3347 /* MSI test failed, go back to INTx mode */
3348 printk(KERN_INFO PFX "%s: No interrupt generated using MSI, "
3349 "switching to INTx mode.\n",
3353 sky2_write8(hw, B0_CTST, CS_CL_SW_IRQ);
3356 sky2_write32(hw, B0_IMSK, 0);
3357 sky2_read32(hw, B0_IMSK);
3359 free_irq(pdev->irq, hw);
3364 static int __devinit sky2_probe(struct pci_dev *pdev,
3365 const struct pci_device_id *ent)
3367 struct net_device *dev, *dev1 = NULL;
3369 int err, pm_cap, using_dac = 0;
3371 err = pci_enable_device(pdev);
3373 printk(KERN_ERR PFX "%s cannot enable PCI device\n",
3378 err = pci_request_regions(pdev, DRV_NAME);
3380 printk(KERN_ERR PFX "%s cannot obtain PCI resources\n",
3385 pci_set_master(pdev);
3387 /* Find power-management capability. */
3388 pm_cap = pci_find_capability(pdev, PCI_CAP_ID_PM);
3390 printk(KERN_ERR PFX "Cannot find PowerManagement capability, "
3393 goto err_out_free_regions;
3396 if (sizeof(dma_addr_t) > sizeof(u32) &&
3397 !(err = pci_set_dma_mask(pdev, DMA_64BIT_MASK))) {
3399 err = pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK);
3401 printk(KERN_ERR PFX "%s unable to obtain 64 bit DMA "
3402 "for consistent allocations\n", pci_name(pdev));
3403 goto err_out_free_regions;
3407 err = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
3409 printk(KERN_ERR PFX "%s no usable DMA configuration\n",
3411 goto err_out_free_regions;
3416 hw = kzalloc(sizeof(*hw), GFP_KERNEL);
3418 printk(KERN_ERR PFX "%s: cannot allocate hardware struct\n",
3420 goto err_out_free_regions;
3425 hw->regs = ioremap_nocache(pci_resource_start(pdev, 0), 0x4000);
3427 printk(KERN_ERR PFX "%s: cannot map device registers\n",
3429 goto err_out_free_hw;
3431 hw->pm_cap = pm_cap;
3434 /* The sk98lin vendor driver uses hardware byte swapping but
3435 * this driver uses software swapping.
3439 reg = sky2_pci_read32(hw, PCI_DEV_REG2);
3440 reg &= ~PCI_REV_DESC;
3441 sky2_pci_write32(hw, PCI_DEV_REG2, reg);
3445 /* ring for status responses */
3446 hw->st_le = pci_alloc_consistent(hw->pdev, STATUS_LE_BYTES,
3449 goto err_out_iounmap;
3451 err = sky2_reset(hw);
3453 goto err_out_iounmap;
3455 printk(KERN_INFO PFX "v%s addr 0x%llx irq %d Yukon-%s (0x%x) rev %d\n",
3456 DRV_VERSION, (unsigned long long)pci_resource_start(pdev, 0),
3457 pdev->irq, yukon2_name[hw->chip_id - CHIP_ID_YUKON_XL],
3458 hw->chip_id, hw->chip_rev);
3460 dev = sky2_init_netdev(hw, 0, using_dac);
3462 goto err_out_free_pci;
3464 if (!disable_msi && pci_enable_msi(pdev) == 0) {
3465 err = sky2_test_msi(hw);
3466 if (err == -EOPNOTSUPP)
3467 pci_disable_msi(pdev);
3469 goto err_out_free_netdev;
3472 err = register_netdev(dev);
3474 printk(KERN_ERR PFX "%s: cannot register net device\n",
3476 goto err_out_free_netdev;
3479 err = request_irq(pdev->irq, sky2_intr, hw->msi ? 0 : IRQF_SHARED,
3482 printk(KERN_ERR PFX "%s: cannot assign irq %d\n",
3483 pci_name(pdev), pdev->irq);
3484 goto err_out_unregister;
3486 sky2_write32(hw, B0_IMSK, Y2_IS_BASE);
3488 sky2_show_addr(dev);
3490 if (hw->ports > 1 && (dev1 = sky2_init_netdev(hw, 1, using_dac))) {
3491 if (register_netdev(dev1) == 0)
3492 sky2_show_addr(dev1);
3494 /* Failure to register second port need not be fatal */
3495 printk(KERN_WARNING PFX
3496 "register of second port failed\n");
3502 setup_timer(&hw->idle_timer, sky2_idle, (unsigned long) hw);
3503 sky2_idle_start(hw);
3505 pci_set_drvdata(pdev, hw);
3511 pci_disable_msi(pdev);
3512 unregister_netdev(dev);
3513 err_out_free_netdev:
3516 sky2_write8(hw, B0_CTST, CS_RST_SET);
3517 pci_free_consistent(hw->pdev, STATUS_LE_BYTES, hw->st_le, hw->st_dma);
3522 err_out_free_regions:
3523 pci_release_regions(pdev);
3524 pci_disable_device(pdev);
3529 static void __devexit sky2_remove(struct pci_dev *pdev)
3531 struct sky2_hw *hw = pci_get_drvdata(pdev);
3532 struct net_device *dev0, *dev1;
3537 del_timer_sync(&hw->idle_timer);
3539 sky2_write32(hw, B0_IMSK, 0);
3540 synchronize_irq(hw->pdev->irq);
3545 unregister_netdev(dev1);
3546 unregister_netdev(dev0);
3548 sky2_set_power_state(hw, PCI_D3hot);
3549 sky2_write16(hw, B0_Y2LED, LED_STAT_OFF);
3550 sky2_write8(hw, B0_CTST, CS_RST_SET);
3551 sky2_read8(hw, B0_CTST);
3553 free_irq(pdev->irq, hw);
3555 pci_disable_msi(pdev);
3556 pci_free_consistent(pdev, STATUS_LE_BYTES, hw->st_le, hw->st_dma);
3557 pci_release_regions(pdev);
3558 pci_disable_device(pdev);
3566 pci_set_drvdata(pdev, NULL);
3570 static int sky2_suspend(struct pci_dev *pdev, pm_message_t state)
3572 struct sky2_hw *hw = pci_get_drvdata(pdev);
3574 pci_power_t pstate = pci_choose_state(pdev, state);
3576 if (!(pstate == PCI_D3hot || pstate == PCI_D3cold))
3579 del_timer_sync(&hw->idle_timer);
3580 netif_poll_disable(hw->dev[0]);
3582 for (i = 0; i < hw->ports; i++) {
3583 struct net_device *dev = hw->dev[i];
3585 if (netif_running(dev)) {
3587 netif_device_detach(dev);
3591 sky2_write32(hw, B0_IMSK, 0);
3592 pci_save_state(pdev);
3593 sky2_set_power_state(hw, pstate);
3597 static int sky2_resume(struct pci_dev *pdev)
3599 struct sky2_hw *hw = pci_get_drvdata(pdev);
3602 pci_restore_state(pdev);
3603 pci_enable_wake(pdev, PCI_D0, 0);
3604 sky2_set_power_state(hw, PCI_D0);
3606 err = sky2_reset(hw);
3610 sky2_write32(hw, B0_IMSK, Y2_IS_BASE);
3612 for (i = 0; i < hw->ports; i++) {
3613 struct net_device *dev = hw->dev[i];
3614 if (netif_running(dev)) {
3615 netif_device_attach(dev);
3619 printk(KERN_ERR PFX "%s: could not up: %d\n",
3627 netif_poll_enable(hw->dev[0]);
3628 sky2_idle_start(hw);
3634 static struct pci_driver sky2_driver = {
3636 .id_table = sky2_id_table,
3637 .probe = sky2_probe,
3638 .remove = __devexit_p(sky2_remove),
3640 .suspend = sky2_suspend,
3641 .resume = sky2_resume,
3645 static int __init sky2_init_module(void)
3647 return pci_register_driver(&sky2_driver);
3650 static void __exit sky2_cleanup_module(void)
3652 pci_unregister_driver(&sky2_driver);
3655 module_init(sky2_init_module);
3656 module_exit(sky2_cleanup_module);
3658 MODULE_DESCRIPTION("Marvell Yukon 2 Gigabit Ethernet driver");
3659 MODULE_AUTHOR("Stephen Hemminger <shemminger@osdl.org>");
3660 MODULE_LICENSE("GPL");
3661 MODULE_VERSION(DRV_VERSION);