2 * New driver for Marvell Yukon 2 chipset.
3 * Based on earlier sk98lin, and skge driver.
5 * This driver intentionally does not support all the features
6 * of the original driver such as link fail-over and link management because
7 * those should be done at higher levels.
9 * Copyright (C) 2005 Stephen Hemminger <shemminger@osdl.org>
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License, or
14 * (at your option) any later version.
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
28 * - coalescing setting?
35 #include <linux/config.h>
36 #include <linux/crc32.h>
37 #include <linux/kernel.h>
38 #include <linux/version.h>
39 #include <linux/module.h>
40 #include <linux/netdevice.h>
41 #include <linux/dma-mapping.h>
42 #include <linux/etherdevice.h>
43 #include <linux/ethtool.h>
44 #include <linux/pci.h>
46 #include <linux/tcp.h>
48 #include <linux/delay.h>
49 #include <linux/if_vlan.h>
50 #include <linux/mii.h>
54 #if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
55 #define SKY2_VLAN_TAG_USED 1
60 #define DRV_NAME "sky2"
61 #define DRV_VERSION "0.7"
62 #define PFX DRV_NAME " "
65 * The Yukon II chipset takes 64 bit command blocks (called list elements)
66 * that are organized into three (receive, transmit, status) different rings
67 * similar to Tigon3. A transmit can require several elements;
68 * a receive requires one (or two if using 64 bit dma).
71 #define is_ec_a1(hw) \
72 unlikely((hw)->chip_id == CHIP_ID_YUKON_EC && \
73 (hw)->chip_rev == CHIP_REV_YU_EC_A1)
75 #define RX_LE_SIZE 512
76 #define RX_LE_BYTES (RX_LE_SIZE*sizeof(struct sky2_rx_le))
77 #define RX_MAX_PENDING (RX_LE_SIZE/2 - 2)
78 #define RX_DEF_PENDING RX_MAX_PENDING
79 #define RX_COPY_THRESHOLD 256
81 #define TX_RING_SIZE 512
82 #define TX_DEF_PENDING (TX_RING_SIZE - 1)
83 #define TX_MIN_PENDING 64
84 #define MAX_SKB_TX_LE (4 + 2*MAX_SKB_FRAGS)
86 #define STATUS_RING_SIZE 2048 /* 2 ports * (TX + 2*RX) */
87 #define STATUS_LE_BYTES (STATUS_RING_SIZE*sizeof(struct sky2_status_le))
88 #define ETH_JUMBO_MTU 9000
89 #define TX_WATCHDOG (5 * HZ)
90 #define NAPI_WEIGHT 64
91 #define PHY_RETRIES 1000
93 static const u32 default_msg =
94 NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_LINK
95 | NETIF_MSG_TIMER | NETIF_MSG_TX_ERR | NETIF_MSG_RX_ERR
96 | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN | NETIF_MSG_INTR;
98 static int debug = -1; /* defaults above */
99 module_param(debug, int, 0);
100 MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
102 static const struct pci_device_id sky2_id_table[] = {
103 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, 0x9000) },
104 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, 0x9E00) },
105 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4b00) },
106 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4b01) },
107 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4340) },
108 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4341) },
109 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4342) },
110 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4343) },
111 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4344) },
112 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4345) },
113 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4346) },
114 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4347) },
115 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4350) },
116 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4351) },
117 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4352) },
118 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4360) },
119 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4361) },
120 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4362) },
121 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4363) },
125 MODULE_DEVICE_TABLE(pci, sky2_id_table);
127 /* Avoid conditionals by using array */
128 static const unsigned txqaddr[] = { Q_XA1, Q_XA2 };
129 static const unsigned rxqaddr[] = { Q_R1, Q_R2 };
131 static const char *yukon_name[] = {
132 [CHIP_ID_YUKON_LITE - CHIP_ID_YUKON] = "Lite", /* 0xb0 */
133 [CHIP_ID_YUKON_LP - CHIP_ID_YUKON] = "LP", /* 0xb2 */
134 [CHIP_ID_YUKON_XL - CHIP_ID_YUKON] = "XL", /* 0xb3 */
135 [CHIP_ID_YUKON_EC_U - CHIP_ID_YUKON] = "EC Ultra", /* 0xb4 */
137 [CHIP_ID_YUKON_EC - CHIP_ID_YUKON] = "EC", /* 0xb6 */
138 [CHIP_ID_YUKON_FE - CHIP_ID_YUKON] = "FE", /* 0xb7 */
142 /* Access to external PHY */
143 static int gm_phy_write(struct sky2_hw *hw, unsigned port, u16 reg, u16 val)
147 gma_write16(hw, port, GM_SMI_DATA, val);
148 gma_write16(hw, port, GM_SMI_CTRL,
149 GM_SMI_CT_PHY_AD(PHY_ADDR_MARV) | GM_SMI_CT_REG_AD(reg));
151 for (i = 0; i < PHY_RETRIES; i++) {
152 if (!(gma_read16(hw, port, GM_SMI_CTRL) & GM_SMI_CT_BUSY))
157 printk(KERN_WARNING PFX "%s: phy write timeout\n", hw->dev[port]->name);
161 static int __gm_phy_read(struct sky2_hw *hw, unsigned port, u16 reg, u16 *val)
165 gma_write16(hw, port, GM_SMI_CTRL, GM_SMI_CT_PHY_AD(PHY_ADDR_MARV)
166 | GM_SMI_CT_REG_AD(reg) | GM_SMI_CT_OP_RD);
168 for (i = 0; i < PHY_RETRIES; i++) {
169 if (gma_read16(hw, port, GM_SMI_CTRL) & GM_SMI_CT_RD_VAL) {
170 *val = gma_read16(hw, port, GM_SMI_DATA);
180 static u16 gm_phy_read(struct sky2_hw *hw, unsigned port, u16 reg)
184 if (__gm_phy_read(hw, port, reg, &v) != 0)
185 printk(KERN_WARNING PFX "%s: phy read timeout\n", hw->dev[port]->name);
189 static int sky2_set_power_state(struct sky2_hw *hw, pci_power_t state)
196 pr_debug("sky2_set_power_state %d\n", state);
197 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
199 pci_read_config_word(hw->pdev, hw->pm_cap + PCI_PM_PMC, &power_control);
200 vaux = (sky2_read8(hw, B0_CTST) & Y2_VAUX_AVAIL) &&
201 (power_control & PCI_PM_CAP_PME_D3cold);
203 pci_read_config_word(hw->pdev, hw->pm_cap + PCI_PM_CTRL, &power_control);
205 power_control |= PCI_PM_CTRL_PME_STATUS;
206 power_control &= ~(PCI_PM_CTRL_STATE_MASK);
210 /* switch power to VCC (WA for VAUX problem) */
211 sky2_write8(hw, B0_POWER_CTRL,
212 PC_VAUX_ENA | PC_VCC_ENA | PC_VAUX_OFF | PC_VCC_ON);
214 /* disable Core Clock Division, */
215 sky2_write32(hw, B2_Y2_CLK_CTRL, Y2_CLK_DIV_DIS);
217 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1)
218 /* enable bits are inverted */
219 sky2_write8(hw, B2_Y2_CLK_GATE,
220 Y2_PCI_CLK_LNK1_DIS | Y2_COR_CLK_LNK1_DIS |
221 Y2_CLK_GAT_LNK1_DIS | Y2_PCI_CLK_LNK2_DIS |
222 Y2_COR_CLK_LNK2_DIS | Y2_CLK_GAT_LNK2_DIS);
224 sky2_write8(hw, B2_Y2_CLK_GATE, 0);
226 /* Turn off phy power saving */
227 pci_read_config_dword(hw->pdev, PCI_DEV_REG1, ®1);
228 reg1 &= ~(PCI_Y2_PHY1_POWD | PCI_Y2_PHY2_POWD);
230 /* looks like this XL is back asswards .. */
231 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1) {
232 reg1 |= PCI_Y2_PHY1_COMA;
234 reg1 |= PCI_Y2_PHY2_COMA;
236 pci_write_config_dword(hw->pdev, PCI_DEV_REG1, reg1);
241 /* Turn on phy power saving */
242 pci_read_config_dword(hw->pdev, PCI_DEV_REG1, ®1);
243 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1)
244 reg1 &= ~(PCI_Y2_PHY1_POWD | PCI_Y2_PHY2_POWD);
246 reg1 |= (PCI_Y2_PHY1_POWD | PCI_Y2_PHY2_POWD);
247 pci_write_config_dword(hw->pdev, PCI_DEV_REG1, reg1);
249 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1)
250 sky2_write8(hw, B2_Y2_CLK_GATE, 0);
252 /* enable bits are inverted */
253 sky2_write8(hw, B2_Y2_CLK_GATE,
254 Y2_PCI_CLK_LNK1_DIS | Y2_COR_CLK_LNK1_DIS |
255 Y2_CLK_GAT_LNK1_DIS | Y2_PCI_CLK_LNK2_DIS |
256 Y2_COR_CLK_LNK2_DIS | Y2_CLK_GAT_LNK2_DIS);
258 /* switch power to VAUX */
259 if (vaux && state != PCI_D3cold)
260 sky2_write8(hw, B0_POWER_CTRL,
261 (PC_VAUX_ENA | PC_VCC_ENA |
262 PC_VAUX_ON | PC_VCC_OFF));
265 printk(KERN_ERR PFX "Unknown power state %d\n", state);
269 pci_write_config_byte(hw->pdev, hw->pm_cap + PCI_PM_CTRL, power_control);
270 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
274 static void sky2_phy_reset(struct sky2_hw *hw, unsigned port)
278 /* disable all GMAC IRQ's */
279 sky2_write8(hw, SK_REG(port, GMAC_IRQ_MSK), 0);
280 /* disable PHY IRQs */
281 gm_phy_write(hw, port, PHY_MARV_INT_MASK, 0);
283 gma_write16(hw, port, GM_MC_ADDR_H1, 0); /* clear MC hash */
284 gma_write16(hw, port, GM_MC_ADDR_H2, 0);
285 gma_write16(hw, port, GM_MC_ADDR_H3, 0);
286 gma_write16(hw, port, GM_MC_ADDR_H4, 0);
288 reg = gma_read16(hw, port, GM_RX_CTRL);
289 reg |= GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA;
290 gma_write16(hw, port, GM_RX_CTRL, reg);
293 static void sky2_phy_init(struct sky2_hw *hw, unsigned port)
295 struct sky2_port *sky2 = netdev_priv(hw->dev[port]);
296 u16 ctrl, ct1000, adv, pg, ledctrl, ledover;
298 if (sky2->autoneg == AUTONEG_ENABLE && hw->chip_id != CHIP_ID_YUKON_XL) {
299 u16 ectrl = gm_phy_read(hw, port, PHY_MARV_EXT_CTRL);
301 ectrl &= ~(PHY_M_EC_M_DSC_MSK | PHY_M_EC_S_DSC_MSK |
303 ectrl |= PHY_M_EC_MAC_S(MAC_TX_CLK_25_MHZ);
305 if (hw->chip_id == CHIP_ID_YUKON_EC)
306 ectrl |= PHY_M_EC_DSC_2(2) | PHY_M_EC_DOWN_S_ENA;
308 ectrl |= PHY_M_EC_M_DSC(2) | PHY_M_EC_S_DSC(3);
310 gm_phy_write(hw, port, PHY_MARV_EXT_CTRL, ectrl);
313 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
315 if (hw->chip_id == CHIP_ID_YUKON_FE) {
316 /* enable automatic crossover */
317 ctrl |= PHY_M_PC_MDI_XMODE(PHY_M_PC_ENA_AUTO) >> 1;
319 /* disable energy detect */
320 ctrl &= ~PHY_M_PC_EN_DET_MSK;
322 /* enable automatic crossover */
323 ctrl |= PHY_M_PC_MDI_XMODE(PHY_M_PC_ENA_AUTO);
325 if (sky2->autoneg == AUTONEG_ENABLE &&
326 hw->chip_id == CHIP_ID_YUKON_XL) {
327 ctrl &= ~PHY_M_PC_DSC_MSK;
328 ctrl |= PHY_M_PC_DSC(2) | PHY_M_PC_DOWN_S_ENA;
331 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
333 /* workaround for deviation #4.88 (CRC errors) */
334 /* disable Automatic Crossover */
336 ctrl &= ~PHY_M_PC_MDIX_MSK;
337 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
339 if (hw->chip_id == CHIP_ID_YUKON_XL) {
340 /* Fiber: select 1000BASE-X only mode MAC Specific Ctrl Reg. */
341 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 2);
342 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
343 ctrl &= ~PHY_M_MAC_MD_MSK;
344 ctrl |= PHY_M_MAC_MODE_SEL(PHY_M_MAC_MD_1000BX);
345 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
347 /* select page 1 to access Fiber registers */
348 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 1);
352 ctrl = gm_phy_read(hw, port, PHY_MARV_CTRL);
353 if (sky2->autoneg == AUTONEG_DISABLE)
358 ctrl |= PHY_CT_RESET;
359 gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
365 if (sky2->autoneg == AUTONEG_ENABLE) {
367 if (sky2->advertising & ADVERTISED_1000baseT_Full)
368 ct1000 |= PHY_M_1000C_AFD;
369 if (sky2->advertising & ADVERTISED_1000baseT_Half)
370 ct1000 |= PHY_M_1000C_AHD;
371 if (sky2->advertising & ADVERTISED_100baseT_Full)
372 adv |= PHY_M_AN_100_FD;
373 if (sky2->advertising & ADVERTISED_100baseT_Half)
374 adv |= PHY_M_AN_100_HD;
375 if (sky2->advertising & ADVERTISED_10baseT_Full)
376 adv |= PHY_M_AN_10_FD;
377 if (sky2->advertising & ADVERTISED_10baseT_Half)
378 adv |= PHY_M_AN_10_HD;
379 } else /* special defines for FIBER (88E1011S only) */
380 adv |= PHY_M_AN_1000X_AHD | PHY_M_AN_1000X_AFD;
382 /* Set Flow-control capabilities */
383 if (sky2->tx_pause && sky2->rx_pause)
384 adv |= PHY_AN_PAUSE_CAP; /* symmetric */
385 else if (sky2->rx_pause && !sky2->tx_pause)
386 adv |= PHY_AN_PAUSE_ASYM | PHY_AN_PAUSE_CAP;
387 else if (!sky2->rx_pause && sky2->tx_pause)
388 adv |= PHY_AN_PAUSE_ASYM; /* local */
390 /* Restart Auto-negotiation */
391 ctrl |= PHY_CT_ANE | PHY_CT_RE_CFG;
393 /* forced speed/duplex settings */
394 ct1000 = PHY_M_1000C_MSE;
396 if (sky2->duplex == DUPLEX_FULL)
397 ctrl |= PHY_CT_DUP_MD;
399 switch (sky2->speed) {
401 ctrl |= PHY_CT_SP1000;
404 ctrl |= PHY_CT_SP100;
408 ctrl |= PHY_CT_RESET;
411 if (hw->chip_id != CHIP_ID_YUKON_FE)
412 gm_phy_write(hw, port, PHY_MARV_1000T_CTRL, ct1000);
414 gm_phy_write(hw, port, PHY_MARV_AUNE_ADV, adv);
415 gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
417 /* Setup Phy LED's */
418 ledctrl = PHY_M_LED_PULS_DUR(PULS_170MS);
421 switch (hw->chip_id) {
422 case CHIP_ID_YUKON_FE:
423 /* on 88E3082 these bits are at 11..9 (shifted left) */
424 ledctrl |= PHY_M_LED_BLINK_RT(BLINK_84MS) << 1;
426 ctrl = gm_phy_read(hw, port, PHY_MARV_FE_LED_PAR);
428 /* delete ACT LED control bits */
429 ctrl &= ~PHY_M_FELP_LED1_MSK;
430 /* change ACT LED control to blink mode */
431 ctrl |= PHY_M_FELP_LED1_CTRL(LED_PAR_CTRL_ACT_BL);
432 gm_phy_write(hw, port, PHY_MARV_FE_LED_PAR, ctrl);
435 case CHIP_ID_YUKON_XL:
436 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
438 /* select page 3 to access LED control register */
439 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
441 /* set LED Function Control register */
442 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, (PHY_M_LEDC_LOS_CTRL(1) | /* LINK/ACT */
443 PHY_M_LEDC_INIT_CTRL(7) | /* 10 Mbps */
444 PHY_M_LEDC_STA1_CTRL(7) | /* 100 Mbps */
445 PHY_M_LEDC_STA0_CTRL(7))); /* 1000 Mbps */
447 /* set Polarity Control register */
448 gm_phy_write(hw, port, PHY_MARV_PHY_STAT,
449 (PHY_M_POLC_LS1_P_MIX(4) |
450 PHY_M_POLC_IS0_P_MIX(4) |
451 PHY_M_POLC_LOS_CTRL(2) |
452 PHY_M_POLC_INIT_CTRL(2) |
453 PHY_M_POLC_STA1_CTRL(2) |
454 PHY_M_POLC_STA0_CTRL(2)));
456 /* restore page register */
457 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
461 /* set Tx LED (LED_TX) to blink mode on Rx OR Tx activity */
462 ledctrl |= PHY_M_LED_BLINK_RT(BLINK_84MS) | PHY_M_LEDC_TX_CTRL;
463 /* turn off the Rx LED (LED_RX) */
464 ledover |= PHY_M_LED_MO_RX(MO_LED_OFF);
467 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, ledctrl);
469 if (sky2->autoneg == AUTONEG_DISABLE || sky2->speed == SPEED_100) {
470 /* turn on 100 Mbps LED (LED_LINK100) */
471 ledover |= PHY_M_LED_MO_100(MO_LED_ON);
475 gm_phy_write(hw, port, PHY_MARV_LED_OVER, ledover);
477 /* Enable phy interrupt on auto-negotiation complete (or link up) */
478 if (sky2->autoneg == AUTONEG_ENABLE)
479 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_IS_AN_COMPL);
481 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_DEF_MSK);
484 static void sky2_mac_init(struct sky2_hw *hw, unsigned port)
486 struct sky2_port *sky2 = netdev_priv(hw->dev[port]);
489 const u8 *addr = hw->dev[port]->dev_addr;
491 sky2_write32(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET);
492 sky2_write32(hw, SK_REG(port, GPHY_CTRL), GPC_RST_CLR|GPC_ENA_PAUSE);
494 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_CLR);
496 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0 && port == 1) {
497 /* WA DEV_472 -- looks like crossed wires on port 2 */
498 /* clear GMAC 1 Control reset */
499 sky2_write8(hw, SK_REG(0, GMAC_CTRL), GMC_RST_CLR);
501 sky2_write8(hw, SK_REG(1, GMAC_CTRL), GMC_RST_SET);
502 sky2_write8(hw, SK_REG(1, GMAC_CTRL), GMC_RST_CLR);
503 } while (gm_phy_read(hw, 1, PHY_MARV_ID0) != PHY_MARV_ID0_VAL ||
504 gm_phy_read(hw, 1, PHY_MARV_ID1) != PHY_MARV_ID1_Y2 ||
505 gm_phy_read(hw, 1, PHY_MARV_INT_MASK) != 0);
508 if (sky2->autoneg == AUTONEG_DISABLE) {
509 reg = gma_read16(hw, port, GM_GP_CTRL);
510 reg |= GM_GPCR_AU_ALL_DIS;
511 gma_write16(hw, port, GM_GP_CTRL, reg);
512 gma_read16(hw, port, GM_GP_CTRL);
514 switch (sky2->speed) {
516 reg |= GM_GPCR_SPEED_1000;
519 reg |= GM_GPCR_SPEED_100;
522 if (sky2->duplex == DUPLEX_FULL)
523 reg |= GM_GPCR_DUP_FULL;
525 reg = GM_GPCR_SPEED_1000 | GM_GPCR_SPEED_100 | GM_GPCR_DUP_FULL;
527 if (!sky2->tx_pause && !sky2->rx_pause) {
528 sky2_write32(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
530 GM_GPCR_FC_TX_DIS | GM_GPCR_FC_RX_DIS | GM_GPCR_AU_FCT_DIS;
531 } else if (sky2->tx_pause && !sky2->rx_pause) {
532 /* disable Rx flow-control */
533 reg |= GM_GPCR_FC_RX_DIS | GM_GPCR_AU_FCT_DIS;
536 gma_write16(hw, port, GM_GP_CTRL, reg);
538 sky2_read16(hw, SK_REG(port, GMAC_IRQ_SRC));
540 spin_lock_bh(&hw->phy_lock);
541 sky2_phy_init(hw, port);
542 spin_unlock_bh(&hw->phy_lock);
545 reg = gma_read16(hw, port, GM_PHY_ADDR);
546 gma_write16(hw, port, GM_PHY_ADDR, reg | GM_PAR_MIB_CLR);
548 for (i = 0; i < GM_MIB_CNT_SIZE; i++)
549 gma_read16(hw, port, GM_MIB_CNT_BASE + 8 * i);
550 gma_write16(hw, port, GM_PHY_ADDR, reg);
552 /* transmit control */
553 gma_write16(hw, port, GM_TX_CTRL, TX_COL_THR(TX_COL_DEF));
555 /* receive control reg: unicast + multicast + no FCS */
556 gma_write16(hw, port, GM_RX_CTRL,
557 GM_RXCR_UCF_ENA | GM_RXCR_CRC_DIS | GM_RXCR_MCF_ENA);
559 /* transmit flow control */
560 gma_write16(hw, port, GM_TX_FLOW_CTRL, 0xffff);
562 /* transmit parameter */
563 gma_write16(hw, port, GM_TX_PARAM,
564 TX_JAM_LEN_VAL(TX_JAM_LEN_DEF) |
565 TX_JAM_IPG_VAL(TX_JAM_IPG_DEF) |
566 TX_IPG_JAM_DATA(TX_IPG_JAM_DEF) |
567 TX_BACK_OFF_LIM(TX_BOF_LIM_DEF));
569 /* serial mode register */
570 reg = DATA_BLIND_VAL(DATA_BLIND_DEF) |
571 GM_SMOD_VLAN_ENA | IPG_DATA_VAL(IPG_DATA_DEF);
573 if (hw->dev[port]->mtu > ETH_DATA_LEN)
574 reg |= GM_SMOD_JUMBO_ENA;
576 gma_write16(hw, port, GM_SERIAL_MODE, reg);
578 /* virtual address for data */
579 gma_set_addr(hw, port, GM_SRC_ADDR_2L, addr);
581 /* physical address: used for pause frames */
582 gma_set_addr(hw, port, GM_SRC_ADDR_1L, addr);
584 /* ignore counter overflows */
585 gma_write16(hw, port, GM_TX_IRQ_MSK, 0);
586 gma_write16(hw, port, GM_RX_IRQ_MSK, 0);
587 gma_write16(hw, port, GM_TR_IRQ_MSK, 0);
589 /* Configure Rx MAC FIFO */
590 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_CLR);
591 sky2_write16(hw, SK_REG(port, RX_GMF_CTRL_T),
594 /* Flush Rx MAC FIFO on any flow control or error */
595 sky2_write16(hw, SK_REG(port, RX_GMF_FL_MSK), GMR_FS_ANY_ERR);
597 /* Set threshold to 0xa (64 bytes)
598 * ASF disabled so no need to do WA dev #4.30
600 sky2_write16(hw, SK_REG(port, RX_GMF_FL_THR), RX_GMF_FL_THR_DEF);
602 /* Configure Tx MAC FIFO */
603 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_CLR);
604 sky2_write16(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_OPER_ON);
606 if (hw->chip_id == CHIP_ID_YUKON_EC_U) {
607 sky2_write8(hw, SK_REG(port, RX_GMF_LP_THR), 768/8);
608 sky2_write8(hw, SK_REG(port, RX_GMF_UP_THR), 1024/8);
609 if (hw->dev[port]->mtu > ETH_DATA_LEN) {
610 /* set Tx GMAC FIFO Almost Empty Threshold */
611 sky2_write32(hw, SK_REG(port, TX_GMF_AE_THR), 0x180);
612 /* Disable Store & Forward mode for TX */
613 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T), TX_STFW_DIS);
619 static void sky2_ramset(struct sky2_hw *hw, u16 q, u32 start, size_t len)
625 end = start + len - 1;
627 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_RST_CLR);
628 sky2_write32(hw, RB_ADDR(q, RB_START), start);
629 sky2_write32(hw, RB_ADDR(q, RB_END), end);
630 sky2_write32(hw, RB_ADDR(q, RB_WP), start);
631 sky2_write32(hw, RB_ADDR(q, RB_RP), start);
633 if (q == Q_R1 || q == Q_R2) {
639 /* Set thresholds on receive queue's */
640 sky2_write32(hw, RB_ADDR(q, RB_RX_UTPP), rxup);
641 sky2_write32(hw, RB_ADDR(q, RB_RX_LTPP), rxlo);
643 /* Enable store & forward on Tx queue's because
644 * Tx FIFO is only 1K on Yukon
646 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_STFWD);
649 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_OP_MD);
650 sky2_read8(hw, RB_ADDR(q, RB_CTRL));
653 /* Setup Bus Memory Interface */
654 static void sky2_qset(struct sky2_hw *hw, u16 q, u32 wm)
656 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_CLR_RESET);
657 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_OPER_INIT);
658 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_FIFO_OP_ON);
659 sky2_write32(hw, Q_ADDR(q, Q_WM), wm);
662 /* Setup prefetch unit registers. This is the interface between
663 * hardware and driver list elements
665 static inline void sky2_prefetch_init(struct sky2_hw *hw, u32 qaddr,
668 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_RST_SET);
669 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_RST_CLR);
670 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_ADDR_HI), addr >> 32);
671 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_ADDR_LO), (u32) addr);
672 sky2_write16(hw, Y2_QADDR(qaddr, PREF_UNIT_LAST_IDX), last);
673 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_OP_ON);
675 sky2_read32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL));
678 static inline struct sky2_tx_le *get_tx_le(struct sky2_port *sky2)
680 struct sky2_tx_le *le = sky2->tx_le + sky2->tx_prod;
682 sky2->tx_prod = (sky2->tx_prod + 1) % TX_RING_SIZE;
687 * This is a workaround code taken from SysKonnect sk98lin driver
688 * to deal with chip bug on Yukon EC rev 0 in the wraparound case.
690 static inline void sky2_put_idx(struct sky2_hw *hw, unsigned q,
691 u16 idx, u16 *last, u16 size)
693 if (is_ec_a1(hw) && idx < *last) {
694 u16 hwget = sky2_read16(hw, Y2_QADDR(q, PREF_UNIT_GET_IDX));
697 /* Start prefetching again */
698 sky2_write8(hw, Y2_QADDR(q, PREF_UNIT_FIFO_WM), 0xe0);
702 if (hwget == size - 1) {
703 /* set watermark to one list element */
704 sky2_write8(hw, Y2_QADDR(q, PREF_UNIT_FIFO_WM), 8);
706 /* set put index to first list element */
707 sky2_write16(hw, Y2_QADDR(q, PREF_UNIT_PUT_IDX), 0);
708 } else /* have hardware go to end of list */
709 sky2_write16(hw, Y2_QADDR(q, PREF_UNIT_PUT_IDX),
713 sky2_write16(hw, Y2_QADDR(q, PREF_UNIT_PUT_IDX), idx);
719 static inline struct sky2_rx_le *sky2_next_rx(struct sky2_port *sky2)
721 struct sky2_rx_le *le = sky2->rx_le + sky2->rx_put;
722 sky2->rx_put = (sky2->rx_put + 1) % RX_LE_SIZE;
726 /* Return high part of DMA address (could be 32 or 64 bit) */
727 static inline u32 high32(dma_addr_t a)
729 return (a >> 16) >> 16;
732 /* Build description to hardware about buffer */
733 static inline void sky2_rx_add(struct sky2_port *sky2, struct ring_info *re)
735 struct sky2_rx_le *le;
736 u32 hi = high32(re->mapaddr);
738 re->idx = sky2->rx_put;
739 if (sky2->rx_addr64 != hi) {
740 le = sky2_next_rx(sky2);
741 le->addr = cpu_to_le32(hi);
743 le->opcode = OP_ADDR64 | HW_OWNER;
744 sky2->rx_addr64 = high32(re->mapaddr + re->maplen);
747 le = sky2_next_rx(sky2);
748 le->addr = cpu_to_le32((u32) re->mapaddr);
749 le->length = cpu_to_le16(re->maplen);
751 le->opcode = OP_PACKET | HW_OWNER;
755 /* Tell chip where to start receive checksum.
756 * Actually has two checksums, but set both same to avoid possible byte
759 static void rx_set_checksum(struct sky2_port *sky2)
761 struct sky2_rx_le *le;
763 le = sky2_next_rx(sky2);
764 le->addr = (ETH_HLEN << 16) | ETH_HLEN;
766 le->opcode = OP_TCPSTART | HW_OWNER;
768 sky2_write32(sky2->hw,
769 Q_ADDR(rxqaddr[sky2->port], Q_CSR),
770 sky2->rx_csum ? BMU_ENA_RX_CHKSUM : BMU_DIS_RX_CHKSUM);
775 * The RX Stop command will not work for Yukon-2 if the BMU does not
776 * reach the end of packet and since we can't make sure that we have
777 * incoming data, we must reset the BMU while it is not doing a DMA
778 * transfer. Since it is possible that the RX path is still active,
779 * the RX RAM buffer will be stopped first, so any possible incoming
780 * data will not trigger a DMA. After the RAM buffer is stopped, the
781 * BMU is polled until any DMA in progress is ended and only then it
784 static void sky2_rx_stop(struct sky2_port *sky2)
786 struct sky2_hw *hw = sky2->hw;
787 unsigned rxq = rxqaddr[sky2->port];
790 /* disable the RAM Buffer receive queue */
791 sky2_write8(hw, RB_ADDR(rxq, RB_CTRL), RB_DIS_OP_MD);
793 for (i = 0; i < 0xffff; i++)
794 if (sky2_read8(hw, RB_ADDR(rxq, Q_RSL))
795 == sky2_read8(hw, RB_ADDR(rxq, Q_RL)))
798 printk(KERN_WARNING PFX "%s: receiver stop failed\n",
801 sky2_write32(hw, Q_ADDR(rxq, Q_CSR), BMU_RST_SET | BMU_FIFO_RST);
803 /* reset the Rx prefetch unit */
804 sky2_write32(hw, Y2_QADDR(rxq, PREF_UNIT_CTRL), PREF_UNIT_RST_SET);
807 /* Clean out receive buffer area, assumes receiver hardware stopped */
808 static void sky2_rx_clean(struct sky2_port *sky2)
812 memset(sky2->rx_le, 0, RX_LE_BYTES);
813 for (i = 0; i < sky2->rx_pending; i++) {
814 struct ring_info *re = sky2->rx_ring + i;
817 pci_unmap_single(sky2->hw->pdev,
818 re->mapaddr, re->maplen,
826 /* Basic MII support */
827 static int sky2_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
829 struct mii_ioctl_data *data = if_mii(ifr);
830 struct sky2_port *sky2 = netdev_priv(dev);
831 struct sky2_hw *hw = sky2->hw;
832 int err = -EOPNOTSUPP;
834 if (!netif_running(dev))
835 return -ENODEV; /* Phy still in reset */
839 data->phy_id = PHY_ADDR_MARV;
844 spin_lock_bh(&hw->phy_lock);
845 err = __gm_phy_read(hw, sky2->port, data->reg_num & 0x1f, &val);
846 spin_unlock_bh(&hw->phy_lock);
852 if (!capable(CAP_NET_ADMIN))
855 spin_lock_bh(&hw->phy_lock);
856 err = gm_phy_write(hw, sky2->port, data->reg_num & 0x1f,
858 spin_unlock_bh(&hw->phy_lock);
864 #ifdef SKY2_VLAN_TAG_USED
865 static void sky2_vlan_rx_register(struct net_device *dev, struct vlan_group *grp)
867 struct sky2_port *sky2 = netdev_priv(dev);
868 struct sky2_hw *hw = sky2->hw;
869 u16 port = sky2->port;
872 spin_lock_irqsave(&sky2->tx_lock, flags);
874 sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T), RX_VLAN_STRIP_ON);
875 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T), TX_VLAN_TAG_ON);
878 spin_unlock_irqrestore(&sky2->tx_lock, flags);
881 static void sky2_vlan_rx_kill_vid(struct net_device *dev, unsigned short vid)
883 struct sky2_port *sky2 = netdev_priv(dev);
884 struct sky2_hw *hw = sky2->hw;
885 u16 port = sky2->port;
888 spin_lock_irqsave(&sky2->tx_lock, flags);
890 sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T), RX_VLAN_STRIP_OFF);
891 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T), TX_VLAN_TAG_OFF);
893 sky2->vlgrp->vlan_devices[vid] = NULL;
895 spin_unlock_irqrestore(&sky2->tx_lock, flags);
899 #define roundup(x, y) ((((x)+((y)-1))/(y))*(y))
900 static inline unsigned rx_size(const struct sky2_port *sky2)
902 return roundup(sky2->netdev->mtu + ETH_HLEN + 4, 8);
906 * Allocate and setup receiver buffer pool.
907 * In case of 64 bit dma, there are 2X as many list elements
908 * available as ring entries
909 * and need to reserve one list element so we don't wrap around.
911 * It appears the hardware has a bug in the FIFO logic that
912 * cause it to hang if the FIFO gets overrun and the receive buffer
913 * is not aligned. This means we can't use skb_reserve to align
916 static int sky2_rx_start(struct sky2_port *sky2)
918 struct sky2_hw *hw = sky2->hw;
919 unsigned size = rx_size(sky2);
920 unsigned rxq = rxqaddr[sky2->port];
923 sky2->rx_put = sky2->rx_next = 0;
924 sky2_qset(hw, rxq, is_pciex(hw) ? 0x80 : 0x600);
925 sky2_prefetch_init(hw, rxq, sky2->rx_le_map, RX_LE_SIZE - 1);
927 rx_set_checksum(sky2);
928 for (i = 0; i < sky2->rx_pending; i++) {
929 struct ring_info *re = sky2->rx_ring + i;
931 re->skb = dev_alloc_skb(size);
935 re->mapaddr = pci_map_single(hw->pdev, re->skb->data,
936 size, PCI_DMA_FROMDEVICE);
938 sky2_rx_add(sky2, re);
941 /* Tell chip about available buffers */
942 sky2_write16(hw, Y2_QADDR(rxq, PREF_UNIT_PUT_IDX), sky2->rx_put);
943 sky2->rx_last_put = sky2_read16(hw, Y2_QADDR(rxq, PREF_UNIT_PUT_IDX));
950 /* Bring up network interface. */
951 static int sky2_up(struct net_device *dev)
953 struct sky2_port *sky2 = netdev_priv(dev);
954 struct sky2_hw *hw = sky2->hw;
955 unsigned port = sky2->port;
956 u32 ramsize, rxspace;
959 if (netif_msg_ifup(sky2))
960 printk(KERN_INFO PFX "%s: enabling interface\n", dev->name);
962 /* must be power of 2 */
963 sky2->tx_le = pci_alloc_consistent(hw->pdev,
965 sizeof(struct sky2_tx_le),
970 sky2->tx_ring = kzalloc(TX_RING_SIZE * sizeof(struct ring_info),
974 sky2->tx_prod = sky2->tx_cons = 0;
976 sky2->rx_le = pci_alloc_consistent(hw->pdev, RX_LE_BYTES,
980 memset(sky2->rx_le, 0, RX_LE_BYTES);
982 sky2->rx_ring = kzalloc(sky2->rx_pending * sizeof(struct ring_info),
987 sky2_mac_init(hw, port);
989 /* Configure RAM buffers */
990 if (hw->chip_id == CHIP_ID_YUKON_FE ||
991 (hw->chip_id == CHIP_ID_YUKON_EC && hw->chip_rev == 2))
994 u8 e0 = sky2_read8(hw, B2_E_0);
995 ramsize = (e0 == 0) ? (128 * 1024) : (e0 * 4096);
999 rxspace = (2 * ramsize) / 3;
1000 sky2_ramset(hw, rxqaddr[port], 0, rxspace);
1001 sky2_ramset(hw, txqaddr[port], rxspace, ramsize - rxspace);
1003 /* Make sure SyncQ is disabled */
1004 sky2_write8(hw, RB_ADDR(port == 0 ? Q_XS1 : Q_XS2, RB_CTRL),
1007 sky2_qset(hw, txqaddr[port], 0x600);
1008 if (hw->chip_id == CHIP_ID_YUKON_EC_U)
1009 sky2_write16(hw, Q_ADDR(txqaddr[port], Q_AL), 0x1a0);
1012 sky2_prefetch_init(hw, txqaddr[port], sky2->tx_le_map,
1015 err = sky2_rx_start(sky2);
1019 /* Enable interrupts from phy/mac for port */
1020 hw->intr_mask |= (port == 0) ? Y2_IS_PORT_1 : Y2_IS_PORT_2;
1021 sky2_write32(hw, B0_IMSK, hw->intr_mask);
1026 pci_free_consistent(hw->pdev, RX_LE_BYTES,
1027 sky2->rx_le, sky2->rx_le_map);
1029 pci_free_consistent(hw->pdev,
1030 TX_RING_SIZE * sizeof(struct sky2_tx_le),
1031 sky2->tx_le, sky2->tx_le_map);
1033 kfree(sky2->tx_ring);
1035 kfree(sky2->rx_ring);
1040 /* Modular subtraction in ring */
1041 static inline int tx_dist(unsigned tail, unsigned head)
1043 return (head >= tail ? head : head + TX_RING_SIZE) - tail;
1046 /* Number of list elements available for next tx */
1047 static inline int tx_avail(const struct sky2_port *sky2)
1049 return sky2->tx_pending - tx_dist(sky2->tx_cons, sky2->tx_prod);
1052 /* Estimate of number of transmit list elements required */
1053 static inline unsigned tx_le_req(const struct sk_buff *skb)
1057 count = sizeof(dma_addr_t) / sizeof(u32);
1058 count += skb_shinfo(skb)->nr_frags * count;
1060 if (skb_shinfo(skb)->tso_size)
1070 * Put one packet in ring for transmit.
1071 * A single packet can generate multiple list elements, and
1072 * the number of ring elements will probably be less than the number
1073 * of list elements used.
1075 static int sky2_xmit_frame(struct sk_buff *skb, struct net_device *dev)
1077 struct sky2_port *sky2 = netdev_priv(dev);
1078 struct sky2_hw *hw = sky2->hw;
1079 struct sky2_tx_le *le = NULL;
1080 struct ring_info *re;
1081 unsigned long flags;
1088 local_irq_save(flags);
1089 if (!spin_trylock(&sky2->tx_lock)) {
1090 local_irq_restore(flags);
1091 return NETDEV_TX_LOCKED;
1094 if (unlikely(tx_avail(sky2) < tx_le_req(skb))) {
1095 netif_stop_queue(dev);
1096 spin_unlock_irqrestore(&sky2->tx_lock, flags);
1098 printk(KERN_WARNING PFX "%s: ring full when queue awake!\n",
1100 return NETDEV_TX_BUSY;
1103 if (unlikely(netif_msg_tx_queued(sky2)))
1104 printk(KERN_DEBUG "%s: tx queued, slot %u, len %d\n",
1105 dev->name, sky2->tx_prod, skb->len);
1107 len = skb_headlen(skb);
1108 mapping = pci_map_single(hw->pdev, skb->data, len, PCI_DMA_TODEVICE);
1109 addr64 = high32(mapping);
1111 re = sky2->tx_ring + sky2->tx_prod;
1113 /* Send high bits if changed or crosses boundary */
1114 if (addr64 != sky2->tx_addr64 || high32(mapping + len) != sky2->tx_addr64) {
1115 le = get_tx_le(sky2);
1116 le->tx.addr = cpu_to_le32(addr64);
1118 le->opcode = OP_ADDR64 | HW_OWNER;
1119 sky2->tx_addr64 = high32(mapping + len);
1122 /* Check for TCP Segmentation Offload */
1123 mss = skb_shinfo(skb)->tso_size;
1125 /* just drop the packet if non-linear expansion fails */
1126 if (skb_header_cloned(skb) &&
1127 pskb_expand_head(skb, 0, 0, GFP_ATOMIC)) {
1128 dev_kfree_skb_any(skb);
1132 mss += ((skb->h.th->doff - 5) * 4); /* TCP options */
1133 mss += (skb->nh.iph->ihl * 4) + sizeof(struct tcphdr);
1137 if (mss != sky2->tx_last_mss) {
1138 le = get_tx_le(sky2);
1139 le->tx.tso.size = cpu_to_le16(mss);
1140 le->tx.tso.rsvd = 0;
1141 le->opcode = OP_LRGLEN | HW_OWNER;
1143 sky2->tx_last_mss = mss;
1147 #ifdef SKY2_VLAN_TAG_USED
1148 /* Add VLAN tag, can piggyback on LRGLEN or ADDR64 */
1149 if (sky2->vlgrp && vlan_tx_tag_present(skb)) {
1151 le = get_tx_le(sky2);
1153 le->opcode = OP_VLAN|HW_OWNER;
1156 le->opcode |= OP_VLAN;
1157 le->length = cpu_to_be16(vlan_tx_tag_get(skb));
1162 /* Handle TCP checksum offload */
1163 if (skb->ip_summed == CHECKSUM_HW) {
1164 u16 hdr = skb->h.raw - skb->data;
1165 u16 offset = hdr + skb->csum;
1167 ctrl = CALSUM | WR_SUM | INIT_SUM | LOCK_SUM;
1168 if (skb->nh.iph->protocol == IPPROTO_UDP)
1171 le = get_tx_le(sky2);
1172 le->tx.csum.start = cpu_to_le16(hdr);
1173 le->tx.csum.offset = cpu_to_le16(offset);
1174 le->length = 0; /* initial checksum value */
1175 le->ctrl = 1; /* one packet */
1176 le->opcode = OP_TCPLISW | HW_OWNER;
1179 le = get_tx_le(sky2);
1180 le->tx.addr = cpu_to_le32((u32) mapping);
1181 le->length = cpu_to_le16(len);
1183 le->opcode = mss ? (OP_LARGESEND | HW_OWNER) : (OP_PACKET | HW_OWNER);
1185 /* Record the transmit mapping info */
1187 re->mapaddr = mapping;
1190 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
1191 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
1192 struct ring_info *fre;
1194 mapping = pci_map_page(hw->pdev, frag->page, frag->page_offset,
1195 frag->size, PCI_DMA_TODEVICE);
1196 addr64 = (mapping >> 16) >> 16;
1197 if (addr64 != sky2->tx_addr64) {
1198 le = get_tx_le(sky2);
1199 le->tx.addr = cpu_to_le32(addr64);
1201 le->opcode = OP_ADDR64 | HW_OWNER;
1202 sky2->tx_addr64 = addr64;
1205 le = get_tx_le(sky2);
1206 le->tx.addr = cpu_to_le32((u32) mapping);
1207 le->length = cpu_to_le16(frag->size);
1209 le->opcode = OP_BUFFER | HW_OWNER;
1212 + ((re - sky2->tx_ring) + i + 1) % TX_RING_SIZE;
1214 fre->mapaddr = mapping;
1215 fre->maplen = frag->size;
1217 re->idx = sky2->tx_prod;
1220 sky2_put_idx(hw, txqaddr[sky2->port], sky2->tx_prod,
1221 &sky2->tx_last_put, TX_RING_SIZE);
1223 if (tx_avail(sky2) < MAX_SKB_TX_LE + 1)
1224 netif_stop_queue(dev);
1228 spin_unlock_irqrestore(&sky2->tx_lock, flags);
1230 dev->trans_start = jiffies;
1231 return NETDEV_TX_OK;
1235 * Free ring elements from starting at tx_cons until "done"
1237 * NB: the hardware will tell us about partial completion of multi-part
1238 * buffers; these are deferred until completion.
1240 static void sky2_tx_complete(struct sky2_port *sky2, u16 done)
1242 struct net_device *dev = sky2->netdev;
1245 if (unlikely(netif_msg_tx_done(sky2)))
1246 printk(KERN_DEBUG "%s: tx done, up to %u\n",
1249 spin_lock(&sky2->tx_lock);
1251 while (sky2->tx_cons != done) {
1252 struct ring_info *re = sky2->tx_ring + sky2->tx_cons;
1253 struct sk_buff *skb;
1255 /* Check for partial status */
1256 if (tx_dist(sky2->tx_cons, done)
1257 < tx_dist(sky2->tx_cons, re->idx))
1261 pci_unmap_single(sky2->hw->pdev,
1262 re->mapaddr, re->maplen, PCI_DMA_TODEVICE);
1264 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
1265 struct ring_info *fre;
1267 sky2->tx_ring + (sky2->tx_cons + i +
1269 pci_unmap_page(sky2->hw->pdev, fre->mapaddr,
1270 fre->maplen, PCI_DMA_TODEVICE);
1273 dev_kfree_skb_any(skb);
1275 sky2->tx_cons = re->idx;
1279 if (netif_queue_stopped(dev) && tx_avail(sky2) > MAX_SKB_TX_LE)
1280 netif_wake_queue(dev);
1281 spin_unlock(&sky2->tx_lock);
1284 /* Cleanup all untransmitted buffers, assume transmitter not running */
1285 static inline void sky2_tx_clean(struct sky2_port *sky2)
1287 sky2_tx_complete(sky2, sky2->tx_prod);
1290 /* Network shutdown */
1291 static int sky2_down(struct net_device *dev)
1293 struct sky2_port *sky2 = netdev_priv(dev);
1294 struct sky2_hw *hw = sky2->hw;
1295 unsigned port = sky2->port;
1298 if (netif_msg_ifdown(sky2))
1299 printk(KERN_INFO PFX "%s: disabling interface\n", dev->name);
1301 /* Stop more packets from being queued */
1302 netif_stop_queue(dev);
1304 /* Disable port IRQ */
1305 local_irq_disable();
1306 hw->intr_mask &= ~((sky2->port == 0) ? Y2_IS_IRQ_PHY1 : Y2_IS_IRQ_PHY2);
1307 sky2_write32(hw, B0_IMSK, hw->intr_mask);
1311 sky2_phy_reset(hw, port);
1313 /* Stop transmitter */
1314 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), BMU_STOP);
1315 sky2_read32(hw, Q_ADDR(txqaddr[port], Q_CSR));
1317 sky2_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL),
1318 RB_RST_SET | RB_DIS_OP_MD);
1320 ctrl = gma_read16(hw, port, GM_GP_CTRL);
1321 ctrl &= ~(GM_GPCR_TX_ENA | GM_GPCR_RX_ENA);
1322 gma_write16(hw, port, GM_GP_CTRL, ctrl);
1324 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET);
1326 /* Workaround shared GMAC reset */
1327 if (!(hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0
1328 && port == 0 && hw->dev[1] && netif_running(hw->dev[1])))
1329 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_SET);
1331 /* Disable Force Sync bit and Enable Alloc bit */
1332 sky2_write8(hw, SK_REG(port, TXA_CTRL),
1333 TXA_DIS_FSYNC | TXA_DIS_ALLOC | TXA_STOP_RC);
1335 /* Stop Interval Timer and Limit Counter of Tx Arbiter */
1336 sky2_write32(hw, SK_REG(port, TXA_ITI_INI), 0L);
1337 sky2_write32(hw, SK_REG(port, TXA_LIM_INI), 0L);
1339 /* Reset the PCI FIFO of the async Tx queue */
1340 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR),
1341 BMU_RST_SET | BMU_FIFO_RST);
1343 /* Reset the Tx prefetch units */
1344 sky2_write32(hw, Y2_QADDR(txqaddr[port], PREF_UNIT_CTRL),
1347 sky2_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL), RB_RST_SET);
1351 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_SET);
1352 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_SET);
1354 /* turn off LED's */
1355 sky2_write16(hw, B0_Y2LED, LED_STAT_OFF);
1357 synchronize_irq(hw->pdev->irq);
1359 sky2_tx_clean(sky2);
1360 sky2_rx_clean(sky2);
1362 pci_free_consistent(hw->pdev, RX_LE_BYTES,
1363 sky2->rx_le, sky2->rx_le_map);
1364 kfree(sky2->rx_ring);
1366 pci_free_consistent(hw->pdev,
1367 TX_RING_SIZE * sizeof(struct sky2_tx_le),
1368 sky2->tx_le, sky2->tx_le_map);
1369 kfree(sky2->tx_ring);
1374 static u16 sky2_phy_speed(const struct sky2_hw *hw, u16 aux)
1379 if (hw->chip_id == CHIP_ID_YUKON_FE)
1380 return (aux & PHY_M_PS_SPEED_100) ? SPEED_100 : SPEED_10;
1382 switch (aux & PHY_M_PS_SPEED_MSK) {
1383 case PHY_M_PS_SPEED_1000:
1385 case PHY_M_PS_SPEED_100:
1392 static void sky2_link_up(struct sky2_port *sky2)
1394 struct sky2_hw *hw = sky2->hw;
1395 unsigned port = sky2->port;
1398 /* Enable Transmit FIFO Underrun */
1399 sky2_write8(hw, SK_REG(port, GMAC_IRQ_MSK), GMAC_DEF_MSK);
1401 reg = gma_read16(hw, port, GM_GP_CTRL);
1402 if (sky2->duplex == DUPLEX_FULL || sky2->autoneg == AUTONEG_ENABLE)
1403 reg |= GM_GPCR_DUP_FULL;
1406 reg |= GM_GPCR_RX_ENA | GM_GPCR_TX_ENA;
1407 gma_write16(hw, port, GM_GP_CTRL, reg);
1408 gma_read16(hw, port, GM_GP_CTRL);
1410 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_DEF_MSK);
1412 netif_carrier_on(sky2->netdev);
1413 netif_wake_queue(sky2->netdev);
1415 /* Turn on link LED */
1416 sky2_write8(hw, SK_REG(port, LNK_LED_REG),
1417 LINKLED_ON | LINKLED_BLINK_OFF | LINKLED_LINKSYNC_OFF);
1419 if (hw->chip_id == CHIP_ID_YUKON_XL) {
1420 u16 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
1422 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
1423 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, PHY_M_LEDC_LOS_CTRL(1) | /* LINK/ACT */
1424 PHY_M_LEDC_INIT_CTRL(sky2->speed ==
1426 PHY_M_LEDC_STA1_CTRL(sky2->speed ==
1427 SPEED_100 ? 7 : 0) |
1428 PHY_M_LEDC_STA0_CTRL(sky2->speed ==
1429 SPEED_1000 ? 7 : 0));
1430 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
1433 if (netif_msg_link(sky2))
1434 printk(KERN_INFO PFX
1435 "%s: Link is up at %d Mbps, %s duplex, flow control %s\n",
1436 sky2->netdev->name, sky2->speed,
1437 sky2->duplex == DUPLEX_FULL ? "full" : "half",
1438 (sky2->tx_pause && sky2->rx_pause) ? "both" :
1439 sky2->tx_pause ? "tx" : sky2->rx_pause ? "rx" : "none");
1442 static void sky2_link_down(struct sky2_port *sky2)
1444 struct sky2_hw *hw = sky2->hw;
1445 unsigned port = sky2->port;
1448 gm_phy_write(hw, port, PHY_MARV_INT_MASK, 0);
1450 reg = gma_read16(hw, port, GM_GP_CTRL);
1451 reg &= ~(GM_GPCR_RX_ENA | GM_GPCR_TX_ENA);
1452 gma_write16(hw, port, GM_GP_CTRL, reg);
1453 gma_read16(hw, port, GM_GP_CTRL); /* PCI post */
1455 if (sky2->rx_pause && !sky2->tx_pause) {
1456 /* restore Asymmetric Pause bit */
1457 gm_phy_write(hw, port, PHY_MARV_AUNE_ADV,
1458 gm_phy_read(hw, port, PHY_MARV_AUNE_ADV)
1462 sky2_phy_reset(hw, port);
1464 netif_carrier_off(sky2->netdev);
1465 netif_stop_queue(sky2->netdev);
1467 /* Turn on link LED */
1468 sky2_write8(hw, SK_REG(port, LNK_LED_REG), LINKLED_OFF);
1470 if (netif_msg_link(sky2))
1471 printk(KERN_INFO PFX "%s: Link is down.\n", sky2->netdev->name);
1472 sky2_phy_init(hw, port);
1475 static int sky2_autoneg_done(struct sky2_port *sky2, u16 aux)
1477 struct sky2_hw *hw = sky2->hw;
1478 unsigned port = sky2->port;
1481 lpa = gm_phy_read(hw, port, PHY_MARV_AUNE_LP);
1483 if (lpa & PHY_M_AN_RF) {
1484 printk(KERN_ERR PFX "%s: remote fault", sky2->netdev->name);
1488 if (hw->chip_id != CHIP_ID_YUKON_FE &&
1489 gm_phy_read(hw, port, PHY_MARV_1000T_STAT) & PHY_B_1000S_MSF) {
1490 printk(KERN_ERR PFX "%s: master/slave fault",
1491 sky2->netdev->name);
1495 if (!(aux & PHY_M_PS_SPDUP_RES)) {
1496 printk(KERN_ERR PFX "%s: speed/duplex mismatch",
1497 sky2->netdev->name);
1501 sky2->duplex = (aux & PHY_M_PS_FULL_DUP) ? DUPLEX_FULL : DUPLEX_HALF;
1503 sky2->speed = sky2_phy_speed(hw, aux);
1505 /* Pause bits are offset (9..8) */
1506 if (hw->chip_id == CHIP_ID_YUKON_XL)
1509 sky2->rx_pause = (aux & PHY_M_PS_RX_P_EN) != 0;
1510 sky2->tx_pause = (aux & PHY_M_PS_TX_P_EN) != 0;
1512 if ((sky2->tx_pause || sky2->rx_pause)
1513 && !(sky2->speed < SPEED_1000 && sky2->duplex == DUPLEX_HALF))
1514 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON);
1516 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
1522 * Interrupt from PHY are handled in tasklet (soft irq)
1523 * because accessing phy registers requires spin wait which might
1524 * cause excess interrupt latency.
1526 static void sky2_phy_task(unsigned long data)
1528 struct sky2_port *sky2 = (struct sky2_port *)data;
1529 struct sky2_hw *hw = sky2->hw;
1530 u16 istatus, phystat;
1532 spin_lock(&hw->phy_lock);
1533 istatus = gm_phy_read(hw, sky2->port, PHY_MARV_INT_STAT);
1534 phystat = gm_phy_read(hw, sky2->port, PHY_MARV_PHY_STAT);
1536 if (netif_msg_intr(sky2))
1537 printk(KERN_INFO PFX "%s: phy interrupt status 0x%x 0x%x\n",
1538 sky2->netdev->name, istatus, phystat);
1540 if (istatus & PHY_M_IS_AN_COMPL) {
1541 if (sky2_autoneg_done(sky2, phystat) == 0)
1546 if (istatus & PHY_M_IS_LSP_CHANGE)
1547 sky2->speed = sky2_phy_speed(hw, phystat);
1549 if (istatus & PHY_M_IS_DUP_CHANGE)
1551 (phystat & PHY_M_PS_FULL_DUP) ? DUPLEX_FULL : DUPLEX_HALF;
1553 if (istatus & PHY_M_IS_LST_CHANGE) {
1554 if (phystat & PHY_M_PS_LINK_UP)
1557 sky2_link_down(sky2);
1560 spin_unlock(&hw->phy_lock);
1562 local_irq_disable();
1563 hw->intr_mask |= (sky2->port == 0) ? Y2_IS_IRQ_PHY1 : Y2_IS_IRQ_PHY2;
1564 sky2_write32(hw, B0_IMSK, hw->intr_mask);
1568 static void sky2_tx_timeout(struct net_device *dev)
1570 struct sky2_port *sky2 = netdev_priv(dev);
1572 if (netif_msg_timer(sky2))
1573 printk(KERN_ERR PFX "%s: tx timeout\n", dev->name);
1575 sky2_write32(sky2->hw, Q_ADDR(txqaddr[sky2->port], Q_CSR), BMU_STOP);
1576 sky2_read32(sky2->hw, Q_ADDR(txqaddr[sky2->port], Q_CSR));
1578 sky2_tx_clean(sky2);
1581 static int sky2_change_mtu(struct net_device *dev, int new_mtu)
1583 struct sky2_port *sky2 = netdev_priv(dev);
1584 struct sky2_hw *hw = sky2->hw;
1588 if (new_mtu < ETH_ZLEN || new_mtu > ETH_JUMBO_MTU)
1591 if (hw->chip_id == CHIP_ID_YUKON_EC_U && new_mtu > ETH_DATA_LEN)
1594 if (!netif_running(dev)) {
1599 sky2_write32(hw, B0_IMSK, 0);
1601 dev->trans_start = jiffies; /* prevent tx timeout */
1602 netif_stop_queue(dev);
1603 netif_poll_disable(hw->dev[0]);
1605 ctl = gma_read16(hw, sky2->port, GM_GP_CTRL);
1606 gma_write16(hw, sky2->port, GM_GP_CTRL, ctl & ~GM_GPCR_RX_ENA);
1608 sky2_rx_clean(sky2);
1611 mode = DATA_BLIND_VAL(DATA_BLIND_DEF) |
1612 GM_SMOD_VLAN_ENA | IPG_DATA_VAL(IPG_DATA_DEF);
1614 if (dev->mtu > ETH_DATA_LEN)
1615 mode |= GM_SMOD_JUMBO_ENA;
1617 gma_write16(hw, sky2->port, GM_SERIAL_MODE, mode);
1619 sky2_write8(hw, RB_ADDR(rxqaddr[sky2->port], RB_CTRL), RB_ENA_OP_MD);
1621 err = sky2_rx_start(sky2);
1622 gma_write16(hw, sky2->port, GM_GP_CTRL, ctl);
1624 netif_poll_disable(hw->dev[0]);
1625 netif_wake_queue(dev);
1626 sky2_write32(hw, B0_IMSK, hw->intr_mask);
1632 * Receive one packet.
1633 * For small packets or errors, just reuse existing skb.
1634 * For larger packets, get new buffer.
1636 static struct sk_buff *sky2_receive(struct sky2_port *sky2,
1637 u16 length, u32 status)
1639 struct ring_info *re = sky2->rx_ring + sky2->rx_next;
1640 struct sk_buff *skb = NULL;
1641 const unsigned int bufsize = rx_size(sky2);
1643 if (unlikely(netif_msg_rx_status(sky2)))
1644 printk(KERN_DEBUG PFX "%s: rx slot %u status 0x%x len %d\n",
1645 sky2->netdev->name, sky2->rx_next, status, length);
1647 sky2->rx_next = (sky2->rx_next + 1) % sky2->rx_pending;
1649 if (status & GMR_FS_ANY_ERR)
1652 if (!(status & GMR_FS_RX_OK))
1655 if (length < RX_COPY_THRESHOLD) {
1656 skb = alloc_skb(length + 2, GFP_ATOMIC);
1660 skb_reserve(skb, 2);
1661 pci_dma_sync_single_for_cpu(sky2->hw->pdev, re->mapaddr,
1662 length, PCI_DMA_FROMDEVICE);
1663 memcpy(skb->data, re->skb->data, length);
1664 skb->ip_summed = re->skb->ip_summed;
1665 skb->csum = re->skb->csum;
1666 pci_dma_sync_single_for_device(sky2->hw->pdev, re->mapaddr,
1667 length, PCI_DMA_FROMDEVICE);
1669 struct sk_buff *nskb;
1671 nskb = dev_alloc_skb(bufsize);
1677 pci_unmap_single(sky2->hw->pdev, re->mapaddr,
1678 re->maplen, PCI_DMA_FROMDEVICE);
1679 prefetch(skb->data);
1681 re->mapaddr = pci_map_single(sky2->hw->pdev, nskb->data,
1682 bufsize, PCI_DMA_FROMDEVICE);
1683 re->maplen = bufsize;
1686 skb_put(skb, length);
1688 re->skb->ip_summed = CHECKSUM_NONE;
1689 sky2_rx_add(sky2, re);
1691 /* Tell receiver about new buffers. */
1692 sky2_put_idx(sky2->hw, rxqaddr[sky2->port], sky2->rx_put,
1693 &sky2->rx_last_put, RX_LE_SIZE);
1698 if (netif_msg_rx_err(sky2))
1699 printk(KERN_INFO PFX "%s: rx error, status 0x%x length %d\n",
1700 sky2->netdev->name, status, length);
1702 if (status & (GMR_FS_LONG_ERR | GMR_FS_UN_SIZE))
1703 sky2->net_stats.rx_length_errors++;
1704 if (status & GMR_FS_FRAGMENT)
1705 sky2->net_stats.rx_frame_errors++;
1706 if (status & GMR_FS_CRC_ERR)
1707 sky2->net_stats.rx_crc_errors++;
1708 if (status & GMR_FS_RX_FF_OV)
1709 sky2->net_stats.rx_fifo_errors++;
1714 /* Transmit ring index in reported status block is encoded as:
1716 * | TXS2 | TXA2 | TXS1 | TXA1
1718 static inline u16 tx_index(u8 port, u32 status, u16 len)
1721 return status & 0xfff;
1723 return ((status >> 24) & 0xff) | (len & 0xf) << 8;
1727 * Both ports share the same status interrupt, therefore there is only
1730 static int sky2_poll(struct net_device *dev0, int *budget)
1732 struct sky2_hw *hw = ((struct sky2_port *) netdev_priv(dev0))->hw;
1733 unsigned int to_do = min(dev0->quota, *budget);
1734 unsigned int work_done = 0;
1737 hwidx = sky2_read16(hw, STAT_PUT_IDX);
1738 BUG_ON(hwidx >= STATUS_RING_SIZE);
1741 while (hwidx != hw->st_idx) {
1742 struct sky2_status_le *le = hw->st_le + hw->st_idx;
1743 struct net_device *dev;
1744 struct sky2_port *sky2;
1745 struct sk_buff *skb;
1750 le = hw->st_le + hw->st_idx;
1751 hw->st_idx = (hw->st_idx + 1) % STATUS_RING_SIZE;
1752 prefetch(hw->st_le + hw->st_idx);
1754 BUG_ON(le->link >= hw->ports || !hw->dev[le->link]);
1756 BUG_ON(le->link >= 2);
1757 dev = hw->dev[le->link];
1758 if (dev == NULL || !netif_running(dev))
1761 sky2 = netdev_priv(dev);
1762 status = le32_to_cpu(le->status);
1763 length = le16_to_cpu(le->length);
1764 op = le->opcode & ~HW_OWNER;
1769 skb = sky2_receive(sky2, length, status);
1774 skb->protocol = eth_type_trans(skb, dev);
1775 dev->last_rx = jiffies;
1777 #ifdef SKY2_VLAN_TAG_USED
1778 if (sky2->vlgrp && (status & GMR_FS_VLAN)) {
1779 vlan_hwaccel_receive_skb(skb,
1781 be16_to_cpu(sky2->rx_tag));
1784 netif_receive_skb(skb);
1786 if (++work_done >= to_do)
1790 #ifdef SKY2_VLAN_TAG_USED
1792 sky2->rx_tag = length;
1796 sky2->rx_tag = length;
1800 skb = sky2->rx_ring[sky2->rx_next].skb;
1801 skb->ip_summed = CHECKSUM_HW;
1802 skb->csum = le16_to_cpu(status);
1806 sky2_tx_complete(sky2,
1807 tx_index(sky2->port, status, length));
1811 if (net_ratelimit())
1812 printk(KERN_WARNING PFX
1813 "unknown status opcode 0x%x\n", op);
1822 if (work_done < to_do) {
1824 * Another chip workaround, need to restart TX timer if status
1825 * LE was handled. WA_DEV_43_418
1828 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_STOP);
1829 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_START);
1832 netif_rx_complete(dev0);
1833 hw->intr_mask |= Y2_IS_STAT_BMU;
1834 sky2_write32(hw, B0_IMSK, hw->intr_mask);
1838 *budget -= work_done;
1839 dev0->quota -= work_done;
1844 static void sky2_hw_error(struct sky2_hw *hw, unsigned port, u32 status)
1846 struct net_device *dev = hw->dev[port];
1848 printk(KERN_INFO PFX "%s: hw error interrupt status 0x%x\n",
1851 if (status & Y2_IS_PAR_RD1) {
1852 printk(KERN_ERR PFX "%s: ram data read parity error\n",
1855 sky2_write16(hw, RAM_BUFFER(port, B3_RI_CTRL), RI_CLR_RD_PERR);
1858 if (status & Y2_IS_PAR_WR1) {
1859 printk(KERN_ERR PFX "%s: ram data write parity error\n",
1862 sky2_write16(hw, RAM_BUFFER(port, B3_RI_CTRL), RI_CLR_WR_PERR);
1865 if (status & Y2_IS_PAR_MAC1) {
1866 printk(KERN_ERR PFX "%s: MAC parity error\n", dev->name);
1867 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_CLI_TX_PE);
1870 if (status & Y2_IS_PAR_RX1) {
1871 printk(KERN_ERR PFX "%s: RX parity error\n", dev->name);
1872 sky2_write32(hw, Q_ADDR(rxqaddr[port], Q_CSR), BMU_CLR_IRQ_PAR);
1875 if (status & Y2_IS_TCP_TXA1) {
1876 printk(KERN_ERR PFX "%s: TCP segmentation error\n", dev->name);
1877 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), BMU_CLR_IRQ_TCP);
1881 static void sky2_hw_intr(struct sky2_hw *hw)
1883 u32 status = sky2_read32(hw, B0_HWE_ISRC);
1885 if (status & Y2_IS_TIST_OV)
1886 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ);
1888 if (status & (Y2_IS_MST_ERR | Y2_IS_IRQ_STAT)) {
1891 pci_read_config_word(hw->pdev, PCI_STATUS, &pci_err);
1892 printk(KERN_ERR PFX "%s: pci hw error (0x%x)\n",
1893 pci_name(hw->pdev), pci_err);
1895 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
1896 pci_write_config_word(hw->pdev, PCI_STATUS,
1897 pci_err | PCI_STATUS_ERROR_BITS);
1898 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
1901 if (status & Y2_IS_PCI_EXP) {
1902 /* PCI-Express uncorrectable Error occurred */
1905 pci_read_config_dword(hw->pdev, PEX_UNC_ERR_STAT, &pex_err);
1907 printk(KERN_ERR PFX "%s: pci express error (0x%x)\n",
1908 pci_name(hw->pdev), pex_err);
1910 /* clear the interrupt */
1911 sky2_write32(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
1912 pci_write_config_dword(hw->pdev, PEX_UNC_ERR_STAT,
1914 sky2_write32(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
1916 if (pex_err & PEX_FATAL_ERRORS) {
1917 u32 hwmsk = sky2_read32(hw, B0_HWE_IMSK);
1918 hwmsk &= ~Y2_IS_PCI_EXP;
1919 sky2_write32(hw, B0_HWE_IMSK, hwmsk);
1923 if (status & Y2_HWE_L1_MASK)
1924 sky2_hw_error(hw, 0, status);
1926 if (status & Y2_HWE_L1_MASK)
1927 sky2_hw_error(hw, 1, status);
1930 static void sky2_mac_intr(struct sky2_hw *hw, unsigned port)
1932 struct net_device *dev = hw->dev[port];
1933 struct sky2_port *sky2 = netdev_priv(dev);
1934 u8 status = sky2_read8(hw, SK_REG(port, GMAC_IRQ_SRC));
1936 if (netif_msg_intr(sky2))
1937 printk(KERN_INFO PFX "%s: mac interrupt status 0x%x\n",
1940 if (status & GM_IS_RX_FF_OR) {
1941 ++sky2->net_stats.rx_fifo_errors;
1942 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_CLI_RX_FO);
1945 if (status & GM_IS_TX_FF_UR) {
1946 ++sky2->net_stats.tx_fifo_errors;
1947 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_CLI_TX_FU);
1951 static void sky2_phy_intr(struct sky2_hw *hw, unsigned port)
1953 struct net_device *dev = hw->dev[port];
1954 struct sky2_port *sky2 = netdev_priv(dev);
1956 hw->intr_mask &= ~(port == 0 ? Y2_IS_IRQ_PHY1 : Y2_IS_IRQ_PHY2);
1957 sky2_write32(hw, B0_IMSK, hw->intr_mask);
1958 tasklet_schedule(&sky2->phy_task);
1961 static irqreturn_t sky2_intr(int irq, void *dev_id, struct pt_regs *regs)
1963 struct sky2_hw *hw = dev_id;
1964 struct net_device *dev0 = hw->dev[0];
1967 status = sky2_read32(hw, B0_Y2_SP_ISRC2);
1968 if (status == 0 || status == ~0)
1971 if (status & Y2_IS_HW_ERR)
1974 /* Do NAPI for Rx and Tx status */
1975 if (status & Y2_IS_STAT_BMU) {
1976 hw->intr_mask &= ~Y2_IS_STAT_BMU;
1977 sky2_write32(hw, B0_IMSK, hw->intr_mask);
1979 if (likely(__netif_rx_schedule_prep(dev0))) {
1980 prefetch(&hw->st_le[hw->st_idx]);
1981 __netif_rx_schedule(dev0);
1985 if (status & Y2_IS_IRQ_PHY1)
1986 sky2_phy_intr(hw, 0);
1988 if (status & Y2_IS_IRQ_PHY2)
1989 sky2_phy_intr(hw, 1);
1991 if (status & Y2_IS_IRQ_MAC1)
1992 sky2_mac_intr(hw, 0);
1994 if (status & Y2_IS_IRQ_MAC2)
1995 sky2_mac_intr(hw, 1);
1997 sky2_write32(hw, B0_Y2_SP_ICR, 2);
1999 sky2_read32(hw, B0_IMSK);
2004 #ifdef CONFIG_NET_POLL_CONTROLLER
2005 static void sky2_netpoll(struct net_device *dev)
2007 struct sky2_port *sky2 = netdev_priv(dev);
2009 sky2_intr(sky2->hw->pdev->irq, sky2->hw, NULL);
2013 /* Chip internal frequency for clock calculations */
2014 static inline u32 sky2_khz(const struct sky2_hw *hw)
2016 switch (hw->chip_id) {
2017 case CHIP_ID_YUKON_EC:
2018 case CHIP_ID_YUKON_EC_U:
2019 return 125000; /* 125 Mhz */
2020 case CHIP_ID_YUKON_FE:
2021 return 100000; /* 100 Mhz */
2022 default: /* YUKON_XL */
2023 return 156000; /* 156 Mhz */
2027 static inline u32 sky2_ms2clk(const struct sky2_hw *hw, u32 ms)
2029 return sky2_khz(hw) * ms;
2032 static inline u32 sky2_us2clk(const struct sky2_hw *hw, u32 us)
2034 return (sky2_khz(hw) * us) / 1000;
2037 static int sky2_reset(struct sky2_hw *hw)
2044 ctst = sky2_read32(hw, B0_CTST);
2046 sky2_write8(hw, B0_CTST, CS_RST_CLR);
2047 hw->chip_id = sky2_read8(hw, B2_CHIP_ID);
2048 if (hw->chip_id < CHIP_ID_YUKON_XL || hw->chip_id > CHIP_ID_YUKON_FE) {
2049 printk(KERN_ERR PFX "%s: unsupported chip type 0x%x\n",
2050 pci_name(hw->pdev), hw->chip_id);
2054 /* ring for status responses */
2055 hw->st_le = pci_alloc_consistent(hw->pdev, STATUS_LE_BYTES,
2061 if (hw->chip_id <= CHIP_ID_YUKON_EC) {
2062 sky2_write8(hw, B28_Y2_ASF_STAT_CMD, Y2_ASF_RESET);
2063 sky2_write16(hw, B0_CTST, Y2_ASF_DISABLE);
2067 sky2_write8(hw, B0_CTST, CS_RST_SET);
2068 sky2_write8(hw, B0_CTST, CS_RST_CLR);
2070 /* clear PCI errors, if any */
2071 pci_read_config_word(hw->pdev, PCI_STATUS, &status);
2072 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
2073 pci_write_config_word(hw->pdev, PCI_STATUS,
2074 status | PCI_STATUS_ERROR_BITS);
2076 sky2_write8(hw, B0_CTST, CS_MRST_CLR);
2078 /* clear any PEX errors */
2081 pci_write_config_dword(hw->pdev, PEX_UNC_ERR_STAT,
2083 pci_read_config_word(hw->pdev, PEX_LNK_STAT, &lstat);
2086 pmd_type = sky2_read8(hw, B2_PMD_TYP);
2087 hw->copper = !(pmd_type == 'L' || pmd_type == 'S');
2090 t8 = sky2_read8(hw, B2_Y2_HW_RES);
2091 if ((t8 & CFG_DUAL_MAC_MSK) == CFG_DUAL_MAC_MSK) {
2092 if (!(sky2_read8(hw, B2_Y2_CLK_GATE) & Y2_STATUS_LNK2_INAC))
2095 hw->chip_rev = (sky2_read8(hw, B2_MAC_CFG) & CFG_CHIP_R_MSK) >> 4;
2097 sky2_set_power_state(hw, PCI_D0);
2099 for (i = 0; i < hw->ports; i++) {
2100 sky2_write8(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_SET);
2101 sky2_write8(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_CLR);
2104 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
2106 /* Clear I2C IRQ noise */
2107 sky2_write32(hw, B2_I2C_IRQ, 1);
2109 /* turn off hardware timer (unused) */
2110 sky2_write8(hw, B2_TI_CTRL, TIM_STOP);
2111 sky2_write8(hw, B2_TI_CTRL, TIM_CLR_IRQ);
2113 sky2_write8(hw, B0_Y2LED, LED_STAT_ON);
2115 /* Turn on descriptor polling (every 75us) */
2116 sky2_write32(hw, B28_DPT_INI, sky2_us2clk(hw, 75));
2117 sky2_write8(hw, B28_DPT_CTRL, DPT_START);
2119 /* Turn off receive timestamp */
2120 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_STOP);
2121 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ);
2123 /* enable the Tx Arbiters */
2124 for (i = 0; i < hw->ports; i++)
2125 sky2_write8(hw, SK_REG(i, TXA_CTRL), TXA_ENA_ARB);
2127 /* Initialize ram interface */
2128 for (i = 0; i < hw->ports; i++) {
2129 sky2_write8(hw, RAM_BUFFER(i, B3_RI_CTRL), RI_RST_CLR);
2131 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_R1), SK_RI_TO_53);
2132 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XA1), SK_RI_TO_53);
2133 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XS1), SK_RI_TO_53);
2134 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_R1), SK_RI_TO_53);
2135 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XA1), SK_RI_TO_53);
2136 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XS1), SK_RI_TO_53);
2137 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_R2), SK_RI_TO_53);
2138 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XA2), SK_RI_TO_53);
2139 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XS2), SK_RI_TO_53);
2140 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_R2), SK_RI_TO_53);
2141 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XA2), SK_RI_TO_53);
2142 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XS2), SK_RI_TO_53);
2148 /* change Max. Read Request Size to 2048 bytes */
2149 pci_read_config_word(hw->pdev, PEX_DEV_CTRL, &pctrl);
2150 pctrl &= ~PEX_DC_MAX_RRS_MSK;
2151 pctrl |= PEX_DC_MAX_RD_RQ_SIZE(4);
2154 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
2155 pci_write_config_word(hw->pdev, PEX_DEV_CTRL, pctrl);
2156 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
2159 sky2_write32(hw, B0_HWE_IMSK, Y2_HWE_ALL_MASK);
2161 spin_lock_bh(&hw->phy_lock);
2162 for (i = 0; i < hw->ports; i++)
2163 sky2_phy_reset(hw, i);
2164 spin_unlock_bh(&hw->phy_lock);
2166 memset(hw->st_le, 0, STATUS_LE_BYTES);
2169 sky2_write32(hw, STAT_CTRL, SC_STAT_RST_SET);
2170 sky2_write32(hw, STAT_CTRL, SC_STAT_RST_CLR);
2172 sky2_write32(hw, STAT_LIST_ADDR_LO, hw->st_dma);
2173 sky2_write32(hw, STAT_LIST_ADDR_HI, (u64) hw->st_dma >> 32);
2175 /* Set the list last index */
2176 sky2_write16(hw, STAT_LAST_IDX, STATUS_RING_SIZE - 1);
2178 sky2_write32(hw, STAT_TX_TIMER_INI, sky2_ms2clk(hw, 10));
2180 /* These status setup values are copied from SysKonnect's driver */
2182 /* WA for dev. #4.3 */
2183 sky2_write16(hw, STAT_TX_IDX_TH, 0xfff); /* Tx Threshold */
2185 /* set Status-FIFO watermark */
2186 sky2_write8(hw, STAT_FIFO_WM, 0x21); /* WA for dev. #4.18 */
2188 /* set Status-FIFO ISR watermark */
2189 sky2_write8(hw, STAT_FIFO_ISR_WM, 0x07); /* WA for dev. #4.18 */
2192 sky2_write16(hw, STAT_TX_IDX_TH, 0x000a);
2194 /* set Status-FIFO watermark */
2195 sky2_write8(hw, STAT_FIFO_WM, 0x10);
2197 /* set Status-FIFO ISR watermark */
2198 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0)
2199 sky2_write8(hw, STAT_FIFO_ISR_WM, 0x10);
2201 else /* WA dev 4.109 */
2202 sky2_write8(hw, STAT_FIFO_ISR_WM, 0x04);
2204 sky2_write32(hw, STAT_ISR_TIMER_INI, 0x0190);
2207 /* enable status unit */
2208 sky2_write32(hw, STAT_CTRL, SC_STAT_OP_ON);
2210 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_START);
2211 sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_START);
2212 sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_START);
2217 static inline u32 sky2_supported_modes(const struct sky2_hw *hw)
2221 modes = SUPPORTED_10baseT_Half
2222 | SUPPORTED_10baseT_Full
2223 | SUPPORTED_100baseT_Half
2224 | SUPPORTED_100baseT_Full
2225 | SUPPORTED_Autoneg | SUPPORTED_TP;
2227 if (hw->chip_id != CHIP_ID_YUKON_FE)
2228 modes |= SUPPORTED_1000baseT_Half
2229 | SUPPORTED_1000baseT_Full;
2231 modes = SUPPORTED_1000baseT_Full | SUPPORTED_FIBRE
2232 | SUPPORTED_Autoneg;
2236 static int sky2_get_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
2238 struct sky2_port *sky2 = netdev_priv(dev);
2239 struct sky2_hw *hw = sky2->hw;
2241 ecmd->transceiver = XCVR_INTERNAL;
2242 ecmd->supported = sky2_supported_modes(hw);
2243 ecmd->phy_address = PHY_ADDR_MARV;
2245 ecmd->supported = SUPPORTED_10baseT_Half
2246 | SUPPORTED_10baseT_Full
2247 | SUPPORTED_100baseT_Half
2248 | SUPPORTED_100baseT_Full
2249 | SUPPORTED_1000baseT_Half
2250 | SUPPORTED_1000baseT_Full
2251 | SUPPORTED_Autoneg | SUPPORTED_TP;
2252 ecmd->port = PORT_TP;
2254 ecmd->port = PORT_FIBRE;
2256 ecmd->advertising = sky2->advertising;
2257 ecmd->autoneg = sky2->autoneg;
2258 ecmd->speed = sky2->speed;
2259 ecmd->duplex = sky2->duplex;
2263 static int sky2_set_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
2265 struct sky2_port *sky2 = netdev_priv(dev);
2266 const struct sky2_hw *hw = sky2->hw;
2267 u32 supported = sky2_supported_modes(hw);
2269 if (ecmd->autoneg == AUTONEG_ENABLE) {
2270 ecmd->advertising = supported;
2276 switch (ecmd->speed) {
2278 if (ecmd->duplex == DUPLEX_FULL)
2279 setting = SUPPORTED_1000baseT_Full;
2280 else if (ecmd->duplex == DUPLEX_HALF)
2281 setting = SUPPORTED_1000baseT_Half;
2286 if (ecmd->duplex == DUPLEX_FULL)
2287 setting = SUPPORTED_100baseT_Full;
2288 else if (ecmd->duplex == DUPLEX_HALF)
2289 setting = SUPPORTED_100baseT_Half;
2295 if (ecmd->duplex == DUPLEX_FULL)
2296 setting = SUPPORTED_10baseT_Full;
2297 else if (ecmd->duplex == DUPLEX_HALF)
2298 setting = SUPPORTED_10baseT_Half;
2306 if ((setting & supported) == 0)
2309 sky2->speed = ecmd->speed;
2310 sky2->duplex = ecmd->duplex;
2313 sky2->autoneg = ecmd->autoneg;
2314 sky2->advertising = ecmd->advertising;
2316 if (netif_running(dev)) {
2324 static void sky2_get_drvinfo(struct net_device *dev,
2325 struct ethtool_drvinfo *info)
2327 struct sky2_port *sky2 = netdev_priv(dev);
2329 strcpy(info->driver, DRV_NAME);
2330 strcpy(info->version, DRV_VERSION);
2331 strcpy(info->fw_version, "N/A");
2332 strcpy(info->bus_info, pci_name(sky2->hw->pdev));
2335 static const struct sky2_stat {
2336 char name[ETH_GSTRING_LEN];
2339 { "tx_bytes", GM_TXO_OK_HI },
2340 { "rx_bytes", GM_RXO_OK_HI },
2341 { "tx_broadcast", GM_TXF_BC_OK },
2342 { "rx_broadcast", GM_RXF_BC_OK },
2343 { "tx_multicast", GM_TXF_MC_OK },
2344 { "rx_multicast", GM_RXF_MC_OK },
2345 { "tx_unicast", GM_TXF_UC_OK },
2346 { "rx_unicast", GM_RXF_UC_OK },
2347 { "tx_mac_pause", GM_TXF_MPAUSE },
2348 { "rx_mac_pause", GM_RXF_MPAUSE },
2349 { "collisions", GM_TXF_SNG_COL },
2350 { "late_collision",GM_TXF_LAT_COL },
2351 { "aborted", GM_TXF_ABO_COL },
2352 { "multi_collisions", GM_TXF_MUL_COL },
2353 { "fifo_underrun", GM_TXE_FIFO_UR },
2354 { "fifo_overflow", GM_RXE_FIFO_OV },
2355 { "rx_toolong", GM_RXF_LNG_ERR },
2356 { "rx_jabber", GM_RXF_JAB_PKT },
2357 { "rx_runt", GM_RXE_FRAG },
2358 { "rx_too_long", GM_RXF_LNG_ERR },
2359 { "rx_fcs_error", GM_RXF_FCS_ERR },
2362 static u32 sky2_get_rx_csum(struct net_device *dev)
2364 struct sky2_port *sky2 = netdev_priv(dev);
2366 return sky2->rx_csum;
2369 static int sky2_set_rx_csum(struct net_device *dev, u32 data)
2371 struct sky2_port *sky2 = netdev_priv(dev);
2373 sky2->rx_csum = data;
2375 sky2_write32(sky2->hw, Q_ADDR(rxqaddr[sky2->port], Q_CSR),
2376 data ? BMU_ENA_RX_CHKSUM : BMU_DIS_RX_CHKSUM);
2381 static u32 sky2_get_msglevel(struct net_device *netdev)
2383 struct sky2_port *sky2 = netdev_priv(netdev);
2384 return sky2->msg_enable;
2387 static int sky2_nway_reset(struct net_device *dev)
2389 struct sky2_port *sky2 = netdev_priv(dev);
2390 struct sky2_hw *hw = sky2->hw;
2392 if (sky2->autoneg != AUTONEG_ENABLE)
2395 netif_stop_queue(dev);
2397 spin_lock_irq(&hw->phy_lock);
2398 sky2_phy_reset(hw, sky2->port);
2399 sky2_phy_init(hw, sky2->port);
2400 spin_unlock_irq(&hw->phy_lock);
2405 static void sky2_phy_stats(struct sky2_port *sky2, u64 * data, unsigned count)
2407 struct sky2_hw *hw = sky2->hw;
2408 unsigned port = sky2->port;
2411 data[0] = (u64) gma_read32(hw, port, GM_TXO_OK_HI) << 32
2412 | (u64) gma_read32(hw, port, GM_TXO_OK_LO);
2413 data[1] = (u64) gma_read32(hw, port, GM_RXO_OK_HI) << 32
2414 | (u64) gma_read32(hw, port, GM_RXO_OK_LO);
2416 for (i = 2; i < count; i++)
2417 data[i] = (u64) gma_read32(hw, port, sky2_stats[i].offset);
2420 static void sky2_set_msglevel(struct net_device *netdev, u32 value)
2422 struct sky2_port *sky2 = netdev_priv(netdev);
2423 sky2->msg_enable = value;
2426 static int sky2_get_stats_count(struct net_device *dev)
2428 return ARRAY_SIZE(sky2_stats);
2431 static void sky2_get_ethtool_stats(struct net_device *dev,
2432 struct ethtool_stats *stats, u64 * data)
2434 struct sky2_port *sky2 = netdev_priv(dev);
2436 sky2_phy_stats(sky2, data, ARRAY_SIZE(sky2_stats));
2439 static void sky2_get_strings(struct net_device *dev, u32 stringset, u8 * data)
2443 switch (stringset) {
2445 for (i = 0; i < ARRAY_SIZE(sky2_stats); i++)
2446 memcpy(data + i * ETH_GSTRING_LEN,
2447 sky2_stats[i].name, ETH_GSTRING_LEN);
2452 /* Use hardware MIB variables for critical path statistics and
2453 * transmit feedback not reported at interrupt.
2454 * Other errors are accounted for in interrupt handler.
2456 static struct net_device_stats *sky2_get_stats(struct net_device *dev)
2458 struct sky2_port *sky2 = netdev_priv(dev);
2461 sky2_phy_stats(sky2, data, ARRAY_SIZE(data));
2463 sky2->net_stats.tx_bytes = data[0];
2464 sky2->net_stats.rx_bytes = data[1];
2465 sky2->net_stats.tx_packets = data[2] + data[4] + data[6];
2466 sky2->net_stats.rx_packets = data[3] + data[5] + data[7];
2467 sky2->net_stats.multicast = data[5] + data[7];
2468 sky2->net_stats.collisions = data[10];
2469 sky2->net_stats.tx_aborted_errors = data[12];
2471 return &sky2->net_stats;
2474 static int sky2_set_mac_address(struct net_device *dev, void *p)
2476 struct sky2_port *sky2 = netdev_priv(dev);
2477 struct sockaddr *addr = p;
2480 if (!is_valid_ether_addr(addr->sa_data))
2481 return -EADDRNOTAVAIL;
2484 memcpy(dev->dev_addr, addr->sa_data, ETH_ALEN);
2485 memcpy_toio(sky2->hw->regs + B2_MAC_1 + sky2->port * 8,
2486 dev->dev_addr, ETH_ALEN);
2487 memcpy_toio(sky2->hw->regs + B2_MAC_2 + sky2->port * 8,
2488 dev->dev_addr, ETH_ALEN);
2489 if (dev->flags & IFF_UP)
2494 static void sky2_set_multicast(struct net_device *dev)
2496 struct sky2_port *sky2 = netdev_priv(dev);
2497 struct sky2_hw *hw = sky2->hw;
2498 unsigned port = sky2->port;
2499 struct dev_mc_list *list = dev->mc_list;
2503 memset(filter, 0, sizeof(filter));
2505 reg = gma_read16(hw, port, GM_RX_CTRL);
2506 reg |= GM_RXCR_UCF_ENA;
2508 if (dev->flags & IFF_PROMISC) /* promiscuous */
2509 reg &= ~(GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA);
2510 else if ((dev->flags & IFF_ALLMULTI) || dev->mc_count > 16) /* all multicast */
2511 memset(filter, 0xff, sizeof(filter));
2512 else if (dev->mc_count == 0) /* no multicast */
2513 reg &= ~GM_RXCR_MCF_ENA;
2516 reg |= GM_RXCR_MCF_ENA;
2518 for (i = 0; list && i < dev->mc_count; i++, list = list->next) {
2519 u32 bit = ether_crc(ETH_ALEN, list->dmi_addr) & 0x3f;
2520 filter[bit / 8] |= 1 << (bit % 8);
2524 gma_write16(hw, port, GM_MC_ADDR_H1,
2525 (u16) filter[0] | ((u16) filter[1] << 8));
2526 gma_write16(hw, port, GM_MC_ADDR_H2,
2527 (u16) filter[2] | ((u16) filter[3] << 8));
2528 gma_write16(hw, port, GM_MC_ADDR_H3,
2529 (u16) filter[4] | ((u16) filter[5] << 8));
2530 gma_write16(hw, port, GM_MC_ADDR_H4,
2531 (u16) filter[6] | ((u16) filter[7] << 8));
2533 gma_write16(hw, port, GM_RX_CTRL, reg);
2536 /* Can have one global because blinking is controlled by
2537 * ethtool and that is always under RTNL mutex
2539 static inline void sky2_led(struct sky2_hw *hw, unsigned port, int on)
2543 spin_lock_bh(&hw->phy_lock);
2544 switch (hw->chip_id) {
2545 case CHIP_ID_YUKON_XL:
2546 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
2547 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
2548 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
2549 on ? (PHY_M_LEDC_LOS_CTRL(1) |
2550 PHY_M_LEDC_INIT_CTRL(7) |
2551 PHY_M_LEDC_STA1_CTRL(7) |
2552 PHY_M_LEDC_STA0_CTRL(7))
2555 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
2559 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, 0);
2560 gm_phy_write(hw, port, PHY_MARV_LED_OVER,
2561 on ? PHY_M_LED_MO_DUP(MO_LED_ON) |
2562 PHY_M_LED_MO_10(MO_LED_ON) |
2563 PHY_M_LED_MO_100(MO_LED_ON) |
2564 PHY_M_LED_MO_1000(MO_LED_ON) |
2565 PHY_M_LED_MO_RX(MO_LED_ON)
2566 : PHY_M_LED_MO_DUP(MO_LED_OFF) |
2567 PHY_M_LED_MO_10(MO_LED_OFF) |
2568 PHY_M_LED_MO_100(MO_LED_OFF) |
2569 PHY_M_LED_MO_1000(MO_LED_OFF) |
2570 PHY_M_LED_MO_RX(MO_LED_OFF));
2573 spin_unlock_bh(&hw->phy_lock);
2576 /* blink LED's for finding board */
2577 static int sky2_phys_id(struct net_device *dev, u32 data)
2579 struct sky2_port *sky2 = netdev_priv(dev);
2580 struct sky2_hw *hw = sky2->hw;
2581 unsigned port = sky2->port;
2582 u16 ledctrl, ledover = 0;
2586 if (!data || data > (u32) (MAX_SCHEDULE_TIMEOUT / HZ))
2587 ms = jiffies_to_msecs(MAX_SCHEDULE_TIMEOUT);
2591 /* save initial values */
2592 spin_lock_bh(&hw->phy_lock);
2593 if (hw->chip_id == CHIP_ID_YUKON_XL) {
2594 u16 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
2595 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
2596 ledctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
2597 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
2599 ledctrl = gm_phy_read(hw, port, PHY_MARV_LED_CTRL);
2600 ledover = gm_phy_read(hw, port, PHY_MARV_LED_OVER);
2602 spin_unlock_bh(&hw->phy_lock);
2605 sky2_led(hw, port, onoff);
2608 if (msleep_interruptible(250))
2609 break; /* interrupted */
2613 /* resume regularly scheduled programming */
2614 spin_lock_bh(&hw->phy_lock);
2615 if (hw->chip_id == CHIP_ID_YUKON_XL) {
2616 u16 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
2617 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
2618 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ledctrl);
2619 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
2621 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, ledctrl);
2622 gm_phy_write(hw, port, PHY_MARV_LED_OVER, ledover);
2624 spin_unlock_bh(&hw->phy_lock);
2629 static void sky2_get_pauseparam(struct net_device *dev,
2630 struct ethtool_pauseparam *ecmd)
2632 struct sky2_port *sky2 = netdev_priv(dev);
2634 ecmd->tx_pause = sky2->tx_pause;
2635 ecmd->rx_pause = sky2->rx_pause;
2636 ecmd->autoneg = sky2->autoneg;
2639 static int sky2_set_pauseparam(struct net_device *dev,
2640 struct ethtool_pauseparam *ecmd)
2642 struct sky2_port *sky2 = netdev_priv(dev);
2645 sky2->autoneg = ecmd->autoneg;
2646 sky2->tx_pause = ecmd->tx_pause != 0;
2647 sky2->rx_pause = ecmd->rx_pause != 0;
2649 if (netif_running(dev)) {
2658 static void sky2_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
2660 struct sky2_port *sky2 = netdev_priv(dev);
2662 wol->supported = WAKE_MAGIC;
2663 wol->wolopts = sky2->wol ? WAKE_MAGIC : 0;
2666 static int sky2_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
2668 struct sky2_port *sky2 = netdev_priv(dev);
2669 struct sky2_hw *hw = sky2->hw;
2671 if (wol->wolopts != WAKE_MAGIC && wol->wolopts != 0)
2674 sky2->wol = wol->wolopts == WAKE_MAGIC;
2677 memcpy_toio(hw->regs + WOL_MAC_ADDR, dev->dev_addr, ETH_ALEN);
2679 sky2_write16(hw, WOL_CTRL_STAT,
2680 WOL_CTL_ENA_PME_ON_MAGIC_PKT |
2681 WOL_CTL_ENA_MAGIC_PKT_UNIT);
2683 sky2_write16(hw, WOL_CTRL_STAT, WOL_CTL_DEFAULT);
2689 static void sky2_get_ringparam(struct net_device *dev,
2690 struct ethtool_ringparam *ering)
2692 struct sky2_port *sky2 = netdev_priv(dev);
2694 ering->rx_max_pending = RX_MAX_PENDING;
2695 ering->rx_mini_max_pending = 0;
2696 ering->rx_jumbo_max_pending = 0;
2697 ering->tx_max_pending = TX_RING_SIZE - 1;
2699 ering->rx_pending = sky2->rx_pending;
2700 ering->rx_mini_pending = 0;
2701 ering->rx_jumbo_pending = 0;
2702 ering->tx_pending = sky2->tx_pending;
2705 static int sky2_set_ringparam(struct net_device *dev,
2706 struct ethtool_ringparam *ering)
2708 struct sky2_port *sky2 = netdev_priv(dev);
2711 if (ering->rx_pending > RX_MAX_PENDING ||
2712 ering->rx_pending < 8 ||
2713 ering->tx_pending < MAX_SKB_TX_LE ||
2714 ering->tx_pending > TX_RING_SIZE - 1)
2717 if (netif_running(dev))
2720 sky2->rx_pending = ering->rx_pending;
2721 sky2->tx_pending = ering->tx_pending;
2723 if (netif_running(dev))
2729 static int sky2_get_regs_len(struct net_device *dev)
2735 * Returns copy of control register region
2736 * Note: access to the RAM address register set will cause timeouts.
2738 static void sky2_get_regs(struct net_device *dev, struct ethtool_regs *regs,
2741 const struct sky2_port *sky2 = netdev_priv(dev);
2742 const void __iomem *io = sky2->hw->regs;
2744 BUG_ON(regs->len < B3_RI_WTO_R1);
2746 memset(p, 0, regs->len);
2748 memcpy_fromio(p, io, B3_RAM_ADDR);
2750 memcpy_fromio(p + B3_RI_WTO_R1,
2752 regs->len - B3_RI_WTO_R1);
2755 static struct ethtool_ops sky2_ethtool_ops = {
2756 .get_settings = sky2_get_settings,
2757 .set_settings = sky2_set_settings,
2758 .get_drvinfo = sky2_get_drvinfo,
2759 .get_msglevel = sky2_get_msglevel,
2760 .set_msglevel = sky2_set_msglevel,
2761 .nway_reset = sky2_nway_reset,
2762 .get_regs_len = sky2_get_regs_len,
2763 .get_regs = sky2_get_regs,
2764 .get_link = ethtool_op_get_link,
2765 .get_sg = ethtool_op_get_sg,
2766 .set_sg = ethtool_op_set_sg,
2767 .get_tx_csum = ethtool_op_get_tx_csum,
2768 .set_tx_csum = ethtool_op_set_tx_csum,
2769 .get_tso = ethtool_op_get_tso,
2770 .set_tso = ethtool_op_set_tso,
2771 .get_rx_csum = sky2_get_rx_csum,
2772 .set_rx_csum = sky2_set_rx_csum,
2773 .get_strings = sky2_get_strings,
2774 .get_ringparam = sky2_get_ringparam,
2775 .set_ringparam = sky2_set_ringparam,
2776 .get_pauseparam = sky2_get_pauseparam,
2777 .set_pauseparam = sky2_set_pauseparam,
2779 .get_wol = sky2_get_wol,
2780 .set_wol = sky2_set_wol,
2782 .phys_id = sky2_phys_id,
2783 .get_stats_count = sky2_get_stats_count,
2784 .get_ethtool_stats = sky2_get_ethtool_stats,
2785 .get_perm_addr = ethtool_op_get_perm_addr,
2788 /* Initialize network device */
2789 static __devinit struct net_device *sky2_init_netdev(struct sky2_hw *hw,
2790 unsigned port, int highmem)
2792 struct sky2_port *sky2;
2793 struct net_device *dev = alloc_etherdev(sizeof(*sky2));
2796 printk(KERN_ERR "sky2 etherdev alloc failed");
2800 SET_MODULE_OWNER(dev);
2801 SET_NETDEV_DEV(dev, &hw->pdev->dev);
2802 dev->irq = hw->pdev->irq;
2803 dev->open = sky2_up;
2804 dev->stop = sky2_down;
2805 dev->do_ioctl = sky2_ioctl;
2806 dev->hard_start_xmit = sky2_xmit_frame;
2807 dev->get_stats = sky2_get_stats;
2808 dev->set_multicast_list = sky2_set_multicast;
2809 dev->set_mac_address = sky2_set_mac_address;
2810 dev->change_mtu = sky2_change_mtu;
2811 SET_ETHTOOL_OPS(dev, &sky2_ethtool_ops);
2812 dev->tx_timeout = sky2_tx_timeout;
2813 dev->watchdog_timeo = TX_WATCHDOG;
2815 dev->poll = sky2_poll;
2816 dev->weight = NAPI_WEIGHT;
2817 #ifdef CONFIG_NET_POLL_CONTROLLER
2818 dev->poll_controller = sky2_netpoll;
2821 sky2 = netdev_priv(dev);
2824 sky2->msg_enable = netif_msg_init(debug, default_msg);
2826 spin_lock_init(&sky2->tx_lock);
2827 /* Auto speed and flow control */
2828 sky2->autoneg = AUTONEG_ENABLE;
2833 sky2->advertising = sky2_supported_modes(hw);
2835 tasklet_init(&sky2->phy_task, sky2_phy_task, (unsigned long)sky2);
2836 sky2->tx_pending = TX_DEF_PENDING;
2837 sky2->rx_pending = is_ec_a1(hw) ? 8 : RX_DEF_PENDING;
2839 hw->dev[port] = dev;
2843 dev->features |= NETIF_F_LLTX;
2844 if (hw->chip_id != CHIP_ID_YUKON_EC_U)
2845 dev->features |= NETIF_F_TSO;
2847 dev->features |= NETIF_F_HIGHDMA;
2848 dev->features |= NETIF_F_IP_CSUM | NETIF_F_SG;
2850 #ifdef SKY2_VLAN_TAG_USED
2851 dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
2852 dev->vlan_rx_register = sky2_vlan_rx_register;
2853 dev->vlan_rx_kill_vid = sky2_vlan_rx_kill_vid;
2856 /* read the mac address */
2857 memcpy_fromio(dev->dev_addr, hw->regs + B2_MAC_1 + port * 8, ETH_ALEN);
2858 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
2860 /* device is off until link detection */
2861 netif_carrier_off(dev);
2862 netif_stop_queue(dev);
2867 static inline void sky2_show_addr(struct net_device *dev)
2869 const struct sky2_port *sky2 = netdev_priv(dev);
2871 if (netif_msg_probe(sky2))
2872 printk(KERN_INFO PFX "%s: addr %02x:%02x:%02x:%02x:%02x:%02x\n",
2874 dev->dev_addr[0], dev->dev_addr[1], dev->dev_addr[2],
2875 dev->dev_addr[3], dev->dev_addr[4], dev->dev_addr[5]);
2878 static int __devinit sky2_probe(struct pci_dev *pdev,
2879 const struct pci_device_id *ent)
2881 struct net_device *dev, *dev1 = NULL;
2883 int err, pm_cap, using_dac = 0;
2885 err = pci_enable_device(pdev);
2887 printk(KERN_ERR PFX "%s cannot enable PCI device\n",
2892 err = pci_request_regions(pdev, DRV_NAME);
2894 printk(KERN_ERR PFX "%s cannot obtain PCI resources\n",
2899 pci_set_master(pdev);
2901 /* Find power-management capability. */
2902 pm_cap = pci_find_capability(pdev, PCI_CAP_ID_PM);
2904 printk(KERN_ERR PFX "Cannot find PowerManagement capability, "
2907 goto err_out_free_regions;
2910 if (sizeof(dma_addr_t) > sizeof(u32)) {
2911 err = pci_set_dma_mask(pdev, DMA_64BIT_MASK);
2917 err = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
2919 printk(KERN_ERR PFX "%s no usable DMA configuration\n",
2921 goto err_out_free_regions;
2925 /* byte swap descriptors in hardware */
2929 pci_read_config_dword(pdev, PCI_DEV_REG2, ®);
2930 reg |= PCI_REV_DESC;
2931 pci_write_config_dword(pdev, PCI_DEV_REG2, reg);
2936 hw = kmalloc(sizeof(*hw), GFP_KERNEL);
2938 printk(KERN_ERR PFX "%s: cannot allocate hardware struct\n",
2940 goto err_out_free_regions;
2943 memset(hw, 0, sizeof(*hw));
2945 spin_lock_init(&hw->phy_lock);
2947 hw->regs = ioremap_nocache(pci_resource_start(pdev, 0), 0x4000);
2949 printk(KERN_ERR PFX "%s: cannot map device registers\n",
2951 goto err_out_free_hw;
2953 hw->pm_cap = pm_cap;
2955 err = sky2_reset(hw);
2957 goto err_out_iounmap;
2959 printk(KERN_INFO PFX "addr 0x%lx irq %d Yukon-%s (0x%x) rev %d\n",
2960 pci_resource_start(pdev, 0), pdev->irq,
2961 yukon_name[hw->chip_id - CHIP_ID_YUKON],
2962 hw->chip_id, hw->chip_rev);
2964 dev = sky2_init_netdev(hw, 0, using_dac);
2966 goto err_out_free_pci;
2968 err = register_netdev(dev);
2970 printk(KERN_ERR PFX "%s: cannot register net device\n",
2972 goto err_out_free_netdev;
2975 sky2_show_addr(dev);
2977 if (hw->ports > 1 && (dev1 = sky2_init_netdev(hw, 1, using_dac))) {
2978 if (register_netdev(dev1) == 0)
2979 sky2_show_addr(dev1);
2981 /* Failure to register second port need not be fatal */
2982 printk(KERN_WARNING PFX
2983 "register of second port failed\n");
2989 err = request_irq(pdev->irq, sky2_intr, SA_SHIRQ, DRV_NAME, hw);
2991 printk(KERN_ERR PFX "%s: cannot assign irq %d\n",
2992 pci_name(pdev), pdev->irq);
2993 goto err_out_unregister;
2996 hw->intr_mask = Y2_IS_BASE;
2997 sky2_write32(hw, B0_IMSK, hw->intr_mask);
2999 pci_set_drvdata(pdev, hw);
3005 unregister_netdev(dev1);
3008 unregister_netdev(dev);
3009 err_out_free_netdev:
3012 sky2_write8(hw, B0_CTST, CS_RST_SET);
3013 pci_free_consistent(hw->pdev, STATUS_LE_BYTES, hw->st_le, hw->st_dma);
3018 err_out_free_regions:
3019 pci_release_regions(pdev);
3020 pci_disable_device(pdev);
3025 static void __devexit sky2_remove(struct pci_dev *pdev)
3027 struct sky2_hw *hw = pci_get_drvdata(pdev);
3028 struct net_device *dev0, *dev1;
3036 unregister_netdev(dev1);
3037 unregister_netdev(dev0);
3039 sky2_write32(hw, B0_IMSK, 0);
3040 sky2_set_power_state(hw, PCI_D3hot);
3041 sky2_write16(hw, B0_Y2LED, LED_STAT_OFF);
3042 sky2_write8(hw, B0_CTST, CS_RST_SET);
3043 sky2_read8(hw, B0_CTST);
3045 free_irq(pdev->irq, hw);
3046 pci_free_consistent(pdev, STATUS_LE_BYTES, hw->st_le, hw->st_dma);
3047 pci_release_regions(pdev);
3048 pci_disable_device(pdev);
3056 pci_set_drvdata(pdev, NULL);
3060 static int sky2_suspend(struct pci_dev *pdev, pm_message_t state)
3062 struct sky2_hw *hw = pci_get_drvdata(pdev);
3065 for (i = 0; i < 2; i++) {
3066 struct net_device *dev = hw->dev[i];
3069 if (!netif_running(dev))
3073 netif_device_detach(dev);
3077 return sky2_set_power_state(hw, pci_choose_state(pdev, state));
3080 static int sky2_resume(struct pci_dev *pdev)
3082 struct sky2_hw *hw = pci_get_drvdata(pdev);
3085 pci_restore_state(pdev);
3086 pci_enable_wake(pdev, PCI_D0, 0);
3087 sky2_set_power_state(hw, PCI_D0);
3091 for (i = 0; i < 2; i++) {
3092 struct net_device *dev = hw->dev[i];
3094 if (netif_running(dev)) {
3095 netif_device_attach(dev);
3104 static struct pci_driver sky2_driver = {
3106 .id_table = sky2_id_table,
3107 .probe = sky2_probe,
3108 .remove = __devexit_p(sky2_remove),
3110 .suspend = sky2_suspend,
3111 .resume = sky2_resume,
3115 static int __init sky2_init_module(void)
3117 return pci_module_init(&sky2_driver);
3120 static void __exit sky2_cleanup_module(void)
3122 pci_unregister_driver(&sky2_driver);
3125 module_init(sky2_init_module);
3126 module_exit(sky2_cleanup_module);
3128 MODULE_DESCRIPTION("Marvell Yukon 2 Gigabit Ethernet driver");
3129 MODULE_AUTHOR("Stephen Hemminger <shemminger@osdl.org>");
3130 MODULE_LICENSE("GPL");