2 * New driver for Marvell Yukon 2 chipset.
3 * Based on earlier sk98lin, and skge driver.
5 * This driver intentionally does not support all the features
6 * of the original driver such as link fail-over and link management because
7 * those should be done at higher levels.
9 * Copyright (C) 2005 Stephen Hemminger <shemminger@osdl.org>
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License, or
14 * (at your option) any later version.
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
28 * - coalescing setting?
35 #include <linux/config.h>
36 #include <linux/crc32.h>
37 #include <linux/kernel.h>
38 #include <linux/version.h>
39 #include <linux/module.h>
40 #include <linux/netdevice.h>
41 #include <linux/dma-mapping.h>
42 #include <linux/etherdevice.h>
43 #include <linux/ethtool.h>
44 #include <linux/pci.h>
46 #include <linux/tcp.h>
48 #include <linux/delay.h>
49 #include <linux/if_vlan.h>
53 #if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
54 #define SKY2_VLAN_TAG_USED 1
59 #define DRV_NAME "sky2"
60 #define DRV_VERSION "0.7"
61 #define PFX DRV_NAME " "
64 * The Yukon II chipset takes 64 bit command blocks (called list elements)
65 * that are organized into three (receive, transmit, status) different rings
66 * similar to Tigon3. A transmit can require several elements;
67 * a receive requires one (or two if using 64 bit dma).
70 #define is_ec_a1(hw) \
71 unlikely((hw)->chip_id == CHIP_ID_YUKON_EC && \
72 (hw)->chip_rev == CHIP_REV_YU_EC_A1)
74 #define RX_LE_SIZE 256
75 #define RX_LE_BYTES (RX_LE_SIZE*sizeof(struct sky2_rx_le))
76 #define RX_MAX_PENDING (RX_LE_SIZE/2 - 2)
77 #define RX_DEF_PENDING 128
78 #define RX_COPY_THRESHOLD 256
80 #define TX_RING_SIZE 512
81 #define TX_DEF_PENDING (TX_RING_SIZE - 1)
82 #define TX_MIN_PENDING 64
83 #define MAX_SKB_TX_LE (4 + 2*MAX_SKB_FRAGS)
85 #define STATUS_RING_SIZE 2048 /* 2 ports * (TX + 2*RX) */
86 #define STATUS_LE_BYTES (STATUS_RING_SIZE*sizeof(struct sky2_status_le))
87 #define ETH_JUMBO_MTU 9000
88 #define TX_WATCHDOG (5 * HZ)
89 #define NAPI_WEIGHT 64
90 #define PHY_RETRIES 1000
92 static const u32 default_msg =
93 NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_LINK
94 | NETIF_MSG_TIMER | NETIF_MSG_TX_ERR | NETIF_MSG_RX_ERR
95 | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN | NETIF_MSG_INTR;
97 static int debug = -1; /* defaults above */
98 module_param(debug, int, 0);
99 MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
101 static const struct pci_device_id sky2_id_table[] = {
102 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, 0x9000) },
103 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, 0x9E00) },
104 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4b00) },
105 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4b01) },
106 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4340) },
107 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4341) },
108 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4342) },
109 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4343) },
110 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4344) },
111 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4345) },
112 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4346) },
113 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4347) },
114 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4350) },
115 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4351) },
116 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4360) },
117 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4361) },
118 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4362) },
122 MODULE_DEVICE_TABLE(pci, sky2_id_table);
124 /* Avoid conditionals by using array */
125 static const unsigned txqaddr[] = { Q_XA1, Q_XA2 };
126 static const unsigned rxqaddr[] = { Q_R1, Q_R2 };
128 static const char *yukon_name[] = {
129 [CHIP_ID_YUKON_LITE - CHIP_ID_YUKON] = "Lite", /* 0xb0 */
130 [CHIP_ID_YUKON_LP - CHIP_ID_YUKON] = "LP", /* 0xb2 */
131 [CHIP_ID_YUKON_XL - CHIP_ID_YUKON] = "XL", /* 0xb3 */
133 [CHIP_ID_YUKON_EC - CHIP_ID_YUKON] = "EC", /* 0xb6 */
134 [CHIP_ID_YUKON_FE - CHIP_ID_YUKON] = "FE", /* 0xb7 */
138 /* Access to external PHY */
139 static void gm_phy_write(struct sky2_hw *hw, unsigned port, u16 reg, u16 val)
143 gma_write16(hw, port, GM_SMI_DATA, val);
144 gma_write16(hw, port, GM_SMI_CTRL,
145 GM_SMI_CT_PHY_AD(PHY_ADDR_MARV) | GM_SMI_CT_REG_AD(reg));
147 for (i = 0; i < PHY_RETRIES; i++) {
148 if (!(gma_read16(hw, port, GM_SMI_CTRL) & GM_SMI_CT_BUSY))
152 printk(KERN_WARNING PFX "%s: phy write timeout\n", hw->dev[port]->name);
155 static u16 gm_phy_read(struct sky2_hw *hw, unsigned port, u16 reg)
159 gma_write16(hw, port, GM_SMI_CTRL, GM_SMI_CT_PHY_AD(PHY_ADDR_MARV)
160 | GM_SMI_CT_REG_AD(reg) | GM_SMI_CT_OP_RD);
162 for (i = 0; i < PHY_RETRIES; i++) {
163 if (gma_read16(hw, port, GM_SMI_CTRL) & GM_SMI_CT_RD_VAL)
168 printk(KERN_WARNING PFX "%s: phy read timeout\n", hw->dev[port]->name);
170 return gma_read16(hw, port, GM_SMI_DATA);
173 static int sky2_set_power_state(struct sky2_hw *hw, pci_power_t state)
180 pr_debug("sky2_set_power_state %d\n", state);
181 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
183 pci_read_config_word(hw->pdev, hw->pm_cap + PCI_PM_PMC, &power_control);
184 vaux = (sky2_read8(hw, B0_CTST) & Y2_VAUX_AVAIL) &&
185 (power_control & PCI_PM_CAP_PME_D3cold);
187 pci_read_config_word(hw->pdev, hw->pm_cap + PCI_PM_CTRL, &power_control);
189 power_control |= PCI_PM_CTRL_PME_STATUS;
190 power_control &= ~(PCI_PM_CTRL_STATE_MASK);
194 /* switch power to VCC (WA for VAUX problem) */
195 sky2_write8(hw, B0_POWER_CTRL,
196 PC_VAUX_ENA | PC_VCC_ENA | PC_VAUX_OFF | PC_VCC_ON);
198 /* disable Core Clock Division, */
199 sky2_write32(hw, B2_Y2_CLK_CTRL, Y2_CLK_DIV_DIS);
201 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1)
202 /* enable bits are inverted */
203 sky2_write8(hw, B2_Y2_CLK_GATE,
204 Y2_PCI_CLK_LNK1_DIS | Y2_COR_CLK_LNK1_DIS |
205 Y2_CLK_GAT_LNK1_DIS | Y2_PCI_CLK_LNK2_DIS |
206 Y2_COR_CLK_LNK2_DIS | Y2_CLK_GAT_LNK2_DIS);
208 sky2_write8(hw, B2_Y2_CLK_GATE, 0);
210 /* Turn off phy power saving */
211 pci_read_config_dword(hw->pdev, PCI_DEV_REG1, ®1);
212 reg1 &= ~(PCI_Y2_PHY1_POWD | PCI_Y2_PHY2_POWD);
214 /* looks like this XL is back asswards .. */
215 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1) {
216 reg1 |= PCI_Y2_PHY1_COMA;
218 reg1 |= PCI_Y2_PHY2_COMA;
220 pci_write_config_dword(hw->pdev, PCI_DEV_REG1, reg1);
225 /* Turn on phy power saving */
226 pci_read_config_dword(hw->pdev, PCI_DEV_REG1, ®1);
227 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1)
228 reg1 &= ~(PCI_Y2_PHY1_POWD | PCI_Y2_PHY2_POWD);
230 reg1 |= (PCI_Y2_PHY1_POWD | PCI_Y2_PHY2_POWD);
231 pci_write_config_dword(hw->pdev, PCI_DEV_REG1, reg1);
233 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1)
234 sky2_write8(hw, B2_Y2_CLK_GATE, 0);
236 /* enable bits are inverted */
237 sky2_write8(hw, B2_Y2_CLK_GATE,
238 Y2_PCI_CLK_LNK1_DIS | Y2_COR_CLK_LNK1_DIS |
239 Y2_CLK_GAT_LNK1_DIS | Y2_PCI_CLK_LNK2_DIS |
240 Y2_COR_CLK_LNK2_DIS | Y2_CLK_GAT_LNK2_DIS);
242 /* switch power to VAUX */
243 if (vaux && state != PCI_D3cold)
244 sky2_write8(hw, B0_POWER_CTRL,
245 (PC_VAUX_ENA | PC_VCC_ENA |
246 PC_VAUX_ON | PC_VCC_OFF));
249 printk(KERN_ERR PFX "Unknown power state %d\n", state);
253 pci_write_config_byte(hw->pdev, hw->pm_cap + PCI_PM_CTRL, power_control);
254 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
258 static void sky2_phy_reset(struct sky2_hw *hw, unsigned port)
262 /* disable all GMAC IRQ's */
263 sky2_write8(hw, SK_REG(port, GMAC_IRQ_MSK), 0);
264 /* disable PHY IRQs */
265 gm_phy_write(hw, port, PHY_MARV_INT_MASK, 0);
267 gma_write16(hw, port, GM_MC_ADDR_H1, 0); /* clear MC hash */
268 gma_write16(hw, port, GM_MC_ADDR_H2, 0);
269 gma_write16(hw, port, GM_MC_ADDR_H3, 0);
270 gma_write16(hw, port, GM_MC_ADDR_H4, 0);
272 reg = gma_read16(hw, port, GM_RX_CTRL);
273 reg |= GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA;
274 gma_write16(hw, port, GM_RX_CTRL, reg);
277 static void sky2_phy_init(struct sky2_hw *hw, unsigned port)
279 struct sky2_port *sky2 = netdev_priv(hw->dev[port]);
280 u16 ctrl, ct1000, adv, pg, ledctrl, ledover;
282 if (sky2->autoneg == AUTONEG_ENABLE && hw->chip_id != CHIP_ID_YUKON_XL) {
283 u16 ectrl = gm_phy_read(hw, port, PHY_MARV_EXT_CTRL);
285 ectrl &= ~(PHY_M_EC_M_DSC_MSK | PHY_M_EC_S_DSC_MSK |
287 ectrl |= PHY_M_EC_MAC_S(MAC_TX_CLK_25_MHZ);
289 if (hw->chip_id == CHIP_ID_YUKON_EC)
290 ectrl |= PHY_M_EC_DSC_2(2) | PHY_M_EC_DOWN_S_ENA;
292 ectrl |= PHY_M_EC_M_DSC(2) | PHY_M_EC_S_DSC(3);
294 gm_phy_write(hw, port, PHY_MARV_EXT_CTRL, ectrl);
297 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
299 if (hw->chip_id == CHIP_ID_YUKON_FE) {
300 /* enable automatic crossover */
301 ctrl |= PHY_M_PC_MDI_XMODE(PHY_M_PC_ENA_AUTO) >> 1;
303 /* disable energy detect */
304 ctrl &= ~PHY_M_PC_EN_DET_MSK;
306 /* enable automatic crossover */
307 ctrl |= PHY_M_PC_MDI_XMODE(PHY_M_PC_ENA_AUTO);
309 if (sky2->autoneg == AUTONEG_ENABLE &&
310 hw->chip_id == CHIP_ID_YUKON_XL) {
311 ctrl &= ~PHY_M_PC_DSC_MSK;
312 ctrl |= PHY_M_PC_DSC(2) | PHY_M_PC_DOWN_S_ENA;
315 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
317 /* workaround for deviation #4.88 (CRC errors) */
318 /* disable Automatic Crossover */
320 ctrl &= ~PHY_M_PC_MDIX_MSK;
321 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
323 if (hw->chip_id == CHIP_ID_YUKON_XL) {
324 /* Fiber: select 1000BASE-X only mode MAC Specific Ctrl Reg. */
325 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 2);
326 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
327 ctrl &= ~PHY_M_MAC_MD_MSK;
328 ctrl |= PHY_M_MAC_MODE_SEL(PHY_M_MAC_MD_1000BX);
329 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
331 /* select page 1 to access Fiber registers */
332 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 1);
336 ctrl = gm_phy_read(hw, port, PHY_MARV_CTRL);
337 if (sky2->autoneg == AUTONEG_DISABLE)
342 ctrl |= PHY_CT_RESET;
343 gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
349 if (sky2->autoneg == AUTONEG_ENABLE) {
351 if (sky2->advertising & ADVERTISED_1000baseT_Full)
352 ct1000 |= PHY_M_1000C_AFD;
353 if (sky2->advertising & ADVERTISED_1000baseT_Half)
354 ct1000 |= PHY_M_1000C_AHD;
355 if (sky2->advertising & ADVERTISED_100baseT_Full)
356 adv |= PHY_M_AN_100_FD;
357 if (sky2->advertising & ADVERTISED_100baseT_Half)
358 adv |= PHY_M_AN_100_HD;
359 if (sky2->advertising & ADVERTISED_10baseT_Full)
360 adv |= PHY_M_AN_10_FD;
361 if (sky2->advertising & ADVERTISED_10baseT_Half)
362 adv |= PHY_M_AN_10_HD;
363 } else /* special defines for FIBER (88E1011S only) */
364 adv |= PHY_M_AN_1000X_AHD | PHY_M_AN_1000X_AFD;
366 /* Set Flow-control capabilities */
367 if (sky2->tx_pause && sky2->rx_pause)
368 adv |= PHY_AN_PAUSE_CAP; /* symmetric */
369 else if (sky2->rx_pause && !sky2->tx_pause)
370 adv |= PHY_AN_PAUSE_ASYM | PHY_AN_PAUSE_CAP;
371 else if (!sky2->rx_pause && sky2->tx_pause)
372 adv |= PHY_AN_PAUSE_ASYM; /* local */
374 /* Restart Auto-negotiation */
375 ctrl |= PHY_CT_ANE | PHY_CT_RE_CFG;
377 /* forced speed/duplex settings */
378 ct1000 = PHY_M_1000C_MSE;
380 if (sky2->duplex == DUPLEX_FULL)
381 ctrl |= PHY_CT_DUP_MD;
383 switch (sky2->speed) {
385 ctrl |= PHY_CT_SP1000;
388 ctrl |= PHY_CT_SP100;
392 ctrl |= PHY_CT_RESET;
395 if (hw->chip_id != CHIP_ID_YUKON_FE)
396 gm_phy_write(hw, port, PHY_MARV_1000T_CTRL, ct1000);
398 gm_phy_write(hw, port, PHY_MARV_AUNE_ADV, adv);
399 gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
401 /* Setup Phy LED's */
402 ledctrl = PHY_M_LED_PULS_DUR(PULS_170MS);
405 switch (hw->chip_id) {
406 case CHIP_ID_YUKON_FE:
407 /* on 88E3082 these bits are at 11..9 (shifted left) */
408 ledctrl |= PHY_M_LED_BLINK_RT(BLINK_84MS) << 1;
410 ctrl = gm_phy_read(hw, port, PHY_MARV_FE_LED_PAR);
412 /* delete ACT LED control bits */
413 ctrl &= ~PHY_M_FELP_LED1_MSK;
414 /* change ACT LED control to blink mode */
415 ctrl |= PHY_M_FELP_LED1_CTRL(LED_PAR_CTRL_ACT_BL);
416 gm_phy_write(hw, port, PHY_MARV_FE_LED_PAR, ctrl);
419 case CHIP_ID_YUKON_XL:
420 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
422 /* select page 3 to access LED control register */
423 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
425 /* set LED Function Control register */
426 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, (PHY_M_LEDC_LOS_CTRL(1) | /* LINK/ACT */
427 PHY_M_LEDC_INIT_CTRL(7) | /* 10 Mbps */
428 PHY_M_LEDC_STA1_CTRL(7) | /* 100 Mbps */
429 PHY_M_LEDC_STA0_CTRL(7))); /* 1000 Mbps */
431 /* set Polarity Control register */
432 gm_phy_write(hw, port, PHY_MARV_PHY_STAT,
433 (PHY_M_POLC_LS1_P_MIX(4) |
434 PHY_M_POLC_IS0_P_MIX(4) |
435 PHY_M_POLC_LOS_CTRL(2) |
436 PHY_M_POLC_INIT_CTRL(2) |
437 PHY_M_POLC_STA1_CTRL(2) |
438 PHY_M_POLC_STA0_CTRL(2)));
440 /* restore page register */
441 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
445 /* set Tx LED (LED_TX) to blink mode on Rx OR Tx activity */
446 ledctrl |= PHY_M_LED_BLINK_RT(BLINK_84MS) | PHY_M_LEDC_TX_CTRL;
447 /* turn off the Rx LED (LED_RX) */
448 ledover |= PHY_M_LED_MO_RX(MO_LED_OFF);
451 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, ledctrl);
453 if (sky2->autoneg == AUTONEG_DISABLE || sky2->speed == SPEED_100) {
454 /* turn on 100 Mbps LED (LED_LINK100) */
455 ledover |= PHY_M_LED_MO_100(MO_LED_ON);
459 gm_phy_write(hw, port, PHY_MARV_LED_OVER, ledover);
461 /* Enable phy interrupt on auto-negotiation complete (or link up) */
462 if (sky2->autoneg == AUTONEG_ENABLE)
463 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_IS_AN_COMPL);
465 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_DEF_MSK);
468 static void sky2_mac_init(struct sky2_hw *hw, unsigned port)
470 struct sky2_port *sky2 = netdev_priv(hw->dev[port]);
473 const u8 *addr = hw->dev[port]->dev_addr;
475 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET);
476 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_CLR);
478 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_CLR);
480 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0 && port == 1) {
481 /* WA DEV_472 -- looks like crossed wires on port 2 */
482 /* clear GMAC 1 Control reset */
483 sky2_write8(hw, SK_REG(0, GMAC_CTRL), GMC_RST_CLR);
485 sky2_write8(hw, SK_REG(1, GMAC_CTRL), GMC_RST_SET);
486 sky2_write8(hw, SK_REG(1, GMAC_CTRL), GMC_RST_CLR);
487 } while (gm_phy_read(hw, 1, PHY_MARV_ID0) != PHY_MARV_ID0_VAL ||
488 gm_phy_read(hw, 1, PHY_MARV_ID1) != PHY_MARV_ID1_Y2 ||
489 gm_phy_read(hw, 1, PHY_MARV_INT_MASK) != 0);
492 if (sky2->autoneg == AUTONEG_DISABLE) {
493 reg = gma_read16(hw, port, GM_GP_CTRL);
494 reg |= GM_GPCR_AU_ALL_DIS;
495 gma_write16(hw, port, GM_GP_CTRL, reg);
496 gma_read16(hw, port, GM_GP_CTRL);
498 switch (sky2->speed) {
500 reg |= GM_GPCR_SPEED_1000;
503 reg |= GM_GPCR_SPEED_100;
506 if (sky2->duplex == DUPLEX_FULL)
507 reg |= GM_GPCR_DUP_FULL;
509 reg = GM_GPCR_SPEED_1000 | GM_GPCR_SPEED_100 | GM_GPCR_DUP_FULL;
511 if (!sky2->tx_pause && !sky2->rx_pause) {
512 sky2_write32(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
514 GM_GPCR_FC_TX_DIS | GM_GPCR_FC_RX_DIS | GM_GPCR_AU_FCT_DIS;
515 } else if (sky2->tx_pause && !sky2->rx_pause) {
516 /* disable Rx flow-control */
517 reg |= GM_GPCR_FC_RX_DIS | GM_GPCR_AU_FCT_DIS;
520 gma_write16(hw, port, GM_GP_CTRL, reg);
522 sky2_read16(hw, SK_REG(port, GMAC_IRQ_SRC));
524 spin_lock_bh(&hw->phy_lock);
525 sky2_phy_init(hw, port);
526 spin_unlock_bh(&hw->phy_lock);
529 reg = gma_read16(hw, port, GM_PHY_ADDR);
530 gma_write16(hw, port, GM_PHY_ADDR, reg | GM_PAR_MIB_CLR);
532 for (i = 0; i < GM_MIB_CNT_SIZE; i++)
533 gma_read16(hw, port, GM_MIB_CNT_BASE + 8 * i);
534 gma_write16(hw, port, GM_PHY_ADDR, reg);
536 /* transmit control */
537 gma_write16(hw, port, GM_TX_CTRL, TX_COL_THR(TX_COL_DEF));
539 /* receive control reg: unicast + multicast + no FCS */
540 gma_write16(hw, port, GM_RX_CTRL,
541 GM_RXCR_UCF_ENA | GM_RXCR_CRC_DIS | GM_RXCR_MCF_ENA);
543 /* transmit flow control */
544 gma_write16(hw, port, GM_TX_FLOW_CTRL, 0xffff);
546 /* transmit parameter */
547 gma_write16(hw, port, GM_TX_PARAM,
548 TX_JAM_LEN_VAL(TX_JAM_LEN_DEF) |
549 TX_JAM_IPG_VAL(TX_JAM_IPG_DEF) |
550 TX_IPG_JAM_DATA(TX_IPG_JAM_DEF) |
551 TX_BACK_OFF_LIM(TX_BOF_LIM_DEF));
553 /* serial mode register */
554 reg = DATA_BLIND_VAL(DATA_BLIND_DEF) |
555 GM_SMOD_VLAN_ENA | IPG_DATA_VAL(IPG_DATA_DEF);
557 if (hw->dev[port]->mtu > ETH_DATA_LEN)
558 reg |= GM_SMOD_JUMBO_ENA;
560 gma_write16(hw, port, GM_SERIAL_MODE, reg);
562 /* virtual address for data */
563 gma_set_addr(hw, port, GM_SRC_ADDR_2L, addr);
565 /* physical address: used for pause frames */
566 gma_set_addr(hw, port, GM_SRC_ADDR_1L, addr);
568 /* ignore counter overflows */
569 gma_write16(hw, port, GM_TX_IRQ_MSK, 0);
570 gma_write16(hw, port, GM_RX_IRQ_MSK, 0);
571 gma_write16(hw, port, GM_TR_IRQ_MSK, 0);
573 /* Configure Rx MAC FIFO */
574 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_CLR);
575 sky2_write16(hw, SK_REG(port, RX_GMF_CTRL_T),
578 /* Flush Rx MAC FIFO on any flow control or error */
579 reg = GMR_FS_ANY_ERR;
580 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev <= 1)
581 reg = 0; /* WA dev #4.115 */
583 sky2_write16(hw, SK_REG(port, RX_GMF_FL_MSK), reg);
584 /* Set threshold to 0xa (64 bytes)
585 * ASF disabled so no need to do WA dev #4.30
587 sky2_write16(hw, SK_REG(port, RX_GMF_FL_THR), RX_GMF_FL_THR_DEF);
589 /* Configure Tx MAC FIFO */
590 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_CLR);
591 sky2_write16(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_OPER_ON);
594 static void sky2_ramset(struct sky2_hw *hw, u16 q, u32 start, size_t len)
600 end = start + len - 1;
602 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_RST_CLR);
603 sky2_write32(hw, RB_ADDR(q, RB_START), start);
604 sky2_write32(hw, RB_ADDR(q, RB_END), end);
605 sky2_write32(hw, RB_ADDR(q, RB_WP), start);
606 sky2_write32(hw, RB_ADDR(q, RB_RP), start);
608 if (q == Q_R1 || q == Q_R2) {
614 /* Set thresholds on receive queue's */
615 sky2_write32(hw, RB_ADDR(q, RB_RX_UTPP), rxup);
616 sky2_write32(hw, RB_ADDR(q, RB_RX_LTPP), rxlo);
618 /* Enable store & forward on Tx queue's because
619 * Tx FIFO is only 1K on Yukon
621 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_STFWD);
624 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_OP_MD);
625 sky2_read8(hw, RB_ADDR(q, RB_CTRL));
628 /* Setup Bus Memory Interface */
629 static void sky2_qset(struct sky2_hw *hw, u16 q, u32 wm)
631 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_CLR_RESET);
632 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_OPER_INIT);
633 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_FIFO_OP_ON);
634 sky2_write32(hw, Q_ADDR(q, Q_WM), wm);
637 /* Setup prefetch unit registers. This is the interface between
638 * hardware and driver list elements
640 static inline void sky2_prefetch_init(struct sky2_hw *hw, u32 qaddr,
643 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_RST_SET);
644 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_RST_CLR);
645 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_ADDR_HI), addr >> 32);
646 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_ADDR_LO), (u32) addr);
647 sky2_write16(hw, Y2_QADDR(qaddr, PREF_UNIT_LAST_IDX), last);
648 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_OP_ON);
650 sky2_read32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL));
653 static inline struct sky2_tx_le *get_tx_le(struct sky2_port *sky2)
655 struct sky2_tx_le *le = sky2->tx_le + sky2->tx_prod;
657 sky2->tx_prod = (sky2->tx_prod + 1) % TX_RING_SIZE;
662 * This is a workaround code taken from SysKonnect sk98lin driver
663 * to deal with chip bug on Yukon EC rev 0 in the wraparound case.
665 static inline void sky2_put_idx(struct sky2_hw *hw, unsigned q,
666 u16 idx, u16 *last, u16 size)
668 if (is_ec_a1(hw) && idx < *last) {
669 u16 hwget = sky2_read16(hw, Y2_QADDR(q, PREF_UNIT_GET_IDX));
672 /* Start prefetching again */
673 sky2_write8(hw, Y2_QADDR(q, PREF_UNIT_FIFO_WM), 0xe0);
677 if (hwget == size - 1) {
678 /* set watermark to one list element */
679 sky2_write8(hw, Y2_QADDR(q, PREF_UNIT_FIFO_WM), 8);
681 /* set put index to first list element */
682 sky2_write16(hw, Y2_QADDR(q, PREF_UNIT_PUT_IDX), 0);
683 } else /* have hardware go to end of list */
684 sky2_write16(hw, Y2_QADDR(q, PREF_UNIT_PUT_IDX),
688 sky2_write16(hw, Y2_QADDR(q, PREF_UNIT_PUT_IDX), idx);
694 static inline struct sky2_rx_le *sky2_next_rx(struct sky2_port *sky2)
696 struct sky2_rx_le *le = sky2->rx_le + sky2->rx_put;
697 sky2->rx_put = (sky2->rx_put + 1) % RX_LE_SIZE;
701 /* Build description to hardware about buffer */
702 static inline void sky2_rx_add(struct sky2_port *sky2, struct ring_info *re)
704 struct sky2_rx_le *le;
705 u32 hi = (re->mapaddr >> 16) >> 16;
707 re->idx = sky2->rx_put;
708 if (sky2->rx_addr64 != hi) {
709 le = sky2_next_rx(sky2);
710 le->addr = cpu_to_le32(hi);
712 le->opcode = OP_ADDR64 | HW_OWNER;
713 sky2->rx_addr64 = hi;
716 le = sky2_next_rx(sky2);
717 le->addr = cpu_to_le32((u32) re->mapaddr);
718 le->length = cpu_to_le16(re->maplen);
720 le->opcode = OP_PACKET | HW_OWNER;
724 /* Tell chip where to start receive checksum.
725 * Actually has two checksums, but set both same to avoid possible byte
728 static void rx_set_checksum(struct sky2_port *sky2)
730 struct sky2_rx_le *le;
732 le = sky2_next_rx(sky2);
733 le->addr = (ETH_HLEN << 16) | ETH_HLEN;
735 le->opcode = OP_TCPSTART | HW_OWNER;
737 sky2_write32(sky2->hw,
738 Q_ADDR(rxqaddr[sky2->port], Q_CSR),
739 sky2->rx_csum ? BMU_ENA_RX_CHKSUM : BMU_DIS_RX_CHKSUM);
744 * The RX Stop command will not work for Yukon-2 if the BMU does not
745 * reach the end of packet and since we can't make sure that we have
746 * incoming data, we must reset the BMU while it is not doing a DMA
747 * transfer. Since it is possible that the RX path is still active,
748 * the RX RAM buffer will be stopped first, so any possible incoming
749 * data will not trigger a DMA. After the RAM buffer is stopped, the
750 * BMU is polled until any DMA in progress is ended and only then it
753 static void sky2_rx_stop(struct sky2_port *sky2)
755 struct sky2_hw *hw = sky2->hw;
756 unsigned rxq = rxqaddr[sky2->port];
759 /* disable the RAM Buffer receive queue */
760 sky2_write8(hw, RB_ADDR(rxq, RB_CTRL), RB_DIS_OP_MD);
762 for (i = 0; i < 0xffff; i++)
763 if (sky2_read8(hw, RB_ADDR(rxq, Q_RSL))
764 == sky2_read8(hw, RB_ADDR(rxq, Q_RL)))
767 printk(KERN_WARNING PFX "%s: receiver stop failed\n",
770 sky2_write32(hw, Q_ADDR(rxq, Q_CSR), BMU_RST_SET | BMU_FIFO_RST);
772 /* reset the Rx prefetch unit */
773 sky2_write32(hw, Y2_QADDR(rxq, PREF_UNIT_CTRL), PREF_UNIT_RST_SET);
776 /* Clean out receive buffer area, assumes receiver hardware stopped */
777 static void sky2_rx_clean(struct sky2_port *sky2)
781 memset(sky2->rx_le, 0, RX_LE_BYTES);
782 for (i = 0; i < sky2->rx_pending; i++) {
783 struct ring_info *re = sky2->rx_ring + i;
786 pci_unmap_single(sky2->hw->pdev,
787 re->mapaddr, re->maplen,
795 #ifdef SKY2_VLAN_TAG_USED
796 static void sky2_vlan_rx_register(struct net_device *dev, struct vlan_group *grp)
798 struct sky2_port *sky2 = netdev_priv(dev);
799 struct sky2_hw *hw = sky2->hw;
800 u16 port = sky2->port;
803 spin_lock_irqsave(&sky2->tx_lock, flags);
805 sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T), RX_VLAN_STRIP_ON);
806 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T), TX_VLAN_TAG_ON);
809 spin_unlock_irqrestore(&sky2->tx_lock, flags);
812 static void sky2_vlan_rx_kill_vid(struct net_device *dev, unsigned short vid)
814 struct sky2_port *sky2 = netdev_priv(dev);
815 struct sky2_hw *hw = sky2->hw;
816 u16 port = sky2->port;
819 spin_lock_irqsave(&sky2->tx_lock, flags);
821 sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T), RX_VLAN_STRIP_OFF);
822 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T), TX_VLAN_TAG_OFF);
824 sky2->vlgrp->vlan_devices[vid] = NULL;
826 spin_unlock_irqrestore(&sky2->tx_lock, flags);
830 #define roundup(x, y) ((((x)+((y)-1))/(y))*(y))
831 static inline unsigned rx_size(const struct sky2_port *sky2)
833 return roundup(sky2->netdev->mtu + ETH_HLEN + 4, 8);
837 * Allocate and setup receiver buffer pool.
838 * In case of 64 bit dma, there are 2X as many list elements
839 * available as ring entries
840 * and need to reserve one list element so we don't wrap around.
842 * It appears the hardware has a bug in the FIFO logic that
843 * cause it to hang if the FIFO gets overrun and the receive buffer
844 * is not aligned. This means we can't use skb_reserve to align
847 static int sky2_rx_start(struct sky2_port *sky2)
849 struct sky2_hw *hw = sky2->hw;
850 unsigned size = rx_size(sky2);
851 unsigned rxq = rxqaddr[sky2->port];
854 sky2->rx_put = sky2->rx_next = 0;
855 sky2_qset(hw, rxq, is_pciex(hw) ? 0x80 : 0x600);
856 sky2_prefetch_init(hw, rxq, sky2->rx_le_map, RX_LE_SIZE - 1);
858 rx_set_checksum(sky2);
859 for (i = 0; i < sky2->rx_pending; i++) {
860 struct ring_info *re = sky2->rx_ring + i;
862 re->skb = dev_alloc_skb(size);
866 re->mapaddr = pci_map_single(hw->pdev, re->skb->data,
867 size, PCI_DMA_FROMDEVICE);
869 sky2_rx_add(sky2, re);
872 /* Tell chip about available buffers */
873 sky2_write16(hw, Y2_QADDR(rxq, PREF_UNIT_PUT_IDX), sky2->rx_put);
874 sky2->rx_last_put = sky2_read16(hw, Y2_QADDR(rxq, PREF_UNIT_PUT_IDX));
881 /* Bring up network interface. */
882 static int sky2_up(struct net_device *dev)
884 struct sky2_port *sky2 = netdev_priv(dev);
885 struct sky2_hw *hw = sky2->hw;
886 unsigned port = sky2->port;
887 u32 ramsize, rxspace;
890 if (netif_msg_ifup(sky2))
891 printk(KERN_INFO PFX "%s: enabling interface\n", dev->name);
893 /* must be power of 2 */
894 sky2->tx_le = pci_alloc_consistent(hw->pdev,
896 sizeof(struct sky2_tx_le),
901 sky2->tx_ring = kzalloc(TX_RING_SIZE * sizeof(struct ring_info),
905 sky2->tx_prod = sky2->tx_cons = 0;
907 sky2->rx_le = pci_alloc_consistent(hw->pdev, RX_LE_BYTES,
911 memset(sky2->rx_le, 0, RX_LE_BYTES);
913 sky2->rx_ring = kzalloc(sky2->rx_pending * sizeof(struct ring_info),
918 sky2_mac_init(hw, port);
920 /* Configure RAM buffers */
921 if (hw->chip_id == CHIP_ID_YUKON_FE ||
922 (hw->chip_id == CHIP_ID_YUKON_EC && hw->chip_rev == 2))
925 u8 e0 = sky2_read8(hw, B2_E_0);
926 ramsize = (e0 == 0) ? (128 * 1024) : (e0 * 4096);
930 rxspace = (2 * ramsize) / 3;
931 sky2_ramset(hw, rxqaddr[port], 0, rxspace);
932 sky2_ramset(hw, txqaddr[port], rxspace, ramsize - rxspace);
934 /* Make sure SyncQ is disabled */
935 sky2_write8(hw, RB_ADDR(port == 0 ? Q_XS1 : Q_XS2, RB_CTRL),
938 sky2_qset(hw, txqaddr[port], 0x600);
939 sky2_prefetch_init(hw, txqaddr[port], sky2->tx_le_map,
942 err = sky2_rx_start(sky2);
946 /* Enable interrupts from phy/mac for port */
947 hw->intr_mask |= (port == 0) ? Y2_IS_PORT_1 : Y2_IS_PORT_2;
948 sky2_write32(hw, B0_IMSK, hw->intr_mask);
953 pci_free_consistent(hw->pdev, RX_LE_BYTES,
954 sky2->rx_le, sky2->rx_le_map);
956 pci_free_consistent(hw->pdev,
957 TX_RING_SIZE * sizeof(struct sky2_tx_le),
958 sky2->tx_le, sky2->tx_le_map);
960 kfree(sky2->tx_ring);
962 kfree(sky2->rx_ring);
967 /* Modular subtraction in ring */
968 static inline int tx_dist(unsigned tail, unsigned head)
970 return (head >= tail ? head : head + TX_RING_SIZE) - tail;
973 /* Number of list elements available for next tx */
974 static inline int tx_avail(const struct sky2_port *sky2)
976 return sky2->tx_pending - tx_dist(sky2->tx_cons, sky2->tx_prod);
979 /* Estimate of number of transmit list elements required */
980 static inline unsigned tx_le_req(const struct sk_buff *skb)
984 count = sizeof(dma_addr_t) / sizeof(u32);
985 count += skb_shinfo(skb)->nr_frags * count;
987 if (skb_shinfo(skb)->tso_size)
997 * Put one packet in ring for transmit.
998 * A single packet can generate multiple list elements, and
999 * the number of ring elements will probably be less than the number
1000 * of list elements used.
1002 static int sky2_xmit_frame(struct sk_buff *skb, struct net_device *dev)
1004 struct sky2_port *sky2 = netdev_priv(dev);
1005 struct sky2_hw *hw = sky2->hw;
1006 struct sky2_tx_le *le = NULL;
1007 struct ring_info *re;
1008 unsigned long flags;
1015 local_irq_save(flags);
1016 if (!spin_trylock(&sky2->tx_lock)) {
1017 local_irq_restore(flags);
1018 return NETDEV_TX_LOCKED;
1021 if (unlikely(tx_avail(sky2) < tx_le_req(skb))) {
1022 netif_stop_queue(dev);
1023 spin_unlock_irqrestore(&sky2->tx_lock, flags);
1025 printk(KERN_WARNING PFX "%s: ring full when queue awake!\n",
1027 return NETDEV_TX_BUSY;
1030 if (unlikely(netif_msg_tx_queued(sky2)))
1031 printk(KERN_DEBUG "%s: tx queued, slot %u, len %d\n",
1032 dev->name, sky2->tx_prod, skb->len);
1034 len = skb_headlen(skb);
1035 mapping = pci_map_single(hw->pdev, skb->data, len, PCI_DMA_TODEVICE);
1036 addr64 = (mapping >> 16) >> 16;
1038 re = sky2->tx_ring + sky2->tx_prod;
1040 /* Send high bits if changed */
1041 if (addr64 != sky2->tx_addr64) {
1042 le = get_tx_le(sky2);
1043 le->tx.addr = cpu_to_le32(addr64);
1045 le->opcode = OP_ADDR64 | HW_OWNER;
1046 sky2->tx_addr64 = addr64;
1049 /* Check for TCP Segmentation Offload */
1050 mss = skb_shinfo(skb)->tso_size;
1052 /* just drop the packet if non-linear expansion fails */
1053 if (skb_header_cloned(skb) &&
1054 pskb_expand_head(skb, 0, 0, GFP_ATOMIC)) {
1055 dev_kfree_skb_any(skb);
1059 mss += ((skb->h.th->doff - 5) * 4); /* TCP options */
1060 mss += (skb->nh.iph->ihl * 4) + sizeof(struct tcphdr);
1064 if (mss != sky2->tx_last_mss) {
1065 le = get_tx_le(sky2);
1066 le->tx.tso.size = cpu_to_le16(mss);
1067 le->tx.tso.rsvd = 0;
1068 le->opcode = OP_LRGLEN | HW_OWNER;
1070 sky2->tx_last_mss = mss;
1074 #ifdef SKY2_VLAN_TAG_USED
1075 /* Add VLAN tag, can piggyback on LRGLEN or ADDR64 */
1076 if (sky2->vlgrp && vlan_tx_tag_present(skb)) {
1078 le = get_tx_le(sky2);
1080 le->opcode = OP_VLAN|HW_OWNER;
1083 le->opcode |= OP_VLAN;
1084 le->length = cpu_to_be16(vlan_tx_tag_get(skb));
1089 /* Handle TCP checksum offload */
1090 if (skb->ip_summed == CHECKSUM_HW) {
1091 u16 hdr = skb->h.raw - skb->data;
1092 u16 offset = hdr + skb->csum;
1094 ctrl = CALSUM | WR_SUM | INIT_SUM | LOCK_SUM;
1095 if (skb->nh.iph->protocol == IPPROTO_UDP)
1098 le = get_tx_le(sky2);
1099 le->tx.csum.start = cpu_to_le16(hdr);
1100 le->tx.csum.offset = cpu_to_le16(offset);
1101 le->length = 0; /* initial checksum value */
1102 le->ctrl = 1; /* one packet */
1103 le->opcode = OP_TCPLISW | HW_OWNER;
1106 le = get_tx_le(sky2);
1107 le->tx.addr = cpu_to_le32((u32) mapping);
1108 le->length = cpu_to_le16(len);
1110 le->opcode = mss ? (OP_LARGESEND | HW_OWNER) : (OP_PACKET | HW_OWNER);
1112 /* Record the transmit mapping info */
1114 re->mapaddr = mapping;
1117 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
1118 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
1119 struct ring_info *fre;
1121 mapping = pci_map_page(hw->pdev, frag->page, frag->page_offset,
1122 frag->size, PCI_DMA_TODEVICE);
1123 addr64 = (mapping >> 16) >> 16;
1124 if (addr64 != sky2->tx_addr64) {
1125 le = get_tx_le(sky2);
1126 le->tx.addr = cpu_to_le32(addr64);
1128 le->opcode = OP_ADDR64 | HW_OWNER;
1129 sky2->tx_addr64 = addr64;
1132 le = get_tx_le(sky2);
1133 le->tx.addr = cpu_to_le32((u32) mapping);
1134 le->length = cpu_to_le16(frag->size);
1136 le->opcode = OP_BUFFER | HW_OWNER;
1139 + ((re - sky2->tx_ring) + i + 1) % TX_RING_SIZE;
1141 fre->mapaddr = mapping;
1142 fre->maplen = frag->size;
1144 re->idx = sky2->tx_prod;
1147 sky2_put_idx(hw, txqaddr[sky2->port], sky2->tx_prod,
1148 &sky2->tx_last_put, TX_RING_SIZE);
1150 if (tx_avail(sky2) < MAX_SKB_TX_LE + 1)
1151 netif_stop_queue(dev);
1155 spin_unlock_irqrestore(&sky2->tx_lock, flags);
1157 dev->trans_start = jiffies;
1158 return NETDEV_TX_OK;
1162 * Free ring elements from starting at tx_cons until "done"
1164 * NB: the hardware will tell us about partial completion of multi-part
1165 * buffers; these are deferred until completion.
1167 static void sky2_tx_complete(struct sky2_port *sky2, u16 done)
1169 struct net_device *dev = sky2->netdev;
1172 if (unlikely(netif_msg_tx_done(sky2)))
1173 printk(KERN_DEBUG "%s: tx done, up to %u\n",
1176 spin_lock(&sky2->tx_lock);
1178 while (sky2->tx_cons != done) {
1179 struct ring_info *re = sky2->tx_ring + sky2->tx_cons;
1180 struct sk_buff *skb;
1182 /* Check for partial status */
1183 if (tx_dist(sky2->tx_cons, done)
1184 < tx_dist(sky2->tx_cons, re->idx))
1188 pci_unmap_single(sky2->hw->pdev,
1189 re->mapaddr, re->maplen, PCI_DMA_TODEVICE);
1191 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
1192 struct ring_info *fre;
1194 sky2->tx_ring + (sky2->tx_cons + i +
1196 pci_unmap_page(sky2->hw->pdev, fre->mapaddr,
1197 fre->maplen, PCI_DMA_TODEVICE);
1200 dev_kfree_skb_any(skb);
1202 sky2->tx_cons = re->idx;
1206 if (netif_queue_stopped(dev) && tx_avail(sky2) > MAX_SKB_TX_LE)
1207 netif_wake_queue(dev);
1208 spin_unlock(&sky2->tx_lock);
1211 /* Cleanup all untransmitted buffers, assume transmitter not running */
1212 static inline void sky2_tx_clean(struct sky2_port *sky2)
1214 sky2_tx_complete(sky2, sky2->tx_prod);
1217 /* Network shutdown */
1218 static int sky2_down(struct net_device *dev)
1220 struct sky2_port *sky2 = netdev_priv(dev);
1221 struct sky2_hw *hw = sky2->hw;
1222 unsigned port = sky2->port;
1225 if (netif_msg_ifdown(sky2))
1226 printk(KERN_INFO PFX "%s: disabling interface\n", dev->name);
1228 netif_stop_queue(dev);
1230 sky2_phy_reset(hw, port);
1232 /* Stop transmitter */
1233 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), BMU_STOP);
1234 sky2_read32(hw, Q_ADDR(txqaddr[port], Q_CSR));
1236 sky2_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL),
1237 RB_RST_SET | RB_DIS_OP_MD);
1239 ctrl = gma_read16(hw, port, GM_GP_CTRL);
1240 ctrl &= ~(GM_GPCR_TX_ENA | GM_GPCR_RX_ENA);
1241 gma_write16(hw, port, GM_GP_CTRL, ctrl);
1243 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET);
1245 /* Workaround shared GMAC reset */
1246 if (!(hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0
1247 && port == 0 && hw->dev[1] && netif_running(hw->dev[1])))
1248 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_SET);
1250 /* Disable Force Sync bit and Enable Alloc bit */
1251 sky2_write8(hw, SK_REG(port, TXA_CTRL),
1252 TXA_DIS_FSYNC | TXA_DIS_ALLOC | TXA_STOP_RC);
1254 /* Stop Interval Timer and Limit Counter of Tx Arbiter */
1255 sky2_write32(hw, SK_REG(port, TXA_ITI_INI), 0L);
1256 sky2_write32(hw, SK_REG(port, TXA_LIM_INI), 0L);
1258 /* Reset the PCI FIFO of the async Tx queue */
1259 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR),
1260 BMU_RST_SET | BMU_FIFO_RST);
1262 /* Reset the Tx prefetch units */
1263 sky2_write32(hw, Y2_QADDR(txqaddr[port], PREF_UNIT_CTRL),
1266 sky2_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL), RB_RST_SET);
1270 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_SET);
1271 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_SET);
1273 /* turn off LED's */
1274 sky2_write16(hw, B0_Y2LED, LED_STAT_OFF);
1276 sky2_tx_clean(sky2);
1277 sky2_rx_clean(sky2);
1279 pci_free_consistent(hw->pdev, RX_LE_BYTES,
1280 sky2->rx_le, sky2->rx_le_map);
1281 kfree(sky2->rx_ring);
1283 pci_free_consistent(hw->pdev,
1284 TX_RING_SIZE * sizeof(struct sky2_tx_le),
1285 sky2->tx_le, sky2->tx_le_map);
1286 kfree(sky2->tx_ring);
1291 static u16 sky2_phy_speed(const struct sky2_hw *hw, u16 aux)
1296 if (hw->chip_id == CHIP_ID_YUKON_FE)
1297 return (aux & PHY_M_PS_SPEED_100) ? SPEED_100 : SPEED_10;
1299 switch (aux & PHY_M_PS_SPEED_MSK) {
1300 case PHY_M_PS_SPEED_1000:
1302 case PHY_M_PS_SPEED_100:
1309 static void sky2_link_up(struct sky2_port *sky2)
1311 struct sky2_hw *hw = sky2->hw;
1312 unsigned port = sky2->port;
1315 /* disable Rx GMAC FIFO flush mode */
1316 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RX_F_FL_OFF);
1318 /* Enable Transmit FIFO Underrun */
1319 sky2_write8(hw, SK_REG(port, GMAC_IRQ_MSK), GMAC_DEF_MSK);
1321 reg = gma_read16(hw, port, GM_GP_CTRL);
1322 if (sky2->duplex == DUPLEX_FULL || sky2->autoneg == AUTONEG_ENABLE)
1323 reg |= GM_GPCR_DUP_FULL;
1326 reg |= GM_GPCR_RX_ENA | GM_GPCR_TX_ENA;
1327 gma_write16(hw, port, GM_GP_CTRL, reg);
1328 gma_read16(hw, port, GM_GP_CTRL);
1330 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_DEF_MSK);
1332 netif_carrier_on(sky2->netdev);
1333 netif_wake_queue(sky2->netdev);
1335 /* Turn on link LED */
1336 sky2_write8(hw, SK_REG(port, LNK_LED_REG),
1337 LINKLED_ON | LINKLED_BLINK_OFF | LINKLED_LINKSYNC_OFF);
1339 if (hw->chip_id == CHIP_ID_YUKON_XL) {
1340 u16 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
1342 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
1343 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, PHY_M_LEDC_LOS_CTRL(1) | /* LINK/ACT */
1344 PHY_M_LEDC_INIT_CTRL(sky2->speed ==
1346 PHY_M_LEDC_STA1_CTRL(sky2->speed ==
1347 SPEED_100 ? 7 : 0) |
1348 PHY_M_LEDC_STA0_CTRL(sky2->speed ==
1349 SPEED_1000 ? 7 : 0));
1350 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
1353 if (netif_msg_link(sky2))
1354 printk(KERN_INFO PFX
1355 "%s: Link is up at %d Mbps, %s duplex, flow control %s\n",
1356 sky2->netdev->name, sky2->speed,
1357 sky2->duplex == DUPLEX_FULL ? "full" : "half",
1358 (sky2->tx_pause && sky2->rx_pause) ? "both" :
1359 sky2->tx_pause ? "tx" : sky2->rx_pause ? "rx" : "none");
1362 static void sky2_link_down(struct sky2_port *sky2)
1364 struct sky2_hw *hw = sky2->hw;
1365 unsigned port = sky2->port;
1368 gm_phy_write(hw, port, PHY_MARV_INT_MASK, 0);
1370 reg = gma_read16(hw, port, GM_GP_CTRL);
1371 reg &= ~(GM_GPCR_RX_ENA | GM_GPCR_TX_ENA);
1372 gma_write16(hw, port, GM_GP_CTRL, reg);
1373 gma_read16(hw, port, GM_GP_CTRL); /* PCI post */
1375 if (sky2->rx_pause && !sky2->tx_pause) {
1376 /* restore Asymmetric Pause bit */
1377 gm_phy_write(hw, port, PHY_MARV_AUNE_ADV,
1378 gm_phy_read(hw, port, PHY_MARV_AUNE_ADV)
1382 sky2_phy_reset(hw, port);
1384 netif_carrier_off(sky2->netdev);
1385 netif_stop_queue(sky2->netdev);
1387 /* Turn on link LED */
1388 sky2_write8(hw, SK_REG(port, LNK_LED_REG), LINKLED_OFF);
1390 if (netif_msg_link(sky2))
1391 printk(KERN_INFO PFX "%s: Link is down.\n", sky2->netdev->name);
1392 sky2_phy_init(hw, port);
1395 static int sky2_autoneg_done(struct sky2_port *sky2, u16 aux)
1397 struct sky2_hw *hw = sky2->hw;
1398 unsigned port = sky2->port;
1401 lpa = gm_phy_read(hw, port, PHY_MARV_AUNE_LP);
1403 if (lpa & PHY_M_AN_RF) {
1404 printk(KERN_ERR PFX "%s: remote fault", sky2->netdev->name);
1408 if (hw->chip_id != CHIP_ID_YUKON_FE &&
1409 gm_phy_read(hw, port, PHY_MARV_1000T_STAT) & PHY_B_1000S_MSF) {
1410 printk(KERN_ERR PFX "%s: master/slave fault",
1411 sky2->netdev->name);
1415 if (!(aux & PHY_M_PS_SPDUP_RES)) {
1416 printk(KERN_ERR PFX "%s: speed/duplex mismatch",
1417 sky2->netdev->name);
1421 sky2->duplex = (aux & PHY_M_PS_FULL_DUP) ? DUPLEX_FULL : DUPLEX_HALF;
1423 sky2->speed = sky2_phy_speed(hw, aux);
1425 /* Pause bits are offset (9..8) */
1426 if (hw->chip_id == CHIP_ID_YUKON_XL)
1429 sky2->rx_pause = (aux & PHY_M_PS_RX_P_EN) != 0;
1430 sky2->tx_pause = (aux & PHY_M_PS_TX_P_EN) != 0;
1432 if ((sky2->tx_pause || sky2->rx_pause)
1433 && !(sky2->speed < SPEED_1000 && sky2->duplex == DUPLEX_HALF))
1434 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON);
1436 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
1442 * Interrupt from PHY are handled in tasklet (soft irq)
1443 * because accessing phy registers requires spin wait which might
1444 * cause excess interrupt latency.
1446 static void sky2_phy_task(unsigned long data)
1448 struct sky2_port *sky2 = (struct sky2_port *)data;
1449 struct sky2_hw *hw = sky2->hw;
1450 u16 istatus, phystat;
1452 spin_lock(&hw->phy_lock);
1453 istatus = gm_phy_read(hw, sky2->port, PHY_MARV_INT_STAT);
1454 phystat = gm_phy_read(hw, sky2->port, PHY_MARV_PHY_STAT);
1456 if (netif_msg_intr(sky2))
1457 printk(KERN_INFO PFX "%s: phy interrupt status 0x%x 0x%x\n",
1458 sky2->netdev->name, istatus, phystat);
1460 if (istatus & PHY_M_IS_AN_COMPL) {
1461 if (sky2_autoneg_done(sky2, phystat) == 0)
1466 if (istatus & PHY_M_IS_LSP_CHANGE)
1467 sky2->speed = sky2_phy_speed(hw, phystat);
1469 if (istatus & PHY_M_IS_DUP_CHANGE)
1471 (phystat & PHY_M_PS_FULL_DUP) ? DUPLEX_FULL : DUPLEX_HALF;
1473 if (istatus & PHY_M_IS_LST_CHANGE) {
1474 if (phystat & PHY_M_PS_LINK_UP)
1477 sky2_link_down(sky2);
1480 spin_unlock(&hw->phy_lock);
1482 local_irq_disable();
1483 hw->intr_mask |= (sky2->port == 0) ? Y2_IS_IRQ_PHY1 : Y2_IS_IRQ_PHY2;
1484 sky2_write32(hw, B0_IMSK, hw->intr_mask);
1488 static void sky2_tx_timeout(struct net_device *dev)
1490 struct sky2_port *sky2 = netdev_priv(dev);
1492 if (netif_msg_timer(sky2))
1493 printk(KERN_ERR PFX "%s: tx timeout\n", dev->name);
1495 sky2_write32(sky2->hw, Q_ADDR(txqaddr[sky2->port], Q_CSR), BMU_STOP);
1496 sky2_read32(sky2->hw, Q_ADDR(txqaddr[sky2->port], Q_CSR));
1498 sky2_tx_clean(sky2);
1501 static int sky2_change_mtu(struct net_device *dev, int new_mtu)
1503 struct sky2_port *sky2 = netdev_priv(dev);
1504 struct sky2_hw *hw = sky2->hw;
1508 if (new_mtu < ETH_ZLEN || new_mtu > ETH_JUMBO_MTU)
1511 if (!netif_running(dev)) {
1516 local_irq_disable();
1517 sky2_write32(hw, B0_IMSK, 0);
1519 ctl = gma_read16(hw, sky2->port, GM_GP_CTRL);
1520 gma_write16(hw, sky2->port, GM_GP_CTRL, ctl & ~GM_GPCR_RX_ENA);
1522 sky2_rx_clean(sky2);
1525 mode = DATA_BLIND_VAL(DATA_BLIND_DEF) |
1526 GM_SMOD_VLAN_ENA | IPG_DATA_VAL(IPG_DATA_DEF);
1528 if (dev->mtu > ETH_DATA_LEN)
1529 mode |= GM_SMOD_JUMBO_ENA;
1531 gma_write16(hw, sky2->port, GM_SERIAL_MODE, mode);
1533 sky2_write8(hw, RB_ADDR(rxqaddr[sky2->port], RB_CTRL), RB_ENA_OP_MD);
1535 err = sky2_rx_start(sky2);
1536 gma_write16(hw, sky2->port, GM_GP_CTRL, ctl);
1538 sky2_write32(hw, B0_IMSK, hw->intr_mask);
1539 sky2_read32(hw, B0_IMSK);
1545 * Receive one packet.
1546 * For small packets or errors, just reuse existing skb.
1547 * For larger packets, get new buffer.
1549 static struct sk_buff *sky2_receive(struct sky2_port *sky2,
1550 u16 length, u32 status)
1552 struct ring_info *re = sky2->rx_ring + sky2->rx_next;
1553 struct sk_buff *skb = NULL;
1554 struct net_device *dev;
1555 const unsigned int bufsize = rx_size(sky2);
1557 if (unlikely(netif_msg_rx_status(sky2)))
1558 printk(KERN_DEBUG PFX "%s: rx slot %u status 0x%x len %d\n",
1559 sky2->netdev->name, sky2->rx_next, status, length);
1561 sky2->rx_next = (sky2->rx_next + 1) % sky2->rx_pending;
1563 if (!(status & GMR_FS_RX_OK) || (status & GMR_FS_ANY_ERR))
1566 if (length < RX_COPY_THRESHOLD) {
1567 skb = alloc_skb(length + 2, GFP_ATOMIC);
1571 skb_reserve(skb, 2);
1572 pci_dma_sync_single_for_cpu(sky2->hw->pdev, re->mapaddr,
1573 length, PCI_DMA_FROMDEVICE);
1574 memcpy(skb->data, re->skb->data, length);
1575 skb->ip_summed = re->skb->ip_summed;
1576 skb->csum = re->skb->csum;
1577 pci_dma_sync_single_for_device(sky2->hw->pdev, re->mapaddr,
1578 length, PCI_DMA_FROMDEVICE);
1580 struct sk_buff *nskb;
1582 nskb = dev_alloc_skb(bufsize);
1588 pci_unmap_single(sky2->hw->pdev, re->mapaddr,
1589 re->maplen, PCI_DMA_FROMDEVICE);
1590 prefetch(skb->data);
1592 re->mapaddr = pci_map_single(sky2->hw->pdev, nskb->data,
1593 bufsize, PCI_DMA_FROMDEVICE);
1594 re->maplen = bufsize;
1597 skb_put(skb, length);
1600 skb->protocol = eth_type_trans(skb, dev);
1601 dev->last_rx = jiffies;
1604 re->skb->ip_summed = CHECKSUM_NONE;
1605 sky2_rx_add(sky2, re);
1607 /* Tell receiver about new buffers. */
1608 sky2_put_idx(sky2->hw, rxqaddr[sky2->port], sky2->rx_put,
1609 &sky2->rx_last_put, RX_LE_SIZE);
1614 if (status & GMR_FS_GOOD_FC)
1617 if (netif_msg_rx_err(sky2))
1618 printk(KERN_INFO PFX "%s: rx error, status 0x%x length %d\n",
1619 sky2->netdev->name, status, length);
1621 if (status & (GMR_FS_LONG_ERR | GMR_FS_UN_SIZE))
1622 sky2->net_stats.rx_length_errors++;
1623 if (status & GMR_FS_FRAGMENT)
1624 sky2->net_stats.rx_frame_errors++;
1625 if (status & GMR_FS_CRC_ERR)
1626 sky2->net_stats.rx_crc_errors++;
1627 if (status & GMR_FS_RX_FF_OV)
1628 sky2->net_stats.rx_fifo_errors++;
1633 /* Transmit ring index in reported status block is encoded as:
1635 * | TXS2 | TXA2 | TXS1 | TXA1
1637 static inline u16 tx_index(u8 port, u32 status, u16 len)
1640 return status & 0xfff;
1642 return ((status >> 24) & 0xff) | (len & 0xf) << 8;
1646 * Both ports share the same status interrupt, therefore there is only
1649 static int sky2_poll(struct net_device *dev0, int *budget)
1651 struct sky2_hw *hw = ((struct sky2_port *) netdev_priv(dev0))->hw;
1652 unsigned int to_do = min(dev0->quota, *budget);
1653 unsigned int work_done = 0;
1656 hwidx = sky2_read16(hw, STAT_PUT_IDX);
1657 BUG_ON(hwidx >= STATUS_RING_SIZE);
1661 struct sky2_status_le *le = hw->st_le + hw->st_idx;
1662 struct sky2_port *sky2;
1663 struct sk_buff *skb;
1667 /* Are we done yet? */
1668 if (hw->st_idx == hwidx) {
1669 sky2_write32(hw, STAT_CTRL, SC_STAT_CLR_IRQ);
1670 hwidx = sky2_read16(hw, STAT_PUT_IDX);
1671 if (hwidx == hw->st_idx)
1675 hw->st_idx = (hw->st_idx + 1) % STATUS_RING_SIZE;
1676 prefetch(&hw->st_le[hw->st_idx]);
1678 BUG_ON(le->link >= hw->ports || !hw->dev[le->link]);
1680 sky2 = netdev_priv(hw->dev[le->link]);
1681 status = le32_to_cpu(le->status);
1682 length = le16_to_cpu(le->length);
1684 switch (le->opcode & ~HW_OWNER) {
1686 skb = sky2_receive(sky2, length, status);
1689 #ifdef SKY2_VLAN_TAG_USED
1690 if (sky2->vlgrp && (status & GMR_FS_VLAN)) {
1691 vlan_hwaccel_receive_skb(skb,
1693 be16_to_cpu(sky2->rx_tag));
1696 netif_receive_skb(skb);
1700 #ifdef SKY2_VLAN_TAG_USED
1702 sky2->rx_tag = length;
1706 sky2->rx_tag = length;
1710 skb = sky2->rx_ring[sky2->rx_next].skb;
1711 skb->ip_summed = CHECKSUM_HW;
1712 skb->csum = le16_to_cpu(status);
1716 sky2_tx_complete(sky2,
1717 tx_index(sky2->port, status, length));
1721 if (net_ratelimit())
1722 printk(KERN_WARNING PFX
1723 "unknown status opcode 0x%x\n",
1728 le->opcode = 0; /* paranoia */
1729 } while (work_done < to_do);
1733 *budget -= work_done;
1734 dev0->quota -= work_done;
1735 if (work_done < to_do) {
1737 * Another chip workaround, need to restart TX timer if status
1738 * LE was handled. WA_DEV_43_418
1741 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_STOP);
1742 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_START);
1745 netif_rx_complete(dev0);
1746 hw->intr_mask |= Y2_IS_STAT_BMU;
1747 sky2_write32(hw, B0_IMSK, hw->intr_mask);
1748 sky2_read32(hw, B0_IMSK);
1751 return work_done >= to_do;
1755 static void sky2_hw_error(struct sky2_hw *hw, unsigned port, u32 status)
1757 struct net_device *dev = hw->dev[port];
1759 printk(KERN_INFO PFX "%s: hw error interrupt status 0x%x\n",
1762 if (status & Y2_IS_PAR_RD1) {
1763 printk(KERN_ERR PFX "%s: ram data read parity error\n",
1766 sky2_write16(hw, RAM_BUFFER(port, B3_RI_CTRL), RI_CLR_RD_PERR);
1769 if (status & Y2_IS_PAR_WR1) {
1770 printk(KERN_ERR PFX "%s: ram data write parity error\n",
1773 sky2_write16(hw, RAM_BUFFER(port, B3_RI_CTRL), RI_CLR_WR_PERR);
1776 if (status & Y2_IS_PAR_MAC1) {
1777 printk(KERN_ERR PFX "%s: MAC parity error\n", dev->name);
1778 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_CLI_TX_PE);
1781 if (status & Y2_IS_PAR_RX1) {
1782 printk(KERN_ERR PFX "%s: RX parity error\n", dev->name);
1783 sky2_write32(hw, Q_ADDR(rxqaddr[port], Q_CSR), BMU_CLR_IRQ_PAR);
1786 if (status & Y2_IS_TCP_TXA1) {
1787 printk(KERN_ERR PFX "%s: TCP segmentation error\n", dev->name);
1788 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), BMU_CLR_IRQ_TCP);
1792 static void sky2_hw_intr(struct sky2_hw *hw)
1794 u32 status = sky2_read32(hw, B0_HWE_ISRC);
1796 if (status & Y2_IS_TIST_OV)
1797 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ);
1799 if (status & (Y2_IS_MST_ERR | Y2_IS_IRQ_STAT)) {
1802 pci_read_config_word(hw->pdev, PCI_STATUS, &pci_err);
1803 printk(KERN_ERR PFX "%s: pci hw error (0x%x)\n",
1804 pci_name(hw->pdev), pci_err);
1806 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
1807 pci_write_config_word(hw->pdev, PCI_STATUS,
1808 pci_err | PCI_STATUS_ERROR_BITS);
1809 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
1812 if (status & Y2_IS_PCI_EXP) {
1813 /* PCI-Express uncorrectable Error occurred */
1816 pci_read_config_dword(hw->pdev, PEX_UNC_ERR_STAT, &pex_err);
1818 printk(KERN_ERR PFX "%s: pci express error (0x%x)\n",
1819 pci_name(hw->pdev), pex_err);
1821 /* clear the interrupt */
1822 sky2_write32(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
1823 pci_write_config_dword(hw->pdev, PEX_UNC_ERR_STAT,
1825 sky2_write32(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
1827 if (pex_err & PEX_FATAL_ERRORS) {
1828 u32 hwmsk = sky2_read32(hw, B0_HWE_IMSK);
1829 hwmsk &= ~Y2_IS_PCI_EXP;
1830 sky2_write32(hw, B0_HWE_IMSK, hwmsk);
1834 if (status & Y2_HWE_L1_MASK)
1835 sky2_hw_error(hw, 0, status);
1837 if (status & Y2_HWE_L1_MASK)
1838 sky2_hw_error(hw, 1, status);
1841 static void sky2_mac_intr(struct sky2_hw *hw, unsigned port)
1843 struct net_device *dev = hw->dev[port];
1844 struct sky2_port *sky2 = netdev_priv(dev);
1845 u8 status = sky2_read8(hw, SK_REG(port, GMAC_IRQ_SRC));
1847 if (netif_msg_intr(sky2))
1848 printk(KERN_INFO PFX "%s: mac interrupt status 0x%x\n",
1851 if (status & GM_IS_RX_FF_OR) {
1852 ++sky2->net_stats.rx_fifo_errors;
1853 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_CLI_RX_FO);
1856 if (status & GM_IS_TX_FF_UR) {
1857 ++sky2->net_stats.tx_fifo_errors;
1858 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_CLI_TX_FU);
1862 static void sky2_phy_intr(struct sky2_hw *hw, unsigned port)
1864 struct net_device *dev = hw->dev[port];
1865 struct sky2_port *sky2 = netdev_priv(dev);
1867 hw->intr_mask &= ~(port == 0 ? Y2_IS_IRQ_PHY1 : Y2_IS_IRQ_PHY2);
1868 sky2_write32(hw, B0_IMSK, hw->intr_mask);
1869 tasklet_schedule(&sky2->phy_task);
1872 static irqreturn_t sky2_intr(int irq, void *dev_id, struct pt_regs *regs)
1874 struct sky2_hw *hw = dev_id;
1875 struct net_device *dev0 = hw->dev[0];
1878 status = sky2_read32(hw, B0_Y2_SP_ISRC2);
1879 if (status == 0 || status == ~0)
1882 if (status & Y2_IS_HW_ERR)
1885 /* Do NAPI for Rx and Tx status */
1886 if (status & Y2_IS_STAT_BMU) {
1887 hw->intr_mask &= ~Y2_IS_STAT_BMU;
1888 sky2_write32(hw, B0_IMSK, hw->intr_mask);
1889 prefetch(&hw->st_le[hw->st_idx]);
1891 if (netif_rx_schedule_test(dev0))
1892 __netif_rx_schedule(dev0);
1895 if (status & Y2_IS_IRQ_PHY1)
1896 sky2_phy_intr(hw, 0);
1898 if (status & Y2_IS_IRQ_PHY2)
1899 sky2_phy_intr(hw, 1);
1901 if (status & Y2_IS_IRQ_MAC1)
1902 sky2_mac_intr(hw, 0);
1904 if (status & Y2_IS_IRQ_MAC2)
1905 sky2_mac_intr(hw, 1);
1907 sky2_write32(hw, B0_Y2_SP_ICR, 2);
1909 sky2_read32(hw, B0_IMSK);
1914 #ifdef CONFIG_NET_POLL_CONTROLLER
1915 static void sky2_netpoll(struct net_device *dev)
1917 struct sky2_port *sky2 = netdev_priv(dev);
1919 sky2_intr(sky2->hw->pdev->irq, sky2->hw, NULL);
1923 /* Chip internal frequency for clock calculations */
1924 static inline u32 sky2_khz(const struct sky2_hw *hw)
1926 switch (hw->chip_id) {
1927 case CHIP_ID_YUKON_EC:
1928 return 125000; /* 125 Mhz */
1929 case CHIP_ID_YUKON_FE:
1930 return 100000; /* 100 Mhz */
1931 default: /* YUKON_XL */
1932 return 156000; /* 156 Mhz */
1936 static inline u32 sky2_ms2clk(const struct sky2_hw *hw, u32 ms)
1938 return sky2_khz(hw) * ms;
1941 static inline u32 sky2_us2clk(const struct sky2_hw *hw, u32 us)
1943 return (sky2_khz(hw) * us) / 1000;
1946 static int sky2_reset(struct sky2_hw *hw)
1953 ctst = sky2_read32(hw, B0_CTST);
1955 sky2_write8(hw, B0_CTST, CS_RST_CLR);
1956 hw->chip_id = sky2_read8(hw, B2_CHIP_ID);
1957 if (hw->chip_id < CHIP_ID_YUKON_XL || hw->chip_id > CHIP_ID_YUKON_FE) {
1958 printk(KERN_ERR PFX "%s: unsupported chip type 0x%x\n",
1959 pci_name(hw->pdev), hw->chip_id);
1963 /* ring for status responses */
1964 hw->st_le = pci_alloc_consistent(hw->pdev, STATUS_LE_BYTES,
1970 if (hw->chip_id <= CHIP_ID_YUKON_EC) {
1971 sky2_write8(hw, B28_Y2_ASF_STAT_CMD, Y2_ASF_RESET);
1972 sky2_write16(hw, B0_CTST, Y2_ASF_DISABLE);
1976 sky2_write8(hw, B0_CTST, CS_RST_SET);
1977 sky2_write8(hw, B0_CTST, CS_RST_CLR);
1979 /* clear PCI errors, if any */
1980 pci_read_config_word(hw->pdev, PCI_STATUS, &status);
1981 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
1982 pci_write_config_word(hw->pdev, PCI_STATUS,
1983 status | PCI_STATUS_ERROR_BITS);
1985 sky2_write8(hw, B0_CTST, CS_MRST_CLR);
1987 /* clear any PEX errors */
1990 pci_write_config_dword(hw->pdev, PEX_UNC_ERR_STAT,
1992 pci_read_config_word(hw->pdev, PEX_LNK_STAT, &lstat);
1995 pmd_type = sky2_read8(hw, B2_PMD_TYP);
1996 hw->copper = !(pmd_type == 'L' || pmd_type == 'S');
1999 t8 = sky2_read8(hw, B2_Y2_HW_RES);
2000 if ((t8 & CFG_DUAL_MAC_MSK) == CFG_DUAL_MAC_MSK) {
2001 if (!(sky2_read8(hw, B2_Y2_CLK_GATE) & Y2_STATUS_LNK2_INAC))
2004 hw->chip_rev = (sky2_read8(hw, B2_MAC_CFG) & CFG_CHIP_R_MSK) >> 4;
2006 sky2_set_power_state(hw, PCI_D0);
2008 for (i = 0; i < hw->ports; i++) {
2009 sky2_write8(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_SET);
2010 sky2_write8(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_CLR);
2013 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
2015 /* Clear I2C IRQ noise */
2016 sky2_write32(hw, B2_I2C_IRQ, 1);
2018 /* turn off hardware timer (unused) */
2019 sky2_write8(hw, B2_TI_CTRL, TIM_STOP);
2020 sky2_write8(hw, B2_TI_CTRL, TIM_CLR_IRQ);
2022 sky2_write8(hw, B0_Y2LED, LED_STAT_ON);
2024 /* Turn on descriptor polling (every 75us) */
2025 sky2_write32(hw, B28_DPT_INI, sky2_us2clk(hw, 75));
2026 sky2_write8(hw, B28_DPT_CTRL, DPT_START);
2028 /* Turn off receive timestamp */
2029 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_STOP);
2030 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ);
2032 /* enable the Tx Arbiters */
2033 for (i = 0; i < hw->ports; i++)
2034 sky2_write8(hw, SK_REG(i, TXA_CTRL), TXA_ENA_ARB);
2036 /* Initialize ram interface */
2037 for (i = 0; i < hw->ports; i++) {
2038 sky2_write8(hw, RAM_BUFFER(i, B3_RI_CTRL), RI_RST_CLR);
2040 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_R1), SK_RI_TO_53);
2041 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XA1), SK_RI_TO_53);
2042 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XS1), SK_RI_TO_53);
2043 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_R1), SK_RI_TO_53);
2044 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XA1), SK_RI_TO_53);
2045 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XS1), SK_RI_TO_53);
2046 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_R2), SK_RI_TO_53);
2047 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XA2), SK_RI_TO_53);
2048 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XS2), SK_RI_TO_53);
2049 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_R2), SK_RI_TO_53);
2050 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XA2), SK_RI_TO_53);
2051 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XS2), SK_RI_TO_53);
2057 /* change Max. Read Request Size to 2048 bytes */
2058 pci_read_config_word(hw->pdev, PEX_DEV_CTRL, &pctrl);
2059 pctrl &= ~PEX_DC_MAX_RRS_MSK;
2060 pctrl |= PEX_DC_MAX_RD_RQ_SIZE(4);
2063 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
2064 pci_write_config_word(hw->pdev, PEX_DEV_CTRL, pctrl);
2065 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
2068 sky2_write32(hw, B0_HWE_IMSK, Y2_HWE_ALL_MASK);
2070 spin_lock_bh(&hw->phy_lock);
2071 for (i = 0; i < hw->ports; i++)
2072 sky2_phy_reset(hw, i);
2073 spin_unlock_bh(&hw->phy_lock);
2075 memset(hw->st_le, 0, STATUS_LE_BYTES);
2078 sky2_write32(hw, STAT_CTRL, SC_STAT_RST_SET);
2079 sky2_write32(hw, STAT_CTRL, SC_STAT_RST_CLR);
2081 sky2_write32(hw, STAT_LIST_ADDR_LO, hw->st_dma);
2082 sky2_write32(hw, STAT_LIST_ADDR_HI, (u64) hw->st_dma >> 32);
2084 /* Set the list last index */
2085 sky2_write16(hw, STAT_LAST_IDX, STATUS_RING_SIZE - 1);
2087 sky2_write32(hw, STAT_TX_TIMER_INI, sky2_ms2clk(hw, 10));
2089 /* These status setup values are copied from SysKonnect's driver */
2091 /* WA for dev. #4.3 */
2092 sky2_write16(hw, STAT_TX_IDX_TH, 0xfff); /* Tx Threshold */
2094 /* set Status-FIFO watermark */
2095 sky2_write8(hw, STAT_FIFO_WM, 0x21); /* WA for dev. #4.18 */
2097 /* set Status-FIFO ISR watermark */
2098 sky2_write8(hw, STAT_FIFO_ISR_WM, 0x07); /* WA for dev. #4.18 */
2101 sky2_write16(hw, STAT_TX_IDX_TH, 0x000a);
2103 /* set Status-FIFO watermark */
2104 sky2_write8(hw, STAT_FIFO_WM, 0x10);
2106 /* set Status-FIFO ISR watermark */
2107 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0)
2108 sky2_write8(hw, STAT_FIFO_ISR_WM, 0x10);
2110 else /* WA dev 4.109 */
2111 sky2_write8(hw, STAT_FIFO_ISR_WM, 0x04);
2113 sky2_write32(hw, STAT_ISR_TIMER_INI, 0x0190);
2116 /* enable status unit */
2117 sky2_write32(hw, STAT_CTRL, SC_STAT_OP_ON);
2119 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_START);
2120 sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_START);
2121 sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_START);
2126 static inline u32 sky2_supported_modes(const struct sky2_hw *hw)
2130 modes = SUPPORTED_10baseT_Half
2131 | SUPPORTED_10baseT_Full
2132 | SUPPORTED_100baseT_Half
2133 | SUPPORTED_100baseT_Full
2134 | SUPPORTED_Autoneg | SUPPORTED_TP;
2136 if (hw->chip_id != CHIP_ID_YUKON_FE)
2137 modes |= SUPPORTED_1000baseT_Half
2138 | SUPPORTED_1000baseT_Full;
2140 modes = SUPPORTED_1000baseT_Full | SUPPORTED_FIBRE
2141 | SUPPORTED_Autoneg;
2145 static int sky2_get_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
2147 struct sky2_port *sky2 = netdev_priv(dev);
2148 struct sky2_hw *hw = sky2->hw;
2150 ecmd->transceiver = XCVR_INTERNAL;
2151 ecmd->supported = sky2_supported_modes(hw);
2152 ecmd->phy_address = PHY_ADDR_MARV;
2154 ecmd->supported = SUPPORTED_10baseT_Half
2155 | SUPPORTED_10baseT_Full
2156 | SUPPORTED_100baseT_Half
2157 | SUPPORTED_100baseT_Full
2158 | SUPPORTED_1000baseT_Half
2159 | SUPPORTED_1000baseT_Full
2160 | SUPPORTED_Autoneg | SUPPORTED_TP;
2161 ecmd->port = PORT_TP;
2163 ecmd->port = PORT_FIBRE;
2165 ecmd->advertising = sky2->advertising;
2166 ecmd->autoneg = sky2->autoneg;
2167 ecmd->speed = sky2->speed;
2168 ecmd->duplex = sky2->duplex;
2172 static int sky2_set_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
2174 struct sky2_port *sky2 = netdev_priv(dev);
2175 const struct sky2_hw *hw = sky2->hw;
2176 u32 supported = sky2_supported_modes(hw);
2178 if (ecmd->autoneg == AUTONEG_ENABLE) {
2179 ecmd->advertising = supported;
2185 switch (ecmd->speed) {
2187 if (ecmd->duplex == DUPLEX_FULL)
2188 setting = SUPPORTED_1000baseT_Full;
2189 else if (ecmd->duplex == DUPLEX_HALF)
2190 setting = SUPPORTED_1000baseT_Half;
2195 if (ecmd->duplex == DUPLEX_FULL)
2196 setting = SUPPORTED_100baseT_Full;
2197 else if (ecmd->duplex == DUPLEX_HALF)
2198 setting = SUPPORTED_100baseT_Half;
2204 if (ecmd->duplex == DUPLEX_FULL)
2205 setting = SUPPORTED_10baseT_Full;
2206 else if (ecmd->duplex == DUPLEX_HALF)
2207 setting = SUPPORTED_10baseT_Half;
2215 if ((setting & supported) == 0)
2218 sky2->speed = ecmd->speed;
2219 sky2->duplex = ecmd->duplex;
2222 sky2->autoneg = ecmd->autoneg;
2223 sky2->advertising = ecmd->advertising;
2225 if (netif_running(dev)) {
2233 static void sky2_get_drvinfo(struct net_device *dev,
2234 struct ethtool_drvinfo *info)
2236 struct sky2_port *sky2 = netdev_priv(dev);
2238 strcpy(info->driver, DRV_NAME);
2239 strcpy(info->version, DRV_VERSION);
2240 strcpy(info->fw_version, "N/A");
2241 strcpy(info->bus_info, pci_name(sky2->hw->pdev));
2244 static const struct sky2_stat {
2245 char name[ETH_GSTRING_LEN];
2248 { "tx_bytes", GM_TXO_OK_HI },
2249 { "rx_bytes", GM_RXO_OK_HI },
2250 { "tx_broadcast", GM_TXF_BC_OK },
2251 { "rx_broadcast", GM_RXF_BC_OK },
2252 { "tx_multicast", GM_TXF_MC_OK },
2253 { "rx_multicast", GM_RXF_MC_OK },
2254 { "tx_unicast", GM_TXF_UC_OK },
2255 { "rx_unicast", GM_RXF_UC_OK },
2256 { "tx_mac_pause", GM_TXF_MPAUSE },
2257 { "rx_mac_pause", GM_RXF_MPAUSE },
2258 { "collisions", GM_TXF_SNG_COL },
2259 { "late_collision",GM_TXF_LAT_COL },
2260 { "aborted", GM_TXF_ABO_COL },
2261 { "multi_collisions", GM_TXF_MUL_COL },
2262 { "fifo_underrun", GM_TXE_FIFO_UR },
2263 { "fifo_overflow", GM_RXE_FIFO_OV },
2264 { "rx_toolong", GM_RXF_LNG_ERR },
2265 { "rx_jabber", GM_RXF_JAB_PKT },
2266 { "rx_runt", GM_RXE_FRAG },
2267 { "rx_too_long", GM_RXF_LNG_ERR },
2268 { "rx_fcs_error", GM_RXF_FCS_ERR },
2271 static u32 sky2_get_rx_csum(struct net_device *dev)
2273 struct sky2_port *sky2 = netdev_priv(dev);
2275 return sky2->rx_csum;
2278 static int sky2_set_rx_csum(struct net_device *dev, u32 data)
2280 struct sky2_port *sky2 = netdev_priv(dev);
2282 sky2->rx_csum = data;
2284 sky2_write32(sky2->hw, Q_ADDR(rxqaddr[sky2->port], Q_CSR),
2285 data ? BMU_ENA_RX_CHKSUM : BMU_DIS_RX_CHKSUM);
2290 static u32 sky2_get_msglevel(struct net_device *netdev)
2292 struct sky2_port *sky2 = netdev_priv(netdev);
2293 return sky2->msg_enable;
2296 static int sky2_nway_reset(struct net_device *dev)
2298 struct sky2_port *sky2 = netdev_priv(dev);
2299 struct sky2_hw *hw = sky2->hw;
2301 if (sky2->autoneg != AUTONEG_ENABLE)
2304 netif_stop_queue(dev);
2306 spin_lock_irq(&hw->phy_lock);
2307 sky2_phy_reset(hw, sky2->port);
2308 sky2_phy_init(hw, sky2->port);
2309 spin_unlock_irq(&hw->phy_lock);
2314 static void sky2_phy_stats(struct sky2_port *sky2, u64 * data, unsigned count)
2316 struct sky2_hw *hw = sky2->hw;
2317 unsigned port = sky2->port;
2320 data[0] = (u64) gma_read32(hw, port, GM_TXO_OK_HI) << 32
2321 | (u64) gma_read32(hw, port, GM_TXO_OK_LO);
2322 data[1] = (u64) gma_read32(hw, port, GM_RXO_OK_HI) << 32
2323 | (u64) gma_read32(hw, port, GM_RXO_OK_LO);
2325 for (i = 2; i < count; i++)
2326 data[i] = (u64) gma_read32(hw, port, sky2_stats[i].offset);
2329 static void sky2_set_msglevel(struct net_device *netdev, u32 value)
2331 struct sky2_port *sky2 = netdev_priv(netdev);
2332 sky2->msg_enable = value;
2335 static int sky2_get_stats_count(struct net_device *dev)
2337 return ARRAY_SIZE(sky2_stats);
2340 static void sky2_get_ethtool_stats(struct net_device *dev,
2341 struct ethtool_stats *stats, u64 * data)
2343 struct sky2_port *sky2 = netdev_priv(dev);
2345 sky2_phy_stats(sky2, data, ARRAY_SIZE(sky2_stats));
2348 static void sky2_get_strings(struct net_device *dev, u32 stringset, u8 * data)
2352 switch (stringset) {
2354 for (i = 0; i < ARRAY_SIZE(sky2_stats); i++)
2355 memcpy(data + i * ETH_GSTRING_LEN,
2356 sky2_stats[i].name, ETH_GSTRING_LEN);
2361 /* Use hardware MIB variables for critical path statistics and
2362 * transmit feedback not reported at interrupt.
2363 * Other errors are accounted for in interrupt handler.
2365 static struct net_device_stats *sky2_get_stats(struct net_device *dev)
2367 struct sky2_port *sky2 = netdev_priv(dev);
2370 sky2_phy_stats(sky2, data, ARRAY_SIZE(data));
2372 sky2->net_stats.tx_bytes = data[0];
2373 sky2->net_stats.rx_bytes = data[1];
2374 sky2->net_stats.tx_packets = data[2] + data[4] + data[6];
2375 sky2->net_stats.rx_packets = data[3] + data[5] + data[7];
2376 sky2->net_stats.multicast = data[5] + data[7];
2377 sky2->net_stats.collisions = data[10];
2378 sky2->net_stats.tx_aborted_errors = data[12];
2380 return &sky2->net_stats;
2383 static int sky2_set_mac_address(struct net_device *dev, void *p)
2385 struct sky2_port *sky2 = netdev_priv(dev);
2386 struct sockaddr *addr = p;
2389 if (!is_valid_ether_addr(addr->sa_data))
2390 return -EADDRNOTAVAIL;
2393 memcpy(dev->dev_addr, addr->sa_data, ETH_ALEN);
2394 memcpy_toio(sky2->hw->regs + B2_MAC_1 + sky2->port * 8,
2395 dev->dev_addr, ETH_ALEN);
2396 memcpy_toio(sky2->hw->regs + B2_MAC_2 + sky2->port * 8,
2397 dev->dev_addr, ETH_ALEN);
2398 if (dev->flags & IFF_UP)
2403 static void sky2_set_multicast(struct net_device *dev)
2405 struct sky2_port *sky2 = netdev_priv(dev);
2406 struct sky2_hw *hw = sky2->hw;
2407 unsigned port = sky2->port;
2408 struct dev_mc_list *list = dev->mc_list;
2412 memset(filter, 0, sizeof(filter));
2414 reg = gma_read16(hw, port, GM_RX_CTRL);
2415 reg |= GM_RXCR_UCF_ENA;
2417 if (dev->flags & IFF_PROMISC) /* promiscuous */
2418 reg &= ~(GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA);
2419 else if ((dev->flags & IFF_ALLMULTI) || dev->mc_count > 16) /* all multicast */
2420 memset(filter, 0xff, sizeof(filter));
2421 else if (dev->mc_count == 0) /* no multicast */
2422 reg &= ~GM_RXCR_MCF_ENA;
2425 reg |= GM_RXCR_MCF_ENA;
2427 for (i = 0; list && i < dev->mc_count; i++, list = list->next) {
2428 u32 bit = ether_crc(ETH_ALEN, list->dmi_addr) & 0x3f;
2429 filter[bit / 8] |= 1 << (bit % 8);
2433 gma_write16(hw, port, GM_MC_ADDR_H1,
2434 (u16) filter[0] | ((u16) filter[1] << 8));
2435 gma_write16(hw, port, GM_MC_ADDR_H2,
2436 (u16) filter[2] | ((u16) filter[3] << 8));
2437 gma_write16(hw, port, GM_MC_ADDR_H3,
2438 (u16) filter[4] | ((u16) filter[5] << 8));
2439 gma_write16(hw, port, GM_MC_ADDR_H4,
2440 (u16) filter[6] | ((u16) filter[7] << 8));
2442 gma_write16(hw, port, GM_RX_CTRL, reg);
2445 /* Can have one global because blinking is controlled by
2446 * ethtool and that is always under RTNL mutex
2448 static inline void sky2_led(struct sky2_hw *hw, unsigned port, int on)
2452 spin_lock_bh(&hw->phy_lock);
2453 switch (hw->chip_id) {
2454 case CHIP_ID_YUKON_XL:
2455 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
2456 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
2457 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
2458 on ? (PHY_M_LEDC_LOS_CTRL(1) |
2459 PHY_M_LEDC_INIT_CTRL(7) |
2460 PHY_M_LEDC_STA1_CTRL(7) |
2461 PHY_M_LEDC_STA0_CTRL(7))
2464 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
2468 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, 0);
2469 gm_phy_write(hw, port, PHY_MARV_LED_OVER,
2470 on ? PHY_M_LED_MO_DUP(MO_LED_ON) |
2471 PHY_M_LED_MO_10(MO_LED_ON) |
2472 PHY_M_LED_MO_100(MO_LED_ON) |
2473 PHY_M_LED_MO_1000(MO_LED_ON) |
2474 PHY_M_LED_MO_RX(MO_LED_ON)
2475 : PHY_M_LED_MO_DUP(MO_LED_OFF) |
2476 PHY_M_LED_MO_10(MO_LED_OFF) |
2477 PHY_M_LED_MO_100(MO_LED_OFF) |
2478 PHY_M_LED_MO_1000(MO_LED_OFF) |
2479 PHY_M_LED_MO_RX(MO_LED_OFF));
2482 spin_unlock_bh(&hw->phy_lock);
2485 /* blink LED's for finding board */
2486 static int sky2_phys_id(struct net_device *dev, u32 data)
2488 struct sky2_port *sky2 = netdev_priv(dev);
2489 struct sky2_hw *hw = sky2->hw;
2490 unsigned port = sky2->port;
2491 u16 ledctrl, ledover = 0;
2495 if (!data || data > (u32) (MAX_SCHEDULE_TIMEOUT / HZ))
2496 ms = jiffies_to_msecs(MAX_SCHEDULE_TIMEOUT);
2500 /* save initial values */
2501 spin_lock_bh(&hw->phy_lock);
2502 if (hw->chip_id == CHIP_ID_YUKON_XL) {
2503 u16 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
2504 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
2505 ledctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
2506 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
2508 ledctrl = gm_phy_read(hw, port, PHY_MARV_LED_CTRL);
2509 ledover = gm_phy_read(hw, port, PHY_MARV_LED_OVER);
2511 spin_unlock_bh(&hw->phy_lock);
2514 sky2_led(hw, port, onoff);
2517 if (msleep_interruptible(250))
2518 break; /* interrupted */
2522 /* resume regularly scheduled programming */
2523 spin_lock_bh(&hw->phy_lock);
2524 if (hw->chip_id == CHIP_ID_YUKON_XL) {
2525 u16 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
2526 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
2527 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ledctrl);
2528 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
2530 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, ledctrl);
2531 gm_phy_write(hw, port, PHY_MARV_LED_OVER, ledover);
2533 spin_unlock_bh(&hw->phy_lock);
2538 static void sky2_get_pauseparam(struct net_device *dev,
2539 struct ethtool_pauseparam *ecmd)
2541 struct sky2_port *sky2 = netdev_priv(dev);
2543 ecmd->tx_pause = sky2->tx_pause;
2544 ecmd->rx_pause = sky2->rx_pause;
2545 ecmd->autoneg = sky2->autoneg;
2548 static int sky2_set_pauseparam(struct net_device *dev,
2549 struct ethtool_pauseparam *ecmd)
2551 struct sky2_port *sky2 = netdev_priv(dev);
2554 sky2->autoneg = ecmd->autoneg;
2555 sky2->tx_pause = ecmd->tx_pause != 0;
2556 sky2->rx_pause = ecmd->rx_pause != 0;
2558 if (netif_running(dev)) {
2567 static void sky2_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
2569 struct sky2_port *sky2 = netdev_priv(dev);
2571 wol->supported = WAKE_MAGIC;
2572 wol->wolopts = sky2->wol ? WAKE_MAGIC : 0;
2575 static int sky2_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
2577 struct sky2_port *sky2 = netdev_priv(dev);
2578 struct sky2_hw *hw = sky2->hw;
2580 if (wol->wolopts != WAKE_MAGIC && wol->wolopts != 0)
2583 sky2->wol = wol->wolopts == WAKE_MAGIC;
2586 memcpy_toio(hw->regs + WOL_MAC_ADDR, dev->dev_addr, ETH_ALEN);
2588 sky2_write16(hw, WOL_CTRL_STAT,
2589 WOL_CTL_ENA_PME_ON_MAGIC_PKT |
2590 WOL_CTL_ENA_MAGIC_PKT_UNIT);
2592 sky2_write16(hw, WOL_CTRL_STAT, WOL_CTL_DEFAULT);
2598 static void sky2_get_ringparam(struct net_device *dev,
2599 struct ethtool_ringparam *ering)
2601 struct sky2_port *sky2 = netdev_priv(dev);
2603 ering->rx_max_pending = RX_MAX_PENDING;
2604 ering->rx_mini_max_pending = 0;
2605 ering->rx_jumbo_max_pending = 0;
2606 ering->tx_max_pending = TX_RING_SIZE - 1;
2608 ering->rx_pending = sky2->rx_pending;
2609 ering->rx_mini_pending = 0;
2610 ering->rx_jumbo_pending = 0;
2611 ering->tx_pending = sky2->tx_pending;
2614 static int sky2_set_ringparam(struct net_device *dev,
2615 struct ethtool_ringparam *ering)
2617 struct sky2_port *sky2 = netdev_priv(dev);
2620 if (ering->rx_pending > RX_MAX_PENDING ||
2621 ering->rx_pending < 8 ||
2622 ering->tx_pending < MAX_SKB_TX_LE ||
2623 ering->tx_pending > TX_RING_SIZE - 1)
2626 if (netif_running(dev))
2629 sky2->rx_pending = ering->rx_pending;
2630 sky2->tx_pending = ering->tx_pending;
2632 if (netif_running(dev))
2638 static int sky2_get_regs_len(struct net_device *dev)
2644 * Returns copy of control register region
2645 * Note: access to the RAM address register set will cause timeouts.
2647 static void sky2_get_regs(struct net_device *dev, struct ethtool_regs *regs,
2650 const struct sky2_port *sky2 = netdev_priv(dev);
2651 const void __iomem *io = sky2->hw->regs;
2653 BUG_ON(regs->len < B3_RI_WTO_R1);
2655 memset(p, 0, regs->len);
2657 memcpy_fromio(p, io, B3_RAM_ADDR);
2659 memcpy_fromio(p + B3_RI_WTO_R1,
2661 regs->len - B3_RI_WTO_R1);
2664 static struct ethtool_ops sky2_ethtool_ops = {
2665 .get_settings = sky2_get_settings,
2666 .set_settings = sky2_set_settings,
2667 .get_drvinfo = sky2_get_drvinfo,
2668 .get_msglevel = sky2_get_msglevel,
2669 .set_msglevel = sky2_set_msglevel,
2670 .nway_reset = sky2_nway_reset,
2671 .get_regs_len = sky2_get_regs_len,
2672 .get_regs = sky2_get_regs,
2673 .get_link = ethtool_op_get_link,
2674 .get_sg = ethtool_op_get_sg,
2675 .set_sg = ethtool_op_set_sg,
2676 .get_tx_csum = ethtool_op_get_tx_csum,
2677 .set_tx_csum = ethtool_op_set_tx_csum,
2678 .get_tso = ethtool_op_get_tso,
2679 .set_tso = ethtool_op_set_tso,
2680 .get_rx_csum = sky2_get_rx_csum,
2681 .set_rx_csum = sky2_set_rx_csum,
2682 .get_strings = sky2_get_strings,
2683 .get_ringparam = sky2_get_ringparam,
2684 .set_ringparam = sky2_set_ringparam,
2685 .get_pauseparam = sky2_get_pauseparam,
2686 .set_pauseparam = sky2_set_pauseparam,
2688 .get_wol = sky2_get_wol,
2689 .set_wol = sky2_set_wol,
2691 .phys_id = sky2_phys_id,
2692 .get_stats_count = sky2_get_stats_count,
2693 .get_ethtool_stats = sky2_get_ethtool_stats,
2694 .get_perm_addr = ethtool_op_get_perm_addr,
2697 /* Initialize network device */
2698 static __devinit struct net_device *sky2_init_netdev(struct sky2_hw *hw,
2699 unsigned port, int highmem)
2701 struct sky2_port *sky2;
2702 struct net_device *dev = alloc_etherdev(sizeof(*sky2));
2705 printk(KERN_ERR "sky2 etherdev alloc failed");
2709 SET_MODULE_OWNER(dev);
2710 SET_NETDEV_DEV(dev, &hw->pdev->dev);
2711 dev->open = sky2_up;
2712 dev->stop = sky2_down;
2713 dev->hard_start_xmit = sky2_xmit_frame;
2714 dev->get_stats = sky2_get_stats;
2715 dev->set_multicast_list = sky2_set_multicast;
2716 dev->set_mac_address = sky2_set_mac_address;
2717 dev->change_mtu = sky2_change_mtu;
2718 SET_ETHTOOL_OPS(dev, &sky2_ethtool_ops);
2719 dev->tx_timeout = sky2_tx_timeout;
2720 dev->watchdog_timeo = TX_WATCHDOG;
2722 dev->poll = sky2_poll;
2723 dev->weight = NAPI_WEIGHT;
2724 #ifdef CONFIG_NET_POLL_CONTROLLER
2725 dev->poll_controller = sky2_netpoll;
2728 sky2 = netdev_priv(dev);
2731 sky2->msg_enable = netif_msg_init(debug, default_msg);
2733 spin_lock_init(&sky2->tx_lock);
2734 /* Auto speed and flow control */
2735 sky2->autoneg = AUTONEG_ENABLE;
2740 sky2->advertising = sky2_supported_modes(hw);
2742 tasklet_init(&sky2->phy_task, sky2_phy_task, (unsigned long)sky2);
2743 sky2->tx_pending = TX_DEF_PENDING;
2744 sky2->rx_pending = is_ec_a1(hw) ? 8 : RX_DEF_PENDING;
2746 hw->dev[port] = dev;
2750 dev->features |= NETIF_F_LLTX | NETIF_F_TSO;
2752 dev->features |= NETIF_F_HIGHDMA;
2753 dev->features |= NETIF_F_IP_CSUM | NETIF_F_SG;
2755 #ifdef SKY2_VLAN_TAG_USED
2756 dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
2757 dev->vlan_rx_register = sky2_vlan_rx_register;
2758 dev->vlan_rx_kill_vid = sky2_vlan_rx_kill_vid;
2761 /* read the mac address */
2762 memcpy_fromio(dev->dev_addr, hw->regs + B2_MAC_1 + port * 8, ETH_ALEN);
2763 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
2765 /* device is off until link detection */
2766 netif_carrier_off(dev);
2767 netif_stop_queue(dev);
2772 static inline void sky2_show_addr(struct net_device *dev)
2774 const struct sky2_port *sky2 = netdev_priv(dev);
2776 if (netif_msg_probe(sky2))
2777 printk(KERN_INFO PFX "%s: addr %02x:%02x:%02x:%02x:%02x:%02x\n",
2779 dev->dev_addr[0], dev->dev_addr[1], dev->dev_addr[2],
2780 dev->dev_addr[3], dev->dev_addr[4], dev->dev_addr[5]);
2783 static int __devinit sky2_probe(struct pci_dev *pdev,
2784 const struct pci_device_id *ent)
2786 struct net_device *dev, *dev1 = NULL;
2788 int err, pm_cap, using_dac = 0;
2790 err = pci_enable_device(pdev);
2792 printk(KERN_ERR PFX "%s cannot enable PCI device\n",
2797 err = pci_request_regions(pdev, DRV_NAME);
2799 printk(KERN_ERR PFX "%s cannot obtain PCI resources\n",
2804 pci_set_master(pdev);
2806 /* Find power-management capability. */
2807 pm_cap = pci_find_capability(pdev, PCI_CAP_ID_PM);
2809 printk(KERN_ERR PFX "Cannot find PowerManagement capability, "
2812 goto err_out_free_regions;
2815 if (sizeof(dma_addr_t) > sizeof(u32)) {
2816 err = pci_set_dma_mask(pdev, DMA_64BIT_MASK);
2822 err = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
2824 printk(KERN_ERR PFX "%s no usable DMA configuration\n",
2826 goto err_out_free_regions;
2830 /* byte swap descriptors in hardware */
2834 pci_read_config_dword(pdev, PCI_DEV_REG2, ®);
2835 reg |= PCI_REV_DESC;
2836 pci_write_config_dword(pdev, PCI_DEV_REG2, reg);
2841 hw = kmalloc(sizeof(*hw), GFP_KERNEL);
2843 printk(KERN_ERR PFX "%s: cannot allocate hardware struct\n",
2845 goto err_out_free_regions;
2848 memset(hw, 0, sizeof(*hw));
2850 spin_lock_init(&hw->phy_lock);
2852 hw->regs = ioremap_nocache(pci_resource_start(pdev, 0), 0x4000);
2854 printk(KERN_ERR PFX "%s: cannot map device registers\n",
2856 goto err_out_free_hw;
2858 hw->pm_cap = pm_cap;
2860 err = sky2_reset(hw);
2862 goto err_out_iounmap;
2864 printk(KERN_INFO PFX "addr 0x%lx irq %d Yukon-%s (0x%x) rev %d\n",
2865 pci_resource_start(pdev, 0), pdev->irq,
2866 yukon_name[hw->chip_id - CHIP_ID_YUKON],
2867 hw->chip_id, hw->chip_rev);
2869 dev = sky2_init_netdev(hw, 0, using_dac);
2871 goto err_out_free_pci;
2873 err = register_netdev(dev);
2875 printk(KERN_ERR PFX "%s: cannot register net device\n",
2877 goto err_out_free_netdev;
2880 sky2_show_addr(dev);
2882 if (hw->ports > 1 && (dev1 = sky2_init_netdev(hw, 1, using_dac))) {
2883 if (register_netdev(dev1) == 0)
2884 sky2_show_addr(dev1);
2886 /* Failure to register second port need not be fatal */
2887 printk(KERN_WARNING PFX
2888 "register of second port failed\n");
2894 err = request_irq(pdev->irq, sky2_intr, SA_SHIRQ, DRV_NAME, hw);
2896 printk(KERN_ERR PFX "%s: cannot assign irq %d\n",
2897 pci_name(pdev), pdev->irq);
2898 goto err_out_unregister;
2901 hw->intr_mask = Y2_IS_BASE;
2902 sky2_write32(hw, B0_IMSK, hw->intr_mask);
2904 pci_set_drvdata(pdev, hw);
2910 unregister_netdev(dev1);
2913 unregister_netdev(dev);
2914 err_out_free_netdev:
2917 sky2_write8(hw, B0_CTST, CS_RST_SET);
2918 pci_free_consistent(hw->pdev, STATUS_LE_BYTES, hw->st_le, hw->st_dma);
2923 err_out_free_regions:
2924 pci_release_regions(pdev);
2925 pci_disable_device(pdev);
2930 static void __devexit sky2_remove(struct pci_dev *pdev)
2932 struct sky2_hw *hw = pci_get_drvdata(pdev);
2933 struct net_device *dev0, *dev1;
2941 unregister_netdev(dev1);
2942 unregister_netdev(dev0);
2944 sky2_write32(hw, B0_IMSK, 0);
2945 sky2_set_power_state(hw, PCI_D3hot);
2946 sky2_write16(hw, B0_Y2LED, LED_STAT_OFF);
2947 sky2_write8(hw, B0_CTST, CS_RST_SET);
2948 sky2_read8(hw, B0_CTST);
2950 free_irq(pdev->irq, hw);
2951 pci_free_consistent(pdev, STATUS_LE_BYTES, hw->st_le, hw->st_dma);
2952 pci_release_regions(pdev);
2953 pci_disable_device(pdev);
2961 pci_set_drvdata(pdev, NULL);
2965 static int sky2_suspend(struct pci_dev *pdev, pm_message_t state)
2967 struct sky2_hw *hw = pci_get_drvdata(pdev);
2970 for (i = 0; i < 2; i++) {
2971 struct net_device *dev = hw->dev[i];
2974 if (!netif_running(dev))
2978 netif_device_detach(dev);
2982 return sky2_set_power_state(hw, pci_choose_state(pdev, state));
2985 static int sky2_resume(struct pci_dev *pdev)
2987 struct sky2_hw *hw = pci_get_drvdata(pdev);
2990 pci_restore_state(pdev);
2991 pci_enable_wake(pdev, PCI_D0, 0);
2992 sky2_set_power_state(hw, PCI_D0);
2996 for (i = 0; i < 2; i++) {
2997 struct net_device *dev = hw->dev[i];
2999 if (netif_running(dev)) {
3000 netif_device_attach(dev);
3009 static struct pci_driver sky2_driver = {
3011 .id_table = sky2_id_table,
3012 .probe = sky2_probe,
3013 .remove = __devexit_p(sky2_remove),
3015 .suspend = sky2_suspend,
3016 .resume = sky2_resume,
3020 static int __init sky2_init_module(void)
3022 return pci_module_init(&sky2_driver);
3025 static void __exit sky2_cleanup_module(void)
3027 pci_unregister_driver(&sky2_driver);
3030 module_init(sky2_init_module);
3031 module_exit(sky2_cleanup_module);
3033 MODULE_DESCRIPTION("Marvell Yukon 2 Gigabit Ethernet driver");
3034 MODULE_AUTHOR("Stephen Hemminger <shemminger@osdl.org>");
3035 MODULE_LICENSE("GPL");