2 * New driver for Marvell Yukon 2 chipset.
3 * Based on earlier sk98lin, and skge driver.
5 * This driver intentionally does not support all the features
6 * of the original driver such as link fail-over and link management because
7 * those should be done at higher levels.
9 * Copyright (C) 2005 Stephen Hemminger <shemminger@osdl.org>
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License, or
14 * (at your option) any later version.
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
26 #include <linux/crc32.h>
27 #include <linux/kernel.h>
28 #include <linux/version.h>
29 #include <linux/module.h>
30 #include <linux/netdevice.h>
31 #include <linux/dma-mapping.h>
32 #include <linux/etherdevice.h>
33 #include <linux/ethtool.h>
34 #include <linux/pci.h>
36 #include <linux/tcp.h>
38 #include <linux/delay.h>
39 #include <linux/workqueue.h>
40 #include <linux/if_vlan.h>
41 #include <linux/prefetch.h>
42 #include <linux/mii.h>
46 #if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
47 #define SKY2_VLAN_TAG_USED 1
52 #define DRV_NAME "sky2"
53 #define DRV_VERSION "1.9"
54 #define PFX DRV_NAME " "
57 * The Yukon II chipset takes 64 bit command blocks (called list elements)
58 * that are organized into three (receive, transmit, status) different rings
62 #define RX_LE_SIZE 1024
63 #define RX_LE_BYTES (RX_LE_SIZE*sizeof(struct sky2_rx_le))
64 #define RX_MAX_PENDING (RX_LE_SIZE/6 - 2)
65 #define RX_DEF_PENDING RX_MAX_PENDING
66 #define RX_SKB_ALIGN 8
67 #define RX_BUF_WRITE 16
69 #define TX_RING_SIZE 512
70 #define TX_DEF_PENDING (TX_RING_SIZE - 1)
71 #define TX_MIN_PENDING 64
72 #define MAX_SKB_TX_LE (4 + (sizeof(dma_addr_t)/sizeof(u32))*MAX_SKB_FRAGS)
74 #define STATUS_RING_SIZE 2048 /* 2 ports * (TX + 2*RX) */
75 #define STATUS_LE_BYTES (STATUS_RING_SIZE*sizeof(struct sky2_status_le))
76 #define TX_WATCHDOG (5 * HZ)
77 #define NAPI_WEIGHT 64
78 #define PHY_RETRIES 1000
80 #define RING_NEXT(x,s) (((x)+1) & ((s)-1))
82 static const u32 default_msg =
83 NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_LINK
84 | NETIF_MSG_TIMER | NETIF_MSG_TX_ERR | NETIF_MSG_RX_ERR
85 | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN;
87 static int debug = -1; /* defaults above */
88 module_param(debug, int, 0);
89 MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
91 static int copybreak __read_mostly = 128;
92 module_param(copybreak, int, 0);
93 MODULE_PARM_DESC(copybreak, "Receive copy threshold");
95 static int disable_msi = 0;
96 module_param(disable_msi, int, 0);
97 MODULE_PARM_DESC(disable_msi, "Disable Message Signaled Interrupt (MSI)");
99 static int idle_timeout = 0;
100 module_param(idle_timeout, int, 0);
101 MODULE_PARM_DESC(idle_timeout, "Watchdog timer for lost interrupts (ms)");
103 static const struct pci_device_id sky2_id_table[] = {
104 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, 0x9000) },
105 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, 0x9E00) },
106 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4b00) }, /* DGE-560T */
107 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4001) }, /* DGE-550SX */
108 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4340) },
109 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4341) },
110 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4342) },
111 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4343) },
112 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4344) },
113 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4345) },
114 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4346) },
115 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4347) },
116 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4350) },
117 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4351) },
118 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4352) },
119 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4353) },
120 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4360) },
121 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4361) },
122 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4362) },
123 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4363) },
124 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4364) },
125 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4365) },
126 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4366) },
127 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4367) },
128 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4368) },
129 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4369) },
133 MODULE_DEVICE_TABLE(pci, sky2_id_table);
135 /* Avoid conditionals by using array */
136 static const unsigned txqaddr[] = { Q_XA1, Q_XA2 };
137 static const unsigned rxqaddr[] = { Q_R1, Q_R2 };
138 static const u32 portirq_msk[] = { Y2_IS_PORT_1, Y2_IS_PORT_2 };
140 /* This driver supports yukon2 chipset only */
141 static const char *yukon2_name[] = {
143 "EC Ultra", /* 0xb4 */
144 "UNKNOWN", /* 0xb5 */
149 /* Access to external PHY */
150 static int gm_phy_write(struct sky2_hw *hw, unsigned port, u16 reg, u16 val)
154 gma_write16(hw, port, GM_SMI_DATA, val);
155 gma_write16(hw, port, GM_SMI_CTRL,
156 GM_SMI_CT_PHY_AD(PHY_ADDR_MARV) | GM_SMI_CT_REG_AD(reg));
158 for (i = 0; i < PHY_RETRIES; i++) {
159 if (!(gma_read16(hw, port, GM_SMI_CTRL) & GM_SMI_CT_BUSY))
164 printk(KERN_WARNING PFX "%s: phy write timeout\n", hw->dev[port]->name);
168 static int __gm_phy_read(struct sky2_hw *hw, unsigned port, u16 reg, u16 *val)
172 gma_write16(hw, port, GM_SMI_CTRL, GM_SMI_CT_PHY_AD(PHY_ADDR_MARV)
173 | GM_SMI_CT_REG_AD(reg) | GM_SMI_CT_OP_RD);
175 for (i = 0; i < PHY_RETRIES; i++) {
176 if (gma_read16(hw, port, GM_SMI_CTRL) & GM_SMI_CT_RD_VAL) {
177 *val = gma_read16(hw, port, GM_SMI_DATA);
187 static u16 gm_phy_read(struct sky2_hw *hw, unsigned port, u16 reg)
191 if (__gm_phy_read(hw, port, reg, &v) != 0)
192 printk(KERN_WARNING PFX "%s: phy read timeout\n", hw->dev[port]->name);
196 static void sky2_set_power_state(struct sky2_hw *hw, pci_power_t state)
201 pr_debug("sky2_set_power_state %d\n", state);
202 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
204 power_control = sky2_pci_read16(hw, hw->pm_cap + PCI_PM_PMC);
205 vaux = (sky2_read16(hw, B0_CTST) & Y2_VAUX_AVAIL) &&
206 (power_control & PCI_PM_CAP_PME_D3cold);
208 power_control = sky2_pci_read16(hw, hw->pm_cap + PCI_PM_CTRL);
210 power_control |= PCI_PM_CTRL_PME_STATUS;
211 power_control &= ~(PCI_PM_CTRL_STATE_MASK);
215 /* switch power to VCC (WA for VAUX problem) */
216 sky2_write8(hw, B0_POWER_CTRL,
217 PC_VAUX_ENA | PC_VCC_ENA | PC_VAUX_OFF | PC_VCC_ON);
219 /* disable Core Clock Division, */
220 sky2_write32(hw, B2_Y2_CLK_CTRL, Y2_CLK_DIV_DIS);
222 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1)
223 /* enable bits are inverted */
224 sky2_write8(hw, B2_Y2_CLK_GATE,
225 Y2_PCI_CLK_LNK1_DIS | Y2_COR_CLK_LNK1_DIS |
226 Y2_CLK_GAT_LNK1_DIS | Y2_PCI_CLK_LNK2_DIS |
227 Y2_COR_CLK_LNK2_DIS | Y2_CLK_GAT_LNK2_DIS);
229 sky2_write8(hw, B2_Y2_CLK_GATE, 0);
231 if (hw->chip_id == CHIP_ID_YUKON_EC_U) {
234 sky2_pci_write32(hw, PCI_DEV_REG3, 0);
235 reg1 = sky2_pci_read32(hw, PCI_DEV_REG4);
236 reg1 &= P_ASPM_CONTROL_MSK;
237 sky2_pci_write32(hw, PCI_DEV_REG4, reg1);
238 sky2_pci_write32(hw, PCI_DEV_REG5, 0);
245 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1)
246 sky2_write8(hw, B2_Y2_CLK_GATE, 0);
248 /* enable bits are inverted */
249 sky2_write8(hw, B2_Y2_CLK_GATE,
250 Y2_PCI_CLK_LNK1_DIS | Y2_COR_CLK_LNK1_DIS |
251 Y2_CLK_GAT_LNK1_DIS | Y2_PCI_CLK_LNK2_DIS |
252 Y2_COR_CLK_LNK2_DIS | Y2_CLK_GAT_LNK2_DIS);
254 /* switch power to VAUX */
255 if (vaux && state != PCI_D3cold)
256 sky2_write8(hw, B0_POWER_CTRL,
257 (PC_VAUX_ENA | PC_VCC_ENA |
258 PC_VAUX_ON | PC_VCC_OFF));
261 printk(KERN_ERR PFX "Unknown power state %d\n", state);
264 sky2_pci_write16(hw, hw->pm_cap + PCI_PM_CTRL, power_control);
265 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
268 static void sky2_gmac_reset(struct sky2_hw *hw, unsigned port)
272 /* disable all GMAC IRQ's */
273 sky2_write8(hw, SK_REG(port, GMAC_IRQ_MSK), 0);
274 /* disable PHY IRQs */
275 gm_phy_write(hw, port, PHY_MARV_INT_MASK, 0);
277 gma_write16(hw, port, GM_MC_ADDR_H1, 0); /* clear MC hash */
278 gma_write16(hw, port, GM_MC_ADDR_H2, 0);
279 gma_write16(hw, port, GM_MC_ADDR_H3, 0);
280 gma_write16(hw, port, GM_MC_ADDR_H4, 0);
282 reg = gma_read16(hw, port, GM_RX_CTRL);
283 reg |= GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA;
284 gma_write16(hw, port, GM_RX_CTRL, reg);
287 static void sky2_phy_init(struct sky2_hw *hw, unsigned port)
289 struct sky2_port *sky2 = netdev_priv(hw->dev[port]);
290 u16 ctrl, ct1000, adv, pg, ledctrl, ledover, reg;
292 if (sky2->autoneg == AUTONEG_ENABLE &&
293 !(hw->chip_id == CHIP_ID_YUKON_XL || hw->chip_id == CHIP_ID_YUKON_EC_U)) {
294 u16 ectrl = gm_phy_read(hw, port, PHY_MARV_EXT_CTRL);
296 ectrl &= ~(PHY_M_EC_M_DSC_MSK | PHY_M_EC_S_DSC_MSK |
298 ectrl |= PHY_M_EC_MAC_S(MAC_TX_CLK_25_MHZ);
300 if (hw->chip_id == CHIP_ID_YUKON_EC)
301 ectrl |= PHY_M_EC_DSC_2(2) | PHY_M_EC_DOWN_S_ENA;
303 ectrl |= PHY_M_EC_M_DSC(2) | PHY_M_EC_S_DSC(3);
305 gm_phy_write(hw, port, PHY_MARV_EXT_CTRL, ectrl);
308 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
309 if (sky2_is_copper(hw)) {
310 if (hw->chip_id == CHIP_ID_YUKON_FE) {
311 /* enable automatic crossover */
312 ctrl |= PHY_M_PC_MDI_XMODE(PHY_M_PC_ENA_AUTO) >> 1;
314 /* disable energy detect */
315 ctrl &= ~PHY_M_PC_EN_DET_MSK;
317 /* enable automatic crossover */
318 ctrl |= PHY_M_PC_MDI_XMODE(PHY_M_PC_ENA_AUTO);
320 if (sky2->autoneg == AUTONEG_ENABLE &&
321 (hw->chip_id == CHIP_ID_YUKON_XL || hw->chip_id == CHIP_ID_YUKON_EC_U)) {
322 ctrl &= ~PHY_M_PC_DSC_MSK;
323 ctrl |= PHY_M_PC_DSC(2) | PHY_M_PC_DOWN_S_ENA;
327 /* workaround for deviation #4.88 (CRC errors) */
328 /* disable Automatic Crossover */
330 ctrl &= ~PHY_M_PC_MDIX_MSK;
333 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
335 /* special setup for PHY 88E1112 Fiber */
336 if (hw->chip_id == CHIP_ID_YUKON_XL && !sky2_is_copper(hw)) {
337 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
339 /* Fiber: select 1000BASE-X only mode MAC Specific Ctrl Reg. */
340 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 2);
341 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
342 ctrl &= ~PHY_M_MAC_MD_MSK;
343 ctrl |= PHY_M_MAC_MODE_SEL(PHY_M_MAC_MD_1000BX);
344 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
346 if (hw->pmd_type == 'P') {
347 /* select page 1 to access Fiber registers */
348 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 1);
350 /* for SFP-module set SIGDET polarity to low */
351 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
352 ctrl |= PHY_M_FIB_SIGD_POL;
353 gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
356 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
364 if (sky2->autoneg == AUTONEG_ENABLE) {
365 if (sky2_is_copper(hw)) {
366 if (sky2->advertising & ADVERTISED_1000baseT_Full)
367 ct1000 |= PHY_M_1000C_AFD;
368 if (sky2->advertising & ADVERTISED_1000baseT_Half)
369 ct1000 |= PHY_M_1000C_AHD;
370 if (sky2->advertising & ADVERTISED_100baseT_Full)
371 adv |= PHY_M_AN_100_FD;
372 if (sky2->advertising & ADVERTISED_100baseT_Half)
373 adv |= PHY_M_AN_100_HD;
374 if (sky2->advertising & ADVERTISED_10baseT_Full)
375 adv |= PHY_M_AN_10_FD;
376 if (sky2->advertising & ADVERTISED_10baseT_Half)
377 adv |= PHY_M_AN_10_HD;
379 /* desired flow control */
380 if (sky2->tx_pause && sky2->rx_pause) /* both */
381 adv |= PHY_M_AN_PC | PHY_M_AN_ASP;
382 else if (sky2->tx_pause)
384 else if (sky2->rx_pause)
388 } else { /* special defines for FIBER (88E1040S only) */
389 if (sky2->advertising & ADVERTISED_1000baseT_Full)
390 adv |= PHY_M_AN_1000X_AFD;
391 if (sky2->advertising & ADVERTISED_1000baseT_Half)
392 adv |= PHY_M_AN_1000X_AHD;
394 if (sky2->tx_pause && sky2->rx_pause) /* both */
395 adv |= PHY_M_P_BOTH_MD_X;
396 else if (sky2->tx_pause)
397 adv |= PHY_M_P_ASYM_MD_X;
398 else if (sky2->rx_pause)
399 adv |= PHY_M_P_SYM_MD_X;
401 adv |= PHY_M_P_NO_PAUSE_X;
404 /* Restart Auto-negotiation */
405 ctrl |= PHY_CT_ANE | PHY_CT_RE_CFG;
407 /* forced speed/duplex settings */
408 ct1000 = PHY_M_1000C_MSE;
410 /* Disable auto update for duplex flow control and speed */
411 reg |= GM_GPCR_AU_ALL_DIS;
413 switch (sky2->speed) {
415 ctrl |= PHY_CT_SP1000;
416 reg |= GM_GPCR_SPEED_1000;
419 ctrl |= PHY_CT_SP100;
420 reg |= GM_GPCR_SPEED_100;
424 if (sky2->duplex == DUPLEX_FULL) {
425 reg |= GM_GPCR_DUP_FULL;
426 ctrl |= PHY_CT_DUP_MD;
427 } else if (sky2->speed != SPEED_1000 && hw->chip_id != CHIP_ID_YUKON_EC_U) {
428 /* Turn off flow control for 10/100mbps */
434 reg |= GM_GPCR_FC_RX_DIS;
437 reg |= GM_GPCR_FC_TX_DIS;
439 /* Forward pause packets to GMAC? */
440 if (sky2->tx_pause || sky2->rx_pause)
441 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON);
443 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
446 gma_write16(hw, port, GM_GP_CTRL, reg);
448 if (hw->chip_id != CHIP_ID_YUKON_FE)
449 gm_phy_write(hw, port, PHY_MARV_1000T_CTRL, ct1000);
451 gm_phy_write(hw, port, PHY_MARV_AUNE_ADV, adv);
452 gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
454 /* Setup Phy LED's */
455 ledctrl = PHY_M_LED_PULS_DUR(PULS_170MS);
458 switch (hw->chip_id) {
459 case CHIP_ID_YUKON_FE:
460 /* on 88E3082 these bits are at 11..9 (shifted left) */
461 ledctrl |= PHY_M_LED_BLINK_RT(BLINK_84MS) << 1;
463 ctrl = gm_phy_read(hw, port, PHY_MARV_FE_LED_PAR);
465 /* delete ACT LED control bits */
466 ctrl &= ~PHY_M_FELP_LED1_MSK;
467 /* change ACT LED control to blink mode */
468 ctrl |= PHY_M_FELP_LED1_CTRL(LED_PAR_CTRL_ACT_BL);
469 gm_phy_write(hw, port, PHY_MARV_FE_LED_PAR, ctrl);
472 case CHIP_ID_YUKON_XL:
473 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
475 /* select page 3 to access LED control register */
476 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
478 /* set LED Function Control register */
479 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
480 (PHY_M_LEDC_LOS_CTRL(1) | /* LINK/ACT */
481 PHY_M_LEDC_INIT_CTRL(7) | /* 10 Mbps */
482 PHY_M_LEDC_STA1_CTRL(7) | /* 100 Mbps */
483 PHY_M_LEDC_STA0_CTRL(7))); /* 1000 Mbps */
485 /* set Polarity Control register */
486 gm_phy_write(hw, port, PHY_MARV_PHY_STAT,
487 (PHY_M_POLC_LS1_P_MIX(4) |
488 PHY_M_POLC_IS0_P_MIX(4) |
489 PHY_M_POLC_LOS_CTRL(2) |
490 PHY_M_POLC_INIT_CTRL(2) |
491 PHY_M_POLC_STA1_CTRL(2) |
492 PHY_M_POLC_STA0_CTRL(2)));
494 /* restore page register */
495 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
497 case CHIP_ID_YUKON_EC_U:
498 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
500 /* select page 3 to access LED control register */
501 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
503 /* set LED Function Control register */
504 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
505 (PHY_M_LEDC_LOS_CTRL(1) | /* LINK/ACT */
506 PHY_M_LEDC_INIT_CTRL(8) | /* 10 Mbps */
507 PHY_M_LEDC_STA1_CTRL(7) | /* 100 Mbps */
508 PHY_M_LEDC_STA0_CTRL(7)));/* 1000 Mbps */
510 /* set Blink Rate in LED Timer Control Register */
511 gm_phy_write(hw, port, PHY_MARV_INT_MASK,
512 ledctrl | PHY_M_LED_BLINK_RT(BLINK_84MS));
513 /* restore page register */
514 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
518 /* set Tx LED (LED_TX) to blink mode on Rx OR Tx activity */
519 ledctrl |= PHY_M_LED_BLINK_RT(BLINK_84MS) | PHY_M_LEDC_TX_CTRL;
520 /* turn off the Rx LED (LED_RX) */
521 ledover |= PHY_M_LED_MO_RX(MO_LED_OFF);
524 if (hw->chip_id == CHIP_ID_YUKON_EC_U && hw->chip_rev == CHIP_REV_YU_EC_A1) {
525 /* apply fixes in PHY AFE */
526 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
527 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 255);
529 /* increase differential signal amplitude in 10BASE-T */
530 gm_phy_write(hw, port, 0x18, 0xaa99);
531 gm_phy_write(hw, port, 0x17, 0x2011);
533 /* fix for IEEE A/B Symmetry failure in 1000BASE-T */
534 gm_phy_write(hw, port, 0x18, 0xa204);
535 gm_phy_write(hw, port, 0x17, 0x2002);
537 /* set page register to 0 */
538 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
540 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, ledctrl);
542 if (sky2->autoneg == AUTONEG_DISABLE || sky2->speed == SPEED_100) {
543 /* turn on 100 Mbps LED (LED_LINK100) */
544 ledover |= PHY_M_LED_MO_100(MO_LED_ON);
548 gm_phy_write(hw, port, PHY_MARV_LED_OVER, ledover);
552 /* Enable phy interrupt on auto-negotiation complete (or link up) */
553 if (sky2->autoneg == AUTONEG_ENABLE)
554 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_IS_AN_COMPL);
556 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_DEF_MSK);
559 static void sky2_phy_power(struct sky2_hw *hw, unsigned port, int onoff)
562 static const u32 phy_power[]
563 = { PCI_Y2_PHY1_POWD, PCI_Y2_PHY2_POWD };
565 /* looks like this XL is back asswards .. */
566 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1)
569 reg1 = sky2_pci_read32(hw, PCI_DEV_REG1);
572 /* Turn off phy power saving */
573 reg1 &= ~phy_power[port];
575 reg1 |= phy_power[port];
577 sky2_pci_write32(hw, PCI_DEV_REG1, reg1);
578 sky2_pci_read32(hw, PCI_DEV_REG1);
582 /* Force a renegotiation */
583 static void sky2_phy_reinit(struct sky2_port *sky2)
585 spin_lock_bh(&sky2->phy_lock);
586 sky2_phy_init(sky2->hw, sky2->port);
587 spin_unlock_bh(&sky2->phy_lock);
590 static void sky2_mac_init(struct sky2_hw *hw, unsigned port)
592 struct sky2_port *sky2 = netdev_priv(hw->dev[port]);
595 const u8 *addr = hw->dev[port]->dev_addr;
597 sky2_write32(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET);
598 sky2_write32(hw, SK_REG(port, GPHY_CTRL), GPC_RST_CLR|GPC_ENA_PAUSE);
600 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_CLR);
602 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0 && port == 1) {
603 /* WA DEV_472 -- looks like crossed wires on port 2 */
604 /* clear GMAC 1 Control reset */
605 sky2_write8(hw, SK_REG(0, GMAC_CTRL), GMC_RST_CLR);
607 sky2_write8(hw, SK_REG(1, GMAC_CTRL), GMC_RST_SET);
608 sky2_write8(hw, SK_REG(1, GMAC_CTRL), GMC_RST_CLR);
609 } while (gm_phy_read(hw, 1, PHY_MARV_ID0) != PHY_MARV_ID0_VAL ||
610 gm_phy_read(hw, 1, PHY_MARV_ID1) != PHY_MARV_ID1_Y2 ||
611 gm_phy_read(hw, 1, PHY_MARV_INT_MASK) != 0);
614 sky2_read16(hw, SK_REG(port, GMAC_IRQ_SRC));
616 /* Enable Transmit FIFO Underrun */
617 sky2_write8(hw, SK_REG(port, GMAC_IRQ_MSK), GMAC_DEF_MSK);
619 spin_lock_bh(&sky2->phy_lock);
620 sky2_phy_init(hw, port);
621 spin_unlock_bh(&sky2->phy_lock);
624 reg = gma_read16(hw, port, GM_PHY_ADDR);
625 gma_write16(hw, port, GM_PHY_ADDR, reg | GM_PAR_MIB_CLR);
627 for (i = GM_MIB_CNT_BASE; i <= GM_MIB_CNT_END; i += 4)
628 gma_read16(hw, port, i);
629 gma_write16(hw, port, GM_PHY_ADDR, reg);
631 /* transmit control */
632 gma_write16(hw, port, GM_TX_CTRL, TX_COL_THR(TX_COL_DEF));
634 /* receive control reg: unicast + multicast + no FCS */
635 gma_write16(hw, port, GM_RX_CTRL,
636 GM_RXCR_UCF_ENA | GM_RXCR_CRC_DIS | GM_RXCR_MCF_ENA);
638 /* transmit flow control */
639 gma_write16(hw, port, GM_TX_FLOW_CTRL, 0xffff);
641 /* transmit parameter */
642 gma_write16(hw, port, GM_TX_PARAM,
643 TX_JAM_LEN_VAL(TX_JAM_LEN_DEF) |
644 TX_JAM_IPG_VAL(TX_JAM_IPG_DEF) |
645 TX_IPG_JAM_DATA(TX_IPG_JAM_DEF) |
646 TX_BACK_OFF_LIM(TX_BOF_LIM_DEF));
648 /* serial mode register */
649 reg = DATA_BLIND_VAL(DATA_BLIND_DEF) |
650 GM_SMOD_VLAN_ENA | IPG_DATA_VAL(IPG_DATA_DEF);
652 if (hw->dev[port]->mtu > ETH_DATA_LEN)
653 reg |= GM_SMOD_JUMBO_ENA;
655 gma_write16(hw, port, GM_SERIAL_MODE, reg);
657 /* virtual address for data */
658 gma_set_addr(hw, port, GM_SRC_ADDR_2L, addr);
660 /* physical address: used for pause frames */
661 gma_set_addr(hw, port, GM_SRC_ADDR_1L, addr);
663 /* ignore counter overflows */
664 gma_write16(hw, port, GM_TX_IRQ_MSK, 0);
665 gma_write16(hw, port, GM_RX_IRQ_MSK, 0);
666 gma_write16(hw, port, GM_TR_IRQ_MSK, 0);
668 /* Configure Rx MAC FIFO */
669 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_CLR);
670 sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T),
671 GMF_OPER_ON | GMF_RX_F_FL_ON);
673 /* Flush Rx MAC FIFO on any flow control or error */
674 sky2_write16(hw, SK_REG(port, RX_GMF_FL_MSK), GMR_FS_ANY_ERR);
676 /* Set threshold to 0xa (64 bytes)
677 * ASF disabled so no need to do WA dev #4.30
679 sky2_write16(hw, SK_REG(port, RX_GMF_FL_THR), RX_GMF_FL_THR_DEF);
681 /* Configure Tx MAC FIFO */
682 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_CLR);
683 sky2_write16(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_OPER_ON);
685 if (hw->chip_id == CHIP_ID_YUKON_EC_U) {
686 sky2_write8(hw, SK_REG(port, RX_GMF_LP_THR), 512/8);
687 sky2_write8(hw, SK_REG(port, RX_GMF_UP_THR), 1024/8);
688 if (hw->dev[port]->mtu > ETH_DATA_LEN) {
689 /* set Tx GMAC FIFO Almost Empty Threshold */
690 sky2_write32(hw, SK_REG(port, TX_GMF_AE_THR), 0x180);
691 /* Disable Store & Forward mode for TX */
692 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T), TX_STFW_DIS);
698 /* Assign Ram Buffer allocation.
699 * start and end are in units of 4k bytes
700 * ram registers are in units of 64bit words
702 static void sky2_ramset(struct sky2_hw *hw, u16 q, u8 startk, u8 endk)
706 start = startk * 4096/8;
707 end = (endk * 4096/8) - 1;
709 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_RST_CLR);
710 sky2_write32(hw, RB_ADDR(q, RB_START), start);
711 sky2_write32(hw, RB_ADDR(q, RB_END), end);
712 sky2_write32(hw, RB_ADDR(q, RB_WP), start);
713 sky2_write32(hw, RB_ADDR(q, RB_RP), start);
715 if (q == Q_R1 || q == Q_R2) {
716 u32 space = (endk - startk) * 4096/8;
717 u32 tp = space - space/4;
719 /* On receive queue's set the thresholds
720 * give receiver priority when > 3/4 full
721 * send pause when down to 2K
723 sky2_write32(hw, RB_ADDR(q, RB_RX_UTHP), tp);
724 sky2_write32(hw, RB_ADDR(q, RB_RX_LTHP), space/2);
727 sky2_write32(hw, RB_ADDR(q, RB_RX_UTPP), tp);
728 sky2_write32(hw, RB_ADDR(q, RB_RX_LTPP), space/4);
730 /* Enable store & forward on Tx queue's because
731 * Tx FIFO is only 1K on Yukon
733 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_STFWD);
736 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_OP_MD);
737 sky2_read8(hw, RB_ADDR(q, RB_CTRL));
740 /* Setup Bus Memory Interface */
741 static void sky2_qset(struct sky2_hw *hw, u16 q)
743 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_CLR_RESET);
744 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_OPER_INIT);
745 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_FIFO_OP_ON);
746 sky2_write32(hw, Q_ADDR(q, Q_WM), BMU_WM_DEFAULT);
749 /* Setup prefetch unit registers. This is the interface between
750 * hardware and driver list elements
752 static void sky2_prefetch_init(struct sky2_hw *hw, u32 qaddr,
755 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_RST_SET);
756 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_RST_CLR);
757 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_ADDR_HI), addr >> 32);
758 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_ADDR_LO), (u32) addr);
759 sky2_write16(hw, Y2_QADDR(qaddr, PREF_UNIT_LAST_IDX), last);
760 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_OP_ON);
762 sky2_read32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL));
765 static inline struct sky2_tx_le *get_tx_le(struct sky2_port *sky2)
767 struct sky2_tx_le *le = sky2->tx_le + sky2->tx_prod;
769 sky2->tx_prod = RING_NEXT(sky2->tx_prod, TX_RING_SIZE);
774 static inline struct tx_ring_info *tx_le_re(struct sky2_port *sky2,
775 struct sky2_tx_le *le)
777 return sky2->tx_ring + (le - sky2->tx_le);
780 /* Update chip's next pointer */
781 static inline void sky2_put_idx(struct sky2_hw *hw, unsigned q, u16 idx)
783 q = Y2_QADDR(q, PREF_UNIT_PUT_IDX);
785 sky2_write16(hw, q, idx);
790 static inline struct sky2_rx_le *sky2_next_rx(struct sky2_port *sky2)
792 struct sky2_rx_le *le = sky2->rx_le + sky2->rx_put;
793 sky2->rx_put = RING_NEXT(sky2->rx_put, RX_LE_SIZE);
798 /* Return high part of DMA address (could be 32 or 64 bit) */
799 static inline u32 high32(dma_addr_t a)
801 return sizeof(a) > sizeof(u32) ? (a >> 16) >> 16 : 0;
804 /* Build description to hardware for one receive segment */
805 static void sky2_rx_add(struct sky2_port *sky2, u8 op,
806 dma_addr_t map, unsigned len)
808 struct sky2_rx_le *le;
809 u32 hi = high32(map);
811 if (sky2->rx_addr64 != hi) {
812 le = sky2_next_rx(sky2);
813 le->addr = cpu_to_le32(hi);
814 le->opcode = OP_ADDR64 | HW_OWNER;
815 sky2->rx_addr64 = high32(map + len);
818 le = sky2_next_rx(sky2);
819 le->addr = cpu_to_le32((u32) map);
820 le->length = cpu_to_le16(len);
821 le->opcode = op | HW_OWNER;
824 /* Build description to hardware for one possibly fragmented skb */
825 static void sky2_rx_submit(struct sky2_port *sky2,
826 const struct rx_ring_info *re)
830 sky2_rx_add(sky2, OP_PACKET, re->data_addr, sky2->rx_data_size);
832 for (i = 0; i < skb_shinfo(re->skb)->nr_frags; i++)
833 sky2_rx_add(sky2, OP_BUFFER, re->frag_addr[i], PAGE_SIZE);
837 static void sky2_rx_map_skb(struct pci_dev *pdev, struct rx_ring_info *re,
840 struct sk_buff *skb = re->skb;
843 re->data_addr = pci_map_single(pdev, skb->data, size, PCI_DMA_FROMDEVICE);
844 pci_unmap_len_set(re, data_size, size);
846 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++)
847 re->frag_addr[i] = pci_map_page(pdev,
848 skb_shinfo(skb)->frags[i].page,
849 skb_shinfo(skb)->frags[i].page_offset,
850 skb_shinfo(skb)->frags[i].size,
854 static void sky2_rx_unmap_skb(struct pci_dev *pdev, struct rx_ring_info *re)
856 struct sk_buff *skb = re->skb;
859 pci_unmap_single(pdev, re->data_addr, pci_unmap_len(re, data_size),
862 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++)
863 pci_unmap_page(pdev, re->frag_addr[i],
864 skb_shinfo(skb)->frags[i].size,
868 /* Tell chip where to start receive checksum.
869 * Actually has two checksums, but set both same to avoid possible byte
872 static void rx_set_checksum(struct sky2_port *sky2)
874 struct sky2_rx_le *le;
876 le = sky2_next_rx(sky2);
877 le->addr = cpu_to_le32((ETH_HLEN << 16) | ETH_HLEN);
879 le->opcode = OP_TCPSTART | HW_OWNER;
881 sky2_write32(sky2->hw,
882 Q_ADDR(rxqaddr[sky2->port], Q_CSR),
883 sky2->rx_csum ? BMU_ENA_RX_CHKSUM : BMU_DIS_RX_CHKSUM);
888 * The RX Stop command will not work for Yukon-2 if the BMU does not
889 * reach the end of packet and since we can't make sure that we have
890 * incoming data, we must reset the BMU while it is not doing a DMA
891 * transfer. Since it is possible that the RX path is still active,
892 * the RX RAM buffer will be stopped first, so any possible incoming
893 * data will not trigger a DMA. After the RAM buffer is stopped, the
894 * BMU is polled until any DMA in progress is ended and only then it
897 static void sky2_rx_stop(struct sky2_port *sky2)
899 struct sky2_hw *hw = sky2->hw;
900 unsigned rxq = rxqaddr[sky2->port];
903 /* disable the RAM Buffer receive queue */
904 sky2_write8(hw, RB_ADDR(rxq, RB_CTRL), RB_DIS_OP_MD);
906 for (i = 0; i < 0xffff; i++)
907 if (sky2_read8(hw, RB_ADDR(rxq, Q_RSL))
908 == sky2_read8(hw, RB_ADDR(rxq, Q_RL)))
911 printk(KERN_WARNING PFX "%s: receiver stop failed\n",
914 sky2_write32(hw, Q_ADDR(rxq, Q_CSR), BMU_RST_SET | BMU_FIFO_RST);
916 /* reset the Rx prefetch unit */
917 sky2_write32(hw, Y2_QADDR(rxq, PREF_UNIT_CTRL), PREF_UNIT_RST_SET);
920 /* Clean out receive buffer area, assumes receiver hardware stopped */
921 static void sky2_rx_clean(struct sky2_port *sky2)
925 memset(sky2->rx_le, 0, RX_LE_BYTES);
926 for (i = 0; i < sky2->rx_pending; i++) {
927 struct rx_ring_info *re = sky2->rx_ring + i;
930 sky2_rx_unmap_skb(sky2->hw->pdev, re);
937 /* Basic MII support */
938 static int sky2_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
940 struct mii_ioctl_data *data = if_mii(ifr);
941 struct sky2_port *sky2 = netdev_priv(dev);
942 struct sky2_hw *hw = sky2->hw;
943 int err = -EOPNOTSUPP;
945 if (!netif_running(dev))
946 return -ENODEV; /* Phy still in reset */
950 data->phy_id = PHY_ADDR_MARV;
956 spin_lock_bh(&sky2->phy_lock);
957 err = __gm_phy_read(hw, sky2->port, data->reg_num & 0x1f, &val);
958 spin_unlock_bh(&sky2->phy_lock);
965 if (!capable(CAP_NET_ADMIN))
968 spin_lock_bh(&sky2->phy_lock);
969 err = gm_phy_write(hw, sky2->port, data->reg_num & 0x1f,
971 spin_unlock_bh(&sky2->phy_lock);
977 #ifdef SKY2_VLAN_TAG_USED
978 static void sky2_vlan_rx_register(struct net_device *dev, struct vlan_group *grp)
980 struct sky2_port *sky2 = netdev_priv(dev);
981 struct sky2_hw *hw = sky2->hw;
982 u16 port = sky2->port;
984 netif_tx_lock_bh(dev);
986 sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T), RX_VLAN_STRIP_ON);
987 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T), TX_VLAN_TAG_ON);
990 netif_tx_unlock_bh(dev);
993 static void sky2_vlan_rx_kill_vid(struct net_device *dev, unsigned short vid)
995 struct sky2_port *sky2 = netdev_priv(dev);
996 struct sky2_hw *hw = sky2->hw;
997 u16 port = sky2->port;
999 netif_tx_lock_bh(dev);
1001 sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T), RX_VLAN_STRIP_OFF);
1002 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T), TX_VLAN_TAG_OFF);
1004 sky2->vlgrp->vlan_devices[vid] = NULL;
1006 netif_tx_unlock_bh(dev);
1011 * Allocate an skb for receiving. If the MTU is large enough
1012 * make the skb non-linear with a fragment list of pages.
1014 * It appears the hardware has a bug in the FIFO logic that
1015 * cause it to hang if the FIFO gets overrun and the receive buffer
1016 * is not 64 byte aligned. The buffer returned from netdev_alloc_skb is
1017 * aligned except if slab debugging is enabled.
1019 static struct sk_buff *sky2_rx_alloc(struct sky2_port *sky2)
1021 struct sk_buff *skb;
1025 skb = netdev_alloc_skb(sky2->netdev, sky2->rx_data_size + RX_SKB_ALIGN);
1029 p = (unsigned long) skb->data;
1030 skb_reserve(skb, ALIGN(p, RX_SKB_ALIGN) - p);
1032 for (i = 0; i < sky2->rx_nfrags; i++) {
1033 struct page *page = alloc_page(GFP_ATOMIC);
1037 skb_fill_page_desc(skb, i, page, 0, PAGE_SIZE);
1048 * Allocate and setup receiver buffer pool.
1049 * Normal case this ends up creating one list element for skb
1050 * in the receive ring. Worst case if using large MTU and each
1051 * allocation falls on a different 64 bit region, that results
1052 * in 6 list elements per ring entry.
1053 * One element is used for checksum enable/disable, and one
1054 * extra to avoid wrap.
1056 static int sky2_rx_start(struct sky2_port *sky2)
1058 struct sky2_hw *hw = sky2->hw;
1059 struct rx_ring_info *re;
1060 unsigned rxq = rxqaddr[sky2->port];
1061 unsigned i, size, space, thresh;
1063 sky2->rx_put = sky2->rx_next = 0;
1066 if (hw->chip_id == CHIP_ID_YUKON_EC_U && hw->chip_rev >= 2) {
1067 /* MAC Rx RAM Read is controlled by hardware */
1068 sky2_write32(hw, Q_ADDR(rxq, Q_F), F_M_RX_RAM_DIS);
1071 sky2_prefetch_init(hw, rxq, sky2->rx_le_map, RX_LE_SIZE - 1);
1073 rx_set_checksum(sky2);
1075 /* Space needed for frame data + headers rounded up */
1076 size = ALIGN(sky2->netdev->mtu + ETH_HLEN + VLAN_HLEN, 8)
1079 /* Stopping point for hardware truncation */
1080 thresh = (size - 8) / sizeof(u32);
1082 /* Account for overhead of skb - to avoid order > 0 allocation */
1083 space = SKB_DATA_ALIGN(size) + NET_SKB_PAD
1084 + sizeof(struct skb_shared_info);
1086 sky2->rx_nfrags = space >> PAGE_SHIFT;
1087 BUG_ON(sky2->rx_nfrags > ARRAY_SIZE(re->frag_addr));
1089 if (sky2->rx_nfrags != 0) {
1090 /* Compute residue after pages */
1091 space = sky2->rx_nfrags << PAGE_SHIFT;
1098 /* Optimize to handle small packets and headers */
1099 if (size < copybreak)
1101 if (size < ETH_HLEN)
1104 sky2->rx_data_size = size;
1107 for (i = 0; i < sky2->rx_pending; i++) {
1108 re = sky2->rx_ring + i;
1110 re->skb = sky2_rx_alloc(sky2);
1114 sky2_rx_map_skb(hw->pdev, re, sky2->rx_data_size);
1115 sky2_rx_submit(sky2, re);
1119 * The receiver hangs if it receives frames larger than the
1120 * packet buffer. As a workaround, truncate oversize frames, but
1121 * the register is limited to 9 bits, so if you do frames > 2052
1122 * you better get the MTU right!
1125 sky2_write32(hw, SK_REG(sky2->port, RX_GMF_CTRL_T), RX_TRUNC_OFF);
1127 sky2_write16(hw, SK_REG(sky2->port, RX_GMF_TR_THR), thresh);
1128 sky2_write32(hw, SK_REG(sky2->port, RX_GMF_CTRL_T), RX_TRUNC_ON);
1131 /* Tell chip about available buffers */
1132 sky2_write16(hw, Y2_QADDR(rxq, PREF_UNIT_PUT_IDX), sky2->rx_put);
1135 sky2_rx_clean(sky2);
1139 /* Bring up network interface. */
1140 static int sky2_up(struct net_device *dev)
1142 struct sky2_port *sky2 = netdev_priv(dev);
1143 struct sky2_hw *hw = sky2->hw;
1144 unsigned port = sky2->port;
1145 u32 ramsize, rxspace, imask;
1146 int cap, err = -ENOMEM;
1147 struct net_device *otherdev = hw->dev[sky2->port^1];
1150 * On dual port PCI-X card, there is an problem where status
1151 * can be received out of order due to split transactions
1153 if (otherdev && netif_running(otherdev) &&
1154 (cap = pci_find_capability(hw->pdev, PCI_CAP_ID_PCIX))) {
1155 struct sky2_port *osky2 = netdev_priv(otherdev);
1158 cmd = sky2_pci_read16(hw, cap + PCI_X_CMD);
1159 cmd &= ~PCI_X_CMD_MAX_SPLIT;
1160 sky2_pci_write16(hw, cap + PCI_X_CMD, cmd);
1166 if (netif_msg_ifup(sky2))
1167 printk(KERN_INFO PFX "%s: enabling interface\n", dev->name);
1169 /* must be power of 2 */
1170 sky2->tx_le = pci_alloc_consistent(hw->pdev,
1172 sizeof(struct sky2_tx_le),
1177 sky2->tx_ring = kcalloc(TX_RING_SIZE, sizeof(struct tx_ring_info),
1181 sky2->tx_prod = sky2->tx_cons = 0;
1183 sky2->rx_le = pci_alloc_consistent(hw->pdev, RX_LE_BYTES,
1187 memset(sky2->rx_le, 0, RX_LE_BYTES);
1189 sky2->rx_ring = kcalloc(sky2->rx_pending, sizeof(struct rx_ring_info),
1194 sky2_phy_power(hw, port, 1);
1196 sky2_mac_init(hw, port);
1198 /* Determine available ram buffer space (in 4K blocks).
1199 * Note: not sure about the FE setting below yet
1201 if (hw->chip_id == CHIP_ID_YUKON_FE)
1204 ramsize = sky2_read8(hw, B2_E_0);
1206 /* Give transmitter one third (rounded up) */
1207 rxspace = ramsize - (ramsize + 2) / 3;
1209 sky2_ramset(hw, rxqaddr[port], 0, rxspace);
1210 sky2_ramset(hw, txqaddr[port], rxspace, ramsize);
1212 /* Make sure SyncQ is disabled */
1213 sky2_write8(hw, RB_ADDR(port == 0 ? Q_XS1 : Q_XS2, RB_CTRL),
1216 sky2_qset(hw, txqaddr[port]);
1218 /* Set almost empty threshold */
1219 if (hw->chip_id == CHIP_ID_YUKON_EC_U
1220 && hw->chip_rev == CHIP_REV_YU_EC_U_A0)
1221 sky2_write16(hw, Q_ADDR(txqaddr[port], Q_AL), 0x1a0);
1223 sky2_prefetch_init(hw, txqaddr[port], sky2->tx_le_map,
1226 err = sky2_rx_start(sky2);
1230 /* Enable interrupts from phy/mac for port */
1231 imask = sky2_read32(hw, B0_IMSK);
1232 imask |= portirq_msk[port];
1233 sky2_write32(hw, B0_IMSK, imask);
1239 pci_free_consistent(hw->pdev, RX_LE_BYTES,
1240 sky2->rx_le, sky2->rx_le_map);
1244 pci_free_consistent(hw->pdev,
1245 TX_RING_SIZE * sizeof(struct sky2_tx_le),
1246 sky2->tx_le, sky2->tx_le_map);
1249 kfree(sky2->tx_ring);
1250 kfree(sky2->rx_ring);
1252 sky2->tx_ring = NULL;
1253 sky2->rx_ring = NULL;
1257 /* Modular subtraction in ring */
1258 static inline int tx_dist(unsigned tail, unsigned head)
1260 return (head - tail) & (TX_RING_SIZE - 1);
1263 /* Number of list elements available for next tx */
1264 static inline int tx_avail(const struct sky2_port *sky2)
1266 return sky2->tx_pending - tx_dist(sky2->tx_cons, sky2->tx_prod);
1269 /* Estimate of number of transmit list elements required */
1270 static unsigned tx_le_req(const struct sk_buff *skb)
1274 count = sizeof(dma_addr_t) / sizeof(u32);
1275 count += skb_shinfo(skb)->nr_frags * count;
1277 if (skb_is_gso(skb))
1280 if (skb->ip_summed == CHECKSUM_PARTIAL)
1287 * Put one packet in ring for transmit.
1288 * A single packet can generate multiple list elements, and
1289 * the number of ring elements will probably be less than the number
1290 * of list elements used.
1292 static int sky2_xmit_frame(struct sk_buff *skb, struct net_device *dev)
1294 struct sky2_port *sky2 = netdev_priv(dev);
1295 struct sky2_hw *hw = sky2->hw;
1296 struct sky2_tx_le *le = NULL;
1297 struct tx_ring_info *re;
1304 if (unlikely(tx_avail(sky2) < tx_le_req(skb)))
1305 return NETDEV_TX_BUSY;
1307 if (unlikely(netif_msg_tx_queued(sky2)))
1308 printk(KERN_DEBUG "%s: tx queued, slot %u, len %d\n",
1309 dev->name, sky2->tx_prod, skb->len);
1311 len = skb_headlen(skb);
1312 mapping = pci_map_single(hw->pdev, skb->data, len, PCI_DMA_TODEVICE);
1313 addr64 = high32(mapping);
1315 /* Send high bits if changed or crosses boundary */
1316 if (addr64 != sky2->tx_addr64 || high32(mapping + len) != sky2->tx_addr64) {
1317 le = get_tx_le(sky2);
1318 le->addr = cpu_to_le32(addr64);
1319 le->opcode = OP_ADDR64 | HW_OWNER;
1320 sky2->tx_addr64 = high32(mapping + len);
1323 /* Check for TCP Segmentation Offload */
1324 mss = skb_shinfo(skb)->gso_size;
1326 mss += ((skb->h.th->doff - 5) * 4); /* TCP options */
1327 mss += (skb->nh.iph->ihl * 4) + sizeof(struct tcphdr);
1330 if (mss != sky2->tx_last_mss) {
1331 le = get_tx_le(sky2);
1332 le->addr = cpu_to_le32(mss);
1333 le->opcode = OP_LRGLEN | HW_OWNER;
1334 sky2->tx_last_mss = mss;
1339 #ifdef SKY2_VLAN_TAG_USED
1340 /* Add VLAN tag, can piggyback on LRGLEN or ADDR64 */
1341 if (sky2->vlgrp && vlan_tx_tag_present(skb)) {
1343 le = get_tx_le(sky2);
1345 le->opcode = OP_VLAN|HW_OWNER;
1347 le->opcode |= OP_VLAN;
1348 le->length = cpu_to_be16(vlan_tx_tag_get(skb));
1353 /* Handle TCP checksum offload */
1354 if (skb->ip_summed == CHECKSUM_PARTIAL) {
1355 unsigned offset = skb->h.raw - skb->data;
1358 tcpsum = offset << 16; /* sum start */
1359 tcpsum |= offset + skb->csum; /* sum write */
1361 ctrl = CALSUM | WR_SUM | INIT_SUM | LOCK_SUM;
1362 if (skb->nh.iph->protocol == IPPROTO_UDP)
1365 if (tcpsum != sky2->tx_tcpsum) {
1366 sky2->tx_tcpsum = tcpsum;
1368 le = get_tx_le(sky2);
1369 le->addr = cpu_to_le32(tcpsum);
1370 le->length = 0; /* initial checksum value */
1371 le->ctrl = 1; /* one packet */
1372 le->opcode = OP_TCPLISW | HW_OWNER;
1376 le = get_tx_le(sky2);
1377 le->addr = cpu_to_le32((u32) mapping);
1378 le->length = cpu_to_le16(len);
1380 le->opcode = mss ? (OP_LARGESEND | HW_OWNER) : (OP_PACKET | HW_OWNER);
1382 re = tx_le_re(sky2, le);
1384 pci_unmap_addr_set(re, mapaddr, mapping);
1385 pci_unmap_len_set(re, maplen, len);
1387 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
1388 const skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
1390 mapping = pci_map_page(hw->pdev, frag->page, frag->page_offset,
1391 frag->size, PCI_DMA_TODEVICE);
1392 addr64 = high32(mapping);
1393 if (addr64 != sky2->tx_addr64) {
1394 le = get_tx_le(sky2);
1395 le->addr = cpu_to_le32(addr64);
1397 le->opcode = OP_ADDR64 | HW_OWNER;
1398 sky2->tx_addr64 = addr64;
1401 le = get_tx_le(sky2);
1402 le->addr = cpu_to_le32((u32) mapping);
1403 le->length = cpu_to_le16(frag->size);
1405 le->opcode = OP_BUFFER | HW_OWNER;
1407 re = tx_le_re(sky2, le);
1409 pci_unmap_addr_set(re, mapaddr, mapping);
1410 pci_unmap_len_set(re, maplen, frag->size);
1415 if (tx_avail(sky2) <= MAX_SKB_TX_LE)
1416 netif_stop_queue(dev);
1418 sky2_put_idx(hw, txqaddr[sky2->port], sky2->tx_prod);
1420 dev->trans_start = jiffies;
1421 return NETDEV_TX_OK;
1425 * Free ring elements from starting at tx_cons until "done"
1427 * NB: the hardware will tell us about partial completion of multi-part
1428 * buffers so make sure not to free skb to early.
1430 static void sky2_tx_complete(struct sky2_port *sky2, u16 done)
1432 struct net_device *dev = sky2->netdev;
1433 struct pci_dev *pdev = sky2->hw->pdev;
1436 BUG_ON(done >= TX_RING_SIZE);
1438 for (idx = sky2->tx_cons; idx != done;
1439 idx = RING_NEXT(idx, TX_RING_SIZE)) {
1440 struct sky2_tx_le *le = sky2->tx_le + idx;
1441 struct tx_ring_info *re = sky2->tx_ring + idx;
1443 switch(le->opcode & ~HW_OWNER) {
1446 pci_unmap_single(pdev,
1447 pci_unmap_addr(re, mapaddr),
1448 pci_unmap_len(re, maplen),
1452 pci_unmap_page(pdev, pci_unmap_addr(re, mapaddr),
1453 pci_unmap_len(re, maplen),
1458 if (le->ctrl & EOP) {
1459 if (unlikely(netif_msg_tx_done(sky2)))
1460 printk(KERN_DEBUG "%s: tx done %u\n",
1462 dev_kfree_skb(re->skb);
1465 le->opcode = 0; /* paranoia */
1468 sky2->tx_cons = idx;
1469 if (tx_avail(sky2) > MAX_SKB_TX_LE + 4)
1470 netif_wake_queue(dev);
1473 /* Cleanup all untransmitted buffers, assume transmitter not running */
1474 static void sky2_tx_clean(struct net_device *dev)
1476 struct sky2_port *sky2 = netdev_priv(dev);
1478 netif_tx_lock_bh(dev);
1479 sky2_tx_complete(sky2, sky2->tx_prod);
1480 netif_tx_unlock_bh(dev);
1483 /* Network shutdown */
1484 static int sky2_down(struct net_device *dev)
1486 struct sky2_port *sky2 = netdev_priv(dev);
1487 struct sky2_hw *hw = sky2->hw;
1488 unsigned port = sky2->port;
1492 /* Never really got started! */
1496 if (netif_msg_ifdown(sky2))
1497 printk(KERN_INFO PFX "%s: disabling interface\n", dev->name);
1499 /* Stop more packets from being queued */
1500 netif_stop_queue(dev);
1502 /* Disable port IRQ */
1503 imask = sky2_read32(hw, B0_IMSK);
1504 imask &= ~portirq_msk[port];
1505 sky2_write32(hw, B0_IMSK, imask);
1507 sky2_gmac_reset(hw, port);
1509 /* Stop transmitter */
1510 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), BMU_STOP);
1511 sky2_read32(hw, Q_ADDR(txqaddr[port], Q_CSR));
1513 sky2_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL),
1514 RB_RST_SET | RB_DIS_OP_MD);
1516 /* WA for dev. #4.209 */
1517 if (hw->chip_id == CHIP_ID_YUKON_EC_U
1518 && hw->chip_rev == CHIP_REV_YU_EC_U_A1)
1519 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T),
1520 sky2->speed != SPEED_1000 ?
1521 TX_STFW_ENA : TX_STFW_DIS);
1523 ctrl = gma_read16(hw, port, GM_GP_CTRL);
1524 ctrl &= ~(GM_GPCR_TX_ENA | GM_GPCR_RX_ENA);
1525 gma_write16(hw, port, GM_GP_CTRL, ctrl);
1527 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET);
1529 /* Workaround shared GMAC reset */
1530 if (!(hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0
1531 && port == 0 && hw->dev[1] && netif_running(hw->dev[1])))
1532 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_SET);
1534 /* Disable Force Sync bit and Enable Alloc bit */
1535 sky2_write8(hw, SK_REG(port, TXA_CTRL),
1536 TXA_DIS_FSYNC | TXA_DIS_ALLOC | TXA_STOP_RC);
1538 /* Stop Interval Timer and Limit Counter of Tx Arbiter */
1539 sky2_write32(hw, SK_REG(port, TXA_ITI_INI), 0L);
1540 sky2_write32(hw, SK_REG(port, TXA_LIM_INI), 0L);
1542 /* Reset the PCI FIFO of the async Tx queue */
1543 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR),
1544 BMU_RST_SET | BMU_FIFO_RST);
1546 /* Reset the Tx prefetch units */
1547 sky2_write32(hw, Y2_QADDR(txqaddr[port], PREF_UNIT_CTRL),
1550 sky2_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL), RB_RST_SET);
1554 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_SET);
1555 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_SET);
1557 sky2_phy_power(hw, port, 0);
1559 /* turn off LED's */
1560 sky2_write16(hw, B0_Y2LED, LED_STAT_OFF);
1562 synchronize_irq(hw->pdev->irq);
1565 sky2_rx_clean(sky2);
1567 pci_free_consistent(hw->pdev, RX_LE_BYTES,
1568 sky2->rx_le, sky2->rx_le_map);
1569 kfree(sky2->rx_ring);
1571 pci_free_consistent(hw->pdev,
1572 TX_RING_SIZE * sizeof(struct sky2_tx_le),
1573 sky2->tx_le, sky2->tx_le_map);
1574 kfree(sky2->tx_ring);
1579 sky2->rx_ring = NULL;
1580 sky2->tx_ring = NULL;
1585 static u16 sky2_phy_speed(const struct sky2_hw *hw, u16 aux)
1587 if (!sky2_is_copper(hw))
1590 if (hw->chip_id == CHIP_ID_YUKON_FE)
1591 return (aux & PHY_M_PS_SPEED_100) ? SPEED_100 : SPEED_10;
1593 switch (aux & PHY_M_PS_SPEED_MSK) {
1594 case PHY_M_PS_SPEED_1000:
1596 case PHY_M_PS_SPEED_100:
1603 static void sky2_link_up(struct sky2_port *sky2)
1605 struct sky2_hw *hw = sky2->hw;
1606 unsigned port = sky2->port;
1610 reg = gma_read16(hw, port, GM_GP_CTRL);
1611 reg |= GM_GPCR_RX_ENA | GM_GPCR_TX_ENA;
1612 gma_write16(hw, port, GM_GP_CTRL, reg);
1614 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_DEF_MSK);
1616 netif_carrier_on(sky2->netdev);
1617 netif_wake_queue(sky2->netdev);
1619 /* Turn on link LED */
1620 sky2_write8(hw, SK_REG(port, LNK_LED_REG),
1621 LINKLED_ON | LINKLED_BLINK_OFF | LINKLED_LINKSYNC_OFF);
1623 if (hw->chip_id == CHIP_ID_YUKON_XL || hw->chip_id == CHIP_ID_YUKON_EC_U) {
1624 u16 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
1625 u16 led = PHY_M_LEDC_LOS_CTRL(1); /* link active */
1627 switch(sky2->speed) {
1629 led |= PHY_M_LEDC_INIT_CTRL(7);
1633 led |= PHY_M_LEDC_STA1_CTRL(7);
1637 led |= PHY_M_LEDC_STA0_CTRL(7);
1641 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
1642 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, led);
1643 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
1646 if (netif_msg_link(sky2))
1647 printk(KERN_INFO PFX
1648 "%s: Link is up at %d Mbps, %s duplex, flow control %s\n",
1649 sky2->netdev->name, sky2->speed,
1650 sky2->duplex == DUPLEX_FULL ? "full" : "half",
1651 (sky2->tx_pause && sky2->rx_pause) ? "both" :
1652 sky2->tx_pause ? "tx" : sky2->rx_pause ? "rx" : "none");
1655 static void sky2_link_down(struct sky2_port *sky2)
1657 struct sky2_hw *hw = sky2->hw;
1658 unsigned port = sky2->port;
1661 gm_phy_write(hw, port, PHY_MARV_INT_MASK, 0);
1663 reg = gma_read16(hw, port, GM_GP_CTRL);
1664 reg &= ~(GM_GPCR_RX_ENA | GM_GPCR_TX_ENA);
1665 gma_write16(hw, port, GM_GP_CTRL, reg);
1667 if (sky2->rx_pause && !sky2->tx_pause) {
1668 /* restore Asymmetric Pause bit */
1669 gm_phy_write(hw, port, PHY_MARV_AUNE_ADV,
1670 gm_phy_read(hw, port, PHY_MARV_AUNE_ADV)
1674 netif_carrier_off(sky2->netdev);
1675 netif_stop_queue(sky2->netdev);
1677 /* Turn on link LED */
1678 sky2_write8(hw, SK_REG(port, LNK_LED_REG), LINKLED_OFF);
1680 if (netif_msg_link(sky2))
1681 printk(KERN_INFO PFX "%s: Link is down.\n", sky2->netdev->name);
1683 sky2_phy_init(hw, port);
1686 static int sky2_autoneg_done(struct sky2_port *sky2, u16 aux)
1688 struct sky2_hw *hw = sky2->hw;
1689 unsigned port = sky2->port;
1692 lpa = gm_phy_read(hw, port, PHY_MARV_AUNE_LP);
1694 if (lpa & PHY_M_AN_RF) {
1695 printk(KERN_ERR PFX "%s: remote fault", sky2->netdev->name);
1699 if (!(aux & PHY_M_PS_SPDUP_RES)) {
1700 printk(KERN_ERR PFX "%s: speed/duplex mismatch",
1701 sky2->netdev->name);
1705 sky2->speed = sky2_phy_speed(hw, aux);
1706 sky2->duplex = (aux & PHY_M_PS_FULL_DUP) ? DUPLEX_FULL : DUPLEX_HALF;
1708 /* Pause bits are offset (9..8) */
1709 if (hw->chip_id == CHIP_ID_YUKON_XL || hw->chip_id == CHIP_ID_YUKON_EC_U)
1712 sky2->rx_pause = (aux & PHY_M_PS_RX_P_EN) != 0;
1713 sky2->tx_pause = (aux & PHY_M_PS_TX_P_EN) != 0;
1715 if (sky2->duplex == DUPLEX_HALF && sky2->speed != SPEED_1000
1716 && hw->chip_id != CHIP_ID_YUKON_EC_U)
1717 sky2->rx_pause = sky2->tx_pause = 0;
1719 if (sky2->rx_pause || sky2->tx_pause)
1720 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON);
1722 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
1727 /* Interrupt from PHY */
1728 static void sky2_phy_intr(struct sky2_hw *hw, unsigned port)
1730 struct net_device *dev = hw->dev[port];
1731 struct sky2_port *sky2 = netdev_priv(dev);
1732 u16 istatus, phystat;
1734 if (!netif_running(dev))
1737 spin_lock(&sky2->phy_lock);
1738 istatus = gm_phy_read(hw, port, PHY_MARV_INT_STAT);
1739 phystat = gm_phy_read(hw, port, PHY_MARV_PHY_STAT);
1741 if (netif_msg_intr(sky2))
1742 printk(KERN_INFO PFX "%s: phy interrupt status 0x%x 0x%x\n",
1743 sky2->netdev->name, istatus, phystat);
1745 if (sky2->autoneg == AUTONEG_ENABLE && (istatus & PHY_M_IS_AN_COMPL)) {
1746 if (sky2_autoneg_done(sky2, phystat) == 0)
1751 if (istatus & PHY_M_IS_LSP_CHANGE)
1752 sky2->speed = sky2_phy_speed(hw, phystat);
1754 if (istatus & PHY_M_IS_DUP_CHANGE)
1756 (phystat & PHY_M_PS_FULL_DUP) ? DUPLEX_FULL : DUPLEX_HALF;
1758 if (istatus & PHY_M_IS_LST_CHANGE) {
1759 if (phystat & PHY_M_PS_LINK_UP)
1762 sky2_link_down(sky2);
1765 spin_unlock(&sky2->phy_lock);
1769 /* Transmit timeout is only called if we are running, carries is up
1770 * and tx queue is full (stopped).
1772 static void sky2_tx_timeout(struct net_device *dev)
1774 struct sky2_port *sky2 = netdev_priv(dev);
1775 struct sky2_hw *hw = sky2->hw;
1776 unsigned txq = txqaddr[sky2->port];
1779 if (netif_msg_timer(sky2))
1780 printk(KERN_ERR PFX "%s: tx timeout\n", dev->name);
1782 report = sky2_read16(hw, sky2->port == 0 ? STAT_TXA1_RIDX : STAT_TXA2_RIDX);
1783 done = sky2_read16(hw, Q_ADDR(txq, Q_DONE));
1785 printk(KERN_DEBUG PFX "%s: transmit ring %u .. %u report=%u done=%u\n",
1787 sky2->tx_cons, sky2->tx_prod, report, done);
1789 if (report != done) {
1790 printk(KERN_INFO PFX "status burst pending (irq moderation?)\n");
1792 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_STOP);
1793 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_START);
1794 } else if (report != sky2->tx_cons) {
1795 printk(KERN_INFO PFX "status report lost?\n");
1797 netif_tx_lock_bh(dev);
1798 sky2_tx_complete(sky2, report);
1799 netif_tx_unlock_bh(dev);
1801 printk(KERN_INFO PFX "hardware hung? flushing\n");
1803 sky2_write32(hw, Q_ADDR(txq, Q_CSR), BMU_STOP);
1804 sky2_write32(hw, Y2_QADDR(txq, PREF_UNIT_CTRL), PREF_UNIT_RST_SET);
1809 sky2_prefetch_init(hw, txq, sky2->tx_le_map, TX_RING_SIZE - 1);
1813 static int sky2_change_mtu(struct net_device *dev, int new_mtu)
1815 struct sky2_port *sky2 = netdev_priv(dev);
1816 struct sky2_hw *hw = sky2->hw;
1821 if (new_mtu < ETH_ZLEN || new_mtu > ETH_JUMBO_MTU)
1824 if (hw->chip_id == CHIP_ID_YUKON_EC_U && new_mtu > ETH_DATA_LEN)
1827 if (!netif_running(dev)) {
1832 imask = sky2_read32(hw, B0_IMSK);
1833 sky2_write32(hw, B0_IMSK, 0);
1835 dev->trans_start = jiffies; /* prevent tx timeout */
1836 netif_stop_queue(dev);
1837 netif_poll_disable(hw->dev[0]);
1839 synchronize_irq(hw->pdev->irq);
1841 ctl = gma_read16(hw, sky2->port, GM_GP_CTRL);
1842 gma_write16(hw, sky2->port, GM_GP_CTRL, ctl & ~GM_GPCR_RX_ENA);
1844 sky2_rx_clean(sky2);
1848 mode = DATA_BLIND_VAL(DATA_BLIND_DEF) |
1849 GM_SMOD_VLAN_ENA | IPG_DATA_VAL(IPG_DATA_DEF);
1851 if (dev->mtu > ETH_DATA_LEN)
1852 mode |= GM_SMOD_JUMBO_ENA;
1854 gma_write16(hw, sky2->port, GM_SERIAL_MODE, mode);
1856 sky2_write8(hw, RB_ADDR(rxqaddr[sky2->port], RB_CTRL), RB_ENA_OP_MD);
1858 err = sky2_rx_start(sky2);
1859 sky2_write32(hw, B0_IMSK, imask);
1864 gma_write16(hw, sky2->port, GM_GP_CTRL, ctl);
1866 netif_poll_enable(hw->dev[0]);
1867 netif_wake_queue(dev);
1873 /* For small just reuse existing skb for next receive */
1874 static struct sk_buff *receive_copy(struct sky2_port *sky2,
1875 const struct rx_ring_info *re,
1878 struct sk_buff *skb;
1880 skb = netdev_alloc_skb(sky2->netdev, length + 2);
1882 skb_reserve(skb, 2);
1883 pci_dma_sync_single_for_cpu(sky2->hw->pdev, re->data_addr,
1884 length, PCI_DMA_FROMDEVICE);
1885 memcpy(skb->data, re->skb->data, length);
1886 skb->ip_summed = re->skb->ip_summed;
1887 skb->csum = re->skb->csum;
1888 pci_dma_sync_single_for_device(sky2->hw->pdev, re->data_addr,
1889 length, PCI_DMA_FROMDEVICE);
1890 re->skb->ip_summed = CHECKSUM_NONE;
1891 skb_put(skb, length);
1896 /* Adjust length of skb with fragments to match received data */
1897 static void skb_put_frags(struct sk_buff *skb, unsigned int hdr_space,
1898 unsigned int length)
1903 /* put header into skb */
1904 size = min(length, hdr_space);
1909 num_frags = skb_shinfo(skb)->nr_frags;
1910 for (i = 0; i < num_frags; i++) {
1911 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
1914 /* don't need this page */
1915 __free_page(frag->page);
1916 --skb_shinfo(skb)->nr_frags;
1918 size = min(length, (unsigned) PAGE_SIZE);
1921 skb->data_len += size;
1922 skb->truesize += size;
1929 /* Normal packet - take skb from ring element and put in a new one */
1930 static struct sk_buff *receive_new(struct sky2_port *sky2,
1931 struct rx_ring_info *re,
1932 unsigned int length)
1934 struct sk_buff *skb, *nskb;
1935 unsigned hdr_space = sky2->rx_data_size;
1937 pr_debug(PFX "receive new length=%d\n", length);
1939 /* Don't be tricky about reusing pages (yet) */
1940 nskb = sky2_rx_alloc(sky2);
1941 if (unlikely(!nskb))
1945 sky2_rx_unmap_skb(sky2->hw->pdev, re);
1947 prefetch(skb->data);
1949 sky2_rx_map_skb(sky2->hw->pdev, re, hdr_space);
1951 if (skb_shinfo(skb)->nr_frags)
1952 skb_put_frags(skb, hdr_space, length);
1954 skb_put(skb, length);
1959 * Receive one packet.
1960 * For larger packets, get new buffer.
1962 static struct sk_buff *sky2_receive(struct net_device *dev,
1963 u16 length, u32 status)
1965 struct sky2_port *sky2 = netdev_priv(dev);
1966 struct rx_ring_info *re = sky2->rx_ring + sky2->rx_next;
1967 struct sk_buff *skb = NULL;
1969 if (unlikely(netif_msg_rx_status(sky2)))
1970 printk(KERN_DEBUG PFX "%s: rx slot %u status 0x%x len %d\n",
1971 dev->name, sky2->rx_next, status, length);
1973 sky2->rx_next = (sky2->rx_next + 1) % sky2->rx_pending;
1974 prefetch(sky2->rx_ring + sky2->rx_next);
1976 if (status & GMR_FS_ANY_ERR)
1979 if (!(status & GMR_FS_RX_OK))
1982 if (length > dev->mtu + ETH_HLEN)
1985 if (length < copybreak)
1986 skb = receive_copy(sky2, re, length);
1988 skb = receive_new(sky2, re, length);
1990 sky2_rx_submit(sky2, re);
1995 ++sky2->net_stats.rx_over_errors;
1999 ++sky2->net_stats.rx_errors;
2001 if (netif_msg_rx_err(sky2) && net_ratelimit())
2002 printk(KERN_INFO PFX "%s: rx error, status 0x%x length %d\n",
2003 dev->name, status, length);
2005 if (status & (GMR_FS_LONG_ERR | GMR_FS_UN_SIZE))
2006 sky2->net_stats.rx_length_errors++;
2007 if (status & GMR_FS_FRAGMENT)
2008 sky2->net_stats.rx_frame_errors++;
2009 if (status & GMR_FS_CRC_ERR)
2010 sky2->net_stats.rx_crc_errors++;
2011 if (status & GMR_FS_RX_FF_OV)
2012 sky2->net_stats.rx_fifo_errors++;
2017 /* Transmit complete */
2018 static inline void sky2_tx_done(struct net_device *dev, u16 last)
2020 struct sky2_port *sky2 = netdev_priv(dev);
2022 if (netif_running(dev)) {
2024 sky2_tx_complete(sky2, last);
2025 netif_tx_unlock(dev);
2029 /* Process status response ring */
2030 static int sky2_status_intr(struct sky2_hw *hw, int to_do)
2032 struct sky2_port *sky2;
2034 unsigned buf_write[2] = { 0, 0 };
2035 u16 hwidx = sky2_read16(hw, STAT_PUT_IDX);
2039 while (hw->st_idx != hwidx) {
2040 struct sky2_status_le *le = hw->st_le + hw->st_idx;
2041 struct net_device *dev;
2042 struct sk_buff *skb;
2046 hw->st_idx = RING_NEXT(hw->st_idx, STATUS_RING_SIZE);
2048 BUG_ON(le->link >= 2);
2049 dev = hw->dev[le->link];
2051 sky2 = netdev_priv(dev);
2052 length = le16_to_cpu(le->length);
2053 status = le32_to_cpu(le->status);
2055 switch (le->opcode & ~HW_OWNER) {
2057 skb = sky2_receive(dev, length, status);
2061 skb->protocol = eth_type_trans(skb, dev);
2062 dev->last_rx = jiffies;
2064 #ifdef SKY2_VLAN_TAG_USED
2065 if (sky2->vlgrp && (status & GMR_FS_VLAN)) {
2066 vlan_hwaccel_receive_skb(skb,
2068 be16_to_cpu(sky2->rx_tag));
2071 netif_receive_skb(skb);
2073 /* Update receiver after 16 frames */
2074 if (++buf_write[le->link] == RX_BUF_WRITE) {
2075 sky2_put_idx(hw, rxqaddr[le->link],
2077 buf_write[le->link] = 0;
2080 /* Stop after net poll weight */
2081 if (++work_done >= to_do)
2085 #ifdef SKY2_VLAN_TAG_USED
2087 sky2->rx_tag = length;
2091 sky2->rx_tag = length;
2095 skb = sky2->rx_ring[sky2->rx_next].skb;
2096 skb->ip_summed = CHECKSUM_COMPLETE;
2097 skb->csum = status & 0xffff;
2101 /* TX index reports status for both ports */
2102 BUILD_BUG_ON(TX_RING_SIZE > 0x1000);
2103 sky2_tx_done(hw->dev[0], status & 0xfff);
2105 sky2_tx_done(hw->dev[1],
2106 ((status >> 24) & 0xff)
2107 | (u16)(length & 0xf) << 8);
2111 if (net_ratelimit())
2112 printk(KERN_WARNING PFX
2113 "unknown status opcode 0x%x\n", le->opcode);
2118 /* Fully processed status ring so clear irq */
2119 sky2_write32(hw, STAT_CTRL, SC_STAT_CLR_IRQ);
2123 sky2 = netdev_priv(hw->dev[0]);
2124 sky2_put_idx(hw, Q_R1, sky2->rx_put);
2128 sky2 = netdev_priv(hw->dev[1]);
2129 sky2_put_idx(hw, Q_R2, sky2->rx_put);
2135 static void sky2_hw_error(struct sky2_hw *hw, unsigned port, u32 status)
2137 struct net_device *dev = hw->dev[port];
2139 if (net_ratelimit())
2140 printk(KERN_INFO PFX "%s: hw error interrupt status 0x%x\n",
2143 if (status & Y2_IS_PAR_RD1) {
2144 if (net_ratelimit())
2145 printk(KERN_ERR PFX "%s: ram data read parity error\n",
2148 sky2_write16(hw, RAM_BUFFER(port, B3_RI_CTRL), RI_CLR_RD_PERR);
2151 if (status & Y2_IS_PAR_WR1) {
2152 if (net_ratelimit())
2153 printk(KERN_ERR PFX "%s: ram data write parity error\n",
2156 sky2_write16(hw, RAM_BUFFER(port, B3_RI_CTRL), RI_CLR_WR_PERR);
2159 if (status & Y2_IS_PAR_MAC1) {
2160 if (net_ratelimit())
2161 printk(KERN_ERR PFX "%s: MAC parity error\n", dev->name);
2162 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_CLI_TX_PE);
2165 if (status & Y2_IS_PAR_RX1) {
2166 if (net_ratelimit())
2167 printk(KERN_ERR PFX "%s: RX parity error\n", dev->name);
2168 sky2_write32(hw, Q_ADDR(rxqaddr[port], Q_CSR), BMU_CLR_IRQ_PAR);
2171 if (status & Y2_IS_TCP_TXA1) {
2172 if (net_ratelimit())
2173 printk(KERN_ERR PFX "%s: TCP segmentation error\n",
2175 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), BMU_CLR_IRQ_TCP);
2179 static void sky2_hw_intr(struct sky2_hw *hw)
2181 u32 status = sky2_read32(hw, B0_HWE_ISRC);
2183 if (status & Y2_IS_TIST_OV)
2184 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ);
2186 if (status & (Y2_IS_MST_ERR | Y2_IS_IRQ_STAT)) {
2189 pci_err = sky2_pci_read16(hw, PCI_STATUS);
2190 if (net_ratelimit())
2191 printk(KERN_ERR PFX "%s: pci hw error (0x%x)\n",
2192 pci_name(hw->pdev), pci_err);
2194 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
2195 sky2_pci_write16(hw, PCI_STATUS,
2196 pci_err | PCI_STATUS_ERROR_BITS);
2197 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
2200 if (status & Y2_IS_PCI_EXP) {
2201 /* PCI-Express uncorrectable Error occurred */
2204 pex_err = sky2_pci_read32(hw, PEX_UNC_ERR_STAT);
2206 if (net_ratelimit())
2207 printk(KERN_ERR PFX "%s: pci express error (0x%x)\n",
2208 pci_name(hw->pdev), pex_err);
2210 /* clear the interrupt */
2211 sky2_write32(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
2212 sky2_pci_write32(hw, PEX_UNC_ERR_STAT,
2214 sky2_write32(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
2216 if (pex_err & PEX_FATAL_ERRORS) {
2217 u32 hwmsk = sky2_read32(hw, B0_HWE_IMSK);
2218 hwmsk &= ~Y2_IS_PCI_EXP;
2219 sky2_write32(hw, B0_HWE_IMSK, hwmsk);
2223 if (status & Y2_HWE_L1_MASK)
2224 sky2_hw_error(hw, 0, status);
2226 if (status & Y2_HWE_L1_MASK)
2227 sky2_hw_error(hw, 1, status);
2230 static void sky2_mac_intr(struct sky2_hw *hw, unsigned port)
2232 struct net_device *dev = hw->dev[port];
2233 struct sky2_port *sky2 = netdev_priv(dev);
2234 u8 status = sky2_read8(hw, SK_REG(port, GMAC_IRQ_SRC));
2236 if (netif_msg_intr(sky2))
2237 printk(KERN_INFO PFX "%s: mac interrupt status 0x%x\n",
2240 if (status & GM_IS_RX_FF_OR) {
2241 ++sky2->net_stats.rx_fifo_errors;
2242 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_CLI_RX_FO);
2245 if (status & GM_IS_TX_FF_UR) {
2246 ++sky2->net_stats.tx_fifo_errors;
2247 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_CLI_TX_FU);
2251 /* This should never happen it is a fatal situation */
2252 static void sky2_descriptor_error(struct sky2_hw *hw, unsigned port,
2253 const char *rxtx, u32 mask)
2255 struct net_device *dev = hw->dev[port];
2256 struct sky2_port *sky2 = netdev_priv(dev);
2259 printk(KERN_ERR PFX "%s: %s descriptor error (hardware problem)\n",
2260 dev ? dev->name : "<not registered>", rxtx);
2262 imask = sky2_read32(hw, B0_IMSK);
2264 sky2_write32(hw, B0_IMSK, imask);
2267 spin_lock(&sky2->phy_lock);
2268 sky2_link_down(sky2);
2269 spin_unlock(&sky2->phy_lock);
2273 /* If idle then force a fake soft NAPI poll once a second
2274 * to work around cases where sharing an edge triggered interrupt.
2276 static inline void sky2_idle_start(struct sky2_hw *hw)
2278 if (idle_timeout > 0)
2279 mod_timer(&hw->idle_timer,
2280 jiffies + msecs_to_jiffies(idle_timeout));
2283 static void sky2_idle(unsigned long arg)
2285 struct sky2_hw *hw = (struct sky2_hw *) arg;
2286 struct net_device *dev = hw->dev[0];
2288 if (__netif_rx_schedule_prep(dev))
2289 __netif_rx_schedule(dev);
2291 mod_timer(&hw->idle_timer, jiffies + msecs_to_jiffies(idle_timeout));
2295 static int sky2_poll(struct net_device *dev0, int *budget)
2297 struct sky2_hw *hw = ((struct sky2_port *) netdev_priv(dev0))->hw;
2298 int work_limit = min(dev0->quota, *budget);
2300 u32 status = sky2_read32(hw, B0_Y2_SP_EISR);
2302 if (status & Y2_IS_HW_ERR)
2305 if (status & Y2_IS_IRQ_PHY1)
2306 sky2_phy_intr(hw, 0);
2308 if (status & Y2_IS_IRQ_PHY2)
2309 sky2_phy_intr(hw, 1);
2311 if (status & Y2_IS_IRQ_MAC1)
2312 sky2_mac_intr(hw, 0);
2314 if (status & Y2_IS_IRQ_MAC2)
2315 sky2_mac_intr(hw, 1);
2317 if (status & Y2_IS_CHK_RX1)
2318 sky2_descriptor_error(hw, 0, "receive", Y2_IS_CHK_RX1);
2320 if (status & Y2_IS_CHK_RX2)
2321 sky2_descriptor_error(hw, 1, "receive", Y2_IS_CHK_RX2);
2323 if (status & Y2_IS_CHK_TXA1)
2324 sky2_descriptor_error(hw, 0, "transmit", Y2_IS_CHK_TXA1);
2326 if (status & Y2_IS_CHK_TXA2)
2327 sky2_descriptor_error(hw, 1, "transmit", Y2_IS_CHK_TXA2);
2329 work_done = sky2_status_intr(hw, work_limit);
2330 if (work_done < work_limit) {
2331 netif_rx_complete(dev0);
2333 sky2_read32(hw, B0_Y2_SP_LISR);
2336 *budget -= work_done;
2337 dev0->quota -= work_done;
2342 static irqreturn_t sky2_intr(int irq, void *dev_id)
2344 struct sky2_hw *hw = dev_id;
2345 struct net_device *dev0 = hw->dev[0];
2348 /* Reading this mask interrupts as side effect */
2349 status = sky2_read32(hw, B0_Y2_SP_ISRC2);
2350 if (status == 0 || status == ~0)
2353 prefetch(&hw->st_le[hw->st_idx]);
2354 if (likely(__netif_rx_schedule_prep(dev0)))
2355 __netif_rx_schedule(dev0);
2360 #ifdef CONFIG_NET_POLL_CONTROLLER
2361 static void sky2_netpoll(struct net_device *dev)
2363 struct sky2_port *sky2 = netdev_priv(dev);
2364 struct net_device *dev0 = sky2->hw->dev[0];
2366 if (netif_running(dev) && __netif_rx_schedule_prep(dev0))
2367 __netif_rx_schedule(dev0);
2371 /* Chip internal frequency for clock calculations */
2372 static inline u32 sky2_mhz(const struct sky2_hw *hw)
2374 switch (hw->chip_id) {
2375 case CHIP_ID_YUKON_EC:
2376 case CHIP_ID_YUKON_EC_U:
2377 return 125; /* 125 Mhz */
2378 case CHIP_ID_YUKON_FE:
2379 return 100; /* 100 Mhz */
2380 default: /* YUKON_XL */
2381 return 156; /* 156 Mhz */
2385 static inline u32 sky2_us2clk(const struct sky2_hw *hw, u32 us)
2387 return sky2_mhz(hw) * us;
2390 static inline u32 sky2_clk2us(const struct sky2_hw *hw, u32 clk)
2392 return clk / sky2_mhz(hw);
2396 static int sky2_reset(struct sky2_hw *hw)
2402 sky2_write8(hw, B0_CTST, CS_RST_CLR);
2404 hw->chip_id = sky2_read8(hw, B2_CHIP_ID);
2405 if (hw->chip_id < CHIP_ID_YUKON_XL || hw->chip_id > CHIP_ID_YUKON_FE) {
2406 printk(KERN_ERR PFX "%s: unsupported chip type 0x%x\n",
2407 pci_name(hw->pdev), hw->chip_id);
2411 hw->chip_rev = (sky2_read8(hw, B2_MAC_CFG) & CFG_CHIP_R_MSK) >> 4;
2413 /* This rev is really old, and requires untested workarounds */
2414 if (hw->chip_id == CHIP_ID_YUKON_EC && hw->chip_rev == CHIP_REV_YU_EC_A1) {
2415 printk(KERN_ERR PFX "%s: unsupported revision Yukon-%s (0x%x) rev %d\n",
2416 pci_name(hw->pdev), yukon2_name[hw->chip_id - CHIP_ID_YUKON_XL],
2417 hw->chip_id, hw->chip_rev);
2422 if (hw->chip_id <= CHIP_ID_YUKON_EC) {
2423 sky2_write8(hw, B28_Y2_ASF_STAT_CMD, Y2_ASF_RESET);
2424 sky2_write16(hw, B0_CTST, Y2_ASF_DISABLE);
2428 sky2_write8(hw, B0_CTST, CS_RST_SET);
2429 sky2_write8(hw, B0_CTST, CS_RST_CLR);
2431 /* clear PCI errors, if any */
2432 status = sky2_pci_read16(hw, PCI_STATUS);
2434 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
2435 sky2_pci_write16(hw, PCI_STATUS, status | PCI_STATUS_ERROR_BITS);
2438 sky2_write8(hw, B0_CTST, CS_MRST_CLR);
2440 /* clear any PEX errors */
2441 if (pci_find_capability(hw->pdev, PCI_CAP_ID_EXP))
2442 sky2_pci_write32(hw, PEX_UNC_ERR_STAT, 0xffffffffUL);
2445 hw->pmd_type = sky2_read8(hw, B2_PMD_TYP);
2447 t8 = sky2_read8(hw, B2_Y2_HW_RES);
2448 if ((t8 & CFG_DUAL_MAC_MSK) == CFG_DUAL_MAC_MSK) {
2449 if (!(sky2_read8(hw, B2_Y2_CLK_GATE) & Y2_STATUS_LNK2_INAC))
2453 sky2_set_power_state(hw, PCI_D0);
2455 for (i = 0; i < hw->ports; i++) {
2456 sky2_write8(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_SET);
2457 sky2_write8(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_CLR);
2460 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
2462 /* Clear I2C IRQ noise */
2463 sky2_write32(hw, B2_I2C_IRQ, 1);
2465 /* turn off hardware timer (unused) */
2466 sky2_write8(hw, B2_TI_CTRL, TIM_STOP);
2467 sky2_write8(hw, B2_TI_CTRL, TIM_CLR_IRQ);
2469 sky2_write8(hw, B0_Y2LED, LED_STAT_ON);
2471 /* Turn off descriptor polling */
2472 sky2_write32(hw, B28_DPT_CTRL, DPT_STOP);
2474 /* Turn off receive timestamp */
2475 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_STOP);
2476 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ);
2478 /* enable the Tx Arbiters */
2479 for (i = 0; i < hw->ports; i++)
2480 sky2_write8(hw, SK_REG(i, TXA_CTRL), TXA_ENA_ARB);
2482 /* Initialize ram interface */
2483 for (i = 0; i < hw->ports; i++) {
2484 sky2_write8(hw, RAM_BUFFER(i, B3_RI_CTRL), RI_RST_CLR);
2486 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_R1), SK_RI_TO_53);
2487 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XA1), SK_RI_TO_53);
2488 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XS1), SK_RI_TO_53);
2489 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_R1), SK_RI_TO_53);
2490 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XA1), SK_RI_TO_53);
2491 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XS1), SK_RI_TO_53);
2492 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_R2), SK_RI_TO_53);
2493 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XA2), SK_RI_TO_53);
2494 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XS2), SK_RI_TO_53);
2495 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_R2), SK_RI_TO_53);
2496 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XA2), SK_RI_TO_53);
2497 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XS2), SK_RI_TO_53);
2500 sky2_write32(hw, B0_HWE_IMSK, Y2_HWE_ALL_MASK);
2502 for (i = 0; i < hw->ports; i++)
2503 sky2_gmac_reset(hw, i);
2505 memset(hw->st_le, 0, STATUS_LE_BYTES);
2508 sky2_write32(hw, STAT_CTRL, SC_STAT_RST_SET);
2509 sky2_write32(hw, STAT_CTRL, SC_STAT_RST_CLR);
2511 sky2_write32(hw, STAT_LIST_ADDR_LO, hw->st_dma);
2512 sky2_write32(hw, STAT_LIST_ADDR_HI, (u64) hw->st_dma >> 32);
2514 /* Set the list last index */
2515 sky2_write16(hw, STAT_LAST_IDX, STATUS_RING_SIZE - 1);
2517 sky2_write16(hw, STAT_TX_IDX_TH, 10);
2518 sky2_write8(hw, STAT_FIFO_WM, 16);
2520 /* set Status-FIFO ISR watermark */
2521 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0)
2522 sky2_write8(hw, STAT_FIFO_ISR_WM, 4);
2524 sky2_write8(hw, STAT_FIFO_ISR_WM, 16);
2526 sky2_write32(hw, STAT_TX_TIMER_INI, sky2_us2clk(hw, 1000));
2527 sky2_write32(hw, STAT_ISR_TIMER_INI, sky2_us2clk(hw, 20));
2528 sky2_write32(hw, STAT_LEV_TIMER_INI, sky2_us2clk(hw, 100));
2530 /* enable status unit */
2531 sky2_write32(hw, STAT_CTRL, SC_STAT_OP_ON);
2533 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_START);
2534 sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_START);
2535 sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_START);
2540 static u32 sky2_supported_modes(const struct sky2_hw *hw)
2542 if (sky2_is_copper(hw)) {
2543 u32 modes = SUPPORTED_10baseT_Half
2544 | SUPPORTED_10baseT_Full
2545 | SUPPORTED_100baseT_Half
2546 | SUPPORTED_100baseT_Full
2547 | SUPPORTED_Autoneg | SUPPORTED_TP;
2549 if (hw->chip_id != CHIP_ID_YUKON_FE)
2550 modes |= SUPPORTED_1000baseT_Half
2551 | SUPPORTED_1000baseT_Full;
2554 return SUPPORTED_1000baseT_Half
2555 | SUPPORTED_1000baseT_Full
2560 static int sky2_get_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
2562 struct sky2_port *sky2 = netdev_priv(dev);
2563 struct sky2_hw *hw = sky2->hw;
2565 ecmd->transceiver = XCVR_INTERNAL;
2566 ecmd->supported = sky2_supported_modes(hw);
2567 ecmd->phy_address = PHY_ADDR_MARV;
2568 if (sky2_is_copper(hw)) {
2569 ecmd->supported = SUPPORTED_10baseT_Half
2570 | SUPPORTED_10baseT_Full
2571 | SUPPORTED_100baseT_Half
2572 | SUPPORTED_100baseT_Full
2573 | SUPPORTED_1000baseT_Half
2574 | SUPPORTED_1000baseT_Full
2575 | SUPPORTED_Autoneg | SUPPORTED_TP;
2576 ecmd->port = PORT_TP;
2577 ecmd->speed = sky2->speed;
2579 ecmd->speed = SPEED_1000;
2580 ecmd->port = PORT_FIBRE;
2583 ecmd->advertising = sky2->advertising;
2584 ecmd->autoneg = sky2->autoneg;
2585 ecmd->duplex = sky2->duplex;
2589 static int sky2_set_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
2591 struct sky2_port *sky2 = netdev_priv(dev);
2592 const struct sky2_hw *hw = sky2->hw;
2593 u32 supported = sky2_supported_modes(hw);
2595 if (ecmd->autoneg == AUTONEG_ENABLE) {
2596 ecmd->advertising = supported;
2602 switch (ecmd->speed) {
2604 if (ecmd->duplex == DUPLEX_FULL)
2605 setting = SUPPORTED_1000baseT_Full;
2606 else if (ecmd->duplex == DUPLEX_HALF)
2607 setting = SUPPORTED_1000baseT_Half;
2612 if (ecmd->duplex == DUPLEX_FULL)
2613 setting = SUPPORTED_100baseT_Full;
2614 else if (ecmd->duplex == DUPLEX_HALF)
2615 setting = SUPPORTED_100baseT_Half;
2621 if (ecmd->duplex == DUPLEX_FULL)
2622 setting = SUPPORTED_10baseT_Full;
2623 else if (ecmd->duplex == DUPLEX_HALF)
2624 setting = SUPPORTED_10baseT_Half;
2632 if ((setting & supported) == 0)
2635 sky2->speed = ecmd->speed;
2636 sky2->duplex = ecmd->duplex;
2639 sky2->autoneg = ecmd->autoneg;
2640 sky2->advertising = ecmd->advertising;
2642 if (netif_running(dev))
2643 sky2_phy_reinit(sky2);
2648 static void sky2_get_drvinfo(struct net_device *dev,
2649 struct ethtool_drvinfo *info)
2651 struct sky2_port *sky2 = netdev_priv(dev);
2653 strcpy(info->driver, DRV_NAME);
2654 strcpy(info->version, DRV_VERSION);
2655 strcpy(info->fw_version, "N/A");
2656 strcpy(info->bus_info, pci_name(sky2->hw->pdev));
2659 static const struct sky2_stat {
2660 char name[ETH_GSTRING_LEN];
2663 { "tx_bytes", GM_TXO_OK_HI },
2664 { "rx_bytes", GM_RXO_OK_HI },
2665 { "tx_broadcast", GM_TXF_BC_OK },
2666 { "rx_broadcast", GM_RXF_BC_OK },
2667 { "tx_multicast", GM_TXF_MC_OK },
2668 { "rx_multicast", GM_RXF_MC_OK },
2669 { "tx_unicast", GM_TXF_UC_OK },
2670 { "rx_unicast", GM_RXF_UC_OK },
2671 { "tx_mac_pause", GM_TXF_MPAUSE },
2672 { "rx_mac_pause", GM_RXF_MPAUSE },
2673 { "collisions", GM_TXF_COL },
2674 { "late_collision",GM_TXF_LAT_COL },
2675 { "aborted", GM_TXF_ABO_COL },
2676 { "single_collisions", GM_TXF_SNG_COL },
2677 { "multi_collisions", GM_TXF_MUL_COL },
2679 { "rx_short", GM_RXF_SHT },
2680 { "rx_runt", GM_RXE_FRAG },
2681 { "rx_64_byte_packets", GM_RXF_64B },
2682 { "rx_65_to_127_byte_packets", GM_RXF_127B },
2683 { "rx_128_to_255_byte_packets", GM_RXF_255B },
2684 { "rx_256_to_511_byte_packets", GM_RXF_511B },
2685 { "rx_512_to_1023_byte_packets", GM_RXF_1023B },
2686 { "rx_1024_to_1518_byte_packets", GM_RXF_1518B },
2687 { "rx_1518_to_max_byte_packets", GM_RXF_MAX_SZ },
2688 { "rx_too_long", GM_RXF_LNG_ERR },
2689 { "rx_fifo_overflow", GM_RXE_FIFO_OV },
2690 { "rx_jabber", GM_RXF_JAB_PKT },
2691 { "rx_fcs_error", GM_RXF_FCS_ERR },
2693 { "tx_64_byte_packets", GM_TXF_64B },
2694 { "tx_65_to_127_byte_packets", GM_TXF_127B },
2695 { "tx_128_to_255_byte_packets", GM_TXF_255B },
2696 { "tx_256_to_511_byte_packets", GM_TXF_511B },
2697 { "tx_512_to_1023_byte_packets", GM_TXF_1023B },
2698 { "tx_1024_to_1518_byte_packets", GM_TXF_1518B },
2699 { "tx_1519_to_max_byte_packets", GM_TXF_MAX_SZ },
2700 { "tx_fifo_underrun", GM_TXE_FIFO_UR },
2703 static u32 sky2_get_rx_csum(struct net_device *dev)
2705 struct sky2_port *sky2 = netdev_priv(dev);
2707 return sky2->rx_csum;
2710 static int sky2_set_rx_csum(struct net_device *dev, u32 data)
2712 struct sky2_port *sky2 = netdev_priv(dev);
2714 sky2->rx_csum = data;
2716 sky2_write32(sky2->hw, Q_ADDR(rxqaddr[sky2->port], Q_CSR),
2717 data ? BMU_ENA_RX_CHKSUM : BMU_DIS_RX_CHKSUM);
2722 static u32 sky2_get_msglevel(struct net_device *netdev)
2724 struct sky2_port *sky2 = netdev_priv(netdev);
2725 return sky2->msg_enable;
2728 static int sky2_nway_reset(struct net_device *dev)
2730 struct sky2_port *sky2 = netdev_priv(dev);
2732 if (sky2->autoneg != AUTONEG_ENABLE)
2735 sky2_phy_reinit(sky2);
2740 static void sky2_phy_stats(struct sky2_port *sky2, u64 * data, unsigned count)
2742 struct sky2_hw *hw = sky2->hw;
2743 unsigned port = sky2->port;
2746 data[0] = (u64) gma_read32(hw, port, GM_TXO_OK_HI) << 32
2747 | (u64) gma_read32(hw, port, GM_TXO_OK_LO);
2748 data[1] = (u64) gma_read32(hw, port, GM_RXO_OK_HI) << 32
2749 | (u64) gma_read32(hw, port, GM_RXO_OK_LO);
2751 for (i = 2; i < count; i++)
2752 data[i] = (u64) gma_read32(hw, port, sky2_stats[i].offset);
2755 static void sky2_set_msglevel(struct net_device *netdev, u32 value)
2757 struct sky2_port *sky2 = netdev_priv(netdev);
2758 sky2->msg_enable = value;
2761 static int sky2_get_stats_count(struct net_device *dev)
2763 return ARRAY_SIZE(sky2_stats);
2766 static void sky2_get_ethtool_stats(struct net_device *dev,
2767 struct ethtool_stats *stats, u64 * data)
2769 struct sky2_port *sky2 = netdev_priv(dev);
2771 sky2_phy_stats(sky2, data, ARRAY_SIZE(sky2_stats));
2774 static void sky2_get_strings(struct net_device *dev, u32 stringset, u8 * data)
2778 switch (stringset) {
2780 for (i = 0; i < ARRAY_SIZE(sky2_stats); i++)
2781 memcpy(data + i * ETH_GSTRING_LEN,
2782 sky2_stats[i].name, ETH_GSTRING_LEN);
2787 /* Use hardware MIB variables for critical path statistics and
2788 * transmit feedback not reported at interrupt.
2789 * Other errors are accounted for in interrupt handler.
2791 static struct net_device_stats *sky2_get_stats(struct net_device *dev)
2793 struct sky2_port *sky2 = netdev_priv(dev);
2796 sky2_phy_stats(sky2, data, ARRAY_SIZE(data));
2798 sky2->net_stats.tx_bytes = data[0];
2799 sky2->net_stats.rx_bytes = data[1];
2800 sky2->net_stats.tx_packets = data[2] + data[4] + data[6];
2801 sky2->net_stats.rx_packets = data[3] + data[5] + data[7];
2802 sky2->net_stats.multicast = data[3] + data[5];
2803 sky2->net_stats.collisions = data[10];
2804 sky2->net_stats.tx_aborted_errors = data[12];
2806 return &sky2->net_stats;
2809 static int sky2_set_mac_address(struct net_device *dev, void *p)
2811 struct sky2_port *sky2 = netdev_priv(dev);
2812 struct sky2_hw *hw = sky2->hw;
2813 unsigned port = sky2->port;
2814 const struct sockaddr *addr = p;
2816 if (!is_valid_ether_addr(addr->sa_data))
2817 return -EADDRNOTAVAIL;
2819 memcpy(dev->dev_addr, addr->sa_data, ETH_ALEN);
2820 memcpy_toio(hw->regs + B2_MAC_1 + port * 8,
2821 dev->dev_addr, ETH_ALEN);
2822 memcpy_toio(hw->regs + B2_MAC_2 + port * 8,
2823 dev->dev_addr, ETH_ALEN);
2825 /* virtual address for data */
2826 gma_set_addr(hw, port, GM_SRC_ADDR_2L, dev->dev_addr);
2828 /* physical address: used for pause frames */
2829 gma_set_addr(hw, port, GM_SRC_ADDR_1L, dev->dev_addr);
2834 static void sky2_set_multicast(struct net_device *dev)
2836 struct sky2_port *sky2 = netdev_priv(dev);
2837 struct sky2_hw *hw = sky2->hw;
2838 unsigned port = sky2->port;
2839 struct dev_mc_list *list = dev->mc_list;
2843 memset(filter, 0, sizeof(filter));
2845 reg = gma_read16(hw, port, GM_RX_CTRL);
2846 reg |= GM_RXCR_UCF_ENA;
2848 if (dev->flags & IFF_PROMISC) /* promiscuous */
2849 reg &= ~(GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA);
2850 else if ((dev->flags & IFF_ALLMULTI) || dev->mc_count > 16) /* all multicast */
2851 memset(filter, 0xff, sizeof(filter));
2852 else if (dev->mc_count == 0) /* no multicast */
2853 reg &= ~GM_RXCR_MCF_ENA;
2856 reg |= GM_RXCR_MCF_ENA;
2858 for (i = 0; list && i < dev->mc_count; i++, list = list->next) {
2859 u32 bit = ether_crc(ETH_ALEN, list->dmi_addr) & 0x3f;
2860 filter[bit / 8] |= 1 << (bit % 8);
2864 gma_write16(hw, port, GM_MC_ADDR_H1,
2865 (u16) filter[0] | ((u16) filter[1] << 8));
2866 gma_write16(hw, port, GM_MC_ADDR_H2,
2867 (u16) filter[2] | ((u16) filter[3] << 8));
2868 gma_write16(hw, port, GM_MC_ADDR_H3,
2869 (u16) filter[4] | ((u16) filter[5] << 8));
2870 gma_write16(hw, port, GM_MC_ADDR_H4,
2871 (u16) filter[6] | ((u16) filter[7] << 8));
2873 gma_write16(hw, port, GM_RX_CTRL, reg);
2876 /* Can have one global because blinking is controlled by
2877 * ethtool and that is always under RTNL mutex
2879 static void sky2_led(struct sky2_hw *hw, unsigned port, int on)
2883 switch (hw->chip_id) {
2884 case CHIP_ID_YUKON_XL:
2885 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
2886 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
2887 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
2888 on ? (PHY_M_LEDC_LOS_CTRL(1) |
2889 PHY_M_LEDC_INIT_CTRL(7) |
2890 PHY_M_LEDC_STA1_CTRL(7) |
2891 PHY_M_LEDC_STA0_CTRL(7))
2894 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
2898 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, 0);
2899 gm_phy_write(hw, port, PHY_MARV_LED_OVER,
2900 on ? PHY_M_LED_MO_DUP(MO_LED_ON) |
2901 PHY_M_LED_MO_10(MO_LED_ON) |
2902 PHY_M_LED_MO_100(MO_LED_ON) |
2903 PHY_M_LED_MO_1000(MO_LED_ON) |
2904 PHY_M_LED_MO_RX(MO_LED_ON)
2905 : PHY_M_LED_MO_DUP(MO_LED_OFF) |
2906 PHY_M_LED_MO_10(MO_LED_OFF) |
2907 PHY_M_LED_MO_100(MO_LED_OFF) |
2908 PHY_M_LED_MO_1000(MO_LED_OFF) |
2909 PHY_M_LED_MO_RX(MO_LED_OFF));
2914 /* blink LED's for finding board */
2915 static int sky2_phys_id(struct net_device *dev, u32 data)
2917 struct sky2_port *sky2 = netdev_priv(dev);
2918 struct sky2_hw *hw = sky2->hw;
2919 unsigned port = sky2->port;
2920 u16 ledctrl, ledover = 0;
2925 if (!data || data > (u32) (MAX_SCHEDULE_TIMEOUT / HZ))
2926 ms = jiffies_to_msecs(MAX_SCHEDULE_TIMEOUT);
2930 /* save initial values */
2931 spin_lock_bh(&sky2->phy_lock);
2932 if (hw->chip_id == CHIP_ID_YUKON_XL) {
2933 u16 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
2934 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
2935 ledctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
2936 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
2938 ledctrl = gm_phy_read(hw, port, PHY_MARV_LED_CTRL);
2939 ledover = gm_phy_read(hw, port, PHY_MARV_LED_OVER);
2943 while (!interrupted && ms > 0) {
2944 sky2_led(hw, port, onoff);
2947 spin_unlock_bh(&sky2->phy_lock);
2948 interrupted = msleep_interruptible(250);
2949 spin_lock_bh(&sky2->phy_lock);
2954 /* resume regularly scheduled programming */
2955 if (hw->chip_id == CHIP_ID_YUKON_XL) {
2956 u16 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
2957 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
2958 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ledctrl);
2959 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
2961 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, ledctrl);
2962 gm_phy_write(hw, port, PHY_MARV_LED_OVER, ledover);
2964 spin_unlock_bh(&sky2->phy_lock);
2969 static void sky2_get_pauseparam(struct net_device *dev,
2970 struct ethtool_pauseparam *ecmd)
2972 struct sky2_port *sky2 = netdev_priv(dev);
2974 ecmd->tx_pause = sky2->tx_pause;
2975 ecmd->rx_pause = sky2->rx_pause;
2976 ecmd->autoneg = sky2->autoneg;
2979 static int sky2_set_pauseparam(struct net_device *dev,
2980 struct ethtool_pauseparam *ecmd)
2982 struct sky2_port *sky2 = netdev_priv(dev);
2984 sky2->autoneg = ecmd->autoneg;
2985 sky2->tx_pause = ecmd->tx_pause != 0;
2986 sky2->rx_pause = ecmd->rx_pause != 0;
2988 sky2_phy_reinit(sky2);
2993 static int sky2_get_coalesce(struct net_device *dev,
2994 struct ethtool_coalesce *ecmd)
2996 struct sky2_port *sky2 = netdev_priv(dev);
2997 struct sky2_hw *hw = sky2->hw;
2999 if (sky2_read8(hw, STAT_TX_TIMER_CTRL) == TIM_STOP)
3000 ecmd->tx_coalesce_usecs = 0;
3002 u32 clks = sky2_read32(hw, STAT_TX_TIMER_INI);
3003 ecmd->tx_coalesce_usecs = sky2_clk2us(hw, clks);
3005 ecmd->tx_max_coalesced_frames = sky2_read16(hw, STAT_TX_IDX_TH);
3007 if (sky2_read8(hw, STAT_LEV_TIMER_CTRL) == TIM_STOP)
3008 ecmd->rx_coalesce_usecs = 0;
3010 u32 clks = sky2_read32(hw, STAT_LEV_TIMER_INI);
3011 ecmd->rx_coalesce_usecs = sky2_clk2us(hw, clks);
3013 ecmd->rx_max_coalesced_frames = sky2_read8(hw, STAT_FIFO_WM);
3015 if (sky2_read8(hw, STAT_ISR_TIMER_CTRL) == TIM_STOP)
3016 ecmd->rx_coalesce_usecs_irq = 0;
3018 u32 clks = sky2_read32(hw, STAT_ISR_TIMER_INI);
3019 ecmd->rx_coalesce_usecs_irq = sky2_clk2us(hw, clks);
3022 ecmd->rx_max_coalesced_frames_irq = sky2_read8(hw, STAT_FIFO_ISR_WM);
3027 /* Note: this affect both ports */
3028 static int sky2_set_coalesce(struct net_device *dev,
3029 struct ethtool_coalesce *ecmd)
3031 struct sky2_port *sky2 = netdev_priv(dev);
3032 struct sky2_hw *hw = sky2->hw;
3033 const u32 tmax = sky2_clk2us(hw, 0x0ffffff);
3035 if (ecmd->tx_coalesce_usecs > tmax ||
3036 ecmd->rx_coalesce_usecs > tmax ||
3037 ecmd->rx_coalesce_usecs_irq > tmax)
3040 if (ecmd->tx_max_coalesced_frames >= TX_RING_SIZE-1)
3042 if (ecmd->rx_max_coalesced_frames > RX_MAX_PENDING)
3044 if (ecmd->rx_max_coalesced_frames_irq >RX_MAX_PENDING)
3047 if (ecmd->tx_coalesce_usecs == 0)
3048 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_STOP);
3050 sky2_write32(hw, STAT_TX_TIMER_INI,
3051 sky2_us2clk(hw, ecmd->tx_coalesce_usecs));
3052 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_START);
3054 sky2_write16(hw, STAT_TX_IDX_TH, ecmd->tx_max_coalesced_frames);
3056 if (ecmd->rx_coalesce_usecs == 0)
3057 sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_STOP);
3059 sky2_write32(hw, STAT_LEV_TIMER_INI,
3060 sky2_us2clk(hw, ecmd->rx_coalesce_usecs));
3061 sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_START);
3063 sky2_write8(hw, STAT_FIFO_WM, ecmd->rx_max_coalesced_frames);
3065 if (ecmd->rx_coalesce_usecs_irq == 0)
3066 sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_STOP);
3068 sky2_write32(hw, STAT_ISR_TIMER_INI,
3069 sky2_us2clk(hw, ecmd->rx_coalesce_usecs_irq));
3070 sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_START);
3072 sky2_write8(hw, STAT_FIFO_ISR_WM, ecmd->rx_max_coalesced_frames_irq);
3076 static void sky2_get_ringparam(struct net_device *dev,
3077 struct ethtool_ringparam *ering)
3079 struct sky2_port *sky2 = netdev_priv(dev);
3081 ering->rx_max_pending = RX_MAX_PENDING;
3082 ering->rx_mini_max_pending = 0;
3083 ering->rx_jumbo_max_pending = 0;
3084 ering->tx_max_pending = TX_RING_SIZE - 1;
3086 ering->rx_pending = sky2->rx_pending;
3087 ering->rx_mini_pending = 0;
3088 ering->rx_jumbo_pending = 0;
3089 ering->tx_pending = sky2->tx_pending;
3092 static int sky2_set_ringparam(struct net_device *dev,
3093 struct ethtool_ringparam *ering)
3095 struct sky2_port *sky2 = netdev_priv(dev);
3098 if (ering->rx_pending > RX_MAX_PENDING ||
3099 ering->rx_pending < 8 ||
3100 ering->tx_pending < MAX_SKB_TX_LE ||
3101 ering->tx_pending > TX_RING_SIZE - 1)
3104 if (netif_running(dev))
3107 sky2->rx_pending = ering->rx_pending;
3108 sky2->tx_pending = ering->tx_pending;
3110 if (netif_running(dev)) {
3115 sky2_set_multicast(dev);
3121 static int sky2_get_regs_len(struct net_device *dev)
3127 * Returns copy of control register region
3128 * Note: access to the RAM address register set will cause timeouts.
3130 static void sky2_get_regs(struct net_device *dev, struct ethtool_regs *regs,
3133 const struct sky2_port *sky2 = netdev_priv(dev);
3134 const void __iomem *io = sky2->hw->regs;
3136 BUG_ON(regs->len < B3_RI_WTO_R1);
3138 memset(p, 0, regs->len);
3140 memcpy_fromio(p, io, B3_RAM_ADDR);
3142 memcpy_fromio(p + B3_RI_WTO_R1,
3144 regs->len - B3_RI_WTO_R1);
3147 static const struct ethtool_ops sky2_ethtool_ops = {
3148 .get_settings = sky2_get_settings,
3149 .set_settings = sky2_set_settings,
3150 .get_drvinfo = sky2_get_drvinfo,
3151 .get_msglevel = sky2_get_msglevel,
3152 .set_msglevel = sky2_set_msglevel,
3153 .nway_reset = sky2_nway_reset,
3154 .get_regs_len = sky2_get_regs_len,
3155 .get_regs = sky2_get_regs,
3156 .get_link = ethtool_op_get_link,
3157 .get_sg = ethtool_op_get_sg,
3158 .set_sg = ethtool_op_set_sg,
3159 .get_tx_csum = ethtool_op_get_tx_csum,
3160 .set_tx_csum = ethtool_op_set_tx_csum,
3161 .get_tso = ethtool_op_get_tso,
3162 .set_tso = ethtool_op_set_tso,
3163 .get_rx_csum = sky2_get_rx_csum,
3164 .set_rx_csum = sky2_set_rx_csum,
3165 .get_strings = sky2_get_strings,
3166 .get_coalesce = sky2_get_coalesce,
3167 .set_coalesce = sky2_set_coalesce,
3168 .get_ringparam = sky2_get_ringparam,
3169 .set_ringparam = sky2_set_ringparam,
3170 .get_pauseparam = sky2_get_pauseparam,
3171 .set_pauseparam = sky2_set_pauseparam,
3172 .phys_id = sky2_phys_id,
3173 .get_stats_count = sky2_get_stats_count,
3174 .get_ethtool_stats = sky2_get_ethtool_stats,
3175 .get_perm_addr = ethtool_op_get_perm_addr,
3178 /* Initialize network device */
3179 static __devinit struct net_device *sky2_init_netdev(struct sky2_hw *hw,
3180 unsigned port, int highmem)
3182 struct sky2_port *sky2;
3183 struct net_device *dev = alloc_etherdev(sizeof(*sky2));
3186 printk(KERN_ERR "sky2 etherdev alloc failed");
3190 SET_MODULE_OWNER(dev);
3191 SET_NETDEV_DEV(dev, &hw->pdev->dev);
3192 dev->irq = hw->pdev->irq;
3193 dev->open = sky2_up;
3194 dev->stop = sky2_down;
3195 dev->do_ioctl = sky2_ioctl;
3196 dev->hard_start_xmit = sky2_xmit_frame;
3197 dev->get_stats = sky2_get_stats;
3198 dev->set_multicast_list = sky2_set_multicast;
3199 dev->set_mac_address = sky2_set_mac_address;
3200 dev->change_mtu = sky2_change_mtu;
3201 SET_ETHTOOL_OPS(dev, &sky2_ethtool_ops);
3202 dev->tx_timeout = sky2_tx_timeout;
3203 dev->watchdog_timeo = TX_WATCHDOG;
3205 dev->poll = sky2_poll;
3206 dev->weight = NAPI_WEIGHT;
3207 #ifdef CONFIG_NET_POLL_CONTROLLER
3208 dev->poll_controller = sky2_netpoll;
3211 sky2 = netdev_priv(dev);
3214 sky2->msg_enable = netif_msg_init(debug, default_msg);
3216 /* Auto speed and flow control */
3217 sky2->autoneg = AUTONEG_ENABLE;
3222 sky2->advertising = sky2_supported_modes(hw);
3225 spin_lock_init(&sky2->phy_lock);
3226 sky2->tx_pending = TX_DEF_PENDING;
3227 sky2->rx_pending = RX_DEF_PENDING;
3229 hw->dev[port] = dev;
3233 if (hw->chip_id != CHIP_ID_YUKON_EC_U)
3234 dev->features |= NETIF_F_TSO;
3236 dev->features |= NETIF_F_HIGHDMA;
3237 dev->features |= NETIF_F_IP_CSUM | NETIF_F_SG;
3239 #ifdef SKY2_VLAN_TAG_USED
3240 dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
3241 dev->vlan_rx_register = sky2_vlan_rx_register;
3242 dev->vlan_rx_kill_vid = sky2_vlan_rx_kill_vid;
3245 /* read the mac address */
3246 memcpy_fromio(dev->dev_addr, hw->regs + B2_MAC_1 + port * 8, ETH_ALEN);
3247 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
3249 /* device is off until link detection */
3250 netif_carrier_off(dev);
3251 netif_stop_queue(dev);
3256 static void __devinit sky2_show_addr(struct net_device *dev)
3258 const struct sky2_port *sky2 = netdev_priv(dev);
3260 if (netif_msg_probe(sky2))
3261 printk(KERN_INFO PFX "%s: addr %02x:%02x:%02x:%02x:%02x:%02x\n",
3263 dev->dev_addr[0], dev->dev_addr[1], dev->dev_addr[2],
3264 dev->dev_addr[3], dev->dev_addr[4], dev->dev_addr[5]);
3267 /* Handle software interrupt used during MSI test */
3268 static irqreturn_t __devinit sky2_test_intr(int irq, void *dev_id)
3270 struct sky2_hw *hw = dev_id;
3271 u32 status = sky2_read32(hw, B0_Y2_SP_ISRC2);
3276 if (status & Y2_IS_IRQ_SW) {
3277 hw->msi_detected = 1;
3278 wake_up(&hw->msi_wait);
3279 sky2_write8(hw, B0_CTST, CS_CL_SW_IRQ);
3281 sky2_write32(hw, B0_Y2_SP_ICR, 2);
3286 /* Test interrupt path by forcing a a software IRQ */
3287 static int __devinit sky2_test_msi(struct sky2_hw *hw)
3289 struct pci_dev *pdev = hw->pdev;
3292 init_waitqueue_head (&hw->msi_wait);
3294 sky2_write32(hw, B0_IMSK, Y2_IS_IRQ_SW);
3296 err = request_irq(pdev->irq, sky2_test_intr, IRQF_SHARED, DRV_NAME, hw);
3298 printk(KERN_ERR PFX "%s: cannot assign irq %d\n",
3299 pci_name(pdev), pdev->irq);
3303 sky2_write8(hw, B0_CTST, CS_ST_SW_IRQ);
3304 sky2_read8(hw, B0_CTST);
3306 wait_event_timeout(hw->msi_wait, hw->msi_detected, HZ/10);
3308 if (!hw->msi_detected) {
3309 /* MSI test failed, go back to INTx mode */
3310 printk(KERN_INFO PFX "%s: No interrupt generated using MSI, "
3311 "switching to INTx mode.\n",
3315 sky2_write8(hw, B0_CTST, CS_CL_SW_IRQ);
3318 sky2_write32(hw, B0_IMSK, 0);
3319 sky2_read32(hw, B0_IMSK);
3321 free_irq(pdev->irq, hw);
3326 static int __devinit sky2_probe(struct pci_dev *pdev,
3327 const struct pci_device_id *ent)
3329 struct net_device *dev, *dev1 = NULL;
3331 int err, pm_cap, using_dac = 0;
3333 err = pci_enable_device(pdev);
3335 printk(KERN_ERR PFX "%s cannot enable PCI device\n",
3340 err = pci_request_regions(pdev, DRV_NAME);
3342 printk(KERN_ERR PFX "%s cannot obtain PCI resources\n",
3347 pci_set_master(pdev);
3349 /* Find power-management capability. */
3350 pm_cap = pci_find_capability(pdev, PCI_CAP_ID_PM);
3352 printk(KERN_ERR PFX "Cannot find PowerManagement capability, "
3355 goto err_out_free_regions;
3358 if (sizeof(dma_addr_t) > sizeof(u32) &&
3359 !(err = pci_set_dma_mask(pdev, DMA_64BIT_MASK))) {
3361 err = pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK);
3363 printk(KERN_ERR PFX "%s unable to obtain 64 bit DMA "
3364 "for consistent allocations\n", pci_name(pdev));
3365 goto err_out_free_regions;
3369 err = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
3371 printk(KERN_ERR PFX "%s no usable DMA configuration\n",
3373 goto err_out_free_regions;
3378 hw = kzalloc(sizeof(*hw), GFP_KERNEL);
3380 printk(KERN_ERR PFX "%s: cannot allocate hardware struct\n",
3382 goto err_out_free_regions;
3387 hw->regs = ioremap_nocache(pci_resource_start(pdev, 0), 0x4000);
3389 printk(KERN_ERR PFX "%s: cannot map device registers\n",
3391 goto err_out_free_hw;
3393 hw->pm_cap = pm_cap;
3396 /* The sk98lin vendor driver uses hardware byte swapping but
3397 * this driver uses software swapping.
3401 reg = sky2_pci_read32(hw, PCI_DEV_REG2);
3402 reg &= ~PCI_REV_DESC;
3403 sky2_pci_write32(hw, PCI_DEV_REG2, reg);
3407 /* ring for status responses */
3408 hw->st_le = pci_alloc_consistent(hw->pdev, STATUS_LE_BYTES,
3411 goto err_out_iounmap;
3413 err = sky2_reset(hw);
3415 goto err_out_iounmap;
3417 printk(KERN_INFO PFX "v%s addr 0x%llx irq %d Yukon-%s (0x%x) rev %d\n",
3418 DRV_VERSION, (unsigned long long)pci_resource_start(pdev, 0),
3419 pdev->irq, yukon2_name[hw->chip_id - CHIP_ID_YUKON_XL],
3420 hw->chip_id, hw->chip_rev);
3422 dev = sky2_init_netdev(hw, 0, using_dac);
3424 goto err_out_free_pci;
3426 if (!disable_msi && pci_enable_msi(pdev) == 0) {
3427 err = sky2_test_msi(hw);
3428 if (err == -EOPNOTSUPP)
3429 pci_disable_msi(pdev);
3431 goto err_out_free_netdev;
3434 err = register_netdev(dev);
3436 printk(KERN_ERR PFX "%s: cannot register net device\n",
3438 goto err_out_free_netdev;
3441 err = request_irq(pdev->irq, sky2_intr, IRQF_SHARED, dev->name, hw);
3443 printk(KERN_ERR PFX "%s: cannot assign irq %d\n",
3444 pci_name(pdev), pdev->irq);
3445 goto err_out_unregister;
3447 sky2_write32(hw, B0_IMSK, Y2_IS_BASE);
3449 sky2_show_addr(dev);
3451 if (hw->ports > 1 && (dev1 = sky2_init_netdev(hw, 1, using_dac))) {
3452 if (register_netdev(dev1) == 0)
3453 sky2_show_addr(dev1);
3455 /* Failure to register second port need not be fatal */
3456 printk(KERN_WARNING PFX
3457 "register of second port failed\n");
3463 setup_timer(&hw->idle_timer, sky2_idle, (unsigned long) hw);
3464 sky2_idle_start(hw);
3466 pci_set_drvdata(pdev, hw);
3471 pci_disable_msi(pdev);
3472 unregister_netdev(dev);
3473 err_out_free_netdev:
3476 sky2_write8(hw, B0_CTST, CS_RST_SET);
3477 pci_free_consistent(hw->pdev, STATUS_LE_BYTES, hw->st_le, hw->st_dma);
3482 err_out_free_regions:
3483 pci_release_regions(pdev);
3484 pci_disable_device(pdev);
3489 static void __devexit sky2_remove(struct pci_dev *pdev)
3491 struct sky2_hw *hw = pci_get_drvdata(pdev);
3492 struct net_device *dev0, *dev1;
3497 del_timer_sync(&hw->idle_timer);
3499 sky2_write32(hw, B0_IMSK, 0);
3500 synchronize_irq(hw->pdev->irq);
3505 unregister_netdev(dev1);
3506 unregister_netdev(dev0);
3508 sky2_set_power_state(hw, PCI_D3hot);
3509 sky2_write16(hw, B0_Y2LED, LED_STAT_OFF);
3510 sky2_write8(hw, B0_CTST, CS_RST_SET);
3511 sky2_read8(hw, B0_CTST);
3513 free_irq(pdev->irq, hw);
3514 pci_disable_msi(pdev);
3515 pci_free_consistent(pdev, STATUS_LE_BYTES, hw->st_le, hw->st_dma);
3516 pci_release_regions(pdev);
3517 pci_disable_device(pdev);
3525 pci_set_drvdata(pdev, NULL);
3529 static int sky2_suspend(struct pci_dev *pdev, pm_message_t state)
3531 struct sky2_hw *hw = pci_get_drvdata(pdev);
3533 pci_power_t pstate = pci_choose_state(pdev, state);
3535 if (!(pstate == PCI_D3hot || pstate == PCI_D3cold))
3538 del_timer_sync(&hw->idle_timer);
3539 netif_poll_disable(hw->dev[0]);
3541 for (i = 0; i < hw->ports; i++) {
3542 struct net_device *dev = hw->dev[i];
3544 if (netif_running(dev)) {
3546 netif_device_detach(dev);
3550 sky2_write32(hw, B0_IMSK, 0);
3551 pci_save_state(pdev);
3552 sky2_set_power_state(hw, pstate);
3556 static int sky2_resume(struct pci_dev *pdev)
3558 struct sky2_hw *hw = pci_get_drvdata(pdev);
3561 pci_restore_state(pdev);
3562 pci_enable_wake(pdev, PCI_D0, 0);
3563 sky2_set_power_state(hw, PCI_D0);
3565 err = sky2_reset(hw);
3569 sky2_write32(hw, B0_IMSK, Y2_IS_BASE);
3571 for (i = 0; i < hw->ports; i++) {
3572 struct net_device *dev = hw->dev[i];
3573 if (netif_running(dev)) {
3574 netif_device_attach(dev);
3578 printk(KERN_ERR PFX "%s: could not up: %d\n",
3586 netif_poll_enable(hw->dev[0]);
3587 sky2_idle_start(hw);
3593 static struct pci_driver sky2_driver = {
3595 .id_table = sky2_id_table,
3596 .probe = sky2_probe,
3597 .remove = __devexit_p(sky2_remove),
3599 .suspend = sky2_suspend,
3600 .resume = sky2_resume,
3604 static int __init sky2_init_module(void)
3606 return pci_register_driver(&sky2_driver);
3609 static void __exit sky2_cleanup_module(void)
3611 pci_unregister_driver(&sky2_driver);
3614 module_init(sky2_init_module);
3615 module_exit(sky2_cleanup_module);
3617 MODULE_DESCRIPTION("Marvell Yukon 2 Gigabit Ethernet driver");
3618 MODULE_AUTHOR("Stephen Hemminger <shemminger@osdl.org>");
3619 MODULE_LICENSE("GPL");
3620 MODULE_VERSION(DRV_VERSION);