2 * New driver for Marvell Yukon chipset and SysKonnect Gigabit
3 * Ethernet adapters. Based on earlier sk98lin, e100 and
4 * FreeBSD if_sk drivers.
6 * This driver intentionally does not support all the features
7 * of the original driver such as link fail-over and link management because
8 * those should be done at higher levels.
10 * Copyright (C) 2004, 2005 Stephen Hemminger <shemminger@osdl.org>
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License as published by
14 * the Free Software Foundation; either version 2 of the License, or
15 * (at your option) any later version.
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
27 #include <linux/config.h>
28 #include <linux/kernel.h>
29 #include <linux/module.h>
30 #include <linux/moduleparam.h>
31 #include <linux/netdevice.h>
32 #include <linux/etherdevice.h>
33 #include <linux/ethtool.h>
34 #include <linux/pci.h>
35 #include <linux/if_vlan.h>
37 #include <linux/delay.h>
38 #include <linux/crc32.h>
39 #include <linux/dma-mapping.h>
44 #define DRV_NAME "skge"
45 #define DRV_VERSION "0.9"
46 #define PFX DRV_NAME " "
48 #define DEFAULT_TX_RING_SIZE 128
49 #define DEFAULT_RX_RING_SIZE 512
50 #define MAX_TX_RING_SIZE 1024
51 #define MAX_RX_RING_SIZE 4096
52 #define RX_COPY_THRESHOLD 128
53 #define RX_BUF_SIZE 1536
54 #define PHY_RETRIES 1000
55 #define ETH_JUMBO_MTU 9000
56 #define TX_WATCHDOG (5 * HZ)
57 #define NAPI_WEIGHT 64
60 MODULE_DESCRIPTION("SysKonnect Gigabit Ethernet driver");
61 MODULE_AUTHOR("Stephen Hemminger <shemminger@osdl.org>");
62 MODULE_LICENSE("GPL");
63 MODULE_VERSION(DRV_VERSION);
65 static const u32 default_msg
66 = NETIF_MSG_DRV| NETIF_MSG_PROBE| NETIF_MSG_LINK
67 | NETIF_MSG_IFUP| NETIF_MSG_IFDOWN;
69 static int debug = -1; /* defaults above */
70 module_param(debug, int, 0);
71 MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
73 static const struct pci_device_id skge_id_table[] = {
74 { PCI_DEVICE(PCI_VENDOR_ID_3COM, PCI_DEVICE_ID_3COM_3C940) },
75 { PCI_DEVICE(PCI_VENDOR_ID_3COM, PCI_DEVICE_ID_3COM_3C940B) },
76 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_GE) },
77 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_YU) },
78 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, PCI_DEVICE_ID_DLINK_DGE510T), },
79 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4320) },
80 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x5005) }, /* Belkin */
81 { PCI_DEVICE(PCI_VENDOR_ID_CNET, PCI_DEVICE_ID_CNET_GIGACARD) },
82 { PCI_DEVICE(PCI_VENDOR_ID_LINKSYS, PCI_DEVICE_ID_LINKSYS_EG1064) },
83 { PCI_VENDOR_ID_LINKSYS, 0x1032, PCI_ANY_ID, 0x0015, },
86 MODULE_DEVICE_TABLE(pci, skge_id_table);
88 static int skge_up(struct net_device *dev);
89 static int skge_down(struct net_device *dev);
90 static void skge_tx_clean(struct skge_port *skge);
91 static void xm_phy_write(struct skge_hw *hw, int port, u16 reg, u16 val);
92 static void gm_phy_write(struct skge_hw *hw, int port, u16 reg, u16 val);
93 static void genesis_get_stats(struct skge_port *skge, u64 *data);
94 static void yukon_get_stats(struct skge_port *skge, u64 *data);
95 static void yukon_init(struct skge_hw *hw, int port);
96 static void yukon_reset(struct skge_hw *hw, int port);
97 static void genesis_mac_init(struct skge_hw *hw, int port);
98 static void genesis_reset(struct skge_hw *hw, int port);
99 static void genesis_link_up(struct skge_port *skge);
101 /* Avoid conditionals by using array */
102 static const int txqaddr[] = { Q_XA1, Q_XA2 };
103 static const int rxqaddr[] = { Q_R1, Q_R2 };
104 static const u32 rxirqmask[] = { IS_R1_F, IS_R2_F };
105 static const u32 txirqmask[] = { IS_XA1_F, IS_XA2_F };
106 static const u32 portirqmask[] = { IS_PORT_1, IS_PORT_2 };
108 /* Don't need to look at whole 16K.
109 * last interesting register is descriptor poll timer.
111 #define SKGE_REGS_LEN (29*128)
113 static int skge_get_regs_len(struct net_device *dev)
115 return SKGE_REGS_LEN;
119 * Returns copy of control register region
120 * I/O region is divided into banks and certain regions are unreadable
122 static void skge_get_regs(struct net_device *dev, struct ethtool_regs *regs,
125 const struct skge_port *skge = netdev_priv(dev);
127 const void __iomem *io = skge->hw->regs;
128 static const unsigned long bankmap
129 = (1<<0) | (1<<2) | (1<<8) | (1<<9)
130 | (1<<12) | (1<<13) | (1<<14) | (1<<15) | (1<<16)
131 | (1<<17) | (1<<20) | (1<<21) | (1<<22) | (1<<23)
132 | (1<<24) | (1<<25) | (1<<26) | (1<<27) | (1<<28);
135 for (offs = 0; offs < regs->len; offs += 128) {
136 u32 len = min_t(u32, 128, regs->len - offs);
138 if (bankmap & (1<<(offs/128)))
139 memcpy_fromio(p + offs, io + offs, len);
141 memset(p + offs, 0, len);
145 /* Wake on Lan only supported on Yukon chps with rev 1 or above */
146 static int wol_supported(const struct skge_hw *hw)
148 return !((hw->chip_id == CHIP_ID_GENESIS ||
149 (hw->chip_id == CHIP_ID_YUKON && hw->chip_rev == 0)));
152 static void skge_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
154 struct skge_port *skge = netdev_priv(dev);
156 wol->supported = wol_supported(skge->hw) ? WAKE_MAGIC : 0;
157 wol->wolopts = skge->wol ? WAKE_MAGIC : 0;
160 static int skge_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
162 struct skge_port *skge = netdev_priv(dev);
163 struct skge_hw *hw = skge->hw;
165 if (wol->wolopts != WAKE_MAGIC && wol->wolopts != 0)
168 if (wol->wolopts == WAKE_MAGIC && !wol_supported(hw))
171 skge->wol = wol->wolopts == WAKE_MAGIC;
174 memcpy_toio(hw->regs + WOL_MAC_ADDR, dev->dev_addr, ETH_ALEN);
176 skge_write16(hw, WOL_CTRL_STAT,
177 WOL_CTL_ENA_PME_ON_MAGIC_PKT |
178 WOL_CTL_ENA_MAGIC_PKT_UNIT);
180 skge_write16(hw, WOL_CTRL_STAT, WOL_CTL_DEFAULT);
185 /* Determine supported/adverised modes based on hardware.
186 * Note: ethtoool ADVERTISED_xxx == SUPPORTED_xxx
188 static u32 skge_supported_modes(const struct skge_hw *hw)
193 supported = SUPPORTED_10baseT_Half
194 | SUPPORTED_10baseT_Full
195 | SUPPORTED_100baseT_Half
196 | SUPPORTED_100baseT_Full
197 | SUPPORTED_1000baseT_Half
198 | SUPPORTED_1000baseT_Full
199 | SUPPORTED_Autoneg| SUPPORTED_TP;
201 if (hw->chip_id == CHIP_ID_GENESIS)
202 supported &= ~(SUPPORTED_10baseT_Half
203 | SUPPORTED_10baseT_Full
204 | SUPPORTED_100baseT_Half
205 | SUPPORTED_100baseT_Full);
207 else if (hw->chip_id == CHIP_ID_YUKON)
208 supported &= ~SUPPORTED_1000baseT_Half;
210 supported = SUPPORTED_1000baseT_Full | SUPPORTED_FIBRE
216 static int skge_get_settings(struct net_device *dev,
217 struct ethtool_cmd *ecmd)
219 struct skge_port *skge = netdev_priv(dev);
220 struct skge_hw *hw = skge->hw;
222 ecmd->transceiver = XCVR_INTERNAL;
223 ecmd->supported = skge_supported_modes(hw);
226 ecmd->port = PORT_TP;
227 ecmd->phy_address = hw->phy_addr;
229 ecmd->port = PORT_FIBRE;
231 ecmd->advertising = skge->advertising;
232 ecmd->autoneg = skge->autoneg;
233 ecmd->speed = skge->speed;
234 ecmd->duplex = skge->duplex;
238 static int skge_set_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
240 struct skge_port *skge = netdev_priv(dev);
241 const struct skge_hw *hw = skge->hw;
242 u32 supported = skge_supported_modes(hw);
244 if (ecmd->autoneg == AUTONEG_ENABLE) {
245 ecmd->advertising = supported;
251 switch (ecmd->speed) {
253 if (ecmd->duplex == DUPLEX_FULL)
254 setting = SUPPORTED_1000baseT_Full;
255 else if (ecmd->duplex == DUPLEX_HALF)
256 setting = SUPPORTED_1000baseT_Half;
261 if (ecmd->duplex == DUPLEX_FULL)
262 setting = SUPPORTED_100baseT_Full;
263 else if (ecmd->duplex == DUPLEX_HALF)
264 setting = SUPPORTED_100baseT_Half;
270 if (ecmd->duplex == DUPLEX_FULL)
271 setting = SUPPORTED_10baseT_Full;
272 else if (ecmd->duplex == DUPLEX_HALF)
273 setting = SUPPORTED_10baseT_Half;
281 if ((setting & supported) == 0)
284 skge->speed = ecmd->speed;
285 skge->duplex = ecmd->duplex;
288 skge->autoneg = ecmd->autoneg;
289 skge->advertising = ecmd->advertising;
291 if (netif_running(dev)) {
298 static void skge_get_drvinfo(struct net_device *dev,
299 struct ethtool_drvinfo *info)
301 struct skge_port *skge = netdev_priv(dev);
303 strcpy(info->driver, DRV_NAME);
304 strcpy(info->version, DRV_VERSION);
305 strcpy(info->fw_version, "N/A");
306 strcpy(info->bus_info, pci_name(skge->hw->pdev));
309 static const struct skge_stat {
310 char name[ETH_GSTRING_LEN];
314 { "tx_bytes", XM_TXO_OK_HI, GM_TXO_OK_HI },
315 { "rx_bytes", XM_RXO_OK_HI, GM_RXO_OK_HI },
317 { "tx_broadcast", XM_TXF_BC_OK, GM_TXF_BC_OK },
318 { "rx_broadcast", XM_RXF_BC_OK, GM_RXF_BC_OK },
319 { "tx_multicast", XM_TXF_MC_OK, GM_TXF_MC_OK },
320 { "rx_multicast", XM_RXF_MC_OK, GM_RXF_MC_OK },
321 { "tx_unicast", XM_TXF_UC_OK, GM_TXF_UC_OK },
322 { "rx_unicast", XM_RXF_UC_OK, GM_RXF_UC_OK },
323 { "tx_mac_pause", XM_TXF_MPAUSE, GM_TXF_MPAUSE },
324 { "rx_mac_pause", XM_RXF_MPAUSE, GM_RXF_MPAUSE },
326 { "collisions", XM_TXF_SNG_COL, GM_TXF_SNG_COL },
327 { "multi_collisions", XM_TXF_MUL_COL, GM_TXF_MUL_COL },
328 { "aborted", XM_TXF_ABO_COL, GM_TXF_ABO_COL },
329 { "late_collision", XM_TXF_LAT_COL, GM_TXF_LAT_COL },
330 { "fifo_underrun", XM_TXE_FIFO_UR, GM_TXE_FIFO_UR },
331 { "fifo_overflow", XM_RXE_FIFO_OV, GM_RXE_FIFO_OV },
333 { "rx_toolong", XM_RXF_LNG_ERR, GM_RXF_LNG_ERR },
334 { "rx_jabber", XM_RXF_JAB_PKT, GM_RXF_JAB_PKT },
335 { "rx_runt", XM_RXE_RUNT, GM_RXE_FRAG },
336 { "rx_too_long", XM_RXF_LNG_ERR, GM_RXF_LNG_ERR },
337 { "rx_fcs_error", XM_RXF_FCS_ERR, GM_RXF_FCS_ERR },
340 static int skge_get_stats_count(struct net_device *dev)
342 return ARRAY_SIZE(skge_stats);
345 static void skge_get_ethtool_stats(struct net_device *dev,
346 struct ethtool_stats *stats, u64 *data)
348 struct skge_port *skge = netdev_priv(dev);
350 if (skge->hw->chip_id == CHIP_ID_GENESIS)
351 genesis_get_stats(skge, data);
353 yukon_get_stats(skge, data);
356 /* Use hardware MIB variables for critical path statistics and
357 * transmit feedback not reported at interrupt.
358 * Other errors are accounted for in interrupt handler.
360 static struct net_device_stats *skge_get_stats(struct net_device *dev)
362 struct skge_port *skge = netdev_priv(dev);
363 u64 data[ARRAY_SIZE(skge_stats)];
365 if (skge->hw->chip_id == CHIP_ID_GENESIS)
366 genesis_get_stats(skge, data);
368 yukon_get_stats(skge, data);
370 skge->net_stats.tx_bytes = data[0];
371 skge->net_stats.rx_bytes = data[1];
372 skge->net_stats.tx_packets = data[2] + data[4] + data[6];
373 skge->net_stats.rx_packets = data[3] + data[5] + data[7];
374 skge->net_stats.multicast = data[5] + data[7];
375 skge->net_stats.collisions = data[10];
376 skge->net_stats.tx_aborted_errors = data[12];
378 return &skge->net_stats;
381 static void skge_get_strings(struct net_device *dev, u32 stringset, u8 *data)
387 for (i = 0; i < ARRAY_SIZE(skge_stats); i++)
388 memcpy(data + i * ETH_GSTRING_LEN,
389 skge_stats[i].name, ETH_GSTRING_LEN);
394 static void skge_get_ring_param(struct net_device *dev,
395 struct ethtool_ringparam *p)
397 struct skge_port *skge = netdev_priv(dev);
399 p->rx_max_pending = MAX_RX_RING_SIZE;
400 p->tx_max_pending = MAX_TX_RING_SIZE;
401 p->rx_mini_max_pending = 0;
402 p->rx_jumbo_max_pending = 0;
404 p->rx_pending = skge->rx_ring.count;
405 p->tx_pending = skge->tx_ring.count;
406 p->rx_mini_pending = 0;
407 p->rx_jumbo_pending = 0;
410 static int skge_set_ring_param(struct net_device *dev,
411 struct ethtool_ringparam *p)
413 struct skge_port *skge = netdev_priv(dev);
415 if (p->rx_pending == 0 || p->rx_pending > MAX_RX_RING_SIZE ||
416 p->tx_pending == 0 || p->tx_pending > MAX_TX_RING_SIZE)
419 skge->rx_ring.count = p->rx_pending;
420 skge->tx_ring.count = p->tx_pending;
422 if (netif_running(dev)) {
430 static u32 skge_get_msglevel(struct net_device *netdev)
432 struct skge_port *skge = netdev_priv(netdev);
433 return skge->msg_enable;
436 static void skge_set_msglevel(struct net_device *netdev, u32 value)
438 struct skge_port *skge = netdev_priv(netdev);
439 skge->msg_enable = value;
442 static int skge_nway_reset(struct net_device *dev)
444 struct skge_port *skge = netdev_priv(dev);
445 struct skge_hw *hw = skge->hw;
446 int port = skge->port;
448 if (skge->autoneg != AUTONEG_ENABLE || !netif_running(dev))
451 spin_lock_bh(&hw->phy_lock);
452 if (hw->chip_id == CHIP_ID_GENESIS) {
453 genesis_reset(hw, port);
454 genesis_mac_init(hw, port);
456 yukon_reset(hw, port);
457 yukon_init(hw, port);
459 spin_unlock_bh(&hw->phy_lock);
463 static int skge_set_sg(struct net_device *dev, u32 data)
465 struct skge_port *skge = netdev_priv(dev);
466 struct skge_hw *hw = skge->hw;
468 if (hw->chip_id == CHIP_ID_GENESIS && data)
470 return ethtool_op_set_sg(dev, data);
473 static int skge_set_tx_csum(struct net_device *dev, u32 data)
475 struct skge_port *skge = netdev_priv(dev);
476 struct skge_hw *hw = skge->hw;
478 if (hw->chip_id == CHIP_ID_GENESIS && data)
481 return ethtool_op_set_tx_csum(dev, data);
484 static u32 skge_get_rx_csum(struct net_device *dev)
486 struct skge_port *skge = netdev_priv(dev);
488 return skge->rx_csum;
491 /* Only Yukon supports checksum offload. */
492 static int skge_set_rx_csum(struct net_device *dev, u32 data)
494 struct skge_port *skge = netdev_priv(dev);
496 if (skge->hw->chip_id == CHIP_ID_GENESIS && data)
499 skge->rx_csum = data;
503 static void skge_get_pauseparam(struct net_device *dev,
504 struct ethtool_pauseparam *ecmd)
506 struct skge_port *skge = netdev_priv(dev);
508 ecmd->tx_pause = (skge->flow_control == FLOW_MODE_LOC_SEND)
509 || (skge->flow_control == FLOW_MODE_SYMMETRIC);
510 ecmd->rx_pause = (skge->flow_control == FLOW_MODE_REM_SEND)
511 || (skge->flow_control == FLOW_MODE_SYMMETRIC);
513 ecmd->autoneg = skge->autoneg;
516 static int skge_set_pauseparam(struct net_device *dev,
517 struct ethtool_pauseparam *ecmd)
519 struct skge_port *skge = netdev_priv(dev);
521 skge->autoneg = ecmd->autoneg;
522 if (ecmd->rx_pause && ecmd->tx_pause)
523 skge->flow_control = FLOW_MODE_SYMMETRIC;
524 else if (ecmd->rx_pause && !ecmd->tx_pause)
525 skge->flow_control = FLOW_MODE_REM_SEND;
526 else if (!ecmd->rx_pause && ecmd->tx_pause)
527 skge->flow_control = FLOW_MODE_LOC_SEND;
529 skge->flow_control = FLOW_MODE_NONE;
531 if (netif_running(dev)) {
538 /* Chip internal frequency for clock calculations */
539 static inline u32 hwkhz(const struct skge_hw *hw)
541 if (hw->chip_id == CHIP_ID_GENESIS)
542 return 53215; /* or: 53.125 MHz */
544 return 78215; /* or: 78.125 MHz */
547 /* Chip hz to microseconds */
548 static inline u32 skge_clk2usec(const struct skge_hw *hw, u32 ticks)
550 return (ticks * 1000) / hwkhz(hw);
553 /* Microseconds to chip hz */
554 static inline u32 skge_usecs2clk(const struct skge_hw *hw, u32 usec)
556 return hwkhz(hw) * usec / 1000;
559 static int skge_get_coalesce(struct net_device *dev,
560 struct ethtool_coalesce *ecmd)
562 struct skge_port *skge = netdev_priv(dev);
563 struct skge_hw *hw = skge->hw;
564 int port = skge->port;
566 ecmd->rx_coalesce_usecs = 0;
567 ecmd->tx_coalesce_usecs = 0;
569 if (skge_read32(hw, B2_IRQM_CTRL) & TIM_START) {
570 u32 delay = skge_clk2usec(hw, skge_read32(hw, B2_IRQM_INI));
571 u32 msk = skge_read32(hw, B2_IRQM_MSK);
573 if (msk & rxirqmask[port])
574 ecmd->rx_coalesce_usecs = delay;
575 if (msk & txirqmask[port])
576 ecmd->tx_coalesce_usecs = delay;
582 /* Note: interrupt timer is per board, but can turn on/off per port */
583 static int skge_set_coalesce(struct net_device *dev,
584 struct ethtool_coalesce *ecmd)
586 struct skge_port *skge = netdev_priv(dev);
587 struct skge_hw *hw = skge->hw;
588 int port = skge->port;
589 u32 msk = skge_read32(hw, B2_IRQM_MSK);
592 if (ecmd->rx_coalesce_usecs == 0)
593 msk &= ~rxirqmask[port];
594 else if (ecmd->rx_coalesce_usecs < 25 ||
595 ecmd->rx_coalesce_usecs > 33333)
598 msk |= rxirqmask[port];
599 delay = ecmd->rx_coalesce_usecs;
602 if (ecmd->tx_coalesce_usecs == 0)
603 msk &= ~txirqmask[port];
604 else if (ecmd->tx_coalesce_usecs < 25 ||
605 ecmd->tx_coalesce_usecs > 33333)
608 msk |= txirqmask[port];
609 delay = min(delay, ecmd->rx_coalesce_usecs);
612 skge_write32(hw, B2_IRQM_MSK, msk);
614 skge_write32(hw, B2_IRQM_CTRL, TIM_STOP);
616 skge_write32(hw, B2_IRQM_INI, skge_usecs2clk(hw, delay));
617 skge_write32(hw, B2_IRQM_CTRL, TIM_START);
622 enum led_mode { LED_MODE_OFF, LED_MODE_ON, LED_MODE_TST };
623 static void skge_led(struct skge_port *skge, enum led_mode mode)
625 struct skge_hw *hw = skge->hw;
626 int port = skge->port;
628 spin_lock_bh(&hw->phy_lock);
629 if (hw->chip_id == CHIP_ID_GENESIS) {
632 xm_phy_write(hw, port, PHY_BCOM_P_EXT_CTRL, PHY_B_PEC_LED_OFF);
633 skge_write8(hw, SK_REG(port, LNK_LED_REG), LINKLED_OFF);
634 skge_write32(hw, SK_REG(port, RX_LED_VAL), 0);
635 skge_write8(hw, SK_REG(port, RX_LED_CTRL), LED_T_OFF);
639 skge_write8(hw, SK_REG(port, LNK_LED_REG), LINKLED_ON);
640 skge_write8(hw, SK_REG(port, LNK_LED_REG), LINKLED_LINKSYNC_ON);
642 skge_write8(hw, SK_REG(port, RX_LED_CTRL), LED_START);
643 skge_write8(hw, SK_REG(port, TX_LED_CTRL), LED_START);
648 skge_write8(hw, SK_REG(port, RX_LED_TST), LED_T_ON);
649 skge_write32(hw, SK_REG(port, RX_LED_VAL), 100);
650 skge_write8(hw, SK_REG(port, RX_LED_CTRL), LED_START);
652 xm_phy_write(hw, port, PHY_BCOM_P_EXT_CTRL, PHY_B_PEC_LED_ON);
658 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, 0);
659 gm_phy_write(hw, port, PHY_MARV_LED_OVER,
660 PHY_M_LED_MO_DUP(MO_LED_OFF) |
661 PHY_M_LED_MO_10(MO_LED_OFF) |
662 PHY_M_LED_MO_100(MO_LED_OFF) |
663 PHY_M_LED_MO_1000(MO_LED_OFF) |
664 PHY_M_LED_MO_RX(MO_LED_OFF));
667 gm_phy_write(hw, port, PHY_MARV_LED_CTRL,
668 PHY_M_LED_PULS_DUR(PULS_170MS) |
669 PHY_M_LED_BLINK_RT(BLINK_84MS) |
673 gm_phy_write(hw, port, PHY_MARV_LED_OVER,
674 PHY_M_LED_MO_RX(MO_LED_OFF) |
675 (skge->speed == SPEED_100 ?
676 PHY_M_LED_MO_100(MO_LED_ON) : 0));
679 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, 0);
680 gm_phy_write(hw, port, PHY_MARV_LED_OVER,
681 PHY_M_LED_MO_DUP(MO_LED_ON) |
682 PHY_M_LED_MO_10(MO_LED_ON) |
683 PHY_M_LED_MO_100(MO_LED_ON) |
684 PHY_M_LED_MO_1000(MO_LED_ON) |
685 PHY_M_LED_MO_RX(MO_LED_ON));
688 spin_unlock_bh(&hw->phy_lock);
691 /* blink LED's for finding board */
692 static int skge_phys_id(struct net_device *dev, u32 data)
694 struct skge_port *skge = netdev_priv(dev);
696 enum led_mode mode = LED_MODE_TST;
698 if (!data || data > (u32)(MAX_SCHEDULE_TIMEOUT / HZ))
699 ms = jiffies_to_msecs(MAX_SCHEDULE_TIMEOUT / HZ) * 1000;
704 skge_led(skge, mode);
705 mode ^= LED_MODE_TST;
707 if (msleep_interruptible(BLINK_MS))
712 /* back to regular LED state */
713 skge_led(skge, netif_running(dev) ? LED_MODE_ON : LED_MODE_OFF);
718 static struct ethtool_ops skge_ethtool_ops = {
719 .get_settings = skge_get_settings,
720 .set_settings = skge_set_settings,
721 .get_drvinfo = skge_get_drvinfo,
722 .get_regs_len = skge_get_regs_len,
723 .get_regs = skge_get_regs,
724 .get_wol = skge_get_wol,
725 .set_wol = skge_set_wol,
726 .get_msglevel = skge_get_msglevel,
727 .set_msglevel = skge_set_msglevel,
728 .nway_reset = skge_nway_reset,
729 .get_link = ethtool_op_get_link,
730 .get_ringparam = skge_get_ring_param,
731 .set_ringparam = skge_set_ring_param,
732 .get_pauseparam = skge_get_pauseparam,
733 .set_pauseparam = skge_set_pauseparam,
734 .get_coalesce = skge_get_coalesce,
735 .set_coalesce = skge_set_coalesce,
736 .get_sg = ethtool_op_get_sg,
737 .set_sg = skge_set_sg,
738 .get_tx_csum = ethtool_op_get_tx_csum,
739 .set_tx_csum = skge_set_tx_csum,
740 .get_rx_csum = skge_get_rx_csum,
741 .set_rx_csum = skge_set_rx_csum,
742 .get_strings = skge_get_strings,
743 .phys_id = skge_phys_id,
744 .get_stats_count = skge_get_stats_count,
745 .get_ethtool_stats = skge_get_ethtool_stats,
746 .get_perm_addr = ethtool_op_get_perm_addr,
750 * Allocate ring elements and chain them together
751 * One-to-one association of board descriptors with ring elements
753 static int skge_ring_alloc(struct skge_ring *ring, void *vaddr, u64 base)
755 struct skge_tx_desc *d;
756 struct skge_element *e;
759 ring->start = kmalloc(sizeof(*e)*ring->count, GFP_KERNEL);
763 for (i = 0, e = ring->start, d = vaddr; i < ring->count; i++, e++, d++) {
766 if (i == ring->count - 1) {
767 e->next = ring->start;
768 d->next_offset = base;
771 d->next_offset = base + (i+1) * sizeof(*d);
774 ring->to_use = ring->to_clean = ring->start;
779 static struct sk_buff *skge_rx_alloc(struct net_device *dev, unsigned int size)
781 struct sk_buff *skb = dev_alloc_skb(size);
785 skb_reserve(skb, NET_IP_ALIGN);
790 /* Allocate and setup a new buffer for receiving */
791 static void skge_rx_setup(struct skge_port *skge, struct skge_element *e,
792 struct sk_buff *skb, unsigned int bufsize)
794 struct skge_rx_desc *rd = e->desc;
797 map = pci_map_single(skge->hw->pdev, skb->data, bufsize,
801 rd->dma_hi = map >> 32;
803 rd->csum1_start = ETH_HLEN;
804 rd->csum2_start = ETH_HLEN;
810 rd->control = BMU_OWN | BMU_STF | BMU_IRQ_EOF | BMU_TCP_CHECK | bufsize;
811 pci_unmap_addr_set(e, mapaddr, map);
812 pci_unmap_len_set(e, maplen, bufsize);
815 /* Resume receiving using existing skb,
816 * Note: DMA address is not changed by chip.
817 * MTU not changed while receiver active.
819 static void skge_rx_reuse(struct skge_element *e, unsigned int size)
821 struct skge_rx_desc *rd = e->desc;
824 rd->csum2_start = ETH_HLEN;
828 rd->control = BMU_OWN | BMU_STF | BMU_IRQ_EOF | BMU_TCP_CHECK | size;
832 /* Free all buffers in receive ring, assumes receiver stopped */
833 static void skge_rx_clean(struct skge_port *skge)
835 struct skge_hw *hw = skge->hw;
836 struct skge_ring *ring = &skge->rx_ring;
837 struct skge_element *e;
841 struct skge_rx_desc *rd = e->desc;
844 pci_unmap_single(hw->pdev,
845 pci_unmap_addr(e, mapaddr),
846 pci_unmap_len(e, maplen),
848 dev_kfree_skb(e->skb);
851 } while ((e = e->next) != ring->start);
855 /* Allocate buffers for receive ring
856 * For receive: to_clean is next received frame.
858 static int skge_rx_fill(struct skge_port *skge)
860 struct skge_ring *ring = &skge->rx_ring;
861 struct skge_element *e;
862 unsigned int bufsize = skge->rx_buf_size;
866 struct sk_buff *skb = skge_rx_alloc(skge->netdev, bufsize);
871 skge_rx_setup(skge, e, skb, bufsize);
872 } while ( (e = e->next) != ring->start);
874 ring->to_clean = ring->start;
878 static void skge_link_up(struct skge_port *skge)
880 skge_write8(skge->hw, SK_REG(skge->port, LNK_LED_REG),
881 LED_BLK_OFF|LED_SYNC_OFF|LED_ON);
883 netif_carrier_on(skge->netdev);
884 if (skge->tx_avail > MAX_SKB_FRAGS + 1)
885 netif_wake_queue(skge->netdev);
887 if (netif_msg_link(skge))
889 "%s: Link is up at %d Mbps, %s duplex, flow control %s\n",
890 skge->netdev->name, skge->speed,
891 skge->duplex == DUPLEX_FULL ? "full" : "half",
892 (skge->flow_control == FLOW_MODE_NONE) ? "none" :
893 (skge->flow_control == FLOW_MODE_LOC_SEND) ? "tx only" :
894 (skge->flow_control == FLOW_MODE_REM_SEND) ? "rx only" :
895 (skge->flow_control == FLOW_MODE_SYMMETRIC) ? "tx and rx" :
899 static void skge_link_down(struct skge_port *skge)
901 skge_write8(skge->hw, SK_REG(skge->port, LNK_LED_REG), LED_OFF);
902 netif_carrier_off(skge->netdev);
903 netif_stop_queue(skge->netdev);
905 if (netif_msg_link(skge))
906 printk(KERN_INFO PFX "%s: Link is down.\n", skge->netdev->name);
909 static u16 xm_phy_read(struct skge_hw *hw, int port, u16 reg)
914 xm_write16(hw, port, XM_PHY_ADDR, reg | hw->phy_addr);
915 v = xm_read16(hw, port, XM_PHY_DATA);
917 /* Need to wait for external PHY */
918 for (i = 0; i < PHY_RETRIES; i++) {
920 if (xm_read16(hw, port, XM_MMU_CMD)
925 printk(KERN_WARNING PFX "%s: phy read timed out\n",
926 hw->dev[port]->name);
929 v = xm_read16(hw, port, XM_PHY_DATA);
934 static void xm_phy_write(struct skge_hw *hw, int port, u16 reg, u16 val)
938 xm_write16(hw, port, XM_PHY_ADDR, reg | hw->phy_addr);
939 for (i = 0; i < PHY_RETRIES; i++) {
940 if (!(xm_read16(hw, port, XM_MMU_CMD) & XM_MMU_PHY_BUSY))
944 printk(KERN_WARNING PFX "%s: phy write failed to come ready\n",
945 hw->dev[port]->name);
949 xm_write16(hw, port, XM_PHY_DATA, val);
950 for (i = 0; i < PHY_RETRIES; i++) {
952 if (!(xm_read16(hw, port, XM_MMU_CMD) & XM_MMU_PHY_BUSY))
955 printk(KERN_WARNING PFX "%s: phy write timed out\n",
956 hw->dev[port]->name);
959 static void genesis_init(struct skge_hw *hw)
961 /* set blink source counter */
962 skge_write32(hw, B2_BSC_INI, (SK_BLK_DUR * SK_FACT_53) / 100);
963 skge_write8(hw, B2_BSC_CTRL, BSC_START);
965 /* configure mac arbiter */
966 skge_write16(hw, B3_MA_TO_CTRL, MA_RST_CLR);
968 /* configure mac arbiter timeout values */
969 skge_write8(hw, B3_MA_TOINI_RX1, SK_MAC_TO_53);
970 skge_write8(hw, B3_MA_TOINI_RX2, SK_MAC_TO_53);
971 skge_write8(hw, B3_MA_TOINI_TX1, SK_MAC_TO_53);
972 skge_write8(hw, B3_MA_TOINI_TX2, SK_MAC_TO_53);
974 skge_write8(hw, B3_MA_RCINI_RX1, 0);
975 skge_write8(hw, B3_MA_RCINI_RX2, 0);
976 skge_write8(hw, B3_MA_RCINI_TX1, 0);
977 skge_write8(hw, B3_MA_RCINI_TX2, 0);
979 /* configure packet arbiter timeout */
980 skge_write16(hw, B3_PA_CTRL, PA_RST_CLR);
981 skge_write16(hw, B3_PA_TOINI_RX1, SK_PKT_TO_MAX);
982 skge_write16(hw, B3_PA_TOINI_TX1, SK_PKT_TO_MAX);
983 skge_write16(hw, B3_PA_TOINI_RX2, SK_PKT_TO_MAX);
984 skge_write16(hw, B3_PA_TOINI_TX2, SK_PKT_TO_MAX);
987 static void genesis_reset(struct skge_hw *hw, int port)
989 const u8 zero[8] = { 0 };
991 /* reset the statistics module */
992 xm_write32(hw, port, XM_GP_PORT, XM_GP_RES_STAT);
993 xm_write16(hw, port, XM_IMSK, 0xffff); /* disable XMAC IRQs */
994 xm_write32(hw, port, XM_MODE, 0); /* clear Mode Reg */
995 xm_write16(hw, port, XM_TX_CMD, 0); /* reset TX CMD Reg */
996 xm_write16(hw, port, XM_RX_CMD, 0); /* reset RX CMD Reg */
998 /* disable Broadcom PHY IRQ */
999 xm_write16(hw, port, PHY_BCOM_INT_MASK, 0xffff);
1001 xm_outhash(hw, port, XM_HSM, zero);
1005 /* Convert mode to MII values */
1006 static const u16 phy_pause_map[] = {
1007 [FLOW_MODE_NONE] = 0,
1008 [FLOW_MODE_LOC_SEND] = PHY_AN_PAUSE_ASYM,
1009 [FLOW_MODE_SYMMETRIC] = PHY_AN_PAUSE_CAP,
1010 [FLOW_MODE_REM_SEND] = PHY_AN_PAUSE_CAP | PHY_AN_PAUSE_ASYM,
1014 /* Check status of Broadcom phy link */
1015 static void bcom_check_link(struct skge_hw *hw, int port)
1017 struct net_device *dev = hw->dev[port];
1018 struct skge_port *skge = netdev_priv(dev);
1021 /* read twice because of latch */
1022 (void) xm_phy_read(hw, port, PHY_BCOM_STAT);
1023 status = xm_phy_read(hw, port, PHY_BCOM_STAT);
1025 pr_debug("bcom_check_link status=0x%x\n", status);
1027 if ((status & PHY_ST_LSYNC) == 0) {
1028 u16 cmd = xm_read16(hw, port, XM_MMU_CMD);
1029 cmd &= ~(XM_MMU_ENA_RX | XM_MMU_ENA_TX);
1030 xm_write16(hw, port, XM_MMU_CMD, cmd);
1031 /* dummy read to ensure writing */
1032 (void) xm_read16(hw, port, XM_MMU_CMD);
1034 if (netif_carrier_ok(dev))
1035 skge_link_down(skge);
1037 if (skge->autoneg == AUTONEG_ENABLE &&
1038 (status & PHY_ST_AN_OVER)) {
1039 u16 lpa = xm_phy_read(hw, port, PHY_BCOM_AUNE_LP);
1040 u16 aux = xm_phy_read(hw, port, PHY_BCOM_AUX_STAT);
1042 if (lpa & PHY_B_AN_RF) {
1043 printk(KERN_NOTICE PFX "%s: remote fault\n",
1048 /* Check Duplex mismatch */
1049 switch (aux & PHY_B_AS_AN_RES_MSK) {
1050 case PHY_B_RES_1000FD:
1051 skge->duplex = DUPLEX_FULL;
1053 case PHY_B_RES_1000HD:
1054 skge->duplex = DUPLEX_HALF;
1057 printk(KERN_NOTICE PFX "%s: duplex mismatch\n",
1063 /* We are using IEEE 802.3z/D5.0 Table 37-4 */
1064 switch (aux & PHY_B_AS_PAUSE_MSK) {
1065 case PHY_B_AS_PAUSE_MSK:
1066 skge->flow_control = FLOW_MODE_SYMMETRIC;
1069 skge->flow_control = FLOW_MODE_REM_SEND;
1072 skge->flow_control = FLOW_MODE_LOC_SEND;
1075 skge->flow_control = FLOW_MODE_NONE;
1078 skge->speed = SPEED_1000;
1081 if (!netif_carrier_ok(dev))
1082 genesis_link_up(skge);
1086 /* Broadcom 5400 only supports giagabit! SysKonnect did not put an additional
1087 * Phy on for 100 or 10Mbit operation
1089 static void bcom_phy_init(struct skge_port *skge, int jumbo)
1091 struct skge_hw *hw = skge->hw;
1092 int port = skge->port;
1094 u16 id1, r, ext, ctl;
1096 /* magic workaround patterns for Broadcom */
1097 static const struct {
1101 { 0x18, 0x0c20 }, { 0x17, 0x0012 }, { 0x15, 0x1104 },
1102 { 0x17, 0x0013 }, { 0x15, 0x0404 }, { 0x17, 0x8006 },
1103 { 0x15, 0x0132 }, { 0x17, 0x8006 }, { 0x15, 0x0232 },
1104 { 0x17, 0x800D }, { 0x15, 0x000F }, { 0x18, 0x0420 },
1106 { 0x18, 0x0c20 }, { 0x17, 0x0012 }, { 0x15, 0x1204 },
1107 { 0x17, 0x0013 }, { 0x15, 0x0A04 }, { 0x18, 0x0420 },
1110 pr_debug("bcom_phy_init\n");
1112 /* read Id from external PHY (all have the same address) */
1113 id1 = xm_phy_read(hw, port, PHY_XMAC_ID1);
1115 /* Optimize MDIO transfer by suppressing preamble. */
1116 r = xm_read16(hw, port, XM_MMU_CMD);
1118 xm_write16(hw, port, XM_MMU_CMD,r);
1121 case PHY_BCOM_ID1_C0:
1123 * Workaround BCOM Errata for the C0 type.
1124 * Write magic patterns to reserved registers.
1126 for (i = 0; i < ARRAY_SIZE(C0hack); i++)
1127 xm_phy_write(hw, port,
1128 C0hack[i].reg, C0hack[i].val);
1131 case PHY_BCOM_ID1_A1:
1133 * Workaround BCOM Errata for the A1 type.
1134 * Write magic patterns to reserved registers.
1136 for (i = 0; i < ARRAY_SIZE(A1hack); i++)
1137 xm_phy_write(hw, port,
1138 A1hack[i].reg, A1hack[i].val);
1143 * Workaround BCOM Errata (#10523) for all BCom PHYs.
1144 * Disable Power Management after reset.
1146 r = xm_phy_read(hw, port, PHY_BCOM_AUX_CTRL);
1147 r |= PHY_B_AC_DIS_PM;
1148 xm_phy_write(hw, port, PHY_BCOM_AUX_CTRL, r);
1151 xm_read16(hw, port, XM_ISRC);
1153 ext = PHY_B_PEC_EN_LTR; /* enable tx led */
1154 ctl = PHY_CT_SP1000; /* always 1000mbit */
1156 if (skge->autoneg == AUTONEG_ENABLE) {
1158 * Workaround BCOM Errata #1 for the C5 type.
1159 * 1000Base-T Link Acquisition Failure in Slave Mode
1160 * Set Repeater/DTE bit 10 of the 1000Base-T Control Register
1162 u16 adv = PHY_B_1000C_RD;
1163 if (skge->advertising & ADVERTISED_1000baseT_Half)
1164 adv |= PHY_B_1000C_AHD;
1165 if (skge->advertising & ADVERTISED_1000baseT_Full)
1166 adv |= PHY_B_1000C_AFD;
1167 xm_phy_write(hw, port, PHY_BCOM_1000T_CTRL, adv);
1169 ctl |= PHY_CT_ANE | PHY_CT_RE_CFG;
1171 if (skge->duplex == DUPLEX_FULL)
1172 ctl |= PHY_CT_DUP_MD;
1173 /* Force to slave */
1174 xm_phy_write(hw, port, PHY_BCOM_1000T_CTRL, PHY_B_1000C_MSE);
1177 /* Set autonegotiation pause parameters */
1178 xm_phy_write(hw, port, PHY_BCOM_AUNE_ADV,
1179 phy_pause_map[skge->flow_control] | PHY_AN_CSMA);
1181 /* Handle Jumbo frames */
1183 xm_phy_write(hw, port, PHY_BCOM_AUX_CTRL,
1184 PHY_B_AC_TX_TST | PHY_B_AC_LONG_PACK);
1186 ext |= PHY_B_PEC_HIGH_LA;
1190 xm_phy_write(hw, port, PHY_BCOM_P_EXT_CTRL, ext);
1191 xm_phy_write(hw, port, PHY_BCOM_CTRL, ctl);
1193 /* Use link status change interrrupt */
1194 xm_phy_write(hw, port, PHY_BCOM_INT_MASK, PHY_B_DEF_MSK);
1196 bcom_check_link(hw, port);
1199 static void genesis_mac_init(struct skge_hw *hw, int port)
1201 struct net_device *dev = hw->dev[port];
1202 struct skge_port *skge = netdev_priv(dev);
1203 int jumbo = hw->dev[port]->mtu > ETH_DATA_LEN;
1206 const u8 zero[6] = { 0 };
1208 /* Clear MIB counters */
1209 xm_write16(hw, port, XM_STAT_CMD,
1210 XM_SC_CLR_RXC | XM_SC_CLR_TXC);
1211 /* Clear two times according to Errata #3 */
1212 xm_write16(hw, port, XM_STAT_CMD,
1213 XM_SC_CLR_RXC | XM_SC_CLR_TXC);
1215 /* Unreset the XMAC. */
1216 skge_write16(hw, SK_REG(port, TX_MFF_CTRL1), MFF_CLR_MAC_RST);
1219 * Perform additional initialization for external PHYs,
1220 * namely for the 1000baseTX cards that use the XMAC's
1223 /* Take external Phy out of reset */
1224 r = skge_read32(hw, B2_GP_IO);
1226 r |= GP_DIR_0|GP_IO_0;
1228 r |= GP_DIR_2|GP_IO_2;
1230 skge_write32(hw, B2_GP_IO, r);
1231 skge_read32(hw, B2_GP_IO);
1233 /* Enable GMII interfac */
1234 xm_write16(hw, port, XM_HW_CFG, XM_HW_GMII_MD);
1236 bcom_phy_init(skge, jumbo);
1238 /* Set Station Address */
1239 xm_outaddr(hw, port, XM_SA, dev->dev_addr);
1241 /* We don't use match addresses so clear */
1242 for (i = 1; i < 16; i++)
1243 xm_outaddr(hw, port, XM_EXM(i), zero);
1245 /* configure Rx High Water Mark (XM_RX_HI_WM) */
1246 xm_write16(hw, port, XM_RX_HI_WM, 1450);
1248 /* We don't need the FCS appended to the packet. */
1249 r = XM_RX_LENERR_OK | XM_RX_STRIP_FCS;
1251 r |= XM_RX_BIG_PK_OK;
1253 if (skge->duplex == DUPLEX_HALF) {
1255 * If in manual half duplex mode the other side might be in
1256 * full duplex mode, so ignore if a carrier extension is not seen
1257 * on frames received
1259 r |= XM_RX_DIS_CEXT;
1261 xm_write16(hw, port, XM_RX_CMD, r);
1264 /* We want short frames padded to 60 bytes. */
1265 xm_write16(hw, port, XM_TX_CMD, XM_TX_AUTO_PAD);
1268 * Bump up the transmit threshold. This helps hold off transmit
1269 * underruns when we're blasting traffic from both ports at once.
1271 xm_write16(hw, port, XM_TX_THR, 512);
1274 * Enable the reception of all error frames. This is is
1275 * a necessary evil due to the design of the XMAC. The
1276 * XMAC's receive FIFO is only 8K in size, however jumbo
1277 * frames can be up to 9000 bytes in length. When bad
1278 * frame filtering is enabled, the XMAC's RX FIFO operates
1279 * in 'store and forward' mode. For this to work, the
1280 * entire frame has to fit into the FIFO, but that means
1281 * that jumbo frames larger than 8192 bytes will be
1282 * truncated. Disabling all bad frame filtering causes
1283 * the RX FIFO to operate in streaming mode, in which
1284 * case the XMAC will start transfering frames out of the
1285 * RX FIFO as soon as the FIFO threshold is reached.
1287 xm_write32(hw, port, XM_MODE, XM_DEF_MODE);
1291 * Initialize the Receive Counter Event Mask (XM_RX_EV_MSK)
1292 * - Enable all bits excepting 'Octets Rx OK Low CntOv'
1293 * and 'Octets Rx OK Hi Cnt Ov'.
1295 xm_write32(hw, port, XM_RX_EV_MSK, XMR_DEF_MSK);
1298 * Initialize the Transmit Counter Event Mask (XM_TX_EV_MSK)
1299 * - Enable all bits excepting 'Octets Tx OK Low CntOv'
1300 * and 'Octets Tx OK Hi Cnt Ov'.
1302 xm_write32(hw, port, XM_TX_EV_MSK, XMT_DEF_MSK);
1304 /* Configure MAC arbiter */
1305 skge_write16(hw, B3_MA_TO_CTRL, MA_RST_CLR);
1307 /* configure timeout values */
1308 skge_write8(hw, B3_MA_TOINI_RX1, 72);
1309 skge_write8(hw, B3_MA_TOINI_RX2, 72);
1310 skge_write8(hw, B3_MA_TOINI_TX1, 72);
1311 skge_write8(hw, B3_MA_TOINI_TX2, 72);
1313 skge_write8(hw, B3_MA_RCINI_RX1, 0);
1314 skge_write8(hw, B3_MA_RCINI_RX2, 0);
1315 skge_write8(hw, B3_MA_RCINI_TX1, 0);
1316 skge_write8(hw, B3_MA_RCINI_TX2, 0);
1318 /* Configure Rx MAC FIFO */
1319 skge_write8(hw, SK_REG(port, RX_MFF_CTRL2), MFF_RST_CLR);
1320 skge_write16(hw, SK_REG(port, RX_MFF_CTRL1), MFF_ENA_TIM_PAT);
1321 skge_write8(hw, SK_REG(port, RX_MFF_CTRL2), MFF_ENA_OP_MD);
1323 /* Configure Tx MAC FIFO */
1324 skge_write8(hw, SK_REG(port, TX_MFF_CTRL2), MFF_RST_CLR);
1325 skge_write16(hw, SK_REG(port, TX_MFF_CTRL1), MFF_TX_CTRL_DEF);
1326 skge_write8(hw, SK_REG(port, TX_MFF_CTRL2), MFF_ENA_OP_MD);
1329 /* Enable frame flushing if jumbo frames used */
1330 skge_write16(hw, SK_REG(port,RX_MFF_CTRL1), MFF_ENA_FLUSH);
1332 /* enable timeout timers if normal frames */
1333 skge_write16(hw, B3_PA_CTRL,
1334 (port == 0) ? PA_ENA_TO_TX1 : PA_ENA_TO_TX2);
1338 static void genesis_stop(struct skge_port *skge)
1340 struct skge_hw *hw = skge->hw;
1341 int port = skge->port;
1344 /* Clear Tx packet arbiter timeout IRQ */
1345 skge_write16(hw, B3_PA_CTRL,
1346 port == 0 ? PA_CLR_TO_TX1 : PA_CLR_TO_TX2);
1349 * If the transfer stucks at the MAC the STOP command will not
1350 * terminate if we don't flush the XMAC's transmit FIFO !
1352 xm_write32(hw, port, XM_MODE,
1353 xm_read32(hw, port, XM_MODE)|XM_MD_FTF);
1357 skge_write16(hw, SK_REG(port, TX_MFF_CTRL1), MFF_SET_MAC_RST);
1359 /* For external PHYs there must be special handling */
1360 reg = skge_read32(hw, B2_GP_IO);
1368 skge_write32(hw, B2_GP_IO, reg);
1369 skge_read32(hw, B2_GP_IO);
1371 xm_write16(hw, port, XM_MMU_CMD,
1372 xm_read16(hw, port, XM_MMU_CMD)
1373 & ~(XM_MMU_ENA_RX | XM_MMU_ENA_TX));
1375 xm_read16(hw, port, XM_MMU_CMD);
1379 static void genesis_get_stats(struct skge_port *skge, u64 *data)
1381 struct skge_hw *hw = skge->hw;
1382 int port = skge->port;
1384 unsigned long timeout = jiffies + HZ;
1386 xm_write16(hw, port,
1387 XM_STAT_CMD, XM_SC_SNP_TXC | XM_SC_SNP_RXC);
1389 /* wait for update to complete */
1390 while (xm_read16(hw, port, XM_STAT_CMD)
1391 & (XM_SC_SNP_TXC | XM_SC_SNP_RXC)) {
1392 if (time_after(jiffies, timeout))
1397 /* special case for 64 bit octet counter */
1398 data[0] = (u64) xm_read32(hw, port, XM_TXO_OK_HI) << 32
1399 | xm_read32(hw, port, XM_TXO_OK_LO);
1400 data[1] = (u64) xm_read32(hw, port, XM_RXO_OK_HI) << 32
1401 | xm_read32(hw, port, XM_RXO_OK_LO);
1403 for (i = 2; i < ARRAY_SIZE(skge_stats); i++)
1404 data[i] = xm_read32(hw, port, skge_stats[i].xmac_offset);
1407 static void genesis_mac_intr(struct skge_hw *hw, int port)
1409 struct skge_port *skge = netdev_priv(hw->dev[port]);
1410 u16 status = xm_read16(hw, port, XM_ISRC);
1412 if (netif_msg_intr(skge))
1413 printk(KERN_DEBUG PFX "%s: mac interrupt status 0x%x\n",
1414 skge->netdev->name, status);
1416 if (status & XM_IS_TXF_UR) {
1417 xm_write32(hw, port, XM_MODE, XM_MD_FTF);
1418 ++skge->net_stats.tx_fifo_errors;
1420 if (status & XM_IS_RXF_OV) {
1421 xm_write32(hw, port, XM_MODE, XM_MD_FRF);
1422 ++skge->net_stats.rx_fifo_errors;
1426 static void gm_phy_write(struct skge_hw *hw, int port, u16 reg, u16 val)
1430 gma_write16(hw, port, GM_SMI_DATA, val);
1431 gma_write16(hw, port, GM_SMI_CTRL,
1432 GM_SMI_CT_PHY_AD(hw->phy_addr) | GM_SMI_CT_REG_AD(reg));
1433 for (i = 0; i < PHY_RETRIES; i++) {
1436 if (!(gma_read16(hw, port, GM_SMI_CTRL) & GM_SMI_CT_BUSY))
1441 static u16 gm_phy_read(struct skge_hw *hw, int port, u16 reg)
1445 gma_write16(hw, port, GM_SMI_CTRL,
1446 GM_SMI_CT_PHY_AD(hw->phy_addr)
1447 | GM_SMI_CT_REG_AD(reg) | GM_SMI_CT_OP_RD);
1449 for (i = 0; i < PHY_RETRIES; i++) {
1451 if (gma_read16(hw, port, GM_SMI_CTRL) & GM_SMI_CT_RD_VAL)
1455 printk(KERN_WARNING PFX "%s: phy read timeout\n",
1456 hw->dev[port]->name);
1459 return gma_read16(hw, port, GM_SMI_DATA);
1462 static void genesis_link_up(struct skge_port *skge)
1464 struct skge_hw *hw = skge->hw;
1465 int port = skge->port;
1469 pr_debug("genesis_link_up\n");
1470 cmd = xm_read16(hw, port, XM_MMU_CMD);
1473 * enabling pause frame reception is required for 1000BT
1474 * because the XMAC is not reset if the link is going down
1476 if (skge->flow_control == FLOW_MODE_NONE ||
1477 skge->flow_control == FLOW_MODE_LOC_SEND)
1478 /* Disable Pause Frame Reception */
1479 cmd |= XM_MMU_IGN_PF;
1481 /* Enable Pause Frame Reception */
1482 cmd &= ~XM_MMU_IGN_PF;
1484 xm_write16(hw, port, XM_MMU_CMD, cmd);
1486 mode = xm_read32(hw, port, XM_MODE);
1487 if (skge->flow_control == FLOW_MODE_SYMMETRIC ||
1488 skge->flow_control == FLOW_MODE_LOC_SEND) {
1490 * Configure Pause Frame Generation
1491 * Use internal and external Pause Frame Generation.
1492 * Sending pause frames is edge triggered.
1493 * Send a Pause frame with the maximum pause time if
1494 * internal oder external FIFO full condition occurs.
1495 * Send a zero pause time frame to re-start transmission.
1497 /* XM_PAUSE_DA = '010000C28001' (default) */
1498 /* XM_MAC_PTIME = 0xffff (maximum) */
1499 /* remember this value is defined in big endian (!) */
1500 xm_write16(hw, port, XM_MAC_PTIME, 0xffff);
1502 mode |= XM_PAUSE_MODE;
1503 skge_write16(hw, SK_REG(port, RX_MFF_CTRL1), MFF_ENA_PAUSE);
1506 * disable pause frame generation is required for 1000BT
1507 * because the XMAC is not reset if the link is going down
1509 /* Disable Pause Mode in Mode Register */
1510 mode &= ~XM_PAUSE_MODE;
1512 skge_write16(hw, SK_REG(port, RX_MFF_CTRL1), MFF_DIS_PAUSE);
1515 xm_write32(hw, port, XM_MODE, mode);
1518 /* disable GP0 interrupt bit for external Phy */
1519 msk |= XM_IS_INP_ASS;
1521 xm_write16(hw, port, XM_IMSK, msk);
1522 xm_read16(hw, port, XM_ISRC);
1524 /* get MMU Command Reg. */
1525 cmd = xm_read16(hw, port, XM_MMU_CMD);
1526 if (skge->duplex == DUPLEX_FULL)
1527 cmd |= XM_MMU_GMII_FD;
1530 * Workaround BCOM Errata (#10523) for all BCom Phys
1531 * Enable Power Management after link up
1533 xm_phy_write(hw, port, PHY_BCOM_AUX_CTRL,
1534 xm_phy_read(hw, port, PHY_BCOM_AUX_CTRL)
1535 & ~PHY_B_AC_DIS_PM);
1536 xm_phy_write(hw, port, PHY_BCOM_INT_MASK, PHY_B_DEF_MSK);
1539 xm_write16(hw, port, XM_MMU_CMD,
1540 cmd | XM_MMU_ENA_RX | XM_MMU_ENA_TX);
1545 static inline void bcom_phy_intr(struct skge_port *skge)
1547 struct skge_hw *hw = skge->hw;
1548 int port = skge->port;
1551 isrc = xm_phy_read(hw, port, PHY_BCOM_INT_STAT);
1552 if (netif_msg_intr(skge))
1553 printk(KERN_DEBUG PFX "%s: phy interrupt status 0x%x\n",
1554 skge->netdev->name, isrc);
1556 if (isrc & PHY_B_IS_PSE)
1557 printk(KERN_ERR PFX "%s: uncorrectable pair swap error\n",
1558 hw->dev[port]->name);
1560 /* Workaround BCom Errata:
1561 * enable and disable loopback mode if "NO HCD" occurs.
1563 if (isrc & PHY_B_IS_NO_HDCL) {
1564 u16 ctrl = xm_phy_read(hw, port, PHY_BCOM_CTRL);
1565 xm_phy_write(hw, port, PHY_BCOM_CTRL,
1566 ctrl | PHY_CT_LOOP);
1567 xm_phy_write(hw, port, PHY_BCOM_CTRL,
1568 ctrl & ~PHY_CT_LOOP);
1571 if (isrc & (PHY_B_IS_AN_PR | PHY_B_IS_LST_CHANGE))
1572 bcom_check_link(hw, port);
1576 /* Marvell Phy Initailization */
1577 static void yukon_init(struct skge_hw *hw, int port)
1579 struct skge_port *skge = netdev_priv(hw->dev[port]);
1580 u16 ctrl, ct1000, adv;
1582 pr_debug("yukon_init\n");
1583 if (skge->autoneg == AUTONEG_ENABLE) {
1584 u16 ectrl = gm_phy_read(hw, port, PHY_MARV_EXT_CTRL);
1586 ectrl &= ~(PHY_M_EC_M_DSC_MSK | PHY_M_EC_S_DSC_MSK |
1587 PHY_M_EC_MAC_S_MSK);
1588 ectrl |= PHY_M_EC_MAC_S(MAC_TX_CLK_25_MHZ);
1590 ectrl |= PHY_M_EC_M_DSC(0) | PHY_M_EC_S_DSC(1);
1592 gm_phy_write(hw, port, PHY_MARV_EXT_CTRL, ectrl);
1595 ctrl = gm_phy_read(hw, port, PHY_MARV_CTRL);
1596 if (skge->autoneg == AUTONEG_DISABLE)
1597 ctrl &= ~PHY_CT_ANE;
1599 ctrl |= PHY_CT_RESET;
1600 gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
1606 if (skge->autoneg == AUTONEG_ENABLE) {
1608 if (skge->advertising & ADVERTISED_1000baseT_Full)
1609 ct1000 |= PHY_M_1000C_AFD;
1610 if (skge->advertising & ADVERTISED_1000baseT_Half)
1611 ct1000 |= PHY_M_1000C_AHD;
1612 if (skge->advertising & ADVERTISED_100baseT_Full)
1613 adv |= PHY_M_AN_100_FD;
1614 if (skge->advertising & ADVERTISED_100baseT_Half)
1615 adv |= PHY_M_AN_100_HD;
1616 if (skge->advertising & ADVERTISED_10baseT_Full)
1617 adv |= PHY_M_AN_10_FD;
1618 if (skge->advertising & ADVERTISED_10baseT_Half)
1619 adv |= PHY_M_AN_10_HD;
1620 } else /* special defines for FIBER (88E1011S only) */
1621 adv |= PHY_M_AN_1000X_AHD | PHY_M_AN_1000X_AFD;
1623 /* Set Flow-control capabilities */
1624 adv |= phy_pause_map[skge->flow_control];
1626 /* Restart Auto-negotiation */
1627 ctrl |= PHY_CT_ANE | PHY_CT_RE_CFG;
1629 /* forced speed/duplex settings */
1630 ct1000 = PHY_M_1000C_MSE;
1632 if (skge->duplex == DUPLEX_FULL)
1633 ctrl |= PHY_CT_DUP_MD;
1635 switch (skge->speed) {
1637 ctrl |= PHY_CT_SP1000;
1640 ctrl |= PHY_CT_SP100;
1644 ctrl |= PHY_CT_RESET;
1647 gm_phy_write(hw, port, PHY_MARV_1000T_CTRL, ct1000);
1649 gm_phy_write(hw, port, PHY_MARV_AUNE_ADV, adv);
1650 gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
1652 /* Enable phy interrupt on autonegotiation complete (or link up) */
1653 if (skge->autoneg == AUTONEG_ENABLE)
1654 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_IS_AN_MSK);
1656 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_IS_DEF_MSK);
1659 static void yukon_reset(struct skge_hw *hw, int port)
1661 gm_phy_write(hw, port, PHY_MARV_INT_MASK, 0);/* disable PHY IRQs */
1662 gma_write16(hw, port, GM_MC_ADDR_H1, 0); /* clear MC hash */
1663 gma_write16(hw, port, GM_MC_ADDR_H2, 0);
1664 gma_write16(hw, port, GM_MC_ADDR_H3, 0);
1665 gma_write16(hw, port, GM_MC_ADDR_H4, 0);
1667 gma_write16(hw, port, GM_RX_CTRL,
1668 gma_read16(hw, port, GM_RX_CTRL)
1669 | GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA);
1672 static void yukon_mac_init(struct skge_hw *hw, int port)
1674 struct skge_port *skge = netdev_priv(hw->dev[port]);
1677 const u8 *addr = hw->dev[port]->dev_addr;
1679 /* WA code for COMA mode -- set PHY reset */
1680 if (hw->chip_id == CHIP_ID_YUKON_LITE &&
1681 hw->chip_rev >= CHIP_REV_YU_LITE_A3)
1682 skge_write32(hw, B2_GP_IO,
1683 (skge_read32(hw, B2_GP_IO) | GP_DIR_9 | GP_IO_9));
1686 skge_write32(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET);
1687 skge_write32(hw, SK_REG(port, GMAC_CTRL), GMC_RST_SET);
1689 /* WA code for COMA mode -- clear PHY reset */
1690 if (hw->chip_id == CHIP_ID_YUKON_LITE &&
1691 hw->chip_rev >= CHIP_REV_YU_LITE_A3)
1692 skge_write32(hw, B2_GP_IO,
1693 (skge_read32(hw, B2_GP_IO) | GP_DIR_9)
1696 /* Set hardware config mode */
1697 reg = GPC_INT_POL_HI | GPC_DIS_FC | GPC_DIS_SLEEP |
1698 GPC_ENA_XC | GPC_ANEG_ADV_ALL_M | GPC_ENA_PAUSE;
1699 reg |= hw->copper ? GPC_HWCFG_GMII_COP : GPC_HWCFG_GMII_FIB;
1701 /* Clear GMC reset */
1702 skge_write32(hw, SK_REG(port, GPHY_CTRL), reg | GPC_RST_SET);
1703 skge_write32(hw, SK_REG(port, GPHY_CTRL), reg | GPC_RST_CLR);
1704 skge_write32(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON | GMC_RST_CLR);
1705 if (skge->autoneg == AUTONEG_DISABLE) {
1706 reg = GM_GPCR_AU_ALL_DIS;
1707 gma_write16(hw, port, GM_GP_CTRL,
1708 gma_read16(hw, port, GM_GP_CTRL) | reg);
1710 switch (skge->speed) {
1712 reg |= GM_GPCR_SPEED_1000;
1715 reg |= GM_GPCR_SPEED_100;
1718 if (skge->duplex == DUPLEX_FULL)
1719 reg |= GM_GPCR_DUP_FULL;
1721 reg = GM_GPCR_SPEED_1000 | GM_GPCR_SPEED_100 | GM_GPCR_DUP_FULL;
1722 switch (skge->flow_control) {
1723 case FLOW_MODE_NONE:
1724 skge_write32(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
1725 reg |= GM_GPCR_FC_TX_DIS | GM_GPCR_FC_RX_DIS | GM_GPCR_AU_FCT_DIS;
1727 case FLOW_MODE_LOC_SEND:
1728 /* disable Rx flow-control */
1729 reg |= GM_GPCR_FC_RX_DIS | GM_GPCR_AU_FCT_DIS;
1732 gma_write16(hw, port, GM_GP_CTRL, reg);
1733 skge_read16(hw, GMAC_IRQ_SRC);
1735 yukon_init(hw, port);
1738 reg = gma_read16(hw, port, GM_PHY_ADDR);
1739 gma_write16(hw, port, GM_PHY_ADDR, reg | GM_PAR_MIB_CLR);
1741 for (i = 0; i < GM_MIB_CNT_SIZE; i++)
1742 gma_read16(hw, port, GM_MIB_CNT_BASE + 8*i);
1743 gma_write16(hw, port, GM_PHY_ADDR, reg);
1745 /* transmit control */
1746 gma_write16(hw, port, GM_TX_CTRL, TX_COL_THR(TX_COL_DEF));
1748 /* receive control reg: unicast + multicast + no FCS */
1749 gma_write16(hw, port, GM_RX_CTRL,
1750 GM_RXCR_UCF_ENA | GM_RXCR_CRC_DIS | GM_RXCR_MCF_ENA);
1752 /* transmit flow control */
1753 gma_write16(hw, port, GM_TX_FLOW_CTRL, 0xffff);
1755 /* transmit parameter */
1756 gma_write16(hw, port, GM_TX_PARAM,
1757 TX_JAM_LEN_VAL(TX_JAM_LEN_DEF) |
1758 TX_JAM_IPG_VAL(TX_JAM_IPG_DEF) |
1759 TX_IPG_JAM_DATA(TX_IPG_JAM_DEF));
1761 /* serial mode register */
1762 reg = GM_SMOD_VLAN_ENA | IPG_DATA_VAL(IPG_DATA_DEF);
1763 if (hw->dev[port]->mtu > 1500)
1764 reg |= GM_SMOD_JUMBO_ENA;
1766 gma_write16(hw, port, GM_SERIAL_MODE, reg);
1768 /* physical address: used for pause frames */
1769 gma_set_addr(hw, port, GM_SRC_ADDR_1L, addr);
1770 /* virtual address for data */
1771 gma_set_addr(hw, port, GM_SRC_ADDR_2L, addr);
1773 /* enable interrupt mask for counter overflows */
1774 gma_write16(hw, port, GM_TX_IRQ_MSK, 0);
1775 gma_write16(hw, port, GM_RX_IRQ_MSK, 0);
1776 gma_write16(hw, port, GM_TR_IRQ_MSK, 0);
1778 /* Initialize Mac Fifo */
1780 /* Configure Rx MAC FIFO */
1781 skge_write16(hw, SK_REG(port, RX_GMF_FL_MSK), RX_FF_FL_DEF_MSK);
1782 reg = GMF_OPER_ON | GMF_RX_F_FL_ON;
1783 if (hw->chip_id == CHIP_ID_YUKON_LITE &&
1784 hw->chip_rev >= CHIP_REV_YU_LITE_A3)
1785 reg &= ~GMF_RX_F_FL_ON;
1786 skge_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_CLR);
1787 skge_write16(hw, SK_REG(port, RX_GMF_CTRL_T), reg);
1789 * because Pause Packet Truncation in GMAC is not working
1790 * we have to increase the Flush Threshold to 64 bytes
1791 * in order to flush pause packets in Rx FIFO on Yukon-1
1793 skge_write16(hw, SK_REG(port, RX_GMF_FL_THR), RX_GMF_FL_THR_DEF+1);
1795 /* Configure Tx MAC FIFO */
1796 skge_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_CLR);
1797 skge_write16(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_OPER_ON);
1800 static void yukon_stop(struct skge_port *skge)
1802 struct skge_hw *hw = skge->hw;
1803 int port = skge->port;
1805 if (hw->chip_id == CHIP_ID_YUKON_LITE &&
1806 hw->chip_rev >= CHIP_REV_YU_LITE_A3) {
1807 skge_write32(hw, B2_GP_IO,
1808 skge_read32(hw, B2_GP_IO) | GP_DIR_9 | GP_IO_9);
1811 gma_write16(hw, port, GM_GP_CTRL,
1812 gma_read16(hw, port, GM_GP_CTRL)
1813 & ~(GM_GPCR_TX_ENA|GM_GPCR_RX_ENA));
1814 gma_read16(hw, port, GM_GP_CTRL);
1816 /* set GPHY Control reset */
1817 skge_write32(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET);
1818 skge_write32(hw, SK_REG(port, GMAC_CTRL), GMC_RST_SET);
1821 static void yukon_get_stats(struct skge_port *skge, u64 *data)
1823 struct skge_hw *hw = skge->hw;
1824 int port = skge->port;
1827 data[0] = (u64) gma_read32(hw, port, GM_TXO_OK_HI) << 32
1828 | gma_read32(hw, port, GM_TXO_OK_LO);
1829 data[1] = (u64) gma_read32(hw, port, GM_RXO_OK_HI) << 32
1830 | gma_read32(hw, port, GM_RXO_OK_LO);
1832 for (i = 2; i < ARRAY_SIZE(skge_stats); i++)
1833 data[i] = gma_read32(hw, port,
1834 skge_stats[i].gma_offset);
1837 static void yukon_mac_intr(struct skge_hw *hw, int port)
1839 struct net_device *dev = hw->dev[port];
1840 struct skge_port *skge = netdev_priv(dev);
1841 u8 status = skge_read8(hw, SK_REG(port, GMAC_IRQ_SRC));
1843 if (netif_msg_intr(skge))
1844 printk(KERN_DEBUG PFX "%s: mac interrupt status 0x%x\n",
1847 if (status & GM_IS_RX_FF_OR) {
1848 ++skge->net_stats.rx_fifo_errors;
1849 skge_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_CLI_RX_FO);
1852 if (status & GM_IS_TX_FF_UR) {
1853 ++skge->net_stats.tx_fifo_errors;
1854 skge_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_CLI_TX_FU);
1859 static u16 yukon_speed(const struct skge_hw *hw, u16 aux)
1861 switch (aux & PHY_M_PS_SPEED_MSK) {
1862 case PHY_M_PS_SPEED_1000:
1864 case PHY_M_PS_SPEED_100:
1871 static void yukon_link_up(struct skge_port *skge)
1873 struct skge_hw *hw = skge->hw;
1874 int port = skge->port;
1877 pr_debug("yukon_link_up\n");
1879 /* Enable Transmit FIFO Underrun */
1880 skge_write8(hw, GMAC_IRQ_MSK, GMAC_DEF_MSK);
1882 reg = gma_read16(hw, port, GM_GP_CTRL);
1883 if (skge->duplex == DUPLEX_FULL || skge->autoneg == AUTONEG_ENABLE)
1884 reg |= GM_GPCR_DUP_FULL;
1887 reg |= GM_GPCR_RX_ENA | GM_GPCR_TX_ENA;
1888 gma_write16(hw, port, GM_GP_CTRL, reg);
1890 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_IS_DEF_MSK);
1894 static void yukon_link_down(struct skge_port *skge)
1896 struct skge_hw *hw = skge->hw;
1897 int port = skge->port;
1900 pr_debug("yukon_link_down\n");
1901 gm_phy_write(hw, port, PHY_MARV_INT_MASK, 0);
1903 ctrl = gma_read16(hw, port, GM_GP_CTRL);
1904 ctrl &= ~(GM_GPCR_RX_ENA | GM_GPCR_TX_ENA);
1905 gma_write16(hw, port, GM_GP_CTRL, ctrl);
1907 if (skge->flow_control == FLOW_MODE_REM_SEND) {
1908 /* restore Asymmetric Pause bit */
1909 gm_phy_write(hw, port, PHY_MARV_AUNE_ADV,
1910 gm_phy_read(hw, port,
1916 yukon_reset(hw, port);
1917 skge_link_down(skge);
1919 yukon_init(hw, port);
1922 static void yukon_phy_intr(struct skge_port *skge)
1924 struct skge_hw *hw = skge->hw;
1925 int port = skge->port;
1926 const char *reason = NULL;
1927 u16 istatus, phystat;
1929 istatus = gm_phy_read(hw, port, PHY_MARV_INT_STAT);
1930 phystat = gm_phy_read(hw, port, PHY_MARV_PHY_STAT);
1932 if (netif_msg_intr(skge))
1933 printk(KERN_DEBUG PFX "%s: phy interrupt status 0x%x 0x%x\n",
1934 skge->netdev->name, istatus, phystat);
1936 if (istatus & PHY_M_IS_AN_COMPL) {
1937 if (gm_phy_read(hw, port, PHY_MARV_AUNE_LP)
1939 reason = "remote fault";
1943 if (gm_phy_read(hw, port, PHY_MARV_1000T_STAT) & PHY_B_1000S_MSF) {
1944 reason = "master/slave fault";
1948 if (!(phystat & PHY_M_PS_SPDUP_RES)) {
1949 reason = "speed/duplex";
1953 skge->duplex = (phystat & PHY_M_PS_FULL_DUP)
1954 ? DUPLEX_FULL : DUPLEX_HALF;
1955 skge->speed = yukon_speed(hw, phystat);
1957 /* We are using IEEE 802.3z/D5.0 Table 37-4 */
1958 switch (phystat & PHY_M_PS_PAUSE_MSK) {
1959 case PHY_M_PS_PAUSE_MSK:
1960 skge->flow_control = FLOW_MODE_SYMMETRIC;
1962 case PHY_M_PS_RX_P_EN:
1963 skge->flow_control = FLOW_MODE_REM_SEND;
1965 case PHY_M_PS_TX_P_EN:
1966 skge->flow_control = FLOW_MODE_LOC_SEND;
1969 skge->flow_control = FLOW_MODE_NONE;
1972 if (skge->flow_control == FLOW_MODE_NONE ||
1973 (skge->speed < SPEED_1000 && skge->duplex == DUPLEX_HALF))
1974 skge_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
1976 skge_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON);
1977 yukon_link_up(skge);
1981 if (istatus & PHY_M_IS_LSP_CHANGE)
1982 skge->speed = yukon_speed(hw, phystat);
1984 if (istatus & PHY_M_IS_DUP_CHANGE)
1985 skge->duplex = (phystat & PHY_M_PS_FULL_DUP) ? DUPLEX_FULL : DUPLEX_HALF;
1986 if (istatus & PHY_M_IS_LST_CHANGE) {
1987 if (phystat & PHY_M_PS_LINK_UP)
1988 yukon_link_up(skge);
1990 yukon_link_down(skge);
1994 printk(KERN_ERR PFX "%s: autonegotiation failed (%s)\n",
1995 skge->netdev->name, reason);
1997 /* XXX restart autonegotiation? */
2000 static void skge_ramset(struct skge_hw *hw, u16 q, u32 start, size_t len)
2006 end = start + len - 1;
2008 skge_write8(hw, RB_ADDR(q, RB_CTRL), RB_RST_CLR);
2009 skge_write32(hw, RB_ADDR(q, RB_START), start);
2010 skge_write32(hw, RB_ADDR(q, RB_WP), start);
2011 skge_write32(hw, RB_ADDR(q, RB_RP), start);
2012 skge_write32(hw, RB_ADDR(q, RB_END), end);
2014 if (q == Q_R1 || q == Q_R2) {
2015 /* Set thresholds on receive queue's */
2016 skge_write32(hw, RB_ADDR(q, RB_RX_UTPP),
2018 skge_write32(hw, RB_ADDR(q, RB_RX_LTPP),
2021 /* Enable store & forward on Tx queue's because
2022 * Tx FIFO is only 4K on Genesis and 1K on Yukon
2024 skge_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_STFWD);
2027 skge_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_OP_MD);
2030 /* Setup Bus Memory Interface */
2031 static void skge_qset(struct skge_port *skge, u16 q,
2032 const struct skge_element *e)
2034 struct skge_hw *hw = skge->hw;
2035 u32 watermark = 0x600;
2036 u64 base = skge->dma + (e->desc - skge->mem);
2038 /* optimization to reduce window on 32bit/33mhz */
2039 if ((skge_read16(hw, B0_CTST) & (CS_BUS_CLOCK | CS_BUS_SLOT_SZ)) == 0)
2042 skge_write32(hw, Q_ADDR(q, Q_CSR), CSR_CLR_RESET);
2043 skge_write32(hw, Q_ADDR(q, Q_F), watermark);
2044 skge_write32(hw, Q_ADDR(q, Q_DA_H), (u32)(base >> 32));
2045 skge_write32(hw, Q_ADDR(q, Q_DA_L), (u32)base);
2048 static int skge_up(struct net_device *dev)
2050 struct skge_port *skge = netdev_priv(dev);
2051 struct skge_hw *hw = skge->hw;
2052 int port = skge->port;
2053 u32 chunk, ram_addr;
2054 size_t rx_size, tx_size;
2057 if (netif_msg_ifup(skge))
2058 printk(KERN_INFO PFX "%s: enabling interface\n", dev->name);
2060 if (dev->mtu > RX_BUF_SIZE)
2061 skge->rx_buf_size = dev->mtu + ETH_HLEN + NET_IP_ALIGN;
2063 skge->rx_buf_size = RX_BUF_SIZE;
2066 rx_size = skge->rx_ring.count * sizeof(struct skge_rx_desc);
2067 tx_size = skge->tx_ring.count * sizeof(struct skge_tx_desc);
2068 skge->mem_size = tx_size + rx_size;
2069 skge->mem = pci_alloc_consistent(hw->pdev, skge->mem_size, &skge->dma);
2073 memset(skge->mem, 0, skge->mem_size);
2075 if ((err = skge_ring_alloc(&skge->rx_ring, skge->mem, skge->dma)))
2078 err = skge_rx_fill(skge);
2082 if ((err = skge_ring_alloc(&skge->tx_ring, skge->mem + rx_size,
2083 skge->dma + rx_size)))
2086 skge->tx_avail = skge->tx_ring.count - 1;
2088 /* Enable IRQ from port */
2089 hw->intr_mask |= portirqmask[port];
2090 skge_write32(hw, B0_IMSK, hw->intr_mask);
2093 spin_lock_bh(&hw->phy_lock);
2094 if (hw->chip_id == CHIP_ID_GENESIS)
2095 genesis_mac_init(hw, port);
2097 yukon_mac_init(hw, port);
2098 spin_unlock_bh(&hw->phy_lock);
2100 /* Configure RAMbuffers */
2101 chunk = hw->ram_size / ((hw->ports + 1)*2);
2102 ram_addr = hw->ram_offset + 2 * chunk * port;
2104 skge_ramset(hw, rxqaddr[port], ram_addr, chunk);
2105 skge_qset(skge, rxqaddr[port], skge->rx_ring.to_clean);
2107 BUG_ON(skge->tx_ring.to_use != skge->tx_ring.to_clean);
2108 skge_ramset(hw, txqaddr[port], ram_addr+chunk, chunk);
2109 skge_qset(skge, txqaddr[port], skge->tx_ring.to_use);
2111 /* Start receiver BMU */
2113 skge_write8(hw, Q_ADDR(rxqaddr[port], Q_CSR), CSR_START | CSR_IRQ_CL_F);
2114 skge_led(skge, LED_MODE_ON);
2116 pr_debug("skge_up completed\n");
2120 skge_rx_clean(skge);
2121 kfree(skge->rx_ring.start);
2123 pci_free_consistent(hw->pdev, skge->mem_size, skge->mem, skge->dma);
2128 static int skge_down(struct net_device *dev)
2130 struct skge_port *skge = netdev_priv(dev);
2131 struct skge_hw *hw = skge->hw;
2132 int port = skge->port;
2134 if (netif_msg_ifdown(skge))
2135 printk(KERN_INFO PFX "%s: disabling interface\n", dev->name);
2137 netif_stop_queue(dev);
2139 /* Stop transmitter */
2140 skge_write8(hw, Q_ADDR(txqaddr[port], Q_CSR), CSR_STOP);
2141 skge_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL),
2142 RB_RST_SET|RB_DIS_OP_MD);
2144 if (hw->chip_id == CHIP_ID_GENESIS)
2149 /* Disable Force Sync bit and Enable Alloc bit */
2150 skge_write8(hw, SK_REG(port, TXA_CTRL),
2151 TXA_DIS_FSYNC | TXA_DIS_ALLOC | TXA_STOP_RC);
2153 /* Stop Interval Timer and Limit Counter of Tx Arbiter */
2154 skge_write32(hw, SK_REG(port, TXA_ITI_INI), 0L);
2155 skge_write32(hw, SK_REG(port, TXA_LIM_INI), 0L);
2157 /* Reset PCI FIFO */
2158 skge_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), CSR_SET_RESET);
2159 skge_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL), RB_RST_SET);
2161 /* Reset the RAM Buffer async Tx queue */
2162 skge_write8(hw, RB_ADDR(port == 0 ? Q_XA1 : Q_XA2, RB_CTRL), RB_RST_SET);
2164 skge_write8(hw, Q_ADDR(rxqaddr[port], Q_CSR), CSR_STOP);
2165 skge_write32(hw, RB_ADDR(port ? Q_R2 : Q_R1, RB_CTRL),
2166 RB_RST_SET|RB_DIS_OP_MD);
2167 skge_write32(hw, Q_ADDR(rxqaddr[port], Q_CSR), CSR_SET_RESET);
2169 if (hw->chip_id == CHIP_ID_GENESIS) {
2170 skge_write8(hw, SK_REG(port, TX_MFF_CTRL2), MFF_RST_SET);
2171 skge_write8(hw, SK_REG(port, RX_MFF_CTRL2), MFF_RST_SET);
2173 skge_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_SET);
2174 skge_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_SET);
2177 skge_led(skge, LED_MODE_OFF);
2179 skge_tx_clean(skge);
2180 skge_rx_clean(skge);
2182 kfree(skge->rx_ring.start);
2183 kfree(skge->tx_ring.start);
2184 pci_free_consistent(hw->pdev, skge->mem_size, skge->mem, skge->dma);
2188 static int skge_xmit_frame(struct sk_buff *skb, struct net_device *dev)
2190 struct skge_port *skge = netdev_priv(dev);
2191 struct skge_hw *hw = skge->hw;
2192 struct skge_ring *ring = &skge->tx_ring;
2193 struct skge_element *e;
2194 struct skge_tx_desc *td;
2198 unsigned long flags;
2200 skb = skb_padto(skb, ETH_ZLEN);
2202 return NETDEV_TX_OK;
2204 local_irq_save(flags);
2205 if (!spin_trylock(&skge->tx_lock)) {
2206 /* Collision - tell upper layer to requeue */
2207 local_irq_restore(flags);
2208 return NETDEV_TX_LOCKED;
2211 if (unlikely(skge->tx_avail < skb_shinfo(skb)->nr_frags +1)) {
2212 netif_stop_queue(dev);
2213 spin_unlock_irqrestore(&skge->tx_lock, flags);
2215 printk(KERN_WARNING PFX "%s: ring full when queue awake!\n",
2217 return NETDEV_TX_BUSY;
2223 len = skb_headlen(skb);
2224 map = pci_map_single(hw->pdev, skb->data, len, PCI_DMA_TODEVICE);
2225 pci_unmap_addr_set(e, mapaddr, map);
2226 pci_unmap_len_set(e, maplen, len);
2229 td->dma_hi = map >> 32;
2231 if (skb->ip_summed == CHECKSUM_HW) {
2232 const struct iphdr *ip
2233 = (const struct iphdr *) (skb->data + ETH_HLEN);
2234 int offset = skb->h.raw - skb->data;
2236 /* This seems backwards, but it is what the sk98lin
2237 * does. Looks like hardware is wrong?
2239 if (ip->protocol == IPPROTO_UDP
2240 && hw->chip_rev == 0 && hw->chip_id == CHIP_ID_YUKON)
2241 control = BMU_TCP_CHECK;
2243 control = BMU_UDP_CHECK;
2246 td->csum_start = offset;
2247 td->csum_write = offset + skb->csum;
2249 control = BMU_CHECK;
2251 if (!skb_shinfo(skb)->nr_frags) /* single buffer i.e. no fragments */
2252 control |= BMU_EOF| BMU_IRQ_EOF;
2254 struct skge_tx_desc *tf = td;
2256 control |= BMU_STFWD;
2257 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
2258 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
2260 map = pci_map_page(hw->pdev, frag->page, frag->page_offset,
2261 frag->size, PCI_DMA_TODEVICE);
2267 tf->dma_hi = (u64) map >> 32;
2268 pci_unmap_addr_set(e, mapaddr, map);
2269 pci_unmap_len_set(e, maplen, frag->size);
2271 tf->control = BMU_OWN | BMU_SW | control | frag->size;
2273 tf->control |= BMU_EOF | BMU_IRQ_EOF;
2275 /* Make sure all the descriptors written */
2277 td->control = BMU_OWN | BMU_SW | BMU_STF | control | len;
2280 skge_write8(hw, Q_ADDR(txqaddr[skge->port], Q_CSR), CSR_START);
2282 if (netif_msg_tx_queued(skge))
2283 printk(KERN_DEBUG "%s: tx queued, slot %td, len %d\n",
2284 dev->name, e - ring->start, skb->len);
2286 ring->to_use = e->next;
2287 skge->tx_avail -= skb_shinfo(skb)->nr_frags + 1;
2288 if (skge->tx_avail <= MAX_SKB_FRAGS + 1) {
2289 pr_debug("%s: transmit queue full\n", dev->name);
2290 netif_stop_queue(dev);
2293 dev->trans_start = jiffies;
2294 spin_unlock_irqrestore(&skge->tx_lock, flags);
2296 return NETDEV_TX_OK;
2299 static inline void skge_tx_free(struct skge_hw *hw, struct skge_element *e)
2301 /* This ring element can be skb or fragment */
2303 pci_unmap_single(hw->pdev,
2304 pci_unmap_addr(e, mapaddr),
2305 pci_unmap_len(e, maplen),
2307 dev_kfree_skb_any(e->skb);
2310 pci_unmap_page(hw->pdev,
2311 pci_unmap_addr(e, mapaddr),
2312 pci_unmap_len(e, maplen),
2317 static void skge_tx_clean(struct skge_port *skge)
2319 struct skge_ring *ring = &skge->tx_ring;
2320 struct skge_element *e;
2321 unsigned long flags;
2323 spin_lock_irqsave(&skge->tx_lock, flags);
2324 for (e = ring->to_clean; e != ring->to_use; e = e->next) {
2326 skge_tx_free(skge->hw, e);
2329 spin_unlock_irqrestore(&skge->tx_lock, flags);
2332 static void skge_tx_timeout(struct net_device *dev)
2334 struct skge_port *skge = netdev_priv(dev);
2336 if (netif_msg_timer(skge))
2337 printk(KERN_DEBUG PFX "%s: tx timeout\n", dev->name);
2339 skge_write8(skge->hw, Q_ADDR(txqaddr[skge->port], Q_CSR), CSR_STOP);
2340 skge_tx_clean(skge);
2343 static int skge_change_mtu(struct net_device *dev, int new_mtu)
2346 int running = netif_running(dev);
2348 if (new_mtu < ETH_ZLEN || new_mtu > ETH_JUMBO_MTU)
2361 static void genesis_set_multicast(struct net_device *dev)
2363 struct skge_port *skge = netdev_priv(dev);
2364 struct skge_hw *hw = skge->hw;
2365 int port = skge->port;
2366 int i, count = dev->mc_count;
2367 struct dev_mc_list *list = dev->mc_list;
2371 pr_debug("genesis_set_multicast flags=%x count=%d\n", dev->flags, dev->mc_count);
2373 mode = xm_read32(hw, port, XM_MODE);
2374 mode |= XM_MD_ENA_HASH;
2375 if (dev->flags & IFF_PROMISC)
2376 mode |= XM_MD_ENA_PROM;
2378 mode &= ~XM_MD_ENA_PROM;
2380 if (dev->flags & IFF_ALLMULTI)
2381 memset(filter, 0xff, sizeof(filter));
2383 memset(filter, 0, sizeof(filter));
2384 for (i = 0; list && i < count; i++, list = list->next) {
2386 crc = ether_crc_le(ETH_ALEN, list->dmi_addr);
2388 filter[bit/8] |= 1 << (bit%8);
2392 xm_write32(hw, port, XM_MODE, mode);
2393 xm_outhash(hw, port, XM_HSM, filter);
2396 static void yukon_set_multicast(struct net_device *dev)
2398 struct skge_port *skge = netdev_priv(dev);
2399 struct skge_hw *hw = skge->hw;
2400 int port = skge->port;
2401 struct dev_mc_list *list = dev->mc_list;
2405 memset(filter, 0, sizeof(filter));
2407 reg = gma_read16(hw, port, GM_RX_CTRL);
2408 reg |= GM_RXCR_UCF_ENA;
2410 if (dev->flags & IFF_PROMISC) /* promiscious */
2411 reg &= ~(GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA);
2412 else if (dev->flags & IFF_ALLMULTI) /* all multicast */
2413 memset(filter, 0xff, sizeof(filter));
2414 else if (dev->mc_count == 0) /* no multicast */
2415 reg &= ~GM_RXCR_MCF_ENA;
2418 reg |= GM_RXCR_MCF_ENA;
2420 for (i = 0; list && i < dev->mc_count; i++, list = list->next) {
2421 u32 bit = ether_crc(ETH_ALEN, list->dmi_addr) & 0x3f;
2422 filter[bit/8] |= 1 << (bit%8);
2427 gma_write16(hw, port, GM_MC_ADDR_H1,
2428 (u16)filter[0] | ((u16)filter[1] << 8));
2429 gma_write16(hw, port, GM_MC_ADDR_H2,
2430 (u16)filter[2] | ((u16)filter[3] << 8));
2431 gma_write16(hw, port, GM_MC_ADDR_H3,
2432 (u16)filter[4] | ((u16)filter[5] << 8));
2433 gma_write16(hw, port, GM_MC_ADDR_H4,
2434 (u16)filter[6] | ((u16)filter[7] << 8));
2436 gma_write16(hw, port, GM_RX_CTRL, reg);
2439 static inline int bad_phy_status(const struct skge_hw *hw, u32 status)
2441 if (hw->chip_id == CHIP_ID_GENESIS)
2442 return (status & (XMR_FS_ERR | XMR_FS_2L_VLAN)) != 0;
2444 return (status & GMR_FS_ANY_ERR) ||
2445 (status & GMR_FS_RX_OK) == 0;
2448 static void skge_rx_error(struct skge_port *skge, int slot,
2449 u32 control, u32 status)
2451 if (netif_msg_rx_err(skge))
2452 printk(KERN_DEBUG PFX "%s: rx err, slot %d control 0x%x status 0x%x\n",
2453 skge->netdev->name, slot, control, status);
2455 if ((control & (BMU_EOF|BMU_STF)) != (BMU_STF|BMU_EOF))
2456 skge->net_stats.rx_length_errors++;
2457 else if (skge->hw->chip_id == CHIP_ID_GENESIS) {
2458 if (status & (XMR_FS_RUNT|XMR_FS_LNG_ERR))
2459 skge->net_stats.rx_length_errors++;
2460 if (status & XMR_FS_FRA_ERR)
2461 skge->net_stats.rx_frame_errors++;
2462 if (status & XMR_FS_FCS_ERR)
2463 skge->net_stats.rx_crc_errors++;
2465 if (status & (GMR_FS_LONG_ERR|GMR_FS_UN_SIZE))
2466 skge->net_stats.rx_length_errors++;
2467 if (status & GMR_FS_FRAGMENT)
2468 skge->net_stats.rx_frame_errors++;
2469 if (status & GMR_FS_CRC_ERR)
2470 skge->net_stats.rx_crc_errors++;
2474 /* Get receive buffer from descriptor.
2475 * Handles copy of small buffers and reallocation failures
2477 static inline struct sk_buff *skge_rx_get(struct skge_port *skge,
2478 struct skge_element *e,
2481 struct sk_buff *nskb, *skb;
2483 if (len < RX_COPY_THRESHOLD) {
2484 nskb = skge_rx_alloc(skge->netdev, len + NET_IP_ALIGN);
2485 if (unlikely(!nskb))
2488 pci_dma_sync_single_for_cpu(skge->hw->pdev,
2489 pci_unmap_addr(e, mapaddr),
2490 len, PCI_DMA_FROMDEVICE);
2491 memcpy(nskb->data, e->skb->data, len);
2492 pci_dma_sync_single_for_device(skge->hw->pdev,
2493 pci_unmap_addr(e, mapaddr),
2494 len, PCI_DMA_FROMDEVICE);
2496 if (skge->rx_csum) {
2497 struct skge_rx_desc *rd = e->desc;
2498 nskb->csum = le16_to_cpu(rd->csum2);
2499 nskb->ip_summed = CHECKSUM_HW;
2501 skge_rx_reuse(e, skge->rx_buf_size);
2504 nskb = skge_rx_alloc(skge->netdev, skge->rx_buf_size);
2505 if (unlikely(!nskb))
2508 pci_unmap_single(skge->hw->pdev,
2509 pci_unmap_addr(e, mapaddr),
2510 pci_unmap_len(e, maplen),
2511 PCI_DMA_FROMDEVICE);
2513 if (skge->rx_csum) {
2514 struct skge_rx_desc *rd = e->desc;
2515 skb->csum = le16_to_cpu(rd->csum2);
2516 skb->ip_summed = CHECKSUM_HW;
2519 skge_rx_setup(skge, e, nskb, skge->rx_buf_size);
2525 static int skge_poll(struct net_device *dev, int *budget)
2527 struct skge_port *skge = netdev_priv(dev);
2528 struct skge_hw *hw = skge->hw;
2529 struct skge_ring *ring = &skge->rx_ring;
2530 struct skge_element *e;
2531 unsigned int to_do = min(dev->quota, *budget);
2532 unsigned int work_done = 0;
2534 pr_debug("skge_poll\n");
2536 for (e = ring->to_clean; work_done < to_do; e = e->next) {
2537 struct skge_rx_desc *rd = e->desc;
2538 struct sk_buff *skb;
2539 u32 control, len, status;
2542 control = rd->control;
2543 if (control & BMU_OWN)
2546 len = control & BMU_BBC;
2547 status = rd->status;
2549 if (unlikely((control & (BMU_EOF|BMU_STF)) != (BMU_STF|BMU_EOF)
2550 || bad_phy_status(hw, status))) {
2551 skge_rx_error(skge, e - ring->start, control, status);
2552 skge_rx_reuse(e, skge->rx_buf_size);
2556 if (netif_msg_rx_status(skge))
2557 printk(KERN_DEBUG PFX "%s: rx slot %td status 0x%x len %d\n",
2558 dev->name, e - ring->start, rd->status, len);
2560 skb = skge_rx_get(skge, e, len);
2563 skb->protocol = eth_type_trans(skb, dev);
2565 dev->last_rx = jiffies;
2566 netif_receive_skb(skb);
2570 skge_rx_reuse(e, skge->rx_buf_size);
2574 /* restart receiver */
2576 skge_write8(hw, Q_ADDR(rxqaddr[skge->port], Q_CSR),
2577 CSR_START | CSR_IRQ_CL_F);
2579 *budget -= work_done;
2580 dev->quota -= work_done;
2582 if (work_done >= to_do)
2583 return 1; /* not done */
2585 local_irq_disable();
2586 __netif_rx_complete(dev);
2587 hw->intr_mask |= portirqmask[skge->port];
2588 skge_write32(hw, B0_IMSK, hw->intr_mask);
2593 static inline void skge_tx_intr(struct net_device *dev)
2595 struct skge_port *skge = netdev_priv(dev);
2596 struct skge_hw *hw = skge->hw;
2597 struct skge_ring *ring = &skge->tx_ring;
2598 struct skge_element *e;
2600 spin_lock(&skge->tx_lock);
2601 for (e = ring->to_clean; e != ring->to_use; e = e->next) {
2602 struct skge_tx_desc *td = e->desc;
2606 control = td->control;
2607 if (control & BMU_OWN)
2610 if (unlikely(netif_msg_tx_done(skge)))
2611 printk(KERN_DEBUG PFX "%s: tx done slot %td status 0x%x\n",
2612 dev->name, e - ring->start, td->status);
2614 skge_tx_free(hw, e);
2619 skge_write8(hw, Q_ADDR(txqaddr[skge->port], Q_CSR), CSR_IRQ_CL_F);
2621 if (skge->tx_avail > MAX_SKB_FRAGS + 1)
2622 netif_wake_queue(dev);
2624 spin_unlock(&skge->tx_lock);
2627 /* Parity errors seem to happen when Genesis is connected to a switch
2628 * with no other ports present. Heartbeat error??
2630 static void skge_mac_parity(struct skge_hw *hw, int port)
2632 struct net_device *dev = hw->dev[port];
2635 struct skge_port *skge = netdev_priv(dev);
2636 ++skge->net_stats.tx_heartbeat_errors;
2639 if (hw->chip_id == CHIP_ID_GENESIS)
2640 skge_write16(hw, SK_REG(port, TX_MFF_CTRL1),
2643 /* HW-Bug #8: cleared by GMF_CLI_TX_FC instead of GMF_CLI_TX_PE */
2644 skge_write8(hw, SK_REG(port, TX_GMF_CTRL_T),
2645 (hw->chip_id == CHIP_ID_YUKON && hw->chip_rev == 0)
2646 ? GMF_CLI_TX_FC : GMF_CLI_TX_PE);
2649 static void skge_pci_clear(struct skge_hw *hw)
2653 pci_read_config_word(hw->pdev, PCI_STATUS, &status);
2654 skge_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
2655 pci_write_config_word(hw->pdev, PCI_STATUS,
2656 status | PCI_STATUS_ERROR_BITS);
2657 skge_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
2660 static void skge_mac_intr(struct skge_hw *hw, int port)
2662 if (hw->chip_id == CHIP_ID_GENESIS)
2663 genesis_mac_intr(hw, port);
2665 yukon_mac_intr(hw, port);
2668 /* Handle device specific framing and timeout interrupts */
2669 static void skge_error_irq(struct skge_hw *hw)
2671 u32 hwstatus = skge_read32(hw, B0_HWE_ISRC);
2673 if (hw->chip_id == CHIP_ID_GENESIS) {
2674 /* clear xmac errors */
2675 if (hwstatus & (IS_NO_STAT_M1|IS_NO_TIST_M1))
2676 skge_write16(hw, SK_REG(0, RX_MFF_CTRL1), MFF_CLR_INSTAT);
2677 if (hwstatus & (IS_NO_STAT_M2|IS_NO_TIST_M2))
2678 skge_write16(hw, SK_REG(0, RX_MFF_CTRL2), MFF_CLR_INSTAT);
2680 /* Timestamp (unused) overflow */
2681 if (hwstatus & IS_IRQ_TIST_OV)
2682 skge_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ);
2685 if (hwstatus & IS_RAM_RD_PAR) {
2686 printk(KERN_ERR PFX "Ram read data parity error\n");
2687 skge_write16(hw, B3_RI_CTRL, RI_CLR_RD_PERR);
2690 if (hwstatus & IS_RAM_WR_PAR) {
2691 printk(KERN_ERR PFX "Ram write data parity error\n");
2692 skge_write16(hw, B3_RI_CTRL, RI_CLR_WR_PERR);
2695 if (hwstatus & IS_M1_PAR_ERR)
2696 skge_mac_parity(hw, 0);
2698 if (hwstatus & IS_M2_PAR_ERR)
2699 skge_mac_parity(hw, 1);
2701 if (hwstatus & IS_R1_PAR_ERR)
2702 skge_write32(hw, B0_R1_CSR, CSR_IRQ_CL_P);
2704 if (hwstatus & IS_R2_PAR_ERR)
2705 skge_write32(hw, B0_R2_CSR, CSR_IRQ_CL_P);
2707 if (hwstatus & (IS_IRQ_MST_ERR|IS_IRQ_STAT)) {
2708 printk(KERN_ERR PFX "hardware error detected (status 0x%x)\n",
2713 /* if error still set then just ignore it */
2714 hwstatus = skge_read32(hw, B0_HWE_ISRC);
2715 if (hwstatus & IS_IRQ_STAT) {
2716 pr_debug("IRQ status %x: still set ignoring hardware errors\n",
2718 hw->intr_mask &= ~IS_HW_ERR;
2724 * Interrrupt from PHY are handled in tasklet (soft irq)
2725 * because accessing phy registers requires spin wait which might
2726 * cause excess interrupt latency.
2728 static void skge_extirq(unsigned long data)
2730 struct skge_hw *hw = (struct skge_hw *) data;
2733 spin_lock(&hw->phy_lock);
2734 for (port = 0; port < 2; port++) {
2735 struct net_device *dev = hw->dev[port];
2737 if (dev && netif_running(dev)) {
2738 struct skge_port *skge = netdev_priv(dev);
2740 if (hw->chip_id != CHIP_ID_GENESIS)
2741 yukon_phy_intr(skge);
2743 bcom_phy_intr(skge);
2746 spin_unlock(&hw->phy_lock);
2748 local_irq_disable();
2749 hw->intr_mask |= IS_EXT_REG;
2750 skge_write32(hw, B0_IMSK, hw->intr_mask);
2754 static irqreturn_t skge_intr(int irq, void *dev_id, struct pt_regs *regs)
2756 struct skge_hw *hw = dev_id;
2757 u32 status = skge_read32(hw, B0_SP_ISRC);
2759 if (status == 0 || status == ~0) /* hotplug or shared irq */
2762 status &= hw->intr_mask;
2763 if (status & IS_R1_F) {
2764 hw->intr_mask &= ~IS_R1_F;
2765 netif_rx_schedule(hw->dev[0]);
2768 if (status & IS_R2_F) {
2769 hw->intr_mask &= ~IS_R2_F;
2770 netif_rx_schedule(hw->dev[1]);
2773 if (status & IS_XA1_F)
2774 skge_tx_intr(hw->dev[0]);
2776 if (status & IS_XA2_F)
2777 skge_tx_intr(hw->dev[1]);
2779 if (status & IS_PA_TO_RX1) {
2780 struct skge_port *skge = netdev_priv(hw->dev[0]);
2781 ++skge->net_stats.rx_over_errors;
2782 skge_write16(hw, B3_PA_CTRL, PA_CLR_TO_RX1);
2785 if (status & IS_PA_TO_RX2) {
2786 struct skge_port *skge = netdev_priv(hw->dev[1]);
2787 ++skge->net_stats.rx_over_errors;
2788 skge_write16(hw, B3_PA_CTRL, PA_CLR_TO_RX2);
2791 if (status & IS_PA_TO_TX1)
2792 skge_write16(hw, B3_PA_CTRL, PA_CLR_TO_TX1);
2794 if (status & IS_PA_TO_TX2)
2795 skge_write16(hw, B3_PA_CTRL, PA_CLR_TO_TX2);
2797 if (status & IS_MAC1)
2798 skge_mac_intr(hw, 0);
2800 if (status & IS_MAC2)
2801 skge_mac_intr(hw, 1);
2803 if (status & IS_HW_ERR)
2806 if (status & IS_EXT_REG) {
2807 hw->intr_mask &= ~IS_EXT_REG;
2808 tasklet_schedule(&hw->ext_tasklet);
2811 skge_write32(hw, B0_IMSK, hw->intr_mask);
2816 #ifdef CONFIG_NET_POLL_CONTROLLER
2817 static void skge_netpoll(struct net_device *dev)
2819 struct skge_port *skge = netdev_priv(dev);
2821 disable_irq(dev->irq);
2822 skge_intr(dev->irq, skge->hw, NULL);
2823 enable_irq(dev->irq);
2827 static int skge_set_mac_address(struct net_device *dev, void *p)
2829 struct skge_port *skge = netdev_priv(dev);
2830 struct sockaddr *addr = p;
2833 if (!is_valid_ether_addr(addr->sa_data))
2834 return -EADDRNOTAVAIL;
2837 memcpy(dev->dev_addr, addr->sa_data, ETH_ALEN);
2838 memcpy_toio(skge->hw->regs + B2_MAC_1 + skge->port*8,
2839 dev->dev_addr, ETH_ALEN);
2840 memcpy_toio(skge->hw->regs + B2_MAC_2 + skge->port*8,
2841 dev->dev_addr, ETH_ALEN);
2842 if (dev->flags & IFF_UP)
2847 static const struct {
2851 { CHIP_ID_GENESIS, "Genesis" },
2852 { CHIP_ID_YUKON, "Yukon" },
2853 { CHIP_ID_YUKON_LITE, "Yukon-Lite"},
2854 { CHIP_ID_YUKON_LP, "Yukon-LP"},
2857 static const char *skge_board_name(const struct skge_hw *hw)
2860 static char buf[16];
2862 for (i = 0; i < ARRAY_SIZE(skge_chips); i++)
2863 if (skge_chips[i].id == hw->chip_id)
2864 return skge_chips[i].name;
2866 snprintf(buf, sizeof buf, "chipid 0x%x", hw->chip_id);
2872 * Setup the board data structure, but don't bring up
2875 static int skge_reset(struct skge_hw *hw)
2878 u8 t8, mac_cfg, pmd_type, phy_type;
2881 ctst = skge_read16(hw, B0_CTST);
2884 skge_write8(hw, B0_CTST, CS_RST_SET);
2885 skge_write8(hw, B0_CTST, CS_RST_CLR);
2887 /* clear PCI errors, if any */
2890 skge_write8(hw, B0_CTST, CS_MRST_CLR);
2892 /* restore CLK_RUN bits (for Yukon-Lite) */
2893 skge_write16(hw, B0_CTST,
2894 ctst & (CS_CLK_RUN_HOT|CS_CLK_RUN_RST|CS_CLK_RUN_ENA));
2896 hw->chip_id = skge_read8(hw, B2_CHIP_ID);
2897 phy_type = skge_read8(hw, B2_E_1) & 0xf;
2898 pmd_type = skge_read8(hw, B2_PMD_TYP);
2899 hw->copper = (pmd_type == 'T' || pmd_type == '1');
2901 switch (hw->chip_id) {
2902 case CHIP_ID_GENESIS:
2905 hw->phy_addr = PHY_ADDR_BCOM;
2908 printk(KERN_ERR PFX "%s: unsupported phy type 0x%x\n",
2909 pci_name(hw->pdev), phy_type);
2915 case CHIP_ID_YUKON_LITE:
2916 case CHIP_ID_YUKON_LP:
2917 if (phy_type < SK_PHY_MARV_COPPER && pmd_type != 'S')
2920 hw->phy_addr = PHY_ADDR_MARV;
2924 printk(KERN_ERR PFX "%s: unsupported chip type 0x%x\n",
2925 pci_name(hw->pdev), hw->chip_id);
2929 mac_cfg = skge_read8(hw, B2_MAC_CFG);
2930 hw->ports = (mac_cfg & CFG_SNG_MAC) ? 1 : 2;
2931 hw->chip_rev = (mac_cfg & CFG_CHIP_R_MSK) >> 4;
2933 /* read the adapters RAM size */
2934 t8 = skge_read8(hw, B2_E_0);
2935 if (hw->chip_id == CHIP_ID_GENESIS) {
2937 /* special case: 4 x 64k x 36, offset = 0x80000 */
2938 hw->ram_size = 0x100000;
2939 hw->ram_offset = 0x80000;
2941 hw->ram_size = t8 * 512;
2944 hw->ram_size = 0x20000;
2946 hw->ram_size = t8 * 4096;
2948 hw->intr_mask = IS_HW_ERR | IS_EXT_REG;
2949 if (hw->chip_id == CHIP_ID_GENESIS)
2952 /* switch power to VCC (WA for VAUX problem) */
2953 skge_write8(hw, B0_POWER_CTRL,
2954 PC_VAUX_ENA | PC_VCC_ENA | PC_VAUX_OFF | PC_VCC_ON);
2955 /* avoid boards with stuck Hardware error bits */
2956 if ((skge_read32(hw, B0_ISRC) & IS_HW_ERR) &&
2957 (skge_read32(hw, B0_HWE_ISRC) & IS_IRQ_SENSOR)) {
2958 printk(KERN_WARNING PFX "stuck hardware sensor bit\n");
2959 hw->intr_mask &= ~IS_HW_ERR;
2962 for (i = 0; i < hw->ports; i++) {
2963 skge_write16(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_SET);
2964 skge_write16(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_CLR);
2968 /* turn off hardware timer (unused) */
2969 skge_write8(hw, B2_TI_CTRL, TIM_STOP);
2970 skge_write8(hw, B2_TI_CTRL, TIM_CLR_IRQ);
2971 skge_write8(hw, B0_LED, LED_STAT_ON);
2973 /* enable the Tx Arbiters */
2974 for (i = 0; i < hw->ports; i++)
2975 skge_write8(hw, SK_REG(i, TXA_CTRL), TXA_ENA_ARB);
2977 /* Initialize ram interface */
2978 skge_write16(hw, B3_RI_CTRL, RI_RST_CLR);
2980 skge_write8(hw, B3_RI_WTO_R1, SK_RI_TO_53);
2981 skge_write8(hw, B3_RI_WTO_XA1, SK_RI_TO_53);
2982 skge_write8(hw, B3_RI_WTO_XS1, SK_RI_TO_53);
2983 skge_write8(hw, B3_RI_RTO_R1, SK_RI_TO_53);
2984 skge_write8(hw, B3_RI_RTO_XA1, SK_RI_TO_53);
2985 skge_write8(hw, B3_RI_RTO_XS1, SK_RI_TO_53);
2986 skge_write8(hw, B3_RI_WTO_R2, SK_RI_TO_53);
2987 skge_write8(hw, B3_RI_WTO_XA2, SK_RI_TO_53);
2988 skge_write8(hw, B3_RI_WTO_XS2, SK_RI_TO_53);
2989 skge_write8(hw, B3_RI_RTO_R2, SK_RI_TO_53);
2990 skge_write8(hw, B3_RI_RTO_XA2, SK_RI_TO_53);
2991 skge_write8(hw, B3_RI_RTO_XS2, SK_RI_TO_53);
2993 skge_write32(hw, B0_HWE_IMSK, IS_ERR_MSK);
2995 /* Set interrupt moderation for Transmit only
2996 * Receive interrupts avoided by NAPI
2998 skge_write32(hw, B2_IRQM_MSK, IS_XA1_F|IS_XA2_F);
2999 skge_write32(hw, B2_IRQM_INI, skge_usecs2clk(hw, 100));
3000 skge_write32(hw, B2_IRQM_CTRL, TIM_START);
3002 skge_write32(hw, B0_IMSK, hw->intr_mask);
3004 if (hw->chip_id != CHIP_ID_GENESIS)
3005 skge_write8(hw, GMAC_IRQ_MSK, 0);
3007 spin_lock_bh(&hw->phy_lock);
3008 for (i = 0; i < hw->ports; i++) {
3009 if (hw->chip_id == CHIP_ID_GENESIS)
3010 genesis_reset(hw, i);
3014 spin_unlock_bh(&hw->phy_lock);
3019 /* Initialize network device */
3020 static struct net_device *skge_devinit(struct skge_hw *hw, int port,
3023 struct skge_port *skge;
3024 struct net_device *dev = alloc_etherdev(sizeof(*skge));
3027 printk(KERN_ERR "skge etherdev alloc failed");
3031 SET_MODULE_OWNER(dev);
3032 SET_NETDEV_DEV(dev, &hw->pdev->dev);
3033 dev->open = skge_up;
3034 dev->stop = skge_down;
3035 dev->hard_start_xmit = skge_xmit_frame;
3036 dev->get_stats = skge_get_stats;
3037 if (hw->chip_id == CHIP_ID_GENESIS)
3038 dev->set_multicast_list = genesis_set_multicast;
3040 dev->set_multicast_list = yukon_set_multicast;
3042 dev->set_mac_address = skge_set_mac_address;
3043 dev->change_mtu = skge_change_mtu;
3044 SET_ETHTOOL_OPS(dev, &skge_ethtool_ops);
3045 dev->tx_timeout = skge_tx_timeout;
3046 dev->watchdog_timeo = TX_WATCHDOG;
3047 dev->poll = skge_poll;
3048 dev->weight = NAPI_WEIGHT;
3049 #ifdef CONFIG_NET_POLL_CONTROLLER
3050 dev->poll_controller = skge_netpoll;
3052 dev->irq = hw->pdev->irq;
3053 dev->features = NETIF_F_LLTX;
3055 dev->features |= NETIF_F_HIGHDMA;
3057 skge = netdev_priv(dev);
3060 skge->msg_enable = netif_msg_init(debug, default_msg);
3061 skge->tx_ring.count = DEFAULT_TX_RING_SIZE;
3062 skge->rx_ring.count = DEFAULT_RX_RING_SIZE;
3064 /* Auto speed and flow control */
3065 skge->autoneg = AUTONEG_ENABLE;
3066 skge->flow_control = FLOW_MODE_SYMMETRIC;
3069 skge->advertising = skge_supported_modes(hw);
3071 hw->dev[port] = dev;
3075 spin_lock_init(&skge->tx_lock);
3077 if (hw->chip_id != CHIP_ID_GENESIS) {
3078 dev->features |= NETIF_F_IP_CSUM | NETIF_F_SG;
3082 /* read the mac address */
3083 memcpy_fromio(dev->dev_addr, hw->regs + B2_MAC_1 + port*8, ETH_ALEN);
3084 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
3086 /* device is off until link detection */
3087 netif_carrier_off(dev);
3088 netif_stop_queue(dev);
3093 static void __devinit skge_show_addr(struct net_device *dev)
3095 const struct skge_port *skge = netdev_priv(dev);
3097 if (netif_msg_probe(skge))
3098 printk(KERN_INFO PFX "%s: addr %02x:%02x:%02x:%02x:%02x:%02x\n",
3100 dev->dev_addr[0], dev->dev_addr[1], dev->dev_addr[2],
3101 dev->dev_addr[3], dev->dev_addr[4], dev->dev_addr[5]);
3104 static int __devinit skge_probe(struct pci_dev *pdev,
3105 const struct pci_device_id *ent)
3107 struct net_device *dev, *dev1;
3109 int err, using_dac = 0;
3111 if ((err = pci_enable_device(pdev))) {
3112 printk(KERN_ERR PFX "%s cannot enable PCI device\n",
3117 if ((err = pci_request_regions(pdev, DRV_NAME))) {
3118 printk(KERN_ERR PFX "%s cannot obtain PCI resources\n",
3120 goto err_out_disable_pdev;
3123 pci_set_master(pdev);
3125 if (!(err = pci_set_dma_mask(pdev, DMA_64BIT_MASK)))
3127 else if (!(err = pci_set_dma_mask(pdev, DMA_32BIT_MASK))) {
3128 printk(KERN_ERR PFX "%s no usable DMA configuration\n",
3130 goto err_out_free_regions;
3134 /* byte swap decriptors in hardware */
3138 pci_read_config_dword(pdev, PCI_DEV_REG2, ®);
3139 reg |= PCI_REV_DESC;
3140 pci_write_config_dword(pdev, PCI_DEV_REG2, reg);
3145 hw = kmalloc(sizeof(*hw), GFP_KERNEL);
3147 printk(KERN_ERR PFX "%s: cannot allocate hardware struct\n",
3149 goto err_out_free_regions;
3152 memset(hw, 0, sizeof(*hw));
3154 spin_lock_init(&hw->phy_lock);
3155 tasklet_init(&hw->ext_tasklet, skge_extirq, (unsigned long) hw);
3157 hw->regs = ioremap_nocache(pci_resource_start(pdev, 0), 0x4000);
3159 printk(KERN_ERR PFX "%s: cannot map device registers\n",
3161 goto err_out_free_hw;
3164 if ((err = request_irq(pdev->irq, skge_intr, SA_SHIRQ, DRV_NAME, hw))) {
3165 printk(KERN_ERR PFX "%s: cannot assign irq %d\n",
3166 pci_name(pdev), pdev->irq);
3167 goto err_out_iounmap;
3169 pci_set_drvdata(pdev, hw);
3171 err = skge_reset(hw);
3173 goto err_out_free_irq;
3175 printk(KERN_INFO PFX "addr 0x%lx irq %d chip %s rev %d\n",
3176 pci_resource_start(pdev, 0), pdev->irq,
3177 skge_board_name(hw), hw->chip_rev);
3179 if ((dev = skge_devinit(hw, 0, using_dac)) == NULL)
3180 goto err_out_led_off;
3182 if ((err = register_netdev(dev))) {
3183 printk(KERN_ERR PFX "%s: cannot register net device\n",
3185 goto err_out_free_netdev;
3188 skge_show_addr(dev);
3190 if (hw->ports > 1 && (dev1 = skge_devinit(hw, 1, using_dac))) {
3191 if (register_netdev(dev1) == 0)
3192 skge_show_addr(dev1);
3194 /* Failure to register second port need not be fatal */
3195 printk(KERN_WARNING PFX "register of second port failed\n");
3203 err_out_free_netdev:
3206 skge_write16(hw, B0_LED, LED_STAT_OFF);
3208 free_irq(pdev->irq, hw);
3213 err_out_free_regions:
3214 pci_release_regions(pdev);
3215 err_out_disable_pdev:
3216 pci_disable_device(pdev);
3217 pci_set_drvdata(pdev, NULL);
3222 static void __devexit skge_remove(struct pci_dev *pdev)
3224 struct skge_hw *hw = pci_get_drvdata(pdev);
3225 struct net_device *dev0, *dev1;
3230 if ((dev1 = hw->dev[1]))
3231 unregister_netdev(dev1);
3233 unregister_netdev(dev0);
3235 tasklet_kill(&hw->ext_tasklet);
3237 free_irq(pdev->irq, hw);
3238 pci_release_regions(pdev);
3239 pci_disable_device(pdev);
3243 skge_write16(hw, B0_LED, LED_STAT_OFF);
3246 pci_set_drvdata(pdev, NULL);
3250 static int skge_suspend(struct pci_dev *pdev, pm_message_t state)
3252 struct skge_hw *hw = pci_get_drvdata(pdev);
3255 for (i = 0; i < 2; i++) {
3256 struct net_device *dev = hw->dev[i];
3259 struct skge_port *skge = netdev_priv(dev);
3260 if (netif_running(dev)) {
3261 netif_carrier_off(dev);
3264 netif_device_detach(dev);
3269 pci_save_state(pdev);
3270 pci_enable_wake(pdev, pci_choose_state(pdev, state), wol);
3271 pci_disable_device(pdev);
3272 pci_set_power_state(pdev, pci_choose_state(pdev, state));
3277 static int skge_resume(struct pci_dev *pdev)
3279 struct skge_hw *hw = pci_get_drvdata(pdev);
3282 pci_set_power_state(pdev, PCI_D0);
3283 pci_restore_state(pdev);
3284 pci_enable_wake(pdev, PCI_D0, 0);
3288 for (i = 0; i < 2; i++) {
3289 struct net_device *dev = hw->dev[i];
3291 netif_device_attach(dev);
3292 if (netif_running(dev))
3300 static struct pci_driver skge_driver = {
3302 .id_table = skge_id_table,
3303 .probe = skge_probe,
3304 .remove = __devexit_p(skge_remove),
3306 .suspend = skge_suspend,
3307 .resume = skge_resume,
3311 static int __init skge_init_module(void)
3313 return pci_module_init(&skge_driver);
3316 static void __exit skge_cleanup_module(void)
3318 pci_unregister_driver(&skge_driver);
3321 module_init(skge_init_module);
3322 module_exit(skge_cleanup_module);