2 * New driver for Marvell Yukon chipset and SysKonnect Gigabit
3 * Ethernet adapters. Based on earlier sk98lin, e100 and
4 * FreeBSD if_sk drivers.
6 * This driver intentionally does not support all the features
7 * of the original driver such as link fail-over and link management because
8 * those should be done at higher levels.
10 * Copyright (C) 2004, 2005 Stephen Hemminger <shemminger@osdl.org>
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License as published by
14 * the Free Software Foundation; either version 2 of the License.
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
27 #include <linux/kernel.h>
28 #include <linux/module.h>
29 #include <linux/moduleparam.h>
30 #include <linux/netdevice.h>
31 #include <linux/etherdevice.h>
32 #include <linux/ethtool.h>
33 #include <linux/pci.h>
34 #include <linux/if_vlan.h>
36 #include <linux/delay.h>
37 #include <linux/crc32.h>
38 #include <linux/dma-mapping.h>
39 #include <linux/mii.h>
44 #define DRV_NAME "skge"
45 #define DRV_VERSION "1.10"
46 #define PFX DRV_NAME " "
48 #define DEFAULT_TX_RING_SIZE 128
49 #define DEFAULT_RX_RING_SIZE 512
50 #define MAX_TX_RING_SIZE 1024
51 #define TX_LOW_WATER (MAX_SKB_FRAGS + 1)
52 #define MAX_RX_RING_SIZE 4096
53 #define RX_COPY_THRESHOLD 128
54 #define RX_BUF_SIZE 1536
55 #define PHY_RETRIES 1000
56 #define ETH_JUMBO_MTU 9000
57 #define TX_WATCHDOG (5 * HZ)
58 #define NAPI_WEIGHT 64
60 #define LINK_HZ (HZ/2)
62 MODULE_DESCRIPTION("SysKonnect Gigabit Ethernet driver");
63 MODULE_AUTHOR("Stephen Hemminger <shemminger@linux-foundation.org>");
64 MODULE_LICENSE("GPL");
65 MODULE_VERSION(DRV_VERSION);
67 static const u32 default_msg
68 = NETIF_MSG_DRV| NETIF_MSG_PROBE| NETIF_MSG_LINK
69 | NETIF_MSG_IFUP| NETIF_MSG_IFDOWN;
71 static int debug = -1; /* defaults above */
72 module_param(debug, int, 0);
73 MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
75 static const struct pci_device_id skge_id_table[] = {
76 { PCI_DEVICE(PCI_VENDOR_ID_3COM, PCI_DEVICE_ID_3COM_3C940) },
77 { PCI_DEVICE(PCI_VENDOR_ID_3COM, PCI_DEVICE_ID_3COM_3C940B) },
78 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_GE) },
79 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_YU) },
80 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, PCI_DEVICE_ID_DLINK_DGE510T) },
81 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4b01) }, /* DGE-530T */
82 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4320) },
83 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x5005) }, /* Belkin */
84 { PCI_DEVICE(PCI_VENDOR_ID_CNET, PCI_DEVICE_ID_CNET_GIGACARD) },
85 { PCI_DEVICE(PCI_VENDOR_ID_LINKSYS, PCI_DEVICE_ID_LINKSYS_EG1064) },
86 { PCI_VENDOR_ID_LINKSYS, 0x1032, PCI_ANY_ID, 0x0015 },
89 MODULE_DEVICE_TABLE(pci, skge_id_table);
91 static int skge_up(struct net_device *dev);
92 static int skge_down(struct net_device *dev);
93 static void skge_phy_reset(struct skge_port *skge);
94 static void skge_tx_clean(struct net_device *dev);
95 static int xm_phy_write(struct skge_hw *hw, int port, u16 reg, u16 val);
96 static int gm_phy_write(struct skge_hw *hw, int port, u16 reg, u16 val);
97 static void genesis_get_stats(struct skge_port *skge, u64 *data);
98 static void yukon_get_stats(struct skge_port *skge, u64 *data);
99 static void yukon_init(struct skge_hw *hw, int port);
100 static void genesis_mac_init(struct skge_hw *hw, int port);
101 static void genesis_link_up(struct skge_port *skge);
103 /* Avoid conditionals by using array */
104 static const int txqaddr[] = { Q_XA1, Q_XA2 };
105 static const int rxqaddr[] = { Q_R1, Q_R2 };
106 static const u32 rxirqmask[] = { IS_R1_F, IS_R2_F };
107 static const u32 txirqmask[] = { IS_XA1_F, IS_XA2_F };
108 static const u32 napimask[] = { IS_R1_F|IS_XA1_F, IS_R2_F|IS_XA2_F };
109 static const u32 portmask[] = { IS_PORT_1, IS_PORT_2 };
111 static int skge_get_regs_len(struct net_device *dev)
117 * Returns copy of whole control register region
118 * Note: skip RAM address register because accessing it will
121 static void skge_get_regs(struct net_device *dev, struct ethtool_regs *regs,
124 const struct skge_port *skge = netdev_priv(dev);
125 const void __iomem *io = skge->hw->regs;
128 memset(p, 0, regs->len);
129 memcpy_fromio(p, io, B3_RAM_ADDR);
131 memcpy_fromio(p + B3_RI_WTO_R1, io + B3_RI_WTO_R1,
132 regs->len - B3_RI_WTO_R1);
135 /* Wake on Lan only supported on Yukon chips with rev 1 or above */
136 static u32 wol_supported(const struct skge_hw *hw)
138 if (hw->chip_id == CHIP_ID_YUKON && hw->chip_rev != 0)
139 return WAKE_MAGIC | WAKE_PHY;
144 static u32 pci_wake_enabled(struct pci_dev *dev)
146 int pm = pci_find_capability(dev, PCI_CAP_ID_PM);
149 /* If device doesn't support PM Capabilities, but request is to disable
150 * wake events, it's a nop; otherwise fail */
154 pci_read_config_word(dev, pm + PCI_PM_PMC, &value);
156 value &= PCI_PM_CAP_PME_MASK;
157 value >>= ffs(PCI_PM_CAP_PME_MASK) - 1; /* First bit of mask */
162 static void skge_wol_init(struct skge_port *skge)
164 struct skge_hw *hw = skge->hw;
165 int port = skge->port;
166 enum pause_control save_mode;
169 /* Bring hardware out of reset */
170 skge_write16(hw, B0_CTST, CS_RST_CLR);
171 skge_write16(hw, SK_REG(port, GMAC_LINK_CTRL), GMLC_RST_CLR);
173 skge_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_CLR);
174 skge_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_CLR);
176 /* Force to 10/100 skge_reset will re-enable on resume */
177 save_mode = skge->flow_control;
178 skge->flow_control = FLOW_MODE_SYMMETRIC;
180 ctrl = skge->advertising;
181 skge->advertising &= ~(ADVERTISED_1000baseT_Half|ADVERTISED_1000baseT_Full);
183 skge_phy_reset(skge);
185 skge->flow_control = save_mode;
186 skge->advertising = ctrl;
188 /* Set GMAC to no flow control and auto update for speed/duplex */
189 gma_write16(hw, port, GM_GP_CTRL,
190 GM_GPCR_FC_TX_DIS|GM_GPCR_TX_ENA|GM_GPCR_RX_ENA|
191 GM_GPCR_DUP_FULL|GM_GPCR_FC_RX_DIS|GM_GPCR_AU_FCT_DIS);
193 /* Set WOL address */
194 memcpy_toio(hw->regs + WOL_REGS(port, WOL_MAC_ADDR),
195 skge->netdev->dev_addr, ETH_ALEN);
197 /* Turn on appropriate WOL control bits */
198 skge_write16(hw, WOL_REGS(port, WOL_CTRL_STAT), WOL_CTL_CLEAR_RESULT);
200 if (skge->wol & WAKE_PHY)
201 ctrl |= WOL_CTL_ENA_PME_ON_LINK_CHG|WOL_CTL_ENA_LINK_CHG_UNIT;
203 ctrl |= WOL_CTL_DIS_PME_ON_LINK_CHG|WOL_CTL_DIS_LINK_CHG_UNIT;
205 if (skge->wol & WAKE_MAGIC)
206 ctrl |= WOL_CTL_ENA_PME_ON_MAGIC_PKT|WOL_CTL_ENA_MAGIC_PKT_UNIT;
208 ctrl |= WOL_CTL_DIS_PME_ON_MAGIC_PKT|WOL_CTL_DIS_MAGIC_PKT_UNIT;;
210 ctrl |= WOL_CTL_DIS_PME_ON_PATTERN|WOL_CTL_DIS_PATTERN_UNIT;
211 skge_write16(hw, WOL_REGS(port, WOL_CTRL_STAT), ctrl);
214 skge_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_SET);
217 static void skge_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
219 struct skge_port *skge = netdev_priv(dev);
221 wol->supported = wol_supported(skge->hw);
222 wol->wolopts = skge->wol;
225 static int skge_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
227 struct skge_port *skge = netdev_priv(dev);
228 struct skge_hw *hw = skge->hw;
230 if (wol->wolopts & wol_supported(hw))
233 skge->wol = wol->wolopts;
234 if (!netif_running(dev))
239 /* Determine supported/advertised modes based on hardware.
240 * Note: ethtool ADVERTISED_xxx == SUPPORTED_xxx
242 static u32 skge_supported_modes(const struct skge_hw *hw)
247 supported = SUPPORTED_10baseT_Half
248 | SUPPORTED_10baseT_Full
249 | SUPPORTED_100baseT_Half
250 | SUPPORTED_100baseT_Full
251 | SUPPORTED_1000baseT_Half
252 | SUPPORTED_1000baseT_Full
253 | SUPPORTED_Autoneg| SUPPORTED_TP;
255 if (hw->chip_id == CHIP_ID_GENESIS)
256 supported &= ~(SUPPORTED_10baseT_Half
257 | SUPPORTED_10baseT_Full
258 | SUPPORTED_100baseT_Half
259 | SUPPORTED_100baseT_Full);
261 else if (hw->chip_id == CHIP_ID_YUKON)
262 supported &= ~SUPPORTED_1000baseT_Half;
264 supported = SUPPORTED_1000baseT_Full | SUPPORTED_1000baseT_Half
265 | SUPPORTED_FIBRE | SUPPORTED_Autoneg;
270 static int skge_get_settings(struct net_device *dev,
271 struct ethtool_cmd *ecmd)
273 struct skge_port *skge = netdev_priv(dev);
274 struct skge_hw *hw = skge->hw;
276 ecmd->transceiver = XCVR_INTERNAL;
277 ecmd->supported = skge_supported_modes(hw);
280 ecmd->port = PORT_TP;
281 ecmd->phy_address = hw->phy_addr;
283 ecmd->port = PORT_FIBRE;
285 ecmd->advertising = skge->advertising;
286 ecmd->autoneg = skge->autoneg;
287 ecmd->speed = skge->speed;
288 ecmd->duplex = skge->duplex;
292 static int skge_set_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
294 struct skge_port *skge = netdev_priv(dev);
295 const struct skge_hw *hw = skge->hw;
296 u32 supported = skge_supported_modes(hw);
298 if (ecmd->autoneg == AUTONEG_ENABLE) {
299 ecmd->advertising = supported;
305 switch (ecmd->speed) {
307 if (ecmd->duplex == DUPLEX_FULL)
308 setting = SUPPORTED_1000baseT_Full;
309 else if (ecmd->duplex == DUPLEX_HALF)
310 setting = SUPPORTED_1000baseT_Half;
315 if (ecmd->duplex == DUPLEX_FULL)
316 setting = SUPPORTED_100baseT_Full;
317 else if (ecmd->duplex == DUPLEX_HALF)
318 setting = SUPPORTED_100baseT_Half;
324 if (ecmd->duplex == DUPLEX_FULL)
325 setting = SUPPORTED_10baseT_Full;
326 else if (ecmd->duplex == DUPLEX_HALF)
327 setting = SUPPORTED_10baseT_Half;
335 if ((setting & supported) == 0)
338 skge->speed = ecmd->speed;
339 skge->duplex = ecmd->duplex;
342 skge->autoneg = ecmd->autoneg;
343 skge->advertising = ecmd->advertising;
345 if (netif_running(dev))
346 skge_phy_reset(skge);
351 static void skge_get_drvinfo(struct net_device *dev,
352 struct ethtool_drvinfo *info)
354 struct skge_port *skge = netdev_priv(dev);
356 strcpy(info->driver, DRV_NAME);
357 strcpy(info->version, DRV_VERSION);
358 strcpy(info->fw_version, "N/A");
359 strcpy(info->bus_info, pci_name(skge->hw->pdev));
362 static const struct skge_stat {
363 char name[ETH_GSTRING_LEN];
367 { "tx_bytes", XM_TXO_OK_HI, GM_TXO_OK_HI },
368 { "rx_bytes", XM_RXO_OK_HI, GM_RXO_OK_HI },
370 { "tx_broadcast", XM_TXF_BC_OK, GM_TXF_BC_OK },
371 { "rx_broadcast", XM_RXF_BC_OK, GM_RXF_BC_OK },
372 { "tx_multicast", XM_TXF_MC_OK, GM_TXF_MC_OK },
373 { "rx_multicast", XM_RXF_MC_OK, GM_RXF_MC_OK },
374 { "tx_unicast", XM_TXF_UC_OK, GM_TXF_UC_OK },
375 { "rx_unicast", XM_RXF_UC_OK, GM_RXF_UC_OK },
376 { "tx_mac_pause", XM_TXF_MPAUSE, GM_TXF_MPAUSE },
377 { "rx_mac_pause", XM_RXF_MPAUSE, GM_RXF_MPAUSE },
379 { "collisions", XM_TXF_SNG_COL, GM_TXF_SNG_COL },
380 { "multi_collisions", XM_TXF_MUL_COL, GM_TXF_MUL_COL },
381 { "aborted", XM_TXF_ABO_COL, GM_TXF_ABO_COL },
382 { "late_collision", XM_TXF_LAT_COL, GM_TXF_LAT_COL },
383 { "fifo_underrun", XM_TXE_FIFO_UR, GM_TXE_FIFO_UR },
384 { "fifo_overflow", XM_RXE_FIFO_OV, GM_RXE_FIFO_OV },
386 { "rx_toolong", XM_RXF_LNG_ERR, GM_RXF_LNG_ERR },
387 { "rx_jabber", XM_RXF_JAB_PKT, GM_RXF_JAB_PKT },
388 { "rx_runt", XM_RXE_RUNT, GM_RXE_FRAG },
389 { "rx_too_long", XM_RXF_LNG_ERR, GM_RXF_LNG_ERR },
390 { "rx_fcs_error", XM_RXF_FCS_ERR, GM_RXF_FCS_ERR },
393 static int skge_get_stats_count(struct net_device *dev)
395 return ARRAY_SIZE(skge_stats);
398 static void skge_get_ethtool_stats(struct net_device *dev,
399 struct ethtool_stats *stats, u64 *data)
401 struct skge_port *skge = netdev_priv(dev);
403 if (skge->hw->chip_id == CHIP_ID_GENESIS)
404 genesis_get_stats(skge, data);
406 yukon_get_stats(skge, data);
409 /* Use hardware MIB variables for critical path statistics and
410 * transmit feedback not reported at interrupt.
411 * Other errors are accounted for in interrupt handler.
413 static struct net_device_stats *skge_get_stats(struct net_device *dev)
415 struct skge_port *skge = netdev_priv(dev);
416 u64 data[ARRAY_SIZE(skge_stats)];
418 if (skge->hw->chip_id == CHIP_ID_GENESIS)
419 genesis_get_stats(skge, data);
421 yukon_get_stats(skge, data);
423 skge->net_stats.tx_bytes = data[0];
424 skge->net_stats.rx_bytes = data[1];
425 skge->net_stats.tx_packets = data[2] + data[4] + data[6];
426 skge->net_stats.rx_packets = data[3] + data[5] + data[7];
427 skge->net_stats.multicast = data[3] + data[5];
428 skge->net_stats.collisions = data[10];
429 skge->net_stats.tx_aborted_errors = data[12];
431 return &skge->net_stats;
434 static void skge_get_strings(struct net_device *dev, u32 stringset, u8 *data)
440 for (i = 0; i < ARRAY_SIZE(skge_stats); i++)
441 memcpy(data + i * ETH_GSTRING_LEN,
442 skge_stats[i].name, ETH_GSTRING_LEN);
447 static void skge_get_ring_param(struct net_device *dev,
448 struct ethtool_ringparam *p)
450 struct skge_port *skge = netdev_priv(dev);
452 p->rx_max_pending = MAX_RX_RING_SIZE;
453 p->tx_max_pending = MAX_TX_RING_SIZE;
454 p->rx_mini_max_pending = 0;
455 p->rx_jumbo_max_pending = 0;
457 p->rx_pending = skge->rx_ring.count;
458 p->tx_pending = skge->tx_ring.count;
459 p->rx_mini_pending = 0;
460 p->rx_jumbo_pending = 0;
463 static int skge_set_ring_param(struct net_device *dev,
464 struct ethtool_ringparam *p)
466 struct skge_port *skge = netdev_priv(dev);
469 if (p->rx_pending == 0 || p->rx_pending > MAX_RX_RING_SIZE ||
470 p->tx_pending < TX_LOW_WATER || p->tx_pending > MAX_TX_RING_SIZE)
473 skge->rx_ring.count = p->rx_pending;
474 skge->tx_ring.count = p->tx_pending;
476 if (netif_running(dev)) {
486 static u32 skge_get_msglevel(struct net_device *netdev)
488 struct skge_port *skge = netdev_priv(netdev);
489 return skge->msg_enable;
492 static void skge_set_msglevel(struct net_device *netdev, u32 value)
494 struct skge_port *skge = netdev_priv(netdev);
495 skge->msg_enable = value;
498 static int skge_nway_reset(struct net_device *dev)
500 struct skge_port *skge = netdev_priv(dev);
502 if (skge->autoneg != AUTONEG_ENABLE || !netif_running(dev))
505 skge_phy_reset(skge);
509 static int skge_set_sg(struct net_device *dev, u32 data)
511 struct skge_port *skge = netdev_priv(dev);
512 struct skge_hw *hw = skge->hw;
514 if (hw->chip_id == CHIP_ID_GENESIS && data)
516 return ethtool_op_set_sg(dev, data);
519 static int skge_set_tx_csum(struct net_device *dev, u32 data)
521 struct skge_port *skge = netdev_priv(dev);
522 struct skge_hw *hw = skge->hw;
524 if (hw->chip_id == CHIP_ID_GENESIS && data)
527 return ethtool_op_set_tx_csum(dev, data);
530 static u32 skge_get_rx_csum(struct net_device *dev)
532 struct skge_port *skge = netdev_priv(dev);
534 return skge->rx_csum;
537 /* Only Yukon supports checksum offload. */
538 static int skge_set_rx_csum(struct net_device *dev, u32 data)
540 struct skge_port *skge = netdev_priv(dev);
542 if (skge->hw->chip_id == CHIP_ID_GENESIS && data)
545 skge->rx_csum = data;
549 static void skge_get_pauseparam(struct net_device *dev,
550 struct ethtool_pauseparam *ecmd)
552 struct skge_port *skge = netdev_priv(dev);
554 ecmd->rx_pause = (skge->flow_control == FLOW_MODE_SYMMETRIC)
555 || (skge->flow_control == FLOW_MODE_SYM_OR_REM);
556 ecmd->tx_pause = ecmd->rx_pause || (skge->flow_control == FLOW_MODE_LOC_SEND);
558 ecmd->autoneg = ecmd->rx_pause || ecmd->tx_pause;
561 static int skge_set_pauseparam(struct net_device *dev,
562 struct ethtool_pauseparam *ecmd)
564 struct skge_port *skge = netdev_priv(dev);
565 struct ethtool_pauseparam old;
567 skge_get_pauseparam(dev, &old);
569 if (ecmd->autoneg != old.autoneg)
570 skge->flow_control = ecmd->autoneg ? FLOW_MODE_NONE : FLOW_MODE_SYMMETRIC;
572 if (ecmd->rx_pause && ecmd->tx_pause)
573 skge->flow_control = FLOW_MODE_SYMMETRIC;
574 else if (ecmd->rx_pause && !ecmd->tx_pause)
575 skge->flow_control = FLOW_MODE_SYM_OR_REM;
576 else if (!ecmd->rx_pause && ecmd->tx_pause)
577 skge->flow_control = FLOW_MODE_LOC_SEND;
579 skge->flow_control = FLOW_MODE_NONE;
582 if (netif_running(dev))
583 skge_phy_reset(skge);
588 /* Chip internal frequency for clock calculations */
589 static inline u32 hwkhz(const struct skge_hw *hw)
591 return (hw->chip_id == CHIP_ID_GENESIS) ? 53125 : 78125;
594 /* Chip HZ to microseconds */
595 static inline u32 skge_clk2usec(const struct skge_hw *hw, u32 ticks)
597 return (ticks * 1000) / hwkhz(hw);
600 /* Microseconds to chip HZ */
601 static inline u32 skge_usecs2clk(const struct skge_hw *hw, u32 usec)
603 return hwkhz(hw) * usec / 1000;
606 static int skge_get_coalesce(struct net_device *dev,
607 struct ethtool_coalesce *ecmd)
609 struct skge_port *skge = netdev_priv(dev);
610 struct skge_hw *hw = skge->hw;
611 int port = skge->port;
613 ecmd->rx_coalesce_usecs = 0;
614 ecmd->tx_coalesce_usecs = 0;
616 if (skge_read32(hw, B2_IRQM_CTRL) & TIM_START) {
617 u32 delay = skge_clk2usec(hw, skge_read32(hw, B2_IRQM_INI));
618 u32 msk = skge_read32(hw, B2_IRQM_MSK);
620 if (msk & rxirqmask[port])
621 ecmd->rx_coalesce_usecs = delay;
622 if (msk & txirqmask[port])
623 ecmd->tx_coalesce_usecs = delay;
629 /* Note: interrupt timer is per board, but can turn on/off per port */
630 static int skge_set_coalesce(struct net_device *dev,
631 struct ethtool_coalesce *ecmd)
633 struct skge_port *skge = netdev_priv(dev);
634 struct skge_hw *hw = skge->hw;
635 int port = skge->port;
636 u32 msk = skge_read32(hw, B2_IRQM_MSK);
639 if (ecmd->rx_coalesce_usecs == 0)
640 msk &= ~rxirqmask[port];
641 else if (ecmd->rx_coalesce_usecs < 25 ||
642 ecmd->rx_coalesce_usecs > 33333)
645 msk |= rxirqmask[port];
646 delay = ecmd->rx_coalesce_usecs;
649 if (ecmd->tx_coalesce_usecs == 0)
650 msk &= ~txirqmask[port];
651 else if (ecmd->tx_coalesce_usecs < 25 ||
652 ecmd->tx_coalesce_usecs > 33333)
655 msk |= txirqmask[port];
656 delay = min(delay, ecmd->rx_coalesce_usecs);
659 skge_write32(hw, B2_IRQM_MSK, msk);
661 skge_write32(hw, B2_IRQM_CTRL, TIM_STOP);
663 skge_write32(hw, B2_IRQM_INI, skge_usecs2clk(hw, delay));
664 skge_write32(hw, B2_IRQM_CTRL, TIM_START);
669 enum led_mode { LED_MODE_OFF, LED_MODE_ON, LED_MODE_TST };
670 static void skge_led(struct skge_port *skge, enum led_mode mode)
672 struct skge_hw *hw = skge->hw;
673 int port = skge->port;
675 spin_lock_bh(&hw->phy_lock);
676 if (hw->chip_id == CHIP_ID_GENESIS) {
679 if (hw->phy_type == SK_PHY_BCOM)
680 xm_phy_write(hw, port, PHY_BCOM_P_EXT_CTRL, PHY_B_PEC_LED_OFF);
682 skge_write32(hw, SK_REG(port, TX_LED_VAL), 0);
683 skge_write8(hw, SK_REG(port, TX_LED_CTRL), LED_T_OFF);
685 skge_write8(hw, SK_REG(port, LNK_LED_REG), LINKLED_OFF);
686 skge_write32(hw, SK_REG(port, RX_LED_VAL), 0);
687 skge_write8(hw, SK_REG(port, RX_LED_CTRL), LED_T_OFF);
691 skge_write8(hw, SK_REG(port, LNK_LED_REG), LINKLED_ON);
692 skge_write8(hw, SK_REG(port, LNK_LED_REG), LINKLED_LINKSYNC_ON);
694 skge_write8(hw, SK_REG(port, RX_LED_CTRL), LED_START);
695 skge_write8(hw, SK_REG(port, TX_LED_CTRL), LED_START);
700 skge_write8(hw, SK_REG(port, RX_LED_TST), LED_T_ON);
701 skge_write32(hw, SK_REG(port, RX_LED_VAL), 100);
702 skge_write8(hw, SK_REG(port, RX_LED_CTRL), LED_START);
704 if (hw->phy_type == SK_PHY_BCOM)
705 xm_phy_write(hw, port, PHY_BCOM_P_EXT_CTRL, PHY_B_PEC_LED_ON);
707 skge_write8(hw, SK_REG(port, TX_LED_TST), LED_T_ON);
708 skge_write32(hw, SK_REG(port, TX_LED_VAL), 100);
709 skge_write8(hw, SK_REG(port, TX_LED_CTRL), LED_START);
716 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, 0);
717 gm_phy_write(hw, port, PHY_MARV_LED_OVER,
718 PHY_M_LED_MO_DUP(MO_LED_OFF) |
719 PHY_M_LED_MO_10(MO_LED_OFF) |
720 PHY_M_LED_MO_100(MO_LED_OFF) |
721 PHY_M_LED_MO_1000(MO_LED_OFF) |
722 PHY_M_LED_MO_RX(MO_LED_OFF));
725 gm_phy_write(hw, port, PHY_MARV_LED_CTRL,
726 PHY_M_LED_PULS_DUR(PULS_170MS) |
727 PHY_M_LED_BLINK_RT(BLINK_84MS) |
731 gm_phy_write(hw, port, PHY_MARV_LED_OVER,
732 PHY_M_LED_MO_RX(MO_LED_OFF) |
733 (skge->speed == SPEED_100 ?
734 PHY_M_LED_MO_100(MO_LED_ON) : 0));
737 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, 0);
738 gm_phy_write(hw, port, PHY_MARV_LED_OVER,
739 PHY_M_LED_MO_DUP(MO_LED_ON) |
740 PHY_M_LED_MO_10(MO_LED_ON) |
741 PHY_M_LED_MO_100(MO_LED_ON) |
742 PHY_M_LED_MO_1000(MO_LED_ON) |
743 PHY_M_LED_MO_RX(MO_LED_ON));
746 spin_unlock_bh(&hw->phy_lock);
749 /* blink LED's for finding board */
750 static int skge_phys_id(struct net_device *dev, u32 data)
752 struct skge_port *skge = netdev_priv(dev);
754 enum led_mode mode = LED_MODE_TST;
756 if (!data || data > (u32)(MAX_SCHEDULE_TIMEOUT / HZ))
757 ms = jiffies_to_msecs(MAX_SCHEDULE_TIMEOUT / HZ) * 1000;
762 skge_led(skge, mode);
763 mode ^= LED_MODE_TST;
765 if (msleep_interruptible(BLINK_MS))
770 /* back to regular LED state */
771 skge_led(skge, netif_running(dev) ? LED_MODE_ON : LED_MODE_OFF);
776 static const struct ethtool_ops skge_ethtool_ops = {
777 .get_settings = skge_get_settings,
778 .set_settings = skge_set_settings,
779 .get_drvinfo = skge_get_drvinfo,
780 .get_regs_len = skge_get_regs_len,
781 .get_regs = skge_get_regs,
782 .get_wol = skge_get_wol,
783 .set_wol = skge_set_wol,
784 .get_msglevel = skge_get_msglevel,
785 .set_msglevel = skge_set_msglevel,
786 .nway_reset = skge_nway_reset,
787 .get_link = ethtool_op_get_link,
788 .get_ringparam = skge_get_ring_param,
789 .set_ringparam = skge_set_ring_param,
790 .get_pauseparam = skge_get_pauseparam,
791 .set_pauseparam = skge_set_pauseparam,
792 .get_coalesce = skge_get_coalesce,
793 .set_coalesce = skge_set_coalesce,
794 .get_sg = ethtool_op_get_sg,
795 .set_sg = skge_set_sg,
796 .get_tx_csum = ethtool_op_get_tx_csum,
797 .set_tx_csum = skge_set_tx_csum,
798 .get_rx_csum = skge_get_rx_csum,
799 .set_rx_csum = skge_set_rx_csum,
800 .get_strings = skge_get_strings,
801 .phys_id = skge_phys_id,
802 .get_stats_count = skge_get_stats_count,
803 .get_ethtool_stats = skge_get_ethtool_stats,
804 .get_perm_addr = ethtool_op_get_perm_addr,
808 * Allocate ring elements and chain them together
809 * One-to-one association of board descriptors with ring elements
811 static int skge_ring_alloc(struct skge_ring *ring, void *vaddr, u32 base)
813 struct skge_tx_desc *d;
814 struct skge_element *e;
817 ring->start = kcalloc(ring->count, sizeof(*e), GFP_KERNEL);
821 for (i = 0, e = ring->start, d = vaddr; i < ring->count; i++, e++, d++) {
823 if (i == ring->count - 1) {
824 e->next = ring->start;
825 d->next_offset = base;
828 d->next_offset = base + (i+1) * sizeof(*d);
831 ring->to_use = ring->to_clean = ring->start;
836 /* Allocate and setup a new buffer for receiving */
837 static void skge_rx_setup(struct skge_port *skge, struct skge_element *e,
838 struct sk_buff *skb, unsigned int bufsize)
840 struct skge_rx_desc *rd = e->desc;
843 map = pci_map_single(skge->hw->pdev, skb->data, bufsize,
847 rd->dma_hi = map >> 32;
849 rd->csum1_start = ETH_HLEN;
850 rd->csum2_start = ETH_HLEN;
856 rd->control = BMU_OWN | BMU_STF | BMU_IRQ_EOF | BMU_TCP_CHECK | bufsize;
857 pci_unmap_addr_set(e, mapaddr, map);
858 pci_unmap_len_set(e, maplen, bufsize);
861 /* Resume receiving using existing skb,
862 * Note: DMA address is not changed by chip.
863 * MTU not changed while receiver active.
865 static inline void skge_rx_reuse(struct skge_element *e, unsigned int size)
867 struct skge_rx_desc *rd = e->desc;
870 rd->csum2_start = ETH_HLEN;
874 rd->control = BMU_OWN | BMU_STF | BMU_IRQ_EOF | BMU_TCP_CHECK | size;
878 /* Free all buffers in receive ring, assumes receiver stopped */
879 static void skge_rx_clean(struct skge_port *skge)
881 struct skge_hw *hw = skge->hw;
882 struct skge_ring *ring = &skge->rx_ring;
883 struct skge_element *e;
887 struct skge_rx_desc *rd = e->desc;
890 pci_unmap_single(hw->pdev,
891 pci_unmap_addr(e, mapaddr),
892 pci_unmap_len(e, maplen),
894 dev_kfree_skb(e->skb);
897 } while ((e = e->next) != ring->start);
901 /* Allocate buffers for receive ring
902 * For receive: to_clean is next received frame.
904 static int skge_rx_fill(struct net_device *dev)
906 struct skge_port *skge = netdev_priv(dev);
907 struct skge_ring *ring = &skge->rx_ring;
908 struct skge_element *e;
914 skb = __netdev_alloc_skb(dev, skge->rx_buf_size + NET_IP_ALIGN,
919 skb_reserve(skb, NET_IP_ALIGN);
920 skge_rx_setup(skge, e, skb, skge->rx_buf_size);
921 } while ( (e = e->next) != ring->start);
923 ring->to_clean = ring->start;
927 static const char *skge_pause(enum pause_status status)
932 case FLOW_STAT_REM_SEND:
934 case FLOW_STAT_LOC_SEND:
936 case FLOW_STAT_SYMMETRIC: /* Both station may send PAUSE */
939 return "indeterminated";
944 static void skge_link_up(struct skge_port *skge)
946 skge_write8(skge->hw, SK_REG(skge->port, LNK_LED_REG),
947 LED_BLK_OFF|LED_SYNC_OFF|LED_ON);
949 netif_carrier_on(skge->netdev);
950 netif_wake_queue(skge->netdev);
952 if (netif_msg_link(skge)) {
954 "%s: Link is up at %d Mbps, %s duplex, flow control %s\n",
955 skge->netdev->name, skge->speed,
956 skge->duplex == DUPLEX_FULL ? "full" : "half",
957 skge_pause(skge->flow_status));
961 static void skge_link_down(struct skge_port *skge)
963 skge_write8(skge->hw, SK_REG(skge->port, LNK_LED_REG), LED_OFF);
964 netif_carrier_off(skge->netdev);
965 netif_stop_queue(skge->netdev);
967 if (netif_msg_link(skge))
968 printk(KERN_INFO PFX "%s: Link is down.\n", skge->netdev->name);
972 static void xm_link_down(struct skge_hw *hw, int port)
974 struct net_device *dev = hw->dev[port];
975 struct skge_port *skge = netdev_priv(dev);
978 if (hw->phy_type == SK_PHY_XMAC) {
979 msk = xm_read16(hw, port, XM_IMSK);
980 msk |= XM_IS_INP_ASS | XM_IS_LIPA_RC | XM_IS_RX_PAGE | XM_IS_AND;
981 xm_write16(hw, port, XM_IMSK, msk);
984 cmd = xm_read16(hw, port, XM_MMU_CMD);
985 cmd &= ~(XM_MMU_ENA_RX | XM_MMU_ENA_TX);
986 xm_write16(hw, port, XM_MMU_CMD, cmd);
987 /* dummy read to ensure writing */
988 (void) xm_read16(hw, port, XM_MMU_CMD);
990 if (netif_carrier_ok(dev))
991 skge_link_down(skge);
994 static int __xm_phy_read(struct skge_hw *hw, int port, u16 reg, u16 *val)
998 xm_write16(hw, port, XM_PHY_ADDR, reg | hw->phy_addr);
999 *val = xm_read16(hw, port, XM_PHY_DATA);
1001 if (hw->phy_type == SK_PHY_XMAC)
1004 for (i = 0; i < PHY_RETRIES; i++) {
1005 if (xm_read16(hw, port, XM_MMU_CMD) & XM_MMU_PHY_RDY)
1012 *val = xm_read16(hw, port, XM_PHY_DATA);
1017 static u16 xm_phy_read(struct skge_hw *hw, int port, u16 reg)
1020 if (__xm_phy_read(hw, port, reg, &v))
1021 printk(KERN_WARNING PFX "%s: phy read timed out\n",
1022 hw->dev[port]->name);
1026 static int xm_phy_write(struct skge_hw *hw, int port, u16 reg, u16 val)
1030 xm_write16(hw, port, XM_PHY_ADDR, reg | hw->phy_addr);
1031 for (i = 0; i < PHY_RETRIES; i++) {
1032 if (!(xm_read16(hw, port, XM_MMU_CMD) & XM_MMU_PHY_BUSY))
1039 xm_write16(hw, port, XM_PHY_DATA, val);
1040 for (i = 0; i < PHY_RETRIES; i++) {
1041 if (!(xm_read16(hw, port, XM_MMU_CMD) & XM_MMU_PHY_BUSY))
1048 static void genesis_init(struct skge_hw *hw)
1050 /* set blink source counter */
1051 skge_write32(hw, B2_BSC_INI, (SK_BLK_DUR * SK_FACT_53) / 100);
1052 skge_write8(hw, B2_BSC_CTRL, BSC_START);
1054 /* configure mac arbiter */
1055 skge_write16(hw, B3_MA_TO_CTRL, MA_RST_CLR);
1057 /* configure mac arbiter timeout values */
1058 skge_write8(hw, B3_MA_TOINI_RX1, SK_MAC_TO_53);
1059 skge_write8(hw, B3_MA_TOINI_RX2, SK_MAC_TO_53);
1060 skge_write8(hw, B3_MA_TOINI_TX1, SK_MAC_TO_53);
1061 skge_write8(hw, B3_MA_TOINI_TX2, SK_MAC_TO_53);
1063 skge_write8(hw, B3_MA_RCINI_RX1, 0);
1064 skge_write8(hw, B3_MA_RCINI_RX2, 0);
1065 skge_write8(hw, B3_MA_RCINI_TX1, 0);
1066 skge_write8(hw, B3_MA_RCINI_TX2, 0);
1068 /* configure packet arbiter timeout */
1069 skge_write16(hw, B3_PA_CTRL, PA_RST_CLR);
1070 skge_write16(hw, B3_PA_TOINI_RX1, SK_PKT_TO_MAX);
1071 skge_write16(hw, B3_PA_TOINI_TX1, SK_PKT_TO_MAX);
1072 skge_write16(hw, B3_PA_TOINI_RX2, SK_PKT_TO_MAX);
1073 skge_write16(hw, B3_PA_TOINI_TX2, SK_PKT_TO_MAX);
1076 static void genesis_reset(struct skge_hw *hw, int port)
1078 const u8 zero[8] = { 0 };
1080 skge_write8(hw, SK_REG(port, GMAC_IRQ_MSK), 0);
1082 /* reset the statistics module */
1083 xm_write32(hw, port, XM_GP_PORT, XM_GP_RES_STAT);
1084 xm_write16(hw, port, XM_IMSK, 0xffff); /* disable XMAC IRQs */
1085 xm_write32(hw, port, XM_MODE, 0); /* clear Mode Reg */
1086 xm_write16(hw, port, XM_TX_CMD, 0); /* reset TX CMD Reg */
1087 xm_write16(hw, port, XM_RX_CMD, 0); /* reset RX CMD Reg */
1089 /* disable Broadcom PHY IRQ */
1090 if (hw->phy_type == SK_PHY_BCOM)
1091 xm_write16(hw, port, PHY_BCOM_INT_MASK, 0xffff);
1093 xm_outhash(hw, port, XM_HSM, zero);
1097 /* Convert mode to MII values */
1098 static const u16 phy_pause_map[] = {
1099 [FLOW_MODE_NONE] = 0,
1100 [FLOW_MODE_LOC_SEND] = PHY_AN_PAUSE_ASYM,
1101 [FLOW_MODE_SYMMETRIC] = PHY_AN_PAUSE_CAP,
1102 [FLOW_MODE_SYM_OR_REM] = PHY_AN_PAUSE_CAP | PHY_AN_PAUSE_ASYM,
1105 /* special defines for FIBER (88E1011S only) */
1106 static const u16 fiber_pause_map[] = {
1107 [FLOW_MODE_NONE] = PHY_X_P_NO_PAUSE,
1108 [FLOW_MODE_LOC_SEND] = PHY_X_P_ASYM_MD,
1109 [FLOW_MODE_SYMMETRIC] = PHY_X_P_SYM_MD,
1110 [FLOW_MODE_SYM_OR_REM] = PHY_X_P_BOTH_MD,
1114 /* Check status of Broadcom phy link */
1115 static void bcom_check_link(struct skge_hw *hw, int port)
1117 struct net_device *dev = hw->dev[port];
1118 struct skge_port *skge = netdev_priv(dev);
1121 /* read twice because of latch */
1122 (void) xm_phy_read(hw, port, PHY_BCOM_STAT);
1123 status = xm_phy_read(hw, port, PHY_BCOM_STAT);
1125 if ((status & PHY_ST_LSYNC) == 0) {
1126 xm_link_down(hw, port);
1130 if (skge->autoneg == AUTONEG_ENABLE) {
1133 if (!(status & PHY_ST_AN_OVER))
1136 lpa = xm_phy_read(hw, port, PHY_XMAC_AUNE_LP);
1137 if (lpa & PHY_B_AN_RF) {
1138 printk(KERN_NOTICE PFX "%s: remote fault\n",
1143 aux = xm_phy_read(hw, port, PHY_BCOM_AUX_STAT);
1145 /* Check Duplex mismatch */
1146 switch (aux & PHY_B_AS_AN_RES_MSK) {
1147 case PHY_B_RES_1000FD:
1148 skge->duplex = DUPLEX_FULL;
1150 case PHY_B_RES_1000HD:
1151 skge->duplex = DUPLEX_HALF;
1154 printk(KERN_NOTICE PFX "%s: duplex mismatch\n",
1159 /* We are using IEEE 802.3z/D5.0 Table 37-4 */
1160 switch (aux & PHY_B_AS_PAUSE_MSK) {
1161 case PHY_B_AS_PAUSE_MSK:
1162 skge->flow_status = FLOW_STAT_SYMMETRIC;
1165 skge->flow_status = FLOW_STAT_REM_SEND;
1168 skge->flow_status = FLOW_STAT_LOC_SEND;
1171 skge->flow_status = FLOW_STAT_NONE;
1173 skge->speed = SPEED_1000;
1176 if (!netif_carrier_ok(dev))
1177 genesis_link_up(skge);
1180 /* Broadcom 5400 only supports giagabit! SysKonnect did not put an additional
1181 * Phy on for 100 or 10Mbit operation
1183 static void bcom_phy_init(struct skge_port *skge)
1185 struct skge_hw *hw = skge->hw;
1186 int port = skge->port;
1188 u16 id1, r, ext, ctl;
1190 /* magic workaround patterns for Broadcom */
1191 static const struct {
1195 { 0x18, 0x0c20 }, { 0x17, 0x0012 }, { 0x15, 0x1104 },
1196 { 0x17, 0x0013 }, { 0x15, 0x0404 }, { 0x17, 0x8006 },
1197 { 0x15, 0x0132 }, { 0x17, 0x8006 }, { 0x15, 0x0232 },
1198 { 0x17, 0x800D }, { 0x15, 0x000F }, { 0x18, 0x0420 },
1200 { 0x18, 0x0c20 }, { 0x17, 0x0012 }, { 0x15, 0x1204 },
1201 { 0x17, 0x0013 }, { 0x15, 0x0A04 }, { 0x18, 0x0420 },
1204 /* read Id from external PHY (all have the same address) */
1205 id1 = xm_phy_read(hw, port, PHY_XMAC_ID1);
1207 /* Optimize MDIO transfer by suppressing preamble. */
1208 r = xm_read16(hw, port, XM_MMU_CMD);
1210 xm_write16(hw, port, XM_MMU_CMD,r);
1213 case PHY_BCOM_ID1_C0:
1215 * Workaround BCOM Errata for the C0 type.
1216 * Write magic patterns to reserved registers.
1218 for (i = 0; i < ARRAY_SIZE(C0hack); i++)
1219 xm_phy_write(hw, port,
1220 C0hack[i].reg, C0hack[i].val);
1223 case PHY_BCOM_ID1_A1:
1225 * Workaround BCOM Errata for the A1 type.
1226 * Write magic patterns to reserved registers.
1228 for (i = 0; i < ARRAY_SIZE(A1hack); i++)
1229 xm_phy_write(hw, port,
1230 A1hack[i].reg, A1hack[i].val);
1235 * Workaround BCOM Errata (#10523) for all BCom PHYs.
1236 * Disable Power Management after reset.
1238 r = xm_phy_read(hw, port, PHY_BCOM_AUX_CTRL);
1239 r |= PHY_B_AC_DIS_PM;
1240 xm_phy_write(hw, port, PHY_BCOM_AUX_CTRL, r);
1243 xm_read16(hw, port, XM_ISRC);
1245 ext = PHY_B_PEC_EN_LTR; /* enable tx led */
1246 ctl = PHY_CT_SP1000; /* always 1000mbit */
1248 if (skge->autoneg == AUTONEG_ENABLE) {
1250 * Workaround BCOM Errata #1 for the C5 type.
1251 * 1000Base-T Link Acquisition Failure in Slave Mode
1252 * Set Repeater/DTE bit 10 of the 1000Base-T Control Register
1254 u16 adv = PHY_B_1000C_RD;
1255 if (skge->advertising & ADVERTISED_1000baseT_Half)
1256 adv |= PHY_B_1000C_AHD;
1257 if (skge->advertising & ADVERTISED_1000baseT_Full)
1258 adv |= PHY_B_1000C_AFD;
1259 xm_phy_write(hw, port, PHY_BCOM_1000T_CTRL, adv);
1261 ctl |= PHY_CT_ANE | PHY_CT_RE_CFG;
1263 if (skge->duplex == DUPLEX_FULL)
1264 ctl |= PHY_CT_DUP_MD;
1265 /* Force to slave */
1266 xm_phy_write(hw, port, PHY_BCOM_1000T_CTRL, PHY_B_1000C_MSE);
1269 /* Set autonegotiation pause parameters */
1270 xm_phy_write(hw, port, PHY_BCOM_AUNE_ADV,
1271 phy_pause_map[skge->flow_control] | PHY_AN_CSMA);
1273 /* Handle Jumbo frames */
1274 if (hw->dev[port]->mtu > ETH_DATA_LEN) {
1275 xm_phy_write(hw, port, PHY_BCOM_AUX_CTRL,
1276 PHY_B_AC_TX_TST | PHY_B_AC_LONG_PACK);
1278 ext |= PHY_B_PEC_HIGH_LA;
1282 xm_phy_write(hw, port, PHY_BCOM_P_EXT_CTRL, ext);
1283 xm_phy_write(hw, port, PHY_BCOM_CTRL, ctl);
1285 /* Use link status change interrupt */
1286 xm_phy_write(hw, port, PHY_BCOM_INT_MASK, PHY_B_DEF_MSK);
1289 static void xm_phy_init(struct skge_port *skge)
1291 struct skge_hw *hw = skge->hw;
1292 int port = skge->port;
1295 if (skge->autoneg == AUTONEG_ENABLE) {
1296 if (skge->advertising & ADVERTISED_1000baseT_Half)
1297 ctrl |= PHY_X_AN_HD;
1298 if (skge->advertising & ADVERTISED_1000baseT_Full)
1299 ctrl |= PHY_X_AN_FD;
1301 ctrl |= fiber_pause_map[skge->flow_control];
1303 xm_phy_write(hw, port, PHY_XMAC_AUNE_ADV, ctrl);
1305 /* Restart Auto-negotiation */
1306 ctrl = PHY_CT_ANE | PHY_CT_RE_CFG;
1308 /* Set DuplexMode in Config register */
1309 if (skge->duplex == DUPLEX_FULL)
1310 ctrl |= PHY_CT_DUP_MD;
1312 * Do NOT enable Auto-negotiation here. This would hold
1313 * the link down because no IDLEs are transmitted
1317 xm_phy_write(hw, port, PHY_XMAC_CTRL, ctrl);
1319 /* Poll PHY for status changes */
1320 mod_timer(&skge->link_timer, jiffies + LINK_HZ);
1323 static void xm_check_link(struct net_device *dev)
1325 struct skge_port *skge = netdev_priv(dev);
1326 struct skge_hw *hw = skge->hw;
1327 int port = skge->port;
1330 /* read twice because of latch */
1331 (void) xm_phy_read(hw, port, PHY_XMAC_STAT);
1332 status = xm_phy_read(hw, port, PHY_XMAC_STAT);
1334 if ((status & PHY_ST_LSYNC) == 0) {
1335 xm_link_down(hw, port);
1339 if (skge->autoneg == AUTONEG_ENABLE) {
1342 if (!(status & PHY_ST_AN_OVER))
1345 lpa = xm_phy_read(hw, port, PHY_XMAC_AUNE_LP);
1346 if (lpa & PHY_B_AN_RF) {
1347 printk(KERN_NOTICE PFX "%s: remote fault\n",
1352 res = xm_phy_read(hw, port, PHY_XMAC_RES_ABI);
1354 /* Check Duplex mismatch */
1355 switch (res & (PHY_X_RS_HD | PHY_X_RS_FD)) {
1357 skge->duplex = DUPLEX_FULL;
1360 skge->duplex = DUPLEX_HALF;
1363 printk(KERN_NOTICE PFX "%s: duplex mismatch\n",
1368 /* We are using IEEE 802.3z/D5.0 Table 37-4 */
1369 if ((skge->flow_control == FLOW_MODE_SYMMETRIC ||
1370 skge->flow_control == FLOW_MODE_SYM_OR_REM) &&
1371 (lpa & PHY_X_P_SYM_MD))
1372 skge->flow_status = FLOW_STAT_SYMMETRIC;
1373 else if (skge->flow_control == FLOW_MODE_SYM_OR_REM &&
1374 (lpa & PHY_X_RS_PAUSE) == PHY_X_P_ASYM_MD)
1375 /* Enable PAUSE receive, disable PAUSE transmit */
1376 skge->flow_status = FLOW_STAT_REM_SEND;
1377 else if (skge->flow_control == FLOW_MODE_LOC_SEND &&
1378 (lpa & PHY_X_RS_PAUSE) == PHY_X_P_BOTH_MD)
1379 /* Disable PAUSE receive, enable PAUSE transmit */
1380 skge->flow_status = FLOW_STAT_LOC_SEND;
1382 skge->flow_status = FLOW_STAT_NONE;
1384 skge->speed = SPEED_1000;
1387 if (!netif_carrier_ok(dev))
1388 genesis_link_up(skge);
1391 /* Poll to check for link coming up.
1392 * Since internal PHY is wired to a level triggered pin, can't
1393 * get an interrupt when carrier is detected.
1395 static void xm_link_timer(unsigned long arg)
1397 struct skge_port *skge = (struct skge_port *) arg;
1398 struct net_device *dev = skge->netdev;
1399 struct skge_hw *hw = skge->hw;
1400 int port = skge->port;
1402 if (!netif_running(dev))
1405 if (netif_carrier_ok(dev)) {
1406 xm_read16(hw, port, XM_ISRC);
1407 if (!(xm_read16(hw, port, XM_ISRC) & XM_IS_INP_ASS))
1410 if (xm_read32(hw, port, XM_GP_PORT) & XM_GP_INP_ASS)
1412 xm_read16(hw, port, XM_ISRC);
1413 if (xm_read16(hw, port, XM_ISRC) & XM_IS_INP_ASS)
1417 spin_lock(&hw->phy_lock);
1419 spin_unlock(&hw->phy_lock);
1422 if (netif_running(dev))
1423 mod_timer(&skge->link_timer, jiffies + LINK_HZ);
1426 static void genesis_mac_init(struct skge_hw *hw, int port)
1428 struct net_device *dev = hw->dev[port];
1429 struct skge_port *skge = netdev_priv(dev);
1430 int jumbo = hw->dev[port]->mtu > ETH_DATA_LEN;
1433 const u8 zero[6] = { 0 };
1435 for (i = 0; i < 10; i++) {
1436 skge_write16(hw, SK_REG(port, TX_MFF_CTRL1),
1438 if (skge_read16(hw, SK_REG(port, TX_MFF_CTRL1)) & MFF_SET_MAC_RST)
1443 printk(KERN_WARNING PFX "%s: genesis reset failed\n", dev->name);
1446 /* Unreset the XMAC. */
1447 skge_write16(hw, SK_REG(port, TX_MFF_CTRL1), MFF_CLR_MAC_RST);
1450 * Perform additional initialization for external PHYs,
1451 * namely for the 1000baseTX cards that use the XMAC's
1454 if (hw->phy_type != SK_PHY_XMAC) {
1455 /* Take external Phy out of reset */
1456 r = skge_read32(hw, B2_GP_IO);
1458 r |= GP_DIR_0|GP_IO_0;
1460 r |= GP_DIR_2|GP_IO_2;
1462 skge_write32(hw, B2_GP_IO, r);
1464 /* Enable GMII interface */
1465 xm_write16(hw, port, XM_HW_CFG, XM_HW_GMII_MD);
1469 switch(hw->phy_type) {
1474 bcom_phy_init(skge);
1475 bcom_check_link(hw, port);
1478 /* Set Station Address */
1479 xm_outaddr(hw, port, XM_SA, dev->dev_addr);
1481 /* We don't use match addresses so clear */
1482 for (i = 1; i < 16; i++)
1483 xm_outaddr(hw, port, XM_EXM(i), zero);
1485 /* Clear MIB counters */
1486 xm_write16(hw, port, XM_STAT_CMD,
1487 XM_SC_CLR_RXC | XM_SC_CLR_TXC);
1488 /* Clear two times according to Errata #3 */
1489 xm_write16(hw, port, XM_STAT_CMD,
1490 XM_SC_CLR_RXC | XM_SC_CLR_TXC);
1492 /* configure Rx High Water Mark (XM_RX_HI_WM) */
1493 xm_write16(hw, port, XM_RX_HI_WM, 1450);
1495 /* We don't need the FCS appended to the packet. */
1496 r = XM_RX_LENERR_OK | XM_RX_STRIP_FCS;
1498 r |= XM_RX_BIG_PK_OK;
1500 if (skge->duplex == DUPLEX_HALF) {
1502 * If in manual half duplex mode the other side might be in
1503 * full duplex mode, so ignore if a carrier extension is not seen
1504 * on frames received
1506 r |= XM_RX_DIS_CEXT;
1508 xm_write16(hw, port, XM_RX_CMD, r);
1511 /* We want short frames padded to 60 bytes. */
1512 xm_write16(hw, port, XM_TX_CMD, XM_TX_AUTO_PAD);
1515 * Bump up the transmit threshold. This helps hold off transmit
1516 * underruns when we're blasting traffic from both ports at once.
1518 xm_write16(hw, port, XM_TX_THR, 512);
1521 * Enable the reception of all error frames. This is is
1522 * a necessary evil due to the design of the XMAC. The
1523 * XMAC's receive FIFO is only 8K in size, however jumbo
1524 * frames can be up to 9000 bytes in length. When bad
1525 * frame filtering is enabled, the XMAC's RX FIFO operates
1526 * in 'store and forward' mode. For this to work, the
1527 * entire frame has to fit into the FIFO, but that means
1528 * that jumbo frames larger than 8192 bytes will be
1529 * truncated. Disabling all bad frame filtering causes
1530 * the RX FIFO to operate in streaming mode, in which
1531 * case the XMAC will start transferring frames out of the
1532 * RX FIFO as soon as the FIFO threshold is reached.
1534 xm_write32(hw, port, XM_MODE, XM_DEF_MODE);
1538 * Initialize the Receive Counter Event Mask (XM_RX_EV_MSK)
1539 * - Enable all bits excepting 'Octets Rx OK Low CntOv'
1540 * and 'Octets Rx OK Hi Cnt Ov'.
1542 xm_write32(hw, port, XM_RX_EV_MSK, XMR_DEF_MSK);
1545 * Initialize the Transmit Counter Event Mask (XM_TX_EV_MSK)
1546 * - Enable all bits excepting 'Octets Tx OK Low CntOv'
1547 * and 'Octets Tx OK Hi Cnt Ov'.
1549 xm_write32(hw, port, XM_TX_EV_MSK, XMT_DEF_MSK);
1551 /* Configure MAC arbiter */
1552 skge_write16(hw, B3_MA_TO_CTRL, MA_RST_CLR);
1554 /* configure timeout values */
1555 skge_write8(hw, B3_MA_TOINI_RX1, 72);
1556 skge_write8(hw, B3_MA_TOINI_RX2, 72);
1557 skge_write8(hw, B3_MA_TOINI_TX1, 72);
1558 skge_write8(hw, B3_MA_TOINI_TX2, 72);
1560 skge_write8(hw, B3_MA_RCINI_RX1, 0);
1561 skge_write8(hw, B3_MA_RCINI_RX2, 0);
1562 skge_write8(hw, B3_MA_RCINI_TX1, 0);
1563 skge_write8(hw, B3_MA_RCINI_TX2, 0);
1565 /* Configure Rx MAC FIFO */
1566 skge_write8(hw, SK_REG(port, RX_MFF_CTRL2), MFF_RST_CLR);
1567 skge_write16(hw, SK_REG(port, RX_MFF_CTRL1), MFF_ENA_TIM_PAT);
1568 skge_write8(hw, SK_REG(port, RX_MFF_CTRL2), MFF_ENA_OP_MD);
1570 /* Configure Tx MAC FIFO */
1571 skge_write8(hw, SK_REG(port, TX_MFF_CTRL2), MFF_RST_CLR);
1572 skge_write16(hw, SK_REG(port, TX_MFF_CTRL1), MFF_TX_CTRL_DEF);
1573 skge_write8(hw, SK_REG(port, TX_MFF_CTRL2), MFF_ENA_OP_MD);
1576 /* Enable frame flushing if jumbo frames used */
1577 skge_write16(hw, SK_REG(port,RX_MFF_CTRL1), MFF_ENA_FLUSH);
1579 /* enable timeout timers if normal frames */
1580 skge_write16(hw, B3_PA_CTRL,
1581 (port == 0) ? PA_ENA_TO_TX1 : PA_ENA_TO_TX2);
1585 static void genesis_stop(struct skge_port *skge)
1587 struct skge_hw *hw = skge->hw;
1588 int port = skge->port;
1591 genesis_reset(hw, port);
1593 /* Clear Tx packet arbiter timeout IRQ */
1594 skge_write16(hw, B3_PA_CTRL,
1595 port == 0 ? PA_CLR_TO_TX1 : PA_CLR_TO_TX2);
1598 * If the transfer sticks at the MAC the STOP command will not
1599 * terminate if we don't flush the XMAC's transmit FIFO !
1601 xm_write32(hw, port, XM_MODE,
1602 xm_read32(hw, port, XM_MODE)|XM_MD_FTF);
1606 skge_write16(hw, SK_REG(port, TX_MFF_CTRL1), MFF_SET_MAC_RST);
1608 /* For external PHYs there must be special handling */
1609 if (hw->phy_type != SK_PHY_XMAC) {
1610 reg = skge_read32(hw, B2_GP_IO);
1618 skge_write32(hw, B2_GP_IO, reg);
1619 skge_read32(hw, B2_GP_IO);
1622 xm_write16(hw, port, XM_MMU_CMD,
1623 xm_read16(hw, port, XM_MMU_CMD)
1624 & ~(XM_MMU_ENA_RX | XM_MMU_ENA_TX));
1626 xm_read16(hw, port, XM_MMU_CMD);
1630 static void genesis_get_stats(struct skge_port *skge, u64 *data)
1632 struct skge_hw *hw = skge->hw;
1633 int port = skge->port;
1635 unsigned long timeout = jiffies + HZ;
1637 xm_write16(hw, port,
1638 XM_STAT_CMD, XM_SC_SNP_TXC | XM_SC_SNP_RXC);
1640 /* wait for update to complete */
1641 while (xm_read16(hw, port, XM_STAT_CMD)
1642 & (XM_SC_SNP_TXC | XM_SC_SNP_RXC)) {
1643 if (time_after(jiffies, timeout))
1648 /* special case for 64 bit octet counter */
1649 data[0] = (u64) xm_read32(hw, port, XM_TXO_OK_HI) << 32
1650 | xm_read32(hw, port, XM_TXO_OK_LO);
1651 data[1] = (u64) xm_read32(hw, port, XM_RXO_OK_HI) << 32
1652 | xm_read32(hw, port, XM_RXO_OK_LO);
1654 for (i = 2; i < ARRAY_SIZE(skge_stats); i++)
1655 data[i] = xm_read32(hw, port, skge_stats[i].xmac_offset);
1658 static void genesis_mac_intr(struct skge_hw *hw, int port)
1660 struct skge_port *skge = netdev_priv(hw->dev[port]);
1661 u16 status = xm_read16(hw, port, XM_ISRC);
1663 if (netif_msg_intr(skge))
1664 printk(KERN_DEBUG PFX "%s: mac interrupt status 0x%x\n",
1665 skge->netdev->name, status);
1667 if (hw->phy_type == SK_PHY_XMAC &&
1668 (status & (XM_IS_INP_ASS | XM_IS_LIPA_RC)))
1669 xm_link_down(hw, port);
1671 if (status & XM_IS_TXF_UR) {
1672 xm_write32(hw, port, XM_MODE, XM_MD_FTF);
1673 ++skge->net_stats.tx_fifo_errors;
1675 if (status & XM_IS_RXF_OV) {
1676 xm_write32(hw, port, XM_MODE, XM_MD_FRF);
1677 ++skge->net_stats.rx_fifo_errors;
1681 static void genesis_link_up(struct skge_port *skge)
1683 struct skge_hw *hw = skge->hw;
1684 int port = skge->port;
1688 cmd = xm_read16(hw, port, XM_MMU_CMD);
1691 * enabling pause frame reception is required for 1000BT
1692 * because the XMAC is not reset if the link is going down
1694 if (skge->flow_status == FLOW_STAT_NONE ||
1695 skge->flow_status == FLOW_STAT_LOC_SEND)
1696 /* Disable Pause Frame Reception */
1697 cmd |= XM_MMU_IGN_PF;
1699 /* Enable Pause Frame Reception */
1700 cmd &= ~XM_MMU_IGN_PF;
1702 xm_write16(hw, port, XM_MMU_CMD, cmd);
1704 mode = xm_read32(hw, port, XM_MODE);
1705 if (skge->flow_status== FLOW_STAT_SYMMETRIC ||
1706 skge->flow_status == FLOW_STAT_LOC_SEND) {
1708 * Configure Pause Frame Generation
1709 * Use internal and external Pause Frame Generation.
1710 * Sending pause frames is edge triggered.
1711 * Send a Pause frame with the maximum pause time if
1712 * internal oder external FIFO full condition occurs.
1713 * Send a zero pause time frame to re-start transmission.
1715 /* XM_PAUSE_DA = '010000C28001' (default) */
1716 /* XM_MAC_PTIME = 0xffff (maximum) */
1717 /* remember this value is defined in big endian (!) */
1718 xm_write16(hw, port, XM_MAC_PTIME, 0xffff);
1720 mode |= XM_PAUSE_MODE;
1721 skge_write16(hw, SK_REG(port, RX_MFF_CTRL1), MFF_ENA_PAUSE);
1724 * disable pause frame generation is required for 1000BT
1725 * because the XMAC is not reset if the link is going down
1727 /* Disable Pause Mode in Mode Register */
1728 mode &= ~XM_PAUSE_MODE;
1730 skge_write16(hw, SK_REG(port, RX_MFF_CTRL1), MFF_DIS_PAUSE);
1733 xm_write32(hw, port, XM_MODE, mode);
1735 if (hw->phy_type != SK_PHY_XMAC)
1736 msk |= XM_IS_INP_ASS; /* disable GP0 interrupt bit */
1738 xm_write16(hw, port, XM_IMSK, msk);
1739 xm_read16(hw, port, XM_ISRC);
1741 /* get MMU Command Reg. */
1742 cmd = xm_read16(hw, port, XM_MMU_CMD);
1743 if (hw->phy_type != SK_PHY_XMAC && skge->duplex == DUPLEX_FULL)
1744 cmd |= XM_MMU_GMII_FD;
1747 * Workaround BCOM Errata (#10523) for all BCom Phys
1748 * Enable Power Management after link up
1750 if (hw->phy_type == SK_PHY_BCOM) {
1751 xm_phy_write(hw, port, PHY_BCOM_AUX_CTRL,
1752 xm_phy_read(hw, port, PHY_BCOM_AUX_CTRL)
1753 & ~PHY_B_AC_DIS_PM);
1754 xm_phy_write(hw, port, PHY_BCOM_INT_MASK, PHY_B_DEF_MSK);
1758 xm_write16(hw, port, XM_MMU_CMD,
1759 cmd | XM_MMU_ENA_RX | XM_MMU_ENA_TX);
1764 static inline void bcom_phy_intr(struct skge_port *skge)
1766 struct skge_hw *hw = skge->hw;
1767 int port = skge->port;
1770 isrc = xm_phy_read(hw, port, PHY_BCOM_INT_STAT);
1771 if (netif_msg_intr(skge))
1772 printk(KERN_DEBUG PFX "%s: phy interrupt status 0x%x\n",
1773 skge->netdev->name, isrc);
1775 if (isrc & PHY_B_IS_PSE)
1776 printk(KERN_ERR PFX "%s: uncorrectable pair swap error\n",
1777 hw->dev[port]->name);
1779 /* Workaround BCom Errata:
1780 * enable and disable loopback mode if "NO HCD" occurs.
1782 if (isrc & PHY_B_IS_NO_HDCL) {
1783 u16 ctrl = xm_phy_read(hw, port, PHY_BCOM_CTRL);
1784 xm_phy_write(hw, port, PHY_BCOM_CTRL,
1785 ctrl | PHY_CT_LOOP);
1786 xm_phy_write(hw, port, PHY_BCOM_CTRL,
1787 ctrl & ~PHY_CT_LOOP);
1790 if (isrc & (PHY_B_IS_AN_PR | PHY_B_IS_LST_CHANGE))
1791 bcom_check_link(hw, port);
1795 static int gm_phy_write(struct skge_hw *hw, int port, u16 reg, u16 val)
1799 gma_write16(hw, port, GM_SMI_DATA, val);
1800 gma_write16(hw, port, GM_SMI_CTRL,
1801 GM_SMI_CT_PHY_AD(hw->phy_addr) | GM_SMI_CT_REG_AD(reg));
1802 for (i = 0; i < PHY_RETRIES; i++) {
1805 if (!(gma_read16(hw, port, GM_SMI_CTRL) & GM_SMI_CT_BUSY))
1809 printk(KERN_WARNING PFX "%s: phy write timeout\n",
1810 hw->dev[port]->name);
1814 static int __gm_phy_read(struct skge_hw *hw, int port, u16 reg, u16 *val)
1818 gma_write16(hw, port, GM_SMI_CTRL,
1819 GM_SMI_CT_PHY_AD(hw->phy_addr)
1820 | GM_SMI_CT_REG_AD(reg) | GM_SMI_CT_OP_RD);
1822 for (i = 0; i < PHY_RETRIES; i++) {
1824 if (gma_read16(hw, port, GM_SMI_CTRL) & GM_SMI_CT_RD_VAL)
1830 *val = gma_read16(hw, port, GM_SMI_DATA);
1834 static u16 gm_phy_read(struct skge_hw *hw, int port, u16 reg)
1837 if (__gm_phy_read(hw, port, reg, &v))
1838 printk(KERN_WARNING PFX "%s: phy read timeout\n",
1839 hw->dev[port]->name);
1843 /* Marvell Phy Initialization */
1844 static void yukon_init(struct skge_hw *hw, int port)
1846 struct skge_port *skge = netdev_priv(hw->dev[port]);
1847 u16 ctrl, ct1000, adv;
1849 if (skge->autoneg == AUTONEG_ENABLE) {
1850 u16 ectrl = gm_phy_read(hw, port, PHY_MARV_EXT_CTRL);
1852 ectrl &= ~(PHY_M_EC_M_DSC_MSK | PHY_M_EC_S_DSC_MSK |
1853 PHY_M_EC_MAC_S_MSK);
1854 ectrl |= PHY_M_EC_MAC_S(MAC_TX_CLK_25_MHZ);
1856 ectrl |= PHY_M_EC_M_DSC(0) | PHY_M_EC_S_DSC(1);
1858 gm_phy_write(hw, port, PHY_MARV_EXT_CTRL, ectrl);
1861 ctrl = gm_phy_read(hw, port, PHY_MARV_CTRL);
1862 if (skge->autoneg == AUTONEG_DISABLE)
1863 ctrl &= ~PHY_CT_ANE;
1865 ctrl |= PHY_CT_RESET;
1866 gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
1872 if (skge->autoneg == AUTONEG_ENABLE) {
1874 if (skge->advertising & ADVERTISED_1000baseT_Full)
1875 ct1000 |= PHY_M_1000C_AFD;
1876 if (skge->advertising & ADVERTISED_1000baseT_Half)
1877 ct1000 |= PHY_M_1000C_AHD;
1878 if (skge->advertising & ADVERTISED_100baseT_Full)
1879 adv |= PHY_M_AN_100_FD;
1880 if (skge->advertising & ADVERTISED_100baseT_Half)
1881 adv |= PHY_M_AN_100_HD;
1882 if (skge->advertising & ADVERTISED_10baseT_Full)
1883 adv |= PHY_M_AN_10_FD;
1884 if (skge->advertising & ADVERTISED_10baseT_Half)
1885 adv |= PHY_M_AN_10_HD;
1887 /* Set Flow-control capabilities */
1888 adv |= phy_pause_map[skge->flow_control];
1890 if (skge->advertising & ADVERTISED_1000baseT_Full)
1891 adv |= PHY_M_AN_1000X_AFD;
1892 if (skge->advertising & ADVERTISED_1000baseT_Half)
1893 adv |= PHY_M_AN_1000X_AHD;
1895 adv |= fiber_pause_map[skge->flow_control];
1898 /* Restart Auto-negotiation */
1899 ctrl |= PHY_CT_ANE | PHY_CT_RE_CFG;
1901 /* forced speed/duplex settings */
1902 ct1000 = PHY_M_1000C_MSE;
1904 if (skge->duplex == DUPLEX_FULL)
1905 ctrl |= PHY_CT_DUP_MD;
1907 switch (skge->speed) {
1909 ctrl |= PHY_CT_SP1000;
1912 ctrl |= PHY_CT_SP100;
1916 ctrl |= PHY_CT_RESET;
1919 gm_phy_write(hw, port, PHY_MARV_1000T_CTRL, ct1000);
1921 gm_phy_write(hw, port, PHY_MARV_AUNE_ADV, adv);
1922 gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
1924 /* Enable phy interrupt on autonegotiation complete (or link up) */
1925 if (skge->autoneg == AUTONEG_ENABLE)
1926 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_IS_AN_MSK);
1928 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_IS_DEF_MSK);
1931 static void yukon_reset(struct skge_hw *hw, int port)
1933 gm_phy_write(hw, port, PHY_MARV_INT_MASK, 0);/* disable PHY IRQs */
1934 gma_write16(hw, port, GM_MC_ADDR_H1, 0); /* clear MC hash */
1935 gma_write16(hw, port, GM_MC_ADDR_H2, 0);
1936 gma_write16(hw, port, GM_MC_ADDR_H3, 0);
1937 gma_write16(hw, port, GM_MC_ADDR_H4, 0);
1939 gma_write16(hw, port, GM_RX_CTRL,
1940 gma_read16(hw, port, GM_RX_CTRL)
1941 | GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA);
1944 /* Apparently, early versions of Yukon-Lite had wrong chip_id? */
1945 static int is_yukon_lite_a0(struct skge_hw *hw)
1950 if (hw->chip_id != CHIP_ID_YUKON)
1953 reg = skge_read32(hw, B2_FAR);
1954 skge_write8(hw, B2_FAR + 3, 0xff);
1955 ret = (skge_read8(hw, B2_FAR + 3) != 0);
1956 skge_write32(hw, B2_FAR, reg);
1960 static void yukon_mac_init(struct skge_hw *hw, int port)
1962 struct skge_port *skge = netdev_priv(hw->dev[port]);
1965 const u8 *addr = hw->dev[port]->dev_addr;
1967 /* WA code for COMA mode -- set PHY reset */
1968 if (hw->chip_id == CHIP_ID_YUKON_LITE &&
1969 hw->chip_rev >= CHIP_REV_YU_LITE_A3) {
1970 reg = skge_read32(hw, B2_GP_IO);
1971 reg |= GP_DIR_9 | GP_IO_9;
1972 skge_write32(hw, B2_GP_IO, reg);
1976 skge_write32(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET);
1977 skge_write32(hw, SK_REG(port, GMAC_CTRL), GMC_RST_SET);
1979 /* WA code for COMA mode -- clear PHY reset */
1980 if (hw->chip_id == CHIP_ID_YUKON_LITE &&
1981 hw->chip_rev >= CHIP_REV_YU_LITE_A3) {
1982 reg = skge_read32(hw, B2_GP_IO);
1985 skge_write32(hw, B2_GP_IO, reg);
1988 /* Set hardware config mode */
1989 reg = GPC_INT_POL_HI | GPC_DIS_FC | GPC_DIS_SLEEP |
1990 GPC_ENA_XC | GPC_ANEG_ADV_ALL_M | GPC_ENA_PAUSE;
1991 reg |= hw->copper ? GPC_HWCFG_GMII_COP : GPC_HWCFG_GMII_FIB;
1993 /* Clear GMC reset */
1994 skge_write32(hw, SK_REG(port, GPHY_CTRL), reg | GPC_RST_SET);
1995 skge_write32(hw, SK_REG(port, GPHY_CTRL), reg | GPC_RST_CLR);
1996 skge_write32(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON | GMC_RST_CLR);
1998 if (skge->autoneg == AUTONEG_DISABLE) {
1999 reg = GM_GPCR_AU_ALL_DIS;
2000 gma_write16(hw, port, GM_GP_CTRL,
2001 gma_read16(hw, port, GM_GP_CTRL) | reg);
2003 switch (skge->speed) {
2005 reg &= ~GM_GPCR_SPEED_100;
2006 reg |= GM_GPCR_SPEED_1000;
2009 reg &= ~GM_GPCR_SPEED_1000;
2010 reg |= GM_GPCR_SPEED_100;
2013 reg &= ~(GM_GPCR_SPEED_1000 | GM_GPCR_SPEED_100);
2017 if (skge->duplex == DUPLEX_FULL)
2018 reg |= GM_GPCR_DUP_FULL;
2020 reg = GM_GPCR_SPEED_1000 | GM_GPCR_SPEED_100 | GM_GPCR_DUP_FULL;
2022 switch (skge->flow_control) {
2023 case FLOW_MODE_NONE:
2024 skge_write32(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
2025 reg |= GM_GPCR_FC_TX_DIS | GM_GPCR_FC_RX_DIS | GM_GPCR_AU_FCT_DIS;
2027 case FLOW_MODE_LOC_SEND:
2028 /* disable Rx flow-control */
2029 reg |= GM_GPCR_FC_RX_DIS | GM_GPCR_AU_FCT_DIS;
2031 case FLOW_MODE_SYMMETRIC:
2032 case FLOW_MODE_SYM_OR_REM:
2033 /* enable Tx & Rx flow-control */
2037 gma_write16(hw, port, GM_GP_CTRL, reg);
2038 skge_read16(hw, SK_REG(port, GMAC_IRQ_SRC));
2040 yukon_init(hw, port);
2043 reg = gma_read16(hw, port, GM_PHY_ADDR);
2044 gma_write16(hw, port, GM_PHY_ADDR, reg | GM_PAR_MIB_CLR);
2046 for (i = 0; i < GM_MIB_CNT_SIZE; i++)
2047 gma_read16(hw, port, GM_MIB_CNT_BASE + 8*i);
2048 gma_write16(hw, port, GM_PHY_ADDR, reg);
2050 /* transmit control */
2051 gma_write16(hw, port, GM_TX_CTRL, TX_COL_THR(TX_COL_DEF));
2053 /* receive control reg: unicast + multicast + no FCS */
2054 gma_write16(hw, port, GM_RX_CTRL,
2055 GM_RXCR_UCF_ENA | GM_RXCR_CRC_DIS | GM_RXCR_MCF_ENA);
2057 /* transmit flow control */
2058 gma_write16(hw, port, GM_TX_FLOW_CTRL, 0xffff);
2060 /* transmit parameter */
2061 gma_write16(hw, port, GM_TX_PARAM,
2062 TX_JAM_LEN_VAL(TX_JAM_LEN_DEF) |
2063 TX_JAM_IPG_VAL(TX_JAM_IPG_DEF) |
2064 TX_IPG_JAM_DATA(TX_IPG_JAM_DEF));
2066 /* serial mode register */
2067 reg = GM_SMOD_VLAN_ENA | IPG_DATA_VAL(IPG_DATA_DEF);
2068 if (hw->dev[port]->mtu > 1500)
2069 reg |= GM_SMOD_JUMBO_ENA;
2071 gma_write16(hw, port, GM_SERIAL_MODE, reg);
2073 /* physical address: used for pause frames */
2074 gma_set_addr(hw, port, GM_SRC_ADDR_1L, addr);
2075 /* virtual address for data */
2076 gma_set_addr(hw, port, GM_SRC_ADDR_2L, addr);
2078 /* enable interrupt mask for counter overflows */
2079 gma_write16(hw, port, GM_TX_IRQ_MSK, 0);
2080 gma_write16(hw, port, GM_RX_IRQ_MSK, 0);
2081 gma_write16(hw, port, GM_TR_IRQ_MSK, 0);
2083 /* Initialize Mac Fifo */
2085 /* Configure Rx MAC FIFO */
2086 skge_write16(hw, SK_REG(port, RX_GMF_FL_MSK), RX_FF_FL_DEF_MSK);
2087 reg = GMF_OPER_ON | GMF_RX_F_FL_ON;
2089 /* disable Rx GMAC FIFO Flush for YUKON-Lite Rev. A0 only */
2090 if (is_yukon_lite_a0(hw))
2091 reg &= ~GMF_RX_F_FL_ON;
2093 skge_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_CLR);
2094 skge_write16(hw, SK_REG(port, RX_GMF_CTRL_T), reg);
2096 * because Pause Packet Truncation in GMAC is not working
2097 * we have to increase the Flush Threshold to 64 bytes
2098 * in order to flush pause packets in Rx FIFO on Yukon-1
2100 skge_write16(hw, SK_REG(port, RX_GMF_FL_THR), RX_GMF_FL_THR_DEF+1);
2102 /* Configure Tx MAC FIFO */
2103 skge_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_CLR);
2104 skge_write16(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_OPER_ON);
2107 /* Go into power down mode */
2108 static void yukon_suspend(struct skge_hw *hw, int port)
2112 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
2113 ctrl |= PHY_M_PC_POL_R_DIS;
2114 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
2116 ctrl = gm_phy_read(hw, port, PHY_MARV_CTRL);
2117 ctrl |= PHY_CT_RESET;
2118 gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
2120 /* switch IEEE compatible power down mode on */
2121 ctrl = gm_phy_read(hw, port, PHY_MARV_CTRL);
2122 ctrl |= PHY_CT_PDOWN;
2123 gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
2126 static void yukon_stop(struct skge_port *skge)
2128 struct skge_hw *hw = skge->hw;
2129 int port = skge->port;
2131 skge_write8(hw, SK_REG(port, GMAC_IRQ_MSK), 0);
2132 yukon_reset(hw, port);
2134 gma_write16(hw, port, GM_GP_CTRL,
2135 gma_read16(hw, port, GM_GP_CTRL)
2136 & ~(GM_GPCR_TX_ENA|GM_GPCR_RX_ENA));
2137 gma_read16(hw, port, GM_GP_CTRL);
2139 yukon_suspend(hw, port);
2141 /* set GPHY Control reset */
2142 skge_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET);
2143 skge_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_SET);
2146 static void yukon_get_stats(struct skge_port *skge, u64 *data)
2148 struct skge_hw *hw = skge->hw;
2149 int port = skge->port;
2152 data[0] = (u64) gma_read32(hw, port, GM_TXO_OK_HI) << 32
2153 | gma_read32(hw, port, GM_TXO_OK_LO);
2154 data[1] = (u64) gma_read32(hw, port, GM_RXO_OK_HI) << 32
2155 | gma_read32(hw, port, GM_RXO_OK_LO);
2157 for (i = 2; i < ARRAY_SIZE(skge_stats); i++)
2158 data[i] = gma_read32(hw, port,
2159 skge_stats[i].gma_offset);
2162 static void yukon_mac_intr(struct skge_hw *hw, int port)
2164 struct net_device *dev = hw->dev[port];
2165 struct skge_port *skge = netdev_priv(dev);
2166 u8 status = skge_read8(hw, SK_REG(port, GMAC_IRQ_SRC));
2168 if (netif_msg_intr(skge))
2169 printk(KERN_DEBUG PFX "%s: mac interrupt status 0x%x\n",
2172 if (status & GM_IS_RX_FF_OR) {
2173 ++skge->net_stats.rx_fifo_errors;
2174 skge_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_CLI_RX_FO);
2177 if (status & GM_IS_TX_FF_UR) {
2178 ++skge->net_stats.tx_fifo_errors;
2179 skge_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_CLI_TX_FU);
2184 static u16 yukon_speed(const struct skge_hw *hw, u16 aux)
2186 switch (aux & PHY_M_PS_SPEED_MSK) {
2187 case PHY_M_PS_SPEED_1000:
2189 case PHY_M_PS_SPEED_100:
2196 static void yukon_link_up(struct skge_port *skge)
2198 struct skge_hw *hw = skge->hw;
2199 int port = skge->port;
2202 /* Enable Transmit FIFO Underrun */
2203 skge_write8(hw, SK_REG(port, GMAC_IRQ_MSK), GMAC_DEF_MSK);
2205 reg = gma_read16(hw, port, GM_GP_CTRL);
2206 if (skge->duplex == DUPLEX_FULL || skge->autoneg == AUTONEG_ENABLE)
2207 reg |= GM_GPCR_DUP_FULL;
2210 reg |= GM_GPCR_RX_ENA | GM_GPCR_TX_ENA;
2211 gma_write16(hw, port, GM_GP_CTRL, reg);
2213 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_IS_DEF_MSK);
2217 static void yukon_link_down(struct skge_port *skge)
2219 struct skge_hw *hw = skge->hw;
2220 int port = skge->port;
2223 ctrl = gma_read16(hw, port, GM_GP_CTRL);
2224 ctrl &= ~(GM_GPCR_RX_ENA | GM_GPCR_TX_ENA);
2225 gma_write16(hw, port, GM_GP_CTRL, ctrl);
2227 if (skge->flow_status == FLOW_STAT_REM_SEND) {
2228 ctrl = gm_phy_read(hw, port, PHY_MARV_AUNE_ADV);
2229 ctrl |= PHY_M_AN_ASP;
2230 /* restore Asymmetric Pause bit */
2231 gm_phy_write(hw, port, PHY_MARV_AUNE_ADV, ctrl);
2234 skge_link_down(skge);
2236 yukon_init(hw, port);
2239 static void yukon_phy_intr(struct skge_port *skge)
2241 struct skge_hw *hw = skge->hw;
2242 int port = skge->port;
2243 const char *reason = NULL;
2244 u16 istatus, phystat;
2246 istatus = gm_phy_read(hw, port, PHY_MARV_INT_STAT);
2247 phystat = gm_phy_read(hw, port, PHY_MARV_PHY_STAT);
2249 if (netif_msg_intr(skge))
2250 printk(KERN_DEBUG PFX "%s: phy interrupt status 0x%x 0x%x\n",
2251 skge->netdev->name, istatus, phystat);
2253 if (istatus & PHY_M_IS_AN_COMPL) {
2254 if (gm_phy_read(hw, port, PHY_MARV_AUNE_LP)
2256 reason = "remote fault";
2260 if (gm_phy_read(hw, port, PHY_MARV_1000T_STAT) & PHY_B_1000S_MSF) {
2261 reason = "master/slave fault";
2265 if (!(phystat & PHY_M_PS_SPDUP_RES)) {
2266 reason = "speed/duplex";
2270 skge->duplex = (phystat & PHY_M_PS_FULL_DUP)
2271 ? DUPLEX_FULL : DUPLEX_HALF;
2272 skge->speed = yukon_speed(hw, phystat);
2274 /* We are using IEEE 802.3z/D5.0 Table 37-4 */
2275 switch (phystat & PHY_M_PS_PAUSE_MSK) {
2276 case PHY_M_PS_PAUSE_MSK:
2277 skge->flow_status = FLOW_STAT_SYMMETRIC;
2279 case PHY_M_PS_RX_P_EN:
2280 skge->flow_status = FLOW_STAT_REM_SEND;
2282 case PHY_M_PS_TX_P_EN:
2283 skge->flow_status = FLOW_STAT_LOC_SEND;
2286 skge->flow_status = FLOW_STAT_NONE;
2289 if (skge->flow_status == FLOW_STAT_NONE ||
2290 (skge->speed < SPEED_1000 && skge->duplex == DUPLEX_HALF))
2291 skge_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
2293 skge_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON);
2294 yukon_link_up(skge);
2298 if (istatus & PHY_M_IS_LSP_CHANGE)
2299 skge->speed = yukon_speed(hw, phystat);
2301 if (istatus & PHY_M_IS_DUP_CHANGE)
2302 skge->duplex = (phystat & PHY_M_PS_FULL_DUP) ? DUPLEX_FULL : DUPLEX_HALF;
2303 if (istatus & PHY_M_IS_LST_CHANGE) {
2304 if (phystat & PHY_M_PS_LINK_UP)
2305 yukon_link_up(skge);
2307 yukon_link_down(skge);
2311 printk(KERN_ERR PFX "%s: autonegotiation failed (%s)\n",
2312 skge->netdev->name, reason);
2314 /* XXX restart autonegotiation? */
2317 static void skge_phy_reset(struct skge_port *skge)
2319 struct skge_hw *hw = skge->hw;
2320 int port = skge->port;
2321 struct net_device *dev = hw->dev[port];
2323 netif_stop_queue(skge->netdev);
2324 netif_carrier_off(skge->netdev);
2326 spin_lock_bh(&hw->phy_lock);
2327 if (hw->chip_id == CHIP_ID_GENESIS) {
2328 genesis_reset(hw, port);
2329 genesis_mac_init(hw, port);
2331 yukon_reset(hw, port);
2332 yukon_init(hw, port);
2334 spin_unlock_bh(&hw->phy_lock);
2336 dev->set_multicast_list(dev);
2339 /* Basic MII support */
2340 static int skge_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
2342 struct mii_ioctl_data *data = if_mii(ifr);
2343 struct skge_port *skge = netdev_priv(dev);
2344 struct skge_hw *hw = skge->hw;
2345 int err = -EOPNOTSUPP;
2347 if (!netif_running(dev))
2348 return -ENODEV; /* Phy still in reset */
2352 data->phy_id = hw->phy_addr;
2357 spin_lock_bh(&hw->phy_lock);
2358 if (hw->chip_id == CHIP_ID_GENESIS)
2359 err = __xm_phy_read(hw, skge->port, data->reg_num & 0x1f, &val);
2361 err = __gm_phy_read(hw, skge->port, data->reg_num & 0x1f, &val);
2362 spin_unlock_bh(&hw->phy_lock);
2363 data->val_out = val;
2368 if (!capable(CAP_NET_ADMIN))
2371 spin_lock_bh(&hw->phy_lock);
2372 if (hw->chip_id == CHIP_ID_GENESIS)
2373 err = xm_phy_write(hw, skge->port, data->reg_num & 0x1f,
2376 err = gm_phy_write(hw, skge->port, data->reg_num & 0x1f,
2378 spin_unlock_bh(&hw->phy_lock);
2384 static void skge_ramset(struct skge_hw *hw, u16 q, u32 start, size_t len)
2390 end = start + len - 1;
2392 skge_write8(hw, RB_ADDR(q, RB_CTRL), RB_RST_CLR);
2393 skge_write32(hw, RB_ADDR(q, RB_START), start);
2394 skge_write32(hw, RB_ADDR(q, RB_WP), start);
2395 skge_write32(hw, RB_ADDR(q, RB_RP), start);
2396 skge_write32(hw, RB_ADDR(q, RB_END), end);
2398 if (q == Q_R1 || q == Q_R2) {
2399 /* Set thresholds on receive queue's */
2400 skge_write32(hw, RB_ADDR(q, RB_RX_UTPP),
2402 skge_write32(hw, RB_ADDR(q, RB_RX_LTPP),
2405 /* Enable store & forward on Tx queue's because
2406 * Tx FIFO is only 4K on Genesis and 1K on Yukon
2408 skge_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_STFWD);
2411 skge_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_OP_MD);
2414 /* Setup Bus Memory Interface */
2415 static void skge_qset(struct skge_port *skge, u16 q,
2416 const struct skge_element *e)
2418 struct skge_hw *hw = skge->hw;
2419 u32 watermark = 0x600;
2420 u64 base = skge->dma + (e->desc - skge->mem);
2422 /* optimization to reduce window on 32bit/33mhz */
2423 if ((skge_read16(hw, B0_CTST) & (CS_BUS_CLOCK | CS_BUS_SLOT_SZ)) == 0)
2426 skge_write32(hw, Q_ADDR(q, Q_CSR), CSR_CLR_RESET);
2427 skge_write32(hw, Q_ADDR(q, Q_F), watermark);
2428 skge_write32(hw, Q_ADDR(q, Q_DA_H), (u32)(base >> 32));
2429 skge_write32(hw, Q_ADDR(q, Q_DA_L), (u32)base);
2432 static int skge_up(struct net_device *dev)
2434 struct skge_port *skge = netdev_priv(dev);
2435 struct skge_hw *hw = skge->hw;
2436 int port = skge->port;
2437 u32 chunk, ram_addr;
2438 size_t rx_size, tx_size;
2441 if (!is_valid_ether_addr(dev->dev_addr))
2444 if (netif_msg_ifup(skge))
2445 printk(KERN_INFO PFX "%s: enabling interface\n", dev->name);
2447 if (dev->mtu > RX_BUF_SIZE)
2448 skge->rx_buf_size = dev->mtu + ETH_HLEN;
2450 skge->rx_buf_size = RX_BUF_SIZE;
2453 rx_size = skge->rx_ring.count * sizeof(struct skge_rx_desc);
2454 tx_size = skge->tx_ring.count * sizeof(struct skge_tx_desc);
2455 skge->mem_size = tx_size + rx_size;
2456 skge->mem = pci_alloc_consistent(hw->pdev, skge->mem_size, &skge->dma);
2460 BUG_ON(skge->dma & 7);
2462 if ((u64)skge->dma >> 32 != ((u64) skge->dma + skge->mem_size) >> 32) {
2463 dev_err(&hw->pdev->dev, "pci_alloc_consistent region crosses 4G boundary\n");
2468 memset(skge->mem, 0, skge->mem_size);
2470 err = skge_ring_alloc(&skge->rx_ring, skge->mem, skge->dma);
2474 err = skge_rx_fill(dev);
2478 err = skge_ring_alloc(&skge->tx_ring, skge->mem + rx_size,
2479 skge->dma + rx_size);
2483 /* Initialize MAC */
2484 spin_lock_bh(&hw->phy_lock);
2485 if (hw->chip_id == CHIP_ID_GENESIS)
2486 genesis_mac_init(hw, port);
2488 yukon_mac_init(hw, port);
2489 spin_unlock_bh(&hw->phy_lock);
2491 /* Configure RAMbuffers */
2492 chunk = hw->ram_size / ((hw->ports + 1)*2);
2493 ram_addr = hw->ram_offset + 2 * chunk * port;
2495 skge_ramset(hw, rxqaddr[port], ram_addr, chunk);
2496 skge_qset(skge, rxqaddr[port], skge->rx_ring.to_clean);
2498 BUG_ON(skge->tx_ring.to_use != skge->tx_ring.to_clean);
2499 skge_ramset(hw, txqaddr[port], ram_addr+chunk, chunk);
2500 skge_qset(skge, txqaddr[port], skge->tx_ring.to_use);
2502 /* Start receiver BMU */
2504 skge_write8(hw, Q_ADDR(rxqaddr[port], Q_CSR), CSR_START | CSR_IRQ_CL_F);
2505 skge_led(skge, LED_MODE_ON);
2507 spin_lock_irq(&hw->hw_lock);
2508 hw->intr_mask |= portmask[port];
2509 skge_write32(hw, B0_IMSK, hw->intr_mask);
2510 spin_unlock_irq(&hw->hw_lock);
2512 netif_poll_enable(dev);
2516 skge_rx_clean(skge);
2517 kfree(skge->rx_ring.start);
2519 pci_free_consistent(hw->pdev, skge->mem_size, skge->mem, skge->dma);
2525 static int skge_down(struct net_device *dev)
2527 struct skge_port *skge = netdev_priv(dev);
2528 struct skge_hw *hw = skge->hw;
2529 int port = skge->port;
2531 if (skge->mem == NULL)
2534 if (netif_msg_ifdown(skge))
2535 printk(KERN_INFO PFX "%s: disabling interface\n", dev->name);
2537 netif_stop_queue(dev);
2538 if (hw->chip_id == CHIP_ID_GENESIS && hw->phy_type == SK_PHY_XMAC)
2539 del_timer_sync(&skge->link_timer);
2541 netif_poll_disable(dev);
2543 spin_lock_irq(&hw->hw_lock);
2544 hw->intr_mask &= ~portmask[port];
2545 skge_write32(hw, B0_IMSK, hw->intr_mask);
2546 spin_unlock_irq(&hw->hw_lock);
2548 skge_write8(skge->hw, SK_REG(skge->port, LNK_LED_REG), LED_OFF);
2549 if (hw->chip_id == CHIP_ID_GENESIS)
2554 /* Stop transmitter */
2555 skge_write8(hw, Q_ADDR(txqaddr[port], Q_CSR), CSR_STOP);
2556 skge_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL),
2557 RB_RST_SET|RB_DIS_OP_MD);
2560 /* Disable Force Sync bit and Enable Alloc bit */
2561 skge_write8(hw, SK_REG(port, TXA_CTRL),
2562 TXA_DIS_FSYNC | TXA_DIS_ALLOC | TXA_STOP_RC);
2564 /* Stop Interval Timer and Limit Counter of Tx Arbiter */
2565 skge_write32(hw, SK_REG(port, TXA_ITI_INI), 0L);
2566 skge_write32(hw, SK_REG(port, TXA_LIM_INI), 0L);
2568 /* Reset PCI FIFO */
2569 skge_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), CSR_SET_RESET);
2570 skge_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL), RB_RST_SET);
2572 /* Reset the RAM Buffer async Tx queue */
2573 skge_write8(hw, RB_ADDR(port == 0 ? Q_XA1 : Q_XA2, RB_CTRL), RB_RST_SET);
2575 skge_write8(hw, Q_ADDR(rxqaddr[port], Q_CSR), CSR_STOP);
2576 skge_write32(hw, RB_ADDR(port ? Q_R2 : Q_R1, RB_CTRL),
2577 RB_RST_SET|RB_DIS_OP_MD);
2578 skge_write32(hw, Q_ADDR(rxqaddr[port], Q_CSR), CSR_SET_RESET);
2580 if (hw->chip_id == CHIP_ID_GENESIS) {
2581 skge_write8(hw, SK_REG(port, TX_MFF_CTRL2), MFF_RST_SET);
2582 skge_write8(hw, SK_REG(port, RX_MFF_CTRL2), MFF_RST_SET);
2584 skge_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_SET);
2585 skge_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_SET);
2588 skge_led(skge, LED_MODE_OFF);
2590 netif_tx_lock_bh(dev);
2592 netif_tx_unlock_bh(dev);
2594 skge_rx_clean(skge);
2596 kfree(skge->rx_ring.start);
2597 kfree(skge->tx_ring.start);
2598 pci_free_consistent(hw->pdev, skge->mem_size, skge->mem, skge->dma);
2603 static inline int skge_avail(const struct skge_ring *ring)
2605 return ((ring->to_clean > ring->to_use) ? 0 : ring->count)
2606 + (ring->to_clean - ring->to_use) - 1;
2609 static int skge_xmit_frame(struct sk_buff *skb, struct net_device *dev)
2611 struct skge_port *skge = netdev_priv(dev);
2612 struct skge_hw *hw = skge->hw;
2613 struct skge_element *e;
2614 struct skge_tx_desc *td;
2619 if (skb_padto(skb, ETH_ZLEN))
2620 return NETDEV_TX_OK;
2622 if (unlikely(skge_avail(&skge->tx_ring) < skb_shinfo(skb)->nr_frags + 1))
2623 return NETDEV_TX_BUSY;
2625 e = skge->tx_ring.to_use;
2627 BUG_ON(td->control & BMU_OWN);
2629 len = skb_headlen(skb);
2630 map = pci_map_single(hw->pdev, skb->data, len, PCI_DMA_TODEVICE);
2631 pci_unmap_addr_set(e, mapaddr, map);
2632 pci_unmap_len_set(e, maplen, len);
2635 td->dma_hi = map >> 32;
2637 if (skb->ip_summed == CHECKSUM_PARTIAL) {
2638 int offset = skb->h.raw - skb->data;
2640 /* This seems backwards, but it is what the sk98lin
2641 * does. Looks like hardware is wrong?
2643 if (skb->h.ipiph->protocol == IPPROTO_UDP
2644 && hw->chip_rev == 0 && hw->chip_id == CHIP_ID_YUKON)
2645 control = BMU_TCP_CHECK;
2647 control = BMU_UDP_CHECK;
2650 td->csum_start = offset;
2651 td->csum_write = offset + skb->csum_offset;
2653 control = BMU_CHECK;
2655 if (!skb_shinfo(skb)->nr_frags) /* single buffer i.e. no fragments */
2656 control |= BMU_EOF| BMU_IRQ_EOF;
2658 struct skge_tx_desc *tf = td;
2660 control |= BMU_STFWD;
2661 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
2662 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
2664 map = pci_map_page(hw->pdev, frag->page, frag->page_offset,
2665 frag->size, PCI_DMA_TODEVICE);
2670 BUG_ON(tf->control & BMU_OWN);
2673 tf->dma_hi = (u64) map >> 32;
2674 pci_unmap_addr_set(e, mapaddr, map);
2675 pci_unmap_len_set(e, maplen, frag->size);
2677 tf->control = BMU_OWN | BMU_SW | control | frag->size;
2679 tf->control |= BMU_EOF | BMU_IRQ_EOF;
2681 /* Make sure all the descriptors written */
2683 td->control = BMU_OWN | BMU_SW | BMU_STF | control | len;
2686 skge_write8(hw, Q_ADDR(txqaddr[skge->port], Q_CSR), CSR_START);
2688 if (unlikely(netif_msg_tx_queued(skge)))
2689 printk(KERN_DEBUG "%s: tx queued, slot %td, len %d\n",
2690 dev->name, e - skge->tx_ring.start, skb->len);
2692 skge->tx_ring.to_use = e->next;
2693 if (skge_avail(&skge->tx_ring) <= TX_LOW_WATER) {
2694 pr_debug("%s: transmit queue full\n", dev->name);
2695 netif_stop_queue(dev);
2698 dev->trans_start = jiffies;
2700 return NETDEV_TX_OK;
2704 /* Free resources associated with this reing element */
2705 static void skge_tx_free(struct skge_port *skge, struct skge_element *e,
2708 struct pci_dev *pdev = skge->hw->pdev;
2712 /* skb header vs. fragment */
2713 if (control & BMU_STF)
2714 pci_unmap_single(pdev, pci_unmap_addr(e, mapaddr),
2715 pci_unmap_len(e, maplen),
2718 pci_unmap_page(pdev, pci_unmap_addr(e, mapaddr),
2719 pci_unmap_len(e, maplen),
2722 if (control & BMU_EOF) {
2723 if (unlikely(netif_msg_tx_done(skge)))
2724 printk(KERN_DEBUG PFX "%s: tx done slot %td\n",
2725 skge->netdev->name, e - skge->tx_ring.start);
2727 dev_kfree_skb(e->skb);
2732 /* Free all buffers in transmit ring */
2733 static void skge_tx_clean(struct net_device *dev)
2735 struct skge_port *skge = netdev_priv(dev);
2736 struct skge_element *e;
2738 for (e = skge->tx_ring.to_clean; e != skge->tx_ring.to_use; e = e->next) {
2739 struct skge_tx_desc *td = e->desc;
2740 skge_tx_free(skge, e, td->control);
2744 skge->tx_ring.to_clean = e;
2745 netif_wake_queue(dev);
2748 static void skge_tx_timeout(struct net_device *dev)
2750 struct skge_port *skge = netdev_priv(dev);
2752 if (netif_msg_timer(skge))
2753 printk(KERN_DEBUG PFX "%s: tx timeout\n", dev->name);
2755 skge_write8(skge->hw, Q_ADDR(txqaddr[skge->port], Q_CSR), CSR_STOP);
2759 static int skge_change_mtu(struct net_device *dev, int new_mtu)
2763 if (new_mtu < ETH_ZLEN || new_mtu > ETH_JUMBO_MTU)
2766 if (!netif_running(dev)) {
2782 static const u8 pause_mc_addr[ETH_ALEN] = { 0x1, 0x80, 0xc2, 0x0, 0x0, 0x1 };
2784 static void genesis_add_filter(u8 filter[8], const u8 *addr)
2788 crc = ether_crc_le(ETH_ALEN, addr);
2790 filter[bit/8] |= 1 << (bit%8);
2793 static void genesis_set_multicast(struct net_device *dev)
2795 struct skge_port *skge = netdev_priv(dev);
2796 struct skge_hw *hw = skge->hw;
2797 int port = skge->port;
2798 int i, count = dev->mc_count;
2799 struct dev_mc_list *list = dev->mc_list;
2803 mode = xm_read32(hw, port, XM_MODE);
2804 mode |= XM_MD_ENA_HASH;
2805 if (dev->flags & IFF_PROMISC)
2806 mode |= XM_MD_ENA_PROM;
2808 mode &= ~XM_MD_ENA_PROM;
2810 if (dev->flags & IFF_ALLMULTI)
2811 memset(filter, 0xff, sizeof(filter));
2813 memset(filter, 0, sizeof(filter));
2815 if (skge->flow_status == FLOW_STAT_REM_SEND
2816 || skge->flow_status == FLOW_STAT_SYMMETRIC)
2817 genesis_add_filter(filter, pause_mc_addr);
2819 for (i = 0; list && i < count; i++, list = list->next)
2820 genesis_add_filter(filter, list->dmi_addr);
2823 xm_write32(hw, port, XM_MODE, mode);
2824 xm_outhash(hw, port, XM_HSM, filter);
2827 static void yukon_add_filter(u8 filter[8], const u8 *addr)
2829 u32 bit = ether_crc(ETH_ALEN, addr) & 0x3f;
2830 filter[bit/8] |= 1 << (bit%8);
2833 static void yukon_set_multicast(struct net_device *dev)
2835 struct skge_port *skge = netdev_priv(dev);
2836 struct skge_hw *hw = skge->hw;
2837 int port = skge->port;
2838 struct dev_mc_list *list = dev->mc_list;
2839 int rx_pause = (skge->flow_status == FLOW_STAT_REM_SEND
2840 || skge->flow_status == FLOW_STAT_SYMMETRIC);
2844 memset(filter, 0, sizeof(filter));
2846 reg = gma_read16(hw, port, GM_RX_CTRL);
2847 reg |= GM_RXCR_UCF_ENA;
2849 if (dev->flags & IFF_PROMISC) /* promiscuous */
2850 reg &= ~(GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA);
2851 else if (dev->flags & IFF_ALLMULTI) /* all multicast */
2852 memset(filter, 0xff, sizeof(filter));
2853 else if (dev->mc_count == 0 && !rx_pause)/* no multicast */
2854 reg &= ~GM_RXCR_MCF_ENA;
2857 reg |= GM_RXCR_MCF_ENA;
2860 yukon_add_filter(filter, pause_mc_addr);
2862 for (i = 0; list && i < dev->mc_count; i++, list = list->next)
2863 yukon_add_filter(filter, list->dmi_addr);
2867 gma_write16(hw, port, GM_MC_ADDR_H1,
2868 (u16)filter[0] | ((u16)filter[1] << 8));
2869 gma_write16(hw, port, GM_MC_ADDR_H2,
2870 (u16)filter[2] | ((u16)filter[3] << 8));
2871 gma_write16(hw, port, GM_MC_ADDR_H3,
2872 (u16)filter[4] | ((u16)filter[5] << 8));
2873 gma_write16(hw, port, GM_MC_ADDR_H4,
2874 (u16)filter[6] | ((u16)filter[7] << 8));
2876 gma_write16(hw, port, GM_RX_CTRL, reg);
2879 static inline u16 phy_length(const struct skge_hw *hw, u32 status)
2881 if (hw->chip_id == CHIP_ID_GENESIS)
2882 return status >> XMR_FS_LEN_SHIFT;
2884 return status >> GMR_FS_LEN_SHIFT;
2887 static inline int bad_phy_status(const struct skge_hw *hw, u32 status)
2889 if (hw->chip_id == CHIP_ID_GENESIS)
2890 return (status & (XMR_FS_ERR | XMR_FS_2L_VLAN)) != 0;
2892 return (status & GMR_FS_ANY_ERR) ||
2893 (status & GMR_FS_RX_OK) == 0;
2897 /* Get receive buffer from descriptor.
2898 * Handles copy of small buffers and reallocation failures
2900 static struct sk_buff *skge_rx_get(struct net_device *dev,
2901 struct skge_element *e,
2902 u32 control, u32 status, u16 csum)
2904 struct skge_port *skge = netdev_priv(dev);
2905 struct sk_buff *skb;
2906 u16 len = control & BMU_BBC;
2908 if (unlikely(netif_msg_rx_status(skge)))
2909 printk(KERN_DEBUG PFX "%s: rx slot %td status 0x%x len %d\n",
2910 dev->name, e - skge->rx_ring.start,
2913 if (len > skge->rx_buf_size)
2916 if ((control & (BMU_EOF|BMU_STF)) != (BMU_STF|BMU_EOF))
2919 if (bad_phy_status(skge->hw, status))
2922 if (phy_length(skge->hw, status) != len)
2925 if (len < RX_COPY_THRESHOLD) {
2926 skb = netdev_alloc_skb(dev, len + 2);
2930 skb_reserve(skb, 2);
2931 pci_dma_sync_single_for_cpu(skge->hw->pdev,
2932 pci_unmap_addr(e, mapaddr),
2933 len, PCI_DMA_FROMDEVICE);
2934 memcpy(skb->data, e->skb->data, len);
2935 pci_dma_sync_single_for_device(skge->hw->pdev,
2936 pci_unmap_addr(e, mapaddr),
2937 len, PCI_DMA_FROMDEVICE);
2938 skge_rx_reuse(e, skge->rx_buf_size);
2940 struct sk_buff *nskb;
2941 nskb = netdev_alloc_skb(dev, skge->rx_buf_size + NET_IP_ALIGN);
2945 skb_reserve(nskb, NET_IP_ALIGN);
2946 pci_unmap_single(skge->hw->pdev,
2947 pci_unmap_addr(e, mapaddr),
2948 pci_unmap_len(e, maplen),
2949 PCI_DMA_FROMDEVICE);
2951 prefetch(skb->data);
2952 skge_rx_setup(skge, e, nskb, skge->rx_buf_size);
2956 if (skge->rx_csum) {
2958 skb->ip_summed = CHECKSUM_COMPLETE;
2961 skb->protocol = eth_type_trans(skb, dev);
2966 if (netif_msg_rx_err(skge))
2967 printk(KERN_DEBUG PFX "%s: rx err, slot %td control 0x%x status 0x%x\n",
2968 dev->name, e - skge->rx_ring.start,
2971 if (skge->hw->chip_id == CHIP_ID_GENESIS) {
2972 if (status & (XMR_FS_RUNT|XMR_FS_LNG_ERR))
2973 skge->net_stats.rx_length_errors++;
2974 if (status & XMR_FS_FRA_ERR)
2975 skge->net_stats.rx_frame_errors++;
2976 if (status & XMR_FS_FCS_ERR)
2977 skge->net_stats.rx_crc_errors++;
2979 if (status & (GMR_FS_LONG_ERR|GMR_FS_UN_SIZE))
2980 skge->net_stats.rx_length_errors++;
2981 if (status & GMR_FS_FRAGMENT)
2982 skge->net_stats.rx_frame_errors++;
2983 if (status & GMR_FS_CRC_ERR)
2984 skge->net_stats.rx_crc_errors++;
2988 skge_rx_reuse(e, skge->rx_buf_size);
2992 /* Free all buffers in Tx ring which are no longer owned by device */
2993 static void skge_tx_done(struct net_device *dev)
2995 struct skge_port *skge = netdev_priv(dev);
2996 struct skge_ring *ring = &skge->tx_ring;
2997 struct skge_element *e;
2999 skge_write8(skge->hw, Q_ADDR(txqaddr[skge->port], Q_CSR), CSR_IRQ_CL_F);
3002 for (e = ring->to_clean; e != ring->to_use; e = e->next) {
3003 struct skge_tx_desc *td = e->desc;
3005 if (td->control & BMU_OWN)
3008 skge_tx_free(skge, e, td->control);
3010 skge->tx_ring.to_clean = e;
3012 if (skge_avail(&skge->tx_ring) > TX_LOW_WATER)
3013 netif_wake_queue(dev);
3015 netif_tx_unlock(dev);
3018 static int skge_poll(struct net_device *dev, int *budget)
3020 struct skge_port *skge = netdev_priv(dev);
3021 struct skge_hw *hw = skge->hw;
3022 struct skge_ring *ring = &skge->rx_ring;
3023 struct skge_element *e;
3024 unsigned long flags;
3025 int to_do = min(dev->quota, *budget);
3030 skge_write8(hw, Q_ADDR(rxqaddr[skge->port], Q_CSR), CSR_IRQ_CL_F);
3032 for (e = ring->to_clean; prefetch(e->next), work_done < to_do; e = e->next) {
3033 struct skge_rx_desc *rd = e->desc;
3034 struct sk_buff *skb;
3038 control = rd->control;
3039 if (control & BMU_OWN)
3042 skb = skge_rx_get(dev, e, control, rd->status, rd->csum2);
3044 dev->last_rx = jiffies;
3045 netif_receive_skb(skb);
3052 /* restart receiver */
3054 skge_write8(hw, Q_ADDR(rxqaddr[skge->port], Q_CSR), CSR_START);
3056 *budget -= work_done;
3057 dev->quota -= work_done;
3059 if (work_done >= to_do)
3060 return 1; /* not done */
3062 spin_lock_irqsave(&hw->hw_lock, flags);
3063 __netif_rx_complete(dev);
3064 hw->intr_mask |= napimask[skge->port];
3065 skge_write32(hw, B0_IMSK, hw->intr_mask);
3066 skge_read32(hw, B0_IMSK);
3067 spin_unlock_irqrestore(&hw->hw_lock, flags);
3072 /* Parity errors seem to happen when Genesis is connected to a switch
3073 * with no other ports present. Heartbeat error??
3075 static void skge_mac_parity(struct skge_hw *hw, int port)
3077 struct net_device *dev = hw->dev[port];
3080 struct skge_port *skge = netdev_priv(dev);
3081 ++skge->net_stats.tx_heartbeat_errors;
3084 if (hw->chip_id == CHIP_ID_GENESIS)
3085 skge_write16(hw, SK_REG(port, TX_MFF_CTRL1),
3088 /* HW-Bug #8: cleared by GMF_CLI_TX_FC instead of GMF_CLI_TX_PE */
3089 skge_write8(hw, SK_REG(port, TX_GMF_CTRL_T),
3090 (hw->chip_id == CHIP_ID_YUKON && hw->chip_rev == 0)
3091 ? GMF_CLI_TX_FC : GMF_CLI_TX_PE);
3094 static void skge_mac_intr(struct skge_hw *hw, int port)
3096 if (hw->chip_id == CHIP_ID_GENESIS)
3097 genesis_mac_intr(hw, port);
3099 yukon_mac_intr(hw, port);
3102 /* Handle device specific framing and timeout interrupts */
3103 static void skge_error_irq(struct skge_hw *hw)
3105 struct pci_dev *pdev = hw->pdev;
3106 u32 hwstatus = skge_read32(hw, B0_HWE_ISRC);
3108 if (hw->chip_id == CHIP_ID_GENESIS) {
3109 /* clear xmac errors */
3110 if (hwstatus & (IS_NO_STAT_M1|IS_NO_TIST_M1))
3111 skge_write16(hw, RX_MFF_CTRL1, MFF_CLR_INSTAT);
3112 if (hwstatus & (IS_NO_STAT_M2|IS_NO_TIST_M2))
3113 skge_write16(hw, RX_MFF_CTRL2, MFF_CLR_INSTAT);
3115 /* Timestamp (unused) overflow */
3116 if (hwstatus & IS_IRQ_TIST_OV)
3117 skge_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ);
3120 if (hwstatus & IS_RAM_RD_PAR) {
3121 dev_err(&pdev->dev, "Ram read data parity error\n");
3122 skge_write16(hw, B3_RI_CTRL, RI_CLR_RD_PERR);
3125 if (hwstatus & IS_RAM_WR_PAR) {
3126 dev_err(&pdev->dev, "Ram write data parity error\n");
3127 skge_write16(hw, B3_RI_CTRL, RI_CLR_WR_PERR);
3130 if (hwstatus & IS_M1_PAR_ERR)
3131 skge_mac_parity(hw, 0);
3133 if (hwstatus & IS_M2_PAR_ERR)
3134 skge_mac_parity(hw, 1);
3136 if (hwstatus & IS_R1_PAR_ERR) {
3137 dev_err(&pdev->dev, "%s: receive queue parity error\n",
3139 skge_write32(hw, B0_R1_CSR, CSR_IRQ_CL_P);
3142 if (hwstatus & IS_R2_PAR_ERR) {
3143 dev_err(&pdev->dev, "%s: receive queue parity error\n",
3145 skge_write32(hw, B0_R2_CSR, CSR_IRQ_CL_P);
3148 if (hwstatus & (IS_IRQ_MST_ERR|IS_IRQ_STAT)) {
3149 u16 pci_status, pci_cmd;
3151 pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd);
3152 pci_read_config_word(pdev, PCI_STATUS, &pci_status);
3154 dev_err(&pdev->dev, "PCI error cmd=%#x status=%#x\n",
3155 pci_cmd, pci_status);
3157 /* Write the error bits back to clear them. */
3158 pci_status &= PCI_STATUS_ERROR_BITS;
3159 skge_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
3160 pci_write_config_word(pdev, PCI_COMMAND,
3161 pci_cmd | PCI_COMMAND_SERR | PCI_COMMAND_PARITY);
3162 pci_write_config_word(pdev, PCI_STATUS, pci_status);
3163 skge_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
3165 /* if error still set then just ignore it */
3166 hwstatus = skge_read32(hw, B0_HWE_ISRC);
3167 if (hwstatus & IS_IRQ_STAT) {
3168 dev_warn(&hw->pdev->dev, "unable to clear error (so ignoring them)\n");
3169 hw->intr_mask &= ~IS_HW_ERR;
3175 * Interrupt from PHY are handled in tasklet (softirq)
3176 * because accessing phy registers requires spin wait which might
3177 * cause excess interrupt latency.
3179 static void skge_extirq(unsigned long arg)
3181 struct skge_hw *hw = (struct skge_hw *) arg;
3184 for (port = 0; port < hw->ports; port++) {
3185 struct net_device *dev = hw->dev[port];
3187 if (netif_running(dev)) {
3188 struct skge_port *skge = netdev_priv(dev);
3190 spin_lock(&hw->phy_lock);
3191 if (hw->chip_id != CHIP_ID_GENESIS)
3192 yukon_phy_intr(skge);
3193 else if (hw->phy_type == SK_PHY_BCOM)
3194 bcom_phy_intr(skge);
3195 spin_unlock(&hw->phy_lock);
3199 spin_lock_irq(&hw->hw_lock);
3200 hw->intr_mask |= IS_EXT_REG;
3201 skge_write32(hw, B0_IMSK, hw->intr_mask);
3202 skge_read32(hw, B0_IMSK);
3203 spin_unlock_irq(&hw->hw_lock);
3206 static irqreturn_t skge_intr(int irq, void *dev_id)
3208 struct skge_hw *hw = dev_id;
3212 spin_lock(&hw->hw_lock);
3213 /* Reading this register masks IRQ */
3214 status = skge_read32(hw, B0_SP_ISRC);
3215 if (status == 0 || status == ~0)
3219 status &= hw->intr_mask;
3220 if (status & IS_EXT_REG) {
3221 hw->intr_mask &= ~IS_EXT_REG;
3222 tasklet_schedule(&hw->phy_task);
3225 if (status & (IS_XA1_F|IS_R1_F)) {
3226 hw->intr_mask &= ~(IS_XA1_F|IS_R1_F);
3227 netif_rx_schedule(hw->dev[0]);
3230 if (status & IS_PA_TO_TX1)
3231 skge_write16(hw, B3_PA_CTRL, PA_CLR_TO_TX1);
3233 if (status & IS_PA_TO_RX1) {
3234 struct skge_port *skge = netdev_priv(hw->dev[0]);
3236 ++skge->net_stats.rx_over_errors;
3237 skge_write16(hw, B3_PA_CTRL, PA_CLR_TO_RX1);
3241 if (status & IS_MAC1)
3242 skge_mac_intr(hw, 0);
3245 if (status & (IS_XA2_F|IS_R2_F)) {
3246 hw->intr_mask &= ~(IS_XA2_F|IS_R2_F);
3247 netif_rx_schedule(hw->dev[1]);
3250 if (status & IS_PA_TO_RX2) {
3251 struct skge_port *skge = netdev_priv(hw->dev[1]);
3252 ++skge->net_stats.rx_over_errors;
3253 skge_write16(hw, B3_PA_CTRL, PA_CLR_TO_RX2);
3256 if (status & IS_PA_TO_TX2)
3257 skge_write16(hw, B3_PA_CTRL, PA_CLR_TO_TX2);
3259 if (status & IS_MAC2)
3260 skge_mac_intr(hw, 1);
3263 if (status & IS_HW_ERR)
3266 skge_write32(hw, B0_IMSK, hw->intr_mask);
3267 skge_read32(hw, B0_IMSK);
3269 spin_unlock(&hw->hw_lock);
3271 return IRQ_RETVAL(handled);
3274 #ifdef CONFIG_NET_POLL_CONTROLLER
3275 static void skge_netpoll(struct net_device *dev)
3277 struct skge_port *skge = netdev_priv(dev);
3279 disable_irq(dev->irq);
3280 skge_intr(dev->irq, skge->hw);
3281 enable_irq(dev->irq);
3285 static int skge_set_mac_address(struct net_device *dev, void *p)
3287 struct skge_port *skge = netdev_priv(dev);
3288 struct skge_hw *hw = skge->hw;
3289 unsigned port = skge->port;
3290 const struct sockaddr *addr = p;
3293 if (!is_valid_ether_addr(addr->sa_data))
3294 return -EADDRNOTAVAIL;
3296 memcpy(dev->dev_addr, addr->sa_data, ETH_ALEN);
3298 if (!netif_running(dev)) {
3299 memcpy_toio(hw->regs + B2_MAC_1 + port*8, dev->dev_addr, ETH_ALEN);
3300 memcpy_toio(hw->regs + B2_MAC_2 + port*8, dev->dev_addr, ETH_ALEN);
3303 spin_lock_bh(&hw->phy_lock);
3304 ctrl = gma_read16(hw, port, GM_GP_CTRL);
3305 gma_write16(hw, port, GM_GP_CTRL, ctrl & ~GM_GPCR_RX_ENA);
3307 memcpy_toio(hw->regs + B2_MAC_1 + port*8, dev->dev_addr, ETH_ALEN);
3308 memcpy_toio(hw->regs + B2_MAC_2 + port*8, dev->dev_addr, ETH_ALEN);
3310 if (hw->chip_id == CHIP_ID_GENESIS)
3311 xm_outaddr(hw, port, XM_SA, dev->dev_addr);
3313 gma_set_addr(hw, port, GM_SRC_ADDR_1L, dev->dev_addr);
3314 gma_set_addr(hw, port, GM_SRC_ADDR_2L, dev->dev_addr);
3317 gma_write16(hw, port, GM_GP_CTRL, ctrl);
3318 spin_unlock_bh(&hw->phy_lock);
3324 static const struct {
3328 { CHIP_ID_GENESIS, "Genesis" },
3329 { CHIP_ID_YUKON, "Yukon" },
3330 { CHIP_ID_YUKON_LITE, "Yukon-Lite"},
3331 { CHIP_ID_YUKON_LP, "Yukon-LP"},
3334 static const char *skge_board_name(const struct skge_hw *hw)
3337 static char buf[16];
3339 for (i = 0; i < ARRAY_SIZE(skge_chips); i++)
3340 if (skge_chips[i].id == hw->chip_id)
3341 return skge_chips[i].name;
3343 snprintf(buf, sizeof buf, "chipid 0x%x", hw->chip_id);
3349 * Setup the board data structure, but don't bring up
3352 static int skge_reset(struct skge_hw *hw)
3355 u16 ctst, pci_status;
3356 u8 t8, mac_cfg, pmd_type;
3359 ctst = skge_read16(hw, B0_CTST);
3362 skge_write8(hw, B0_CTST, CS_RST_SET);
3363 skge_write8(hw, B0_CTST, CS_RST_CLR);
3365 /* clear PCI errors, if any */
3366 skge_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
3367 skge_write8(hw, B2_TST_CTRL2, 0);
3369 pci_read_config_word(hw->pdev, PCI_STATUS, &pci_status);
3370 pci_write_config_word(hw->pdev, PCI_STATUS,
3371 pci_status | PCI_STATUS_ERROR_BITS);
3372 skge_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
3373 skge_write8(hw, B0_CTST, CS_MRST_CLR);
3375 /* restore CLK_RUN bits (for Yukon-Lite) */
3376 skge_write16(hw, B0_CTST,
3377 ctst & (CS_CLK_RUN_HOT|CS_CLK_RUN_RST|CS_CLK_RUN_ENA));
3379 hw->chip_id = skge_read8(hw, B2_CHIP_ID);
3380 hw->phy_type = skge_read8(hw, B2_E_1) & 0xf;
3381 pmd_type = skge_read8(hw, B2_PMD_TYP);
3382 hw->copper = (pmd_type == 'T' || pmd_type == '1');
3384 switch (hw->chip_id) {
3385 case CHIP_ID_GENESIS:
3386 switch (hw->phy_type) {
3388 hw->phy_addr = PHY_ADDR_XMAC;
3391 hw->phy_addr = PHY_ADDR_BCOM;
3394 dev_err(&hw->pdev->dev, "unsupported phy type 0x%x\n",
3401 case CHIP_ID_YUKON_LITE:
3402 case CHIP_ID_YUKON_LP:
3403 if (hw->phy_type < SK_PHY_MARV_COPPER && pmd_type != 'S')
3406 hw->phy_addr = PHY_ADDR_MARV;
3410 dev_err(&hw->pdev->dev, "unsupported chip type 0x%x\n",
3415 mac_cfg = skge_read8(hw, B2_MAC_CFG);
3416 hw->ports = (mac_cfg & CFG_SNG_MAC) ? 1 : 2;
3417 hw->chip_rev = (mac_cfg & CFG_CHIP_R_MSK) >> 4;
3419 /* read the adapters RAM size */
3420 t8 = skge_read8(hw, B2_E_0);
3421 if (hw->chip_id == CHIP_ID_GENESIS) {
3423 /* special case: 4 x 64k x 36, offset = 0x80000 */
3424 hw->ram_size = 0x100000;
3425 hw->ram_offset = 0x80000;
3427 hw->ram_size = t8 * 512;
3430 hw->ram_size = 0x20000;
3432 hw->ram_size = t8 * 4096;
3434 hw->intr_mask = IS_HW_ERR;
3436 /* Use PHY IRQ for all but fiber based Genesis board */
3437 if (!(hw->chip_id == CHIP_ID_GENESIS && hw->phy_type == SK_PHY_XMAC))
3438 hw->intr_mask |= IS_EXT_REG;
3440 if (hw->chip_id == CHIP_ID_GENESIS)
3443 /* switch power to VCC (WA for VAUX problem) */
3444 skge_write8(hw, B0_POWER_CTRL,
3445 PC_VAUX_ENA | PC_VCC_ENA | PC_VAUX_OFF | PC_VCC_ON);
3447 /* avoid boards with stuck Hardware error bits */
3448 if ((skge_read32(hw, B0_ISRC) & IS_HW_ERR) &&
3449 (skge_read32(hw, B0_HWE_ISRC) & IS_IRQ_SENSOR)) {
3450 dev_warn(&hw->pdev->dev, "stuck hardware sensor bit\n");
3451 hw->intr_mask &= ~IS_HW_ERR;
3454 /* Clear PHY COMA */
3455 skge_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
3456 pci_read_config_dword(hw->pdev, PCI_DEV_REG1, ®);
3457 reg &= ~PCI_PHY_COMA;
3458 pci_write_config_dword(hw->pdev, PCI_DEV_REG1, reg);
3459 skge_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
3462 for (i = 0; i < hw->ports; i++) {
3463 skge_write16(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_SET);
3464 skge_write16(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_CLR);
3468 /* turn off hardware timer (unused) */
3469 skge_write8(hw, B2_TI_CTRL, TIM_STOP);
3470 skge_write8(hw, B2_TI_CTRL, TIM_CLR_IRQ);
3471 skge_write8(hw, B0_LED, LED_STAT_ON);
3473 /* enable the Tx Arbiters */
3474 for (i = 0; i < hw->ports; i++)
3475 skge_write8(hw, SK_REG(i, TXA_CTRL), TXA_ENA_ARB);
3477 /* Initialize ram interface */
3478 skge_write16(hw, B3_RI_CTRL, RI_RST_CLR);
3480 skge_write8(hw, B3_RI_WTO_R1, SK_RI_TO_53);
3481 skge_write8(hw, B3_RI_WTO_XA1, SK_RI_TO_53);
3482 skge_write8(hw, B3_RI_WTO_XS1, SK_RI_TO_53);
3483 skge_write8(hw, B3_RI_RTO_R1, SK_RI_TO_53);
3484 skge_write8(hw, B3_RI_RTO_XA1, SK_RI_TO_53);
3485 skge_write8(hw, B3_RI_RTO_XS1, SK_RI_TO_53);
3486 skge_write8(hw, B3_RI_WTO_R2, SK_RI_TO_53);
3487 skge_write8(hw, B3_RI_WTO_XA2, SK_RI_TO_53);
3488 skge_write8(hw, B3_RI_WTO_XS2, SK_RI_TO_53);
3489 skge_write8(hw, B3_RI_RTO_R2, SK_RI_TO_53);
3490 skge_write8(hw, B3_RI_RTO_XA2, SK_RI_TO_53);
3491 skge_write8(hw, B3_RI_RTO_XS2, SK_RI_TO_53);
3493 skge_write32(hw, B0_HWE_IMSK, IS_ERR_MSK);
3495 /* Set interrupt moderation for Transmit only
3496 * Receive interrupts avoided by NAPI
3498 skge_write32(hw, B2_IRQM_MSK, IS_XA1_F|IS_XA2_F);
3499 skge_write32(hw, B2_IRQM_INI, skge_usecs2clk(hw, 100));
3500 skge_write32(hw, B2_IRQM_CTRL, TIM_START);
3502 skge_write32(hw, B0_IMSK, hw->intr_mask);
3504 for (i = 0; i < hw->ports; i++) {
3505 if (hw->chip_id == CHIP_ID_GENESIS)
3506 genesis_reset(hw, i);
3514 /* Initialize network device */
3515 static struct net_device *skge_devinit(struct skge_hw *hw, int port,
3518 struct skge_port *skge;
3519 struct net_device *dev = alloc_etherdev(sizeof(*skge));
3522 dev_err(&hw->pdev->dev, "etherdev alloc failed\n");
3526 SET_MODULE_OWNER(dev);
3527 SET_NETDEV_DEV(dev, &hw->pdev->dev);
3528 dev->open = skge_up;
3529 dev->stop = skge_down;
3530 dev->do_ioctl = skge_ioctl;
3531 dev->hard_start_xmit = skge_xmit_frame;
3532 dev->get_stats = skge_get_stats;
3533 if (hw->chip_id == CHIP_ID_GENESIS)
3534 dev->set_multicast_list = genesis_set_multicast;
3536 dev->set_multicast_list = yukon_set_multicast;
3538 dev->set_mac_address = skge_set_mac_address;
3539 dev->change_mtu = skge_change_mtu;
3540 SET_ETHTOOL_OPS(dev, &skge_ethtool_ops);
3541 dev->tx_timeout = skge_tx_timeout;
3542 dev->watchdog_timeo = TX_WATCHDOG;
3543 dev->poll = skge_poll;
3544 dev->weight = NAPI_WEIGHT;
3545 #ifdef CONFIG_NET_POLL_CONTROLLER
3546 dev->poll_controller = skge_netpoll;
3548 dev->irq = hw->pdev->irq;
3551 dev->features |= NETIF_F_HIGHDMA;
3553 skge = netdev_priv(dev);
3556 skge->msg_enable = netif_msg_init(debug, default_msg);
3558 skge->tx_ring.count = DEFAULT_TX_RING_SIZE;
3559 skge->rx_ring.count = DEFAULT_RX_RING_SIZE;
3561 /* Auto speed and flow control */
3562 skge->autoneg = AUTONEG_ENABLE;
3563 skge->flow_control = FLOW_MODE_SYM_OR_REM;
3566 skge->advertising = skge_supported_modes(hw);
3567 skge->wol = pci_wake_enabled(hw->pdev) ? wol_supported(hw) : 0;
3569 hw->dev[port] = dev;
3573 /* Only used for Genesis XMAC */
3574 setup_timer(&skge->link_timer, xm_link_timer, (unsigned long) skge);
3576 if (hw->chip_id != CHIP_ID_GENESIS) {
3577 dev->features |= NETIF_F_IP_CSUM | NETIF_F_SG;
3581 /* read the mac address */
3582 memcpy_fromio(dev->dev_addr, hw->regs + B2_MAC_1 + port*8, ETH_ALEN);
3583 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
3585 /* device is off until link detection */
3586 netif_carrier_off(dev);
3587 netif_stop_queue(dev);
3592 static void __devinit skge_show_addr(struct net_device *dev)
3594 const struct skge_port *skge = netdev_priv(dev);
3596 if (netif_msg_probe(skge))
3597 printk(KERN_INFO PFX "%s: addr %02x:%02x:%02x:%02x:%02x:%02x\n",
3599 dev->dev_addr[0], dev->dev_addr[1], dev->dev_addr[2],
3600 dev->dev_addr[3], dev->dev_addr[4], dev->dev_addr[5]);
3603 static int __devinit skge_probe(struct pci_dev *pdev,
3604 const struct pci_device_id *ent)
3606 struct net_device *dev, *dev1;
3608 int err, using_dac = 0;
3610 err = pci_enable_device(pdev);
3612 dev_err(&pdev->dev, "cannot enable PCI device\n");
3616 err = pci_request_regions(pdev, DRV_NAME);
3618 dev_err(&pdev->dev, "cannot obtain PCI resources\n");
3619 goto err_out_disable_pdev;
3622 pci_set_master(pdev);
3624 if (!pci_set_dma_mask(pdev, DMA_64BIT_MASK)) {
3626 err = pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK);
3627 } else if (!(err = pci_set_dma_mask(pdev, DMA_32BIT_MASK))) {
3629 err = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
3633 dev_err(&pdev->dev, "no usable DMA configuration\n");
3634 goto err_out_free_regions;
3638 /* byte swap descriptors in hardware */
3642 pci_read_config_dword(pdev, PCI_DEV_REG2, ®);
3643 reg |= PCI_REV_DESC;
3644 pci_write_config_dword(pdev, PCI_DEV_REG2, reg);
3649 hw = kzalloc(sizeof(*hw), GFP_KERNEL);
3651 dev_err(&pdev->dev, "cannot allocate hardware struct\n");
3652 goto err_out_free_regions;
3656 spin_lock_init(&hw->hw_lock);
3657 spin_lock_init(&hw->phy_lock);
3658 tasklet_init(&hw->phy_task, &skge_extirq, (unsigned long) hw);
3660 hw->regs = ioremap_nocache(pci_resource_start(pdev, 0), 0x4000);
3662 dev_err(&pdev->dev, "cannot map device registers\n");
3663 goto err_out_free_hw;
3666 err = skge_reset(hw);
3668 goto err_out_iounmap;
3670 printk(KERN_INFO PFX DRV_VERSION " addr 0x%llx irq %d chip %s rev %d\n",
3671 (unsigned long long)pci_resource_start(pdev, 0), pdev->irq,
3672 skge_board_name(hw), hw->chip_rev);
3674 dev = skge_devinit(hw, 0, using_dac);
3676 goto err_out_led_off;
3678 /* Some motherboards are broken and has zero in ROM. */
3679 if (!is_valid_ether_addr(dev->dev_addr))
3680 dev_warn(&pdev->dev, "bad (zero?) ethernet address in rom\n");
3682 err = register_netdev(dev);
3684 dev_err(&pdev->dev, "cannot register net device\n");
3685 goto err_out_free_netdev;
3688 err = request_irq(pdev->irq, skge_intr, IRQF_SHARED, dev->name, hw);
3690 dev_err(&pdev->dev, "%s: cannot assign irq %d\n",
3691 dev->name, pdev->irq);
3692 goto err_out_unregister;
3694 skge_show_addr(dev);
3696 if (hw->ports > 1 && (dev1 = skge_devinit(hw, 1, using_dac))) {
3697 if (register_netdev(dev1) == 0)
3698 skge_show_addr(dev1);
3700 /* Failure to register second port need not be fatal */
3701 dev_warn(&pdev->dev, "register of second port failed\n");
3706 pci_set_drvdata(pdev, hw);
3711 unregister_netdev(dev);
3712 err_out_free_netdev:
3715 skge_write16(hw, B0_LED, LED_STAT_OFF);
3720 err_out_free_regions:
3721 pci_release_regions(pdev);
3722 err_out_disable_pdev:
3723 pci_disable_device(pdev);
3724 pci_set_drvdata(pdev, NULL);
3729 static void __devexit skge_remove(struct pci_dev *pdev)
3731 struct skge_hw *hw = pci_get_drvdata(pdev);
3732 struct net_device *dev0, *dev1;
3737 flush_scheduled_work();
3739 if ((dev1 = hw->dev[1]))
3740 unregister_netdev(dev1);
3742 unregister_netdev(dev0);
3744 tasklet_disable(&hw->phy_task);
3746 spin_lock_irq(&hw->hw_lock);
3748 skge_write32(hw, B0_IMSK, 0);
3749 skge_read32(hw, B0_IMSK);
3750 spin_unlock_irq(&hw->hw_lock);
3752 skge_write16(hw, B0_LED, LED_STAT_OFF);
3753 skge_write8(hw, B0_CTST, CS_RST_SET);
3755 free_irq(pdev->irq, hw);
3756 pci_release_regions(pdev);
3757 pci_disable_device(pdev);
3764 pci_set_drvdata(pdev, NULL);
3768 static int vaux_avail(struct pci_dev *pdev)
3772 pm_cap = pci_find_capability(pdev, PCI_CAP_ID_PM);
3775 pci_read_config_word(pdev, pm_cap + PCI_PM_PMC, &ctl);
3776 if (ctl & PCI_PM_CAP_AUX_POWER)
3783 static int skge_suspend(struct pci_dev *pdev, pm_message_t state)
3785 struct skge_hw *hw = pci_get_drvdata(pdev);
3786 int i, err, wol = 0;
3788 err = pci_save_state(pdev);
3792 for (i = 0; i < hw->ports; i++) {
3793 struct net_device *dev = hw->dev[i];
3794 struct skge_port *skge = netdev_priv(dev);
3796 if (netif_running(dev))
3799 skge_wol_init(skge);
3804 if (wol && vaux_avail(pdev))
3805 skge_write8(hw, B0_POWER_CTRL,
3806 PC_VAUX_ENA | PC_VCC_ENA | PC_VAUX_ON | PC_VCC_OFF);
3808 skge_write32(hw, B0_IMSK, 0);
3809 pci_enable_wake(pdev, pci_choose_state(pdev, state), wol);
3810 pci_set_power_state(pdev, pci_choose_state(pdev, state));
3815 static int skge_resume(struct pci_dev *pdev)
3817 struct skge_hw *hw = pci_get_drvdata(pdev);
3820 err = pci_set_power_state(pdev, PCI_D0);
3824 err = pci_restore_state(pdev);
3828 pci_enable_wake(pdev, PCI_D0, 0);
3830 err = skge_reset(hw);
3834 for (i = 0; i < hw->ports; i++) {
3835 struct net_device *dev = hw->dev[i];
3837 if (netif_running(dev)) {
3841 printk(KERN_ERR PFX "%s: could not up: %d\n",
3853 static struct pci_driver skge_driver = {
3855 .id_table = skge_id_table,
3856 .probe = skge_probe,
3857 .remove = __devexit_p(skge_remove),
3859 .suspend = skge_suspend,
3860 .resume = skge_resume,
3864 static int __init skge_init_module(void)
3866 return pci_register_driver(&skge_driver);
3869 static void __exit skge_cleanup_module(void)
3871 pci_unregister_driver(&skge_driver);
3874 module_init(skge_init_module);
3875 module_exit(skge_cleanup_module);