err.no Git - linux-2.6/blob - drivers/net/s2io.c

   1 /************************************************************************
   2  * s2io.c: A Linux PCI-X Ethernet driver for Neterion 10GbE Server NIC
   3  * Copyright(c) 2002-2007 Neterion Inc.
   4
   5  * This software may be used and distributed according to the terms of
   6  * the GNU General Public License (GPL), incorporated herein by reference.
   7  * Drivers based on or derived from this code fall under the GPL and must
   8  * retain the authorship, copyright and license notice.  This file is not
   9  * a complete program and may only be used when the entire operating
  10  * system is licensed under the GPL.
  11  * See the file COPYING in this distribution for more information.
  12  *
  13  * Credits:
  14  * Jeff Garzik          : For pointing out the improper error condition
  15  *                        check in the s2io_xmit routine and also some
  16  *                        issues in the Tx watch dog function. Also for
  17  *                        patiently answering all those innumerable
  18  *                        questions regaring the 2.6 porting issues.
  19  * Stephen Hemminger    : Providing proper 2.6 porting mechanism for some
  20  *                        macros available only in 2.6 Kernel.
  21  * Francois Romieu      : For pointing out all code part that were
  22  *                        deprecated and also styling related comments.
  23  * Grant Grundler       : For helping me get rid of some Architecture
  24  *                        dependent code.
  25  * Christopher Hellwig  : Some more 2.6 specific issues in the driver.
  26  *
  27  * The module loadable parameters that are supported by the driver and a brief
  28  * explaination of all the variables.
  29  *
  30  * rx_ring_num : This can be used to program the number of receive rings used
  31  * in the driver.
  32  * rx_ring_sz: This defines the number of receive blocks each ring can have.
  33  *     This is also an array of size 8.
  34  * rx_ring_mode: This defines the operation mode of all 8 rings. The valid
  35  *              values are 1, 2.
  36  * tx_fifo_num: This defines the number of Tx FIFOs thats used int the driver.
  37  * tx_fifo_len: This too is an array of 8. Each element defines the number of
  38  * Tx descriptors that can be associated with each corresponding FIFO.
  39  * intr_type: This defines the type of interrupt. The values can be 0(INTA),
  40  *     2(MSI_X). Default value is '2(MSI_X)'
  41  * lro_enable: Specifies whether to enable Large Receive Offload (LRO) or not.
  42  *     Possible values '1' for enable '0' for disable. Default is '0'
  43  * lro_max_pkts: This parameter defines maximum number of packets can be
  44  *     aggregated as a single large packet
  45  * napi: This parameter used to enable/disable NAPI (polling Rx)
  46  *     Possible values '1' for enable and '0' for disable. Default is '1'
  47  * ufo: This parameter used to enable/disable UDP Fragmentation Offload(UFO)
  48  *      Possible values '1' for enable and '0' for disable. Default is '0'
  49  * vlan_tag_strip: This can be used to enable or disable vlan stripping.
  50  *                 Possible values '1' for enable , '0' for disable.
  51  *                 Default is '2' - which means disable in promisc mode
  52  *                 and enable in non-promiscuous mode.
  53  * multiq: This parameter used to enable/disable MULTIQUEUE support.
  54  *      Possible values '1' for enable and '0' for disable. Default is '0'
  55  ************************************************************************/
  56
  57 #include <linux/module.h>
  58 #include <linux/types.h>
  59 #include <linux/errno.h>
  60 #include <linux/ioport.h>
  61 #include <linux/pci.h>
  62 #include <linux/dma-mapping.h>
  63 #include <linux/kernel.h>
  64 #include <linux/netdevice.h>
  65 #include <linux/etherdevice.h>
  66 #include <linux/skbuff.h>
  67 #include <linux/init.h>
  68 #include <linux/delay.h>
  69 #include <linux/stddef.h>
  70 #include <linux/ioctl.h>
  71 #include <linux/timex.h>
  72 #include <linux/ethtool.h>
  73 #include <linux/workqueue.h>
  74 #include <linux/if_vlan.h>
  75 #include <linux/ip.h>
  76 #include <linux/tcp.h>
  77 #include <net/tcp.h>
  78
  79 #include <asm/system.h>
  80 #include <asm/uaccess.h>
  81 #include <asm/io.h>
  82 #include <asm/div64.h>
  83 #include <asm/irq.h>
  84
  85 /* local include */
  86 #include "s2io.h"
  87 #include "s2io-regs.h"
  88
  89 #define DRV_VERSION "2.0.26.23"
  90
  91 /* S2io Driver name & version. */
  92 static char s2io_driver_name[] = "Neterion";
  93 static char s2io_driver_version[] = DRV_VERSION;
  94
  95 static int rxd_size[2] = {32,48};
  96 static int rxd_count[2] = {127,85};
  97
  98 static inline int RXD_IS_UP2DT(struct RxD_t *rxdp)
  99 {
 100         int ret;
 101
 102         ret = ((!(rxdp->Control_1 & RXD_OWN_XENA)) &&
 103                 (GET_RXD_MARKER(rxdp->Control_2) != THE_RXD_MARK));
 104
 105         return ret;
 106 }
 107
 108 /*
 109  * Cards with following subsystem_id have a link state indication
 110  * problem, 600B, 600C, 600D, 640B, 640C and 640D.
 111  * macro below identifies these cards given the subsystem_id.
 112  */
 113 #define CARDS_WITH_FAULTY_LINK_INDICATORS(dev_type, subid) \
 114         (dev_type == XFRAME_I_DEVICE) ?                 \
 115                 ((((subid >= 0x600B) && (subid <= 0x600D)) || \
 116                  ((subid >= 0x640B) && (subid <= 0x640D))) ? 1 : 0) : 0
 117
 118 #define LINK_IS_UP(val64) (!(val64 & (ADAPTER_STATUS_RMAC_REMOTE_FAULT | \
 119                                       ADAPTER_STATUS_RMAC_LOCAL_FAULT)))
 120
 121 static inline int is_s2io_card_up(const struct s2io_nic * sp)
 122 {
 123         return test_bit(__S2IO_STATE_CARD_UP, &sp->state);
 124 }
 125
 126 /* Ethtool related variables and Macros. */
 127 static char s2io_gstrings[][ETH_GSTRING_LEN] = {
 128         "Register test\t(offline)",
 129         "Eeprom test\t(offline)",
 130         "Link test\t(online)",
 131         "RLDRAM test\t(offline)",
 132         "BIST Test\t(offline)"
 133 };
 134
 135 static char ethtool_xena_stats_keys[][ETH_GSTRING_LEN] = {
 136         {"tmac_frms"},
 137         {"tmac_data_octets"},
 138         {"tmac_drop_frms"},
 139         {"tmac_mcst_frms"},
 140         {"tmac_bcst_frms"},
 141         {"tmac_pause_ctrl_frms"},
 142         {"tmac_ttl_octets"},
 143         {"tmac_ucst_frms"},
 144         {"tmac_nucst_frms"},
 145         {"tmac_any_err_frms"},
 146         {"tmac_ttl_less_fb_octets"},
 147         {"tmac_vld_ip_octets"},
 148         {"tmac_vld_ip"},
 149         {"tmac_drop_ip"},
 150         {"tmac_icmp"},
 151         {"tmac_rst_tcp"},
 152         {"tmac_tcp"},
 153         {"tmac_udp"},
 154         {"rmac_vld_frms"},
 155         {"rmac_data_octets"},
 156         {"rmac_fcs_err_frms"},
 157         {"rmac_drop_frms"},
 158         {"rmac_vld_mcst_frms"},
 159         {"rmac_vld_bcst_frms"},
 160         {"rmac_in_rng_len_err_frms"},
 161         {"rmac_out_rng_len_err_frms"},
 162         {"rmac_long_frms"},
 163         {"rmac_pause_ctrl_frms"},
 164         {"rmac_unsup_ctrl_frms"},
 165         {"rmac_ttl_octets"},
 166         {"rmac_accepted_ucst_frms"},
 167         {"rmac_accepted_nucst_frms"},
 168         {"rmac_discarded_frms"},
 169         {"rmac_drop_events"},
 170         {"rmac_ttl_less_fb_octets"},
 171         {"rmac_ttl_frms"},
 172         {"rmac_usized_frms"},
 173         {"rmac_osized_frms"},
 174         {"rmac_frag_frms"},
 175         {"rmac_jabber_frms"},
 176         {"rmac_ttl_64_frms"},
 177         {"rmac_ttl_65_127_frms"},
 178         {"rmac_ttl_128_255_frms"},
 179         {"rmac_ttl_256_511_frms"},
 180         {"rmac_ttl_512_1023_frms"},
 181         {"rmac_ttl_1024_1518_frms"},
 182         {"rmac_ip"},
 183         {"rmac_ip_octets"},
 184         {"rmac_hdr_err_ip"},
 185         {"rmac_drop_ip"},
 186         {"rmac_icmp"},
 187         {"rmac_tcp"},
 188         {"rmac_udp"},
 189         {"rmac_err_drp_udp"},
 190         {"rmac_xgmii_err_sym"},
 191         {"rmac_frms_q0"},
 192         {"rmac_frms_q1"},
 193         {"rmac_frms_q2"},
 194         {"rmac_frms_q3"},
 195         {"rmac_frms_q4"},
 196         {"rmac_frms_q5"},
 197         {"rmac_frms_q6"},
 198         {"rmac_frms_q7"},
 199         {"rmac_full_q0"},
 200         {"rmac_full_q1"},
 201         {"rmac_full_q2"},
 202         {"rmac_full_q3"},
 203         {"rmac_full_q4"},
 204         {"rmac_full_q5"},
 205         {"rmac_full_q6"},
 206         {"rmac_full_q7"},
 207         {"rmac_pause_cnt"},
 208         {"rmac_xgmii_data_err_cnt"},
 209         {"rmac_xgmii_ctrl_err_cnt"},
 210         {"rmac_accepted_ip"},
 211         {"rmac_err_tcp"},
 212         {"rd_req_cnt"},
 213         {"new_rd_req_cnt"},
 214         {"new_rd_req_rtry_cnt"},
 215         {"rd_rtry_cnt"},
 216         {"wr_rtry_rd_ack_cnt"},
 217         {"wr_req_cnt"},
 218         {"new_wr_req_cnt"},
 219         {"new_wr_req_rtry_cnt"},
 220         {"wr_rtry_cnt"},
 221         {"wr_disc_cnt"},
 222         {"rd_rtry_wr_ack_cnt"},
 223         {"txp_wr_cnt"},
 224         {"txd_rd_cnt"},
 225         {"txd_wr_cnt"},
 226         {"rxd_rd_cnt"},
 227         {"rxd_wr_cnt"},
 228         {"txf_rd_cnt"},
 229         {"rxf_wr_cnt"}
 230 };
 231
 232 static char ethtool_enhanced_stats_keys[][ETH_GSTRING_LEN] = {
 233         {"rmac_ttl_1519_4095_frms"},
 234         {"rmac_ttl_4096_8191_frms"},
 235         {"rmac_ttl_8192_max_frms"},
 236         {"rmac_ttl_gt_max_frms"},
 237         {"rmac_osized_alt_frms"},
 238         {"rmac_jabber_alt_frms"},
 239         {"rmac_gt_max_alt_frms"},
 240         {"rmac_vlan_frms"},
 241         {"rmac_len_discard"},
 242         {"rmac_fcs_discard"},
 243         {"rmac_pf_discard"},
 244         {"rmac_da_discard"},
 245         {"rmac_red_discard"},
 246         {"rmac_rts_discard"},
 247         {"rmac_ingm_full_discard"},
 248         {"link_fault_cnt"}
 249 };
 250
 251 static char ethtool_driver_stats_keys[][ETH_GSTRING_LEN] = {
 252         {"\n DRIVER STATISTICS"},
 253         {"single_bit_ecc_errs"},
 254         {"double_bit_ecc_errs"},
 255         {"parity_err_cnt"},
 256         {"serious_err_cnt"},
 257         {"soft_reset_cnt"},
 258         {"fifo_full_cnt"},
 259         {"ring_0_full_cnt"},
 260         {"ring_1_full_cnt"},
 261         {"ring_2_full_cnt"},
 262         {"ring_3_full_cnt"},
 263         {"ring_4_full_cnt"},
 264         {"ring_5_full_cnt"},
 265         {"ring_6_full_cnt"},
 266         {"ring_7_full_cnt"},
 267         {"alarm_transceiver_temp_high"},
 268         {"alarm_transceiver_temp_low"},
 269         {"alarm_laser_bias_current_high"},
 270         {"alarm_laser_bias_current_low"},
 271         {"alarm_laser_output_power_high"},
 272         {"alarm_laser_output_power_low"},
 273         {"warn_transceiver_temp_high"},
 274         {"warn_transceiver_temp_low"},
 275         {"warn_laser_bias_current_high"},
 276         {"warn_laser_bias_current_low"},
 277         {"warn_laser_output_power_high"},
 278         {"warn_laser_output_power_low"},
 279         {"lro_aggregated_pkts"},
 280         {"lro_flush_both_count"},
 281         {"lro_out_of_sequence_pkts"},
 282         {"lro_flush_due_to_max_pkts"},
 283         {"lro_avg_aggr_pkts"},
 284         {"mem_alloc_fail_cnt"},
 285         {"pci_map_fail_cnt"},
 286         {"watchdog_timer_cnt"},
 287         {"mem_allocated"},
 288         {"mem_freed"},
 289         {"link_up_cnt"},
 290         {"link_down_cnt"},
 291         {"link_up_time"},
 292         {"link_down_time"},
 293         {"tx_tcode_buf_abort_cnt"},
 294         {"tx_tcode_desc_abort_cnt"},
 295         {"tx_tcode_parity_err_cnt"},
 296         {"tx_tcode_link_loss_cnt"},
 297         {"tx_tcode_list_proc_err_cnt"},
 298         {"rx_tcode_parity_err_cnt"},
 299         {"rx_tcode_abort_cnt"},
 300         {"rx_tcode_parity_abort_cnt"},
 301         {"rx_tcode_rda_fail_cnt"},
 302         {"rx_tcode_unkn_prot_cnt"},
 303         {"rx_tcode_fcs_err_cnt"},
 304         {"rx_tcode_buf_size_err_cnt"},
 305         {"rx_tcode_rxd_corrupt_cnt"},
 306         {"rx_tcode_unkn_err_cnt"},
 307         {"tda_err_cnt"},
 308         {"pfc_err_cnt"},
 309         {"pcc_err_cnt"},
 310         {"tti_err_cnt"},
 311         {"tpa_err_cnt"},
 312         {"sm_err_cnt"},
 313         {"lso_err_cnt"},
 314         {"mac_tmac_err_cnt"},
 315         {"mac_rmac_err_cnt"},
 316         {"xgxs_txgxs_err_cnt"},
 317         {"xgxs_rxgxs_err_cnt"},
 318         {"rc_err_cnt"},
 319         {"prc_pcix_err_cnt"},
 320         {"rpa_err_cnt"},
 321         {"rda_err_cnt"},
 322         {"rti_err_cnt"},
 323         {"mc_err_cnt"}
 324 };
 325
 326 #define S2IO_XENA_STAT_LEN      ARRAY_SIZE(ethtool_xena_stats_keys)
 327 #define S2IO_ENHANCED_STAT_LEN  ARRAY_SIZE(ethtool_enhanced_stats_keys)
 328 #define S2IO_DRIVER_STAT_LEN    ARRAY_SIZE(ethtool_driver_stats_keys)
 329
 330 #define XFRAME_I_STAT_LEN (S2IO_XENA_STAT_LEN + S2IO_DRIVER_STAT_LEN )
 331 #define XFRAME_II_STAT_LEN (XFRAME_I_STAT_LEN + S2IO_ENHANCED_STAT_LEN )
 332
 333 #define XFRAME_I_STAT_STRINGS_LEN ( XFRAME_I_STAT_LEN * ETH_GSTRING_LEN )
 334 #define XFRAME_II_STAT_STRINGS_LEN ( XFRAME_II_STAT_LEN * ETH_GSTRING_LEN )
 335
 336 #define S2IO_TEST_LEN   ARRAY_SIZE(s2io_gstrings)
 337 #define S2IO_STRINGS_LEN        S2IO_TEST_LEN * ETH_GSTRING_LEN
 338
 339 #define S2IO_TIMER_CONF(timer, handle, arg, exp)                \
 340                         init_timer(&timer);                     \
 341                         timer.function = handle;                \
 342                         timer.data = (unsigned long) arg;       \
 343                         mod_timer(&timer, (jiffies + exp))      \
 344
 345 /* copy mac addr to def_mac_addr array */
 346 static void do_s2io_copy_mac_addr(struct s2io_nic *sp, int offset, u64 mac_addr)
 347 {
 348         sp->def_mac_addr[offset].mac_addr[5] = (u8) (mac_addr);
 349         sp->def_mac_addr[offset].mac_addr[4] = (u8) (mac_addr >> 8);
 350         sp->def_mac_addr[offset].mac_addr[3] = (u8) (mac_addr >> 16);
 351         sp->def_mac_addr[offset].mac_addr[2] = (u8) (mac_addr >> 24);
 352         sp->def_mac_addr[offset].mac_addr[1] = (u8) (mac_addr >> 32);
 353         sp->def_mac_addr[offset].mac_addr[0] = (u8) (mac_addr >> 40);
 354 }
 355 /* Add the vlan */
 356 static void s2io_vlan_rx_register(struct net_device *dev,
 357                                         struct vlan_group *grp)
 358 {
 359         int i;
 360         struct s2io_nic *nic = dev->priv;
 361         unsigned long flags[MAX_TX_FIFOS];
 362         struct mac_info *mac_control = &nic->mac_control;
 363         struct config_param *config = &nic->config;
 364
 365         for (i = 0; i < config->tx_fifo_num; i++)
 366                 spin_lock_irqsave(&mac_control->fifos[i].tx_lock, flags[i]);
 367
 368         nic->vlgrp = grp;
 369         for (i = config->tx_fifo_num - 1; i >= 0; i--)
 370                 spin_unlock_irqrestore(&mac_control->fifos[i].tx_lock,
 371                                 flags[i]);
 372 }
 373
 374 /* A flag indicating whether 'RX_PA_CFG_STRIP_VLAN_TAG' bit is set or not */
 375 static int vlan_strip_flag;
 376
 377 /* Unregister the vlan */
 378 static void s2io_vlan_rx_kill_vid(struct net_device *dev, unsigned long vid)
 379 {
 380         int i;
 381         struct s2io_nic *nic = dev->priv;
 382         unsigned long flags[MAX_TX_FIFOS];
 383         struct mac_info *mac_control = &nic->mac_control;
 384         struct config_param *config = &nic->config;
 385
 386         for (i = 0; i < config->tx_fifo_num; i++)
 387                 spin_lock_irqsave(&mac_control->fifos[i].tx_lock, flags[i]);
 388
 389         if (nic->vlgrp)
 390                 vlan_group_set_device(nic->vlgrp, vid, NULL);
 391
 392         for (i = config->tx_fifo_num - 1; i >= 0; i--)
 393                 spin_unlock_irqrestore(&mac_control->fifos[i].tx_lock,
 394                         flags[i]);
 395 }
 396
 397 /*
 398  * Constants to be programmed into the Xena's registers, to configure
 399  * the XAUI.
 400  */
 401
 402 #define END_SIGN        0x0
 403 static const u64 herc_act_dtx_cfg[] = {
 404         /* Set address */
 405         0x8000051536750000ULL, 0x80000515367500E0ULL,
 406         /* Write data */
 407         0x8000051536750004ULL, 0x80000515367500E4ULL,
 408         /* Set address */
 409         0x80010515003F0000ULL, 0x80010515003F00E0ULL,
 410         /* Write data */
 411         0x80010515003F0004ULL, 0x80010515003F00E4ULL,
 412         /* Set address */
 413         0x801205150D440000ULL, 0x801205150D4400E0ULL,
 414         /* Write data */
 415         0x801205150D440004ULL, 0x801205150D4400E4ULL,
 416         /* Set address */
 417         0x80020515F2100000ULL, 0x80020515F21000E0ULL,
 418         /* Write data */
 419         0x80020515F2100004ULL, 0x80020515F21000E4ULL,
 420         /* Done */
 421         END_SIGN
 422 };
 423
 424 static const u64 xena_dtx_cfg[] = {
 425         /* Set address */
 426         0x8000051500000000ULL, 0x80000515000000E0ULL,
 427         /* Write data */
 428         0x80000515D9350004ULL, 0x80000515D93500E4ULL,
 429         /* Set address */
 430         0x8001051500000000ULL, 0x80010515000000E0ULL,
 431         /* Write data */
 432         0x80010515001E0004ULL, 0x80010515001E00E4ULL,
 433         /* Set address */
 434         0x8002051500000000ULL, 0x80020515000000E0ULL,
 435         /* Write data */
 436         0x80020515F2100004ULL, 0x80020515F21000E4ULL,
 437         END_SIGN
 438 };
 439
 440 /*
 441  * Constants for Fixing the MacAddress problem seen mostly on
 442  * Alpha machines.
 443  */
 444 static const u64 fix_mac[] = {
 445         0x0060000000000000ULL, 0x0060600000000000ULL,
 446         0x0040600000000000ULL, 0x0000600000000000ULL,
 447         0x0020600000000000ULL, 0x0060600000000000ULL,
 448         0x0020600000000000ULL, 0x0060600000000000ULL,
 449         0x0020600000000000ULL, 0x0060600000000000ULL,
 450         0x0020600000000000ULL, 0x0060600000000000ULL,
 451         0x0020600000000000ULL, 0x0060600000000000ULL,
 452         0x0020600000000000ULL, 0x0060600000000000ULL,
 453         0x0020600000000000ULL, 0x0060600000000000ULL,
 454         0x0020600000000000ULL, 0x0060600000000000ULL,
 455         0x0020600000000000ULL, 0x0060600000000000ULL,
 456         0x0020600000000000ULL, 0x0060600000000000ULL,
 457         0x0020600000000000ULL, 0x0000600000000000ULL,
 458         0x0040600000000000ULL, 0x0060600000000000ULL,
 459         END_SIGN
 460 };
 461
 462 MODULE_LICENSE("GPL");
 463 MODULE_VERSION(DRV_VERSION);
 464
 465
 466 /* Module Loadable parameters. */
 467 S2IO_PARM_INT(tx_fifo_num, FIFO_DEFAULT_NUM);
 468 S2IO_PARM_INT(rx_ring_num, 1);
 469 S2IO_PARM_INT(multiq, 0);
 470 S2IO_PARM_INT(rx_ring_mode, 1);
 471 S2IO_PARM_INT(use_continuous_tx_intrs, 1);
 472 S2IO_PARM_INT(rmac_pause_time, 0x100);
 473 S2IO_PARM_INT(mc_pause_threshold_q0q3, 187);
 474 S2IO_PARM_INT(mc_pause_threshold_q4q7, 187);
 475 S2IO_PARM_INT(shared_splits, 0);
 476 S2IO_PARM_INT(tmac_util_period, 5);
 477 S2IO_PARM_INT(rmac_util_period, 5);
 478 S2IO_PARM_INT(l3l4hdr_size, 128);
 479 /* 0 is no steering, 1 is Priority steering, 2 is Default steering */
 480 S2IO_PARM_INT(tx_steering_type, TX_DEFAULT_STEERING);
 481 /* Frequency of Rx desc syncs expressed as power of 2 */
 482 S2IO_PARM_INT(rxsync_frequency, 3);
 483 /* Interrupt type. Values can be 0(INTA), 2(MSI_X) */
 484 S2IO_PARM_INT(intr_type, 2);
 485 /* Large receive offload feature */
 486 static unsigned int lro_enable;
 487 module_param_named(lro, lro_enable, uint, 0);
 488
 489 /* Max pkts to be aggregated by LRO at one time. If not specified,
 490  * aggregation happens until we hit max IP pkt size(64K)
 491  */
 492 S2IO_PARM_INT(lro_max_pkts, 0xFFFF);
 493 S2IO_PARM_INT(indicate_max_pkts, 0);
 494
 495 S2IO_PARM_INT(napi, 1);
 496 S2IO_PARM_INT(ufo, 0);
 497 S2IO_PARM_INT(vlan_tag_strip, NO_STRIP_IN_PROMISC);
 498
 499 static unsigned int tx_fifo_len[MAX_TX_FIFOS] =
 500     {DEFAULT_FIFO_0_LEN, [1 ...(MAX_TX_FIFOS - 1)] = DEFAULT_FIFO_1_7_LEN};
 501 static unsigned int rx_ring_sz[MAX_RX_RINGS] =
 502     {[0 ...(MAX_RX_RINGS - 1)] = SMALL_BLK_CNT};
 503 static unsigned int rts_frm_len[MAX_RX_RINGS] =
 504     {[0 ...(MAX_RX_RINGS - 1)] = 0 };
 505
 506 module_param_array(tx_fifo_len, uint, NULL, 0);
 507 module_param_array(rx_ring_sz, uint, NULL, 0);
 508 module_param_array(rts_frm_len, uint, NULL, 0);
 509
 510 /*
 511  * S2IO device table.
 512  * This table lists all the devices that this driver supports.
 513  */
 514 static struct pci_device_id s2io_tbl[] __devinitdata = {
 515         {PCI_VENDOR_ID_S2IO, PCI_DEVICE_ID_S2IO_WIN,
 516          PCI_ANY_ID, PCI_ANY_ID},
 517         {PCI_VENDOR_ID_S2IO, PCI_DEVICE_ID_S2IO_UNI,
 518          PCI_ANY_ID, PCI_ANY_ID},
 519         {PCI_VENDOR_ID_S2IO, PCI_DEVICE_ID_HERC_WIN,
 520          PCI_ANY_ID, PCI_ANY_ID},
 521         {PCI_VENDOR_ID_S2IO, PCI_DEVICE_ID_HERC_UNI,
 522          PCI_ANY_ID, PCI_ANY_ID},
 523         {0,}
 524 };
 525
 526 MODULE_DEVICE_TABLE(pci, s2io_tbl);
 527
 528 static struct pci_error_handlers s2io_err_handler = {
 529         .error_detected = s2io_io_error_detected,
 530         .slot_reset = s2io_io_slot_reset,
 531         .resume = s2io_io_resume,
 532 };
 533
 534 static struct pci_driver s2io_driver = {
 535       .name = "S2IO",
 536       .id_table = s2io_tbl,
 537       .probe = s2io_init_nic,
 538       .remove = __devexit_p(s2io_rem_nic),
 539       .err_handler = &s2io_err_handler,
 540 };
 541
 542 /* A simplifier macro used both by init and free shared_mem Fns(). */
 543 #define TXD_MEM_PAGE_CNT(len, per_each) ((len+per_each - 1) / per_each)
 544
 545 /* netqueue manipulation helper functions */
 546 static inline void s2io_stop_all_tx_queue(struct s2io_nic *sp)
 547 {
 548         int i;
 549 #ifdef CONFIG_NETDEVICES_MULTIQUEUE
 550         if (sp->config.multiq) {
 551                 for (i = 0; i < sp->config.tx_fifo_num; i++)
 552                         netif_stop_subqueue(sp->dev, i);
 553         } else
 554 #endif
 555         {
 556                 for (i = 0; i < sp->config.tx_fifo_num; i++)
 557                         sp->mac_control.fifos[i].queue_state = FIFO_QUEUE_STOP;
 558                 netif_stop_queue(sp->dev);
 559         }
 560 }
 561
 562 static inline void s2io_stop_tx_queue(struct s2io_nic *sp, int fifo_no)
 563 {
 564 #ifdef CONFIG_NETDEVICES_MULTIQUEUE
 565         if (sp->config.multiq)
 566                 netif_stop_subqueue(sp->dev, fifo_no);
 567         else
 568 #endif
 569         {
 570                 sp->mac_control.fifos[fifo_no].queue_state =
 571                         FIFO_QUEUE_STOP;
 572                 netif_stop_queue(sp->dev);
 573         }
 574 }
 575
 576 static inline void s2io_start_all_tx_queue(struct s2io_nic *sp)
 577 {
 578         int i;
 579 #ifdef CONFIG_NETDEVICES_MULTIQUEUE
 580         if (sp->config.multiq) {
 581                 for (i = 0; i < sp->config.tx_fifo_num; i++)
 582                         netif_start_subqueue(sp->dev, i);
 583         } else
 584 #endif
 585         {
 586                 for (i = 0; i < sp->config.tx_fifo_num; i++)
 587                         sp->mac_control.fifos[i].queue_state = FIFO_QUEUE_START;
 588                 netif_start_queue(sp->dev);
 589         }
 590 }
 591
 592 static inline void s2io_start_tx_queue(struct s2io_nic *sp, int fifo_no)
 593 {
 594 #ifdef CONFIG_NETDEVICES_MULTIQUEUE
 595         if (sp->config.multiq)
 596                 netif_start_subqueue(sp->dev, fifo_no);
 597         else
 598 #endif
 599         {
 600                 sp->mac_control.fifos[fifo_no].queue_state =
 601                         FIFO_QUEUE_START;
 602                 netif_start_queue(sp->dev);
 603         }
 604 }
 605
 606 static inline void s2io_wake_all_tx_queue(struct s2io_nic *sp)
 607 {
 608         int i;
 609 #ifdef CONFIG_NETDEVICES_MULTIQUEUE
 610         if (sp->config.multiq) {
 611                 for (i = 0; i < sp->config.tx_fifo_num; i++)
 612                         netif_wake_subqueue(sp->dev, i);
 613         } else
 614 #endif
 615         {
 616                 for (i = 0; i < sp->config.tx_fifo_num; i++)
 617                         sp->mac_control.fifos[i].queue_state = FIFO_QUEUE_START;
 618                 netif_wake_queue(sp->dev);
 619         }
 620 }
 621
 622 static inline void s2io_wake_tx_queue(
 623         struct fifo_info *fifo, int cnt, u8 multiq)
 624 {
 625
 626 #ifdef CONFIG_NETDEVICES_MULTIQUEUE
 627         if (multiq) {
 628                 if (cnt && __netif_subqueue_stopped(fifo->dev, fifo->fifo_no))
 629                         netif_wake_subqueue(fifo->dev, fifo->fifo_no);
 630         } else
 631 #endif
 632         if (cnt && (fifo->queue_state == FIFO_QUEUE_STOP)) {
 633                 if (netif_queue_stopped(fifo->dev)) {
 634                         fifo->queue_state = FIFO_QUEUE_START;
 635                         netif_wake_queue(fifo->dev);
 636                 }
 637         }
 638 }
 639
 640 /**
 641  * init_shared_mem - Allocation and Initialization of Memory
 642  * @nic: Device private variable.
 643  * Description: The function allocates all the memory areas shared
 644  * between the NIC and the driver. This includes Tx descriptors,
 645  * Rx descriptors and the statistics block.
 646  */
 647
 648 static int init_shared_mem(struct s2io_nic *nic)
 649 {
 650         u32 size;
 651         void *tmp_v_addr, *tmp_v_addr_next;
 652         dma_addr_t tmp_p_addr, tmp_p_addr_next;
 653         struct RxD_block *pre_rxd_blk = NULL;
 654         int i, j, blk_cnt;
 655         int lst_size, lst_per_page;
 656         struct net_device *dev = nic->dev;
 657         unsigned long tmp;
 658         struct buffAdd *ba;
 659
 660         struct mac_info *mac_control;
 661         struct config_param *config;
 662         unsigned long long mem_allocated = 0;
 663
 664         mac_control = &nic->mac_control;
 665         config = &nic->config;
 666
 667
 668         /* Allocation and initialization of TXDLs in FIOFs */
 669         size = 0;
 670         for (i = 0; i < config->tx_fifo_num; i++) {
 671                 size += config->tx_cfg[i].fifo_len;
 672         }
 673         if (size > MAX_AVAILABLE_TXDS) {
 674                 DBG_PRINT(ERR_DBG, "s2io: Requested TxDs too high, ");
 675                 DBG_PRINT(ERR_DBG, "Requested: %d, max supported: 8192\n", size);
 676                 return -EINVAL;
 677         }
 678
 679         size = 0;
 680         for (i = 0; i < config->tx_fifo_num; i++) {
 681                 size = config->tx_cfg[i].fifo_len;
 682                 /*
 683                  * Legal values are from 2 to 8192
 684                  */
 685                 if (size < 2) {
 686                         DBG_PRINT(ERR_DBG, "s2io: Invalid fifo len (%d)", size);
 687                         DBG_PRINT(ERR_DBG, "for fifo %d\n", i);
 688                         DBG_PRINT(ERR_DBG, "s2io: Legal values for fifo len"
 689                                 "are 2 to 8192\n");
 690                         return -EINVAL;
 691                 }
 692         }
 693
 694         lst_size = (sizeof(struct TxD) * config->max_txds);
 695         lst_per_page = PAGE_SIZE / lst_size;
 696
 697         for (i = 0; i < config->tx_fifo_num; i++) {
 698                 int fifo_len = config->tx_cfg[i].fifo_len;
 699                 int list_holder_size = fifo_len * sizeof(struct list_info_hold);
 700                 mac_control->fifos[i].list_info = kzalloc(list_holder_size,
 701                                                           GFP_KERNEL);
 702                 if (!mac_control->fifos[i].list_info) {
 703                         DBG_PRINT(INFO_DBG,
 704                                   "Malloc failed for list_info\n");
 705                         return -ENOMEM;
 706                 }
 707                 mem_allocated += list_holder_size;
 708         }
 709         for (i = 0; i < config->tx_fifo_num; i++) {
 710                 int page_num = TXD_MEM_PAGE_CNT(config->tx_cfg[i].fifo_len,
 711                                                 lst_per_page);
 712                 mac_control->fifos[i].tx_curr_put_info.offset = 0;
 713                 mac_control->fifos[i].tx_curr_put_info.fifo_len =
 714                     config->tx_cfg[i].fifo_len - 1;
 715                 mac_control->fifos[i].tx_curr_get_info.offset = 0;
 716                 mac_control->fifos[i].tx_curr_get_info.fifo_len =
 717                     config->tx_cfg[i].fifo_len - 1;
 718                 mac_control->fifos[i].fifo_no = i;
 719                 mac_control->fifos[i].nic = nic;
 720                 mac_control->fifos[i].max_txds = MAX_SKB_FRAGS + 2;
 721                 mac_control->fifos[i].dev = dev;
 722
 723                 for (j = 0; j < page_num; j++) {
 724                         int k = 0;
 725                         dma_addr_t tmp_p;
 726                         void *tmp_v;
 727                         tmp_v = pci_alloc_consistent(nic->pdev,
 728                                                      PAGE_SIZE, &tmp_p);
 729                         if (!tmp_v) {
 730                                 DBG_PRINT(INFO_DBG,
 731                                           "pci_alloc_consistent ");
 732                                 DBG_PRINT(INFO_DBG, "failed for TxDL\n");
 733                                 return -ENOMEM;
 734                         }
 735                         /* If we got a zero DMA address(can happen on
 736                          * certain platforms like PPC), reallocate.
 737                          * Store virtual address of page we don't want,
 738                          * to be freed later.
 739                          */
 740                         if (!tmp_p) {
 741                                 mac_control->zerodma_virt_addr = tmp_v;
 742                                 DBG_PRINT(INIT_DBG,
 743                                 "%s: Zero DMA address for TxDL. ", dev->name);
 744                                 DBG_PRINT(INIT_DBG,
 745                                 "Virtual address %p\n", tmp_v);
 746                                 tmp_v = pci_alloc_consistent(nic->pdev,
 747                                                      PAGE_SIZE, &tmp_p);
 748                                 if (!tmp_v) {
 749                                         DBG_PRINT(INFO_DBG,
 750                                           "pci_alloc_consistent ");
 751                                         DBG_PRINT(INFO_DBG, "failed for TxDL\n");
 752                                         return -ENOMEM;
 753                                 }
 754                                 mem_allocated += PAGE_SIZE;
 755                         }
 756                         while (k < lst_per_page) {
 757                                 int l = (j * lst_per_page) + k;
 758                                 if (l == config->tx_cfg[i].fifo_len)
 759                                         break;
 760                                 mac_control->fifos[i].list_info[l].list_virt_addr =
 761                                     tmp_v + (k * lst_size);
 762                                 mac_control->fifos[i].list_info[l].list_phy_addr =
 763                                     tmp_p + (k * lst_size);
 764                                 k++;
 765                         }
 766                 }
 767         }
 768
 769         for (i = 0; i < config->tx_fifo_num; i++) {
 770                 size = config->tx_cfg[i].fifo_len;
 771                 mac_control->fifos[i].ufo_in_band_v
 772                         = kcalloc(size, sizeof(u64), GFP_KERNEL);
 773                 if (!mac_control->fifos[i].ufo_in_band_v)
 774                         return -ENOMEM;
 775                 mem_allocated += (size * sizeof(u64));
 776         }
 777
 778         /* Allocation and initialization of RXDs in Rings */
 779         size = 0;
 780         for (i = 0; i < config->rx_ring_num; i++) {
 781                 if (config->rx_cfg[i].num_rxd %
 782                     (rxd_count[nic->rxd_mode] + 1)) {
 783                         DBG_PRINT(ERR_DBG, "%s: RxD count of ", dev->name);
 784                         DBG_PRINT(ERR_DBG, "Ring%d is not a multiple of ",
 785                                   i);
 786                         DBG_PRINT(ERR_DBG, "RxDs per Block");
 787                         return FAILURE;
 788                 }
 789                 size += config->rx_cfg[i].num_rxd;
 790                 mac_control->rings[i].block_count =
 791                         config->rx_cfg[i].num_rxd /
 792                         (rxd_count[nic->rxd_mode] + 1 );
 793                 mac_control->rings[i].pkt_cnt = config->rx_cfg[i].num_rxd -
 794                         mac_control->rings[i].block_count;
 795         }
 796         if (nic->rxd_mode == RXD_MODE_1)
 797                 size = (size * (sizeof(struct RxD1)));
 798         else
 799                 size = (size * (sizeof(struct RxD3)));
 800
 801         for (i = 0; i < config->rx_ring_num; i++) {
 802                 mac_control->rings[i].rx_curr_get_info.block_index = 0;
 803                 mac_control->rings[i].rx_curr_get_info.offset = 0;
 804                 mac_control->rings[i].rx_curr_get_info.ring_len =
 805                     config->rx_cfg[i].num_rxd - 1;
 806                 mac_control->rings[i].rx_curr_put_info.block_index = 0;
 807                 mac_control->rings[i].rx_curr_put_info.offset = 0;
 808                 mac_control->rings[i].rx_curr_put_info.ring_len =
 809                     config->rx_cfg[i].num_rxd - 1;
 810                 mac_control->rings[i].nic = nic;
 811                 mac_control->rings[i].ring_no = i;
 812                 mac_control->rings[i].lro = lro_enable;
 813
 814                 blk_cnt = config->rx_cfg[i].num_rxd /
 815                                 (rxd_count[nic->rxd_mode] + 1);
 816                 /*  Allocating all the Rx blocks */
 817                 for (j = 0; j < blk_cnt; j++) {
 818                         struct rx_block_info *rx_blocks;
 819                         int l;
 820
 821                         rx_blocks = &mac_control->rings[i].rx_blocks[j];
 822                         size = SIZE_OF_BLOCK; //size is always page size
 823                         tmp_v_addr = pci_alloc_consistent(nic->pdev, size,
 824                                                           &tmp_p_addr);
 825                         if (tmp_v_addr == NULL) {
 826                                 /*
 827                                  * In case of failure, free_shared_mem()
 828                                  * is called, which should free any
 829                                  * memory that was alloced till the
 830                                  * failure happened.
 831                                  */
 832                                 rx_blocks->block_virt_addr = tmp_v_addr;
 833                                 return -ENOMEM;
 834                         }
 835                         mem_allocated += size;
 836                         memset(tmp_v_addr, 0, size);
 837                         rx_blocks->block_virt_addr = tmp_v_addr;
 838                         rx_blocks->block_dma_addr = tmp_p_addr;
 839                         rx_blocks->rxds = kmalloc(sizeof(struct rxd_info)*
 840                                                   rxd_count[nic->rxd_mode],
 841                                                   GFP_KERNEL);
 842                         if (!rx_blocks->rxds)
 843                                 return -ENOMEM;
 844                         mem_allocated +=
 845                         (sizeof(struct rxd_info)* rxd_count[nic->rxd_mode]);
 846                         for (l=0; l<rxd_count[nic->rxd_mode];l++) {
 847                                 rx_blocks->rxds[l].virt_addr =
 848                                         rx_blocks->block_virt_addr +
 849                                         (rxd_size[nic->rxd_mode] * l);
 850                                 rx_blocks->rxds[l].dma_addr =
 851                                         rx_blocks->block_dma_addr +
 852                                         (rxd_size[nic->rxd_mode] * l);
 853                         }
 854                 }
 855                 /* Interlinking all Rx Blocks */
 856                 for (j = 0; j < blk_cnt; j++) {
 857                         tmp_v_addr =
 858                                 mac_control->rings[i].rx_blocks[j].block_virt_addr;
 859                         tmp_v_addr_next =
 860                                 mac_control->rings[i].rx_blocks[(j + 1) %
 861                                               blk_cnt].block_virt_addr;
 862                         tmp_p_addr =
 863                                 mac_control->rings[i].rx_blocks[j].block_dma_addr;
 864                         tmp_p_addr_next =
 865                                 mac_control->rings[i].rx_blocks[(j + 1) %
 866                                               blk_cnt].block_dma_addr;
 867
 868                         pre_rxd_blk = (struct RxD_block *) tmp_v_addr;
 869                         pre_rxd_blk->reserved_2_pNext_RxD_block =
 870                             (unsigned long) tmp_v_addr_next;
 871                         pre_rxd_blk->pNext_RxD_Blk_physical =
 872                             (u64) tmp_p_addr_next;
 873                 }
 874         }
 875         if (nic->rxd_mode == RXD_MODE_3B) {
 876                 /*
 877                  * Allocation of Storages for buffer addresses in 2BUFF mode
 878                  * and the buffers as well.
 879                  */
 880                 for (i = 0; i < config->rx_ring_num; i++) {
 881                         blk_cnt = config->rx_cfg[i].num_rxd /
 882                            (rxd_count[nic->rxd_mode]+ 1);
 883                         mac_control->rings[i].ba =
 884                                 kmalloc((sizeof(struct buffAdd *) * blk_cnt),
 885                                      GFP_KERNEL);
 886                         if (!mac_control->rings[i].ba)
 887                                 return -ENOMEM;
 888                         mem_allocated +=(sizeof(struct buffAdd *) * blk_cnt);
 889                         for (j = 0; j < blk_cnt; j++) {
 890                                 int k = 0;
 891                                 mac_control->rings[i].ba[j] =
 892                                         kmalloc((sizeof(struct buffAdd) *
 893                                                 (rxd_count[nic->rxd_mode] + 1)),
 894                                                 GFP_KERNEL);
 895                                 if (!mac_control->rings[i].ba[j])
 896                                         return -ENOMEM;
 897                                 mem_allocated += (sizeof(struct buffAdd) *  \
 898                                         (rxd_count[nic->rxd_mode] + 1));
 899                                 while (k != rxd_count[nic->rxd_mode]) {
 900                                         ba = &mac_control->rings[i].ba[j][k];
 901
 902                                         ba->ba_0_org = (void *) kmalloc
 903                                             (BUF0_LEN + ALIGN_SIZE, GFP_KERNEL);
 904                                         if (!ba->ba_0_org)
 905                                                 return -ENOMEM;
 906                                         mem_allocated +=
 907                                                 (BUF0_LEN + ALIGN_SIZE);
 908                                         tmp = (unsigned long)ba->ba_0_org;
 909                                         tmp += ALIGN_SIZE;
 910                                         tmp &= ~((unsigned long) ALIGN_SIZE);
 911                                         ba->ba_0 = (void *) tmp;
 912
 913                                         ba->ba_1_org = (void *) kmalloc
 914                                             (BUF1_LEN + ALIGN_SIZE, GFP_KERNEL);
 915                                         if (!ba->ba_1_org)
 916                                                 return -ENOMEM;
 917                                         mem_allocated
 918                                                 += (BUF1_LEN + ALIGN_SIZE);
 919                                         tmp = (unsigned long) ba->ba_1_org;
 920                                         tmp += ALIGN_SIZE;
 921                                         tmp &= ~((unsigned long) ALIGN_SIZE);
 922                                         ba->ba_1 = (void *) tmp;
 923                                         k++;
 924                                 }
 925                         }
 926                 }
 927         }
 928
 929         /* Allocation and initialization of Statistics block */
 930         size = sizeof(struct stat_block);
 931         mac_control->stats_mem = pci_alloc_consistent
 932             (nic->pdev, size, &mac_control->stats_mem_phy);
 933
 934         if (!mac_control->stats_mem) {
 935                 /*
 936                  * In case of failure, free_shared_mem() is called, which
 937                  * should free any memory that was alloced till the
 938                  * failure happened.
 939                  */
 940                 return -ENOMEM;
 941         }
 942         mem_allocated += size;
 943         mac_control->stats_mem_sz = size;
 944
 945         tmp_v_addr = mac_control->stats_mem;
 946         mac_control->stats_info = (struct stat_block *) tmp_v_addr;
 947         memset(tmp_v_addr, 0, size);
 948         DBG_PRINT(INIT_DBG, "%s:Ring Mem PHY: 0x%llx\n", dev->name,
 949                   (unsigned long long) tmp_p_addr);
 950         mac_control->stats_info->sw_stat.mem_allocated += mem_allocated;
 951         return SUCCESS;
 952 }
 953
 954 /**
 955  * free_shared_mem - Free the allocated Memory
 956  * @nic:  Device private variable.
 957  * Description: This function is to free all memory locations allocated by
 958  * the init_shared_mem() function and return it to the kernel.
 959  */
 960
 961 static void free_shared_mem(struct s2io_nic *nic)
 962 {
 963         int i, j, blk_cnt, size;
 964         void *tmp_v_addr;
 965         dma_addr_t tmp_p_addr;
 966         struct mac_info *mac_control;
 967         struct config_param *config;
 968         int lst_size, lst_per_page;
 969         struct net_device *dev;
 970         int page_num = 0;
 971
 972         if (!nic)
 973                 return;
 974
 975         dev = nic->dev;
 976
 977         mac_control = &nic->mac_control;
 978         config = &nic->config;
 979
 980         lst_size = (sizeof(struct TxD) * config->max_txds);
 981         lst_per_page = PAGE_SIZE / lst_size;
 982
 983         for (i = 0; i < config->tx_fifo_num; i++) {
 984                 page_num = TXD_MEM_PAGE_CNT(config->tx_cfg[i].fifo_len,
 985                                                         lst_per_page);
 986                 for (j = 0; j < page_num; j++) {
 987                         int mem_blks = (j * lst_per_page);
 988                         if (!mac_control->fifos[i].list_info)
 989                                 return;
 990                         if (!mac_control->fifos[i].list_info[mem_blks].
 991                                  list_virt_addr)
 992                                 break;
 993                         pci_free_consistent(nic->pdev, PAGE_SIZE,
 994                                             mac_control->fifos[i].
 995                                             list_info[mem_blks].
 996                                             list_virt_addr,
 997                                             mac_control->fifos[i].
 998                                             list_info[mem_blks].
 999                                             list_phy_addr);
1000                         nic->mac_control.stats_info->sw_stat.mem_freed
1001                                                 += PAGE_SIZE;
1002                 }
1003                 /* If we got a zero DMA address during allocation,
1004                  * free the page now
1005                  */
1006                 if (mac_control->zerodma_virt_addr) {
1007                         pci_free_consistent(nic->pdev, PAGE_SIZE,
1008                                             mac_control->zerodma_virt_addr,
1009                                             (dma_addr_t)0);
1010                         DBG_PRINT(INIT_DBG,
1011                                 "%s: Freeing TxDL with zero DMA addr. ",
1012                                 dev->name);
1013                         DBG_PRINT(INIT_DBG, "Virtual address %p\n",
1014                                 mac_control->zerodma_virt_addr);
1015                         nic->mac_control.stats_info->sw_stat.mem_freed
1016                                                 += PAGE_SIZE;
1017                 }
1018                 kfree(mac_control->fifos[i].list_info);
1019                 nic->mac_control.stats_info->sw_stat.mem_freed +=
1020                 (nic->config.tx_cfg[i].fifo_len *sizeof(struct list_info_hold));
1021         }
1022
1023         size = SIZE_OF_BLOCK;
1024         for (i = 0; i < config->rx_ring_num; i++) {
1025                 blk_cnt = mac_control->rings[i].block_count;
1026                 for (j = 0; j < blk_cnt; j++) {
1027                         tmp_v_addr = mac_control->rings[i].rx_blocks[j].
1028                                 block_virt_addr;
1029                         tmp_p_addr = mac_control->rings[i].rx_blocks[j].
1030                                 block_dma_addr;
1031                         if (tmp_v_addr == NULL)
1032                                 break;
1033                         pci_free_consistent(nic->pdev, size,
1034                                             tmp_v_addr, tmp_p_addr);
1035                         nic->mac_control.stats_info->sw_stat.mem_freed += size;
1036                         kfree(mac_control->rings[i].rx_blocks[j].rxds);
1037                         nic->mac_control.stats_info->sw_stat.mem_freed +=
1038                         ( sizeof(struct rxd_info)* rxd_count[nic->rxd_mode]);
1039                 }
1040         }
1041
1042         if (nic->rxd_mode == RXD_MODE_3B) {
1043                 /* Freeing buffer storage addresses in 2BUFF mode. */
1044                 for (i = 0; i < config->rx_ring_num; i++) {
1045                         blk_cnt = config->rx_cfg[i].num_rxd /
1046                             (rxd_count[nic->rxd_mode] + 1);
1047                         for (j = 0; j < blk_cnt; j++) {
1048                                 int k = 0;
1049                                 if (!mac_control->rings[i].ba[j])
1050                                         continue;
1051                                 while (k != rxd_count[nic->rxd_mode]) {
1052                                         struct buffAdd *ba =
1053                                                 &mac_control->rings[i].ba[j][k];
1054                                         kfree(ba->ba_0_org);
1055                                         nic->mac_control.stats_info->sw_stat.\
1056                                         mem_freed += (BUF0_LEN + ALIGN_SIZE);
1057                                         kfree(ba->ba_1_org);
1058                                         nic->mac_control.stats_info->sw_stat.\
1059                                         mem_freed += (BUF1_LEN + ALIGN_SIZE);
1060                                         k++;
1061                                 }
1062                                 kfree(mac_control->rings[i].ba[j]);
1063                                 nic->mac_control.stats_info->sw_stat.mem_freed +=
1064                                         (sizeof(struct buffAdd) *
1065                                         (rxd_count[nic->rxd_mode] + 1));
1066                         }
1067                         kfree(mac_control->rings[i].ba);
1068                         nic->mac_control.stats_info->sw_stat.mem_freed +=
1069                         (sizeof(struct buffAdd *) * blk_cnt);
1070                 }
1071         }
1072
1073         for (i = 0; i < nic->config.tx_fifo_num; i++) {
1074                 if (mac_control->fifos[i].ufo_in_band_v) {
1075                         nic->mac_control.stats_info->sw_stat.mem_freed
1076                                 += (config->tx_cfg[i].fifo_len * sizeof(u64));
1077                         kfree(mac_control->fifos[i].ufo_in_band_v);
1078                 }
1079         }
1080
1081         if (mac_control->stats_mem) {
1082                 nic->mac_control.stats_info->sw_stat.mem_freed +=
1083                         mac_control->stats_mem_sz;
1084                 pci_free_consistent(nic->pdev,
1085                                     mac_control->stats_mem_sz,
1086                                     mac_control->stats_mem,
1087                                     mac_control->stats_mem_phy);
1088         }
1089 }
1090
1091 /**
1092  * s2io_verify_pci_mode -
1093  */
1094
1095 static int s2io_verify_pci_mode(struct s2io_nic *nic)
1096 {
1097         struct XENA_dev_config __iomem *bar0 = nic->bar0;
1098         register u64 val64 = 0;
1099         int     mode;
1100
1101         val64 = readq(&bar0->pci_mode);
1102         mode = (u8)GET_PCI_MODE(val64);
1103
1104         if ( val64 & PCI_MODE_UNKNOWN_MODE)
1105                 return -1;      /* Unknown PCI mode */
1106         return mode;
1107 }
1108
1109 #define NEC_VENID   0x1033
1110 #define NEC_DEVID   0x0125
1111 static int s2io_on_nec_bridge(struct pci_dev *s2io_pdev)
1112 {
1113         struct pci_dev *tdev = NULL;
1114         while ((tdev = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, tdev)) != NULL) {
1115                 if (tdev->vendor == NEC_VENID && tdev->device == NEC_DEVID) {
1116                         if (tdev->bus == s2io_pdev->bus->parent) {
1117                                 pci_dev_put(tdev);
1118                                 return 1;
1119                         }
1120                 }
1121         }
1122         return 0;
1123 }
1124
1125 static int bus_speed[8] = {33, 133, 133, 200, 266, 133, 200, 266};
1126 /**
1127  * s2io_print_pci_mode -
1128  */
1129 static int s2io_print_pci_mode(struct s2io_nic *nic)
1130 {
1131         struct XENA_dev_config __iomem *bar0 = nic->bar0;
1132         register u64 val64 = 0;
1133         int     mode;
1134         struct config_param *config = &nic->config;
1135
1136         val64 = readq(&bar0->pci_mode);
1137         mode = (u8)GET_PCI_MODE(val64);
1138
1139         if ( val64 & PCI_MODE_UNKNOWN_MODE)
1140                 return -1;      /* Unknown PCI mode */
1141
1142         config->bus_speed = bus_speed[mode];
1143
1144         if (s2io_on_nec_bridge(nic->pdev)) {
1145                 DBG_PRINT(ERR_DBG, "%s: Device is on PCI-E bus\n",
1146                                                         nic->dev->name);
1147                 return mode;
1148         }
1149
1150         if (val64 & PCI_MODE_32_BITS) {
1151                 DBG_PRINT(ERR_DBG, "%s: Device is on 32 bit ", nic->dev->name);
1152         } else {
1153                 DBG_PRINT(ERR_DBG, "%s: Device is on 64 bit ", nic->dev->name);
1154         }
1155
1156         switch(mode) {
1157                 case PCI_MODE_PCI_33:
1158                         DBG_PRINT(ERR_DBG, "33MHz PCI bus\n");
1159                         break;
1160                 case PCI_MODE_PCI_66:
1161                         DBG_PRINT(ERR_DBG, "66MHz PCI bus\n");
1162                         break;
1163                 case PCI_MODE_PCIX_M1_66:
1164                         DBG_PRINT(ERR_DBG, "66MHz PCIX(M1) bus\n");
1165                         break;
1166                 case PCI_MODE_PCIX_M1_100:
1167                         DBG_PRINT(ERR_DBG, "100MHz PCIX(M1) bus\n");
1168                         break;
1169                 case PCI_MODE_PCIX_M1_133:
1170                         DBG_PRINT(ERR_DBG, "133MHz PCIX(M1) bus\n");
1171                         break;
1172                 case PCI_MODE_PCIX_M2_66:
1173                         DBG_PRINT(ERR_DBG, "133MHz PCIX(M2) bus\n");
1174                         break;
1175                 case PCI_MODE_PCIX_M2_100:
1176                         DBG_PRINT(ERR_DBG, "200MHz PCIX(M2) bus\n");
1177                         break;
1178                 case PCI_MODE_PCIX_M2_133:
1179                         DBG_PRINT(ERR_DBG, "266MHz PCIX(M2) bus\n");
1180                         break;
1181                 default:
1182                         return -1;      /* Unsupported bus speed */
1183         }
1184
1185         return mode;
1186 }
1187
1188 /**
1189  *  init_tti - Initialization transmit traffic interrupt scheme
1190  *  @nic: device private variable
1191  *  @link: link status (UP/DOWN) used to enable/disable continuous
1192  *  transmit interrupts
1193  *  Description: The function configures transmit traffic interrupts
1194  *  Return Value:  SUCCESS on success and
1195  *  '-1' on failure
1196  */
1197
1198 static int init_tti(struct s2io_nic *nic, int link)
1199 {
1200         struct XENA_dev_config __iomem *bar0 = nic->bar0;
1201         register u64 val64 = 0;
1202         int i;
1203         struct config_param *config;
1204
1205         config = &nic->config;
1206
1207         for (i = 0; i < config->tx_fifo_num; i++) {
1208                 /*
1209                  * TTI Initialization. Default Tx timer gets us about
1210                  * 250 interrupts per sec. Continuous interrupts are enabled
1211                  * by default.
1212                  */
1213                 if (nic->device_type == XFRAME_II_DEVICE) {
1214                         int count = (nic->config.bus_speed * 125)/2;
1215                         val64 = TTI_DATA1_MEM_TX_TIMER_VAL(count);
1216                 } else
1217                         val64 = TTI_DATA1_MEM_TX_TIMER_VAL(0x2078);
1218
1219                 val64 |= TTI_DATA1_MEM_TX_URNG_A(0xA) |
1220                                 TTI_DATA1_MEM_TX_URNG_B(0x10) |
1221                                 TTI_DATA1_MEM_TX_URNG_C(0x30) |
1222                                 TTI_DATA1_MEM_TX_TIMER_AC_EN;
1223                 if (i == 0)
1224                         if (use_continuous_tx_intrs && (link == LINK_UP))
1225                                 val64 |= TTI_DATA1_MEM_TX_TIMER_CI_EN;
1226                 writeq(val64, &bar0->tti_data1_mem);
1227
1228                 if (nic->config.intr_type == MSI_X) {
1229                         val64 = TTI_DATA2_MEM_TX_UFC_A(0x10) |
1230                                 TTI_DATA2_MEM_TX_UFC_B(0x100) |
1231                                 TTI_DATA2_MEM_TX_UFC_C(0x200) |
1232                                 TTI_DATA2_MEM_TX_UFC_D(0x300);
1233                 } else {
1234                         if ((nic->config.tx_steering_type ==
1235                                 TX_DEFAULT_STEERING) &&
1236                                 (config->tx_fifo_num > 1) &&
1237                                 (i >= nic->udp_fifo_idx) &&
1238                                 (i < (nic->udp_fifo_idx +
1239                                 nic->total_udp_fifos)))
1240                                 val64 = TTI_DATA2_MEM_TX_UFC_A(0x50) |
1241                                         TTI_DATA2_MEM_TX_UFC_B(0x80) |
1242                                         TTI_DATA2_MEM_TX_UFC_C(0x100) |
1243                                         TTI_DATA2_MEM_TX_UFC_D(0x120);
1244                         else
1245                                 val64 = TTI_DATA2_MEM_TX_UFC_A(0x10) |
1246                                         TTI_DATA2_MEM_TX_UFC_B(0x20) |
1247                                         TTI_DATA2_MEM_TX_UFC_C(0x40) |
1248                                         TTI_DATA2_MEM_TX_UFC_D(0x80);
1249                 }
1250
1251                 writeq(val64, &bar0->tti_data2_mem);
1252
1253                 val64 = TTI_CMD_MEM_WE | TTI_CMD_MEM_STROBE_NEW_CMD |
1254                                 TTI_CMD_MEM_OFFSET(i);
1255                 writeq(val64, &bar0->tti_command_mem);
1256
1257                 if (wait_for_cmd_complete(&bar0->tti_command_mem,
1258                         TTI_CMD_MEM_STROBE_NEW_CMD, S2IO_BIT_RESET) != SUCCESS)
1259                         return FAILURE;
1260         }
1261
1262         return SUCCESS;
1263 }
1264
1265 /**
1266  *  init_nic - Initialization of hardware
1267  *  @nic: device private variable
1268  *  Description: The function sequentially configures every block
1269  *  of the H/W from their reset values.
1270  *  Return Value:  SUCCESS on success and
1271  *  '-1' on failure (endian settings incorrect).
1272  */
1273
1274 static int init_nic(struct s2io_nic *nic)
1275 {
1276         struct XENA_dev_config __iomem *bar0 = nic->bar0;
1277         struct net_device *dev = nic->dev;
1278         register u64 val64 = 0;
1279         void __iomem *add;
1280         u32 time;
1281         int i, j;
1282         struct mac_info *mac_control;
1283         struct config_param *config;
1284         int dtx_cnt = 0;
1285         unsigned long long mem_share;
1286         int mem_size;
1287
1288         mac_control = &nic->mac_control;
1289         config = &nic->config;
1290
1291         /* to set the swapper controle on the card */
1292         if(s2io_set_swapper(nic)) {
1293                 DBG_PRINT(ERR_DBG,"ERROR: Setting Swapper failed\n");
1294                 return -EIO;
1295         }
1296
1297         /*
1298          * Herc requires EOI to be removed from reset before XGXS, so..
1299          */
1300         if (nic->device_type & XFRAME_II_DEVICE) {
1301                 val64 = 0xA500000000ULL;
1302                 writeq(val64, &bar0->sw_reset);
1303                 msleep(500);
1304                 val64 = readq(&bar0->sw_reset);
1305         }
1306
1307         /* Remove XGXS from reset state */
1308         val64 = 0;
1309         writeq(val64, &bar0->sw_reset);
1310         msleep(500);
1311         val64 = readq(&bar0->sw_reset);
1312
1313         /* Ensure that it's safe to access registers by checking
1314          * RIC_RUNNING bit is reset. Check is valid only for XframeII.
1315          */
1316         if (nic->device_type == XFRAME_II_DEVICE) {
1317                 for (i = 0; i < 50; i++) {
1318                         val64 = readq(&bar0->adapter_status);
1319                         if (!(val64 & ADAPTER_STATUS_RIC_RUNNING))
1320                                 break;
1321                         msleep(10);
1322                 }
1323                 if (i == 50)
1324                         return -ENODEV;
1325         }
1326
1327         /*  Enable Receiving broadcasts */
1328         add = &bar0->mac_cfg;
1329         val64 = readq(&bar0->mac_cfg);
1330         val64 |= MAC_RMAC_BCAST_ENABLE;
1331         writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
1332         writel((u32) val64, add);
1333         writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
1334         writel((u32) (val64 >> 32), (add + 4));
1335
1336         /* Read registers in all blocks */
1337         val64 = readq(&bar0->mac_int_mask);
1338         val64 = readq(&bar0->mc_int_mask);
1339         val64 = readq(&bar0->xgxs_int_mask);
1340
1341         /*  Set MTU */
1342         val64 = dev->mtu;
1343         writeq(vBIT(val64, 2, 14), &bar0->rmac_max_pyld_len);
1344
1345         if (nic->device_type & XFRAME_II_DEVICE) {
1346                 while (herc_act_dtx_cfg[dtx_cnt] != END_SIGN) {
1347                         SPECIAL_REG_WRITE(herc_act_dtx_cfg[dtx_cnt],
1348                                           &bar0->dtx_control, UF);
1349                         if (dtx_cnt & 0x1)
1350                                 msleep(1); /* Necessary!! */
1351                         dtx_cnt++;
1352                 }
1353         } else {
1354                 while (xena_dtx_cfg[dtx_cnt] != END_SIGN) {
1355                         SPECIAL_REG_WRITE(xena_dtx_cfg[dtx_cnt],
1356                                           &bar0->dtx_control, UF);
1357                         val64 = readq(&bar0->dtx_control);
1358                         dtx_cnt++;
1359                 }
1360         }
1361
1362         /*  Tx DMA Initialization */
1363         val64 = 0;
1364         writeq(val64, &bar0->tx_fifo_partition_0);
1365         writeq(val64, &bar0->tx_fifo_partition_1);
1366         writeq(val64, &bar0->tx_fifo_partition_2);
1367         writeq(val64, &bar0->tx_fifo_partition_3);
1368
1369
1370         for (i = 0, j = 0; i < config->tx_fifo_num; i++) {
1371                 val64 |=
1372                     vBIT(config->tx_cfg[i].fifo_len - 1, ((j * 32) + 19),
1373                          13) | vBIT(config->tx_cfg[i].fifo_priority,
1374                                     ((j * 32) + 5), 3);
1375
1376                 if (i == (config->tx_fifo_num - 1)) {
1377                         if (i % 2 == 0)
1378                                 i++;
1379                 }
1380
1381                 switch (i) {
1382                 case 1:
1383                         writeq(val64, &bar0->tx_fifo_partition_0);
1384                         val64 = 0;
1385                         j = 0;
1386                         break;
1387                 case 3:
1388                         writeq(val64, &bar0->tx_fifo_partition_1);
1389                         val64 = 0;
1390                         j = 0;
1391                         break;
1392                 case 5:
1393                         writeq(val64, &bar0->tx_fifo_partition_2);
1394                         val64 = 0;
1395                         j = 0;
1396                         break;
1397                 case 7:
1398                         writeq(val64, &bar0->tx_fifo_partition_3);
1399                         val64 = 0;
1400                         j = 0;
1401                         break;
1402                 default:
1403                         j++;
1404                         break;
1405                 }
1406         }
1407
1408         /*
1409          * Disable 4 PCCs for Xena1, 2 and 3 as per H/W bug
1410          * SXE-008 TRANSMIT DMA ARBITRATION ISSUE.
1411          */
1412         if ((nic->device_type == XFRAME_I_DEVICE) &&
1413                 (nic->pdev->revision < 4))
1414                 writeq(PCC_ENABLE_FOUR, &bar0->pcc_enable);
1415
1416         val64 = readq(&bar0->tx_fifo_partition_0);
1417         DBG_PRINT(INIT_DBG, "Fifo partition at: 0x%p is: 0x%llx\n",
1418                   &bar0->tx_fifo_partition_0, (unsigned long long) val64);
1419
1420         /*
1421          * Initialization of Tx_PA_CONFIG register to ignore packet
1422          * integrity checking.
1423          */
1424         val64 = readq(&bar0->tx_pa_cfg);
1425         val64 |= TX_PA_CFG_IGNORE_FRM_ERR | TX_PA_CFG_IGNORE_SNAP_OUI |
1426             TX_PA_CFG_IGNORE_LLC_CTRL | TX_PA_CFG_IGNORE_L2_ERR;
1427         writeq(val64, &bar0->tx_pa_cfg);
1428
1429         /* Rx DMA intialization. */
1430         val64 = 0;
1431         for (i = 0; i < config->rx_ring_num; i++) {
1432                 val64 |=
1433                     vBIT(config->rx_cfg[i].ring_priority, (5 + (i * 8)),
1434                          3);
1435         }
1436         writeq(val64, &bar0->rx_queue_priority);
1437
1438         /*
1439          * Allocating equal share of memory to all the
1440          * configured Rings.
1441          */
1442         val64 = 0;
1443         if (nic->device_type & XFRAME_II_DEVICE)
1444                 mem_size = 32;
1445         else
1446                 mem_size = 64;
1447
1448         for (i = 0; i < config->rx_ring_num; i++) {
1449                 switch (i) {
1450                 case 0:
1451                         mem_share = (mem_size / config->rx_ring_num +
1452                                      mem_size % config->rx_ring_num);
1453                         val64 |= RX_QUEUE_CFG_Q0_SZ(mem_share);
1454                         continue;
1455                 case 1:
1456                         mem_share = (mem_size / config->rx_ring_num);
1457                         val64 |= RX_QUEUE_CFG_Q1_SZ(mem_share);
1458                         continue;
1459                 case 2:
1460                         mem_share = (mem_size / config->rx_ring_num);
1461                         val64 |= RX_QUEUE_CFG_Q2_SZ(mem_share);
1462                         continue;
1463                 case 3:
1464                         mem_share = (mem_size / config->rx_ring_num);
1465                         val64 |= RX_QUEUE_CFG_Q3_SZ(mem_share);
1466                         continue;
1467                 case 4:
1468                         mem_share = (mem_size / config->rx_ring_num);
1469                         val64 |= RX_QUEUE_CFG_Q4_SZ(mem_share);
1470                         continue;
1471                 case 5:
1472                         mem_share = (mem_size / config->rx_ring_num);
1473                         val64 |= RX_QUEUE_CFG_Q5_SZ(mem_share);
1474                         continue;
1475                 case 6:
1476                         mem_share = (mem_size / config->rx_ring_num);
1477                         val64 |= RX_QUEUE_CFG_Q6_SZ(mem_share);
1478                         continue;
1479                 case 7:
1480                         mem_share = (mem_size / config->rx_ring_num);
1481                         val64 |= RX_QUEUE_CFG_Q7_SZ(mem_share);
1482                         continue;
1483                 }
1484         }
1485         writeq(val64, &bar0->rx_queue_cfg);
1486
1487         /*
1488          * Filling Tx round robin registers
1489          * as per the number of FIFOs for equal scheduling priority
1490          */
1491         switch (config->tx_fifo_num) {
1492         case 1:
1493                 val64 = 0x0;
1494                 writeq(val64, &bar0->tx_w_round_robin_0);
1495                 writeq(val64, &bar0->tx_w_round_robin_1);
1496                 writeq(val64, &bar0->tx_w_round_robin_2);
1497                 writeq(val64, &bar0->tx_w_round_robin_3);
1498                 writeq(val64, &bar0->tx_w_round_robin_4);
1499                 break;
1500         case 2:
1501                 val64 = 0x0001000100010001ULL;
1502                 writeq(val64, &bar0->tx_w_round_robin_0);
1503                 writeq(val64, &bar0->tx_w_round_robin_1);
1504                 writeq(val64, &bar0->tx_w_round_robin_2);
1505                 writeq(val64, &bar0->tx_w_round_robin_3);
1506                 val64 = 0x0001000100000000ULL;
1507                 writeq(val64, &bar0->tx_w_round_robin_4);
1508                 break;
1509         case 3:
1510                 val64 = 0x0001020001020001ULL;
1511                 writeq(val64, &bar0->tx_w_round_robin_0);
1512                 val64 = 0x0200010200010200ULL;
1513                 writeq(val64, &bar0->tx_w_round_robin_1);
1514                 val64 = 0x0102000102000102ULL;
1515                 writeq(val64, &bar0->tx_w_round_robin_2);
1516                 val64 = 0x0001020001020001ULL;
1517                 writeq(val64, &bar0->tx_w_round_robin_3);
1518                 val64 = 0x0200010200000000ULL;
1519                 writeq(val64, &bar0->tx_w_round_robin_4);
1520                 break;
1521         case 4:
1522                 val64 = 0x0001020300010203ULL;
1523                 writeq(val64, &bar0->tx_w_round_robin_0);
1524                 writeq(val64, &bar0->tx_w_round_robin_1);
1525                 writeq(val64, &bar0->tx_w_round_robin_2);
1526                 writeq(val64, &bar0->tx_w_round_robin_3);
1527                 val64 = 0x0001020300000000ULL;
1528                 writeq(val64, &bar0->tx_w_round_robin_4);
1529                 break;
1530         case 5:
1531                 val64 = 0x0001020304000102ULL;
1532                 writeq(val64, &bar0->tx_w_round_robin_0);
1533                 val64 = 0x0304000102030400ULL;
1534                 writeq(val64, &bar0->tx_w_round_robin_1);
1535                 val64 = 0x0102030400010203ULL;
1536                 writeq(val64, &bar0->tx_w_round_robin_2);
1537                 val64 = 0x0400010203040001ULL;
1538                 writeq(val64, &bar0->tx_w_round_robin_3);
1539                 val64 = 0x0203040000000000ULL;
1540                 writeq(val64, &bar0->tx_w_round_robin_4);
1541                 break;
1542         case 6:
1543                 val64 = 0x0001020304050001ULL;
1544                 writeq(val64, &bar0->tx_w_round_robin_0);
1545                 val64 = 0x0203040500010203ULL;
1546                 writeq(val64, &bar0->tx_w_round_robin_1);
1547                 val64 = 0x0405000102030405ULL;
1548                 writeq(val64, &bar0->tx_w_round_robin_2);
1549                 val64 = 0x0001020304050001ULL;
1550                 writeq(val64, &bar0->tx_w_round_robin_3);
1551                 val64 = 0x0203040500000000ULL;
1552                 writeq(val64, &bar0->tx_w_round_robin_4);
1553                 break;
1554         case 7:
1555                 val64 = 0x0001020304050600ULL;
1556                 writeq(val64, &bar0->tx_w_round_robin_0);
1557                 val64 = 0x0102030405060001ULL;
1558                 writeq(val64, &bar0->tx_w_round_robin_1);
1559                 val64 = 0x0203040506000102ULL;
1560                 writeq(val64, &bar0->tx_w_round_robin_2);
1561                 val64 = 0x0304050600010203ULL;
1562                 writeq(val64, &bar0->tx_w_round_robin_3);
1563                 val64 = 0x0405060000000000ULL;
1564                 writeq(val64, &bar0->tx_w_round_robin_4);
1565                 break;
1566         case 8:
1567                 val64 = 0x0001020304050607ULL;
1568                 writeq(val64, &bar0->tx_w_round_robin_0);
1569                 writeq(val64, &bar0->tx_w_round_robin_1);
1570                 writeq(val64, &bar0->tx_w_round_robin_2);
1571                 writeq(val64, &bar0->tx_w_round_robin_3);
1572                 val64 = 0x0001020300000000ULL;
1573                 writeq(val64, &bar0->tx_w_round_robin_4);
1574                 break;
1575         }
1576
1577         /* Enable all configured Tx FIFO partitions */
1578         val64 = readq(&bar0->tx_fifo_partition_0);
1579         val64 |= (TX_FIFO_PARTITION_EN);
1580         writeq(val64, &bar0->tx_fifo_partition_0);
1581
1582         /* Filling the Rx round robin registers as per the
1583          * number of Rings and steering based on QoS with
1584          * equal priority.
1585          */
1586         switch (config->rx_ring_num) {
1587         case 1:
1588                 val64 = 0x0;
1589                 writeq(val64, &bar0->rx_w_round_robin_0);
1590                 writeq(val64, &bar0->rx_w_round_robin_1);
1591                 writeq(val64, &bar0->rx_w_round_robin_2);
1592                 writeq(val64, &bar0->rx_w_round_robin_3);
1593                 writeq(val64, &bar0->rx_w_round_robin_4);
1594
1595                 val64 = 0x8080808080808080ULL;
1596                 writeq(val64, &bar0->rts_qos_steering);
1597                 break;
1598         case 2:
1599                 val64 = 0x0001000100010001ULL;
1600                 writeq(val64, &bar0->rx_w_round_robin_0);
1601                 writeq(val64, &bar0->rx_w_round_robin_1);
1602                 writeq(val64, &bar0->rx_w_round_robin_2);
1603                 writeq(val64, &bar0->rx_w_round_robin_3);
1604                 val64 = 0x0001000100000000ULL;
1605                 writeq(val64, &bar0->rx_w_round_robin_4);
1606
1607                 val64 = 0x8080808040404040ULL;
1608                 writeq(val64, &bar0->rts_qos_steering);
1609                 break;
1610         case 3:
1611                 val64 = 0x0001020001020001ULL;
1612                 writeq(val64, &bar0->rx_w_round_robin_0);
1613                 val64 = 0x0200010200010200ULL;
1614                 writeq(val64, &bar0->rx_w_round_robin_1);
1615                 val64 = 0x0102000102000102ULL;
1616                 writeq(val64, &bar0->rx_w_round_robin_2);
1617                 val64 = 0x0001020001020001ULL;
1618                 writeq(val64, &bar0->rx_w_round_robin_3);
1619                 val64 = 0x0200010200000000ULL;
1620                 writeq(val64, &bar0->rx_w_round_robin_4);
1621
1622                 val64 = 0x8080804040402020ULL;
1623                 writeq(val64, &bar0->rts_qos_steering);
1624                 break;
1625         case 4:
1626                 val64 = 0x0001020300010203ULL;
1627                 writeq(val64, &bar0->rx_w_round_robin_0);
1628                 writeq(val64, &bar0->rx_w_round_robin_1);
1629                 writeq(val64, &bar0->rx_w_round_robin_2);
1630                 writeq(val64, &bar0->rx_w_round_robin_3);
1631                 val64 = 0x0001020300000000ULL;
1632                 writeq(val64, &bar0->rx_w_round_robin_4);
1633
1634                 val64 = 0x8080404020201010ULL;
1635                 writeq(val64, &bar0->rts_qos_steering);
1636                 break;
1637         case 5:
1638                 val64 = 0x0001020304000102ULL;
1639                 writeq(val64, &bar0->rx_w_round_robin_0);
1640                 val64 = 0x0304000102030400ULL;
1641                 writeq(val64, &bar0->rx_w_round_robin_1);
1642                 val64 = 0x0102030400010203ULL;
1643                 writeq(val64, &bar0->rx_w_round_robin_2);
1644                 val64 = 0x0400010203040001ULL;
1645                 writeq(val64, &bar0->rx_w_round_robin_3);
1646                 val64 = 0x0203040000000000ULL;
1647                 writeq(val64, &bar0->rx_w_round_robin_4);
1648
1649                 val64 = 0x8080404020201008ULL;
1650                 writeq(val64, &bar0->rts_qos_steering);
1651                 break;
1652         case 6:
1653                 val64 = 0x0001020304050001ULL;
1654                 writeq(val64, &bar0->rx_w_round_robin_0);
1655                 val64 = 0x0203040500010203ULL;
1656                 writeq(val64, &bar0->rx_w_round_robin_1);
1657                 val64 = 0x0405000102030405ULL;
1658                 writeq(val64, &bar0->rx_w_round_robin_2);
1659                 val64 = 0x0001020304050001ULL;
1660                 writeq(val64, &bar0->rx_w_round_robin_3);
1661                 val64 = 0x0203040500000000ULL;
1662                 writeq(val64, &bar0->rx_w_round_robin_4);
1663
1664                 val64 = 0x8080404020100804ULL;
1665                 writeq(val64, &bar0->rts_qos_steering);
1666                 break;
1667         case 7:
1668                 val64 = 0x0001020304050600ULL;
1669                 writeq(val64, &bar0->rx_w_round_robin_0);
1670                 val64 = 0x0102030405060001ULL;
1671                 writeq(val64, &bar0->rx_w_round_robin_1);
1672                 val64 = 0x0203040506000102ULL;
1673                 writeq(val64, &bar0->rx_w_round_robin_2);
1674                 val64 = 0x0304050600010203ULL;
1675                 writeq(val64, &bar0->rx_w_round_robin_3);
1676                 val64 = 0x0405060000000000ULL;
1677                 writeq(val64, &bar0->rx_w_round_robin_4);
1678
1679                 val64 = 0x8080402010080402ULL;
1680                 writeq(val64, &bar0->rts_qos_steering);
1681                 break;
1682         case 8:
1683                 val64 = 0x0001020304050607ULL;
1684                 writeq(val64, &bar0->rx_w_round_robin_0);
1685                 writeq(val64, &bar0->rx_w_round_robin_1);
1686                 writeq(val64, &bar0->rx_w_round_robin_2);
1687                 writeq(val64, &bar0->rx_w_round_robin_3);
1688                 val64 = 0x0001020300000000ULL;
1689                 writeq(val64, &bar0->rx_w_round_robin_4);
1690
1691                 val64 = 0x8040201008040201ULL;
1692                 writeq(val64, &bar0->rts_qos_steering);
1693                 break;
1694         }
1695
1696         /* UDP Fix */
1697         val64 = 0;
1698         for (i = 0; i < 8; i++)
1699                 writeq(val64, &bar0->rts_frm_len_n[i]);
1700
1701         /* Set the default rts frame length for the rings configured */
1702         val64 = MAC_RTS_FRM_LEN_SET(dev->mtu+22);
1703         for (i = 0 ; i < config->rx_ring_num ; i++)
1704                 writeq(val64, &bar0->rts_frm_len_n[i]);
1705
1706         /* Set the frame length for the configured rings
1707          * desired by the user
1708          */
1709         for (i = 0; i < config->rx_ring_num; i++) {
1710                 /* If rts_frm_len[i] == 0 then it is assumed that user not
1711                  * specified frame length steering.
1712                  * If the user provides the frame length then program
1713                  * the rts_frm_len register for those values or else
1714                  * leave it as it is.
1715                  */
1716                 if (rts_frm_len[i] != 0) {
1717                         writeq(MAC_RTS_FRM_LEN_SET(rts_frm_len[i]),
1718                                 &bar0->rts_frm_len_n[i]);
1719                 }
1720         }
1721
1722         /* Disable differentiated services steering logic */
1723         for (i = 0; i < 64; i++) {
1724                 if (rts_ds_steer(nic, i, 0) == FAILURE) {
1725                         DBG_PRINT(ERR_DBG, "%s: failed rts ds steering",
1726                                 dev->name);
1727                         DBG_PRINT(ERR_DBG, "set on codepoint %d\n", i);
1728                         return -ENODEV;
1729                 }
1730         }
1731
1732         /* Program statistics memory */
1733         writeq(mac_control->stats_mem_phy, &bar0->stat_addr);
1734
1735         if (nic->device_type == XFRAME_II_DEVICE) {
1736                 val64 = STAT_BC(0x320);
1737                 writeq(val64, &bar0->stat_byte_cnt);
1738         }
1739
1740         /*
1741          * Initializing the sampling rate for the device to calculate the
1742          * bandwidth utilization.
1743          */
1744         val64 = MAC_TX_LINK_UTIL_VAL(tmac_util_period) |
1745             MAC_RX_LINK_UTIL_VAL(rmac_util_period);
1746         writeq(val64, &bar0->mac_link_util);
1747
1748         /*
1749          * Initializing the Transmit and Receive Traffic Interrupt
1750          * Scheme.
1751          */
1752
1753         /* Initialize TTI */
1754         if (SUCCESS != init_tti(nic, nic->last_link_state))
1755                 return -ENODEV;
1756
1757         /* RTI Initialization */
1758         if (nic->device_type == XFRAME_II_DEVICE) {
1759                 /*
1760                  * Programmed to generate Apprx 500 Intrs per
1761                  * second
1762                  */
1763                 int count = (nic->config.bus_speed * 125)/4;
1764                 val64 = RTI_DATA1_MEM_RX_TIMER_VAL(count);
1765         } else
1766                 val64 = RTI_DATA1_MEM_RX_TIMER_VAL(0xFFF);
1767         val64 |= RTI_DATA1_MEM_RX_URNG_A(0xA) |
1768                  RTI_DATA1_MEM_RX_URNG_B(0x10) |
1769                  RTI_DATA1_MEM_RX_URNG_C(0x30) | RTI_DATA1_MEM_RX_TIMER_AC_EN;
1770
1771         writeq(val64, &bar0->rti_data1_mem);
1772
1773         val64 = RTI_DATA2_MEM_RX_UFC_A(0x1) |
1774                 RTI_DATA2_MEM_RX_UFC_B(0x2) ;
1775         if (nic->config.intr_type == MSI_X)
1776             val64 |= (RTI_DATA2_MEM_RX_UFC_C(0x20) | \
1777                         RTI_DATA2_MEM_RX_UFC_D(0x40));
1778         else
1779             val64 |= (RTI_DATA2_MEM_RX_UFC_C(0x40) | \
1780                         RTI_DATA2_MEM_RX_UFC_D(0x80));
1781         writeq(val64, &bar0->rti_data2_mem);
1782
1783         for (i = 0; i < config->rx_ring_num; i++) {
1784                 val64 = RTI_CMD_MEM_WE | RTI_CMD_MEM_STROBE_NEW_CMD
1785                                 | RTI_CMD_MEM_OFFSET(i);
1786                 writeq(val64, &bar0->rti_command_mem);
1787
1788                 /*
1789                  * Once the operation completes, the Strobe bit of the
1790                  * command register will be reset. We poll for this
1791                  * particular condition. We wait for a maximum of 500ms
1792                  * for the operation to complete, if it's not complete
1793                  * by then we return error.
1794                  */
1795                 time = 0;
1796                 while (TRUE) {
1797                         val64 = readq(&bar0->rti_command_mem);
1798                         if (!(val64 & RTI_CMD_MEM_STROBE_NEW_CMD))
1799                                 break;
1800
1801                         if (time > 10) {
1802                                 DBG_PRINT(ERR_DBG, "%s: RTI init Failed\n",
1803                                           dev->name);
1804                                 return -ENODEV;
1805                         }
1806                         time++;
1807                         msleep(50);
1808                 }
1809         }
1810
1811         /*
1812          * Initializing proper values as Pause threshold into all
1813          * the 8 Queues on Rx side.
1814          */
1815         writeq(0xffbbffbbffbbffbbULL, &bar0->mc_pause_thresh_q0q3);
1816         writeq(0xffbbffbbffbbffbbULL, &bar0->mc_pause_thresh_q4q7);
1817
1818         /* Disable RMAC PAD STRIPPING */
1819         add = &bar0->mac_cfg;
1820         val64 = readq(&bar0->mac_cfg);
1821         val64 &= ~(MAC_CFG_RMAC_STRIP_PAD);
1822         writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
1823         writel((u32) (val64), add);
1824         writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
1825         writel((u32) (val64 >> 32), (add + 4));
1826         val64 = readq(&bar0->mac_cfg);
1827
1828         /* Enable FCS stripping by adapter */
1829         add = &bar0->mac_cfg;
1830         val64 = readq(&bar0->mac_cfg);
1831         val64 |= MAC_CFG_RMAC_STRIP_FCS;
1832         if (nic->device_type == XFRAME_II_DEVICE)
1833                 writeq(val64, &bar0->mac_cfg);
1834         else {
1835                 writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
1836                 writel((u32) (val64), add);
1837                 writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
1838                 writel((u32) (val64 >> 32), (add + 4));
1839         }
1840
1841         /*
1842          * Set the time value to be inserted in the pause frame
1843          * generated by xena.
1844          */
1845         val64 = readq(&bar0->rmac_pause_cfg);
1846         val64 &= ~(RMAC_PAUSE_HG_PTIME(0xffff));
1847         val64 |= RMAC_PAUSE_HG_PTIME(nic->mac_control.rmac_pause_time);
1848         writeq(val64, &bar0->rmac_pause_cfg);
1849
1850         /*
1851          * Set the Threshold Limit for Generating the pause frame
1852          * If the amount of data in any Queue exceeds ratio of
1853          * (mac_control.mc_pause_threshold_q0q3 or q4q7)/256
1854          * pause frame is generated
1855          */
1856         val64 = 0;
1857         for (i = 0; i < 4; i++) {
1858                 val64 |=
1859                     (((u64) 0xFF00 | nic->mac_control.
1860                       mc_pause_threshold_q0q3)
1861                      << (i * 2 * 8));
1862         }
1863         writeq(val64, &bar0->mc_pause_thresh_q0q3);
1864
1865         val64 = 0;
1866         for (i = 0; i < 4; i++) {
1867                 val64 |=
1868                     (((u64) 0xFF00 | nic->mac_control.
1869                       mc_pause_threshold_q4q7)
1870                      << (i * 2 * 8));
1871         }
1872         writeq(val64, &bar0->mc_pause_thresh_q4q7);
1873
1874         /*
1875          * TxDMA will stop Read request if the number of read split has
1876          * exceeded the limit pointed by shared_splits
1877          */
1878         val64 = readq(&bar0->pic_control);
1879         val64 |= PIC_CNTL_SHARED_SPLITS(shared_splits);
1880         writeq(val64, &bar0->pic_control);
1881
1882         if (nic->config.bus_speed == 266) {
1883                 writeq(TXREQTO_VAL(0x7f) | TXREQTO_EN, &bar0->txreqtimeout);
1884                 writeq(0x0, &bar0->read_retry_delay);
1885                 writeq(0x0, &bar0->write_retry_delay);
1886         }
1887
1888         /*
1889          * Programming the Herc to split every write transaction
1890          * that does not start on an ADB to reduce disconnects.
1891          */
1892         if (nic->device_type == XFRAME_II_DEVICE) {
1893                 val64 = FAULT_BEHAVIOUR | EXT_REQ_EN |
1894                         MISC_LINK_STABILITY_PRD(3);
1895                 writeq(val64, &bar0->misc_control);
1896                 val64 = readq(&bar0->pic_control2);
1897                 val64 &= ~(s2BIT(13)|s2BIT(14)|s2BIT(15));
1898                 writeq(val64, &bar0->pic_control2);
1899         }
1900         if (strstr(nic->product_name, "CX4")) {
1901                 val64 = TMAC_AVG_IPG(0x17);
1902                 writeq(val64, &bar0->tmac_avg_ipg);
1903         }
1904
1905         return SUCCESS;
1906 }
1907 #define LINK_UP_DOWN_INTERRUPT          1
1908 #define MAC_RMAC_ERR_TIMER              2
1909
1910 static int s2io_link_fault_indication(struct s2io_nic *nic)
1911 {
1912         if (nic->config.intr_type != INTA)
1913                 return MAC_RMAC_ERR_TIMER;
1914         if (nic->device_type == XFRAME_II_DEVICE)
1915                 return LINK_UP_DOWN_INTERRUPT;
1916         else
1917                 return MAC_RMAC_ERR_TIMER;
1918 }
1919
1920 /**
1921  *  do_s2io_write_bits -  update alarm bits in alarm register
1922  *  @value: alarm bits
1923  *  @flag: interrupt status
1924  *  @addr: address value
1925  *  Description: update alarm bits in alarm register
1926  *  Return Value:
1927  *  NONE.
1928  */
1929 static void do_s2io_write_bits(u64 value, int flag, void __iomem *addr)
1930 {
1931         u64 temp64;
1932
1933         temp64 = readq(addr);
1934
1935         if(flag == ENABLE_INTRS)
1936                 temp64 &= ~((u64) value);
1937         else
1938                 temp64 |= ((u64) value);
1939         writeq(temp64, addr);
1940 }
1941
1942 static void en_dis_err_alarms(struct s2io_nic *nic, u16 mask, int flag)
1943 {
1944         struct XENA_dev_config __iomem *bar0 = nic->bar0;
1945         register u64 gen_int_mask = 0;
1946
1947         if (mask & TX_DMA_INTR) {
1948
1949                 gen_int_mask |= TXDMA_INT_M;
1950
1951                 do_s2io_write_bits(TXDMA_TDA_INT | TXDMA_PFC_INT |
1952                                 TXDMA_PCC_INT | TXDMA_TTI_INT |
1953                                 TXDMA_LSO_INT | TXDMA_TPA_INT |
1954                                 TXDMA_SM_INT, flag, &bar0->txdma_int_mask);
1955
1956                 do_s2io_write_bits(PFC_ECC_DB_ERR | PFC_SM_ERR_ALARM |
1957                                 PFC_MISC_0_ERR | PFC_MISC_1_ERR |
1958                                 PFC_PCIX_ERR | PFC_ECC_SG_ERR, flag,
1959                                 &bar0->pfc_err_mask);
1960
1961                 do_s2io_write_bits(TDA_Fn_ECC_DB_ERR | TDA_SM0_ERR_ALARM |
1962                                 TDA_SM1_ERR_ALARM | TDA_Fn_ECC_SG_ERR |
1963                                 TDA_PCIX_ERR, flag, &bar0->tda_err_mask);
1964
1965                 do_s2io_write_bits(PCC_FB_ECC_DB_ERR | PCC_TXB_ECC_DB_ERR |
1966                                 PCC_SM_ERR_ALARM | PCC_WR_ERR_ALARM |
1967                                 PCC_N_SERR | PCC_6_COF_OV_ERR |
1968                                 PCC_7_COF_OV_ERR | PCC_6_LSO_OV_ERR |
1969                                 PCC_7_LSO_OV_ERR | PCC_FB_ECC_SG_ERR |
1970                                 PCC_TXB_ECC_SG_ERR, flag, &bar0->pcc_err_mask);
1971
1972                 do_s2io_write_bits(TTI_SM_ERR_ALARM | TTI_ECC_SG_ERR |
1973                                 TTI_ECC_DB_ERR, flag, &bar0->tti_err_mask);
1974
1975                 do_s2io_write_bits(LSO6_ABORT | LSO7_ABORT |
1976                                 LSO6_SM_ERR_ALARM | LSO7_SM_ERR_ALARM |
1977                                 LSO6_SEND_OFLOW | LSO7_SEND_OFLOW,
1978                                 flag, &bar0->lso_err_mask);
1979
1980                 do_s2io_write_bits(TPA_SM_ERR_ALARM | TPA_TX_FRM_DROP,
1981                                 flag, &bar0->tpa_err_mask);
1982
1983                 do_s2io_write_bits(SM_SM_ERR_ALARM, flag, &bar0->sm_err_mask);
1984
1985         }
1986
1987         if (mask & TX_MAC_INTR) {
1988                 gen_int_mask |= TXMAC_INT_M;
1989                 do_s2io_write_bits(MAC_INT_STATUS_TMAC_INT, flag,
1990                                 &bar0->mac_int_mask);
1991                 do_s2io_write_bits(TMAC_TX_BUF_OVRN | TMAC_TX_SM_ERR |
1992                                 TMAC_ECC_SG_ERR | TMAC_ECC_DB_ERR |
1993                                 TMAC_DESC_ECC_SG_ERR | TMAC_DESC_ECC_DB_ERR,
1994                                 flag, &bar0->mac_tmac_err_mask);
1995         }
1996
1997         if (mask & TX_XGXS_INTR) {
1998                 gen_int_mask |= TXXGXS_INT_M;
1999                 do_s2io_write_bits(XGXS_INT_STATUS_TXGXS, flag,
2000                                 &bar0->xgxs_int_mask);
2001                 do_s2io_write_bits(TXGXS_ESTORE_UFLOW | TXGXS_TX_SM_ERR |
2002                                 TXGXS_ECC_SG_ERR | TXGXS_ECC_DB_ERR,
2003                                 flag, &bar0->xgxs_txgxs_err_mask);
2004         }
2005
2006         if (mask & RX_DMA_INTR) {
2007                 gen_int_mask |= RXDMA_INT_M;
2008                 do_s2io_write_bits(RXDMA_INT_RC_INT_M | RXDMA_INT_RPA_INT_M |
2009                                 RXDMA_INT_RDA_INT_M | RXDMA_INT_RTI_INT_M,
2010                                 flag, &bar0->rxdma_int_mask);
2011                 do_s2io_write_bits(RC_PRCn_ECC_DB_ERR | RC_FTC_ECC_DB_ERR |
2012                                 RC_PRCn_SM_ERR_ALARM | RC_FTC_SM_ERR_ALARM |
2013                                 RC_PRCn_ECC_SG_ERR | RC_FTC_ECC_SG_ERR |
2014                                 RC_RDA_FAIL_WR_Rn, flag, &bar0->rc_err_mask);
2015                 do_s2io_write_bits(PRC_PCI_AB_RD_Rn | PRC_PCI_AB_WR_Rn |
2016                                 PRC_PCI_AB_F_WR_Rn | PRC_PCI_DP_RD_Rn |
2017                                 PRC_PCI_DP_WR_Rn | PRC_PCI_DP_F_WR_Rn, flag,
2018                                 &bar0->prc_pcix_err_mask);
2019                 do_s2io_write_bits(RPA_SM_ERR_ALARM | RPA_CREDIT_ERR |
2020                                 RPA_ECC_SG_ERR | RPA_ECC_DB_ERR, flag,
2021                                 &bar0->rpa_err_mask);
2022                 do_s2io_write_bits(RDA_RXDn_ECC_DB_ERR | RDA_FRM_ECC_DB_N_AERR |
2023                                 RDA_SM1_ERR_ALARM | RDA_SM0_ERR_ALARM |
2024                                 RDA_RXD_ECC_DB_SERR | RDA_RXDn_ECC_SG_ERR |
2025                                 RDA_FRM_ECC_SG_ERR | RDA_MISC_ERR|RDA_PCIX_ERR,
2026                                 flag, &bar0->rda_err_mask);
2027                 do_s2io_write_bits(RTI_SM_ERR_ALARM |
2028                                 RTI_ECC_SG_ERR | RTI_ECC_DB_ERR,
2029                                 flag, &bar0->rti_err_mask);
2030         }
2031
2032         if (mask & RX_MAC_INTR) {
2033                 gen_int_mask |= RXMAC_INT_M;
2034                 do_s2io_write_bits(MAC_INT_STATUS_RMAC_INT, flag,
2035                                 &bar0->mac_int_mask);
2036                 do_s2io_write_bits(RMAC_RX_BUFF_OVRN | RMAC_RX_SM_ERR |
2037                                 RMAC_UNUSED_INT | RMAC_SINGLE_ECC_ERR |
2038                                 RMAC_DOUBLE_ECC_ERR |
2039                                 RMAC_LINK_STATE_CHANGE_INT,
2040                                 flag, &bar0->mac_rmac_err_mask);
2041         }
2042
2043         if (mask & RX_XGXS_INTR)
2044         {
2045                 gen_int_mask |= RXXGXS_INT_M;
2046                 do_s2io_write_bits(XGXS_INT_STATUS_RXGXS, flag,
2047                                 &bar0->xgxs_int_mask);
2048                 do_s2io_write_bits(RXGXS_ESTORE_OFLOW | RXGXS_RX_SM_ERR, flag,
2049                                 &bar0->xgxs_rxgxs_err_mask);
2050         }
2051
2052         if (mask & MC_INTR) {
2053                 gen_int_mask |= MC_INT_M;
2054                 do_s2io_write_bits(MC_INT_MASK_MC_INT, flag, &bar0->mc_int_mask);
2055                 do_s2io_write_bits(MC_ERR_REG_SM_ERR | MC_ERR_REG_ECC_ALL_SNG |
2056                                 MC_ERR_REG_ECC_ALL_DBL | PLL_LOCK_N, flag,
2057                                 &bar0->mc_err_mask);
2058         }
2059         nic->general_int_mask = gen_int_mask;
2060
2061         /* Remove this line when alarm interrupts are enabled */
2062         nic->general_int_mask = 0;
2063 }
2064 /**
2065  *  en_dis_able_nic_intrs - Enable or Disable the interrupts
2066  *  @nic: device private variable,
2067  *  @mask: A mask indicating which Intr block must be modified and,
2068  *  @flag: A flag indicating whether to enable or disable the Intrs.
2069  *  Description: This function will either disable or enable the interrupts
2070  *  depending on the flag argument. The mask argument can be used to
2071  *  enable/disable any Intr block.
2072  *  Return Value: NONE.
2073  */
2074
2075 static void en_dis_able_nic_intrs(struct s2io_nic *nic, u16 mask, int flag)
2076 {
2077         struct XENA_dev_config __iomem *bar0 = nic->bar0;
2078         register u64 temp64 = 0, intr_mask = 0;
2079
2080         intr_mask = nic->general_int_mask;
2081
2082         /*  Top level interrupt classification */
2083         /*  PIC Interrupts */
2084         if (mask & TX_PIC_INTR) {
2085                 /*  Enable PIC Intrs in the general intr mask register */
2086                 intr_mask |= TXPIC_INT_M;
2087                 if (flag == ENABLE_INTRS) {
2088                         /*
2089                          * If Hercules adapter enable GPIO otherwise
2090                          * disable all PCIX, Flash, MDIO, IIC and GPIO
2091                          * interrupts for now.
2092                          * TODO
2093                          */
2094                         if (s2io_link_fault_indication(nic) ==
2095                                         LINK_UP_DOWN_INTERRUPT ) {
2096                                 do_s2io_write_bits(PIC_INT_GPIO, flag,
2097                                                 &bar0->pic_int_mask);
2098                                 do_s2io_write_bits(GPIO_INT_MASK_LINK_UP, flag,
2099                                                 &bar0->gpio_int_mask);
2100                         } else
2101                                 writeq(DISABLE_ALL_INTRS, &bar0->pic_int_mask);
2102                 } else if (flag == DISABLE_INTRS) {
2103                         /*
2104                          * Disable PIC Intrs in the general
2105                          * intr mask register
2106                          */
2107                         writeq(DISABLE_ALL_INTRS, &bar0->pic_int_mask);
2108                 }
2109         }
2110
2111         /*  Tx traffic interrupts */
2112         if (mask & TX_TRAFFIC_INTR) {
2113                 intr_mask |= TXTRAFFIC_INT_M;
2114                 if (flag == ENABLE_INTRS) {
2115                         /*
2116                          * Enable all the Tx side interrupts
2117                          * writing 0 Enables all 64 TX interrupt levels
2118                          */
2119                         writeq(0x0, &bar0->tx_traffic_mask);
2120                 } else if (flag == DISABLE_INTRS) {
2121                         /*
2122                          * Disable Tx Traffic Intrs in the general intr mask
2123                          * register.
2124                          */
2125                         writeq(DISABLE_ALL_INTRS, &bar0->tx_traffic_mask);
2126                 }
2127         }
2128
2129         /*  Rx traffic interrupts */
2130         if (mask & RX_TRAFFIC_INTR) {
2131                 intr_mask |= RXTRAFFIC_INT_M;
2132                 if (flag == ENABLE_INTRS) {
2133                         /* writing 0 Enables all 8 RX interrupt levels */
2134                         writeq(0x0, &bar0->rx_traffic_mask);
2135                 } else if (flag == DISABLE_INTRS) {
2136                         /*
2137                          * Disable Rx Traffic Intrs in the general intr mask
2138                          * register.
2139                          */
2140                         writeq(DISABLE_ALL_INTRS, &bar0->rx_traffic_mask);
2141                 }
2142         }
2143
2144         temp64 = readq(&bar0->general_int_mask);
2145         if (flag == ENABLE_INTRS)
2146                 temp64 &= ~((u64) intr_mask);
2147         else
2148                 temp64 = DISABLE_ALL_INTRS;
2149         writeq(temp64, &bar0->general_int_mask);
2150
2151         nic->general_int_mask = readq(&bar0->general_int_mask);
2152 }
2153
2154 /**
2155  *  verify_pcc_quiescent- Checks for PCC quiescent state
2156  *  Return: 1 If PCC is quiescence
2157  *          0 If PCC is not quiescence
2158  */
2159 static int verify_pcc_quiescent(struct s2io_nic *sp, int flag)
2160 {
2161         int ret = 0, herc;
2162         struct XENA_dev_config __iomem *bar0 = sp->bar0;
2163         u64 val64 = readq(&bar0->adapter_status);
2164
2165         herc = (sp->device_type == XFRAME_II_DEVICE);
2166
2167         if (flag == FALSE) {
2168                 if ((!herc && (sp->pdev->revision >= 4)) || herc) {
2169                         if (!(val64 & ADAPTER_STATUS_RMAC_PCC_IDLE))
2170                                 ret = 1;
2171                 } else {
2172                         if (!(val64 & ADAPTER_STATUS_RMAC_PCC_FOUR_IDLE))
2173                                 ret = 1;
2174                 }
2175         } else {
2176                 if ((!herc && (sp->pdev->revision >= 4)) || herc) {
2177                         if (((val64 & ADAPTER_STATUS_RMAC_PCC_IDLE) ==
2178                              ADAPTER_STATUS_RMAC_PCC_IDLE))
2179                                 ret = 1;
2180                 } else {
2181                         if (((val64 & ADAPTER_STATUS_RMAC_PCC_FOUR_IDLE) ==
2182                              ADAPTER_STATUS_RMAC_PCC_FOUR_IDLE))
2183                                 ret = 1;
2184                 }
2185         }
2186
2187         return ret;
2188 }
2189 /**
2190  *  verify_xena_quiescence - Checks whether the H/W is ready
2191  *  Description: Returns whether the H/W is ready to go or not. Depending
2192  *  on whether adapter enable bit was written or not the comparison
2193  *  differs and the calling function passes the input argument flag to
2194  *  indicate this.
2195  *  Return: 1 If xena is quiescence
2196  *          0 If Xena is not quiescence
2197  */
2198
2199 static int verify_xena_quiescence(struct s2io_nic *sp)
2200 {
2201         int  mode;
2202         struct XENA_dev_config __iomem *bar0 = sp->bar0;
2203         u64 val64 = readq(&bar0->adapter_status);
2204         mode = s2io_verify_pci_mode(sp);
2205
2206         if (!(val64 & ADAPTER_STATUS_TDMA_READY)) {
2207                 DBG_PRINT(ERR_DBG, "%s", "TDMA is not ready!");
2208                 return 0;
2209         }
2210         if (!(val64 & ADAPTER_STATUS_RDMA_READY)) {
2211         DBG_PRINT(ERR_DBG, "%s", "RDMA is not ready!");
2212                 return 0;
2213         }
2214         if (!(val64 & ADAPTER_STATUS_PFC_READY)) {
2215                 DBG_PRINT(ERR_DBG, "%s", "PFC is not ready!");
2216                 return 0;
2217         }
2218         if (!(val64 & ADAPTER_STATUS_TMAC_BUF_EMPTY)) {
2219                 DBG_PRINT(ERR_DBG, "%s", "TMAC BUF is not empty!");
2220                 return 0;
2221         }
2222         if (!(val64 & ADAPTER_STATUS_PIC_QUIESCENT)) {
2223                 DBG_PRINT(ERR_DBG, "%s", "PIC is not QUIESCENT!");
2224                 return 0;
2225         }
2226         if (!(val64 & ADAPTER_STATUS_MC_DRAM_READY)) {
2227                 DBG_PRINT(ERR_DBG, "%s", "MC_DRAM is not ready!");
2228                 return 0;
2229         }
2230         if (!(val64 & ADAPTER_STATUS_MC_QUEUES_READY)) {
2231                 DBG_PRINT(ERR_DBG, "%s", "MC_QUEUES is not ready!");
2232                 return 0;
2233         }
2234         if (!(val64 & ADAPTER_STATUS_M_PLL_LOCK)) {
2235                 DBG_PRINT(ERR_DBG, "%s", "M_PLL is not locked!");
2236                 return 0;
2237         }
2238
2239         /*
2240          * In PCI 33 mode, the P_PLL is not used, and therefore,
2241          * the the P_PLL_LOCK bit in the adapter_status register will
2242          * not be asserted.
2243          */
2244         if (!(val64 & ADAPTER_STATUS_P_PLL_LOCK) &&
2245                 sp->device_type == XFRAME_II_DEVICE && mode !=
2246                 PCI_MODE_PCI_33) {
2247                 DBG_PRINT(ERR_DBG, "%s", "P_PLL is not locked!");
2248                 return 0;
2249         }
2250         if (!((val64 & ADAPTER_STATUS_RC_PRC_QUIESCENT) ==
2251                         ADAPTER_STATUS_RC_PRC_QUIESCENT)) {
2252                 DBG_PRINT(ERR_DBG, "%s", "RC_PRC is not QUIESCENT!");
2253                 return 0;
2254         }
2255         return 1;
2256 }
2257
2258 /**
2259  * fix_mac_address -  Fix for Mac addr problem on Alpha platforms
2260  * @sp: Pointer to device specifc structure
2261  * Description :
2262  * New procedure to clear mac address reading  problems on Alpha platforms
2263  *
2264  */
2265
2266 static void fix_mac_address(struct s2io_nic * sp)
2267 {
2268         struct XENA_dev_config __iomem *bar0 = sp->bar0;
2269         u64 val64;
2270         int i = 0;
2271
2272         while (fix_mac[i] != END_SIGN) {
2273                 writeq(fix_mac[i++], &bar0->gpio_control);
2274                 udelay(10);
2275                 val64 = readq(&bar0->gpio_control);
2276         }
2277 }
2278
2279 /**
2280  *  start_nic - Turns the device on
2281  *  @nic : device private variable.
2282  *  Description:
2283  *  This function actually turns the device on. Before this  function is
2284  *  called,all Registers are configured from their reset states
2285  *  and shared memory is allocated but the NIC is still quiescent. On
2286  *  calling this function, the device interrupts are cleared and the NIC is
2287  *  literally switched on by writing into the adapter control register.
2288  *  Return Value:
2289  *  SUCCESS on success and -1 on failure.
2290  */
2291
2292 static int start_nic(struct s2io_nic *nic)
2293 {
2294         struct XENA_dev_config __iomem *bar0 = nic->bar0;
2295         struct net_device *dev = nic->dev;
2296         register u64 val64 = 0;
2297         u16 subid, i;
2298         struct mac_info *mac_control;
2299         struct config_param *config;
2300
2301         mac_control = &nic->mac_control;
2302         config = &nic->config;
2303
2304         /*  PRC Initialization and configuration */
2305         for (i = 0; i < config->rx_ring_num; i++) {
2306                 writeq((u64) mac_control->rings[i].rx_blocks[0].block_dma_addr,
2307                        &bar0->prc_rxd0_n[i]);
2308
2309                 val64 = readq(&bar0->prc_ctrl_n[i]);
2310                 if (nic->rxd_mode == RXD_MODE_1)
2311                         val64 |= PRC_CTRL_RC_ENABLED;
2312                 else
2313                         val64 |= PRC_CTRL_RC_ENABLED | PRC_CTRL_RING_MODE_3;
2314                 if (nic->device_type == XFRAME_II_DEVICE)
2315                         val64 |= PRC_CTRL_GROUP_READS;
2316                 val64 &= ~PRC_CTRL_RXD_BACKOFF_INTERVAL(0xFFFFFF);
2317                 val64 |= PRC_CTRL_RXD_BACKOFF_INTERVAL(0x1000);
2318                 writeq(val64, &bar0->prc_ctrl_n[i]);
2319         }
2320
2321         if (nic->rxd_mode == RXD_MODE_3B) {
2322                 /* Enabling 2 buffer mode by writing into Rx_pa_cfg reg. */
2323                 val64 = readq(&bar0->rx_pa_cfg);
2324                 val64 |= RX_PA_CFG_IGNORE_L2_ERR;
2325                 writeq(val64, &bar0->rx_pa_cfg);
2326         }
2327
2328         if (vlan_tag_strip == 0) {
2329                 val64 = readq(&bar0->rx_pa_cfg);
2330                 val64 &= ~RX_PA_CFG_STRIP_VLAN_TAG;
2331                 writeq(val64, &bar0->rx_pa_cfg);
2332                 vlan_strip_flag = 0;
2333         }
2334
2335         /*
2336          * Enabling MC-RLDRAM. After enabling the device, we timeout
2337          * for around 100ms, which is approximately the time required
2338          * for the device to be ready for operation.
2339          */
2340         val64 = readq(&bar0->mc_rldram_mrs);
2341         val64 |= MC_RLDRAM_QUEUE_SIZE_ENABLE | MC_RLDRAM_MRS_ENABLE;
2342         SPECIAL_REG_WRITE(val64, &bar0->mc_rldram_mrs, UF);
2343         val64 = readq(&bar0->mc_rldram_mrs);
2344
2345         msleep(100);    /* Delay by around 100 ms. */
2346
2347         /* Enabling ECC Protection. */
2348         val64 = readq(&bar0->adapter_control);
2349         val64 &= ~ADAPTER_ECC_EN;
2350         writeq(val64, &bar0->adapter_control);
2351
2352         /*
2353          * Verify if the device is ready to be enabled, if so enable
2354          * it.
2355          */
2356         val64 = readq(&bar0->adapter_status);
2357         if (!verify_xena_quiescence(nic)) {
2358                 DBG_PRINT(ERR_DBG, "%s: device is not ready, ", dev->name);
2359                 DBG_PRINT(ERR_DBG, "Adapter status reads: 0x%llx\n",
2360                           (unsigned long long) val64);
2361                 return FAILURE;
2362         }
2363
2364         /*
2365          * With some switches, link might be already up at this point.
2366          * Because of this weird behavior, when we enable laser,
2367          * we may not get link. We need to handle this. We cannot
2368          * figure out which switch is misbehaving. So we are forced to
2369          * make a global change.
2370          */
2371
2372         /* Enabling Laser. */
2373         val64 = readq(&bar0->adapter_control);
2374         val64 |= ADAPTER_EOI_TX_ON;
2375         writeq(val64, &bar0->adapter_control);
2376
2377         if (s2io_link_fault_indication(nic) == MAC_RMAC_ERR_TIMER) {
2378                 /*
2379                  * Dont see link state interrupts initally on some switches,
2380                  * so directly scheduling the link state task here.
2381                  */
2382                 schedule_work(&nic->set_link_task);
2383         }
2384         /* SXE-002: Initialize link and activity LED */
2385         subid = nic->pdev->subsystem_device;
2386         if (((subid & 0xFF) >= 0x07) &&
2387             (nic->device_type == XFRAME_I_DEVICE)) {
2388                 val64 = readq(&bar0->gpio_control);
2389                 val64 |= 0x0000800000000000ULL;
2390                 writeq(val64, &bar0->gpio_control);
2391                 val64 = 0x0411040400000000ULL;
2392                 writeq(val64, (void __iomem *)bar0 + 0x2700);
2393         }
2394
2395         return SUCCESS;
2396 }
2397 /**
2398  * s2io_txdl_getskb - Get the skb from txdl, unmap and return skb
2399  */
2400 static struct sk_buff *s2io_txdl_getskb(struct fifo_info *fifo_data, struct \
2401                                         TxD *txdlp, int get_off)
2402 {
2403         struct s2io_nic *nic = fifo_data->nic;
2404         struct sk_buff *skb;
2405         struct TxD *txds;
2406         u16 j, frg_cnt;
2407
2408         txds = txdlp;
2409         if (txds->Host_Control == (u64)(long)fifo_data->ufo_in_band_v) {
2410                 pci_unmap_single(nic->pdev, (dma_addr_t)
2411                         txds->Buffer_Pointer, sizeof(u64),
2412                         PCI_DMA_TODEVICE);
2413                 txds++;
2414         }
2415
2416         skb = (struct sk_buff *) ((unsigned long)
2417                         txds->Host_Control);
2418         if (!skb) {
2419                 memset(txdlp, 0, (sizeof(struct TxD) * fifo_data->max_txds));
2420                 return NULL;
2421         }
2422         pci_unmap_single(nic->pdev, (dma_addr_t)
2423                          txds->Buffer_Pointer,
2424                          skb->len - skb->data_len,
2425                          PCI_DMA_TODEVICE);
2426         frg_cnt = skb_shinfo(skb)->nr_frags;
2427         if (frg_cnt) {
2428                 txds++;
2429                 for (j = 0; j < frg_cnt; j++, txds++) {
2430                         skb_frag_t *frag = &skb_shinfo(skb)->frags[j];
2431                         if (!txds->Buffer_Pointer)
2432                                 break;
2433                         pci_unmap_page(nic->pdev, (dma_addr_t)
2434                                         txds->Buffer_Pointer,
2435                                        frag->size, PCI_DMA_TODEVICE);
2436                 }
2437         }
2438         memset(txdlp,0, (sizeof(struct TxD) * fifo_data->max_txds));
2439         return(skb);
2440 }
2441
2442 /**
2443  *  free_tx_buffers - Free all queued Tx buffers
2444  *  @nic : device private variable.
2445  *  Description:
2446  *  Free all queued Tx buffers.
2447  *  Return Value: void
2448 */
2449
2450 static void free_tx_buffers(struct s2io_nic *nic)
2451 {
2452         struct net_device *dev = nic->dev;
2453         struct sk_buff *skb;
2454         struct TxD *txdp;
2455         int i, j;
2456         struct mac_info *mac_control;
2457         struct config_param *config;
2458         int cnt = 0;
2459
2460         mac_control = &nic->mac_control;
2461         config = &nic->config;
2462
2463         for (i = 0; i < config->tx_fifo_num; i++) {
2464                 unsigned long flags;
2465                 spin_lock_irqsave(&mac_control->fifos[i].tx_lock, flags);
2466                 for (j = 0; j < config->tx_cfg[i].fifo_len; j++) {
2467                         txdp = (struct TxD *) \
2468                         mac_control->fifos[i].list_info[j].list_virt_addr;
2469                         skb = s2io_txdl_getskb(&mac_control->fifos[i], txdp, j);
2470                         if (skb) {
2471                                 nic->mac_control.stats_info->sw_stat.mem_freed
2472                                         += skb->truesize;
2473                                 dev_kfree_skb(skb);
2474                                 cnt++;
2475                         }
2476                 }
2477                 DBG_PRINT(INTR_DBG,
2478                           "%s:forcibly freeing %d skbs on FIFO%d\n",
2479                           dev->name, cnt, i);
2480                 mac_control->fifos[i].tx_curr_get_info.offset = 0;
2481                 mac_control->fifos[i].tx_curr_put_info.offset = 0;
2482                 spin_unlock_irqrestore(&mac_control->fifos[i].tx_lock, flags);
2483         }
2484 }
2485
2486 /**
2487  *   stop_nic -  To stop the nic
2488  *   @nic ; device private variable.
2489  *   Description:
2490  *   This function does exactly the opposite of what the start_nic()
2491  *   function does. This function is called to stop the device.
2492  *   Return Value:
2493  *   void.
2494  */
2495
2496 static void stop_nic(struct s2io_nic *nic)
2497 {
2498         struct XENA_dev_config __iomem *bar0 = nic->bar0;
2499         register u64 val64 = 0;
2500         u16 interruptible;
2501         struct mac_info *mac_control;
2502         struct config_param *config;
2503
2504         mac_control = &nic->mac_control;
2505         config = &nic->config;
2506
2507         /*  Disable all interrupts */
2508         en_dis_err_alarms(nic, ENA_ALL_INTRS, DISABLE_INTRS);
2509         interruptible = TX_TRAFFIC_INTR | RX_TRAFFIC_INTR;
2510         interruptible |= TX_PIC_INTR;
2511         en_dis_able_nic_intrs(nic, interruptible, DISABLE_INTRS);
2512
2513         /* Clearing Adapter_En bit of ADAPTER_CONTROL Register */
2514         val64 = readq(&bar0->adapter_control);
2515         val64 &= ~(ADAPTER_CNTL_EN);
2516         writeq(val64, &bar0->adapter_control);
2517 }
2518
2519 /**
2520  *  fill_rx_buffers - Allocates the Rx side skbs
2521  *  @ring_info: per ring structure
2522  *  Description:
2523  *  The function allocates Rx side skbs and puts the physical
2524  *  address of these buffers into the RxD buffer pointers, so that the NIC
2525  *  can DMA the received frame into these locations.
2526  *  The NIC supports 3 receive modes, viz
2527  *  1. single buffer,
2528  *  2. three buffer and
2529  *  3. Five buffer modes.
2530  *  Each mode defines how many fragments the received frame will be split
2531  *  up into by the NIC. The frame is split into L3 header, L4 Header,
2532  *  L4 payload in three buffer mode and in 5 buffer mode, L4 payload itself
2533  *  is split into 3 fragments. As of now only single buffer mode is
2534  *  supported.
2535  *   Return Value:
2536  *  SUCCESS on success or an appropriate -ve value on failure.
2537  */
2538
2539 static int fill_rx_buffers(struct ring_info *ring)
2540 {
2541         struct sk_buff *skb;
2542         struct RxD_t *rxdp;
2543         int off, size, block_no, block_no1;
2544         u32 alloc_tab = 0;
2545         u32 alloc_cnt;
2546         u64 tmp;
2547         struct buffAdd *ba;
2548         struct RxD_t *first_rxdp = NULL;
2549         u64 Buffer0_ptr = 0, Buffer1_ptr = 0;
2550         int rxd_index = 0;
2551         struct RxD1 *rxdp1;
2552         struct RxD3 *rxdp3;
2553         struct swStat *stats = &ring->nic->mac_control.stats_info->sw_stat;
2554
2555         alloc_cnt = ring->pkt_cnt - ring->rx_bufs_left;
2556
2557         block_no1 = ring->rx_curr_get_info.block_index;
2558         while (alloc_tab < alloc_cnt) {
2559                 block_no = ring->rx_curr_put_info.block_index;
2560
2561                 off = ring->rx_curr_put_info.offset;
2562
2563                 rxdp = ring->rx_blocks[block_no].rxds[off].virt_addr;
2564
2565                 rxd_index = off + 1;
2566                 if (block_no)
2567                         rxd_index += (block_no * ring->rxd_count);
2568
2569                 if ((block_no == block_no1) &&
2570                         (off == ring->rx_curr_get_info.offset) &&
2571                         (rxdp->Host_Control)) {
2572                         DBG_PRINT(INTR_DBG, "%s: Get and Put",
2573                                 ring->dev->name);
2574                         DBG_PRINT(INTR_DBG, " info equated\n");
2575                         goto end;
2576                 }
2577                 if (off && (off == ring->rxd_count)) {
2578                         ring->rx_curr_put_info.block_index++;
2579                         if (ring->rx_curr_put_info.block_index ==
2580                                                         ring->block_count)
2581                                 ring->rx_curr_put_info.block_index = 0;
2582                         block_no = ring->rx_curr_put_info.block_index;
2583                         off = 0;
2584                         ring->rx_curr_put_info.offset = off;
2585                         rxdp = ring->rx_blocks[block_no].block_virt_addr;
2586                         DBG_PRINT(INTR_DBG, "%s: Next block at: %p\n",
2587                                   ring->dev->name, rxdp);
2588
2589                 }
2590
2591                 if ((rxdp->Control_1 & RXD_OWN_XENA) &&
2592                         ((ring->rxd_mode == RXD_MODE_3B) &&
2593                                 (rxdp->Control_2 & s2BIT(0)))) {
2594                         ring->rx_curr_put_info.offset = off;
2595                         goto end;
2596                 }
2597                 /* calculate size of skb based on ring mode */
2598                 size = ring->mtu + HEADER_ETHERNET_II_802_3_SIZE +
2599                                 HEADER_802_2_SIZE + HEADER_SNAP_SIZE;
2600                 if (ring->rxd_mode == RXD_MODE_1)
2601                         size += NET_IP_ALIGN;
2602                 else
2603                         size = ring->mtu + ALIGN_SIZE + BUF0_LEN + 4;
2604
2605                 /* allocate skb */
2606                 skb = dev_alloc_skb(size);
2607                 if(!skb) {
2608                         DBG_PRINT(INFO_DBG, "%s: Out of ", ring->dev->name);
2609                         DBG_PRINT(INFO_DBG, "memory to allocate SKBs\n");
2610                         if (first_rxdp) {
2611                                 wmb();
2612                                 first_rxdp->Control_1 |= RXD_OWN_XENA;
2613                         }
2614                         stats->mem_alloc_fail_cnt++;
2615
2616                         return -ENOMEM ;
2617                 }
2618                 stats->mem_allocated += skb->truesize;
2619
2620                 if (ring->rxd_mode == RXD_MODE_1) {
2621                         /* 1 buffer mode - normal operation mode */
2622                         rxdp1 = (struct RxD1*)rxdp;
2623                         memset(rxdp, 0, sizeof(struct RxD1));
2624                         skb_reserve(skb, NET_IP_ALIGN);
2625                         rxdp1->Buffer0_ptr = pci_map_single
2626                             (ring->pdev, skb->data, size - NET_IP_ALIGN,
2627                                 PCI_DMA_FROMDEVICE);
2628                         if( (rxdp1->Buffer0_ptr == 0) ||
2629                                 (rxdp1->Buffer0_ptr ==
2630                                 DMA_ERROR_CODE))
2631                                 goto pci_map_failed;
2632
2633                         rxdp->Control_2 =
2634                                 SET_BUFFER0_SIZE_1(size - NET_IP_ALIGN);
2635                         rxdp->Host_Control = (unsigned long) (skb);
2636                 } else if (ring->rxd_mode == RXD_MODE_3B) {
2637                         /*
2638                          * 2 buffer mode -
2639                          * 2 buffer mode provides 128
2640                          * byte aligned receive buffers.
2641                          */
2642
2643                         rxdp3 = (struct RxD3*)rxdp;
2644                         /* save buffer pointers to avoid frequent dma mapping */
2645                         Buffer0_ptr = rxdp3->Buffer0_ptr;
2646                         Buffer1_ptr = rxdp3->Buffer1_ptr;
2647                         memset(rxdp, 0, sizeof(struct RxD3));
2648                         /* restore the buffer pointers for dma sync*/
2649                         rxdp3->Buffer0_ptr = Buffer0_ptr;
2650                         rxdp3->Buffer1_ptr = Buffer1_ptr;
2651
2652                         ba = &ring->ba[block_no][off];
2653                         skb_reserve(skb, BUF0_LEN);
2654                         tmp = (u64)(unsigned long) skb->data;
2655                         tmp += ALIGN_SIZE;
2656                         tmp &= ~ALIGN_SIZE;
2657                         skb->data = (void *) (unsigned long)tmp;
2658                         skb_reset_tail_pointer(skb);
2659
2660                         if (!(rxdp3->Buffer0_ptr))
2661                                 rxdp3->Buffer0_ptr =
2662                                    pci_map_single(ring->pdev, ba->ba_0,
2663                                         BUF0_LEN, PCI_DMA_FROMDEVICE);
2664                         else
2665                                 pci_dma_sync_single_for_device(ring->pdev,
2666                                 (dma_addr_t) rxdp3->Buffer0_ptr,
2667                                     BUF0_LEN, PCI_DMA_FROMDEVICE);
2668                         if( (rxdp3->Buffer0_ptr == 0) ||
2669                                 (rxdp3->Buffer0_ptr == DMA_ERROR_CODE))
2670                                 goto pci_map_failed;
2671
2672                         rxdp->Control_2 = SET_BUFFER0_SIZE_3(BUF0_LEN);
2673                         if (ring->rxd_mode == RXD_MODE_3B) {
2674                                 /* Two buffer mode */
2675
2676                                 /*
2677                                  * Buffer2 will have L3/L4 header plus
2678                                  * L4 payload
2679                                  */
2680                                 rxdp3->Buffer2_ptr = pci_map_single
2681                                 (ring->pdev, skb->data, ring->mtu + 4,
2682                                                 PCI_DMA_FROMDEVICE);
2683
2684                                 if( (rxdp3->Buffer2_ptr == 0) ||
2685                                         (rxdp3->Buffer2_ptr == DMA_ERROR_CODE))
2686                                         goto pci_map_failed;
2687
2688                                 if (!rxdp3->Buffer1_ptr)
2689                                         rxdp3->Buffer1_ptr =
2690                                                 pci_map_single(ring->pdev,
2691                                                 ba->ba_1, BUF1_LEN,
2692                                                 PCI_DMA_FROMDEVICE);
2693
2694                                 if( (rxdp3->Buffer1_ptr == 0) ||
2695                                         (rxdp3->Buffer1_ptr == DMA_ERROR_CODE)) {
2696                                         pci_unmap_single
2697                                                 (ring->pdev,
2698                                                 (dma_addr_t)(unsigned long)
2699                                                 skb->data,
2700                                                 ring->mtu + 4,
2701                                                 PCI_DMA_FROMDEVICE);
2702                                         goto pci_map_failed;
2703                                 }
2704                                 rxdp->Control_2 |= SET_BUFFER1_SIZE_3(1);
2705                                 rxdp->Control_2 |= SET_BUFFER2_SIZE_3
2706                                                                 (ring->mtu + 4);
2707                         }
2708                         rxdp->Control_2 |= s2BIT(0);
2709                         rxdp->Host_Control = (unsigned long) (skb);
2710                 }
2711                 if (alloc_tab & ((1 << rxsync_frequency) - 1))
2712                         rxdp->Control_1 |= RXD_OWN_XENA;
2713                 off++;
2714                 if (off == (ring->rxd_count + 1))
2715                         off = 0;
2716                 ring->rx_curr_put_info.offset = off;
2717
2718                 rxdp->Control_2 |= SET_RXD_MARKER;
2719                 if (!(alloc_tab & ((1 << rxsync_frequency) - 1))) {
2720                         if (first_rxdp) {
2721                                 wmb();
2722                                 first_rxdp->Control_1 |= RXD_OWN_XENA;
2723                         }
2724                         first_rxdp = rxdp;
2725                 }
2726                 ring->rx_bufs_left += 1;
2727                 alloc_tab++;
2728         }
2729
2730       end:
2731         /* Transfer ownership of first descriptor to adapter just before
2732          * exiting. Before that, use memory barrier so that ownership
2733          * and other fields are seen by adapter correctly.
2734          */
2735         if (first_rxdp) {
2736                 wmb();
2737                 first_rxdp->Control_1 |= RXD_OWN_XENA;
2738         }
2739
2740         return SUCCESS;
2741 pci_map_failed:
2742         stats->pci_map_fail_cnt++;
2743         stats->mem_freed += skb->truesize;
2744         dev_kfree_skb_irq(skb);
2745         return -ENOMEM;
2746 }
2747
2748 static void free_rxd_blk(struct s2io_nic *sp, int ring_no, int blk)
2749 {
2750         struct net_device *dev = sp->dev;
2751         int j;
2752         struct sk_buff *skb;
2753         struct RxD_t *rxdp;
2754         struct mac_info *mac_control;
2755         struct buffAdd *ba;
2756         struct RxD1 *rxdp1;
2757         struct RxD3 *rxdp3;
2758
2759         mac_control = &sp->mac_control;
2760         for (j = 0 ; j < rxd_count[sp->rxd_mode]; j++) {
2761                 rxdp = mac_control->rings[ring_no].
2762                                 rx_blocks[blk].rxds[j].virt_addr;
2763                 skb = (struct sk_buff *)
2764                         ((unsigned long) rxdp->Host_Control);
2765                 if (!skb) {
2766                         continue;
2767                 }
2768                 if (sp->rxd_mode == RXD_MODE_1) {
2769                         rxdp1 = (struct RxD1*)rxdp;
2770                         pci_unmap_single(sp->pdev, (dma_addr_t)
2771                                 rxdp1->Buffer0_ptr,
2772                                 dev->mtu +
2773                                 HEADER_ETHERNET_II_802_3_SIZE
2774                                 + HEADER_802_2_SIZE +
2775                                 HEADER_SNAP_SIZE,
2776                                 PCI_DMA_FROMDEVICE);
2777                         memset(rxdp, 0, sizeof(struct RxD1));
2778                 } else if(sp->rxd_mode == RXD_MODE_3B) {
2779                         rxdp3 = (struct RxD3*)rxdp;
2780                         ba = &mac_control->rings[ring_no].
2781                                 ba[blk][j];
2782                         pci_unmap_single(sp->pdev, (dma_addr_t)
2783                                 rxdp3->Buffer0_ptr,
2784                                 BUF0_LEN,
2785                                 PCI_DMA_FROMDEVICE);
2786                         pci_unmap_single(sp->pdev, (dma_addr_t)
2787                                 rxdp3->Buffer1_ptr,
2788                                 BUF1_LEN,
2789                                 PCI_DMA_FROMDEVICE);
2790                         pci_unmap_single(sp->pdev, (dma_addr_t)
2791                                 rxdp3->Buffer2_ptr,
2792                                 dev->mtu + 4,
2793                                 PCI_DMA_FROMDEVICE);
2794                         memset(rxdp, 0, sizeof(struct RxD3));
2795                 }
2796                 sp->mac_control.stats_info->sw_stat.mem_freed += skb->truesize;
2797                 dev_kfree_skb(skb);
2798                 mac_control->rings[ring_no].rx_bufs_left -= 1;
2799         }
2800 }
2801
2802 /**
2803  *  free_rx_buffers - Frees all Rx buffers
2804  *  @sp: device private variable.
2805  *  Description:
2806  *  This function will free all Rx buffers allocated by host.
2807  *  Return Value:
2808  *  NONE.
2809  */
2810
2811 static void free_rx_buffers(struct s2io_nic *sp)
2812 {
2813         struct net_device *dev = sp->dev;
2814         int i, blk = 0, buf_cnt = 0;
2815         struct mac_info *mac_control;
2816         struct config_param *config;
2817
2818         mac_control = &sp->mac_control;
2819         config = &sp->config;
2820
2821         for (i = 0; i < config->rx_ring_num; i++) {
2822                 for (blk = 0; blk < rx_ring_sz[i]; blk++)
2823                         free_rxd_blk(sp,i,blk);
2824
2825                 mac_control->rings[i].rx_curr_put_info.block_index = 0;
2826                 mac_control->rings[i].rx_curr_get_info.block_index = 0;
2827                 mac_control->rings[i].rx_curr_put_info.offset = 0;
2828                 mac_control->rings[i].rx_curr_get_info.offset = 0;
2829                 mac_control->rings[i].rx_bufs_left = 0;
2830                 DBG_PRINT(INIT_DBG, "%s:Freed 0x%x Rx Buffers on ring%d\n",
2831                           dev->name, buf_cnt, i);
2832         }
2833 }
2834
2835 /**
2836  * s2io_poll - Rx interrupt handler for NAPI support
2837  * @napi : pointer to the napi structure.
2838  * @budget : The number of packets that were budgeted to be processed
2839  * during  one pass through the 'Poll" function.
2840  * Description:
2841  * Comes into picture only if NAPI support has been incorporated. It does
2842  * the same thing that rx_intr_handler does, but not in a interrupt context
2843  * also It will process only a given number of packets.
2844  * Return value:
2845  * 0 on success and 1 if there are No Rx packets to be processed.
2846  */
2847
2848 static int s2io_poll(struct napi_struct *napi, int budget)
2849 {
2850         struct s2io_nic *nic = container_of(napi, struct s2io_nic, napi);
2851         struct net_device *dev = nic->dev;
2852         int pkt_cnt = 0, org_pkts_to_process;
2853         struct mac_info *mac_control;
2854         struct config_param *config;
2855         struct XENA_dev_config __iomem *bar0 = nic->bar0;
2856         int i;
2857
2858         mac_control = &nic->mac_control;
2859         config = &nic->config;
2860
2861         nic->pkts_to_process = budget;
2862         org_pkts_to_process = nic->pkts_to_process;
2863
2864         writeq(S2IO_MINUS_ONE, &bar0->rx_traffic_int);
2865         readl(&bar0->rx_traffic_int);
2866
2867         for (i = 0; i < config->rx_ring_num; i++) {
2868                 rx_intr_handler(&mac_control->rings[i]);
2869                 pkt_cnt = org_pkts_to_process - nic->pkts_to_process;
2870                 if (!nic->pkts_to_process) {
2871                         /* Quota for the current iteration has been met */
2872                         goto no_rx;
2873                 }
2874         }
2875
2876         netif_rx_complete(dev, napi);
2877
2878         for (i = 0; i < config->rx_ring_num; i++) {
2879                 if (fill_rx_buffers(&mac_control->rings[i]) == -ENOMEM) {
2880                         DBG_PRINT(INFO_DBG, "%s:Out of memory", dev->name);
2881                         DBG_PRINT(INFO_DBG, " in Rx Poll!!\n");
2882                         break;
2883                 }
2884         }
2885         /* Re enable the Rx interrupts. */
2886         writeq(0x0, &bar0->rx_traffic_mask);
2887         readl(&bar0->rx_traffic_mask);
2888         return pkt_cnt;
2889
2890 no_rx:
2891         for (i = 0; i < config->rx_ring_num; i++) {
2892                 if (fill_rx_buffers(&mac_control->rings[i]) == -ENOMEM) {
2893                         DBG_PRINT(INFO_DBG, "%s:Out of memory", dev->name);
2894                         DBG_PRINT(INFO_DBG, " in Rx Poll!!\n");
2895                         break;
2896                 }
2897         }
2898         return pkt_cnt;
2899 }
2900
2901 #ifdef CONFIG_NET_POLL_CONTROLLER
2902 /**
2903  * s2io_netpoll - netpoll event handler entry point
2904  * @dev : pointer to the device structure.
2905  * Description:
2906  *      This function will be called by upper layer to check for events on the
2907  * interface in situations where interrupts are disabled. It is used for
2908  * specific in-kernel networking tasks, such as remote consoles and kernel
2909  * debugging over the network (example netdump in RedHat).
2910  */
2911 static void s2io_netpoll(struct net_device *dev)
2912 {
2913         struct s2io_nic *nic = dev->priv;
2914         struct mac_info *mac_control;
2915         struct config_param *config;
2916         struct XENA_dev_config __iomem *bar0 = nic->bar0;
2917         u64 val64 = 0xFFFFFFFFFFFFFFFFULL;
2918         int i;
2919
2920         if (pci_channel_offline(nic->pdev))
2921                 return;
2922
2923         disable_irq(dev->irq);
2924
2925         mac_control = &nic->mac_control;
2926         config = &nic->config;
2927
2928         writeq(val64, &bar0->rx_traffic_int);
2929         writeq(val64, &bar0->tx_traffic_int);
2930
2931         /* we need to free up the transmitted skbufs or else netpoll will
2932          * run out of skbs and will fail and eventually netpoll application such
2933          * as netdump will fail.
2934          */
2935         for (i = 0; i < config->tx_fifo_num; i++)
2936                 tx_intr_handler(&mac_control->fifos[i]);
2937
2938         /* check for received packet and indicate up to network */
2939         for (i = 0; i < config->rx_ring_num; i++)
2940                 rx_intr_handler(&mac_control->rings[i]);
2941
2942         for (i = 0; i < config->rx_ring_num; i++) {
2943                 if (fill_rx_buffers(&mac_control->rings[i]) == -ENOMEM) {
2944                         DBG_PRINT(INFO_DBG, "%s:Out of memory", dev->name);
2945                         DBG_PRINT(INFO_DBG, " in Rx Netpoll!!\n");
2946                         break;
2947                 }
2948         }
2949         enable_irq(dev->irq);
2950         return;
2951 }
2952 #endif
2953
2954 /**
2955  *  rx_intr_handler - Rx interrupt handler
2956  *  @nic: device private variable.
2957  *  Description:
2958  *  If the interrupt is because of a received frame or if the
2959  *  receive ring contains fresh as yet un-processed frames,this function is
2960  *  called. It picks out the RxD at which place the last Rx processing had
2961  *  stopped and sends the skb to the OSM's Rx handler and then increments
2962  *  the offset.
2963  *  Return Value:
2964  *  NONE.
2965  */
2966 static void rx_intr_handler(struct ring_info *ring_data)
2967 {
2968         int get_block, put_block;
2969         struct rx_curr_get_info get_info, put_info;
2970         struct RxD_t *rxdp;
2971         struct sk_buff *skb;
2972         int pkt_cnt = 0;
2973         int i;
2974         struct RxD1* rxdp1;
2975         struct RxD3* rxdp3;
2976
2977         get_info = ring_data->rx_curr_get_info;
2978         get_block = get_info.block_index;
2979         memcpy(&put_info, &ring_data->rx_curr_put_info, sizeof(put_info));
2980         put_block = put_info.block_index;
2981         rxdp = ring_data->rx_blocks[get_block].rxds[get_info.offset].virt_addr;
2982
2983         while (RXD_IS_UP2DT(rxdp)) {
2984                 /*
2985                  * If your are next to put index then it's
2986                  * FIFO full condition
2987                  */
2988                 if ((get_block == put_block) &&
2989                     (get_info.offset + 1) == put_info.offset) {
2990                         DBG_PRINT(INTR_DBG, "%s: Ring Full\n",
2991                                 ring_data->dev->name);
2992                         break;
2993                 }
2994                 skb = (struct sk_buff *) ((unsigned long)rxdp->Host_Control);
2995                 if (skb == NULL) {
2996                         DBG_PRINT(ERR_DBG, "%s: The skb is ",
2997                                   ring_data->dev->name);
2998                         DBG_PRINT(ERR_DBG, "Null in Rx Intr\n");
2999                         return;
3000                 }
3001                 if (ring_data->rxd_mode == RXD_MODE_1) {
3002                         rxdp1 = (struct RxD1*)rxdp;
3003                         pci_unmap_single(ring_data->pdev, (dma_addr_t)
3004                                 rxdp1->Buffer0_ptr,
3005                                 ring_data->mtu +
3006                                 HEADER_ETHERNET_II_802_3_SIZE +
3007                                 HEADER_802_2_SIZE +
3008                                 HEADER_SNAP_SIZE,
3009                                 PCI_DMA_FROMDEVICE);
3010                 } else if (ring_data->rxd_mode == RXD_MODE_3B) {
3011                         rxdp3 = (struct RxD3*)rxdp;
3012                         pci_dma_sync_single_for_cpu(ring_data->pdev, (dma_addr_t)
3013                                 rxdp3->Buffer0_ptr,
3014                                 BUF0_LEN, PCI_DMA_FROMDEVICE);
3015                         pci_unmap_single(ring_data->pdev, (dma_addr_t)
3016                                 rxdp3->Buffer2_ptr,
3017                                 ring_data->mtu + 4,
3018                                 PCI_DMA_FROMDEVICE);
3019                 }
3020                 prefetch(skb->data);
3021                 rx_osm_handler(ring_data, rxdp);
3022                 get_info.offset++;
3023                 ring_data->rx_curr_get_info.offset = get_info.offset;
3024                 rxdp = ring_data->rx_blocks[get_block].
3025                                 rxds[get_info.offset].virt_addr;
3026                 if (get_info.offset == rxd_count[ring_data->rxd_mode]) {
3027                         get_info.offset = 0;
3028                         ring_data->rx_curr_get_info.offset = get_info.offset;
3029                         get_block++;
3030                         if (get_block == ring_data->block_count)
3031                                 get_block = 0;
3032                         ring_data->rx_curr_get_info.block_index = get_block;
3033                         rxdp = ring_data->rx_blocks[get_block].block_virt_addr;
3034                 }
3035
3036                 if(ring_data->nic->config.napi){
3037                         ring_data->nic->pkts_to_process -= 1;
3038                         if (!ring_data->nic->pkts_to_process)
3039                                 break;
3040                 }
3041                 pkt_cnt++;
3042                 if ((indicate_max_pkts) && (pkt_cnt > indicate_max_pkts))
3043                         break;
3044         }
3045         if (ring_data->lro) {
3046                 /* Clear all LRO sessions before exiting */
3047                 for (i=0; i<MAX_LRO_SESSIONS; i++) {
3048                         struct lro *lro = &ring_data->lro0_n[i];
3049                         if (lro->in_use) {
3050                                 update_L3L4_header(ring_data->nic, lro);
3051                                 queue_rx_frame(lro->parent, lro->vlan_tag);
3052                                 clear_lro_session(lro);
3053                         }
3054                 }
3055         }
3056 }
3057
3058 /**
3059  *  tx_intr_handler - Transmit interrupt handler
3060  *  @nic : device private variable
3061  *  Description:
3062  *  If an interrupt was raised to indicate DMA complete of the
3063  *  Tx packet, this function is called. It identifies the last TxD
3064  *  whose buffer was freed and frees all skbs whose data have already
3065  *  DMA'ed into the NICs internal memory.
3066  *  Return Value:
3067  *  NONE
3068  */
3069
3070 static void tx_intr_handler(struct fifo_info *fifo_data)
3071 {
3072         struct s2io_nic *nic = fifo_data->nic;
3073         struct tx_curr_get_info get_info, put_info;
3074         struct sk_buff *skb = NULL;
3075         struct TxD *txdlp;
3076         int pkt_cnt = 0;
3077         unsigned long flags = 0;
3078         u8 err_mask;
3079
3080         if (!spin_trylock_irqsave(&fifo_data->tx_lock, flags))
3081                         return;
3082
3083         get_info = fifo_data->tx_curr_get_info;
3084         memcpy(&put_info, &fifo_data->tx_curr_put_info, sizeof(put_info));
3085         txdlp = (struct TxD *) fifo_data->list_info[get_info.offset].
3086             list_virt_addr;
3087         while ((!(txdlp->Control_1 & TXD_LIST_OWN_XENA)) &&
3088                (get_info.offset != put_info.offset) &&
3089                (txdlp->Host_Control)) {
3090                 /* Check for TxD errors */
3091                 if (txdlp->Control_1 & TXD_T_CODE) {
3092                         unsigned long long err;
3093                         err = txdlp->Control_1 & TXD_T_CODE;
3094                         if (err & 0x1) {
3095                                 nic->mac_control.stats_info->sw_stat.
3096                                                 parity_err_cnt++;
3097                         }
3098
3099                         /* update t_code statistics */
3100                         err_mask = err >> 48;
3101                         switch(err_mask) {
3102                                 case 2:
3103                                         nic->mac_control.stats_info->sw_stat.
3104                                                         tx_buf_abort_cnt++;
3105                                 break;
3106
3107                                 case 3:
3108                                         nic->mac_control.stats_info->sw_stat.
3109                                                         tx_desc_abort_cnt++;
3110                                 break;
3111
3112                                 case 7:
3113                                         nic->mac_control.stats_info->sw_stat.
3114                                                         tx_parity_err_cnt++;
3115                                 break;
3116
3117                                 case 10:
3118                                         nic->mac_control.stats_info->sw_stat.
3119                                                         tx_link_loss_cnt++;
3120                                 break;
3121
3122                                 case 15:
3123                                         nic->mac_control.stats_info->sw_stat.
3124                                                         tx_list_proc_err_cnt++;
3125                                 break;
3126                         }
3127                 }
3128
3129                 skb = s2io_txdl_getskb(fifo_data, txdlp, get_info.offset);
3130                 if (skb == NULL) {
3131                         spin_unlock_irqrestore(&fifo_data->tx_lock, flags);
3132                         DBG_PRINT(ERR_DBG, "%s: Null skb ",
3133                         __FUNCTION__);
3134                         DBG_PRINT(ERR_DBG, "in Tx Free Intr\n");
3135                         return;
3136                 }
3137                 pkt_cnt++;
3138
3139                 /* Updating the statistics block */
3140                 nic->stats.tx_bytes += skb->len;
3141                 nic->mac_control.stats_info->sw_stat.mem_freed += skb->truesize;
3142                 dev_kfree_skb_irq(skb);
3143
3144                 get_info.offset++;
3145                 if (get_info.offset == get_info.fifo_len + 1)
3146                         get_info.offset = 0;
3147                 txdlp = (struct TxD *) fifo_data->list_info
3148                     [get_info.offset].list_virt_addr;
3149                 fifo_data->tx_curr_get_info.offset =
3150                     get_info.offset;
3151         }
3152
3153         s2io_wake_tx_queue(fifo_data, pkt_cnt, nic->config.multiq);
3154
3155         spin_unlock_irqrestore(&fifo_data->tx_lock, flags);
3156 }
3157
3158 /**
3159  *  s2io_mdio_write - Function to write in to MDIO registers
3160  *  @mmd_type : MMD type value (PMA/PMD/WIS/PCS/PHYXS)
3161  *  @addr     : address value
3162  *  @value    : data value
3163  *  @dev      : pointer to net_device structure
3164  *  Description:
3165  *  This function is used to write values to the MDIO registers
3166  *  NONE
3167  */
3168 static void s2io_mdio_write(u32 mmd_type, u64 addr, u16 value, struct net_device *dev)
3169 {
3170         u64 val64 = 0x0;
3171         struct s2io_nic *sp = dev->priv;
3172         struct XENA_dev_config __iomem *bar0 = sp->bar0;
3173
3174         //address transaction
3175         val64 = val64 | MDIO_MMD_INDX_ADDR(addr)
3176                         | MDIO_MMD_DEV_ADDR(mmd_type)
3177                         | MDIO_MMS_PRT_ADDR(0x0);
3178         writeq(val64, &bar0->mdio_control);
3179         val64 = val64 | MDIO_CTRL_START_TRANS(0xE);
3180         writeq(val64, &bar0->mdio_control);
3181         udelay(100);
3182
3183         //Data transaction
3184         val64 = 0x0;
3185         val64 = val64 | MDIO_MMD_INDX_ADDR(addr)
3186                         | MDIO_MMD_DEV_ADDR(mmd_type)
3187                         | MDIO_MMS_PRT_ADDR(0x0)
3188                         | MDIO_MDIO_DATA(value)
3189                         | MDIO_OP(MDIO_OP_WRITE_TRANS);
3190         writeq(val64, &bar0->mdio_control);
3191         val64 = val64 | MDIO_CTRL_START_TRANS(0xE);
3192         writeq(val64, &bar0->mdio_control);
3193         udelay(100);
3194
3195         val64 = 0x0;
3196         val64 = val64 | MDIO_MMD_INDX_ADDR(addr)
3197         | MDIO_MMD_DEV_ADDR(mmd_type)
3198         | MDIO_MMS_PRT_ADDR(0x0)
3199         | MDIO_OP(MDIO_OP_READ_TRANS);
3200         writeq(val64, &bar0->mdio_control);
3201         val64 = val64 | MDIO_CTRL_START_TRANS(0xE);
3202         writeq(val64, &bar0->mdio_control);
3203         udelay(100);
3204
3205 }
3206
3207 /**
3208  *  s2io_mdio_read - Function to write in to MDIO registers
3209  *  @mmd_type : MMD type value (PMA/PMD/WIS/PCS/PHYXS)
3210  *  @addr     : address value
3211  *  @dev      : pointer to net_device structure
3212  *  Description:
3213  *  This function is used to read values to the MDIO registers
3214  *  NONE
3215  */
3216 static u64 s2io_mdio_read(u32 mmd_type, u64 addr, struct net_device *dev)
3217 {
3218         u64 val64 = 0x0;
3219         u64 rval64 = 0x0;
3220         struct s2io_nic *sp = dev->priv;
3221         struct XENA_dev_config __iomem *bar0 = sp->bar0;
3222
3223         /* address transaction */
3224         val64 = val64 | MDIO_MMD_INDX_ADDR(addr)
3225                         | MDIO_MMD_DEV_ADDR(mmd_type)
3226                         | MDIO_MMS_PRT_ADDR(0x0);
3227         writeq(val64, &bar0->mdio_control);
3228         val64 = val64 | MDIO_CTRL_START_TRANS(0xE);
3229         writeq(val64, &bar0->mdio_control);
3230         udelay(100);
3231
3232         /* Data transaction */
3233         val64 = 0x0;
3234         val64 = val64 | MDIO_MMD_INDX_ADDR(addr)
3235                         | MDIO_MMD_DEV_ADDR(mmd_type)
3236                         | MDIO_MMS_PRT_ADDR(0x0)
3237                         | MDIO_OP(MDIO_OP_READ_TRANS);
3238         writeq(val64, &bar0->mdio_control);
3239         val64 = val64 | MDIO_CTRL_START_TRANS(0xE);
3240         writeq(val64, &bar0->mdio_control);
3241         udelay(100);
3242
3243         /* Read the value from regs */
3244         rval64 = readq(&bar0->mdio_control);
3245         rval64 = rval64 & 0xFFFF0000;
3246         rval64 = rval64 >> 16;
3247         return rval64;
3248 }
3249 /**
3250  *  s2io_chk_xpak_counter - Function to check the status of the xpak counters
3251  *  @counter      : couter value to be updated
3252  *  @flag         : flag to indicate the status
3253  *  @type         : counter type
3254  *  Description:
3255  *  This function is to check the status of the xpak counters value
3256  *  NONE
3257  */
3258
3259 static void s2io_chk_xpak_counter(u64 *counter, u64 * regs_stat, u32 index, u16 flag, u16 type)
3260 {
3261         u64 mask = 0x3;
3262         u64 val64;
3263         int i;
3264         for(i = 0; i <index; i++)
3265                 mask = mask << 0x2;
3266
3267         if(flag > 0)
3268         {
3269                 *counter = *counter + 1;
3270                 val64 = *regs_stat & mask;
3271                 val64 = val64 >> (index * 0x2);
3272                 val64 = val64 + 1;
3273                 if(val64 == 3)
3274                 {
3275                         switch(type)
3276                         {
3277                         case 1:
3278                                 DBG_PRINT(ERR_DBG, "Take Xframe NIC out of "
3279                                           "service. Excessive temperatures may "
3280                                           "result in premature transceiver "
3281                                           "failure \n");
3282                         break;
3283                         case 2:
3284                                 DBG_PRINT(ERR_DBG, "Take Xframe NIC out of "
3285                                           "service Excessive bias currents may "
3286                                           "indicate imminent laser diode "
3287                                           "failure \n");
3288                         break;
3289                         case 3:
3290                                 DBG_PRINT(ERR_DBG, "Take Xframe NIC out of "
3291                                           "service Excessive laser output "
3292                                           "power may saturate far-end "
3293                                           "receiver\n");
3294                         break;
3295                         default:
3296                                 DBG_PRINT(ERR_DBG, "Incorrect XPAK Alarm "
3297                                           "type \n");
3298                         }
3299                         val64 = 0x0;
3300                 }
3301                 val64 = val64 << (index * 0x2);
3302                 *regs_stat = (*regs_stat & (~mask)) | (val64);
3303
3304         } else {
3305                 *regs_stat = *regs_stat & (~mask);
3306         }
3307 }
3308
3309 /**
3310  *  s2io_updt_xpak_counter - Function to update the xpak counters
3311  *  @dev         : pointer to net_device struct
3312  *  Description:
3313  *  This function is to upate the status of the xpak counters value
3314  *  NONE
3315  */
3316 static void s2io_updt_xpak_counter(struct net_device *dev)
3317 {
3318         u16 flag  = 0x0;
3319         u16 type  = 0x0;
3320         u16 val16 = 0x0;
3321         u64 val64 = 0x0;
3322         u64 addr  = 0x0;
3323
3324         struct s2io_nic *sp = dev->priv;
3325         struct stat_block *stat_info = sp->mac_control.stats_info;
3326
3327         /* Check the communication with the MDIO slave */
3328         addr = 0x0000;
3329         val64 = 0x0;
3330         val64 = s2io_mdio_read(MDIO_MMD_PMA_DEV_ADDR, addr, dev);
3331         if((val64 == 0xFFFF) || (val64 == 0x0000))
3332         {
3333                 DBG_PRINT(ERR_DBG, "ERR: MDIO slave access failed - "
3334                           "Returned %llx\n", (unsigned long long)val64);
3335                 return;
3336         }
3337
3338         /* Check for the expecte value of 2040 at PMA address 0x0000 */
3339         if(val64 != 0x2040)
3340         {
3341                 DBG_PRINT(ERR_DBG, "Incorrect value at PMA address 0x0000 - ");
3342                 DBG_PRINT(ERR_DBG, "Returned: %llx- Expected: 0x2040\n",
3343                           (unsigned long long)val64);
3344                 return;
3345         }
3346
3347         /* Loading the DOM register to MDIO register */
3348         addr = 0xA100;
3349         s2io_mdio_write(MDIO_MMD_PMA_DEV_ADDR, addr, val16, dev);
3350         val64 = s2io_mdio_read(MDIO_MMD_PMA_DEV_ADDR, addr, dev);
3351
3352         /* Reading the Alarm flags */
3353         addr = 0xA070;
3354         val64 = 0x0;
3355         val64 = s2io_mdio_read(MDIO_MMD_PMA_DEV_ADDR, addr, dev);
3356
3357         flag = CHECKBIT(val64, 0x7);
3358         type = 1;
3359         s2io_chk_xpak_counter(&stat_info->xpak_stat.alarm_transceiver_temp_high,
3360                                 &stat_info->xpak_stat.xpak_regs_stat,
3361                                 0x0, flag, type);
3362
3363         if(CHECKBIT(val64, 0x6))
3364                 stat_info->xpak_stat.alarm_transceiver_temp_low++;
3365
3366         flag = CHECKBIT(val64, 0x3);
3367         type = 2;
3368         s2io_chk_xpak_counter(&stat_info->xpak_stat.alarm_laser_bias_current_high,
3369                                 &stat_info->xpak_stat.xpak_regs_stat,
3370                                 0x2, flag, type);
3371
3372         if(CHECKBIT(val64, 0x2))
3373                 stat_info->xpak_stat.alarm_laser_bias_current_low++;
3374
3375         flag = CHECKBIT(val64, 0x1);
3376         type = 3;
3377         s2io_chk_xpak_counter(&stat_info->xpak_stat.alarm_laser_output_power_high,
3378                                 &stat_info->xpak_stat.xpak_regs_stat,
3379                                 0x4, flag, type);
3380
3381         if(CHECKBIT(val64, 0x0))
3382                 stat_info->xpak_stat.alarm_laser_output_power_low++;
3383
3384         /* Reading the Warning flags */
3385         addr = 0xA074;
3386         val64 = 0x0;
3387         val64 = s2io_mdio_read(MDIO_MMD_PMA_DEV_ADDR, addr, dev);
3388
3389         if(CHECKBIT(val64, 0x7))
3390                 stat_info->xpak_stat.warn_transceiver_temp_high++;
3391
3392         if(CHECKBIT(val64, 0x6))
3393                 stat_info->xpak_stat.warn_transceiver_temp_low++;
3394
3395         if(CHECKBIT(val64, 0x3))
3396                 stat_info->xpak_stat.warn_laser_bias_current_high++;
3397
3398         if(CHECKBIT(val64, 0x2))
3399                 stat_info->xpak_stat.warn_laser_bias_current_low++;
3400
3401         if(CHECKBIT(val64, 0x1))
3402                 stat_info->xpak_stat.warn_laser_output_power_high++;
3403
3404         if(CHECKBIT(val64, 0x0))
3405                 stat_info->xpak_stat.warn_laser_output_power_low++;
3406 }
3407
3408 /**
3409  *  wait_for_cmd_complete - waits for a command to complete.
3410  *  @sp : private member of the device structure, which is a pointer to the
3411  *  s2io_nic structure.
3412  *  Description: Function that waits for a command to Write into RMAC
3413  *  ADDR DATA registers to be completed and returns either success or
3414  *  error depending on whether the command was complete or not.
3415  *  Return value:
3416  *   SUCCESS on success and FAILURE on failure.
3417  */
3418
3419 static int wait_for_cmd_complete(void __iomem *addr, u64 busy_bit,
3420                                 int bit_state)
3421 {
3422         int ret = FAILURE, cnt = 0, delay = 1;
3423         u64 val64;
3424
3425         if ((bit_state != S2IO_BIT_RESET) && (bit_state != S2IO_BIT_SET))
3426                 return FAILURE;
3427
3428         do {
3429                 val64 = readq(addr);
3430                 if (bit_state == S2IO_BIT_RESET) {
3431                         if (!(val64 & busy_bit)) {
3432                                 ret = SUCCESS;
3433                                 break;
3434                         }
3435                 } else {
3436                         if (!(val64 & busy_bit)) {
3437                                 ret = SUCCESS;
3438                                 break;
3439                         }
3440                 }
3441
3442                 if(in_interrupt())
3443                         mdelay(delay);
3444                 else
3445                         msleep(delay);
3446
3447                 if (++cnt >= 10)
3448                         delay = 50;
3449         } while (cnt < 20);
3450         return ret;
3451 }
3452 /*
3453  * check_pci_device_id - Checks if the device id is supported
3454  * @id : device id
3455  * Description: Function to check if the pci device id is supported by driver.
3456  * Return value: Actual device id if supported else PCI_ANY_ID
3457  */
3458 static u16 check_pci_device_id(u16 id)
3459 {
3460         switch (id) {
3461         case PCI_DEVICE_ID_HERC_WIN:
3462         case PCI_DEVICE_ID_HERC_UNI:
3463                 return XFRAME_II_DEVICE;
3464         case PCI_DEVICE_ID_S2IO_UNI:
3465         case PCI_DEVICE_ID_S2IO_WIN:
3466                 return XFRAME_I_DEVICE;
3467         default:
3468                 return PCI_ANY_ID;
3469         }
3470 }
3471
3472 /**
3473  *  s2io_reset - Resets the card.
3474  *  @sp : private member of the device structure.
3475  *  Description: Function to Reset the card. This function then also
3476  *  restores the previously saved PCI configuration space registers as
3477  *  the card reset also resets the configuration space.
3478  *  Return value:
3479  *  void.
3480  */
3481
3482 static void s2io_reset(struct s2io_nic * sp)
3483 {
3484         struct XENA_dev_config __iomem *bar0 = sp->bar0;
3485         u64 val64;
3486         u16 subid, pci_cmd;
3487         int i;
3488         u16 val16;
3489         unsigned long long up_cnt, down_cnt, up_time, down_time, reset_cnt;
3490         unsigned long long mem_alloc_cnt, mem_free_cnt, watchdog_cnt;
3491
3492         DBG_PRINT(INIT_DBG,"%s - Resetting XFrame card %s\n",
3493                         __FUNCTION__, sp->dev->name);
3494
3495         /* Back up  the PCI-X CMD reg, dont want to lose MMRBC, OST settings */
3496         pci_read_config_word(sp->pdev, PCIX_COMMAND_REGISTER, &(pci_cmd));
3497
3498         val64 = SW_RESET_ALL;
3499         writeq(val64, &bar0->sw_reset);
3500         if (strstr(sp->product_name, "CX4")) {
3501                 msleep(750);
3502         }
3503         msleep(250);
3504         for (i = 0; i < S2IO_MAX_PCI_CONFIG_SPACE_REINIT; i++) {
3505
3506                 /* Restore the PCI state saved during initialization. */
3507                 pci_restore_state(sp->pdev);
3508                 pci_read_config_word(sp->pdev, 0x2, &val16);
3509                 if (check_pci_device_id(val16) != (u16)PCI_ANY_ID)
3510                         break;
3511                 msleep(200);
3512         }
3513
3514         if (check_pci_device_id(val16) == (u16)PCI_ANY_ID) {
3515                 DBG_PRINT(ERR_DBG,"%s SW_Reset failed!\n", __FUNCTION__);
3516         }
3517
3518         pci_write_config_word(sp->pdev, PCIX_COMMAND_REGISTER, pci_cmd);
3519
3520         s2io_init_pci(sp);
3521
3522         /* Set swapper to enable I/O register access */
3523         s2io_set_swapper(sp);
3524
3525         /* restore mac_addr entries */
3526         do_s2io_restore_unicast_mc(sp);
3527
3528         /* Restore the MSIX table entries from local variables */
3529         restore_xmsi_data(sp);
3530
3531         /* Clear certain PCI/PCI-X fields after reset */
3532         if (sp->device_type == XFRAME_II_DEVICE) {
3533                 /* Clear "detected parity error" bit */
3534                 pci_write_config_word(sp->pdev, PCI_STATUS, 0x8000);
3535
3536                 /* Clearing PCIX Ecc status register */
3537                 pci_write_config_dword(sp->pdev, 0x68, 0x7C);
3538
3539                 /* Clearing PCI_STATUS error reflected here */
3540                 writeq(s2BIT(62), &bar0->txpic_int_reg);
3541         }
3542
3543         /* Reset device statistics maintained by OS */
3544         memset(&sp->stats, 0, sizeof (struct net_device_stats));
3545
3546         up_cnt = sp->mac_control.stats_info->sw_stat.link_up_cnt;
3547         down_cnt = sp->mac_control.stats_info->sw_stat.link_down_cnt;
3548         up_time = sp->mac_control.stats_info->sw_stat.link_up_time;
3549         down_time = sp->mac_control.stats_info->sw_stat.link_down_time;
3550         reset_cnt = sp->mac_control.stats_info->sw_stat.soft_reset_cnt;
3551         mem_alloc_cnt = sp->mac_control.stats_info->sw_stat.mem_allocated;
3552         mem_free_cnt = sp->mac_control.stats_info->sw_stat.mem_freed;
3553         watchdog_cnt = sp->mac_control.stats_info->sw_stat.watchdog_timer_cnt;
3554         /* save link up/down time/cnt, reset/memory/watchdog cnt */
3555         memset(sp->mac_control.stats_info, 0, sizeof(struct stat_block));
3556         /* restore link up/down time/cnt, reset/memory/watchdog cnt */
3557         sp->mac_control.stats_info->sw_stat.link_up_cnt = up_cnt;
3558         sp->mac_control.stats_info->sw_stat.link_down_cnt = down_cnt;
3559         sp->mac_control.stats_info->sw_stat.link_up_time = up_time;
3560         sp->mac_control.stats_info->sw_stat.link_down_time = down_time;
3561         sp->mac_control.stats_info->sw_stat.soft_reset_cnt = reset_cnt;
3562         sp->mac_control.stats_info->sw_stat.mem_allocated = mem_alloc_cnt;
3563         sp->mac_control.stats_info->sw_stat.mem_freed = mem_free_cnt;
3564         sp->mac_control.stats_info->sw_stat.watchdog_timer_cnt = watchdog_cnt;
3565
3566         /* SXE-002: Configure link and activity LED to turn it off */
3567         subid = sp->pdev->subsystem_device;
3568         if (((subid & 0xFF) >= 0x07) &&
3569             (sp->device_type == XFRAME_I_DEVICE)) {
3570                 val64 = readq(&bar0->gpio_control);
3571                 val64 |= 0x0000800000000000ULL;
3572                 writeq(val64, &bar0->gpio_control);
3573                 val64 = 0x0411040400000000ULL;
3574                 writeq(val64, (void __iomem *)bar0 + 0x2700);
3575         }
3576
3577         /*
3578          * Clear spurious ECC interrupts that would have occured on
3579          * XFRAME II cards after reset.
3580          */
3581         if (sp->device_type == XFRAME_II_DEVICE) {
3582                 val64 = readq(&bar0->pcc_err_reg);
3583                 writeq(val64, &bar0->pcc_err_reg);
3584         }
3585
3586         sp->device_enabled_once = FALSE;
3587 }
3588
3589 /**
3590  *  s2io_set_swapper - to set the swapper controle on the card
3591  *  @sp : private member of the device structure,
3592  *  pointer to the s2io_nic structure.
3593  *  Description: Function to set the swapper control on the card
3594  *  correctly depending on the 'endianness' of the system.
3595  *  Return value:
3596  *  SUCCESS on success and FAILURE on failure.
3597  */
3598
3599 static int s2io_set_swapper(struct s2io_nic * sp)
3600 {
3601         struct net_device *dev = sp->dev;
3602         struct XENA_dev_config __iomem *bar0 = sp->bar0;
3603         u64 val64, valt, valr;
3604
3605         /*
3606          * Set proper endian settings and verify the same by reading
3607          * the PIF Feed-back register.
3608          */
3609
3610         val64 = readq(&bar0->pif_rd_swapper_fb);
3611         if (val64 != 0x0123456789ABCDEFULL) {
3612                 int i = 0;
3613                 u64 value[] = { 0xC30000C3C30000C3ULL,   /* FE=1, SE=1 */
3614                                 0x8100008181000081ULL,  /* FE=1, SE=0 */
3615                                 0x4200004242000042ULL,  /* FE=0, SE=1 */
3616                                 0};                     /* FE=0, SE=0 */
3617
3618                 while(i<4) {
3619                         writeq(value[i], &bar0->swapper_ctrl);
3620                         val64 = readq(&bar0->pif_rd_swapper_fb);
3621                         if (val64 == 0x0123456789ABCDEFULL)
3622                                 break;
3623                         i++;
3624                 }
3625                 if (i == 4) {
3626                         DBG_PRINT(ERR_DBG, "%s: Endian settings are wrong, ",
3627                                 dev->name);
3628                         DBG_PRINT(ERR_DBG, "feedback read %llx\n",
3629                                 (unsigned long long) val64);
3630                         return FAILURE;
3631                 }
3632                 valr = value[i];
3633         } else {
3634                 valr = readq(&bar0->swapper_ctrl);
3635         }
3636
3637         valt = 0x0123456789ABCDEFULL;
3638         writeq(valt, &bar0->xmsi_address);
3639         val64 = readq(&bar0->xmsi_address);
3640
3641         if(val64 != valt) {
3642                 int i = 0;
3643                 u64 value[] = { 0x00C3C30000C3C300ULL,  /* FE=1, SE=1 */
3644                                 0x0081810000818100ULL,  /* FE=1, SE=0 */
3645                                 0x0042420000424200ULL,  /* FE=0, SE=1 */
3646                                 0};                     /* FE=0, SE=0 */
3647
3648                 while(i<4) {
3649                         writeq((value[i] | valr), &bar0->swapper_ctrl);
3650                         writeq(valt, &bar0->xmsi_address);
3651                         val64 = readq(&bar0->xmsi_address);
3652                         if(val64 == valt)
3653                                 break;
3654                         i++;
3655                 }
3656                 if(i == 4) {
3657                         unsigned long long x = val64;
3658                         DBG_PRINT(ERR_DBG, "Write failed, Xmsi_addr ");
3659                         DBG_PRINT(ERR_DBG, "reads:0x%llx\n", x);
3660                         return FAILURE;
3661                 }
3662         }
3663         val64 = readq(&bar0->swapper_ctrl);
3664         val64 &= 0xFFFF000000000000ULL;
3665
3666 #ifdef  __BIG_ENDIAN
3667         /*
3668          * The device by default set to a big endian format, so a
3669          * big endian driver need not set anything.
3670          */
3671         val64 |= (SWAPPER_CTRL_TXP_FE |
3672                  SWAPPER_CTRL_TXP_SE |
3673                  SWAPPER_CTRL_TXD_R_FE |
3674                  SWAPPER_CTRL_TXD_W_FE |
3675                  SWAPPER_CTRL_TXF_R_FE |
3676                  SWAPPER_CTRL_RXD_R_FE |
3677                  SWAPPER_CTRL_RXD_W_FE |
3678                  SWAPPER_CTRL_RXF_W_FE |
3679                  SWAPPER_CTRL_XMSI_FE |
3680                  SWAPPER_CTRL_STATS_FE | SWAPPER_CTRL_STATS_SE);
3681         if (sp->config.intr_type == INTA)
3682                 val64 |= SWAPPER_CTRL_XMSI_SE;
3683         writeq(val64, &bar0->swapper_ctrl);
3684 #else
3685         /*
3686          * Initially we enable all bits to make it accessible by the
3687          * driver, then we selectively enable only those bits that
3688          * we want to set.
3689          */
3690         val64 |= (SWAPPER_CTRL_TXP_FE |
3691                  SWAPPER_CTRL_TXP_SE |
3692                  SWAPPER_CTRL_TXD_R_FE |
3693                  SWAPPER_CTRL_TXD_R_SE |
3694                  SWAPPER_CTRL_TXD_W_FE |
3695                  SWAPPER_CTRL_TXD_W_SE |
3696                  SWAPPER_CTRL_TXF_R_FE |
3697                  SWAPPER_CTRL_RXD_R_FE |
3698                  SWAPPER_CTRL_RXD_R_SE |
3699                  SWAPPER_CTRL_RXD_W_FE |
3700                  SWAPPER_CTRL_RXD_W_SE |
3701                  SWAPPER_CTRL_RXF_W_FE |
3702                  SWAPPER_CTRL_XMSI_FE |
3703                  SWAPPER_CTRL_STATS_FE | SWAPPER_CTRL_STATS_SE);
3704         if (sp->config.intr_type == INTA)
3705                 val64 |= SWAPPER_CTRL_XMSI_SE;
3706         writeq(val64, &bar0->swapper_ctrl);
3707 #endif
3708         val64 = readq(&bar0->swapper_ctrl);
3709
3710         /*
3711          * Verifying if endian settings are accurate by reading a
3712          * feedback register.
3713          */
3714         val64 = readq(&bar0->pif_rd_swapper_fb);
3715         if (val64 != 0x0123456789ABCDEFULL) {
3716                 /* Endian settings are incorrect, calls for another dekko. */
3717                 DBG_PRINT(ERR_DBG, "%s: Endian settings are wrong, ",
3718                           dev->name);
3719                 DBG_PRINT(ERR_DBG, "feedback read %llx\n",
3720                           (unsigned long long) val64);
3721                 return FAILURE;
3722         }
3723
3724         return SUCCESS;
3725 }
3726
3727 static int wait_for_msix_trans(struct s2io_nic *nic, int i)
3728 {
3729         struct XENA_dev_config __iomem *bar0 = nic->bar0;
3730         u64 val64;
3731         int ret = 0, cnt = 0;
3732
3733         do {
3734                 val64 = readq(&bar0->xmsi_access);
3735                 if (!(val64 & s2BIT(15)))
3736                         break;
3737                 mdelay(1);
3738                 cnt++;
3739         } while(cnt < 5);
3740         if (cnt == 5) {
3741                 DBG_PRINT(ERR_DBG, "XMSI # %d Access failed\n", i);
3742                 ret = 1;
3743         }
3744
3745         return ret;
3746 }
3747
3748 static void restore_xmsi_data(struct s2io_nic *nic)
3749 {
3750         struct XENA_dev_config __iomem *bar0 = nic->bar0;
3751         u64 val64;
3752         int i;
3753
3754         for (i=0; i < MAX_REQUESTED_MSI_X; i++) {
3755                 writeq(nic->msix_info[i].addr, &bar0->xmsi_address);
3756                 writeq(nic->msix_info[i].data, &bar0->xmsi_data);
3757                 val64 = (s2BIT(7) | s2BIT(15) | vBIT(i, 26, 6));
3758                 writeq(val64, &bar0->xmsi_access);
3759                 if (wait_for_msix_trans(nic, i)) {
3760                         DBG_PRINT(ERR_DBG, "failed in %s\n", __FUNCTION__);
3761                         continue;
3762                 }
3763         }
3764 }
3765
3766 static void store_xmsi_data(struct s2io_nic *nic)
3767 {
3768         struct XENA_dev_config __iomem *bar0 = nic->bar0;
3769         u64 val64, addr, data;
3770         int i;
3771
3772         /* Store and display */
3773         for (i=0; i < MAX_REQUESTED_MSI_X; i++) {
3774                 val64 = (s2BIT(15) | vBIT(i, 26, 6));
3775                 writeq(val64, &bar0->xmsi_access);
3776                 if (wait_for_msix_trans(nic, i)) {
3777                         DBG_PRINT(ERR_DBG, "failed in %s\n", __FUNCTION__);
3778                         continue;
3779                 }
3780                 addr = readq(&bar0->xmsi_address);
3781                 data = readq(&bar0->xmsi_data);
3782                 if (addr && data) {
3783                         nic->msix_info[i].addr = addr;
3784                         nic->msix_info[i].data = data;
3785                 }
3786         }
3787 }
3788
3789 static int s2io_enable_msi_x(struct s2io_nic *nic)
3790 {
3791         struct XENA_dev_config __iomem *bar0 = nic->bar0;
3792         u64 rx_mat;
3793         u16 msi_control; /* Temp variable */
3794         int ret, i, j, msix_indx = 1;
3795
3796         nic->entries = kcalloc(MAX_REQUESTED_MSI_X, sizeof(struct msix_entry),
3797                                GFP_KERNEL);
3798         if (!nic->entries) {
3799                 DBG_PRINT(INFO_DBG, "%s: Memory allocation failed\n", \
3800                         __FUNCTION__);
3801                 nic->mac_control.stats_info->sw_stat.mem_alloc_fail_cnt++;
3802                 return -ENOMEM;
3803         }
3804         nic->mac_control.stats_info->sw_stat.mem_allocated
3805                 += (MAX_REQUESTED_MSI_X * sizeof(struct msix_entry));
3806
3807         nic->s2io_entries =
3808                 kcalloc(MAX_REQUESTED_MSI_X, sizeof(struct s2io_msix_entry),
3809                                    GFP_KERNEL);
3810         if (!nic->s2io_entries) {
3811                 DBG_PRINT(INFO_DBG, "%s: Memory allocation failed\n",
3812                         __FUNCTION__);
3813                 nic->mac_control.stats_info->sw_stat.mem_alloc_fail_cnt++;
3814                 kfree(nic->entries);
3815                 nic->mac_control.stats_info->sw_stat.mem_freed
3816                         += (MAX_REQUESTED_MSI_X * sizeof(struct msix_entry));
3817                 return -ENOMEM;
3818         }
3819          nic->mac_control.stats_info->sw_stat.mem_allocated
3820                 += (MAX_REQUESTED_MSI_X * sizeof(struct s2io_msix_entry));
3821
3822         nic->entries[0].entry = 0;
3823         nic->s2io_entries[0].entry = 0;
3824         nic->s2io_entries[0].in_use = MSIX_FLG;
3825         nic->s2io_entries[0].type = MSIX_ALARM_TYPE;
3826         nic->s2io_entries[0].arg = &nic->mac_control.fifos;
3827
3828         for (i = 1; i < MAX_REQUESTED_MSI_X; i++) {
3829                 nic->entries[i].entry = i;
3830                 nic->s2io_entries[i].entry = i;
3831                 nic->s2io_entries[i].arg = NULL;
3832                 nic->s2io_entries[i].in_use = 0;
3833         }
3834
3835         rx_mat = readq(&bar0->rx_mat);
3836         for (j = 0; j < nic->config.rx_ring_num; j++, msix_indx++) {
3837                 rx_mat |= RX_MAT_SET(j, msix_indx);
3838                 nic->s2io_entries[msix_indx].arg
3839                         = &nic->mac_control.rings[j];
3840                 nic->s2io_entries[msix_indx].type = MSIX_RING_TYPE;
3841                 nic->s2io_entries[msix_indx].in_use = MSIX_FLG;
3842         }
3843         writeq(rx_mat, &bar0->rx_mat);
3844
3845         nic->avail_msix_vectors = 0;
3846         ret = pci_enable_msix(nic->pdev, nic->entries, MAX_REQUESTED_MSI_X);
3847         /* We fail init if error or we get less vectors than min required */
3848         if (ret >= (nic->config.tx_fifo_num + nic->config.rx_ring_num + 1)) {
3849                 nic->avail_msix_vectors = ret;
3850                 ret = pci_enable_msix(nic->pdev, nic->entries, ret);
3851         }
3852         if (ret) {
3853                 DBG_PRINT(ERR_DBG, "%s: Enabling MSIX failed\n", nic->dev->name);
3854                 kfree(nic->entries);
3855                 nic->mac_control.stats_info->sw_stat.mem_freed
3856                         += (MAX_REQUESTED_MSI_X * sizeof(struct msix_entry));
3857                 kfree(nic->s2io_entries);
3858                 nic->mac_control.stats_info->sw_stat.mem_freed
3859                 += (MAX_REQUESTED_MSI_X * sizeof(struct s2io_msix_entry));
3860                 nic->entries = NULL;
3861                 nic->s2io_entries = NULL;
3862                 nic->avail_msix_vectors = 0;
3863                 return -ENOMEM;
3864         }
3865         if (!nic->avail_msix_vectors)
3866                 nic->avail_msix_vectors = MAX_REQUESTED_MSI_X;
3867
3868         /*
3869          * To enable MSI-X, MSI also needs to be enabled, due to a bug
3870          * in the herc NIC. (Temp change, needs to be removed later)
3871          */
3872         pci_read_config_word(nic->pdev, 0x42, &msi_control);
3873         msi_control |= 0x1; /* Enable MSI */
3874         pci_write_config_word(nic->pdev, 0x42, msi_control);
3875
3876         return 0;
3877 }
3878
3879 /* Handle software interrupt used during MSI(X) test */
3880 static irqreturn_t s2io_test_intr(int irq, void *dev_id)
3881 {
3882         struct s2io_nic *sp = dev_id;
3883
3884         sp->msi_detected = 1;
3885         wake_up(&sp->msi_wait);
3886
3887         return IRQ_HANDLED;
3888 }
3889
3890 /* Test interrupt path by forcing a a software IRQ */
3891 static int s2io_test_msi(struct s2io_nic *sp)
3892 {
3893         struct pci_dev *pdev = sp->pdev;
3894         struct XENA_dev_config __iomem *bar0 = sp->bar0;
3895         int err;
3896         u64 val64, saved64;
3897
3898         err = request_irq(sp->entries[1].vector, s2io_test_intr, 0,
3899                         sp->name, sp);
3900         if (err) {
3901                 DBG_PRINT(ERR_DBG, "%s: PCI %s: cannot assign irq %d\n",
3902                        sp->dev->name, pci_name(pdev), pdev->irq);
3903                 return err;
3904         }
3905
3906         init_waitqueue_head (&sp->msi_wait);
3907         sp->msi_detected = 0;
3908
3909         saved64 = val64 = readq(&bar0->scheduled_int_ctrl);
3910         val64 |= SCHED_INT_CTRL_ONE_SHOT;
3911         val64 |= SCHED_INT_CTRL_TIMER_EN;
3912         val64 |= SCHED_INT_CTRL_INT2MSI(1);
3913         writeq(val64, &bar0->scheduled_int_ctrl);
3914
3915         wait_event_timeout(sp->msi_wait, sp->msi_detected, HZ/10);
3916
3917         if (!sp->msi_detected) {
3918                 /* MSI(X) test failed, go back to INTx mode */
3919                 DBG_PRINT(ERR_DBG, "%s: PCI %s: No interrupt was generated "
3920                         "using MSI(X) during test\n", sp->dev->name,
3921                         pci_name(pdev));
3922
3923                 err = -EOPNOTSUPP;
3924         }
3925
3926         free_irq(sp->entries[1].vector, sp);
3927
3928         writeq(saved64, &bar0->scheduled_int_ctrl);
3929
3930         return err;
3931 }
3932
3933 static void remove_msix_isr(struct s2io_nic *sp)
3934 {
3935         int i;
3936         u16 msi_control;
3937
3938         for (i = 0; i < MAX_REQUESTED_MSI_X; i++) {
3939                 if (sp->s2io_entries[i].in_use ==
3940                         MSIX_REGISTERED_SUCCESS) {
3941                         int vector = sp->entries[i].vector;
3942                         void *arg = sp->s2io_entries[i].arg;
3943                         free_irq(vector, arg);
3944                 }
3945         }
3946
3947         kfree(sp->entries);
3948         kfree(sp->s2io_entries);
3949         sp->entries = NULL;
3950         sp->s2io_entries = NULL;
3951
3952         pci_read_config_word(sp->pdev, 0x42, &msi_control);
3953         msi_control &= 0xFFFE; /* Disable MSI */
3954         pci_write_config_word(sp->pdev, 0x42, msi_control);
3955
3956         pci_disable_msix(sp->pdev);
3957 }
3958
3959 static void remove_inta_isr(struct s2io_nic *sp)
3960 {
3961         struct net_device *dev = sp->dev;
3962
3963         free_irq(sp->pdev->irq, dev);
3964 }
3965
3966 /* ********************************************************* *
3967  * Functions defined below concern the OS part of the driver *
3968  * ********************************************************* */
3969
3970 /**
3971  *  s2io_open - open entry point of the driver
3972  *  @dev : pointer to the device structure.
3973  *  Description:
3974  *  This function is the open entry point of the driver. It mainly calls a
3975  *  function to allocate Rx buffers and inserts them into the buffer
3976  *  descriptors and then enables the Rx part of the NIC.
3977  *  Return value:
3978  *  0 on success and an appropriate (-)ve integer as defined in errno.h
3979  *   file on failure.
3980  */
3981
3982 static int s2io_open(struct net_device *dev)
3983 {
3984         struct s2io_nic *sp = dev->priv;
3985         int err = 0;
3986
3987         /*
3988          * Make sure you have link off by default every time
3989          * Nic is initialized
3990          */
3991         netif_carrier_off(dev);
3992         sp->last_link_state = 0;
3993
3994         if (sp->config.intr_type == MSI_X) {
3995                 int ret = s2io_enable_msi_x(sp);
3996
3997                 if (!ret) {
3998                         ret = s2io_test_msi(sp);
3999                         /* rollback MSI-X, will re-enable during add_isr() */
4000                         remove_msix_isr(sp);
4001                 }
4002                 if (ret) {
4003
4004                         DBG_PRINT(ERR_DBG,
4005                           "%s: MSI-X requested but failed to enable\n",
4006                           dev->name);
4007                         sp->config.intr_type = INTA;
4008                 }
4009         }
4010
4011         /* NAPI doesn't work well with MSI(X) */
4012          if (sp->config.intr_type != INTA) {
4013                 if(sp->config.napi)
4014                         sp->config.napi = 0;
4015         }
4016
4017         /* Initialize H/W and enable interrupts */
4018         err = s2io_card_up(sp);
4019         if (err) {
4020                 DBG_PRINT(ERR_DBG, "%s: H/W initialization failed\n",
4021                           dev->name);
4022                 goto hw_init_failed;
4023         }
4024
4025         if (do_s2io_prog_unicast(dev, dev->dev_addr) == FAILURE) {
4026                 DBG_PRINT(ERR_DBG, "Set Mac Address Failed\n");
4027                 s2io_card_down(sp);
4028                 err = -ENODEV;
4029                 goto hw_init_failed;
4030         }
4031         s2io_start_all_tx_queue(sp);
4032         return 0;
4033
4034 hw_init_failed:
4035         if (sp->config.intr_type == MSI_X) {
4036                 if (sp->entries) {
4037                         kfree(sp->entries);
4038                         sp->mac_control.stats_info->sw_stat.mem_freed
4039                         += (MAX_REQUESTED_MSI_X * sizeof(struct msix_entry));
4040                 }
4041                 if (sp->s2io_entries) {
4042                         kfree(sp->s2io_entries);
4043                         sp->mac_control.stats_info->sw_stat.mem_freed
4044                         += (MAX_REQUESTED_MSI_X * sizeof(struct s2io_msix_entry));
4045                 }
4046         }
4047         return err;
4048 }
4049
4050 /**
4051  *  s2io_close -close entry point of the driver
4052  *  @dev : device pointer.
4053  *  Description:
4054  *  This is the stop entry point of the driver. It needs to undo exactly
4055  *  whatever was done by the open entry point,thus it's usually referred to
4056  *  as the close function.Among other things this function mainly stops the
4057  *  Rx side of the NIC and frees all the Rx buffers in the Rx rings.
4058  *  Return value:
4059  *  0 on success and an appropriate (-)ve integer as defined in errno.h
4060  *  file on failure.
4061  */
4062
4063 static int s2io_close(struct net_device *dev)
4064 {
4065         struct s2io_nic *sp = dev->priv;
4066         struct config_param *config = &sp->config;
4067         u64 tmp64;
4068         int offset;
4069
4070         /* Return if the device is already closed               *
4071         *  Can happen when s2io_card_up failed in change_mtu    *
4072         */
4073         if (!is_s2io_card_up(sp))
4074                 return 0;
4075
4076         s2io_stop_all_tx_queue(sp);
4077         /* delete all populated mac entries */
4078         for (offset = 1; offset < config->max_mc_addr; offset++) {
4079                 tmp64 = do_s2io_read_unicast_mc(sp, offset);
4080                 if (tmp64 != S2IO_DISABLE_MAC_ENTRY)
4081                         do_s2io_delete_unicast_mc(sp, tmp64);
4082         }
4083
4084         s2io_card_down(sp);
4085
4086         return 0;
4087 }
4088
4089 /**
4090  *  s2io_xmit - Tx entry point of te driver
4091  *  @skb : the socket buffer containing the Tx data.
4092  *  @dev : device pointer.
4093  *  Description :
4094  *  This function is the Tx entry point of the driver. S2IO NIC supports
4095  *  certain protocol assist features on Tx side, namely  CSO, S/G, LSO.
4096  *  NOTE: when device cant queue the pkt,just the trans_start variable will
4097  *  not be upadted.
4098  *  Return value:
4099  *  0 on success & 1 on failure.
4100  */
4101
4102 static int s2io_xmit(struct sk_buff *skb, struct net_device *dev)
4103 {
4104         struct s2io_nic *sp = dev->priv;
4105         u16 frg_cnt, frg_len, i, queue, queue_len, put_off, get_off;
4106         register u64 val64;
4107         struct TxD *txdp;
4108         struct TxFIFO_element __iomem *tx_fifo;
4109         unsigned long flags = 0;
4110         u16 vlan_tag = 0;
4111         struct fifo_info *fifo = NULL;
4112         struct mac_info *mac_control;
4113         struct config_param *config;
4114         int do_spin_lock = 1;
4115         int offload_type;
4116         int enable_per_list_interrupt = 0;
4117         struct swStat *stats = &sp->mac_control.stats_info->sw_stat;
4118
4119         mac_control = &sp->mac_control;
4120         config = &sp->config;
4121
4122         DBG_PRINT(TX_DBG, "%s: In Neterion Tx routine\n", dev->name);
4123
4124         if (unlikely(skb->len <= 0)) {
4125                 DBG_PRINT(TX_DBG, "%s:Buffer has no data..\n", dev->name);
4126                 dev_kfree_skb_any(skb);
4127                 return 0;
4128         }
4129
4130         if (!is_s2io_card_up(sp)) {
4131                 DBG_PRINT(TX_DBG, "%s: Card going down for reset\n",
4132                           dev->name);
4133                 dev_kfree_skb(skb);
4134                 return 0;
4135         }
4136
4137         queue = 0;
4138         if (sp->vlgrp && vlan_tx_tag_present(skb))
4139                 vlan_tag = vlan_tx_tag_get(skb);
4140         if (sp->config.tx_steering_type == TX_DEFAULT_STEERING) {
4141                 if (skb->protocol == htons(ETH_P_IP)) {
4142                         struct iphdr *ip;
4143                         struct tcphdr *th;
4144                         ip = ip_hdr(skb);
4145
4146                         if ((ip->frag_off & htons(IP_OFFSET|IP_MF)) == 0) {
4147                                 th = (struct tcphdr *)(((unsigned char *)ip) +
4148                                                 ip->ihl*4);
4149
4150                                 if (ip->protocol == IPPROTO_TCP) {
4151                                         queue_len = sp->total_tcp_fifos;
4152                                         queue = (ntohs(th->source) +
4153                                                         ntohs(th->dest)) &
4154                                             sp->fifo_selector[queue_len - 1];
4155                                         if (queue >= queue_len)
4156                                                 queue = queue_len - 1;
4157                                 } else if (ip->protocol == IPPROTO_UDP) {
4158                                         queue_len = sp->total_udp_fifos;
4159                                         queue = (ntohs(th->source) +
4160                                                         ntohs(th->dest)) &
4161                                             sp->fifo_selector[queue_len - 1];
4162                                         if (queue >= queue_len)
4163                                                 queue = queue_len - 1;
4164                                         queue += sp->udp_fifo_idx;
4165                                         if (skb->len > 1024)
4166                                                 enable_per_list_interrupt = 1;
4167                                         do_spin_lock = 0;
4168                                 }
4169                         }
4170                 }
4171         } else if (sp->config.tx_steering_type == TX_PRIORITY_STEERING)
4172                 /* get fifo number based on skb->priority value */
4173                 queue = config->fifo_mapping
4174                                         [skb->priority & (MAX_TX_FIFOS - 1)];
4175         fifo = &mac_control->fifos[queue];
4176
4177         if (do_spin_lock)
4178                 spin_lock_irqsave(&fifo->tx_lock, flags);
4179         else {
4180                 if (unlikely(!spin_trylock_irqsave(&fifo->tx_lock, flags)))
4181                         return NETDEV_TX_LOCKED;
4182         }
4183
4184 #ifdef CONFIG_NETDEVICES_MULTIQUEUE
4185         if (sp->config.multiq) {
4186                 if (__netif_subqueue_stopped(dev, fifo->fifo_no)) {
4187                         spin_unlock_irqrestore(&fifo->tx_lock, flags);
4188                         return NETDEV_TX_BUSY;
4189                 }
4190         } else
4191 #endif
4192         if (unlikely(fifo->queue_state == FIFO_QUEUE_STOP)) {
4193                 if (netif_queue_stopped(dev)) {
4194                         spin_unlock_irqrestore(&fifo->tx_lock, flags);
4195                         return NETDEV_TX_BUSY;
4196                 }
4197         }
4198
4199         put_off = (u16) fifo->tx_curr_put_info.offset;
4200         get_off = (u16) fifo->tx_curr_get_info.offset;
4201         txdp = (struct TxD *) fifo->list_info[put_off].list_virt_addr;
4202
4203         queue_len = fifo->tx_curr_put_info.fifo_len + 1;
4204         /* Avoid "put" pointer going beyond "get" pointer */
4205         if (txdp->Host_Control ||
4206                    ((put_off+1) == queue_len ? 0 : (put_off+1)) == get_off) {
4207                 DBG_PRINT(TX_DBG, "Error in xmit, No free TXDs.\n");
4208                 s2io_stop_tx_queue(sp, fifo->fifo_no);
4209                 dev_kfree_skb(skb);
4210                 spin_unlock_irqrestore(&fifo->tx_lock, flags);
4211                 return 0;
4212         }
4213
4214         offload_type = s2io_offload_type(skb);
4215         if (offload_type & (SKB_GSO_TCPV4 | SKB_GSO_TCPV6)) {
4216                 txdp->Control_1 |= TXD_TCP_LSO_EN;
4217                 txdp->Control_1 |= TXD_TCP_LSO_MSS(s2io_tcp_mss(skb));
4218         }
4219         if (skb->ip_summed == CHECKSUM_PARTIAL) {
4220                 txdp->Control_2 |=
4221                     (TXD_TX_CKO_IPV4_EN | TXD_TX_CKO_TCP_EN |
4222                      TXD_TX_CKO_UDP_EN);
4223         }
4224         txdp->Control_1 |= TXD_GATHER_CODE_FIRST;
4225         txdp->Control_1 |= TXD_LIST_OWN_XENA;
4226         txdp->Control_2 |= TXD_INT_NUMBER(fifo->fifo_no);
4227         if (enable_per_list_interrupt)
4228                 if (put_off & (queue_len >> 5))
4229                         txdp->Control_2 |= TXD_INT_TYPE_PER_LIST;
4230         if (vlan_tag) {
4231                 txdp->Control_2 |= TXD_VLAN_ENABLE;
4232                 txdp->Control_2 |= TXD_VLAN_TAG(vlan_tag);
4233         }
4234
4235         frg_len = skb->len - skb->data_len;
4236         if (offload_type == SKB_GSO_UDP) {
4237                 int ufo_size;
4238
4239                 ufo_size = s2io_udp_mss(skb);
4240                 ufo_size &= ~7;
4241                 txdp->Control_1 |= TXD_UFO_EN;
4242                 txdp->Control_1 |= TXD_UFO_MSS(ufo_size);
4243                 txdp->Control_1 |= TXD_BUFFER0_SIZE(8);
4244 #ifdef __BIG_ENDIAN
4245                 /* both variants do cpu_to_be64(be32_to_cpu(...)) */
4246                 fifo->ufo_in_band_v[put_off] =
4247                                 (__force u64)skb_shinfo(skb)->ip6_frag_id;
4248 #else
4249                 fifo->ufo_in_band_v[put_off] =
4250                                 (__force u64)skb_shinfo(skb)->ip6_frag_id << 32;
4251 #endif
4252                 txdp->Host_Control = (unsigned long)fifo->ufo_in_band_v;
4253                 txdp->Buffer_Pointer = pci_map_single(sp->pdev,
4254                                         fifo->ufo_in_band_v,
4255                                         sizeof(u64), PCI_DMA_TODEVICE);
4256                 if((txdp->Buffer_Pointer == 0) ||
4257                         (txdp->Buffer_Pointer == DMA_ERROR_CODE))
4258                         goto pci_map_failed;
4259                 txdp++;
4260         }
4261
4262         txdp->Buffer_Pointer = pci_map_single
4263             (sp->pdev, skb->data, frg_len, PCI_DMA_TODEVICE);
4264         if((txdp->Buffer_Pointer == 0) ||
4265                 (txdp->Buffer_Pointer == DMA_ERROR_CODE))
4266                 goto pci_map_failed;
4267
4268         txdp->Host_Control = (unsigned long) skb;
4269         txdp->Control_1 |= TXD_BUFFER0_SIZE(frg_len);
4270         if (offload_type == SKB_GSO_UDP)
4271                 txdp->Control_1 |= TXD_UFO_EN;
4272
4273         frg_cnt = skb_shinfo(skb)->nr_frags;
4274         /* For fragmented SKB. */
4275         for (i = 0; i < frg_cnt; i++) {
4276                 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
4277                 /* A '0' length fragment will be ignored */
4278                 if (!frag->size)
4279                         continue;
4280                 txdp++;
4281                 txdp->Buffer_Pointer = (u64) pci_map_page
4282                     (sp->pdev, frag->page, frag->page_offset,
4283                      frag->size, PCI_DMA_TODEVICE);
4284                 txdp->Control_1 = TXD_BUFFER0_SIZE(frag->size);
4285                 if (offload_type == SKB_GSO_UDP)
4286                         txdp->Control_1 |= TXD_UFO_EN;
4287         }
4288         txdp->Control_1 |= TXD_GATHER_CODE_LAST;
4289
4290         if (offload_type == SKB_GSO_UDP)
4291                 frg_cnt++; /* as Txd0 was used for inband header */
4292
4293         tx_fifo = mac_control->tx_FIFO_start[queue];
4294         val64 = fifo->list_info[put_off].list_phy_addr;
4295         writeq(val64, &tx_fifo->TxDL_Pointer);
4296
4297         val64 = (TX_FIFO_LAST_TXD_NUM(frg_cnt) | TX_FIFO_FIRST_LIST |
4298                  TX_FIFO_LAST_LIST);
4299         if (offload_type)
4300                 val64 |= TX_FIFO_SPECIAL_FUNC;
4301
4302         writeq(val64, &tx_fifo->List_Control);
4303
4304         mmiowb();
4305
4306         put_off++;
4307         if (put_off == fifo->tx_curr_put_info.fifo_len + 1)
4308                 put_off = 0;
4309         fifo->tx_curr_put_info.offset = put_off;
4310
4311         /* Avoid "put" pointer going beyond "get" pointer */
4312         if (((put_off+1) == queue_len ? 0 : (put_off+1)) == get_off) {
4313                 sp->mac_control.stats_info->sw_stat.fifo_full_cnt++;
4314                 DBG_PRINT(TX_DBG,
4315                           "No free TxDs for xmit, Put: 0x%x Get:0x%x\n",
4316                           put_off, get_off);
4317                 s2io_stop_tx_queue(sp, fifo->fifo_no);
4318         }
4319         mac_control->stats_info->sw_stat.mem_allocated += skb->truesize;
4320         dev->trans_start = jiffies;
4321         spin_unlock_irqrestore(&fifo->tx_lock, flags);
4322
4323         if (sp->config.intr_type == MSI_X)
4324                 tx_intr_handler(fifo);
4325
4326         return 0;
4327 pci_map_failed:
4328         stats->pci_map_fail_cnt++;
4329         s2io_stop_tx_queue(sp, fifo->fifo_no);
4330         stats->mem_freed += skb->truesize;
4331         dev_kfree_skb(skb);
4332         spin_unlock_irqrestore(&fifo->tx_lock, flags);
4333         return 0;
4334 }
4335
4336 static void
4337 s2io_alarm_handle(unsigned long data)
4338 {
4339         struct s2io_nic *sp = (struct s2io_nic *)data;
4340         struct net_device *dev = sp->dev;
4341
4342         s2io_handle_errors(dev);
4343         mod_timer(&sp->alarm_timer, jiffies + HZ / 2);
4344 }
4345
4346 static int s2io_chk_rx_buffers(struct ring_info *ring)
4347 {
4348         if (fill_rx_buffers(ring) == -ENOMEM) {
4349                 DBG_PRINT(INFO_DBG, "%s:Out of memory", ring->dev->name);
4350                 DBG_PRINT(INFO_DBG, " in Rx Intr!!\n");
4351         }
4352         return 0;
4353 }
4354
4355 static irqreturn_t s2io_msix_ring_handle(int irq, void *dev_id)
4356 {
4357         struct ring_info *ring = (struct ring_info *)dev_id;
4358         struct s2io_nic *sp = ring->nic;
4359
4360         if (!is_s2io_card_up(sp))
4361                 return IRQ_HANDLED;
4362
4363         rx_intr_handler(ring);
4364         s2io_chk_rx_buffers(ring);
4365
4366         return IRQ_HANDLED;
4367 }
4368
4369 static irqreturn_t s2io_msix_fifo_handle(int irq, void *dev_id)
4370 {
4371         int i;
4372         struct fifo_info *fifos = (struct fifo_info *)dev_id;
4373         struct s2io_nic *sp = fifos->nic;
4374         struct XENA_dev_config __iomem *bar0 = sp->bar0;
4375         struct config_param *config  = &sp->config;
4376         u64 reason;
4377
4378         if (unlikely(!is_s2io_card_up(sp)))
4379                 return IRQ_NONE;
4380
4381         reason = readq(&bar0->general_int_status);
4382         if (unlikely(reason == S2IO_MINUS_ONE))
4383                 /* Nothing much can be done. Get out */
4384                 return IRQ_HANDLED;
4385
4386         writeq(S2IO_MINUS_ONE, &bar0->general_int_mask);
4387
4388         if (reason & GEN_INTR_TXTRAFFIC)
4389                 writeq(S2IO_MINUS_ONE, &bar0->tx_traffic_int);
4390
4391         for (i = 0; i < config->tx_fifo_num; i++)
4392                 tx_intr_handler(&fifos[i]);
4393
4394         writeq(sp->general_int_mask, &bar0->general_int_mask);
4395         readl(&bar0->general_int_status);
4396
4397         return IRQ_HANDLED;
4398 }
4399
4400 static void s2io_txpic_intr_handle(struct s2io_nic *sp)
4401 {
4402         struct XENA_dev_config __iomem *bar0 = sp->bar0;
4403         u64 val64;
4404
4405         val64 = readq(&bar0->pic_int_status);
4406         if (val64 & PIC_INT_GPIO) {
4407                 val64 = readq(&bar0->gpio_int_reg);
4408                 if ((val64 & GPIO_INT_REG_LINK_DOWN) &&
4409                     (val64 & GPIO_INT_REG_LINK_UP)) {
4410                         /*
4411                          * This is unstable state so clear both up/down
4412                          * interrupt and adapter to re-evaluate the link state.
4413                          */
4414                         val64 |=  GPIO_INT_REG_LINK_DOWN;
4415                         val64 |= GPIO_INT_REG_LINK_UP;
4416                         writeq(val64, &bar0->gpio_int_reg);
4417                         val64 = readq(&bar0->gpio_int_mask);
4418                         val64 &= ~(GPIO_INT_MASK_LINK_UP |
4419                                    GPIO_INT_MASK_LINK_DOWN);
4420                         writeq(val64, &bar0->gpio_int_mask);
4421                 }
4422                 else if (val64 & GPIO_INT_REG_LINK_UP) {
4423                         val64 = readq(&bar0->adapter_status);
4424                                 /* Enable Adapter */
4425                         val64 = readq(&bar0->adapter_control);
4426                         val64 |= ADAPTER_CNTL_EN;
4427                         writeq(val64, &bar0->adapter_control);
4428                         val64 |= ADAPTER_LED_ON;
4429                         writeq(val64, &bar0->adapter_control);
4430                         if (!sp->device_enabled_once)
4431                                 sp->device_enabled_once = 1;
4432
4433                         s2io_link(sp, LINK_UP);
4434                         /*
4435                          * unmask link down interrupt and mask link-up
4436                          * intr
4437                          */
4438                         val64 = readq(&bar0->gpio_int_mask);
4439                         val64 &= ~GPIO_INT_MASK_LINK_DOWN;
4440                         val64 |= GPIO_INT_MASK_LINK_UP;
4441                         writeq(val64, &bar0->gpio_int_mask);
4442
4443                 }else if (val64 & GPIO_INT_REG_LINK_DOWN) {
4444                         val64 = readq(&bar0->adapter_status);
4445                         s2io_link(sp, LINK_DOWN);
4446                         /* Link is down so unmaks link up interrupt */
4447                         val64 = readq(&bar0->gpio_int_mask);
4448                         val64 &= ~GPIO_INT_MASK_LINK_UP;
4449                         val64 |= GPIO_INT_MASK_LINK_DOWN;
4450                         writeq(val64, &bar0->gpio_int_mask);
4451
4452                         /* turn off LED */
4453                         val64 = readq(&bar0->adapter_control);
4454                         val64 = val64 &(~ADAPTER_LED_ON);
4455                         writeq(val64, &bar0->adapter_control);
4456                 }
4457         }
4458         val64 = readq(&bar0->gpio_int_mask);
4459 }
4460
4461 /**
4462  *  do_s2io_chk_alarm_bit - Check for alarm and incrment the counter
4463  *  @value: alarm bits
4464  *  @addr: address value
4465  *  @cnt: counter variable
4466  *  Description: Check for alarm and increment the counter
4467  *  Return Value:
4468  *  1 - if alarm bit set
4469  *  0 - if alarm bit is not set
4470  */
4471 static int do_s2io_chk_alarm_bit(u64 value, void __iomem * addr,
4472                           unsigned long long *cnt)
4473 {
4474         u64 val64;
4475         val64 = readq(addr);
4476         if ( val64 & value ) {
4477                 writeq(val64, addr);
4478                 (*cnt)++;
4479                 return 1;
4480         }
4481         return 0;
4482
4483 }
4484
4485 /**
4486  *  s2io_handle_errors - Xframe error indication handler
4487  *  @nic: device private variable
4488  *  Description: Handle alarms such as loss of link, single or
4489  *  double ECC errors, critical and serious errors.
4490  *  Return Value:
4491  *  NONE
4492  */
4493 static void s2io_handle_errors(void * dev_id)
4494 {
4495         struct net_device *dev = (struct net_device *) dev_id;
4496         struct s2io_nic *sp = dev->priv;
4497         struct XENA_dev_config __iomem *bar0 = sp->bar0;
4498         u64 temp64 = 0,val64=0;
4499         int i = 0;
4500
4501         struct swStat *sw_stat = &sp->mac_control.stats_info->sw_stat;
4502         struct xpakStat *stats = &sp->mac_control.stats_info->xpak_stat;
4503
4504         if (!is_s2io_card_up(sp))
4505                 return;
4506
4507         if (pci_channel_offline(sp->pdev))
4508                 return;
4509
4510         memset(&sw_stat->ring_full_cnt, 0,
4511                 sizeof(sw_stat->ring_full_cnt));
4512
4513         /* Handling the XPAK counters update */
4514         if(stats->xpak_timer_count < 72000) {
4515                 /* waiting for an hour */
4516                 stats->xpak_timer_count++;
4517         } else {
4518                 s2io_updt_xpak_counter(dev);
4519                 /* reset the count to zero */
4520                 stats->xpak_timer_count = 0;
4521         }
4522
4523         /* Handling link status change error Intr */
4524         if (s2io_link_fault_indication(sp) == MAC_RMAC_ERR_TIMER) {
4525                 val64 = readq(&bar0->mac_rmac_err_reg);
4526                 writeq(val64, &bar0->mac_rmac_err_reg);
4527                 if (val64 & RMAC_LINK_STATE_CHANGE_INT)
4528                         schedule_work(&sp->set_link_task);
4529         }
4530
4531         /* In case of a serious error, the device will be Reset. */
4532         if (do_s2io_chk_alarm_bit(SERR_SOURCE_ANY, &bar0->serr_source,
4533                                 &sw_stat->serious_err_cnt))
4534                 goto reset;
4535
4536         /* Check for data parity error */
4537         if (do_s2io_chk_alarm_bit(GPIO_INT_REG_DP_ERR_INT, &bar0->gpio_int_reg,
4538                                 &sw_stat->parity_err_cnt))
4539                 goto reset;
4540
4541         /* Check for ring full counter */
4542         if (sp->device_type == XFRAME_II_DEVICE) {
4543                 val64 = readq(&bar0->ring_bump_counter1);
4544                 for (i=0; i<4; i++) {
4545                         temp64 = ( val64 & vBIT(0xFFFF,(i*16),16));
4546                         temp64 >>= 64 - ((i+1)*16);
4547                         sw_stat->ring_full_cnt[i] += temp64;
4548                 }
4549
4550                 val64 = readq(&bar0->ring_bump_counter2);
4551                 for (i=0; i<4; i++) {
4552                         temp64 = ( val64 & vBIT(0xFFFF,(i*16),16));
4553                         temp64 >>= 64 - ((i+1)*16);
4554                          sw_stat->ring_full_cnt[i+4] += temp64;
4555                 }
4556         }
4557
4558         val64 = readq(&bar0->txdma_int_status);
4559         /*check for pfc_err*/
4560         if (val64 & TXDMA_PFC_INT) {
4561                 if (do_s2io_chk_alarm_bit(PFC_ECC_DB_ERR | PFC_SM_ERR_ALARM|
4562                                 PFC_MISC_0_ERR | PFC_MISC_1_ERR|
4563                                 PFC_PCIX_ERR, &bar0->pfc_err_reg,
4564                                 &sw_stat->pfc_err_cnt))
4565                         goto reset;
4566                 do_s2io_chk_alarm_bit(PFC_ECC_SG_ERR, &bar0->pfc_err_reg,
4567                                 &sw_stat->pfc_err_cnt);
4568         }
4569
4570         /*check for tda_err*/
4571         if (val64 & TXDMA_TDA_INT) {
4572                 if(do_s2io_chk_alarm_bit(TDA_Fn_ECC_DB_ERR | TDA_SM0_ERR_ALARM |
4573                                 TDA_SM1_ERR_ALARM, &bar0->tda_err_reg,
4574                                 &sw_stat->tda_err_cnt))
4575                         goto reset;
4576                 do_s2io_chk_alarm_bit(TDA_Fn_ECC_SG_ERR | TDA_PCIX_ERR,
4577                                 &bar0->tda_err_reg, &sw_stat->tda_err_cnt);
4578         }
4579         /*check for pcc_err*/
4580         if (val64 & TXDMA_PCC_INT) {
4581                 if (do_s2io_chk_alarm_bit(PCC_SM_ERR_ALARM | PCC_WR_ERR_ALARM
4582                                 | PCC_N_SERR | PCC_6_COF_OV_ERR
4583                                 | PCC_7_COF_OV_ERR | PCC_6_LSO_OV_ERR
4584                                 | PCC_7_LSO_OV_ERR | PCC_FB_ECC_DB_ERR
4585                                 | PCC_TXB_ECC_DB_ERR, &bar0->pcc_err_reg,
4586                                 &sw_stat->pcc_err_cnt))
4587                         goto reset;
4588                 do_s2io_chk_alarm_bit(PCC_FB_ECC_SG_ERR | PCC_TXB_ECC_SG_ERR,
4589                                 &bar0->pcc_err_reg, &sw_stat->pcc_err_cnt);
4590         }
4591
4592         /*check for tti_err*/
4593         if (val64 & TXDMA_TTI_INT) {
4594                 if (do_s2io_chk_alarm_bit(TTI_SM_ERR_ALARM, &bar0->tti_err_reg,
4595                                 &sw_stat->tti_err_cnt))
4596                         goto reset;
4597                 do_s2io_chk_alarm_bit(TTI_ECC_SG_ERR | TTI_ECC_DB_ERR,
4598                                 &bar0->tti_err_reg, &sw_stat->tti_err_cnt);
4599         }
4600
4601         /*check for lso_err*/
4602         if (val64 & TXDMA_LSO_INT) {
4603                 if (do_s2io_chk_alarm_bit(LSO6_ABORT | LSO7_ABORT
4604                                 | LSO6_SM_ERR_ALARM | LSO7_SM_ERR_ALARM,
4605                                 &bar0->lso_err_reg, &sw_stat->lso_err_cnt))
4606                         goto reset;
4607                 do_s2io_chk_alarm_bit(LSO6_SEND_OFLOW | LSO7_SEND_OFLOW,
4608                                 &bar0->lso_err_reg, &sw_stat->lso_err_cnt);
4609         }
4610
4611         /*check for tpa_err*/
4612         if (val64 & TXDMA_TPA_INT) {
4613                 if (do_s2io_chk_alarm_bit(TPA_SM_ERR_ALARM, &bar0->tpa_err_reg,
4614                         &sw_stat->tpa_err_cnt))
4615                         goto reset;
4616                 do_s2io_chk_alarm_bit(TPA_TX_FRM_DROP, &bar0->tpa_err_reg,
4617                         &sw_stat->tpa_err_cnt);
4618         }
4619
4620         /*check for sm_err*/
4621         if (val64 & TXDMA_SM_INT) {
4622                 if (do_s2io_chk_alarm_bit(SM_SM_ERR_ALARM, &bar0->sm_err_reg,
4623                         &sw_stat->sm_err_cnt))
4624                         goto reset;
4625         }
4626
4627         val64 = readq(&bar0->mac_int_status);
4628         if (val64 & MAC_INT_STATUS_TMAC_INT) {
4629                 if (do_s2io_chk_alarm_bit(TMAC_TX_BUF_OVRN | TMAC_TX_SM_ERR,
4630                                 &bar0->mac_tmac_err_reg,
4631                                 &sw_stat->mac_tmac_err_cnt))
4632                         goto reset;
4633                 do_s2io_chk_alarm_bit(TMAC_ECC_SG_ERR | TMAC_ECC_DB_ERR
4634                                 | TMAC_DESC_ECC_SG_ERR | TMAC_DESC_ECC_DB_ERR,
4635                                 &bar0->mac_tmac_err_reg,
4636                                 &sw_stat->mac_tmac_err_cnt);
4637         }
4638
4639         val64 = readq(&bar0->xgxs_int_status);
4640         if (val64 & XGXS_INT_STATUS_TXGXS) {
4641                 if (do_s2io_chk_alarm_bit(TXGXS_ESTORE_UFLOW | TXGXS_TX_SM_ERR,
4642                                 &bar0->xgxs_txgxs_err_reg,
4643                                 &sw_stat->xgxs_txgxs_err_cnt))
4644                         goto reset;
4645                 do_s2io_chk_alarm_bit(TXGXS_ECC_SG_ERR | TXGXS_ECC_DB_ERR,
4646                                 &bar0->xgxs_txgxs_err_reg,
4647                                 &sw_stat->xgxs_txgxs_err_cnt);
4648         }
4649
4650         val64 = readq(&bar0->rxdma_int_status);
4651         if (val64 & RXDMA_INT_RC_INT_M) {
4652                 if (do_s2io_chk_alarm_bit(RC_PRCn_ECC_DB_ERR | RC_FTC_ECC_DB_ERR
4653                                 | RC_PRCn_SM_ERR_ALARM |RC_FTC_SM_ERR_ALARM,
4654                                 &bar0->rc_err_reg, &sw_stat->rc_err_cnt))
4655                         goto reset;
4656                 do_s2io_chk_alarm_bit(RC_PRCn_ECC_SG_ERR | RC_FTC_ECC_SG_ERR
4657                                 | RC_RDA_FAIL_WR_Rn, &bar0->rc_err_reg,
4658                                 &sw_stat->rc_err_cnt);
4659                 if (do_s2io_chk_alarm_bit(PRC_PCI_AB_RD_Rn | PRC_PCI_AB_WR_Rn
4660                                 | PRC_PCI_AB_F_WR_Rn, &bar0->prc_pcix_err_reg,
4661                                 &sw_stat->prc_pcix_err_cnt))
4662                         goto reset;
4663                 do_s2io_chk_alarm_bit(PRC_PCI_DP_RD_Rn | PRC_PCI_DP_WR_Rn
4664                                 | PRC_PCI_DP_F_WR_Rn, &bar0->prc_pcix_err_reg,
4665                                 &sw_stat->prc_pcix_err_cnt);
4666         }
4667
4668         if (val64 & RXDMA_INT_RPA_INT_M) {
4669                 if (do_s2io_chk_alarm_bit(RPA_SM_ERR_ALARM | RPA_CREDIT_ERR,
4670                                 &bar0->rpa_err_reg, &sw_stat->rpa_err_cnt))
4671                         goto reset;
4672                 do_s2io_chk_alarm_bit(RPA_ECC_SG_ERR | RPA_ECC_DB_ERR,
4673                                 &bar0->rpa_err_reg, &sw_stat->rpa_err_cnt);
4674         }
4675
4676         if (val64 & RXDMA_INT_RDA_INT_M) {
4677                 if (do_s2io_chk_alarm_bit(RDA_RXDn_ECC_DB_ERR
4678                                 | RDA_FRM_ECC_DB_N_AERR | RDA_SM1_ERR_ALARM
4679                                 | RDA_SM0_ERR_ALARM | RDA_RXD_ECC_DB_SERR,
4680                                 &bar0->rda_err_reg, &sw_stat->rda_err_cnt))
4681                         goto reset;
4682                 do_s2io_chk_alarm_bit(RDA_RXDn_ECC_SG_ERR | RDA_FRM_ECC_SG_ERR
4683                                 | RDA_MISC_ERR | RDA_PCIX_ERR,
4684                                 &bar0->rda_err_reg, &sw_stat->rda_err_cnt);
4685         }
4686
4687         if (val64 & RXDMA_INT_RTI_INT_M) {
4688                 if (do_s2io_chk_alarm_bit(RTI_SM_ERR_ALARM, &bar0->rti_err_reg,
4689                                 &sw_stat->rti_err_cnt))
4690                         goto reset;
4691                 do_s2io_chk_alarm_bit(RTI_ECC_SG_ERR | RTI_ECC_DB_ERR,
4692                                 &bar0->rti_err_reg, &sw_stat->rti_err_cnt);
4693         }
4694
4695         val64 = readq(&bar0->mac_int_status);
4696         if (val64 & MAC_INT_STATUS_RMAC_INT) {
4697                 if (do_s2io_chk_alarm_bit(RMAC_RX_BUFF_OVRN | RMAC_RX_SM_ERR,
4698                                 &bar0->mac_rmac_err_reg,
4699                                 &sw_stat->mac_rmac_err_cnt))
4700                         goto reset;
4701                 do_s2io_chk_alarm_bit(RMAC_UNUSED_INT|RMAC_SINGLE_ECC_ERR|
4702                                 RMAC_DOUBLE_ECC_ERR, &bar0->mac_rmac_err_reg,
4703                                 &sw_stat->mac_rmac_err_cnt);
4704         }
4705
4706         val64 = readq(&bar0->xgxs_int_status);
4707         if (val64 & XGXS_INT_STATUS_RXGXS) {
4708                 if (do_s2io_chk_alarm_bit(RXGXS_ESTORE_OFLOW | RXGXS_RX_SM_ERR,
4709                                 &bar0->xgxs_rxgxs_err_reg,
4710                                 &sw_stat->xgxs_rxgxs_err_cnt))
4711                         goto reset;
4712         }
4713
4714         val64 = readq(&bar0->mc_int_status);
4715         if(val64 & MC_INT_STATUS_MC_INT) {
4716                 if (do_s2io_chk_alarm_bit(MC_ERR_REG_SM_ERR, &bar0->mc_err_reg,
4717                                 &sw_stat->mc_err_cnt))
4718                         goto reset;
4719
4720                 /* Handling Ecc errors */
4721                 if (val64 & (MC_ERR_REG_ECC_ALL_SNG | MC_ERR_REG_ECC_ALL_DBL)) {
4722                         writeq(val64, &bar0->mc_err_reg);
4723                         if (val64 & MC_ERR_REG_ECC_ALL_DBL) {
4724                                 sw_stat->double_ecc_errs++;
4725                                 if (sp->device_type != XFRAME_II_DEVICE) {
4726                                         /*
4727                                          * Reset XframeI only if critical error
4728                                          */
4729                                         if (val64 &
4730                                                 (MC_ERR_REG_MIRI_ECC_DB_ERR_0 |
4731                                                 MC_ERR_REG_MIRI_ECC_DB_ERR_1))
4732                                                                 goto reset;
4733                                         }
4734                         } else
4735                                 sw_stat->single_ecc_errs++;
4736                 }
4737         }
4738         return;
4739
4740 reset:
4741         s2io_stop_all_tx_queue(sp);
4742         schedule_work(&sp->rst_timer_task);
4743         sw_stat->soft_reset_cnt++;
4744         return;
4745 }
4746
4747 /**
4748  *  s2io_isr - ISR handler of the device .
4749  *  @irq: the irq of the device.
4750  *  @dev_id: a void pointer to the dev structure of the NIC.
4751  *  Description:  This function is the ISR handler of the device. It
4752  *  identifies the reason for the interrupt and calls the relevant
4753  *  service routines. As a contongency measure, this ISR allocates the
4754  *  recv buffers, if their numbers are below the panic value which is
4755  *  presently set to 25% of the original number of rcv buffers allocated.
4756  *  Return value:
4757  *   IRQ_HANDLED: will be returned if IRQ was handled by this routine
4758  *   IRQ_NONE: will be returned if interrupt is not from our device
4759  */
4760 static irqreturn_t s2io_isr(int irq, void *dev_id)
4761 {
4762         struct net_device *dev = (struct net_device *) dev_id;
4763         struct s2io_nic *sp = dev->priv;
4764         struct XENA_dev_config __iomem *bar0 = sp->bar0;
4765         int i;
4766         u64 reason = 0;
4767         struct mac_info *mac_control;
4768         struct config_param *config;
4769
4770         /* Pretend we handled any irq's from a disconnected card */
4771         if (pci_channel_offline(sp->pdev))
4772                 return IRQ_NONE;
4773
4774         if (!is_s2io_card_up(sp))
4775                 return IRQ_NONE;
4776
4777         mac_control = &sp->mac_control;
4778         config = &sp->config;
4779
4780         /*
4781          * Identify the cause for interrupt and call the appropriate
4782          * interrupt handler. Causes for the interrupt could be;
4783          * 1. Rx of packet.
4784          * 2. Tx complete.
4785          * 3. Link down.
4786          */
4787         reason = readq(&bar0->general_int_status);
4788
4789         if (unlikely(reason == S2IO_MINUS_ONE) ) {
4790                 /* Nothing much can be done. Get out */
4791                 return IRQ_HANDLED;
4792         }
4793
4794         if (reason & (GEN_INTR_RXTRAFFIC |
4795                 GEN_INTR_TXTRAFFIC | GEN_INTR_TXPIC))
4796         {
4797                 writeq(S2IO_MINUS_ONE, &bar0->general_int_mask);
4798
4799                 if (config->napi) {
4800                         if (reason & GEN_INTR_RXTRAFFIC) {
4801                                 if (likely(netif_rx_schedule_prep(dev,
4802                                                         &sp->napi))) {
4803                                         __netif_rx_schedule(dev, &sp->napi);
4804                                         writeq(S2IO_MINUS_ONE,
4805                                                &bar0->rx_traffic_mask);
4806                                 } else
4807                                         writeq(S2IO_MINUS_ONE,
4808                                                &bar0->rx_traffic_int);
4809                         }
4810                 } else {
4811                         /*
4812                          * rx_traffic_int reg is an R1 register, writing all 1's
4813                          * will ensure that the actual interrupt causing bit
4814                          * get's cleared and hence a read can be avoided.
4815                          */
4816                         if (reason & GEN_INTR_RXTRAFFIC)
4817                                 writeq(S2IO_MINUS_ONE, &bar0->rx_traffic_int);
4818
4819                         for (i = 0; i < config->rx_ring_num; i++)
4820                                 rx_intr_handler(&mac_control->rings[i]);
4821                 }
4822
4823                 /*
4824                  * tx_traffic_int reg is an R1 register, writing all 1's
4825                  * will ensure that the actual interrupt causing bit get's
4826                  * cleared and hence a read can be avoided.
4827                  */
4828                 if (reason & GEN_INTR_TXTRAFFIC)
4829                         writeq(S2IO_MINUS_ONE, &bar0->tx_traffic_int);
4830
4831                 for (i = 0; i < config->tx_fifo_num; i++)
4832                         tx_intr_handler(&mac_control->fifos[i]);
4833
4834                 if (reason & GEN_INTR_TXPIC)
4835                         s2io_txpic_intr_handle(sp);
4836
4837                 /*
4838                  * Reallocate the buffers from the interrupt handler itself.
4839                  */
4840                 if (!config->napi) {
4841                         for (i = 0; i < config->rx_ring_num; i++)
4842                                 s2io_chk_rx_buffers(&mac_control->rings[i]);
4843                 }
4844                 writeq(sp->general_int_mask, &bar0->general_int_mask);
4845                 readl(&bar0->general_int_status);
4846
4847                 return IRQ_HANDLED;
4848
4849         }
4850         else if (!reason) {
4851                 /* The interrupt was not raised by us */
4852                 return IRQ_NONE;
4853         }
4854
4855         return IRQ_HANDLED;
4856 }
4857
4858 /**
4859  * s2io_updt_stats -
4860  */
4861 static void s2io_updt_stats(struct s2io_nic *sp)
4862 {
4863         struct XENA_dev_config __iomem *bar0 = sp->bar0;
4864         u64 val64;
4865         int cnt = 0;
4866
4867         if (is_s2io_card_up(sp)) {
4868                 /* Apprx 30us on a 133 MHz bus */
4869                 val64 = SET_UPDT_CLICKS(10) |
4870                         STAT_CFG_ONE_SHOT_EN | STAT_CFG_STAT_EN;
4871                 writeq(val64, &bar0->stat_cfg);
4872                 do {
4873                         udelay(100);
4874                         val64 = readq(&bar0->stat_cfg);
4875                         if (!(val64 & s2BIT(0)))
4876                                 break;
4877                         cnt++;
4878                         if (cnt == 5)
4879                                 break; /* Updt failed */
4880                 } while(1);
4881         }
4882 }
4883
4884 /**
4885  *  s2io_get_stats - Updates the device statistics structure.
4886  *  @dev : pointer to the device structure.
4887  *  Description:
4888  *  This function updates the device statistics structure in the s2io_nic
4889  *  structure and returns a pointer to the same.
4890  *  Return value:
4891  *  pointer to the updated net_device_stats structure.
4892  */
4893
4894 static struct net_device_stats *s2io_get_stats(struct net_device *dev)
4895 {
4896         struct s2io_nic *sp = dev->priv;
4897         struct mac_info *mac_control;
4898         struct config_param *config;
4899         int i;
4900
4901
4902         mac_control = &sp->mac_control;
4903         config = &sp->config;
4904
4905         /* Configure Stats for immediate updt */
4906         s2io_updt_stats(sp);
4907
4908         sp->stats.tx_packets =
4909                 le32_to_cpu(mac_control->stats_info->tmac_frms);
4910         sp->stats.tx_errors =
4911                 le32_to_cpu(mac_control->stats_info->tmac_any_err_frms);
4912         sp->stats.rx_errors =
4913                 le64_to_cpu(mac_control->stats_info->rmac_drop_frms);
4914         sp->stats.multicast =
4915                 le32_to_cpu(mac_control->stats_info->rmac_vld_mcst_frms);
4916         sp->stats.rx_length_errors =
4917                 le64_to_cpu(mac_control->stats_info->rmac_long_frms);
4918
4919         /* collect per-ring rx_packets and rx_bytes */
4920         sp->stats.rx_packets = sp->stats.rx_bytes = 0;
4921         for (i = 0; i < config->rx_ring_num; i++) {
4922                 sp->stats.rx_packets += mac_control->rings[i].rx_packets;
4923                 sp->stats.rx_bytes += mac_control->rings[i].rx_bytes;
4924         }
4925
4926         return (&sp->stats);
4927 }
4928
4929 /**
4930  *  s2io_set_multicast - entry point for multicast address enable/disable.
4931  *  @dev : pointer to the device structure
4932  *  Description:
4933  *  This function is a driver entry point which gets called by the kernel
4934  *  whenever multicast addresses must be enabled/disabled. This also gets
4935  *  called to set/reset promiscuous mode. Depending on the deivce flag, we
4936  *  determine, if multicast address must be enabled or if promiscuous mode
4937  *  is to be disabled etc.
4938  *  Return value:
4939  *  void.
4940  */
4941
4942 static void s2io_set_multicast(struct net_device *dev)
4943 {
4944         int i, j, prev_cnt;
4945         struct dev_mc_list *mclist;
4946         struct s2io_nic *sp = dev->priv;
4947         struct XENA_dev_config __iomem *bar0 = sp->bar0;
4948         u64 val64 = 0, multi_mac = 0x010203040506ULL, mask =
4949             0xfeffffffffffULL;
4950         u64 dis_addr = S2IO_DISABLE_MAC_ENTRY, mac_addr = 0;
4951         void __iomem *add;
4952         struct config_param *config = &sp->config;
4953
4954         if ((dev->flags & IFF_ALLMULTI) && (!sp->m_cast_flg)) {
4955                 /*  Enable all Multicast addresses */
4956                 writeq(RMAC_ADDR_DATA0_MEM_ADDR(multi_mac),
4957                        &bar0->rmac_addr_data0_mem);
4958                 writeq(RMAC_ADDR_DATA1_MEM_MASK(mask),
4959                        &bar0->rmac_addr_data1_mem);
4960                 val64 = RMAC_ADDR_CMD_MEM_WE |
4961                     RMAC_ADDR_CMD_MEM_STROBE_NEW_CMD |
4962                     RMAC_ADDR_CMD_MEM_OFFSET(config->max_mc_addr - 1);
4963                 writeq(val64, &bar0->rmac_addr_cmd_mem);
4964                 /* Wait till command completes */
4965                 wait_for_cmd_complete(&bar0->rmac_addr_cmd_mem,
4966                                         RMAC_ADDR_CMD_MEM_STROBE_CMD_EXECUTING,
4967                                         S2IO_BIT_RESET);
4968
4969                 sp->m_cast_flg = 1;
4970                 sp->all_multi_pos = config->max_mc_addr - 1;
4971         } else if ((dev->flags & IFF_ALLMULTI) && (sp->m_cast_flg)) {
4972                 /*  Disable all Multicast addresses */
4973                 writeq(RMAC_ADDR_DATA0_MEM_ADDR(dis_addr),
4974                        &bar0->rmac_addr_data0_mem);
4975                 writeq(RMAC_ADDR_DATA1_MEM_MASK(0x0),
4976                        &bar0->rmac_addr_data1_mem);
4977                 val64 = RMAC_ADDR_CMD_MEM_WE |
4978                     RMAC_ADDR_CMD_MEM_STROBE_NEW_CMD |
4979                     RMAC_ADDR_CMD_MEM_OFFSET(sp->all_multi_pos);
4980                 writeq(val64, &bar0->rmac_addr_cmd_mem);
4981                 /* Wait till command completes */
4982                 wait_for_cmd_complete(&bar0->rmac_addr_cmd_mem,
4983                                         RMAC_ADDR_CMD_MEM_STROBE_CMD_EXECUTING,
4984                                         S2IO_BIT_RESET);
4985
4986                 sp->m_cast_flg = 0;
4987                 sp->all_multi_pos = 0;
4988         }
4989
4990         if ((dev->flags & IFF_PROMISC) && (!sp->promisc_flg)) {
4991                 /*  Put the NIC into promiscuous mode */
4992                 add = &bar0->mac_cfg;
4993                 val64 = readq(&bar0->mac_cfg);
4994                 val64 |= MAC_CFG_RMAC_PROM_ENABLE;
4995
4996                 writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
4997                 writel((u32) val64, add);
4998                 writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
4999                 writel((u32) (val64 >> 32), (add + 4));
5000
5001                 if (vlan_tag_strip != 1) {
5002                         val64 = readq(&bar0->rx_pa_cfg);
5003                         val64 &= ~RX_PA_CFG_STRIP_VLAN_TAG;
5004                         writeq(val64, &bar0->rx_pa_cfg);
5005                         vlan_strip_flag = 0;
5006                 }
5007
5008                 val64 = readq(&bar0->mac_cfg);
5009                 sp->promisc_flg = 1;
5010                 DBG_PRINT(INFO_DBG, "%s: entered promiscuous mode\n",
5011                           dev->name);
5012         } else if (!(dev->flags & IFF_PROMISC) && (sp->promisc_flg)) {
5013                 /*  Remove the NIC from promiscuous mode */
5014                 add = &bar0->mac_cfg;
5015                 val64 = readq(&bar0->mac_cfg);
5016                 val64 &= ~MAC_CFG_RMAC_PROM_ENABLE;
5017
5018                 writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
5019                 writel((u32) val64, add);
5020                 writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
5021                 writel((u32) (val64 >> 32), (add + 4));
5022
5023                 if (vlan_tag_strip != 0) {
5024                         val64 = readq(&bar0->rx_pa_cfg);
5025                         val64 |= RX_PA_CFG_STRIP_VLAN_TAG;
5026                         writeq(val64, &bar0->rx_pa_cfg);
5027                         vlan_strip_flag = 1;
5028                 }
5029
5030                 val64 = readq(&bar0->mac_cfg);
5031                 sp->promisc_flg = 0;
5032                 DBG_PRINT(INFO_DBG, "%s: left promiscuous mode\n",
5033                           dev->name);
5034         }
5035
5036         /*  Update individual M_CAST address list */
5037         if ((!sp->m_cast_flg) && dev->mc_count) {
5038                 if (dev->mc_count >
5039                     (config->max_mc_addr - config->max_mac_addr)) {
5040                         DBG_PRINT(ERR_DBG, "%s: No more Rx filters ",
5041                                   dev->name);
5042                         DBG_PRINT(ERR_DBG, "can be added, please enable ");
5043                         DBG_PRINT(ERR_DBG, "ALL_MULTI instead\n");
5044                         return;
5045                 }
5046
5047                 prev_cnt = sp->mc_addr_count;
5048                 sp->mc_addr_count = dev->mc_count;
5049
5050                 /* Clear out the previous list of Mc in the H/W. */
5051                 for (i = 0; i < prev_cnt; i++) {
5052                         writeq(RMAC_ADDR_DATA0_MEM_ADDR(dis_addr),
5053                                &bar0->rmac_addr_data0_mem);
5054                         writeq(RMAC_ADDR_DATA1_MEM_MASK(0ULL),
5055                                 &bar0->rmac_addr_data1_mem);
5056                         val64 = RMAC_ADDR_CMD_MEM_WE |
5057                             RMAC_ADDR_CMD_MEM_STROBE_NEW_CMD |
5058                             RMAC_ADDR_CMD_MEM_OFFSET
5059                             (config->mc_start_offset + i);
5060                         writeq(val64, &bar0->rmac_addr_cmd_mem);
5061
5062                         /* Wait for command completes */
5063                         if (wait_for_cmd_complete(&bar0->rmac_addr_cmd_mem,
5064                                         RMAC_ADDR_CMD_MEM_STROBE_CMD_EXECUTING,
5065                                         S2IO_BIT_RESET)) {
5066                                 DBG_PRINT(ERR_DBG, "%s: Adding ",
5067                                           dev->name);
5068                                 DBG_PRINT(ERR_DBG, "Multicasts failed\n");
5069                                 return;
5070                         }
5071                 }
5072
5073                 /* Create the new Rx filter list and update the same in H/W. */
5074                 for (i = 0, mclist = dev->mc_list; i < dev->mc_count;
5075                      i++, mclist = mclist->next) {
5076                         memcpy(sp->usr_addrs[i].addr, mclist->dmi_addr,
5077                                ETH_ALEN);
5078                         mac_addr = 0;
5079                         for (j = 0; j < ETH_ALEN; j++) {
5080                                 mac_addr |= mclist->dmi_addr[j];
5081                                 mac_addr <<= 8;
5082                         }
5083                         mac_addr >>= 8;
5084                         writeq(RMAC_ADDR_DATA0_MEM_ADDR(mac_addr),
5085                                &bar0->rmac_addr_data0_mem);
5086                         writeq(RMAC_ADDR_DATA1_MEM_MASK(0ULL),
5087                                 &bar0->rmac_addr_data1_mem);
5088                         val64 = RMAC_ADDR_CMD_MEM_WE |
5089                             RMAC_ADDR_CMD_MEM_STROBE_NEW_CMD |
5090                             RMAC_ADDR_CMD_MEM_OFFSET
5091                             (i + config->mc_start_offset);
5092                         writeq(val64, &bar0->rmac_addr_cmd_mem);
5093
5094                         /* Wait for command completes */
5095                         if (wait_for_cmd_complete(&bar0->rmac_addr_cmd_mem,
5096                                         RMAC_ADDR_CMD_MEM_STROBE_CMD_EXECUTING,
5097                                         S2IO_BIT_RESET)) {
5098                                 DBG_PRINT(ERR_DBG, "%s: Adding ",
5099                                           dev->name);
5100                                 DBG_PRINT(ERR_DBG, "Multicasts failed\n");
5101                                 return;
5102                         }
5103                 }
5104         }
5105 }
5106
5107 /* read from CAM unicast & multicast addresses and store it in
5108  * def_mac_addr structure
5109  */
5110 void do_s2io_store_unicast_mc(struct s2io_nic *sp)
5111 {
5112         int offset;
5113         u64 mac_addr = 0x0;
5114         struct config_param *config = &sp->config;
5115
5116         /* store unicast & multicast mac addresses */
5117         for (offset = 0; offset < config->max_mc_addr; offset++) {
5118                 mac_addr = do_s2io_read_unicast_mc(sp, offset);
5119                 /* if read fails disable the entry */
5120                 if (mac_addr == FAILURE)
5121                         mac_addr = S2IO_DISABLE_MAC_ENTRY;
5122                 do_s2io_copy_mac_addr(sp, offset, mac_addr);
5123         }
5124 }
5125
5126 /* restore unicast & multicast MAC to CAM from def_mac_addr structure */
5127 static void do_s2io_restore_unicast_mc(struct s2io_nic *sp)
5128 {
5129         int offset;
5130         struct config_param *config = &sp->config;
5131         /* restore unicast mac address */
5132         for (offset = 0; offset < config->max_mac_addr; offset++)
5133                 do_s2io_prog_unicast(sp->dev,
5134                         sp->def_mac_addr[offset].mac_addr);
5135
5136         /* restore multicast mac address */
5137         for (offset = config->mc_start_offset;
5138                 offset < config->max_mc_addr; offset++)
5139                 do_s2io_add_mc(sp, sp->def_mac_addr[offset].mac_addr);
5140 }
5141
5142 /* add a multicast MAC address to CAM */
5143 static int do_s2io_add_mc(struct s2io_nic *sp, u8 *addr)
5144 {
5145         int i;
5146         u64 mac_addr = 0;
5147         struct config_param *config = &sp->config;
5148
5149         for (i = 0; i < ETH_ALEN; i++) {
5150                 mac_addr <<= 8;
5151                 mac_addr |= addr[i];
5152         }
5153         if ((0ULL == mac_addr) || (mac_addr == S2IO_DISABLE_MAC_ENTRY))
5154                 return SUCCESS;
5155
5156         /* check if the multicast mac already preset in CAM */
5157         for (i = config->mc_start_offset; i < config->max_mc_addr; i++) {
5158                 u64 tmp64;
5159                 tmp64 = do_s2io_read_unicast_mc(sp, i);
5160                 if (tmp64 == S2IO_DISABLE_MAC_ENTRY) /* CAM entry is empty */
5161                         break;
5162
5163                 if (tmp64 == mac_addr)
5164                         return SUCCESS;
5165         }
5166         if (i == config->max_mc_addr) {
5167                 DBG_PRINT(ERR_DBG,
5168                         "CAM full no space left for multicast MAC\n");
5169                 return FAILURE;
5170         }
5171         /* Update the internal structure with this new mac address */
5172         do_s2io_copy_mac_addr(sp, i, mac_addr);
5173
5174         return (do_s2io_add_mac(sp, mac_addr, i));
5175 }
5176
5177 /* add MAC address to CAM */
5178 static int do_s2io_add_mac(struct s2io_nic *sp, u64 addr, int off)
5179 {
5180         u64 val64;
5181         struct XENA_dev_config __iomem *bar0 = sp->bar0;
5182
5183         writeq(RMAC_ADDR_DATA0_MEM_ADDR(addr),
5184                 &bar0->rmac_addr_data0_mem);
5185
5186         val64 =
5187                 RMAC_ADDR_CMD_MEM_WE | RMAC_ADDR_CMD_MEM_STROBE_NEW_CMD |
5188                 RMAC_ADDR_CMD_MEM_OFFSET(off);
5189         writeq(val64, &bar0->rmac_addr_cmd_mem);
5190
5191         /* Wait till command completes */
5192         if (wait_for_cmd_complete(&bar0->rmac_addr_cmd_mem,
5193                 RMAC_ADDR_CMD_MEM_STROBE_CMD_EXECUTING,
5194                 S2IO_BIT_RESET)) {
5195                 DBG_PRINT(INFO_DBG, "do_s2io_add_mac failed\n");
5196                 return FAILURE;
5197         }
5198         return SUCCESS;
5199 }
5200 /* deletes a specified unicast/multicast mac entry from CAM */
5201 static int do_s2io_delete_unicast_mc(struct s2io_nic *sp, u64 addr)
5202 {
5203         int offset;
5204         u64 dis_addr = S2IO_DISABLE_MAC_ENTRY, tmp64;
5205         struct config_param *config = &sp->config;
5206
5207         for (offset = 1;
5208                 offset < config->max_mc_addr; offset++) {
5209                 tmp64 = do_s2io_read_unicast_mc(sp, offset);
5210                 if (tmp64 == addr) {
5211                         /* disable the entry by writing  0xffffffffffffULL */
5212                         if (do_s2io_add_mac(sp, dis_addr, offset) ==  FAILURE)
5213                                 return FAILURE;
5214                         /* store the new mac list from CAM */
5215                         do_s2io_store_unicast_mc(sp);
5216                         return SUCCESS;
5217                 }
5218         }
5219         DBG_PRINT(ERR_DBG, "MAC address 0x%llx not found in CAM\n",
5220                         (unsigned long long)addr);
5221         return FAILURE;
5222 }
5223
5224 /* read mac entries from CAM */
5225 static u64 do_s2io_read_unicast_mc(struct s2io_nic *sp, int offset)
5226 {
5227         u64 tmp64 = 0xffffffffffff0000ULL, val64;
5228         struct XENA_dev_config __iomem *bar0 = sp->bar0;
5229
5230         /* read mac addr */
5231         val64 =
5232                 RMAC_ADDR_CMD_MEM_RD | RMAC_ADDR_CMD_MEM_STROBE_NEW_CMD |
5233                 RMAC_ADDR_CMD_MEM_OFFSET(offset);
5234         writeq(val64, &bar0->rmac_addr_cmd_mem);
5235
5236         /* Wait till command completes */
5237         if (wait_for_cmd_complete(&bar0->rmac_addr_cmd_mem,
5238                 RMAC_ADDR_CMD_MEM_STROBE_CMD_EXECUTING,
5239                 S2IO_BIT_RESET)) {
5240                 DBG_PRINT(INFO_DBG, "do_s2io_read_unicast_mc failed\n");
5241                 return FAILURE;
5242         }
5243         tmp64 = readq(&bar0->rmac_addr_data0_mem);
5244         return (tmp64 >> 16);
5245 }
5246
5247 /**
5248  * s2io_set_mac_addr driver entry point
5249  */
5250
5251 static int s2io_set_mac_addr(struct net_device *dev, void *p)
5252 {
5253         struct sockaddr *addr = p;
5254
5255         if (!is_valid_ether_addr(addr->sa_data))
5256                 return -EINVAL;
5257
5258         memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
5259
5260         /* store the MAC address in CAM */
5261         return (do_s2io_prog_unicast(dev, dev->dev_addr));
5262 }
5263 /**
5264  *  do_s2io_prog_unicast - Programs the Xframe mac address
5265  *  @dev : pointer to the device structure.
5266  *  @addr: a uchar pointer to the new mac address which is to be set.
5267  *  Description : This procedure will program the Xframe to receive
5268  *  frames with new Mac Address
5269  *  Return value: SUCCESS on success and an appropriate (-)ve integer
5270  *  as defined in errno.h file on failure.
5271  */
5272
5273 static int do_s2io_prog_unicast(struct net_device *dev, u8 *addr)
5274 {
5275         struct s2io_nic *sp = dev->priv;
5276         register u64 mac_addr = 0, perm_addr = 0;
5277         int i;
5278         u64 tmp64;
5279         struct config_param *config = &sp->config;
5280
5281         /*
5282         * Set the new MAC address as the new unicast filter and reflect this
5283         * change on the device address registered with the OS. It will be
5284         * at offset 0.
5285         */
5286         for (i = 0; i < ETH_ALEN; i++) {
5287                 mac_addr <<= 8;
5288                 mac_addr |= addr[i];
5289                 perm_addr <<= 8;
5290                 perm_addr |= sp->def_mac_addr[0].mac_addr[i];
5291         }
5292
5293         /* check if the dev_addr is different than perm_addr */
5294         if (mac_addr == perm_addr)
5295                 return SUCCESS;
5296
5297         /* check if the mac already preset in CAM */
5298         for (i = 1; i < config->max_mac_addr; i++) {
5299                 tmp64 = do_s2io_read_unicast_mc(sp, i);
5300                 if (tmp64 == S2IO_DISABLE_MAC_ENTRY) /* CAM entry is empty */
5301                         break;
5302
5303                 if (tmp64 == mac_addr) {
5304                         DBG_PRINT(INFO_DBG,
5305                         "MAC addr:0x%llx already present in CAM\n",
5306                         (unsigned long long)mac_addr);
5307                         return SUCCESS;
5308                 }
5309         }
5310         if (i == config->max_mac_addr) {
5311                 DBG_PRINT(ERR_DBG, "CAM full no space left for Unicast MAC\n");
5312                 return FAILURE;
5313         }
5314         /* Update the internal structure with this new mac address */
5315         do_s2io_copy_mac_addr(sp, i, mac_addr);
5316         return (do_s2io_add_mac(sp, mac_addr, i));
5317 }
5318
5319 /**
5320  * s2io_ethtool_sset - Sets different link parameters.
5321  * @sp : private member of the device structure, which is a pointer to the  * s2io_nic structure.
5322  * @info: pointer to the structure with parameters given by ethtool to set
5323  * link information.
5324  * Description:
5325  * The function sets different link parameters provided by the user onto
5326  * the NIC.
5327  * Return value:
5328  * 0 on success.
5329 */
5330
5331 static int s2io_ethtool_sset(struct net_device *dev,
5332                              struct ethtool_cmd *info)
5333 {
5334         struct s2io_nic *sp = dev->priv;
5335         if ((info->autoneg == AUTONEG_ENABLE) ||
5336             (info->speed != SPEED_10000) || (info->duplex != DUPLEX_FULL))
5337                 return -EINVAL;
5338         else {
5339                 s2io_close(sp->dev);
5340                 s2io_open(sp->dev);
5341         }
5342
5343         return 0;
5344 }
5345
5346 /**
5347  * s2io_ethtol_gset - Return link specific information.
5348  * @sp : private member of the device structure, pointer to the
5349  *      s2io_nic structure.
5350  * @info : pointer to the structure with parameters given by ethtool
5351  * to return link information.
5352  * Description:
5353  * Returns link specific information like speed, duplex etc.. to ethtool.
5354  * Return value :
5355  * return 0 on success.
5356  */
5357
5358 static int s2io_ethtool_gset(struct net_device *dev, struct ethtool_cmd *info)
5359 {
5360         struct s2io_nic *sp = dev->priv;
5361         info->supported = (SUPPORTED_10000baseT_Full | SUPPORTED_FIBRE);
5362         info->advertising = (SUPPORTED_10000baseT_Full | SUPPORTED_FIBRE);
5363         info->port = PORT_FIBRE;
5364
5365         /* info->transceiver */
5366         info->transceiver = XCVR_EXTERNAL;
5367
5368         if (netif_carrier_ok(sp->dev)) {
5369                 info->speed = 10000;
5370                 info->duplex = DUPLEX_FULL;
5371         } else {
5372                 info->speed = -1;
5373                 info->duplex = -1;
5374         }
5375
5376         info->autoneg = AUTONEG_DISABLE;
5377         return 0;
5378 }
5379
5380 /**
5381  * s2io_ethtool_gdrvinfo - Returns driver specific information.
5382  * @sp : private member of the device structure, which is a pointer to the
5383  * s2io_nic structure.
5384  * @info : pointer to the structure with parameters given by ethtool to
5385  * return driver information.
5386  * Description:
5387  * Returns driver specefic information like name, version etc.. to ethtool.
5388  * Return value:
5389  *  void
5390  */
5391
5392 static void s2io_ethtool_gdrvinfo(struct net_device *dev,
5393                                   struct ethtool_drvinfo *info)
5394 {
5395         struct s2io_nic *sp = dev->priv;
5396
5397         strncpy(info->driver, s2io_driver_name, sizeof(info->driver));
5398         strncpy(info->version, s2io_driver_version, sizeof(info->version));
5399         strncpy(info->fw_version, "", sizeof(info->fw_version));
5400         strncpy(info->bus_info, pci_name(sp->pdev), sizeof(info->bus_info));
5401         info->regdump_len = XENA_REG_SPACE;
5402         info->eedump_len = XENA_EEPROM_SPACE;
5403 }
5404
5405 /**
5406  *  s2io_ethtool_gregs - dumps the entire space of Xfame into the buffer.
5407  *  @sp: private member of the device structure, which is a pointer to the
5408  *  s2io_nic structure.
5409  *  @regs : pointer to the structure with parameters given by ethtool for
5410  *  dumping the registers.
5411  *  @reg_space: The input argumnet into which all the registers are dumped.
5412  *  Description:
5413  *  Dumps the entire register space of xFrame NIC into the user given
5414  *  buffer area.
5415  * Return value :
5416  * void .
5417 */
5418
5419 static void s2io_ethtool_gregs(struct net_device *dev,
5420                                struct ethtool_regs *regs, void *space)
5421 {
5422         int i;
5423         u64 reg;
5424         u8 *reg_space = (u8 *) space;
5425         struct s2io_nic *sp = dev->priv;
5426
5427         regs->len = XENA_REG_SPACE;
5428         regs->version = sp->pdev->subsystem_device;
5429
5430         for (i = 0; i < regs->len; i += 8) {
5431                 reg = readq(sp->bar0 + i);
5432                 memcpy((reg_space + i), &reg, 8);
5433         }
5434 }
5435
5436 /**
5437  *  s2io_phy_id  - timer function that alternates adapter LED.
5438  *  @data : address of the private member of the device structure, which
5439  *  is a pointer to the s2io_nic structure, provided as an u32.
5440  * Description: This is actually the timer function that alternates the
5441  * adapter LED bit of the adapter control bit to set/reset every time on
5442  * invocation. The timer is set for 1/2 a second, hence tha NIC blinks
5443  *  once every second.
5444 */
5445 static void s2io_phy_id(unsigned long data)
5446 {
5447         struct s2io_nic *sp = (struct s2io_nic *) data;
5448         struct XENA_dev_config __iomem *bar0 = sp->bar0;
5449         u64 val64 = 0;
5450         u16 subid;
5451
5452         subid = sp->pdev->subsystem_device;
5453         if ((sp->device_type == XFRAME_II_DEVICE) ||
5454                    ((subid & 0xFF) >= 0x07)) {
5455                 val64 = readq(&bar0->gpio_control);
5456                 val64 ^= GPIO_CTRL_GPIO_0;
5457                 writeq(val64, &bar0->gpio_control);
5458         } else {
5459                 val64 = readq(&bar0->adapter_control);
5460                 val64 ^= ADAPTER_LED_ON;
5461                 writeq(val64, &bar0->adapter_control);
5462         }
5463
5464         mod_timer(&sp->id_timer, jiffies + HZ / 2);
5465 }
5466
5467 /**
5468  * s2io_ethtool_idnic - To physically identify the nic on the system.
5469  * @sp : private member of the device structure, which is a pointer to the
5470  * s2io_nic structure.
5471  * @id : pointer to the structure with identification parameters given by
5472  * ethtool.
5473  * Description: Used to physically identify the NIC on the system.
5474  * The Link LED will blink for a time specified by the user for
5475  * identification.
5476  * NOTE: The Link has to be Up to be able to blink the LED. Hence
5477  * identification is possible only if it's link is up.
5478  * Return value:
5479  * int , returns 0 on success
5480  */
5481
5482 static int s2io_ethtool_idnic(struct net_device *dev, u32 data)
5483 {
5484         u64 val64 = 0, last_gpio_ctrl_val;
5485         struct s2io_nic *sp = dev->priv;
5486         struct XENA_dev_config __iomem *bar0 = sp->bar0;
5487         u16 subid;
5488
5489         subid = sp->pdev->subsystem_device;
5490         last_gpio_ctrl_val = readq(&bar0->gpio_control);
5491         if ((sp->device_type == XFRAME_I_DEVICE) &&
5492                 ((subid & 0xFF) < 0x07)) {
5493                 val64 = readq(&bar0->adapter_control);
5494                 if (!(val64 & ADAPTER_CNTL_EN)) {
5495                         printk(KERN_ERR
5496                                "Adapter Link down, cannot blink LED\n");
5497                         return -EFAULT;
5498                 }
5499         }
5500         if (sp->id_timer.function == NULL) {
5501                 init_timer(&sp->id_timer);
5502                 sp->id_timer.function = s2io_phy_id;
5503                 sp->id_timer.data = (unsigned long) sp;
5504         }
5505         mod_timer(&sp->id_timer, jiffies);
5506         if (data)
5507                 msleep_interruptible(data * HZ);
5508         else
5509                 msleep_interruptible(MAX_FLICKER_TIME);
5510         del_timer_sync(&sp->id_timer);
5511
5512         if (CARDS_WITH_FAULTY_LINK_INDICATORS(sp->device_type, subid)) {
5513                 writeq(last_gpio_ctrl_val, &bar0->gpio_control);
5514                 last_gpio_ctrl_val = readq(&bar0->gpio_control);
5515         }
5516
5517         return 0;
5518 }
5519
5520 static void s2io_ethtool_gringparam(struct net_device *dev,
5521                                     struct ethtool_ringparam *ering)
5522 {
5523         struct s2io_nic *sp = dev->priv;
5524         int i,tx_desc_count=0,rx_desc_count=0;
5525
5526         if (sp->rxd_mode == RXD_MODE_1)
5527                 ering->rx_max_pending = MAX_RX_DESC_1;
5528         else if (sp->rxd_mode == RXD_MODE_3B)
5529                 ering->rx_max_pending = MAX_RX_DESC_2;
5530
5531         ering->tx_max_pending = MAX_TX_DESC;
5532         for (i = 0 ; i < sp->config.tx_fifo_num ; i++)
5533                 tx_desc_count += sp->config.tx_cfg[i].fifo_len;
5534
5535         DBG_PRINT(INFO_DBG,"\nmax txds : %d\n",sp->config.max_txds);
5536         ering->tx_pending = tx_desc_count;
5537         rx_desc_count = 0;
5538         for (i = 0 ; i < sp->config.rx_ring_num ; i++)
5539                 rx_desc_count += sp->config.rx_cfg[i].num_rxd;
5540
5541         ering->rx_pending = rx_desc_count;
5542
5543         ering->rx_mini_max_pending = 0;
5544         ering->rx_mini_pending = 0;
5545         if(sp->rxd_mode == RXD_MODE_1)
5546                 ering->rx_jumbo_max_pending = MAX_RX_DESC_1;
5547         else if (sp->rxd_mode == RXD_MODE_3B)
5548                 ering->rx_jumbo_max_pending = MAX_RX_DESC_2;
5549         ering->rx_jumbo_pending = rx_desc_count;
5550 }
5551
5552 /**
5553  * s2io_ethtool_getpause_data -Pause frame frame generation and reception.
5554  * @sp : private member of the device structure, which is a pointer to the
5555  *      s2io_nic structure.
5556  * @ep : pointer to the structure with pause parameters given by ethtool.
5557  * Description:
5558  * Returns the Pause frame generation and reception capability of the NIC.
5559  * Return value:
5560  *  void
5561  */
5562 static void s2io_ethtool_getpause_data(struct net_device *dev,
5563                                        struct ethtool_pauseparam *ep)
5564 {
5565         u64 val64;
5566         struct s2io_nic *sp = dev->priv;
5567         struct XENA_dev_config __iomem *bar0 = sp->bar0;
5568
5569         val64 = readq(&bar0->rmac_pause_cfg);
5570         if (val64 & RMAC_PAUSE_GEN_ENABLE)
5571                 ep->tx_pause = TRUE;
5572         if (val64 & RMAC_PAUSE_RX_ENABLE)
5573                 ep->rx_pause = TRUE;
5574         ep->autoneg = FALSE;
5575 }
5576
5577 /**
5578  * s2io_ethtool_setpause_data -  set/reset pause frame generation.
5579  * @sp : private member of the device structure, which is a pointer to the
5580  *      s2io_nic structure.
5581  * @ep : pointer to the structure with pause parameters given by ethtool.
5582  * Description:
5583  * It can be used to set or reset Pause frame generation or reception
5584  * support of the NIC.
5585  * Return value:
5586  * int, returns 0 on Success
5587  */
5588
5589 static int s2io_ethtool_setpause_data(struct net_device *dev,
5590                                struct ethtool_pauseparam *ep)
5591 {
5592         u64 val64;
5593         struct s2io_nic *sp = dev->priv;
5594         struct XENA_dev_config __iomem *bar0 = sp->bar0;
5595
5596         val64 = readq(&bar0->rmac_pause_cfg);
5597         if (ep->tx_pause)
5598                 val64 |= RMAC_PAUSE_GEN_ENABLE;
5599         else
5600                 val64 &= ~RMAC_PAUSE_GEN_ENABLE;
5601         if (ep->rx_pause)
5602                 val64 |= RMAC_PAUSE_RX_ENABLE;
5603         else
5604                 val64 &= ~RMAC_PAUSE_RX_ENABLE;
5605         writeq(val64, &bar0->rmac_pause_cfg);
5606         return 0;
5607 }
5608
5609 /**
5610  * read_eeprom - reads 4 bytes of data from user given offset.
5611  * @sp : private member of the device structure, which is a pointer to the
5612  *      s2io_nic structure.
5613  * @off : offset at which the data must be written
5614  * @data : Its an output parameter where the data read at the given
5615  *      offset is stored.
5616  * Description:
5617  * Will read 4 bytes of data from the user given offset and return the
5618  * read data.
5619  * NOTE: Will allow to read only part of the EEPROM visible through the
5620  *   I2C bus.
5621  * Return value:
5622  *  -1 on failure and 0 on success.
5623  */
5624
5625 #define S2IO_DEV_ID             5
5626 static int read_eeprom(struct s2io_nic * sp, int off, u64 * data)
5627 {
5628         int ret = -1;
5629         u32 exit_cnt = 0;
5630         u64 val64;
5631         struct XENA_dev_config __iomem *bar0 = sp->bar0;
5632
5633         if (sp->device_type == XFRAME_I_DEVICE) {
5634                 val64 = I2C_CONTROL_DEV_ID(S2IO_DEV_ID) | I2C_CONTROL_ADDR(off) |
5635                     I2C_CONTROL_BYTE_CNT(0x3) | I2C_CONTROL_READ |
5636                     I2C_CONTROL_CNTL_START;
5637                 SPECIAL_REG_WRITE(val64, &bar0->i2c_control, LF);
5638
5639                 while (exit_cnt < 5) {
5640                         val64 = readq(&bar0->i2c_control);
5641                         if (I2C_CONTROL_CNTL_END(val64)) {
5642                                 *data = I2C_CONTROL_GET_DATA(val64);
5643                                 ret = 0;
5644                                 break;
5645                         }
5646                         msleep(50);
5647                         exit_cnt++;
5648                 }
5649         }
5650
5651         if (sp->device_type == XFRAME_II_DEVICE) {
5652                 val64 = SPI_CONTROL_KEY(0x9) | SPI_CONTROL_SEL1 |
5653                         SPI_CONTROL_BYTECNT(0x3) |
5654                         SPI_CONTROL_CMD(0x3) | SPI_CONTROL_ADDR(off);
5655                 SPECIAL_REG_WRITE(val64, &bar0->spi_control, LF);
5656                 val64 |= SPI_CONTROL_REQ;
5657                 SPECIAL_REG_WRITE(val64, &bar0->spi_control, LF);
5658                 while (exit_cnt < 5) {
5659                         val64 = readq(&bar0->spi_control);
5660                         if (val64 & SPI_CONTROL_NACK) {
5661                                 ret = 1;
5662                                 break;
5663                         } else if (val64 & SPI_CONTROL_DONE) {
5664                                 *data = readq(&bar0->spi_data);
5665                                 *data &= 0xffffff;
5666                                 ret = 0;
5667                                 break;
5668                         }
5669                         msleep(50);
5670                         exit_cnt++;
5671                 }
5672         }
5673         return ret;
5674 }
5675
5676 /**
5677  *  write_eeprom - actually writes the relevant part of the data value.
5678  *  @sp : private member of the device structure, which is a pointer to the
5679  *       s2io_nic structure.
5680  *  @off : offset at which the data must be written
5681  *  @data : The data that is to be written
5682  *  @cnt : Number of bytes of the data that are actually to be written into
5683  *  the Eeprom. (max of 3)
5684  * Description:
5685  *  Actually writes the relevant part of the data value into the Eeprom
5686  *  through the I2C bus.
5687  * Return value:
5688  *  0 on success, -1 on failure.
5689  */
5690
5691 static int write_eeprom(struct s2io_nic * sp, int off, u64 data, int cnt)
5692 {
5693         int exit_cnt = 0, ret = -1;
5694         u64 val64;
5695         struct XENA_dev_config __iomem *bar0 = sp->bar0;
5696
5697         if (sp->device_type == XFRAME_I_DEVICE) {
5698                 val64 = I2C_CONTROL_DEV_ID(S2IO_DEV_ID) | I2C_CONTROL_ADDR(off) |
5699                     I2C_CONTROL_BYTE_CNT(cnt) | I2C_CONTROL_SET_DATA((u32)data) |
5700                     I2C_CONTROL_CNTL_START;
5701                 SPECIAL_REG_WRITE(val64, &bar0->i2c_control, LF);
5702
5703                 while (exit_cnt < 5) {
5704                         val64 = readq(&bar0->i2c_control);
5705                         if (I2C_CONTROL_CNTL_END(val64)) {
5706                                 if (!(val64 & I2C_CONTROL_NACK))
5707                                         ret = 0;
5708                                 break;
5709                         }
5710                         msleep(50);
5711                         exit_cnt++;
5712                 }
5713         }
5714
5715         if (sp->device_type == XFRAME_II_DEVICE) {
5716                 int write_cnt = (cnt == 8) ? 0 : cnt;
5717                 writeq(SPI_DATA_WRITE(data,(cnt<<3)), &bar0->spi_data);
5718
5719                 val64 = SPI_CONTROL_KEY(0x9) | SPI_CONTROL_SEL1 |
5720                         SPI_CONTROL_BYTECNT(write_cnt) |
5721                         SPI_CONTROL_CMD(0x2) | SPI_CONTROL_ADDR(off);
5722                 SPECIAL_REG_WRITE(val64, &bar0->spi_control, LF);
5723                 val64 |= SPI_CONTROL_REQ;
5724                 SPECIAL_REG_WRITE(val64, &bar0->spi_control, LF);
5725                 while (exit_cnt < 5) {
5726                         val64 = readq(&bar0->spi_control);
5727                         if (val64 & SPI_CONTROL_NACK) {
5728                                 ret = 1;
5729                                 break;
5730                         } else if (val64 & SPI_CONTROL_DONE) {
5731                                 ret = 0;
5732                                 break;
5733                         }
5734                         msleep(50);
5735                         exit_cnt++;
5736                 }
5737         }
5738         return ret;
5739 }
5740 static void s2io_vpd_read(struct s2io_nic *nic)
5741 {
5742         u8 *vpd_data;
5743         u8 data;
5744         int i=0, cnt, fail = 0;
5745         int vpd_addr = 0x80;
5746
5747         if (nic->device_type == XFRAME_II_DEVICE) {
5748                 strcpy(nic->product_name, "Xframe II 10GbE network adapter");
5749                 vpd_addr = 0x80;
5750         }
5751         else {
5752                 strcpy(nic->product_name, "Xframe I 10GbE network adapter");
5753                 vpd_addr = 0x50;
5754         }
5755         strcpy(nic->serial_num, "NOT AVAILABLE");
5756
5757         vpd_data = kmalloc(256, GFP_KERNEL);
5758         if (!vpd_data) {
5759                 nic->mac_control.stats_info->sw_stat.mem_alloc_fail_cnt++;
5760                 return;
5761         }
5762         nic->mac_control.stats_info->sw_stat.mem_allocated += 256;
5763
5764         for (i = 0; i < 256; i +=4 ) {
5765                 pci_write_config_byte(nic->pdev, (vpd_addr + 2), i);
5766                 pci_read_config_byte(nic->pdev,  (vpd_addr + 2), &data);
5767                 pci_write_config_byte(nic->pdev, (vpd_addr + 3), 0);
5768                 for (cnt = 0; cnt <5; cnt++) {
5769                         msleep(2);
5770                         pci_read_config_byte(nic->pdev, (vpd_addr + 3), &data);
5771                         if (data == 0x80)
5772                                 break;
5773                 }
5774                 if (cnt >= 5) {
5775                         DBG_PRINT(ERR_DBG, "Read of VPD data failed\n");
5776                         fail = 1;
5777                         break;
5778                 }
5779                 pci_read_config_dword(nic->pdev,  (vpd_addr + 4),
5780                                       (u32 *)&vpd_data[i]);
5781         }
5782
5783         if(!fail) {
5784                 /* read serial number of adapter */
5785                 for (cnt = 0; cnt < 256; cnt++) {
5786                 if ((vpd_data[cnt] == 'S') &&
5787                         (vpd_data[cnt+1] == 'N') &&
5788                         (vpd_data[cnt+2] < VPD_STRING_LEN)) {
5789                                 memset(nic->serial_num, 0, VPD_STRING_LEN);
5790                                 memcpy(nic->serial_num, &vpd_data[cnt + 3],
5791                                         vpd_data[cnt+2]);
5792                                 break;
5793                         }
5794                 }
5795         }
5796
5797         if ((!fail) && (vpd_data[1] < VPD_STRING_LEN)) {
5798                 memset(nic->product_name, 0, vpd_data[1]);
5799                 memcpy(nic->product_name, &vpd_data[3], vpd_data[1]);
5800         }
5801         kfree(vpd_data);
5802         nic->mac_control.stats_info->sw_stat.mem_freed += 256;
5803 }
5804
5805 /**
5806  *  s2io_ethtool_geeprom  - reads the value stored in the Eeprom.
5807  *  @sp : private member of the device structure, which is a pointer to the *       s2io_nic structure.
5808  *  @eeprom : pointer to the user level structure provided by ethtool,
5809  *  containing all relevant information.
5810  *  @data_buf : user defined value to be written into Eeprom.
5811  *  Description: Reads the values stored in the Eeprom at given offset
5812  *  for a given length. Stores these values int the input argument data
5813  *  buffer 'data_buf' and returns these to the caller (ethtool.)
5814  *  Return value:
5815  *  int  0 on success
5816  */
5817
5818 static int s2io_ethtool_geeprom(struct net_device *dev,
5819                          struct ethtool_eeprom *eeprom, u8 * data_buf)
5820 {
5821         u32 i, valid;
5822         u64 data;
5823         struct s2io_nic *sp = dev->priv;
5824
5825         eeprom->magic = sp->pdev->vendor | (sp->pdev->device << 16);
5826
5827         if ((eeprom->offset + eeprom->len) > (XENA_EEPROM_SPACE))
5828                 eeprom->len = XENA_EEPROM_SPACE - eeprom->offset;
5829
5830         for (i = 0; i < eeprom->len; i += 4) {
5831                 if (read_eeprom(sp, (eeprom->offset + i), &data)) {
5832                         DBG_PRINT(ERR_DBG, "Read of EEPROM failed\n");
5833                         return -EFAULT;
5834                 }
5835                 valid = INV(data);
5836                 memcpy((data_buf + i), &valid, 4);
5837         }
5838         return 0;
5839 }
5840
5841 /**
5842  *  s2io_ethtool_seeprom - tries to write the user provided value in Eeprom
5843  *  @sp : private member of the device structure, which is a pointer to the
5844  *  s2io_nic structure.
5845  *  @eeprom : pointer to the user level structure provided by ethtool,
5846  *  containing all relevant information.
5847  *  @data_buf ; user defined value to be written into Eeprom.
5848  *  Description:
5849  *  Tries to write the user provided value in the Eeprom, at the offset
5850  *  given by the user.
5851  *  Return value:
5852  *  0 on success, -EFAULT on failure.
5853  */
5854
5855 static int s2io_ethtool_seeprom(struct net_device *dev,
5856                                 struct ethtool_eeprom *eeprom,
5857                                 u8 * data_buf)
5858 {
5859         int len = eeprom->len, cnt = 0;
5860         u64 valid = 0, data;
5861         struct s2io_nic *sp = dev->priv;
5862
5863         if (eeprom->magic != (sp->pdev->vendor | (sp->pdev->device << 16))) {
5864                 DBG_PRINT(ERR_DBG,
5865                           "ETHTOOL_WRITE_EEPROM Err: Magic value ");
5866                 DBG_PRINT(ERR_DBG, "is wrong, Its not 0x%x\n",
5867                           eeprom->magic);
5868                 return -EFAULT;
5869         }
5870
5871         while (len) {
5872                 data = (u32) data_buf[cnt] & 0x000000FF;
5873                 if (data) {
5874                         valid = (u32) (data << 24);
5875                 } else
5876                         valid = data;
5877
5878                 if (write_eeprom(sp, (eeprom->offset + cnt), valid, 0)) {
5879                         DBG_PRINT(ERR_DBG,
5880                                   "ETHTOOL_WRITE_EEPROM Err: Cannot ");
5881                         DBG_PRINT(ERR_DBG,
5882                                   "write into the specified offset\n");
5883                         return -EFAULT;
5884                 }
5885                 cnt++;
5886                 len--;
5887         }
5888
5889         return 0;
5890 }
5891
5892 /**
5893  * s2io_register_test - reads and writes into all clock domains.
5894  * @sp : private member of the device structure, which is a pointer to the
5895  * s2io_nic structure.
5896  * @data : variable that returns the result of each of the test conducted b
5897  * by the driver.
5898  * Description:
5899  * Read and write into all clock domains. The NIC has 3 clock domains,
5900  * see that registers in all the three regions are accessible.
5901  * Return value:
5902  * 0 on success.
5903  */
5904
5905 static int s2io_register_test(struct s2io_nic * sp, uint64_t * data)
5906 {
5907         struct XENA_dev_config __iomem *bar0 = sp->bar0;
5908         u64 val64 = 0, exp_val;
5909         int fail = 0;
5910
5911         val64 = readq(&bar0->pif_rd_swapper_fb);
5912         if (val64 != 0x123456789abcdefULL) {
5913                 fail = 1;
5914                 DBG_PRINT(INFO_DBG, "Read Test level 1 fails\n");
5915         }
5916
5917         val64 = readq(&bar0->rmac_pause_cfg);
5918         if (val64 != 0xc000ffff00000000ULL) {
5919                 fail = 1;
5920                 DBG_PRINT(INFO_DBG, "Read Test level 2 fails\n");
5921         }
5922
5923         val64 = readq(&bar0->rx_queue_cfg);
5924         if (sp->device_type == XFRAME_II_DEVICE)
5925                 exp_val = 0x0404040404040404ULL;
5926         else
5927                 exp_val = 0x0808080808080808ULL;
5928         if (val64 != exp_val) {
5929                 fail = 1;
5930                 DBG_PRINT(INFO_DBG, "Read Test level 3 fails\n");
5931         }
5932
5933         val64 = readq(&bar0->xgxs_efifo_cfg);
5934         if (val64 != 0x000000001923141EULL) {
5935                 fail = 1;
5936                 DBG_PRINT(INFO_DBG, "Read Test level 4 fails\n");
5937         }
5938
5939         val64 = 0x5A5A5A5A5A5A5A5AULL;
5940         writeq(val64, &bar0->xmsi_data);
5941         val64 = readq(&bar0->xmsi_data);
5942         if (val64 != 0x5A5A5A5A5A5A5A5AULL) {
5943                 fail = 1;
5944                 DBG_PRINT(ERR_DBG, "Write Test level 1 fails\n");
5945         }
5946
5947         val64 = 0xA5A5A5A5A5A5A5A5ULL;
5948         writeq(val64, &bar0->xmsi_data);
5949         val64 = readq(&bar0->xmsi_data);
5950         if (val64 != 0xA5A5A5A5A5A5A5A5ULL) {
5951                 fail = 1;
5952                 DBG_PRINT(ERR_DBG, "Write Test level 2 fails\n");
5953         }
5954
5955         *data = fail;
5956         return fail;
5957 }
5958
5959 /**
5960  * s2io_eeprom_test - to verify that EEprom in the xena can be programmed.
5961  * @sp : private member of the device structure, which is a pointer to the
5962  * s2io_nic structure.
5963  * @data:variable that returns the result of each of the test conducted by
5964  * the driver.
5965  * Description:
5966  * Verify that EEPROM in the xena can be programmed using I2C_CONTROL
5967  * register.
5968  * Return value:
5969  * 0 on success.
5970  */
5971
5972 static int s2io_eeprom_test(struct s2io_nic * sp, uint64_t * data)
5973 {
5974         int fail = 0;
5975         u64 ret_data, org_4F0, org_7F0;
5976         u8 saved_4F0 = 0, saved_7F0 = 0;
5977         struct net_device *dev = sp->dev;
5978
5979         /* Test Write Error at offset 0 */
5980         /* Note that SPI interface allows write access to all areas
5981          * of EEPROM. Hence doing all negative testing only for Xframe I.
5982          */
5983         if (sp->device_type == XFRAME_I_DEVICE)
5984                 if (!write_eeprom(sp, 0, 0, 3))
5985                         fail = 1;
5986
5987         /* Save current values at offsets 0x4F0 and 0x7F0 */
5988         if (!read_eeprom(sp, 0x4F0, &org_4F0))
5989                 saved_4F0 = 1;
5990         if (!read_eeprom(sp, 0x7F0, &org_7F0))
5991                 saved_7F0 = 1;
5992
5993         /* Test Write at offset 4f0 */
5994         if (write_eeprom(sp, 0x4F0, 0x012345, 3))
5995                 fail = 1;
5996         if (read_eeprom(sp, 0x4F0, &ret_data))
5997                 fail = 1;
5998
5999         if (ret_data != 0x012345) {
6000                 DBG_PRINT(ERR_DBG, "%s: eeprom test error at offset 0x4F0. "
6001                         "Data written %llx Data read %llx\n",
6002                         dev->name, (unsigned long long)0x12345,
6003                         (unsigned long long)ret_data);
6004                 fail = 1;
6005         }
6006
6007         /* Reset the EEPROM data go FFFF */
6008         write_eeprom(sp, 0x4F0, 0xFFFFFF, 3);
6009
6010         /* Test Write Request Error at offset 0x7c */
6011         if (sp->device_type == XFRAME_I_DEVICE)
6012                 if (!write_eeprom(sp, 0x07C, 0, 3))
6013                         fail = 1;
6014
6015         /* Test Write Request at offset 0x7f0 */
6016         if (write_eeprom(sp, 0x7F0, 0x012345, 3))
6017                 fail = 1;
6018         if (read_eeprom(sp, 0x7F0, &ret_data))
6019                 fail = 1;
6020
6021         if (ret_data != 0x012345) {
6022                 DBG_PRINT(ERR_DBG, "%s: eeprom test error at offset 0x7F0. "
6023                         "Data written %llx Data read %llx\n",
6024                         dev->name, (unsigned long long)0x12345,
6025                         (unsigned long long)ret_data);
6026                 fail = 1;
6027         }
6028
6029         /* Reset the EEPROM data go FFFF */
6030         write_eeprom(sp, 0x7F0, 0xFFFFFF, 3);
6031
6032         if (sp->device_type == XFRAME_I_DEVICE) {
6033                 /* Test Write Error at offset 0x80 */
6034                 if (!write_eeprom(sp, 0x080, 0, 3))
6035                         fail = 1;
6036
6037                 /* Test Write Error at offset 0xfc */
6038                 if (!write_eeprom(sp, 0x0FC, 0, 3))
6039                         fail = 1;
6040
6041                 /* Test Write Error at offset 0x100 */
6042                 if (!write_eeprom(sp, 0x100, 0, 3))
6043                         fail = 1;
6044
6045                 /* Test Write Error at offset 4ec */
6046                 if (!write_eeprom(sp, 0x4EC, 0, 3))
6047                         fail = 1;
6048         }
6049
6050         /* Restore values at offsets 0x4F0 and 0x7F0 */
6051         if (saved_4F0)
6052                 write_eeprom(sp, 0x4F0, org_4F0, 3);
6053         if (saved_7F0)
6054                 write_eeprom(sp, 0x7F0, org_7F0, 3);
6055
6056         *data = fail;
6057         return fail;
6058 }
6059
6060 /**
6061  * s2io_bist_test - invokes the MemBist test of the card .
6062  * @sp : private member of the device structure, which is a pointer to the
6063  * s2io_nic structure.
6064  * @data:variable that returns the result of each of the test conducted by
6065  * the driver.
6066  * Description:
6067  * This invokes the MemBist test of the card. We give around
6068  * 2 secs time for the Test to complete. If it's still not complete
6069  * within this peiod, we consider that the test failed.
6070  * Return value:
6071  * 0 on success and -1 on failure.
6072  */
6073
6074 static int s2io_bist_test(struct s2io_nic * sp, uint64_t * data)
6075 {
6076         u8 bist = 0;
6077         int cnt = 0, ret = -1;
6078
6079         pci_read_config_byte(sp->pdev, PCI_BIST, &bist);
6080         bist |= PCI_BIST_START;
6081         pci_write_config_word(sp->pdev, PCI_BIST, bist);
6082
6083         while (cnt < 20) {
6084                 pci_read_config_byte(sp->pdev, PCI_BIST, &bist);
6085                 if (!(bist & PCI_BIST_START)) {
6086                         *data = (bist & PCI_BIST_CODE_MASK);
6087                         ret = 0;
6088                         break;
6089                 }
6090                 msleep(100);
6091                 cnt++;
6092         }
6093
6094         return ret;
6095 }
6096
6097 /**
6098  * s2io-link_test - verifies the link state of the nic
6099  * @sp ; private member of the device structure, which is a pointer to the
6100  * s2io_nic structure.
6101  * @data: variable that returns the result of each of the test conducted by
6102  * the driver.
6103  * Description:
6104  * The function verifies the link state of the NIC and updates the input
6105  * argument 'data' appropriately.
6106  * Return value:
6107  * 0 on success.
6108  */
6109
6110 static int s2io_link_test(struct s2io_nic * sp, uint64_t * data)
6111 {
6112         struct XENA_dev_config __iomem *bar0 = sp->bar0;
6113         u64 val64;
6114
6115         val64 = readq(&bar0->adapter_status);
6116         if(!(LINK_IS_UP(val64)))
6117                 *data = 1;
6118         else
6119                 *data = 0;
6120
6121         return *data;
6122 }
6123
6124 /**
6125  * s2io_rldram_test - offline test for access to the RldRam chip on the NIC
6126  * @sp - private member of the device structure, which is a pointer to the
6127  * s2io_nic structure.
6128  * @data - variable that returns the result of each of the test
6129  * conducted by the driver.
6130  * Description:
6131  *  This is one of the offline test that tests the read and write
6132  *  access to the RldRam chip on the NIC.
6133  * Return value:
6134  *  0 on success.
6135  */
6136
6137 static int s2io_rldram_test(struct s2io_nic * sp, uint64_t * data)
6138 {
6139         struct XENA_dev_config __iomem *bar0 = sp->bar0;
6140         u64 val64;
6141         int cnt, iteration = 0, test_fail = 0;
6142
6143         val64 = readq(&bar0->adapter_control);
6144         val64 &= ~ADAPTER_ECC_EN;
6145         writeq(val64, &bar0->adapter_control);
6146
6147         val64 = readq(&bar0->mc_rldram_test_ctrl);
6148         val64 |= MC_RLDRAM_TEST_MODE;
6149         SPECIAL_REG_WRITE(val64, &bar0->mc_rldram_test_ctrl, LF);
6150
6151         val64 = readq(&bar0->mc_rldram_mrs);
6152         val64 |= MC_RLDRAM_QUEUE_SIZE_ENABLE;
6153         SPECIAL_REG_WRITE(val64, &bar0->mc_rldram_mrs, UF);
6154
6155         val64 |= MC_RLDRAM_MRS_ENABLE;
6156         SPECIAL_REG_WRITE(val64, &bar0->mc_rldram_mrs, UF);
6157
6158         while (iteration < 2) {
6159                 val64 = 0x55555555aaaa0000ULL;
6160                 if (iteration == 1) {
6161                         val64 ^= 0xFFFFFFFFFFFF0000ULL;
6162                 }
6163                 writeq(val64, &bar0->mc_rldram_test_d0);
6164
6165                 val64 = 0xaaaa5a5555550000ULL;
6166                 if (iteration == 1) {
6167                         val64 ^= 0xFFFFFFFFFFFF0000ULL;
6168                 }
6169                 writeq(val64, &bar0->mc_rldram_test_d1);
6170
6171                 val64 = 0x55aaaaaaaa5a0000ULL;
6172                 if (iteration == 1) {
6173                         val64 ^= 0xFFFFFFFFFFFF0000ULL;
6174                 }
6175                 writeq(val64, &bar0->mc_rldram_test_d2);
6176
6177                 val64 = (u64) (0x0000003ffffe0100ULL);
6178                 writeq(val64, &bar0->mc_rldram_test_add);
6179
6180                 val64 = MC_RLDRAM_TEST_MODE | MC_RLDRAM_TEST_WRITE |
6181                         MC_RLDRAM_TEST_GO;
6182                 SPECIAL_REG_WRITE(val64, &bar0->mc_rldram_test_ctrl, LF);
6183
6184                 for (cnt = 0; cnt < 5; cnt++) {
6185                         val64 = readq(&bar0->mc_rldram_test_ctrl);
6186                         if (val64 & MC_RLDRAM_TEST_DONE)
6187                                 break;
6188                         msleep(200);
6189                 }
6190
6191                 if (cnt == 5)
6192                         break;
6193
6194                 val64 = MC_RLDRAM_TEST_MODE | MC_RLDRAM_TEST_GO;
6195                 SPECIAL_REG_WRITE(val64, &bar0->mc_rldram_test_ctrl, LF);
6196
6197                 for (cnt = 0; cnt < 5; cnt++) {
6198                         val64 = readq(&bar0->mc_rldram_test_ctrl);
6199                         if (val64 & MC_RLDRAM_TEST_DONE)
6200                                 break;
6201                         msleep(500);
6202                 }
6203
6204                 if (cnt == 5)
6205                         break;
6206
6207                 val64 = readq(&bar0->mc_rldram_test_ctrl);
6208                 if (!(val64 & MC_RLDRAM_TEST_PASS))
6209                         test_fail = 1;
6210
6211                 iteration++;
6212         }
6213
6214         *data = test_fail;
6215
6216         /* Bring the adapter out of test mode */
6217         SPECIAL_REG_WRITE(0, &bar0->mc_rldram_test_ctrl, LF);
6218
6219         return test_fail;
6220 }
6221
6222 /**
6223  *  s2io_ethtool_test - conducts 6 tsets to determine the health of card.
6224  *  @sp : private member of the device structure, which is a pointer to the
6225  *  s2io_nic structure.
6226  *  @ethtest : pointer to a ethtool command specific structure that will be
6227  *  returned to the user.
6228  *  @data : variable that returns the result of each of the test
6229  * conducted by the driver.
6230  * Description:
6231  *  This function conducts 6 tests ( 4 offline and 2 online) to determine
6232  *  the health of the card.
6233  * Return value:
6234  *  void
6235  */
6236
6237 static void s2io_ethtool_test(struct net_device *dev,
6238                               struct ethtool_test *ethtest,
6239                               uint64_t * data)
6240 {
6241         struct s2io_nic *sp = dev->priv;
6242         int orig_state = netif_running(sp->dev);
6243
6244         if (ethtest->flags == ETH_TEST_FL_OFFLINE) {
6245                 /* Offline Tests. */
6246                 if (orig_state)
6247                         s2io_close(sp->dev);
6248
6249                 if (s2io_register_test(sp, &data[0]))
6250                         ethtest->flags |= ETH_TEST_FL_FAILED;
6251
6252                 s2io_reset(sp);
6253
6254                 if (s2io_rldram_test(sp, &data[3]))
6255                         ethtest->flags |= ETH_TEST_FL_FAILED;
6256
6257                 s2io_reset(sp);
6258
6259                 if (s2io_eeprom_test(sp, &data[1]))
6260                         ethtest->flags |= ETH_TEST_FL_FAILED;
6261
6262                 if (s2io_bist_test(sp, &data[4]))
6263                         ethtest->flags |= ETH_TEST_FL_FAILED;
6264
6265                 if (orig_state)
6266                         s2io_open(sp->dev);
6267
6268                 data[2] = 0;
6269         } else {
6270                 /* Online Tests. */
6271                 if (!orig_state) {
6272                         DBG_PRINT(ERR_DBG,
6273                                   "%s: is not up, cannot run test\n",
6274                                   dev->name);
6275                         data[0] = -1;
6276                         data[1] = -1;
6277                         data[2] = -1;
6278                         data[3] = -1;
6279                         data[4] = -1;
6280                 }
6281
6282                 if (s2io_link_test(sp, &data[2]))
6283                         ethtest->flags |= ETH_TEST_FL_FAILED;
6284
6285                 data[0] = 0;
6286                 data[1] = 0;
6287                 data[3] = 0;
6288                 data[4] = 0;
6289         }
6290 }
6291
6292 static void s2io_get_ethtool_stats(struct net_device *dev,
6293                                    struct ethtool_stats *estats,
6294                                    u64 * tmp_stats)
6295 {
6296         int i = 0, k;
6297         struct s2io_nic *sp = dev->priv;
6298         struct stat_block *stat_info = sp->mac_control.stats_info;
6299
6300         s2io_updt_stats(sp);
6301         tmp_stats[i++] =
6302                 (u64)le32_to_cpu(stat_info->tmac_frms_oflow) << 32  |
6303                 le32_to_cpu(stat_info->tmac_frms);
6304         tmp_stats[i++] =
6305                 (u64)le32_to_cpu(stat_info->tmac_data_octets_oflow) << 32 |
6306                 le32_to_cpu(stat_info->tmac_data_octets);
6307         tmp_stats[i++] = le64_to_cpu(stat_info->tmac_drop_frms);
6308         tmp_stats[i++] =
6309                 (u64)le32_to_cpu(stat_info->tmac_mcst_frms_oflow) << 32 |
6310                 le32_to_cpu(stat_info->tmac_mcst_frms);
6311         tmp_stats[i++] =
6312                 (u64)le32_to_cpu(stat_info->tmac_bcst_frms_oflow) << 32 |
6313                 le32_to_cpu(stat_info->tmac_bcst_frms);
6314         tmp_stats[i++] = le64_to_cpu(stat_info->tmac_pause_ctrl_frms);
6315         tmp_stats[i++] =
6316                 (u64)le32_to_cpu(stat_info->tmac_ttl_octets_oflow) << 32 |
6317                 le32_to_cpu(stat_info->tmac_ttl_octets);
6318         tmp_stats[i++] =
6319                 (u64)le32_to_cpu(stat_info->tmac_ucst_frms_oflow) << 32 |
6320                 le32_to_cpu(stat_info->tmac_ucst_frms);
6321         tmp_stats[i++] =
6322                 (u64)le32_to_cpu(stat_info->tmac_nucst_frms_oflow) << 32 |
6323                 le32_to_cpu(stat_info->tmac_nucst_frms);
6324         tmp_stats[i++] =
6325                 (u64)le32_to_cpu(stat_info->tmac_any_err_frms_oflow) << 32 |
6326                 le32_to_cpu(stat_info->tmac_any_err_frms);
6327         tmp_stats[i++] = le64_to_cpu(stat_info->tmac_ttl_less_fb_octets);
6328         tmp_stats[i++] = le64_to_cpu(stat_info->tmac_vld_ip_octets);
6329         tmp_stats[i++] =
6330                 (u64)le32_to_cpu(stat_info->tmac_vld_ip_oflow) << 32 |
6331                 le32_to_cpu(stat_info->tmac_vld_ip);
6332         tmp_stats[i++] =
6333                 (u64)le32_to_cpu(stat_info->tmac_drop_ip_oflow) << 32 |
6334                 le32_to_cpu(stat_info->tmac_drop_ip);
6335         tmp_stats[i++] =
6336                 (u64)le32_to_cpu(stat_info->tmac_icmp_oflow) << 32 |
6337                 le32_to_cpu(stat_info->tmac_icmp);
6338         tmp_stats[i++] =
6339                 (u64)le32_to_cpu(stat_info->tmac_rst_tcp_oflow) << 32 |
6340                 le32_to_cpu(stat_info->tmac_rst_tcp);
6341         tmp_stats[i++] = le64_to_cpu(stat_info->tmac_tcp);
6342         tmp_stats[i++] = (u64)le32_to_cpu(stat_info->tmac_udp_oflow) << 32 |
6343                 le32_to_cpu(stat_info->tmac_udp);
6344         tmp_stats[i++] =
6345                 (u64)le32_to_cpu(stat_info->rmac_vld_frms_oflow) << 32 |
6346                 le32_to_cpu(stat_info->rmac_vld_frms);
6347         tmp_stats[i++] =
6348                 (u64)le32_to_cpu(stat_info->rmac_data_octets_oflow) << 32 |
6349                 le32_to_cpu(stat_info->rmac_data_octets);
6350         tmp_stats[i++] = le64_to_cpu(stat_info->rmac_fcs_err_frms);
6351         tmp_stats[i++] = le64_to_cpu(stat_info->rmac_drop_frms);
6352         tmp_stats[i++] =
6353                 (u64)le32_to_cpu(stat_info->rmac_vld_mcst_frms_oflow) << 32 |
6354                 le32_to_cpu(stat_info->rmac_vld_mcst_frms);
6355         tmp_stats[i++] =
6356                 (u64)le32_to_cpu(stat_info->rmac_vld_bcst_frms_oflow) << 32 |
6357                 le32_to_cpu(stat_info->rmac_vld_bcst_frms);
6358         tmp_stats[i++] = le32_to_cpu(stat_info->rmac_in_rng_len_err_frms);
6359         tmp_stats[i++] = le32_to_cpu(stat_info->rmac_out_rng_len_err_frms);
6360         tmp_stats[i++] = le64_to_cpu(stat_info->rmac_long_frms);
6361         tmp_stats[i++] = le64_to_cpu(stat_info->rmac_pause_ctrl_frms);
6362         tmp_stats[i++] = le64_to_cpu(stat_info->rmac_unsup_ctrl_frms);
6363         tmp_stats[i++] =
6364                 (u64)le32_to_cpu(stat_info->rmac_ttl_octets_oflow) << 32 |
6365                 le32_to_cpu(stat_info->rmac_ttl_octets);
6366         tmp_stats[i++] =
6367                 (u64)le32_to_cpu(stat_info->rmac_accepted_ucst_frms_oflow)
6368                 << 32 | le32_to_cpu(stat_info->rmac_accepted_ucst_frms);
6369         tmp_stats[i++] =
6370                 (u64)le32_to_cpu(stat_info->rmac_accepted_nucst_frms_oflow)
6371                  << 32 | le32_to_cpu(stat_info->rmac_accepted_nucst_frms);
6372         tmp_stats[i++] =
6373                 (u64)le32_to_cpu(stat_info->rmac_discarded_frms_oflow) << 32 |
6374                 le32_to_cpu(stat_info->rmac_discarded_frms);
6375         tmp_stats[i++] =
6376                 (u64)le32_to_cpu(stat_info->rmac_drop_events_oflow)
6377                  << 32 | le32_to_cpu(stat_info->rmac_drop_events);
6378         tmp_stats[i++] = le64_to_cpu(stat_info->rmac_ttl_less_fb_octets);
6379         tmp_stats[i++] = le64_to_cpu(stat_info->rmac_ttl_frms);
6380         tmp_stats[i++] =
6381                 (u64)le32_to_cpu(stat_info->rmac_usized_frms_oflow) << 32 |
6382                 le32_to_cpu(stat_info->rmac_usized_frms);
6383         tmp_stats[i++] =
6384                 (u64)le32_to_cpu(stat_info->rmac_osized_frms_oflow) << 32 |
6385                 le32_to_cpu(stat_info->rmac_osized_frms);
6386         tmp_stats[i++] =
6387                 (u64)le32_to_cpu(stat_info->rmac_frag_frms_oflow) << 32 |
6388                 le32_to_cpu(stat_info->rmac_frag_frms);
6389         tmp_stats[i++] =
6390                 (u64)le32_to_cpu(stat_info->rmac_jabber_frms_oflow) << 32 |
6391                 le32_to_cpu(stat_info->rmac_jabber_frms);
6392         tmp_stats[i++] = le64_to_cpu(stat_info->rmac_ttl_64_frms);
6393         tmp_stats[i++] = le64_to_cpu(stat_info->rmac_ttl_65_127_frms);
6394         tmp_stats[i++] = le64_to_cpu(stat_info->rmac_ttl_128_255_frms);
6395         tmp_stats[i++] = le64_to_cpu(stat_info->rmac_ttl_256_511_frms);
6396         tmp_stats[i++] = le64_to_cpu(stat_info->rmac_ttl_512_1023_frms);
6397         tmp_stats[i++] = le64_to_cpu(stat_info->rmac_ttl_1024_1518_frms);
6398         tmp_stats[i++] =
6399                 (u64)le32_to_cpu(stat_info->rmac_ip_oflow) << 32 |
6400                 le32_to_cpu(stat_info->rmac_ip);
6401         tmp_stats[i++] = le64_to_cpu(stat_info->rmac_ip_octets);
6402         tmp_stats[i++] = le32_to_cpu(stat_info->rmac_hdr_err_ip);
6403         tmp_stats[i++] =
6404                 (u64)le32_to_cpu(stat_info->rmac_drop_ip_oflow) << 32 |
6405                 le32_to_cpu(stat_info->rmac_drop_ip);
6406         tmp_stats[i++] =
6407                 (u64)le32_to_cpu(stat_info->rmac_icmp_oflow) << 32 |
6408                 le32_to_cpu(stat_info->rmac_icmp);
6409         tmp_stats[i++] = le64_to_cpu(stat_info->rmac_tcp);
6410         tmp_stats[i++] =
6411                 (u64)le32_to_cpu(stat_info->rmac_udp_oflow) << 32 |
6412                 le32_to_cpu(stat_info->rmac_udp);
6413         tmp_stats[i++] =
6414                 (u64)le32_to_cpu(stat_info->rmac_err_drp_udp_oflow) << 32 |
6415                 le32_to_cpu(stat_info->rmac_err_drp_udp);
6416         tmp_stats[i++] = le64_to_cpu(stat_info->rmac_xgmii_err_sym);
6417         tmp_stats[i++] = le64_to_cpu(stat_info->rmac_frms_q0);
6418         tmp_stats[i++] = le64_to_cpu(stat_info->rmac_frms_q1);
6419         tmp_stats[i++] = le64_to_cpu(stat_info->rmac_frms_q2);
6420         tmp_stats[i++] = le64_to_cpu(stat_info->rmac_frms_q3);
6421         tmp_stats[i++] = le64_to_cpu(stat_info->rmac_frms_q4);
6422         tmp_stats[i++] = le64_to_cpu(stat_info->rmac_frms_q5);
6423         tmp_stats[i++] = le64_to_cpu(stat_info->rmac_frms_q6);
6424         tmp_stats[i++] = le64_to_cpu(stat_info->rmac_frms_q7);
6425         tmp_stats[i++] = le16_to_cpu(stat_info->rmac_full_q0);
6426         tmp_stats[i++] = le16_to_cpu(stat_info->rmac_full_q1);
6427         tmp_stats[i++] = le16_to_cpu(stat_info->rmac_full_q2);
6428         tmp_stats[i++] = le16_to_cpu(stat_info->rmac_full_q3);
6429         tmp_stats[i++] = le16_to_cpu(stat_info->rmac_full_q4);
6430         tmp_stats[i++] = le16_to_cpu(stat_info->rmac_full_q5);
6431         tmp_stats[i++] = le16_to_cpu(stat_info->rmac_full_q6);
6432         tmp_stats[i++] = le16_to_cpu(stat_info->rmac_full_q7);
6433         tmp_stats[i++] =
6434                 (u64)le32_to_cpu(stat_info->rmac_pause_cnt_oflow) << 32 |
6435                 le32_to_cpu(stat_info->rmac_pause_cnt);
6436         tmp_stats[i++] = le64_to_cpu(stat_info->rmac_xgmii_data_err_cnt);
6437         tmp_stats[i++] = le64_to_cpu(stat_info->rmac_xgmii_ctrl_err_cnt);
6438         tmp_stats[i++] =
6439                 (u64)le32_to_cpu(stat_info->rmac_accepted_ip_oflow) << 32 |
6440                 le32_to_cpu(stat_info->rmac_accepted_ip);
6441         tmp_stats[i++] = le32_to_cpu(stat_info->rmac_err_tcp);
6442         tmp_stats[i++] = le32_to_cpu(stat_info->rd_req_cnt);
6443         tmp_stats[i++] = le32_to_cpu(stat_info->new_rd_req_cnt);
6444         tmp_stats[i++] = le32_to_cpu(stat_info->new_rd_req_rtry_cnt);
6445         tmp_stats[i++] = le32_to_cpu(stat_info->rd_rtry_cnt);
6446         tmp_stats[i++] = le32_to_cpu(stat_info->wr_rtry_rd_ack_cnt);
6447         tmp_stats[i++] = le32_to_cpu(stat_info->wr_req_cnt);
6448         tmp_stats[i++] = le32_to_cpu(stat_info->new_wr_req_cnt);
6449         tmp_stats[i++] = le32_to_cpu(stat_info->new_wr_req_rtry_cnt);
6450         tmp_stats[i++] = le32_to_cpu(stat_info->wr_rtry_cnt);
6451         tmp_stats[i++] = le32_to_cpu(stat_info->wr_disc_cnt);
6452         tmp_stats[i++] = le32_to_cpu(stat_info->rd_rtry_wr_ack_cnt);
6453         tmp_stats[i++] = le32_to_cpu(stat_info->txp_wr_cnt);
6454         tmp_stats[i++] = le32_to_cpu(stat_info->txd_rd_cnt);
6455         tmp_stats[i++] = le32_to_cpu(stat_info->txd_wr_cnt);
6456         tmp_stats[i++] = le32_to_cpu(stat_info->rxd_rd_cnt);
6457         tmp_stats[i++] = le32_to_cpu(stat_info->rxd_wr_cnt);
6458         tmp_stats[i++] = le32_to_cpu(stat_info->txf_rd_cnt);
6459         tmp_stats[i++] = le32_to_cpu(stat_info->rxf_wr_cnt);
6460
6461         /* Enhanced statistics exist only for Hercules */
6462         if(sp->device_type == XFRAME_II_DEVICE) {
6463                 tmp_stats[i++] =
6464                                 le64_to_cpu(stat_info->rmac_ttl_1519_4095_frms);
6465                 tmp_stats[i++] =
6466                                 le64_to_cpu(stat_info->rmac_ttl_4096_8191_frms);
6467                 tmp_stats[i++] =
6468                                 le64_to_cpu(stat_info->rmac_ttl_8192_max_frms);
6469                 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_ttl_gt_max_frms);
6470                 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_osized_alt_frms);
6471                 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_jabber_alt_frms);
6472                 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_gt_max_alt_frms);
6473                 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_vlan_frms);
6474                 tmp_stats[i++] = le32_to_cpu(stat_info->rmac_len_discard);
6475                 tmp_stats[i++] = le32_to_cpu(stat_info->rmac_fcs_discard);
6476                 tmp_stats[i++] = le32_to_cpu(stat_info->rmac_pf_discard);
6477                 tmp_stats[i++] = le32_to_cpu(stat_info->rmac_da_discard);
6478                 tmp_stats[i++] = le32_to_cpu(stat_info->rmac_red_discard);
6479                 tmp_stats[i++] = le32_to_cpu(stat_info->rmac_rts_discard);
6480                 tmp_stats[i++] = le32_to_cpu(stat_info->rmac_ingm_full_discard);
6481                 tmp_stats[i++] = le32_to_cpu(stat_info->link_fault_cnt);
6482         }
6483
6484         tmp_stats[i++] = 0;
6485         tmp_stats[i++] = stat_info->sw_stat.single_ecc_errs;
6486         tmp_stats[i++] = stat_info->sw_stat.double_ecc_errs;
6487         tmp_stats[i++] = stat_info->sw_stat.parity_err_cnt;
6488         tmp_stats[i++] = stat_info->sw_stat.serious_err_cnt;
6489         tmp_stats[i++] = stat_info->sw_stat.soft_reset_cnt;
6490         tmp_stats[i++] = stat_info->sw_stat.fifo_full_cnt;
6491         for (k = 0; k < MAX_RX_RINGS; k++)
6492                 tmp_stats[i++] = stat_info->sw_stat.ring_full_cnt[k];
6493         tmp_stats[i++] = stat_info->xpak_stat.alarm_transceiver_temp_high;
6494         tmp_stats[i++] = stat_info->xpak_stat.alarm_transceiver_temp_low;
6495         tmp_stats[i++] = stat_info->xpak_stat.alarm_laser_bias_current_high;
6496         tmp_stats[i++] = stat_info->xpak_stat.alarm_laser_bias_current_low;
6497         tmp_stats[i++] = stat_info->xpak_stat.alarm_laser_output_power_high;
6498         tmp_stats[i++] = stat_info->xpak_stat.alarm_laser_output_power_low;
6499         tmp_stats[i++] = stat_info->xpak_stat.warn_transceiver_temp_high;
6500         tmp_stats[i++] = stat_info->xpak_stat.warn_transceiver_temp_low;
6501         tmp_stats[i++] = stat_info->xpak_stat.warn_laser_bias_current_high;
6502         tmp_stats[i++] = stat_info->xpak_stat.warn_laser_bias_current_low;
6503         tmp_stats[i++] = stat_info->xpak_stat.warn_laser_output_power_high;
6504         tmp_stats[i++] = stat_info->xpak_stat.warn_laser_output_power_low;
6505         tmp_stats[i++] = stat_info->sw_stat.clubbed_frms_cnt;
6506         tmp_stats[i++] = stat_info->sw_stat.sending_both;
6507         tmp_stats[i++] = stat_info->sw_stat.outof_sequence_pkts;
6508         tmp_stats[i++] = stat_info->sw_stat.flush_max_pkts;
6509         if (stat_info->sw_stat.num_aggregations) {
6510                 u64 tmp = stat_info->sw_stat.sum_avg_pkts_aggregated;
6511                 int count = 0;
6512                 /*
6513                  * Since 64-bit divide does not work on all platforms,
6514                  * do repeated subtraction.
6515                  */
6516                 while (tmp >= stat_info->sw_stat.num_aggregations) {
6517                         tmp -= stat_info->sw_stat.num_aggregations;
6518                         count++;
6519                 }
6520                 tmp_stats[i++] = count;
6521         }
6522         else
6523                 tmp_stats[i++] = 0;
6524         tmp_stats[i++] = stat_info->sw_stat.mem_alloc_fail_cnt;
6525         tmp_stats[i++] = stat_info->sw_stat.pci_map_fail_cnt;
6526         tmp_stats[i++] = stat_info->sw_stat.watchdog_timer_cnt;
6527         tmp_stats[i++] = stat_info->sw_stat.mem_allocated;
6528         tmp_stats[i++] = stat_info->sw_stat.mem_freed;
6529         tmp_stats[i++] = stat_info->sw_stat.link_up_cnt;
6530         tmp_stats[i++] = stat_info->sw_stat.link_down_cnt;
6531         tmp_stats[i++] = stat_info->sw_stat.link_up_time;
6532         tmp_stats[i++] = stat_info->sw_stat.link_down_time;
6533
6534         tmp_stats[i++] = stat_info->sw_stat.tx_buf_abort_cnt;
6535         tmp_stats[i++] = stat_info->sw_stat.tx_desc_abort_cnt;
6536         tmp_stats[i++] = stat_info->sw_stat.tx_parity_err_cnt;
6537         tmp_stats[i++] = stat_info->sw_stat.tx_link_loss_cnt;
6538         tmp_stats[i++] = stat_info->sw_stat.tx_list_proc_err_cnt;
6539
6540         tmp_stats[i++] = stat_info->sw_stat.rx_parity_err_cnt;
6541         tmp_stats[i++] = stat_info->sw_stat.rx_abort_cnt;
6542         tmp_stats[i++] = stat_info->sw_stat.rx_parity_abort_cnt;
6543         tmp_stats[i++] = stat_info->sw_stat.rx_rda_fail_cnt;
6544         tmp_stats[i++] = stat_info->sw_stat.rx_unkn_prot_cnt;
6545         tmp_stats[i++] = stat_info->sw_stat.rx_fcs_err_cnt;
6546         tmp_stats[i++] = stat_info->sw_stat.rx_buf_size_err_cnt;
6547         tmp_stats[i++] = stat_info->sw_stat.rx_rxd_corrupt_cnt;
6548         tmp_stats[i++] = stat_info->sw_stat.rx_unkn_err_cnt;
6549         tmp_stats[i++] = stat_info->sw_stat.tda_err_cnt;
6550         tmp_stats[i++] = stat_info->sw_stat.pfc_err_cnt;
6551         tmp_stats[i++] = stat_info->sw_stat.pcc_err_cnt;
6552         tmp_stats[i++] = stat_info->sw_stat.tti_err_cnt;
6553         tmp_stats[i++] = stat_info->sw_stat.tpa_err_cnt;
6554         tmp_stats[i++] = stat_info->sw_stat.sm_err_cnt;
6555         tmp_stats[i++] = stat_info->sw_stat.lso_err_cnt;
6556         tmp_stats[i++] = stat_info->sw_stat.mac_tmac_err_cnt;
6557         tmp_stats[i++] = stat_info->sw_stat.mac_rmac_err_cnt;
6558         tmp_stats[i++] = stat_info->sw_stat.xgxs_txgxs_err_cnt;
6559         tmp_stats[i++] = stat_info->sw_stat.xgxs_rxgxs_err_cnt;
6560         tmp_stats[i++] = stat_info->sw_stat.rc_err_cnt;
6561         tmp_stats[i++] = stat_info->sw_stat.prc_pcix_err_cnt;
6562         tmp_stats[i++] = stat_info->sw_stat.rpa_err_cnt;
6563         tmp_stats[i++] = stat_info->sw_stat.rda_err_cnt;
6564         tmp_stats[i++] = stat_info->sw_stat.rti_err_cnt;
6565         tmp_stats[i++] = stat_info->sw_stat.mc_err_cnt;
6566 }
6567
6568 static int s2io_ethtool_get_regs_len(struct net_device *dev)
6569 {
6570         return (XENA_REG_SPACE);
6571 }
6572
6573
6574 static u32 s2io_ethtool_get_rx_csum(struct net_device * dev)
6575 {
6576         struct s2io_nic *sp = dev->priv;
6577
6578         return (sp->rx_csum);
6579 }
6580
6581 static int s2io_ethtool_set_rx_csum(struct net_device *dev, u32 data)
6582 {
6583         struct s2io_nic *sp = dev->priv;
6584
6585         if (data)
6586                 sp->rx_csum = 1;
6587         else
6588                 sp->rx_csum = 0;
6589
6590         return 0;
6591 }
6592
6593 static int s2io_get_eeprom_len(struct net_device *dev)
6594 {
6595         return (XENA_EEPROM_SPACE);
6596 }
6597
6598 static int s2io_get_sset_count(struct net_device *dev, int sset)
6599 {
6600         struct s2io_nic *sp = dev->priv;
6601
6602         switch (sset) {
6603         case ETH_SS_TEST:
6604                 return S2IO_TEST_LEN;
6605         case ETH_SS_STATS:
6606                 switch(sp->device_type) {
6607                 case XFRAME_I_DEVICE:
6608                         return XFRAME_I_STAT_LEN;
6609                 case XFRAME_II_DEVICE:
6610                         return XFRAME_II_STAT_LEN;
6611                 default:
6612                         return 0;
6613                 }
6614         default:
6615                 return -EOPNOTSUPP;
6616         }
6617 }
6618
6619 static void s2io_ethtool_get_strings(struct net_device *dev,
6620                                      u32 stringset, u8 * data)
6621 {
6622         int stat_size = 0;
6623         struct s2io_nic *sp = dev->priv;
6624
6625         switch (stringset) {
6626         case ETH_SS_TEST:
6627                 memcpy(data, s2io_gstrings, S2IO_STRINGS_LEN);
6628                 break;
6629         case ETH_SS_STATS:
6630                 stat_size = sizeof(ethtool_xena_stats_keys);
6631                 memcpy(data, &ethtool_xena_stats_keys,stat_size);
6632                 if(sp->device_type == XFRAME_II_DEVICE) {
6633                         memcpy(data + stat_size,
6634                                 &ethtool_enhanced_stats_keys,
6635                                 sizeof(ethtool_enhanced_stats_keys));
6636                         stat_size += sizeof(ethtool_enhanced_stats_keys);
6637                 }
6638
6639                 memcpy(data + stat_size, &ethtool_driver_stats_keys,
6640                         sizeof(ethtool_driver_stats_keys));
6641         }
6642 }
6643
6644 static int s2io_ethtool_op_set_tx_csum(struct net_device *dev, u32 data)
6645 {
6646         if (data)
6647                 dev->features |= NETIF_F_IP_CSUM;
6648         else
6649                 dev->features &= ~NETIF_F_IP_CSUM;
6650
6651         return 0;
6652 }
6653
6654 static u32 s2io_ethtool_op_get_tso(struct net_device *dev)
6655 {
6656         return (dev->features & NETIF_F_TSO) != 0;
6657 }
6658 static int s2io_ethtool_op_set_tso(struct net_device *dev, u32 data)
6659 {
6660         if (data)
6661                 dev->features |= (NETIF_F_TSO | NETIF_F_TSO6);
6662         else
6663                 dev->features &= ~(NETIF_F_TSO | NETIF_F_TSO6);
6664
6665         return 0;
6666 }
6667
6668 static const struct ethtool_ops netdev_ethtool_ops = {
6669         .get_settings = s2io_ethtool_gset,
6670         .set_settings = s2io_ethtool_sset,
6671         .get_drvinfo = s2io_ethtool_gdrvinfo,
6672         .get_regs_len = s2io_ethtool_get_regs_len,
6673         .get_regs = s2io_ethtool_gregs,
6674         .get_link = ethtool_op_get_link,
6675         .get_eeprom_len = s2io_get_eeprom_len,
6676         .get_eeprom = s2io_ethtool_geeprom,
6677         .set_eeprom = s2io_ethtool_seeprom,
6678         .get_ringparam = s2io_ethtool_gringparam,
6679         .get_pauseparam = s2io_ethtool_getpause_data,
6680         .set_pauseparam = s2io_ethtool_setpause_data,
6681         .get_rx_csum = s2io_ethtool_get_rx_csum,
6682         .set_rx_csum = s2io_ethtool_set_rx_csum,
6683         .set_tx_csum = s2io_ethtool_op_set_tx_csum,
6684         .set_sg = ethtool_op_set_sg,
6685         .get_tso = s2io_ethtool_op_get_tso,
6686         .set_tso = s2io_ethtool_op_set_tso,
6687         .set_ufo = ethtool_op_set_ufo,
6688         .self_test = s2io_ethtool_test,
6689         .get_strings = s2io_ethtool_get_strings,
6690         .phys_id = s2io_ethtool_idnic,
6691         .get_ethtool_stats = s2io_get_ethtool_stats,
6692         .get_sset_count = s2io_get_sset_count,
6693 };
6694
6695 /**
6696  *  s2io_ioctl - Entry point for the Ioctl
6697  *  @dev :  Device pointer.
6698  *  @ifr :  An IOCTL specefic structure, that can contain a pointer to
6699  *  a proprietary structure used to pass information to the driver.
6700  *  @cmd :  This is used to distinguish between the different commands that
6701  *  can be passed to the IOCTL functions.
6702  *  Description:
6703  *  Currently there are no special functionality supported in IOCTL, hence
6704  *  function always return EOPNOTSUPPORTED
6705  */
6706
6707 static int s2io_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
6708 {
6709         return -EOPNOTSUPP;
6710 }
6711
6712 /**
6713  *  s2io_change_mtu - entry point to change MTU size for the device.
6714  *   @dev : device pointer.
6715  *   @new_mtu : the new MTU size for the device.
6716  *   Description: A driver entry point to change MTU size for the device.
6717  *   Before changing the MTU the device must be stopped.
6718  *  Return value:
6719  *   0 on success and an appropriate (-)ve integer as defined in errno.h
6720  *   file on failure.
6721  */
6722
6723 static int s2io_change_mtu(struct net_device *dev, int new_mtu)
6724 {
6725         struct s2io_nic *sp = dev->priv;
6726         int ret = 0;
6727
6728         if ((new_mtu < MIN_MTU) || (new_mtu > S2IO_JUMBO_SIZE)) {
6729                 DBG_PRINT(ERR_DBG, "%s: MTU size is invalid.\n",
6730                           dev->name);
6731                 return -EPERM;
6732         }
6733
6734         dev->mtu = new_mtu;
6735         if (netif_running(dev)) {
6736                 s2io_stop_all_tx_queue(sp);
6737                 s2io_card_down(sp);
6738                 ret = s2io_card_up(sp);
6739                 if (ret) {
6740                         DBG_PRINT(ERR_DBG, "%s: Device bring up failed\n",
6741                                   __FUNCTION__);
6742                         return ret;
6743                 }
6744                 s2io_wake_all_tx_queue(sp);
6745         } else { /* Device is down */
6746                 struct XENA_dev_config __iomem *bar0 = sp->bar0;
6747                 u64 val64 = new_mtu;
6748
6749                 writeq(vBIT(val64, 2, 14), &bar0->rmac_max_pyld_len);
6750         }
6751
6752         return ret;
6753 }
6754
6755 /**
6756  * s2io_set_link - Set the LInk status
6757  * @data: long pointer to device private structue
6758  * Description: Sets the link status for the adapter
6759  */
6760
6761 static void s2io_set_link(struct work_struct *work)
6762 {
6763         struct s2io_nic *nic = container_of(work, struct s2io_nic, set_link_task);
6764         struct net_device *dev = nic->dev;
6765         struct XENA_dev_config __iomem *bar0 = nic->bar0;
6766         register u64 val64;
6767         u16 subid;
6768
6769         rtnl_lock();
6770
6771         if (!netif_running(dev))
6772                 goto out_unlock;
6773
6774         if (test_and_set_bit(__S2IO_STATE_LINK_TASK, &(nic->state))) {
6775                 /* The card is being reset, no point doing anything */
6776                 goto out_unlock;
6777         }
6778
6779         subid = nic->pdev->subsystem_device;
6780         if (s2io_link_fault_indication(nic) == MAC_RMAC_ERR_TIMER) {
6781                 /*
6782                  * Allow a small delay for the NICs self initiated
6783                  * cleanup to complete.
6784                  */
6785                 msleep(100);
6786         }
6787
6788         val64 = readq(&bar0->adapter_status);
6789         if (LINK_IS_UP(val64)) {
6790                 if (!(readq(&bar0->adapter_control) & ADAPTER_CNTL_EN)) {
6791                         if (verify_xena_quiescence(nic)) {
6792                                 val64 = readq(&bar0->adapter_control);
6793                                 val64 |= ADAPTER_CNTL_EN;
6794                                 writeq(val64, &bar0->adapter_control);
6795                                 if (CARDS_WITH_FAULTY_LINK_INDICATORS(
6796                                         nic->device_type, subid)) {
6797                                         val64 = readq(&bar0->gpio_control);
6798                                         val64 |= GPIO_CTRL_GPIO_0;
6799                                         writeq(val64, &bar0->gpio_control);
6800                                         val64 = readq(&bar0->gpio_control);
6801                                 } else {
6802                                         val64 |= ADAPTER_LED_ON;
6803                                         writeq(val64, &bar0->adapter_control);
6804                                 }
6805                                 nic->device_enabled_once = TRUE;
6806                         } else {
6807                                 DBG_PRINT(ERR_DBG, "%s: Error: ", dev->name);
6808                                 DBG_PRINT(ERR_DBG, "device is not Quiescent\n");
6809                                 s2io_stop_all_tx_queue(nic);
6810                         }
6811                 }
6812                 val64 = readq(&bar0->adapter_control);
6813                 val64 |= ADAPTER_LED_ON;
6814                 writeq(val64, &bar0->adapter_control);
6815                 s2io_link(nic, LINK_UP);
6816         } else {
6817                 if (CARDS_WITH_FAULTY_LINK_INDICATORS(nic->device_type,
6818                                                       subid)) {
6819                         val64 = readq(&bar0->gpio_control);
6820                         val64 &= ~GPIO_CTRL_GPIO_0;
6821                         writeq(val64, &bar0->gpio_control);
6822                         val64 = readq(&bar0->gpio_control);
6823                 }
6824                 /* turn off LED */
6825                 val64 = readq(&bar0->adapter_control);
6826                 val64 = val64 &(~ADAPTER_LED_ON);
6827                 writeq(val64, &bar0->adapter_control);
6828                 s2io_link(nic, LINK_DOWN);
6829         }
6830         clear_bit(__S2IO_STATE_LINK_TASK, &(nic->state));
6831
6832 out_unlock:
6833         rtnl_unlock();
6834 }
6835
6836 static int set_rxd_buffer_pointer(struct s2io_nic *sp, struct RxD_t *rxdp,
6837                                 struct buffAdd *ba,
6838                                 struct sk_buff **skb, u64 *temp0, u64 *temp1,
6839                                 u64 *temp2, int size)
6840 {
6841         struct net_device *dev = sp->dev;
6842         struct swStat *stats = &sp->mac_control.stats_info->sw_stat;
6843
6844         if ((sp->rxd_mode == RXD_MODE_1) && (rxdp->Host_Control == 0)) {
6845                 struct RxD1 *rxdp1 = (struct RxD1 *)rxdp;
6846                 /* allocate skb */
6847                 if (*skb) {
6848                         DBG_PRINT(INFO_DBG, "SKB is not NULL\n");
6849                         /*
6850                          * As Rx frame are not going to be processed,
6851                          * using same mapped address for the Rxd
6852                          * buffer pointer
6853                          */
6854                         rxdp1->Buffer0_ptr = *temp0;
6855                 } else {
6856                         *skb = dev_alloc_skb(size);
6857                         if (!(*skb)) {
6858                                 DBG_PRINT(INFO_DBG, "%s: Out of ", dev->name);
6859                                 DBG_PRINT(INFO_DBG, "memory to allocate ");
6860                                 DBG_PRINT(INFO_DBG, "1 buf mode SKBs\n");
6861                                 sp->mac_control.stats_info->sw_stat. \
6862                                         mem_alloc_fail_cnt++;
6863                                 return -ENOMEM ;
6864                         }
6865                         sp->mac_control.stats_info->sw_stat.mem_allocated
6866                                 += (*skb)->truesize;
6867                         /* storing the mapped addr in a temp variable
6868                          * such it will be used for next rxd whose
6869                          * Host Control is NULL
6870                          */
6871                         rxdp1->Buffer0_ptr = *temp0 =
6872                                 pci_map_single( sp->pdev, (*skb)->data,
6873                                         size - NET_IP_ALIGN,
6874                                         PCI_DMA_FROMDEVICE);
6875                         if( (rxdp1->Buffer0_ptr == 0) ||
6876                                 (rxdp1->Buffer0_ptr == DMA_ERROR_CODE)) {
6877                                 goto memalloc_failed;
6878                         }
6879                         rxdp->Host_Control = (unsigned long) (*skb);
6880                 }
6881         } else if ((sp->rxd_mode == RXD_MODE_3B) && (rxdp->Host_Control == 0)) {
6882                 struct RxD3 *rxdp3 = (struct RxD3 *)rxdp;
6883                 /* Two buffer Mode */
6884                 if (*skb) {
6885                         rxdp3->Buffer2_ptr = *temp2;
6886                         rxdp3->Buffer0_ptr = *temp0;
6887                         rxdp3->Buffer1_ptr = *temp1;
6888                 } else {
6889                         *skb = dev_alloc_skb(size);
6890                         if (!(*skb)) {
6891                                 DBG_PRINT(INFO_DBG, "%s: Out of ", dev->name);
6892                                 DBG_PRINT(INFO_DBG, "memory to allocate ");
6893                                 DBG_PRINT(INFO_DBG, "2 buf mode SKBs\n");
6894                                 sp->mac_control.stats_info->sw_stat. \
6895                                         mem_alloc_fail_cnt++;
6896                                 return -ENOMEM;
6897                         }
6898                         sp->mac_control.stats_info->sw_stat.mem_allocated
6899                                 += (*skb)->truesize;
6900                         rxdp3->Buffer2_ptr = *temp2 =
6901                                 pci_map_single(sp->pdev, (*skb)->data,
6902                                                dev->mtu + 4,
6903                                                PCI_DMA_FROMDEVICE);
6904                         if( (rxdp3->Buffer2_ptr == 0) ||
6905                                 (rxdp3->Buffer2_ptr == DMA_ERROR_CODE)) {
6906                                 goto memalloc_failed;
6907                         }
6908                         rxdp3->Buffer0_ptr = *temp0 =
6909                                 pci_map_single( sp->pdev, ba->ba_0, BUF0_LEN,
6910                                                 PCI_DMA_FROMDEVICE);
6911                         if( (rxdp3->Buffer0_ptr == 0) ||
6912                                 (rxdp3->Buffer0_ptr == DMA_ERROR_CODE)) {
6913                                 pci_unmap_single (sp->pdev,
6914                                         (dma_addr_t)rxdp3->Buffer2_ptr,
6915                                         dev->mtu + 4, PCI_DMA_FROMDEVICE);
6916                                 goto memalloc_failed;
6917                         }
6918                         rxdp->Host_Control = (unsigned long) (*skb);
6919
6920                         /* Buffer-1 will be dummy buffer not used */
6921                         rxdp3->Buffer1_ptr = *temp1 =
6922                                 pci_map_single(sp->pdev, ba->ba_1, BUF1_LEN,
6923                                                 PCI_DMA_FROMDEVICE);
6924                         if( (rxdp3->Buffer1_ptr == 0) ||
6925                                 (rxdp3->Buffer1_ptr == DMA_ERROR_CODE)) {
6926                                 pci_unmap_single (sp->pdev,
6927                                         (dma_addr_t)rxdp3->Buffer0_ptr,
6928                                         BUF0_LEN, PCI_DMA_FROMDEVICE);
6929                                 pci_unmap_single (sp->pdev,
6930                                         (dma_addr_t)rxdp3->Buffer2_ptr,
6931                                         dev->mtu + 4, PCI_DMA_FROMDEVICE);
6932                                 goto memalloc_failed;
6933                         }
6934                 }
6935         }
6936         return 0;
6937         memalloc_failed:
6938                 stats->pci_map_fail_cnt++;
6939                 stats->mem_freed += (*skb)->truesize;
6940                 dev_kfree_skb(*skb);
6941                 return -ENOMEM;
6942 }
6943
6944 static void set_rxd_buffer_size(struct s2io_nic *sp, struct RxD_t *rxdp,
6945                                 int size)
6946 {
6947         struct net_device *dev = sp->dev;
6948         if (sp->rxd_mode == RXD_MODE_1) {
6949                 rxdp->Control_2 = SET_BUFFER0_SIZE_1( size - NET_IP_ALIGN);
6950         } else if (sp->rxd_mode == RXD_MODE_3B) {
6951                 rxdp->Control_2 = SET_BUFFER0_SIZE_3(BUF0_LEN);
6952                 rxdp->Control_2 |= SET_BUFFER1_SIZE_3(1);
6953                 rxdp->Control_2 |= SET_BUFFER2_SIZE_3( dev->mtu + 4);
6954         }
6955 }
6956
6957 static  int rxd_owner_bit_reset(struct s2io_nic *sp)
6958 {
6959         int i, j, k, blk_cnt = 0, size;
6960         struct mac_info * mac_control = &sp->mac_control;
6961         struct config_param *config = &sp->config;
6962         struct net_device *dev = sp->dev;
6963         struct RxD_t *rxdp = NULL;
6964         struct sk_buff *skb = NULL;
6965         struct buffAdd *ba = NULL;
6966         u64 temp0_64 = 0, temp1_64 = 0, temp2_64 = 0;
6967
6968         /* Calculate the size based on ring mode */
6969         size = dev->mtu + HEADER_ETHERNET_II_802_3_SIZE +
6970                 HEADER_802_2_SIZE + HEADER_SNAP_SIZE;
6971         if (sp->rxd_mode == RXD_MODE_1)
6972                 size += NET_IP_ALIGN;
6973         else if (sp->rxd_mode == RXD_MODE_3B)
6974                 size = dev->mtu + ALIGN_SIZE + BUF0_LEN + 4;
6975
6976         for (i = 0; i < config->rx_ring_num; i++) {
6977                 blk_cnt = config->rx_cfg[i].num_rxd /
6978                         (rxd_count[sp->rxd_mode] +1);
6979
6980                 for (j = 0; j < blk_cnt; j++) {
6981                         for (k = 0; k < rxd_count[sp->rxd_mode]; k++) {
6982                                 rxdp = mac_control->rings[i].
6983                                         rx_blocks[j].rxds[k].virt_addr;
6984                                 if(sp->rxd_mode == RXD_MODE_3B)
6985                                         ba = &mac_control->rings[i].ba[j][k];
6986                                 if (set_rxd_buffer_pointer(sp, rxdp, ba,
6987                                                        &skb,(u64 *)&temp0_64,
6988                                                        (u64 *)&temp1_64,
6989                                                        (u64 *)&temp2_64,
6990                                                         size) == ENOMEM) {
6991                                         return 0;
6992                                 }
6993
6994                                 set_rxd_buffer_size(sp, rxdp, size);
6995                                 wmb();
6996                                 /* flip the Ownership bit to Hardware */
6997                                 rxdp->Control_1 |= RXD_OWN_XENA;
6998                         }
6999                 }
7000         }
7001         return 0;
7002
7003 }
7004
7005 static int s2io_add_isr(struct s2io_nic * sp)
7006 {
7007         int ret = 0;
7008         struct net_device *dev = sp->dev;
7009         int err = 0;
7010
7011         if (sp->config.intr_type == MSI_X)
7012                 ret = s2io_enable_msi_x(sp);
7013         if (ret) {
7014                 DBG_PRINT(ERR_DBG, "%s: Defaulting to INTA\n", dev->name);
7015                 sp->config.intr_type = INTA;
7016         }
7017
7018         /* Store the values of the MSIX table in the struct s2io_nic structure */
7019         store_xmsi_data(sp);
7020
7021         /* After proper initialization of H/W, register ISR */
7022         if (sp->config.intr_type == MSI_X) {
7023                 int i, msix_rx_cnt = 0;
7024
7025                 for (i = 0; (sp->s2io_entries[i].in_use == MSIX_FLG); i++) {
7026                         if (sp->s2io_entries[i].type ==
7027                                         MSIX_RING_TYPE) {
7028                                         sprintf(sp->desc[i], "%s:MSI-X-%d-RX",
7029                                                 dev->name, i);
7030                                         err = request_irq(sp->entries[i].vector,
7031                                                 s2io_msix_ring_handle, 0,
7032                                                 sp->desc[i],
7033                                                 sp->s2io_entries[i].arg);
7034                                 } else if (sp->s2io_entries[i].type ==
7035                                         MSIX_ALARM_TYPE) {
7036                                         sprintf(sp->desc[i], "%s:MSI-X-%d-TX",
7037                                         dev->name, i);
7038                                         err = request_irq(sp->entries[i].vector,
7039                                                 s2io_msix_fifo_handle, 0,
7040                                                 sp->desc[i],
7041                                                 sp->s2io_entries[i].arg);
7042
7043                                 }
7044                                 /* if either data or addr is zero print it. */
7045                                 if (!(sp->msix_info[i].addr &&
7046                                         sp->msix_info[i].data)) {
7047                                         DBG_PRINT(ERR_DBG,
7048                                                 "%s @Addr:0x%llx Data:0x%llx\n",
7049                                                 sp->desc[i],
7050                                                 (unsigned long long)
7051                                                 sp->msix_info[i].addr,
7052                                                 (unsigned long long)
7053                                                 ntohl(sp->msix_info[i].data));
7054                                 } else
7055                                         msix_rx_cnt++;
7056                                 if (err) {
7057                                         remove_msix_isr(sp);
7058
7059                                         DBG_PRINT(ERR_DBG,
7060                                                 "%s:MSI-X-%d registration "
7061                                                 "failed\n", dev->name, i);
7062
7063                                         DBG_PRINT(ERR_DBG,
7064                                                 "%s: Defaulting to INTA\n",
7065                                                 dev->name);
7066                                         sp->config.intr_type = INTA;
7067                                         break;
7068                                 }
7069                                 sp->s2io_entries[i].in_use =
7070                                         MSIX_REGISTERED_SUCCESS;
7071
7072                 }
7073                 if (!err) {
7074                         printk(KERN_INFO "MSI-X-RX %d entries enabled\n",
7075                                 --msix_rx_cnt);
7076                         DBG_PRINT(INFO_DBG, "MSI-X-TX entries enabled"
7077                                                 " through alarm vector\n");
7078                 }
7079         }
7080         if (sp->config.intr_type == INTA) {
7081                 err = request_irq((int) sp->pdev->irq, s2io_isr, IRQF_SHARED,
7082                                 sp->name, dev);
7083                 if (err) {
7084                         DBG_PRINT(ERR_DBG, "%s: ISR registration failed\n",
7085                                   dev->name);
7086                         return -1;
7087                 }
7088         }
7089         return 0;
7090 }
7091 static void s2io_rem_isr(struct s2io_nic * sp)
7092 {
7093         if (sp->config.intr_type == MSI_X)
7094                 remove_msix_isr(sp);
7095         else
7096                 remove_inta_isr(sp);
7097 }
7098
7099 static void do_s2io_card_down(struct s2io_nic * sp, int do_io)
7100 {
7101         int cnt = 0;
7102         struct XENA_dev_config __iomem *bar0 = sp->bar0;
7103         register u64 val64 = 0;
7104         struct config_param *config;
7105         config = &sp->config;
7106
7107         if (!is_s2io_card_up(sp))
7108                 return;
7109
7110         del_timer_sync(&sp->alarm_timer);
7111         /* If s2io_set_link task is executing, wait till it completes. */
7112         while (test_and_set_bit(__S2IO_STATE_LINK_TASK, &(sp->state))) {
7113                 msleep(50);
7114         }
7115         clear_bit(__S2IO_STATE_CARD_UP, &sp->state);
7116
7117         /* Disable napi */
7118         if (config->napi)
7119                 napi_disable(&sp->napi);
7120
7121         /* disable Tx and Rx traffic on the NIC */
7122         if (do_io)
7123                 stop_nic(sp);
7124
7125         s2io_rem_isr(sp);
7126
7127         /* Check if the device is Quiescent and then Reset the NIC */
7128         while(do_io) {
7129                 /* As per the HW requirement we need to replenish the
7130                  * receive buffer to avoid the ring bump. Since there is
7131                  * no intention of processing the Rx frame at this pointwe are
7132                  * just settting the ownership bit of rxd in Each Rx
7133                  * ring to HW and set the appropriate buffer size
7134                  * based on the ring mode
7135                  */
7136                 rxd_owner_bit_reset(sp);
7137
7138                 val64 = readq(&bar0->adapter_status);
7139                 if (verify_xena_quiescence(sp)) {
7140                         if(verify_pcc_quiescent(sp, sp->device_enabled_once))
7141                         break;
7142                 }
7143
7144                 msleep(50);
7145                 cnt++;
7146                 if (cnt == 10) {
7147                         DBG_PRINT(ERR_DBG,
7148                                   "s2io_close:Device not Quiescent ");
7149                         DBG_PRINT(ERR_DBG, "adaper status reads 0x%llx\n",
7150                                   (unsigned long long) val64);
7151                         break;
7152                 }
7153         }
7154         if (do_io)
7155                 s2io_reset(sp);
7156
7157         /* Free all Tx buffers */
7158         free_tx_buffers(sp);
7159
7160         /* Free all Rx buffers */
7161         free_rx_buffers(sp);
7162
7163         clear_bit(__S2IO_STATE_LINK_TASK, &(sp->state));
7164 }
7165
7166 static void s2io_card_down(struct s2io_nic * sp)
7167 {
7168         do_s2io_card_down(sp, 1);
7169 }
7170
7171 static int s2io_card_up(struct s2io_nic * sp)
7172 {
7173         int i, ret = 0;
7174         struct mac_info *mac_control;
7175         struct config_param *config;
7176         struct net_device *dev = (struct net_device *) sp->dev;
7177         u16 interruptible;
7178
7179         /* Initialize the H/W I/O registers */
7180         ret = init_nic(sp);
7181         if (ret != 0) {
7182                 DBG_PRINT(ERR_DBG, "%s: H/W initialization failed\n",
7183                           dev->name);
7184                 if (ret != -EIO)
7185                         s2io_reset(sp);
7186                 return ret;
7187         }
7188
7189         /*
7190          * Initializing the Rx buffers. For now we are considering only 1
7191          * Rx ring and initializing buffers into 30 Rx blocks
7192          */
7193         mac_control = &sp->mac_control;
7194         config = &sp->config;
7195
7196         for (i = 0; i < config->rx_ring_num; i++) {
7197                 mac_control->rings[i].mtu = dev->mtu;
7198                 ret = fill_rx_buffers(&mac_control->rings[i]);
7199                 if (ret) {
7200                         DBG_PRINT(ERR_DBG, "%s: Out of memory in Open\n",
7201                                   dev->name);
7202                         s2io_reset(sp);
7203                         free_rx_buffers(sp);
7204                         return -ENOMEM;
7205                 }
7206                 DBG_PRINT(INFO_DBG, "Buf in ring:%d is %d:\n", i,
7207                           mac_control->rings[i].rx_bufs_left);
7208         }
7209
7210         /* Initialise napi */
7211         if (config->napi)
7212                 napi_enable(&sp->napi);
7213
7214         /* Maintain the state prior to the open */
7215         if (sp->promisc_flg)
7216                 sp->promisc_flg = 0;
7217         if (sp->m_cast_flg) {
7218                 sp->m_cast_flg = 0;
7219                 sp->all_multi_pos= 0;
7220         }
7221
7222         /* Setting its receive mode */
7223         s2io_set_multicast(dev);
7224
7225         if (sp->lro) {
7226                 /* Initialize max aggregatable pkts per session based on MTU */
7227                 sp->lro_max_aggr_per_sess = ((1<<16) - 1) / dev->mtu;
7228                 /* Check if we can use(if specified) user provided value */
7229                 if (lro_max_pkts < sp->lro_max_aggr_per_sess)
7230                         sp->lro_max_aggr_per_sess = lro_max_pkts;
7231         }
7232
7233         /* Enable Rx Traffic and interrupts on the NIC */
7234         if (start_nic(sp)) {
7235                 DBG_PRINT(ERR_DBG, "%s: Starting NIC failed\n", dev->name);
7236                 s2io_reset(sp);
7237                 free_rx_buffers(sp);
7238                 return -ENODEV;
7239         }
7240
7241         /* Add interrupt service routine */
7242         if (s2io_add_isr(sp) != 0) {
7243                 if (sp->config.intr_type == MSI_X)
7244                         s2io_rem_isr(sp);
7245                 s2io_reset(sp);
7246                 free_rx_buffers(sp);
7247                 return -ENODEV;
7248         }
7249
7250         S2IO_TIMER_CONF(sp->alarm_timer, s2io_alarm_handle, sp, (HZ/2));
7251
7252         /*  Enable select interrupts */
7253         en_dis_err_alarms(sp, ENA_ALL_INTRS, ENABLE_INTRS);
7254         if (sp->config.intr_type != INTA)
7255                 en_dis_able_nic_intrs(sp, TX_TRAFFIC_INTR, ENABLE_INTRS);
7256         else {
7257                 interruptible = TX_TRAFFIC_INTR | RX_TRAFFIC_INTR;
7258                 interruptible |= TX_PIC_INTR;
7259                 en_dis_able_nic_intrs(sp, interruptible, ENABLE_INTRS);
7260         }
7261
7262         set_bit(__S2IO_STATE_CARD_UP, &sp->state);
7263         return 0;
7264 }
7265
7266 /**
7267  * s2io_restart_nic - Resets the NIC.
7268  * @data : long pointer to the device private structure
7269  * Description:
7270  * This function is scheduled to be run by the s2io_tx_watchdog
7271  * function after 0.5 secs to reset the NIC. The idea is to reduce
7272  * the run time of the watch dog routine which is run holding a
7273  * spin lock.
7274  */
7275
7276 static void s2io_restart_nic(struct work_struct *work)
7277 {
7278         struct s2io_nic *sp = container_of(work, struct s2io_nic, rst_timer_task);
7279         struct net_device *dev = sp->dev;
7280
7281         rtnl_lock();
7282
7283         if (!netif_running(dev))
7284                 goto out_unlock;
7285
7286         s2io_card_down(sp);
7287         if (s2io_card_up(sp)) {
7288                 DBG_PRINT(ERR_DBG, "%s: Device bring up failed\n",
7289                           dev->name);
7290         }
7291         s2io_wake_all_tx_queue(sp);
7292         DBG_PRINT(ERR_DBG, "%s: was reset by Tx watchdog timer\n",
7293                   dev->name);
7294 out_unlock:
7295         rtnl_unlock();
7296 }
7297
7298 /**
7299  *  s2io_tx_watchdog - Watchdog for transmit side.
7300  *  @dev : Pointer to net device structure
7301  *  Description:
7302  *  This function is triggered if the Tx Queue is stopped
7303  *  for a pre-defined amount of time when the Interface is still up.
7304  *  If the Interface is jammed in such a situation, the hardware is
7305  *  reset (by s2io_close) and restarted again (by s2io_open) to
7306  *  overcome any problem that might have been caused in the hardware.
7307  *  Return value:
7308  *  void
7309  */
7310
7311 static void s2io_tx_watchdog(struct net_device *dev)
7312 {
7313         struct s2io_nic *sp = dev->priv;
7314
7315         if (netif_carrier_ok(dev)) {
7316                 sp->mac_control.stats_info->sw_stat.watchdog_timer_cnt++;
7317                 schedule_work(&sp->rst_timer_task);
7318                 sp->mac_control.stats_info->sw_stat.soft_reset_cnt++;
7319         }
7320 }
7321
7322 /**
7323  *   rx_osm_handler - To perform some OS related operations on SKB.
7324  *   @sp: private member of the device structure,pointer to s2io_nic structure.
7325  *   @skb : the socket buffer pointer.
7326  *   @len : length of the packet
7327  *   @cksum : FCS checksum of the frame.
7328  *   @ring_no : the ring from which this RxD was extracted.
7329  *   Description:
7330  *   This function is called by the Rx interrupt serivce routine to perform
7331  *   some OS related operations on the SKB before passing it to the upper
7332  *   layers. It mainly checks if the checksum is OK, if so adds it to the
7333  *   SKBs cksum variable, increments the Rx packet count and passes the SKB
7334  *   to the upper layer. If the checksum is wrong, it increments the Rx
7335  *   packet error count, frees the SKB and returns error.
7336  *   Return value:
7337  *   SUCCESS on success and -1 on failure.
7338  */
7339 static int rx_osm_handler(struct ring_info *ring_data, struct RxD_t * rxdp)
7340 {
7341         struct s2io_nic *sp = ring_data->nic;
7342         struct net_device *dev = (struct net_device *) ring_data->dev;
7343         struct sk_buff *skb = (struct sk_buff *)
7344                 ((unsigned long) rxdp->Host_Control);
7345         int ring_no = ring_data->ring_no;
7346         u16 l3_csum, l4_csum;
7347         unsigned long long err = rxdp->Control_1 & RXD_T_CODE;
7348         struct lro *lro;
7349         u8 err_mask;
7350
7351         skb->dev = dev;
7352
7353         if (err) {
7354                 /* Check for parity error */
7355                 if (err & 0x1) {
7356                         sp->mac_control.stats_info->sw_stat.parity_err_cnt++;
7357                 }
7358                 err_mask = err >> 48;
7359                 switch(err_mask) {
7360                         case 1:
7361                                 sp->mac_control.stats_info->sw_stat.
7362                                 rx_parity_err_cnt++;
7363                         break;
7364
7365                         case 2:
7366                                 sp->mac_control.stats_info->sw_stat.
7367                                 rx_abort_cnt++;
7368                         break;
7369
7370                         case 3:
7371                                 sp->mac_control.stats_info->sw_stat.
7372                                 rx_parity_abort_cnt++;
7373                         break;
7374
7375                         case 4:
7376                                 sp->mac_control.stats_info->sw_stat.
7377                                 rx_rda_fail_cnt++;
7378                         break;
7379
7380                         case 5:
7381                                 sp->mac_control.stats_info->sw_stat.
7382                                 rx_unkn_prot_cnt++;
7383                         break;
7384
7385                         case 6:
7386                                 sp->mac_control.stats_info->sw_stat.
7387                                 rx_fcs_err_cnt++;
7388                         break;
7389
7390                         case 7:
7391                                 sp->mac_control.stats_info->sw_stat.
7392                                 rx_buf_size_err_cnt++;
7393                         break;
7394
7395                         case 8:
7396                                 sp->mac_control.stats_info->sw_stat.
7397                                 rx_rxd_corrupt_cnt++;
7398                         break;
7399
7400                         case 15:
7401                                 sp->mac_control.stats_info->sw_stat.
7402                                 rx_unkn_err_cnt++;
7403                         break;
7404                 }
7405                 /*
7406                 * Drop the packet if bad transfer code. Exception being
7407                 * 0x5, which could be due to unsupported IPv6 extension header.
7408                 * In this case, we let stack handle the packet.
7409                 * Note that in this case, since checksum will be incorrect,
7410                 * stack will validate the same.
7411                 */
7412                 if (err_mask != 0x5) {
7413                         DBG_PRINT(ERR_DBG, "%s: Rx error Value: 0x%x\n",
7414                                 dev->name, err_mask);
7415                         sp->stats.rx_crc_errors++;
7416                         sp->mac_control.stats_info->sw_stat.mem_freed
7417                                 += skb->truesize;
7418                         dev_kfree_skb(skb);
7419                         ring_data->rx_bufs_left -= 1;
7420                         rxdp->Host_Control = 0;
7421                         return 0;
7422                 }
7423         }
7424
7425         /* Updating statistics */
7426         ring_data->rx_packets++;
7427         rxdp->Host_Control = 0;
7428         if (sp->rxd_mode == RXD_MODE_1) {
7429                 int len = RXD_GET_BUFFER0_SIZE_1(rxdp->Control_2);
7430
7431                 ring_data->rx_bytes += len;
7432                 skb_put(skb, len);
7433
7434         } else if (sp->rxd_mode == RXD_MODE_3B) {
7435                 int get_block = ring_data->rx_curr_get_info.block_index;
7436                 int get_off = ring_data->rx_curr_get_info.offset;
7437                 int buf0_len = RXD_GET_BUFFER0_SIZE_3(rxdp->Control_2);
7438                 int buf2_len = RXD_GET_BUFFER2_SIZE_3(rxdp->Control_2);
7439                 unsigned char *buff = skb_push(skb, buf0_len);
7440
7441                 struct buffAdd *ba = &ring_data->ba[get_block][get_off];
7442                 ring_data->rx_bytes += buf0_len + buf2_len;
7443                 memcpy(buff, ba->ba_0, buf0_len);
7444                 skb_put(skb, buf2_len);
7445         }
7446
7447         if ((rxdp->Control_1 & TCP_OR_UDP_FRAME) && ((!ring_data->lro) ||
7448             (ring_data->lro && (!(rxdp->Control_1 & RXD_FRAME_IP_FRAG)))) &&
7449             (sp->rx_csum)) {
7450                 l3_csum = RXD_GET_L3_CKSUM(rxdp->Control_1);
7451                 l4_csum = RXD_GET_L4_CKSUM(rxdp->Control_1);
7452                 if ((l3_csum == L3_CKSUM_OK) && (l4_csum == L4_CKSUM_OK)) {
7453                         /*
7454                          * NIC verifies if the Checksum of the received
7455                          * frame is Ok or not and accordingly returns
7456                          * a flag in the RxD.
7457                          */
7458                         skb->ip_summed = CHECKSUM_UNNECESSARY;
7459                         if (ring_data->lro) {
7460                                 u32 tcp_len;
7461                                 u8 *tcp;
7462                                 int ret = 0;
7463
7464                                 ret = s2io_club_tcp_session(ring_data,
7465                                         skb->data, &tcp, &tcp_len, &lro,
7466                                         rxdp, sp);
7467                                 switch (ret) {
7468                                         case 3: /* Begin anew */
7469                                                 lro->parent = skb;
7470                                                 goto aggregate;
7471                                         case 1: /* Aggregate */
7472                                         {
7473                                                 lro_append_pkt(sp, lro,
7474                                                         skb, tcp_len);
7475                                                 goto aggregate;
7476                                         }
7477                                         case 4: /* Flush session */
7478                                         {
7479                                                 lro_append_pkt(sp, lro,
7480                                                         skb, tcp_len);
7481                                                 queue_rx_frame(lro->parent,
7482                                                         lro->vlan_tag);
7483                                                 clear_lro_session(lro);
7484                                                 sp->mac_control.stats_info->
7485                                                     sw_stat.flush_max_pkts++;
7486                                                 goto aggregate;
7487                                         }
7488                                         case 2: /* Flush both */
7489                                                 lro->parent->data_len =
7490                                                         lro->frags_len;
7491                                                 sp->mac_control.stats_info->
7492                                                      sw_stat.sending_both++;
7493                                                 queue_rx_frame(lro->parent,
7494                                                         lro->vlan_tag);
7495                                                 clear_lro_session(lro);
7496                                                 goto send_up;
7497                                         case 0: /* sessions exceeded */
7498                                         case -1: /* non-TCP or not
7499                                                   * L2 aggregatable
7500                                                   */
7501                                         case 5: /*
7502                                                  * First pkt in session not
7503                                                  * L3/L4 aggregatable
7504                                                  */
7505                                                 break;
7506                                         default:
7507                                                 DBG_PRINT(ERR_DBG,
7508                                                         "%s: Samadhana!!\n",
7509                                                          __FUNCTION__);
7510                                                 BUG();
7511                                 }
7512                         }
7513                 } else {
7514                         /*
7515                          * Packet with erroneous checksum, let the
7516                          * upper layers deal with it.
7517                          */
7518                         skb->ip_summed = CHECKSUM_NONE;
7519                 }
7520         } else
7521                 skb->ip_summed = CHECKSUM_NONE;
7522
7523         sp->mac_control.stats_info->sw_stat.mem_freed += skb->truesize;
7524 send_up:
7525         queue_rx_frame(skb, RXD_GET_VLAN_TAG(rxdp->Control_2));
7526         dev->last_rx = jiffies;
7527 aggregate:
7528         sp->mac_control.rings[ring_no].rx_bufs_left -= 1;
7529         return SUCCESS;
7530 }
7531
7532 /**
7533  *  s2io_link - stops/starts the Tx queue.
7534  *  @sp : private member of the device structure, which is a pointer to the
7535  *  s2io_nic structure.
7536  *  @link : inidicates whether link is UP/DOWN.
7537  *  Description:
7538  *  This function stops/starts the Tx queue depending on whether the link
7539  *  status of the NIC is is down or up. This is called by the Alarm
7540  *  interrupt handler whenever a link change interrupt comes up.
7541  *  Return value:
7542  *  void.
7543  */
7544
7545 static void s2io_link(struct s2io_nic * sp, int link)
7546 {
7547         struct net_device *dev = (struct net_device *) sp->dev;
7548
7549         if (link != sp->last_link_state) {
7550                 init_tti(sp, link);
7551                 if (link == LINK_DOWN) {
7552                         DBG_PRINT(ERR_DBG, "%s: Link down\n", dev->name);
7553                         s2io_stop_all_tx_queue(sp);
7554                         netif_carrier_off(dev);
7555                         if(sp->mac_control.stats_info->sw_stat.link_up_cnt)
7556                         sp->mac_control.stats_info->sw_stat.link_up_time =
7557                                 jiffies - sp->start_time;
7558                         sp->mac_control.stats_info->sw_stat.link_down_cnt++;
7559                 } else {
7560                         DBG_PRINT(ERR_DBG, "%s: Link Up\n", dev->name);
7561                         if (sp->mac_control.stats_info->sw_stat.link_down_cnt)
7562                         sp->mac_control.stats_info->sw_stat.link_down_time =
7563                                 jiffies - sp->start_time;
7564                         sp->mac_control.stats_info->sw_stat.link_up_cnt++;
7565                         netif_carrier_on(dev);
7566                         s2io_wake_all_tx_queue(sp);
7567                 }
7568         }
7569         sp->last_link_state = link;
7570         sp->start_time = jiffies;
7571 }
7572
7573 /**
7574  *  s2io_init_pci -Initialization of PCI and PCI-X configuration registers .
7575  *  @sp : private member of the device structure, which is a pointer to the
7576  *  s2io_nic structure.
7577  *  Description:
7578  *  This function initializes a few of the PCI and PCI-X configuration registers
7579  *  with recommended values.
7580  *  Return value:
7581  *  void
7582  */
7583
7584 static void s2io_init_pci(struct s2io_nic * sp)
7585 {
7586         u16 pci_cmd = 0, pcix_cmd = 0;
7587
7588         /* Enable Data Parity Error Recovery in PCI-X command register. */
7589         pci_read_config_word(sp->pdev, PCIX_COMMAND_REGISTER,
7590                              &(pcix_cmd));
7591         pci_write_config_word(sp->pdev, PCIX_COMMAND_REGISTER,
7592                               (pcix_cmd | 1));
7593         pci_read_config_word(sp->pdev, PCIX_COMMAND_REGISTER,
7594                              &(pcix_cmd));
7595
7596         /* Set the PErr Response bit in PCI command register. */
7597         pci_read_config_word(sp->pdev, PCI_COMMAND, &pci_cmd);
7598         pci_write_config_word(sp->pdev, PCI_COMMAND,
7599                               (pci_cmd | PCI_COMMAND_PARITY));
7600         pci_read_config_word(sp->pdev, PCI_COMMAND, &pci_cmd);
7601 }
7602
7603 static int s2io_verify_parm(struct pci_dev *pdev, u8 *dev_intr_type,
7604         u8 *dev_multiq)
7605 {
7606         if ((tx_fifo_num > MAX_TX_FIFOS) ||
7607                 (tx_fifo_num < 1)) {
7608                 DBG_PRINT(ERR_DBG, "s2io: Requested number of tx fifos "
7609                         "(%d) not supported\n", tx_fifo_num);
7610
7611                 if (tx_fifo_num < 1)
7612                         tx_fifo_num = 1;
7613                 else
7614                         tx_fifo_num = MAX_TX_FIFOS;
7615
7616                 DBG_PRINT(ERR_DBG, "s2io: Default to %d ", tx_fifo_num);
7617                 DBG_PRINT(ERR_DBG, "tx fifos\n");
7618         }
7619
7620 #ifndef CONFIG_NETDEVICES_MULTIQUEUE
7621         if (multiq) {
7622                 DBG_PRINT(ERR_DBG, "s2io: Multiqueue support not enabled\n");
7623                 multiq = 0;
7624         }
7625 #endif
7626         if (multiq)
7627                 *dev_multiq = multiq;
7628
7629         if (tx_steering_type && (1 == tx_fifo_num)) {
7630                 if (tx_steering_type != TX_DEFAULT_STEERING)
7631                         DBG_PRINT(ERR_DBG,
7632                                 "s2io: Tx steering is not supported with "
7633                                 "one fifo. Disabling Tx steering.\n");
7634                 tx_steering_type = NO_STEERING;
7635         }
7636
7637         if ((tx_steering_type < NO_STEERING) ||
7638                 (tx_steering_type > TX_DEFAULT_STEERING)) {
7639                 DBG_PRINT(ERR_DBG, "s2io: Requested transmit steering not "
7640                          "supported\n");
7641                 DBG_PRINT(ERR_DBG, "s2io: Disabling transmit steering\n");
7642                 tx_steering_type = NO_STEERING;
7643         }
7644
7645         if (rx_ring_num > MAX_RX_RINGS) {
7646                 DBG_PRINT(ERR_DBG, "s2io: Requested number of rx rings not "
7647                          "supported\n");
7648                 DBG_PRINT(ERR_DBG, "s2io: Default to %d rx rings\n",
7649                         MAX_RX_RINGS);
7650                 rx_ring_num = MAX_RX_RINGS;
7651         }
7652
7653         if (*dev_intr_type != INTA)
7654                 napi = 0;
7655
7656         if ((*dev_intr_type != INTA) && (*dev_intr_type != MSI_X)) {
7657                 DBG_PRINT(ERR_DBG, "s2io: Wrong intr_type requested. "
7658                           "Defaulting to INTA\n");
7659                 *dev_intr_type = INTA;
7660         }
7661
7662         if ((*dev_intr_type == MSI_X) &&
7663                         ((pdev->device != PCI_DEVICE_ID_HERC_WIN) &&
7664                         (pdev->device != PCI_DEVICE_ID_HERC_UNI))) {
7665                 DBG_PRINT(ERR_DBG, "s2io: Xframe I does not support MSI_X. "
7666                                         "Defaulting to INTA\n");
7667                 *dev_intr_type = INTA;
7668         }
7669
7670         if ((rx_ring_mode != 1) && (rx_ring_mode != 2)) {
7671                 DBG_PRINT(ERR_DBG, "s2io: Requested ring mode not supported\n");
7672                 DBG_PRINT(ERR_DBG, "s2io: Defaulting to 1-buffer mode\n");
7673                 rx_ring_mode = 1;
7674         }
7675         return SUCCESS;
7676 }
7677
7678 /**
7679  * rts_ds_steer - Receive traffic steering based on IPv4 or IPv6 TOS
7680  * or Traffic class respectively.
7681  * @nic: device private variable
7682  * Description: The function configures the receive steering to
7683  * desired receive ring.
7684  * Return Value:  SUCCESS on success and
7685  * '-1' on failure (endian settings incorrect).
7686  */
7687 static int rts_ds_steer(struct s2io_nic *nic, u8 ds_codepoint, u8 ring)
7688 {
7689         struct XENA_dev_config __iomem *bar0 = nic->bar0;
7690         register u64 val64 = 0;
7691
7692         if (ds_codepoint > 63)
7693                 return FAILURE;
7694
7695         val64 = RTS_DS_MEM_DATA(ring);
7696         writeq(val64, &bar0->rts_ds_mem_data);
7697
7698         val64 = RTS_DS_MEM_CTRL_WE |
7699                 RTS_DS_MEM_CTRL_STROBE_NEW_CMD |
7700                 RTS_DS_MEM_CTRL_OFFSET(ds_codepoint);
7701
7702         writeq(val64, &bar0->rts_ds_mem_ctrl);
7703
7704         return wait_for_cmd_complete(&bar0->rts_ds_mem_ctrl,
7705                                 RTS_DS_MEM_CTRL_STROBE_CMD_BEING_EXECUTED,
7706                                 S2IO_BIT_RESET);
7707 }
7708
7709 /**
7710  *  s2io_init_nic - Initialization of the adapter .
7711  *  @pdev : structure containing the PCI related information of the device.
7712  *  @pre: List of PCI devices supported by the driver listed in s2io_tbl.
7713  *  Description:
7714  *  The function initializes an adapter identified by the pci_dec structure.
7715  *  All OS related initialization including memory and device structure and
7716  *  initlaization of the device private variable is done. Also the swapper
7717  *  control register is initialized to enable read and write into the I/O
7718  *  registers of the device.
7719  *  Return value:
7720  *  returns 0 on success and negative on failure.
7721  */
7722
7723 static int __devinit
7724 s2io_init_nic(struct pci_dev *pdev, const struct pci_device_id *pre)
7725 {
7726         struct s2io_nic *sp;
7727         struct net_device *dev;
7728         int i, j, ret;
7729         int dma_flag = FALSE;
7730         u32 mac_up, mac_down;
7731         u64 val64 = 0, tmp64 = 0;
7732         struct XENA_dev_config __iomem *bar0 = NULL;
7733         u16 subid;
7734         struct mac_info *mac_control;
7735         struct config_param *config;
7736         int mode;
7737         u8 dev_intr_type = intr_type;
7738         u8 dev_multiq = 0;
7739         DECLARE_MAC_BUF(mac);
7740
7741         ret = s2io_verify_parm(pdev, &dev_intr_type, &dev_multiq);
7742         if (ret)
7743                 return ret;
7744
7745         if ((ret = pci_enable_device(pdev))) {
7746                 DBG_PRINT(ERR_DBG,
7747                           "s2io_init_nic: pci_enable_device failed\n");
7748                 return ret;
7749         }
7750
7751         if (!pci_set_dma_mask(pdev, DMA_64BIT_MASK)) {
7752                 DBG_PRINT(INIT_DBG, "s2io_init_nic: Using 64bit DMA\n");
7753                 dma_flag = TRUE;
7754                 if (pci_set_consistent_dma_mask
7755                     (pdev, DMA_64BIT_MASK)) {
7756                         DBG_PRINT(ERR_DBG,
7757                                   "Unable to obtain 64bit DMA for \
7758                                         consistent allocations\n");
7759                         pci_disable_device(pdev);
7760                         return -ENOMEM;
7761                 }
7762         } else if (!pci_set_dma_mask(pdev, DMA_32BIT_MASK)) {
7763                 DBG_PRINT(INIT_DBG, "s2io_init_nic: Using 32bit DMA\n");
7764         } else {
7765                 pci_disable_device(pdev);
7766                 return -ENOMEM;
7767         }
7768         if ((ret = pci_request_regions(pdev, s2io_driver_name))) {
7769                 DBG_PRINT(ERR_DBG, "%s: Request Regions failed - %x \n", __FUNCTION__, ret);
7770                 pci_disable_device(pdev);
7771                 return -ENODEV;
7772         }
7773 #ifdef CONFIG_NETDEVICES_MULTIQUEUE
7774         if (dev_multiq)
7775                 dev = alloc_etherdev_mq(sizeof(struct s2io_nic), tx_fifo_num);
7776         else
7777 #endif
7778         dev = alloc_etherdev(sizeof(struct s2io_nic));
7779         if (dev == NULL) {
7780                 DBG_PRINT(ERR_DBG, "Device allocation failed\n");
7781                 pci_disable_device(pdev);
7782                 pci_release_regions(pdev);
7783                 return -ENODEV;
7784         }
7785
7786         pci_set_master(pdev);
7787         pci_set_drvdata(pdev, dev);
7788         SET_NETDEV_DEV(dev, &pdev->dev);
7789
7790         /*  Private member variable initialized to s2io NIC structure */
7791         sp = dev->priv;
7792         memset(sp, 0, sizeof(struct s2io_nic));
7793         sp->dev = dev;
7794         sp->pdev = pdev;
7795         sp->high_dma_flag = dma_flag;
7796         sp->device_enabled_once = FALSE;
7797         if (rx_ring_mode == 1)
7798                 sp->rxd_mode = RXD_MODE_1;
7799         if (rx_ring_mode == 2)
7800                 sp->rxd_mode = RXD_MODE_3B;
7801
7802         sp->config.intr_type = dev_intr_type;
7803
7804         if ((pdev->device == PCI_DEVICE_ID_HERC_WIN) ||
7805                 (pdev->device == PCI_DEVICE_ID_HERC_UNI))
7806                 sp->device_type = XFRAME_II_DEVICE;
7807         else
7808                 sp->device_type = XFRAME_I_DEVICE;
7809
7810         sp->lro = lro_enable;
7811
7812         /* Initialize some PCI/PCI-X fields of the NIC. */
7813         s2io_init_pci(sp);
7814
7815         /*
7816          * Setting the device configuration parameters.
7817          * Most of these parameters can be specified by the user during
7818          * module insertion as they are module loadable parameters. If
7819          * these parameters are not not specified during load time, they
7820          * are initialized with default values.
7821          */
7822         mac_control = &sp->mac_control;
7823         config = &sp->config;
7824
7825         config->napi = napi;
7826         config->tx_steering_type = tx_steering_type;
7827
7828         /* Tx side parameters. */
7829         if (config->tx_steering_type == TX_PRIORITY_STEERING)
7830                 config->tx_fifo_num = MAX_TX_FIFOS;
7831         else
7832                 config->tx_fifo_num = tx_fifo_num;
7833
7834         /* Initialize the fifos used for tx steering */
7835         if (config->tx_fifo_num < 5) {
7836                         if (config->tx_fifo_num  == 1)
7837                                 sp->total_tcp_fifos = 1;
7838                         else
7839                                 sp->total_tcp_fifos = config->tx_fifo_num - 1;
7840                         sp->udp_fifo_idx = config->tx_fifo_num - 1;
7841                         sp->total_udp_fifos = 1;
7842                         sp->other_fifo_idx = sp->total_tcp_fifos - 1;
7843         } else {
7844                 sp->total_tcp_fifos = (tx_fifo_num - FIFO_UDP_MAX_NUM -
7845                                                 FIFO_OTHER_MAX_NUM);
7846                 sp->udp_fifo_idx = sp->total_tcp_fifos;
7847                 sp->total_udp_fifos = FIFO_UDP_MAX_NUM;
7848                 sp->other_fifo_idx = sp->udp_fifo_idx + FIFO_UDP_MAX_NUM;
7849         }
7850
7851         config->multiq = dev_multiq;
7852         for (i = 0; i < config->tx_fifo_num; i++) {
7853                 config->tx_cfg[i].fifo_len = tx_fifo_len[i];
7854                 config->tx_cfg[i].fifo_priority = i;
7855         }
7856
7857         /* mapping the QoS priority to the configured fifos */
7858         for (i = 0; i < MAX_TX_FIFOS; i++)
7859                 config->fifo_mapping[i] = fifo_map[config->tx_fifo_num - 1][i];
7860
7861         /* map the hashing selector table to the configured fifos */
7862         for (i = 0; i < config->tx_fifo_num; i++)
7863                 sp->fifo_selector[i] = fifo_selector[i];
7864
7865
7866         config->tx_intr_type = TXD_INT_TYPE_UTILZ;
7867         for (i = 0; i < config->tx_fifo_num; i++) {
7868                 config->tx_cfg[i].f_no_snoop =
7869                     (NO_SNOOP_TXD | NO_SNOOP_TXD_BUFFER);
7870                 if (config->tx_cfg[i].fifo_len < 65) {
7871                         config->tx_intr_type = TXD_INT_TYPE_PER_LIST;
7872                         break;
7873                 }
7874         }
7875         /* + 2 because one Txd for skb->data and one Txd for UFO */
7876         config->max_txds = MAX_SKB_FRAGS + 2;
7877
7878         /* Rx side parameters. */
7879         config->rx_ring_num = rx_ring_num;
7880         for (i = 0; i < config->rx_ring_num; i++) {
7881                 config->rx_cfg[i].num_rxd = rx_ring_sz[i] *
7882                     (rxd_count[sp->rxd_mode] + 1);
7883                 config->rx_cfg[i].ring_priority = i;
7884                 mac_control->rings[i].rx_bufs_left = 0;
7885                 mac_control->rings[i].rxd_mode = sp->rxd_mode;
7886                 mac_control->rings[i].rxd_count = rxd_count[sp->rxd_mode];
7887                 mac_control->rings[i].pdev = sp->pdev;
7888                 mac_control->rings[i].dev = sp->dev;
7889         }
7890
7891         for (i = 0; i < rx_ring_num; i++) {
7892                 config->rx_cfg[i].ring_org = RING_ORG_BUFF1;
7893                 config->rx_cfg[i].f_no_snoop =
7894                     (NO_SNOOP_RXD | NO_SNOOP_RXD_BUFFER);
7895         }
7896
7897         /*  Setting Mac Control parameters */
7898         mac_control->rmac_pause_time = rmac_pause_time;
7899         mac_control->mc_pause_threshold_q0q3 = mc_pause_threshold_q0q3;
7900         mac_control->mc_pause_threshold_q4q7 = mc_pause_threshold_q4q7;
7901
7902
7903         /*  initialize the shared memory used by the NIC and the host */
7904         if (init_shared_mem(sp)) {
7905                 DBG_PRINT(ERR_DBG, "%s: Memory allocation failed\n",
7906                           dev->name);
7907                 ret = -ENOMEM;
7908                 goto mem_alloc_failed;
7909         }
7910
7911         sp->bar0 = ioremap(pci_resource_start(pdev, 0),
7912                                      pci_resource_len(pdev, 0));
7913         if (!sp->bar0) {
7914                 DBG_PRINT(ERR_DBG, "%s: Neterion: cannot remap io mem1\n",
7915                           dev->name);
7916                 ret = -ENOMEM;
7917                 goto bar0_remap_failed;
7918         }
7919
7920         sp->bar1 = ioremap(pci_resource_start(pdev, 2),
7921                                      pci_resource_len(pdev, 2));
7922         if (!sp->bar1) {
7923                 DBG_PRINT(ERR_DBG, "%s: Neterion: cannot remap io mem2\n",
7924                           dev->name);
7925                 ret = -ENOMEM;
7926                 goto bar1_remap_failed;
7927         }
7928
7929         dev->irq = pdev->irq;
7930         dev->base_addr = (unsigned long) sp->bar0;
7931
7932         /* Initializing the BAR1 address as the start of the FIFO pointer. */
7933         for (j = 0; j < MAX_TX_FIFOS; j++) {
7934                 mac_control->tx_FIFO_start[j] = (struct TxFIFO_element __iomem *)
7935                     (sp->bar1 + (j * 0x00020000));
7936         }
7937
7938         /*  Driver entry points */
7939         dev->open = &s2io_open;
7940         dev->stop = &s2io_close;
7941         dev->hard_start_xmit = &s2io_xmit;
7942         dev->get_stats = &s2io_get_stats;
7943         dev->set_multicast_list = &s2io_set_multicast;
7944         dev->do_ioctl = &s2io_ioctl;
7945         dev->set_mac_address = &s2io_set_mac_addr;
7946         dev->change_mtu = &s2io_change_mtu;
7947         SET_ETHTOOL_OPS(dev, &netdev_ethtool_ops);
7948         dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
7949         dev->vlan_rx_register = s2io_vlan_rx_register;
7950         dev->vlan_rx_kill_vid = (void *)s2io_vlan_rx_kill_vid;
7951
7952         /*
7953          * will use eth_mac_addr() for  dev->set_mac_address
7954          * mac address will be set every time dev->open() is called
7955          */
7956         netif_napi_add(dev, &sp->napi, s2io_poll, 32);
7957
7958 #ifdef CONFIG_NET_POLL_CONTROLLER
7959         dev->poll_controller = s2io_netpoll;
7960 #endif
7961
7962         dev->features |= NETIF_F_SG | NETIF_F_IP_CSUM;
7963         if (sp->high_dma_flag == TRUE)
7964                 dev->features |= NETIF_F_HIGHDMA;
7965         dev->features |= NETIF_F_TSO;
7966         dev->features |= NETIF_F_TSO6;
7967         if ((sp->device_type & XFRAME_II_DEVICE) && (ufo))  {
7968                 dev->features |= NETIF_F_UFO;
7969                 dev->features |= NETIF_F_HW_CSUM;
7970         }
7971 #ifdef CONFIG_NETDEVICES_MULTIQUEUE
7972         if (config->multiq)
7973                 dev->features |= NETIF_F_MULTI_QUEUE;
7974 #endif
7975         dev->tx_timeout = &s2io_tx_watchdog;
7976         dev->watchdog_timeo = WATCH_DOG_TIMEOUT;
7977         INIT_WORK(&sp->rst_timer_task, s2io_restart_nic);
7978         INIT_WORK(&sp->set_link_task, s2io_set_link);
7979
7980         pci_save_state(sp->pdev);
7981
7982         /* Setting swapper control on the NIC, for proper reset operation */
7983         if (s2io_set_swapper(sp)) {
7984                 DBG_PRINT(ERR_DBG, "%s:swapper settings are wrong\n",
7985                           dev->name);
7986                 ret = -EAGAIN;
7987                 goto set_swap_failed;
7988         }
7989
7990         /* Verify if the Herc works on the slot its placed into */
7991         if (sp->device_type & XFRAME_II_DEVICE) {
7992                 mode = s2io_verify_pci_mode(sp);
7993                 if (mode < 0) {
7994                         DBG_PRINT(ERR_DBG, "%s: ", __FUNCTION__);
7995                         DBG_PRINT(ERR_DBG, " Unsupported PCI bus mode\n");
7996                         ret = -EBADSLT;
7997                         goto set_swap_failed;
7998                 }
7999         }
8000
8001         /* Not needed for Herc */
8002         if (sp->device_type & XFRAME_I_DEVICE) {
8003                 /*
8004                  * Fix for all "FFs" MAC address problems observed on
8005                  * Alpha platforms
8006                  */
8007                 fix_mac_address(sp);
8008                 s2io_reset(sp);
8009         }
8010
8011         /*
8012          * MAC address initialization.
8013          * For now only one mac address will be read and used.
8014          */
8015         bar0 = sp->bar0;
8016         val64 = RMAC_ADDR_CMD_MEM_RD | RMAC_ADDR_CMD_MEM_STROBE_NEW_CMD |
8017             RMAC_ADDR_CMD_MEM_OFFSET(0 + S2IO_MAC_ADDR_START_OFFSET);
8018         writeq(val64, &bar0->rmac_addr_cmd_mem);
8019         wait_for_cmd_complete(&bar0->rmac_addr_cmd_mem,
8020                       RMAC_ADDR_CMD_MEM_STROBE_CMD_EXECUTING, S2IO_BIT_RESET);
8021         tmp64 = readq(&bar0->rmac_addr_data0_mem);
8022         mac_down = (u32) tmp64;
8023         mac_up = (u32) (tmp64 >> 32);
8024
8025         sp->def_mac_addr[0].mac_addr[3] = (u8) (mac_up);
8026         sp->def_mac_addr[0].mac_addr[2] = (u8) (mac_up >> 8);
8027         sp->def_mac_addr[0].mac_addr[1] = (u8) (mac_up >> 16);
8028         sp->def_mac_addr[0].mac_addr[0] = (u8) (mac_up >> 24);
8029         sp->def_mac_addr[0].mac_addr[5] = (u8) (mac_down >> 16);
8030         sp->def_mac_addr[0].mac_addr[4] = (u8) (mac_down >> 24);
8031
8032         /*  Set the factory defined MAC address initially   */
8033         dev->addr_len = ETH_ALEN;
8034         memcpy(dev->dev_addr, sp->def_mac_addr, ETH_ALEN);
8035         memcpy(dev->perm_addr, dev->dev_addr, ETH_ALEN);
8036
8037         /* initialize number of multicast & unicast MAC entries variables */
8038         if (sp->device_type == XFRAME_I_DEVICE) {
8039                 config->max_mc_addr = S2IO_XENA_MAX_MC_ADDRESSES;
8040                 config->max_mac_addr = S2IO_XENA_MAX_MAC_ADDRESSES;
8041                 config->mc_start_offset = S2IO_XENA_MC_ADDR_START_OFFSET;
8042         } else if (sp->device_type == XFRAME_II_DEVICE) {
8043                 config->max_mc_addr = S2IO_HERC_MAX_MC_ADDRESSES;
8044                 config->max_mac_addr = S2IO_HERC_MAX_MAC_ADDRESSES;
8045                 config->mc_start_offset = S2IO_HERC_MC_ADDR_START_OFFSET;
8046         }
8047
8048         /* store mac addresses from CAM to s2io_nic structure */
8049         do_s2io_store_unicast_mc(sp);
8050
8051          /* Store the values of the MSIX table in the s2io_nic structure */
8052         store_xmsi_data(sp);
8053         /* reset Nic and bring it to known state */
8054         s2io_reset(sp);
8055
8056         /*
8057          * Initialize link state flags
8058          * and the card state parameter
8059          */
8060         sp->state = 0;
8061
8062         /* Initialize spinlocks */
8063         for (i = 0; i < sp->config.tx_fifo_num; i++)
8064                 spin_lock_init(&mac_control->fifos[i].tx_lock);
8065
8066         /*
8067          * SXE-002: Configure link and activity LED to init state
8068          * on driver load.
8069          */
8070         subid = sp->pdev->subsystem_device;
8071         if ((subid & 0xFF) >= 0x07) {
8072                 val64 = readq(&bar0->gpio_control);
8073                 val64 |= 0x0000800000000000ULL;
8074                 writeq(val64, &bar0->gpio_control);
8075                 val64 = 0x0411040400000000ULL;
8076                 writeq(val64, (void __iomem *) bar0 + 0x2700);
8077                 val64 = readq(&bar0->gpio_control);
8078         }
8079
8080         sp->rx_csum = 1;        /* Rx chksum verify enabled by default */
8081
8082         if (register_netdev(dev)) {
8083                 DBG_PRINT(ERR_DBG, "Device registration failed\n");
8084                 ret = -ENODEV;
8085                 goto register_failed;
8086         }
8087         s2io_vpd_read(sp);
8088         DBG_PRINT(ERR_DBG, "Copyright(c) 2002-2007 Neterion Inc.\n");
8089         DBG_PRINT(ERR_DBG, "%s: Neterion %s (rev %d)\n",dev->name,
8090                   sp->product_name, pdev->revision);
8091         DBG_PRINT(ERR_DBG, "%s: Driver version %s\n", dev->name,
8092                   s2io_driver_version);
8093         DBG_PRINT(ERR_DBG, "%s: MAC ADDR: %s\n",
8094                   dev->name, print_mac(mac, dev->dev_addr));
8095         DBG_PRINT(ERR_DBG, "SERIAL NUMBER: %s\n", sp->serial_num);
8096         if (sp->device_type & XFRAME_II_DEVICE) {
8097                 mode = s2io_print_pci_mode(sp);
8098                 if (mode < 0) {
8099                         DBG_PRINT(ERR_DBG, " Unsupported PCI bus mode\n");
8100                         ret = -EBADSLT;
8101                         unregister_netdev(dev);
8102                         goto set_swap_failed;
8103                 }
8104         }
8105         switch(sp->rxd_mode) {
8106                 case RXD_MODE_1:
8107                     DBG_PRINT(ERR_DBG, "%s: 1-Buffer receive mode enabled\n",
8108                                                 dev->name);
8109                     break;
8110                 case RXD_MODE_3B:
8111                     DBG_PRINT(ERR_DBG, "%s: 2-Buffer receive mode enabled\n",
8112                                                 dev->name);
8113                     break;
8114         }
8115
8116         if (napi)
8117                 DBG_PRINT(ERR_DBG, "%s: NAPI enabled\n", dev->name);
8118
8119         DBG_PRINT(ERR_DBG, "%s: Using %d Tx fifo(s)\n", dev->name,
8120                 sp->config.tx_fifo_num);
8121
8122         DBG_PRINT(ERR_DBG, "%s: Using %d Rx ring(s)\n", dev->name,
8123                   sp->config.rx_ring_num);
8124
8125         switch(sp->config.intr_type) {
8126                 case INTA:
8127                     DBG_PRINT(ERR_DBG, "%s: Interrupt type INTA\n", dev->name);
8128                     break;
8129                 case MSI_X:
8130                     DBG_PRINT(ERR_DBG, "%s: Interrupt type MSI-X\n", dev->name);
8131                     break;
8132         }
8133         if (sp->config.multiq) {
8134         for (i = 0; i < sp->config.tx_fifo_num; i++)
8135                 mac_control->fifos[i].multiq = config->multiq;
8136                 DBG_PRINT(ERR_DBG, "%s: Multiqueue support enabled\n",
8137                         dev->name);
8138         } else
8139                 DBG_PRINT(ERR_DBG, "%s: Multiqueue support disabled\n",
8140                         dev->name);
8141
8142         switch (sp->config.tx_steering_type) {
8143         case NO_STEERING:
8144                 DBG_PRINT(ERR_DBG, "%s: No steering enabled for"
8145                         " transmit\n", dev->name);
8146                         break;
8147         case TX_PRIORITY_STEERING:
8148                 DBG_PRINT(ERR_DBG, "%s: Priority steering enabled for"
8149                         " transmit\n", dev->name);
8150                 break;
8151         case TX_DEFAULT_STEERING:
8152                 DBG_PRINT(ERR_DBG, "%s: Default steering enabled for"
8153                         " transmit\n", dev->name);
8154         }
8155
8156         if (sp->lro)
8157                 DBG_PRINT(ERR_DBG, "%s: Large receive offload enabled\n",
8158                           dev->name);
8159         if (ufo)
8160                 DBG_PRINT(ERR_DBG, "%s: UDP Fragmentation Offload(UFO)"
8161                                         " enabled\n", dev->name);
8162         /* Initialize device name */
8163         sprintf(sp->name, "%s Neterion %s", dev->name, sp->product_name);
8164
8165         /*
8166          * Make Link state as off at this point, when the Link change
8167          * interrupt comes the state will be automatically changed to
8168          * the right state.
8169          */
8170         netif_carrier_off(dev);
8171
8172         return 0;
8173
8174       register_failed:
8175       set_swap_failed:
8176         iounmap(sp->bar1);
8177       bar1_remap_failed:
8178         iounmap(sp->bar0);
8179       bar0_remap_failed:
8180       mem_alloc_failed:
8181         free_shared_mem(sp);
8182         pci_disable_device(pdev);
8183         pci_release_regions(pdev);
8184         pci_set_drvdata(pdev, NULL);
8185         free_netdev(dev);
8186
8187         return ret;
8188 }
8189
8190 /**
8191  * s2io_rem_nic - Free the PCI device
8192  * @pdev: structure containing the PCI related information of the device.
8193  * Description: This function is called by the Pci subsystem to release a
8194  * PCI device and free up all resource held up by the device. This could
8195  * be in response to a Hot plug event or when the driver is to be removed
8196  * from memory.
8197  */
8198
8199 static void __devexit s2io_rem_nic(struct pci_dev *pdev)
8200 {
8201         struct net_device *dev =
8202             (struct net_device *) pci_get_drvdata(pdev);
8203         struct s2io_nic *sp;
8204
8205         if (dev == NULL) {
8206                 DBG_PRINT(ERR_DBG, "Driver Data is NULL!!\n");
8207                 return;
8208         }
8209
8210         flush_scheduled_work();
8211
8212         sp = dev->priv;
8213         unregister_netdev(dev);
8214
8215         free_shared_mem(sp);
8216         iounmap(sp->bar0);
8217         iounmap(sp->bar1);
8218         pci_release_regions(pdev);
8219         pci_set_drvdata(pdev, NULL);
8220         free_netdev(dev);
8221         pci_disable_device(pdev);
8222 }
8223
8224 /**
8225  * s2io_starter - Entry point for the driver
8226  * Description: This function is the entry point for the driver. It verifies
8227  * the module loadable parameters and initializes PCI configuration space.
8228  */
8229
8230 static int __init s2io_starter(void)
8231 {
8232         return pci_register_driver(&s2io_driver);
8233 }
8234
8235 /**
8236  * s2io_closer - Cleanup routine for the driver
8237  * Description: This function is the cleanup routine for the driver. It unregist * ers the driver.
8238  */
8239
8240 static __exit void s2io_closer(void)
8241 {
8242         pci_unregister_driver(&s2io_driver);
8243         DBG_PRINT(INIT_DBG, "cleanup done\n");
8244 }
8245
8246 module_init(s2io_starter);
8247 module_exit(s2io_closer);
8248
8249 static int check_L2_lro_capable(u8 *buffer, struct iphdr **ip,
8250                 struct tcphdr **tcp, struct RxD_t *rxdp,
8251                 struct s2io_nic *sp)
8252 {
8253         int ip_off;
8254         u8 l2_type = (u8)((rxdp->Control_1 >> 37) & 0x7), ip_len;
8255
8256         if (!(rxdp->Control_1 & RXD_FRAME_PROTO_TCP)) {
8257                 DBG_PRINT(INIT_DBG,"%s: Non-TCP frames not supported for LRO\n",
8258                           __FUNCTION__);
8259                 return -1;
8260         }
8261
8262         /* Checking for DIX type or DIX type with VLAN */
8263         if ((l2_type == 0)
8264                 || (l2_type == 4)) {
8265                 ip_off = HEADER_ETHERNET_II_802_3_SIZE;
8266                 /*
8267                  * If vlan stripping is disabled and the frame is VLAN tagged,
8268                  * shift the offset by the VLAN header size bytes.
8269                  */
8270                 if ((!vlan_strip_flag) &&
8271                         (rxdp->Control_1 & RXD_FRAME_VLAN_TAG))
8272                         ip_off += HEADER_VLAN_SIZE;
8273         } else {
8274                 /* LLC, SNAP etc are considered non-mergeable */
8275                 return -1;
8276         }
8277
8278         *ip = (struct iphdr *)((u8 *)buffer + ip_off);
8279         ip_len = (u8)((*ip)->ihl);
8280         ip_len <<= 2;
8281         *tcp = (struct tcphdr *)((unsigned long)*ip + ip_len);
8282
8283         return 0;
8284 }
8285
8286 static int check_for_socket_match(struct lro *lro, struct iphdr *ip,
8287                                   struct tcphdr *tcp)
8288 {
8289         DBG_PRINT(INFO_DBG,"%s: Been here...\n", __FUNCTION__);
8290         if ((lro->iph->saddr != ip->saddr) || (lro->iph->daddr != ip->daddr) ||
8291            (lro->tcph->source != tcp->source) || (lro->tcph->dest != tcp->dest))
8292                 return -1;
8293         return 0;
8294 }
8295
8296 static inline int get_l4_pyld_length(struct iphdr *ip, struct tcphdr *tcp)
8297 {
8298         return(ntohs(ip->tot_len) - (ip->ihl << 2) - (tcp->doff << 2));
8299 }
8300
8301 static void initiate_new_session(struct lro *lro, u8 *l2h,
8302         struct iphdr *ip, struct tcphdr *tcp, u32 tcp_pyld_len, u16 vlan_tag)
8303 {
8304         DBG_PRINT(INFO_DBG,"%s: Been here...\n", __FUNCTION__);
8305         lro->l2h = l2h;
8306         lro->iph = ip;
8307         lro->tcph = tcp;
8308         lro->tcp_next_seq = tcp_pyld_len + ntohl(tcp->seq);
8309         lro->tcp_ack = tcp->ack_seq;
8310         lro->sg_num = 1;
8311         lro->total_len = ntohs(ip->tot_len);
8312         lro->frags_len = 0;
8313         lro->vlan_tag = vlan_tag;
8314         /*
8315          * check if we saw TCP timestamp. Other consistency checks have
8316          * already been done.
8317          */
8318         if (tcp->doff == 8) {
8319                 __be32 *ptr;
8320                 ptr = (__be32 *)(tcp+1);
8321                 lro->saw_ts = 1;
8322                 lro->cur_tsval = ntohl(*(ptr+1));
8323                 lro->cur_tsecr = *(ptr+2);
8324         }
8325         lro->in_use = 1;
8326 }
8327
8328 static void update_L3L4_header(struct s2io_nic *sp, struct lro *lro)
8329 {
8330         struct iphdr *ip = lro->iph;
8331         struct tcphdr *tcp = lro->tcph;
8332         __sum16 nchk;
8333         struct stat_block *statinfo = sp->mac_control.stats_info;
8334         DBG_PRINT(INFO_DBG,"%s: Been here...\n", __FUNCTION__);
8335
8336         /* Update L3 header */
8337         ip->tot_len = htons(lro->total_len);
8338         ip->check = 0;
8339         nchk = ip_fast_csum((u8 *)lro->iph, ip->ihl);
8340         ip->check = nchk;
8341
8342         /* Update L4 header */
8343         tcp->ack_seq = lro->tcp_ack;
8344         tcp->window = lro->window;
8345
8346         /* Update tsecr field if this session has timestamps enabled */
8347         if (lro->saw_ts) {
8348                 __be32 *ptr = (__be32 *)(tcp + 1);
8349                 *(ptr+2) = lro->cur_tsecr;
8350         }
8351
8352         /* Update counters required for calculation of
8353          * average no. of packets aggregated.
8354          */
8355         statinfo->sw_stat.sum_avg_pkts_aggregated += lro->sg_num;
8356         statinfo->sw_stat.num_aggregations++;
8357 }
8358
8359 static void aggregate_new_rx(struct lro *lro, struct iphdr *ip,
8360                 struct tcphdr *tcp, u32 l4_pyld)
8361 {
8362         DBG_PRINT(INFO_DBG,"%s: Been here...\n", __FUNCTION__);
8363         lro->total_len += l4_pyld;
8364         lro->frags_len += l4_pyld;
8365         lro->tcp_next_seq += l4_pyld;
8366         lro->sg_num++;
8367
8368         /* Update ack seq no. and window ad(from this pkt) in LRO object */
8369         lro->tcp_ack = tcp->ack_seq;
8370         lro->window = tcp->window;
8371
8372         if (lro->saw_ts) {
8373                 __be32 *ptr;
8374                 /* Update tsecr and tsval from this packet */
8375                 ptr = (__be32 *)(tcp+1);
8376                 lro->cur_tsval = ntohl(*(ptr+1));
8377                 lro->cur_tsecr = *(ptr + 2);
8378         }
8379 }
8380
8381 static int verify_l3_l4_lro_capable(struct lro *l_lro, struct iphdr *ip,
8382                                     struct tcphdr *tcp, u32 tcp_pyld_len)
8383 {
8384         u8 *ptr;
8385
8386         DBG_PRINT(INFO_DBG,"%s: Been here...\n", __FUNCTION__);
8387
8388         if (!tcp_pyld_len) {
8389                 /* Runt frame or a pure ack */
8390                 return -1;
8391         }
8392
8393         if (ip->ihl != 5) /* IP has options */
8394                 return -1;
8395
8396         /* If we see CE codepoint in IP header, packet is not mergeable */
8397         if (INET_ECN_is_ce(ipv4_get_dsfield(ip)))
8398                 return -1;
8399
8400         /* If we see ECE or CWR flags in TCP header, packet is not mergeable */
8401         if (tcp->urg || tcp->psh || tcp->rst || tcp->syn || tcp->fin ||
8402                                     tcp->ece || tcp->cwr || !tcp->ack) {
8403                 /*
8404                  * Currently recognize only the ack control word and
8405                  * any other control field being set would result in
8406                  * flushing the LRO session
8407                  */
8408                 return -1;
8409         }
8410
8411         /*
8412          * Allow only one TCP timestamp option. Don't aggregate if
8413          * any other options are detected.
8414          */
8415         if (tcp->doff != 5 && tcp->doff != 8)
8416                 return -1;
8417
8418         if (tcp->doff == 8) {
8419                 ptr = (u8 *)(tcp + 1);
8420                 while (*ptr == TCPOPT_NOP)
8421                         ptr++;
8422                 if (*ptr != TCPOPT_TIMESTAMP || *(ptr+1) != TCPOLEN_TIMESTAMP)
8423                         return -1;
8424
8425                 /* Ensure timestamp value increases monotonically */
8426                 if (l_lro)
8427                         if (l_lro->cur_tsval > ntohl(*((__be32 *)(ptr+2))))
8428                                 return -1;
8429
8430                 /* timestamp echo reply should be non-zero */
8431                 if (*((__be32 *)(ptr+6)) == 0)
8432                         return -1;
8433         }
8434
8435         return 0;
8436 }
8437
8438 static int
8439 s2io_club_tcp_session(struct ring_info *ring_data, u8 *buffer, u8 **tcp,
8440         u32 *tcp_len, struct lro **lro, struct RxD_t *rxdp,
8441         struct s2io_nic *sp)
8442 {
8443         struct iphdr *ip;
8444         struct tcphdr *tcph;
8445         int ret = 0, i;
8446         u16 vlan_tag = 0;
8447
8448         if (!(ret = check_L2_lro_capable(buffer, &ip, (struct tcphdr **)tcp,
8449                                          rxdp, sp))) {
8450                 DBG_PRINT(INFO_DBG,"IP Saddr: %x Daddr: %x\n",
8451                           ip->saddr, ip->daddr);
8452         } else
8453                 return ret;
8454
8455         vlan_tag = RXD_GET_VLAN_TAG(rxdp->Control_2);
8456         tcph = (struct tcphdr *)*tcp;
8457         *tcp_len = get_l4_pyld_length(ip, tcph);
8458         for (i=0; i<MAX_LRO_SESSIONS; i++) {
8459                 struct lro *l_lro = &ring_data->lro0_n[i];
8460                 if (l_lro->in_use) {
8461                         if (check_for_socket_match(l_lro, ip, tcph))
8462                                 continue;
8463                         /* Sock pair matched */
8464                         *lro = l_lro;
8465
8466                         if ((*lro)->tcp_next_seq != ntohl(tcph->seq)) {
8467                                 DBG_PRINT(INFO_DBG, "%s:Out of order. expected "
8468                                           "0x%x, actual 0x%x\n", __FUNCTION__,
8469                                           (*lro)->tcp_next_seq,
8470                                           ntohl(tcph->seq));
8471
8472                                 sp->mac_control.stats_info->
8473                                    sw_stat.outof_sequence_pkts++;
8474                                 ret = 2;
8475                                 break;
8476                         }
8477
8478                         if (!verify_l3_l4_lro_capable(l_lro, ip, tcph,*tcp_len))
8479                                 ret = 1; /* Aggregate */
8480                         else
8481                                 ret = 2; /* Flush both */
8482                         break;
8483                 }
8484         }
8485
8486         if (ret == 0) {
8487                 /* Before searching for available LRO objects,
8488                  * check if the pkt is L3/L4 aggregatable. If not
8489                  * don't create new LRO session. Just send this
8490                  * packet up.
8491                  */
8492                 if (verify_l3_l4_lro_capable(NULL, ip, tcph, *tcp_len)) {
8493                         return 5;
8494                 }
8495
8496                 for (i=0; i<MAX_LRO_SESSIONS; i++) {
8497                         struct lro *l_lro = &ring_data->lro0_n[i];
8498                         if (!(l_lro->in_use)) {
8499                                 *lro = l_lro;
8500                                 ret = 3; /* Begin anew */
8501                                 break;
8502                         }
8503                 }
8504         }
8505
8506         if (ret == 0) { /* sessions exceeded */
8507                 DBG_PRINT(INFO_DBG,"%s:All LRO sessions already in use\n",
8508                           __FUNCTION__);
8509                 *lro = NULL;
8510                 return ret;
8511         }
8512
8513         switch (ret) {
8514                 case 3:
8515                         initiate_new_session(*lro, buffer, ip, tcph, *tcp_len,
8516                                                                 vlan_tag);
8517                         break;
8518                 case 2:
8519                         update_L3L4_header(sp, *lro);
8520                         break;
8521                 case 1:
8522                         aggregate_new_rx(*lro, ip, tcph, *tcp_len);
8523                         if ((*lro)->sg_num == sp->lro_max_aggr_per_sess) {
8524                                 update_L3L4_header(sp, *lro);
8525                                 ret = 4; /* Flush the LRO */
8526                         }
8527                         break;
8528                 default:
8529                         DBG_PRINT(ERR_DBG,"%s:Dont know, can't say!!\n",
8530                                 __FUNCTION__);
8531                         break;
8532         }
8533
8534         return ret;
8535 }
8536
8537 static void clear_lro_session(struct lro *lro)
8538 {
8539         static u16 lro_struct_size = sizeof(struct lro);
8540
8541         memset(lro, 0, lro_struct_size);
8542 }
8543
8544 static void queue_rx_frame(struct sk_buff *skb, u16 vlan_tag)
8545 {
8546         struct net_device *dev = skb->dev;
8547         struct s2io_nic *sp = dev->priv;
8548
8549         skb->protocol = eth_type_trans(skb, dev);
8550         if (sp->vlgrp && vlan_tag
8551                 && (vlan_strip_flag)) {
8552                 /* Queueing the vlan frame to the upper layer */
8553                 if (sp->config.napi)
8554                         vlan_hwaccel_receive_skb(skb, sp->vlgrp, vlan_tag);
8555                 else
8556                         vlan_hwaccel_rx(skb, sp->vlgrp, vlan_tag);
8557         } else {
8558                 if (sp->config.napi)
8559                         netif_receive_skb(skb);
8560                 else
8561                         netif_rx(skb);
8562         }
8563 }
8564
8565 static void lro_append_pkt(struct s2io_nic *sp, struct lro *lro,
8566                            struct sk_buff *skb,
8567                            u32 tcp_len)
8568 {
8569         struct sk_buff *first = lro->parent;
8570
8571         first->len += tcp_len;
8572         first->data_len = lro->frags_len;
8573         skb_pull(skb, (skb->len - tcp_len));
8574         if (skb_shinfo(first)->frag_list)
8575                 lro->last_frag->next = skb;
8576         else
8577                 skb_shinfo(first)->frag_list = skb;
8578         first->truesize += skb->truesize;
8579         lro->last_frag = skb;
8580         sp->mac_control.stats_info->sw_stat.clubbed_frms_cnt++;
8581         return;
8582 }
8583
8584 /**
8585  * s2io_io_error_detected - called when PCI error is detected
8586  * @pdev: Pointer to PCI device
8587  * @state: The current pci connection state
8588  *
8589  * This function is called after a PCI bus error affecting
8590  * this device has been detected.
8591  */
8592 static pci_ers_result_t s2io_io_error_detected(struct pci_dev *pdev,
8593                                                pci_channel_state_t state)
8594 {
8595         struct net_device *netdev = pci_get_drvdata(pdev);
8596         struct s2io_nic *sp = netdev->priv;
8597
8598         netif_device_detach(netdev);
8599
8600         if (netif_running(netdev)) {
8601                 /* Bring down the card, while avoiding PCI I/O */
8602                 do_s2io_card_down(sp, 0);
8603         }
8604         pci_disable_device(pdev);
8605
8606         return PCI_ERS_RESULT_NEED_RESET;
8607 }
8608
8609 /**
8610  * s2io_io_slot_reset - called after the pci bus has been reset.
8611  * @pdev: Pointer to PCI device
8612  *
8613  * Restart the card from scratch, as if from a cold-boot.
8614  * At this point, the card has exprienced a hard reset,
8615  * followed by fixups by BIOS, and has its config space
8616  * set up identically to what it was at cold boot.
8617  */
8618 static pci_ers_result_t s2io_io_slot_reset(struct pci_dev *pdev)
8619 {
8620         struct net_device *netdev = pci_get_drvdata(pdev);
8621         struct s2io_nic *sp = netdev->priv;
8622
8623         if (pci_enable_device(pdev)) {
8624                 printk(KERN_ERR "s2io: "
8625                        "Cannot re-enable PCI device after reset.\n");
8626                 return PCI_ERS_RESULT_DISCONNECT;
8627         }
8628
8629         pci_set_master(pdev);
8630         s2io_reset(sp);
8631
8632         return PCI_ERS_RESULT_RECOVERED;
8633 }
8634
8635 /**
8636  * s2io_io_resume - called when traffic can start flowing again.
8637  * @pdev: Pointer to PCI device
8638  *
8639  * This callback is called when the error recovery driver tells
8640  * us that its OK to resume normal operation.
8641  */
8642 static void s2io_io_resume(struct pci_dev *pdev)
8643 {
8644         struct net_device *netdev = pci_get_drvdata(pdev);
8645         struct s2io_nic *sp = netdev->priv;
8646
8647         if (netif_running(netdev)) {
8648                 if (s2io_card_up(sp)) {
8649                         printk(KERN_ERR "s2io: "
8650                                "Can't bring device back up after reset.\n");
8651                         return;
8652                 }
8653
8654                 if (s2io_set_mac_addr(netdev, netdev->dev_addr) == FAILURE) {
8655                         s2io_card_down(sp);
8656                         printk(KERN_ERR "s2io: "
8657                                "Can't resetore mac addr after reset.\n");
8658                         return;
8659                 }
8660         }
8661
8662         netif_device_attach(netdev);
8663         netif_wake_queue(netdev);
8664 }