err.no Git - linux-2.6/blob - drivers/net/s2io.c

   1 /************************************************************************
   2  * s2io.c: A Linux PCI-X Ethernet driver for Neterion 10GbE Server NIC
   3  * Copyright(c) 2002-2007 Neterion Inc.
   4
   5  * This software may be used and distributed according to the terms of
   6  * the GNU General Public License (GPL), incorporated herein by reference.
   7  * Drivers based on or derived from this code fall under the GPL and must
   8  * retain the authorship, copyright and license notice.  This file is not
   9  * a complete program and may only be used when the entire operating
  10  * system is licensed under the GPL.
  11  * See the file COPYING in this distribution for more information.
  12  *
  13  * Credits:
  14  * Jeff Garzik          : For pointing out the improper error condition
  15  *                        check in the s2io_xmit routine and also some
  16  *                        issues in the Tx watch dog function. Also for
  17  *                        patiently answering all those innumerable
  18  *                        questions regaring the 2.6 porting issues.
  19  * Stephen Hemminger    : Providing proper 2.6 porting mechanism for some
  20  *                        macros available only in 2.6 Kernel.
  21  * Francois Romieu      : For pointing out all code part that were
  22  *                        deprecated and also styling related comments.
  23  * Grant Grundler       : For helping me get rid of some Architecture
  24  *                        dependent code.
  25  * Christopher Hellwig  : Some more 2.6 specific issues in the driver.
  26  *
  27  * The module loadable parameters that are supported by the driver and a brief
  28  * explaination of all the variables.
  29  *
  30  * rx_ring_num : This can be used to program the number of receive rings used
  31  * in the driver.
  32  * rx_ring_sz: This defines the number of receive blocks each ring can have.
  33  *     This is also an array of size 8.
  34  * rx_ring_mode: This defines the operation mode of all 8 rings. The valid
  35  *              values are 1, 2.
  36  * tx_fifo_num: This defines the number of Tx FIFOs thats used int the driver.
  37  * tx_fifo_len: This too is an array of 8. Each element defines the number of
  38  * Tx descriptors that can be associated with each corresponding FIFO.
  39  * intr_type: This defines the type of interrupt. The values can be 0(INTA),
  40  *     2(MSI_X). Default value is '2(MSI_X)'
  41  * lro: Specifies whether to enable Large Receive Offload (LRO) or not.
  42  *     Possible values '1' for enable '0' for disable. Default is '0'
  43  * lro_max_pkts: This parameter defines maximum number of packets can be
  44  *     aggregated as a single large packet
  45  * napi: This parameter used to enable/disable NAPI (polling Rx)
  46  *     Possible values '1' for enable and '0' for disable. Default is '1'
  47  * ufo: This parameter used to enable/disable UDP Fragmentation Offload(UFO)
  48  *      Possible values '1' for enable and '0' for disable. Default is '0'
  49  * vlan_tag_strip: This can be used to enable or disable vlan stripping.
  50  *                 Possible values '1' for enable , '0' for disable.
  51  *                 Default is '2' - which means disable in promisc mode
  52  *                 and enable in non-promiscuous mode.
  53  ************************************************************************/
  54
  55 #include <linux/module.h>
  56 #include <linux/types.h>
  57 #include <linux/errno.h>
  58 #include <linux/ioport.h>
  59 #include <linux/pci.h>
  60 #include <linux/dma-mapping.h>
  61 #include <linux/kernel.h>
  62 #include <linux/netdevice.h>
  63 #include <linux/etherdevice.h>
  64 #include <linux/skbuff.h>
  65 #include <linux/init.h>
  66 #include <linux/delay.h>
  67 #include <linux/stddef.h>
  68 #include <linux/ioctl.h>
  69 #include <linux/timex.h>
  70 #include <linux/ethtool.h>
  71 #include <linux/workqueue.h>
  72 #include <linux/if_vlan.h>
  73 #include <linux/ip.h>
  74 #include <linux/tcp.h>
  75 #include <net/tcp.h>
  76
  77 #include <asm/system.h>
  78 #include <asm/uaccess.h>
  79 #include <asm/io.h>
  80 #include <asm/div64.h>
  81 #include <asm/irq.h>
  82
  83 /* local include */
  84 #include "s2io.h"
  85 #include "s2io-regs.h"
  86
  87 #define DRV_VERSION "2.0.26.1"
  88
  89 /* S2io Driver name & version. */
  90 static char s2io_driver_name[] = "Neterion";
  91 static char s2io_driver_version[] = DRV_VERSION;
  92
  93 static int rxd_size[2] = {32,48};
  94 static int rxd_count[2] = {127,85};
  95
  96 static inline int RXD_IS_UP2DT(struct RxD_t *rxdp)
  97 {
  98         int ret;
  99
 100         ret = ((!(rxdp->Control_1 & RXD_OWN_XENA)) &&
 101                 (GET_RXD_MARKER(rxdp->Control_2) != THE_RXD_MARK));
 102
 103         return ret;
 104 }
 105
 106 /*
 107  * Cards with following subsystem_id have a link state indication
 108  * problem, 600B, 600C, 600D, 640B, 640C and 640D.
 109  * macro below identifies these cards given the subsystem_id.
 110  */
 111 #define CARDS_WITH_FAULTY_LINK_INDICATORS(dev_type, subid) \
 112         (dev_type == XFRAME_I_DEVICE) ?                 \
 113                 ((((subid >= 0x600B) && (subid <= 0x600D)) || \
 114                  ((subid >= 0x640B) && (subid <= 0x640D))) ? 1 : 0) : 0
 115
 116 #define LINK_IS_UP(val64) (!(val64 & (ADAPTER_STATUS_RMAC_REMOTE_FAULT | \
 117                                       ADAPTER_STATUS_RMAC_LOCAL_FAULT)))
 118 #define TASKLET_IN_USE test_and_set_bit(0, (&sp->tasklet_status))
 119 #define PANIC   1
 120 #define LOW     2
 121 static inline int rx_buffer_level(struct s2io_nic * sp, int rxb_size, int ring)
 122 {
 123         struct mac_info *mac_control;
 124
 125         mac_control = &sp->mac_control;
 126         if (rxb_size <= rxd_count[sp->rxd_mode])
 127                 return PANIC;
 128         else if ((mac_control->rings[ring].pkt_cnt - rxb_size) > 16)
 129                 return  LOW;
 130         return 0;
 131 }
 132
 133 static inline int is_s2io_card_up(const struct s2io_nic * sp)
 134 {
 135         return test_bit(__S2IO_STATE_CARD_UP, &sp->state);
 136 }
 137
 138 /* Ethtool related variables and Macros. */
 139 static char s2io_gstrings[][ETH_GSTRING_LEN] = {
 140         "Register test\t(offline)",
 141         "Eeprom test\t(offline)",
 142         "Link test\t(online)",
 143         "RLDRAM test\t(offline)",
 144         "BIST Test\t(offline)"
 145 };
 146
 147 static char ethtool_xena_stats_keys[][ETH_GSTRING_LEN] = {
 148         {"tmac_frms"},
 149         {"tmac_data_octets"},
 150         {"tmac_drop_frms"},
 151         {"tmac_mcst_frms"},
 152         {"tmac_bcst_frms"},
 153         {"tmac_pause_ctrl_frms"},
 154         {"tmac_ttl_octets"},
 155         {"tmac_ucst_frms"},
 156         {"tmac_nucst_frms"},
 157         {"tmac_any_err_frms"},
 158         {"tmac_ttl_less_fb_octets"},
 159         {"tmac_vld_ip_octets"},
 160         {"tmac_vld_ip"},
 161         {"tmac_drop_ip"},
 162         {"tmac_icmp"},
 163         {"tmac_rst_tcp"},
 164         {"tmac_tcp"},
 165         {"tmac_udp"},
 166         {"rmac_vld_frms"},
 167         {"rmac_data_octets"},
 168         {"rmac_fcs_err_frms"},
 169         {"rmac_drop_frms"},
 170         {"rmac_vld_mcst_frms"},
 171         {"rmac_vld_bcst_frms"},
 172         {"rmac_in_rng_len_err_frms"},
 173         {"rmac_out_rng_len_err_frms"},
 174         {"rmac_long_frms"},
 175         {"rmac_pause_ctrl_frms"},
 176         {"rmac_unsup_ctrl_frms"},
 177         {"rmac_ttl_octets"},
 178         {"rmac_accepted_ucst_frms"},
 179         {"rmac_accepted_nucst_frms"},
 180         {"rmac_discarded_frms"},
 181         {"rmac_drop_events"},
 182         {"rmac_ttl_less_fb_octets"},
 183         {"rmac_ttl_frms"},
 184         {"rmac_usized_frms"},
 185         {"rmac_osized_frms"},
 186         {"rmac_frag_frms"},
 187         {"rmac_jabber_frms"},
 188         {"rmac_ttl_64_frms"},
 189         {"rmac_ttl_65_127_frms"},
 190         {"rmac_ttl_128_255_frms"},
 191         {"rmac_ttl_256_511_frms"},
 192         {"rmac_ttl_512_1023_frms"},
 193         {"rmac_ttl_1024_1518_frms"},
 194         {"rmac_ip"},
 195         {"rmac_ip_octets"},
 196         {"rmac_hdr_err_ip"},
 197         {"rmac_drop_ip"},
 198         {"rmac_icmp"},
 199         {"rmac_tcp"},
 200         {"rmac_udp"},
 201         {"rmac_err_drp_udp"},
 202         {"rmac_xgmii_err_sym"},
 203         {"rmac_frms_q0"},
 204         {"rmac_frms_q1"},
 205         {"rmac_frms_q2"},
 206         {"rmac_frms_q3"},
 207         {"rmac_frms_q4"},
 208         {"rmac_frms_q5"},
 209         {"rmac_frms_q6"},
 210         {"rmac_frms_q7"},
 211         {"rmac_full_q0"},
 212         {"rmac_full_q1"},
 213         {"rmac_full_q2"},
 214         {"rmac_full_q3"},
 215         {"rmac_full_q4"},
 216         {"rmac_full_q5"},
 217         {"rmac_full_q6"},
 218         {"rmac_full_q7"},
 219         {"rmac_pause_cnt"},
 220         {"rmac_xgmii_data_err_cnt"},
 221         {"rmac_xgmii_ctrl_err_cnt"},
 222         {"rmac_accepted_ip"},
 223         {"rmac_err_tcp"},
 224         {"rd_req_cnt"},
 225         {"new_rd_req_cnt"},
 226         {"new_rd_req_rtry_cnt"},
 227         {"rd_rtry_cnt"},
 228         {"wr_rtry_rd_ack_cnt"},
 229         {"wr_req_cnt"},
 230         {"new_wr_req_cnt"},
 231         {"new_wr_req_rtry_cnt"},
 232         {"wr_rtry_cnt"},
 233         {"wr_disc_cnt"},
 234         {"rd_rtry_wr_ack_cnt"},
 235         {"txp_wr_cnt"},
 236         {"txd_rd_cnt"},
 237         {"txd_wr_cnt"},
 238         {"rxd_rd_cnt"},
 239         {"rxd_wr_cnt"},
 240         {"txf_rd_cnt"},
 241         {"rxf_wr_cnt"}
 242 };
 243
 244 static char ethtool_enhanced_stats_keys[][ETH_GSTRING_LEN] = {
 245         {"rmac_ttl_1519_4095_frms"},
 246         {"rmac_ttl_4096_8191_frms"},
 247         {"rmac_ttl_8192_max_frms"},
 248         {"rmac_ttl_gt_max_frms"},
 249         {"rmac_osized_alt_frms"},
 250         {"rmac_jabber_alt_frms"},
 251         {"rmac_gt_max_alt_frms"},
 252         {"rmac_vlan_frms"},
 253         {"rmac_len_discard"},
 254         {"rmac_fcs_discard"},
 255         {"rmac_pf_discard"},
 256         {"rmac_da_discard"},
 257         {"rmac_red_discard"},
 258         {"rmac_rts_discard"},
 259         {"rmac_ingm_full_discard"},
 260         {"link_fault_cnt"}
 261 };
 262
 263 static char ethtool_driver_stats_keys[][ETH_GSTRING_LEN] = {
 264         {"\n DRIVER STATISTICS"},
 265         {"single_bit_ecc_errs"},
 266         {"double_bit_ecc_errs"},
 267         {"parity_err_cnt"},
 268         {"serious_err_cnt"},
 269         {"soft_reset_cnt"},
 270         {"fifo_full_cnt"},
 271         {"ring_0_full_cnt"},
 272         {"ring_1_full_cnt"},
 273         {"ring_2_full_cnt"},
 274         {"ring_3_full_cnt"},
 275         {"ring_4_full_cnt"},
 276         {"ring_5_full_cnt"},
 277         {"ring_6_full_cnt"},
 278         {"ring_7_full_cnt"},
 279         ("alarm_transceiver_temp_high"),
 280         ("alarm_transceiver_temp_low"),
 281         ("alarm_laser_bias_current_high"),
 282         ("alarm_laser_bias_current_low"),
 283         ("alarm_laser_output_power_high"),
 284         ("alarm_laser_output_power_low"),
 285         ("warn_transceiver_temp_high"),
 286         ("warn_transceiver_temp_low"),
 287         ("warn_laser_bias_current_high"),
 288         ("warn_laser_bias_current_low"),
 289         ("warn_laser_output_power_high"),
 290         ("warn_laser_output_power_low"),
 291         ("lro_aggregated_pkts"),
 292         ("lro_flush_both_count"),
 293         ("lro_out_of_sequence_pkts"),
 294         ("lro_flush_due_to_max_pkts"),
 295         ("lro_avg_aggr_pkts"),
 296         ("mem_alloc_fail_cnt"),
 297         ("pci_map_fail_cnt"),
 298         ("watchdog_timer_cnt"),
 299         ("mem_allocated"),
 300         ("mem_freed"),
 301         ("link_up_cnt"),
 302         ("link_down_cnt"),
 303         ("link_up_time"),
 304         ("link_down_time"),
 305         ("tx_tcode_buf_abort_cnt"),
 306         ("tx_tcode_desc_abort_cnt"),
 307         ("tx_tcode_parity_err_cnt"),
 308         ("tx_tcode_link_loss_cnt"),
 309         ("tx_tcode_list_proc_err_cnt"),
 310         ("rx_tcode_parity_err_cnt"),
 311         ("rx_tcode_abort_cnt"),
 312         ("rx_tcode_parity_abort_cnt"),
 313         ("rx_tcode_rda_fail_cnt"),
 314         ("rx_tcode_unkn_prot_cnt"),
 315         ("rx_tcode_fcs_err_cnt"),
 316         ("rx_tcode_buf_size_err_cnt"),
 317         ("rx_tcode_rxd_corrupt_cnt"),
 318         ("rx_tcode_unkn_err_cnt"),
 319         {"tda_err_cnt"},
 320         {"pfc_err_cnt"},
 321         {"pcc_err_cnt"},
 322         {"tti_err_cnt"},
 323         {"tpa_err_cnt"},
 324         {"sm_err_cnt"},
 325         {"lso_err_cnt"},
 326         {"mac_tmac_err_cnt"},
 327         {"mac_rmac_err_cnt"},
 328         {"xgxs_txgxs_err_cnt"},
 329         {"xgxs_rxgxs_err_cnt"},
 330         {"rc_err_cnt"},
 331         {"prc_pcix_err_cnt"},
 332         {"rpa_err_cnt"},
 333         {"rda_err_cnt"},
 334         {"rti_err_cnt"},
 335         {"mc_err_cnt"}
 336 };
 337
 338 #define S2IO_XENA_STAT_LEN sizeof(ethtool_xena_stats_keys)/ ETH_GSTRING_LEN
 339 #define S2IO_ENHANCED_STAT_LEN sizeof(ethtool_enhanced_stats_keys)/ \
 340                                         ETH_GSTRING_LEN
 341 #define S2IO_DRIVER_STAT_LEN sizeof(ethtool_driver_stats_keys)/ ETH_GSTRING_LEN
 342
 343 #define XFRAME_I_STAT_LEN (S2IO_XENA_STAT_LEN + S2IO_DRIVER_STAT_LEN )
 344 #define XFRAME_II_STAT_LEN (XFRAME_I_STAT_LEN + S2IO_ENHANCED_STAT_LEN )
 345
 346 #define XFRAME_I_STAT_STRINGS_LEN ( XFRAME_I_STAT_LEN * ETH_GSTRING_LEN )
 347 #define XFRAME_II_STAT_STRINGS_LEN ( XFRAME_II_STAT_LEN * ETH_GSTRING_LEN )
 348
 349 #define S2IO_TEST_LEN   sizeof(s2io_gstrings) / ETH_GSTRING_LEN
 350 #define S2IO_STRINGS_LEN        S2IO_TEST_LEN * ETH_GSTRING_LEN
 351
 352 #define S2IO_TIMER_CONF(timer, handle, arg, exp)                \
 353                         init_timer(&timer);                     \
 354                         timer.function = handle;                \
 355                         timer.data = (unsigned long) arg;       \
 356                         mod_timer(&timer, (jiffies + exp))      \
 357
 358 /* Add the vlan */
 359 static void s2io_vlan_rx_register(struct net_device *dev,
 360                                         struct vlan_group *grp)
 361 {
 362         struct s2io_nic *nic = dev->priv;
 363         unsigned long flags;
 364
 365         spin_lock_irqsave(&nic->tx_lock, flags);
 366         nic->vlgrp = grp;
 367         spin_unlock_irqrestore(&nic->tx_lock, flags);
 368 }
 369
 370 /* A flag indicating whether 'RX_PA_CFG_STRIP_VLAN_TAG' bit is set or not */
 371 static int vlan_strip_flag;
 372
 373 /*
 374  * Constants to be programmed into the Xena's registers, to configure
 375  * the XAUI.
 376  */
 377
 378 #define END_SIGN        0x0
 379 static const u64 herc_act_dtx_cfg[] = {
 380         /* Set address */
 381         0x8000051536750000ULL, 0x80000515367500E0ULL,
 382         /* Write data */
 383         0x8000051536750004ULL, 0x80000515367500E4ULL,
 384         /* Set address */
 385         0x80010515003F0000ULL, 0x80010515003F00E0ULL,
 386         /* Write data */
 387         0x80010515003F0004ULL, 0x80010515003F00E4ULL,
 388         /* Set address */
 389         0x801205150D440000ULL, 0x801205150D4400E0ULL,
 390         /* Write data */
 391         0x801205150D440004ULL, 0x801205150D4400E4ULL,
 392         /* Set address */
 393         0x80020515F2100000ULL, 0x80020515F21000E0ULL,
 394         /* Write data */
 395         0x80020515F2100004ULL, 0x80020515F21000E4ULL,
 396         /* Done */
 397         END_SIGN
 398 };
 399
 400 static const u64 xena_dtx_cfg[] = {
 401         /* Set address */
 402         0x8000051500000000ULL, 0x80000515000000E0ULL,
 403         /* Write data */
 404         0x80000515D9350004ULL, 0x80000515D93500E4ULL,
 405         /* Set address */
 406         0x8001051500000000ULL, 0x80010515000000E0ULL,
 407         /* Write data */
 408         0x80010515001E0004ULL, 0x80010515001E00E4ULL,
 409         /* Set address */
 410         0x8002051500000000ULL, 0x80020515000000E0ULL,
 411         /* Write data */
 412         0x80020515F2100004ULL, 0x80020515F21000E4ULL,
 413         END_SIGN
 414 };
 415
 416 /*
 417  * Constants for Fixing the MacAddress problem seen mostly on
 418  * Alpha machines.
 419  */
 420 static const u64 fix_mac[] = {
 421         0x0060000000000000ULL, 0x0060600000000000ULL,
 422         0x0040600000000000ULL, 0x0000600000000000ULL,
 423         0x0020600000000000ULL, 0x0060600000000000ULL,
 424         0x0020600000000000ULL, 0x0060600000000000ULL,
 425         0x0020600000000000ULL, 0x0060600000000000ULL,
 426         0x0020600000000000ULL, 0x0060600000000000ULL,
 427         0x0020600000000000ULL, 0x0060600000000000ULL,
 428         0x0020600000000000ULL, 0x0060600000000000ULL,
 429         0x0020600000000000ULL, 0x0060600000000000ULL,
 430         0x0020600000000000ULL, 0x0060600000000000ULL,
 431         0x0020600000000000ULL, 0x0060600000000000ULL,
 432         0x0020600000000000ULL, 0x0060600000000000ULL,
 433         0x0020600000000000ULL, 0x0000600000000000ULL,
 434         0x0040600000000000ULL, 0x0060600000000000ULL,
 435         END_SIGN
 436 };
 437
 438 MODULE_LICENSE("GPL");
 439 MODULE_VERSION(DRV_VERSION);
 440
 441
 442 /* Module Loadable parameters. */
 443 S2IO_PARM_INT(tx_fifo_num, 1);
 444 S2IO_PARM_INT(rx_ring_num, 1);
 445
 446
 447 S2IO_PARM_INT(rx_ring_mode, 1);
 448 S2IO_PARM_INT(use_continuous_tx_intrs, 1);
 449 S2IO_PARM_INT(rmac_pause_time, 0x100);
 450 S2IO_PARM_INT(mc_pause_threshold_q0q3, 187);
 451 S2IO_PARM_INT(mc_pause_threshold_q4q7, 187);
 452 S2IO_PARM_INT(shared_splits, 0);
 453 S2IO_PARM_INT(tmac_util_period, 5);
 454 S2IO_PARM_INT(rmac_util_period, 5);
 455 S2IO_PARM_INT(bimodal, 0);
 456 S2IO_PARM_INT(l3l4hdr_size, 128);
 457 /* Frequency of Rx desc syncs expressed as power of 2 */
 458 S2IO_PARM_INT(rxsync_frequency, 3);
 459 /* Interrupt type. Values can be 0(INTA), 2(MSI_X) */
 460 S2IO_PARM_INT(intr_type, 2);
 461 /* Large receive offload feature */
 462 S2IO_PARM_INT(lro, 0);
 463 /* Max pkts to be aggregated by LRO at one time. If not specified,
 464  * aggregation happens until we hit max IP pkt size(64K)
 465  */
 466 S2IO_PARM_INT(lro_max_pkts, 0xFFFF);
 467 S2IO_PARM_INT(indicate_max_pkts, 0);
 468
 469 S2IO_PARM_INT(napi, 1);
 470 S2IO_PARM_INT(ufo, 0);
 471 S2IO_PARM_INT(vlan_tag_strip, NO_STRIP_IN_PROMISC);
 472
 473 static unsigned int tx_fifo_len[MAX_TX_FIFOS] =
 474     {DEFAULT_FIFO_0_LEN, [1 ...(MAX_TX_FIFOS - 1)] = DEFAULT_FIFO_1_7_LEN};
 475 static unsigned int rx_ring_sz[MAX_RX_RINGS] =
 476     {[0 ...(MAX_RX_RINGS - 1)] = SMALL_BLK_CNT};
 477 static unsigned int rts_frm_len[MAX_RX_RINGS] =
 478     {[0 ...(MAX_RX_RINGS - 1)] = 0 };
 479
 480 module_param_array(tx_fifo_len, uint, NULL, 0);
 481 module_param_array(rx_ring_sz, uint, NULL, 0);
 482 module_param_array(rts_frm_len, uint, NULL, 0);
 483
 484 /*
 485  * S2IO device table.
 486  * This table lists all the devices that this driver supports.
 487  */
 488 static struct pci_device_id s2io_tbl[] __devinitdata = {
 489         {PCI_VENDOR_ID_S2IO, PCI_DEVICE_ID_S2IO_WIN,
 490          PCI_ANY_ID, PCI_ANY_ID},
 491         {PCI_VENDOR_ID_S2IO, PCI_DEVICE_ID_S2IO_UNI,
 492          PCI_ANY_ID, PCI_ANY_ID},
 493         {PCI_VENDOR_ID_S2IO, PCI_DEVICE_ID_HERC_WIN,
 494          PCI_ANY_ID, PCI_ANY_ID},
 495         {PCI_VENDOR_ID_S2IO, PCI_DEVICE_ID_HERC_UNI,
 496          PCI_ANY_ID, PCI_ANY_ID},
 497         {0,}
 498 };
 499
 500 MODULE_DEVICE_TABLE(pci, s2io_tbl);
 501
 502 static struct pci_error_handlers s2io_err_handler = {
 503         .error_detected = s2io_io_error_detected,
 504         .slot_reset = s2io_io_slot_reset,
 505         .resume = s2io_io_resume,
 506 };
 507
 508 static struct pci_driver s2io_driver = {
 509       .name = "S2IO",
 510       .id_table = s2io_tbl,
 511       .probe = s2io_init_nic,
 512       .remove = __devexit_p(s2io_rem_nic),
 513       .err_handler = &s2io_err_handler,
 514 };
 515
 516 /* A simplifier macro used both by init and free shared_mem Fns(). */
 517 #define TXD_MEM_PAGE_CNT(len, per_each) ((len+per_each - 1) / per_each)
 518
 519 /**
 520  * init_shared_mem - Allocation and Initialization of Memory
 521  * @nic: Device private variable.
 522  * Description: The function allocates all the memory areas shared
 523  * between the NIC and the driver. This includes Tx descriptors,
 524  * Rx descriptors and the statistics block.
 525  */
 526
 527 static int init_shared_mem(struct s2io_nic *nic)
 528 {
 529         u32 size;
 530         void *tmp_v_addr, *tmp_v_addr_next;
 531         dma_addr_t tmp_p_addr, tmp_p_addr_next;
 532         struct RxD_block *pre_rxd_blk = NULL;
 533         int i, j, blk_cnt;
 534         int lst_size, lst_per_page;
 535         struct net_device *dev = nic->dev;
 536         unsigned long tmp;
 537         struct buffAdd *ba;
 538
 539         struct mac_info *mac_control;
 540         struct config_param *config;
 541         unsigned long long mem_allocated = 0;
 542
 543         mac_control = &nic->mac_control;
 544         config = &nic->config;
 545
 546
 547         /* Allocation and initialization of TXDLs in FIOFs */
 548         size = 0;
 549         for (i = 0; i < config->tx_fifo_num; i++) {
 550                 size += config->tx_cfg[i].fifo_len;
 551         }
 552         if (size > MAX_AVAILABLE_TXDS) {
 553                 DBG_PRINT(ERR_DBG, "s2io: Requested TxDs too high, ");
 554                 DBG_PRINT(ERR_DBG, "Requested: %d, max supported: 8192\n", size);
 555                 return -EINVAL;
 556         }
 557
 558         lst_size = (sizeof(struct TxD) * config->max_txds);
 559         lst_per_page = PAGE_SIZE / lst_size;
 560
 561         for (i = 0; i < config->tx_fifo_num; i++) {
 562                 int fifo_len = config->tx_cfg[i].fifo_len;
 563                 int list_holder_size = fifo_len * sizeof(struct list_info_hold);
 564                 mac_control->fifos[i].list_info = kmalloc(list_holder_size,
 565                                                           GFP_KERNEL);
 566                 if (!mac_control->fifos[i].list_info) {
 567                         DBG_PRINT(INFO_DBG,
 568                                   "Malloc failed for list_info\n");
 569                         return -ENOMEM;
 570                 }
 571                 mem_allocated += list_holder_size;
 572                 memset(mac_control->fifos[i].list_info, 0, list_holder_size);
 573         }
 574         for (i = 0; i < config->tx_fifo_num; i++) {
 575                 int page_num = TXD_MEM_PAGE_CNT(config->tx_cfg[i].fifo_len,
 576                                                 lst_per_page);
 577                 mac_control->fifos[i].tx_curr_put_info.offset = 0;
 578                 mac_control->fifos[i].tx_curr_put_info.fifo_len =
 579                     config->tx_cfg[i].fifo_len - 1;
 580                 mac_control->fifos[i].tx_curr_get_info.offset = 0;
 581                 mac_control->fifos[i].tx_curr_get_info.fifo_len =
 582                     config->tx_cfg[i].fifo_len - 1;
 583                 mac_control->fifos[i].fifo_no = i;
 584                 mac_control->fifos[i].nic = nic;
 585                 mac_control->fifos[i].max_txds = MAX_SKB_FRAGS + 2;
 586
 587                 for (j = 0; j < page_num; j++) {
 588                         int k = 0;
 589                         dma_addr_t tmp_p;
 590                         void *tmp_v;
 591                         tmp_v = pci_alloc_consistent(nic->pdev,
 592                                                      PAGE_SIZE, &tmp_p);
 593                         if (!tmp_v) {
 594                                 DBG_PRINT(INFO_DBG,
 595                                           "pci_alloc_consistent ");
 596                                 DBG_PRINT(INFO_DBG, "failed for TxDL\n");
 597                                 return -ENOMEM;
 598                         }
 599                         /* If we got a zero DMA address(can happen on
 600                          * certain platforms like PPC), reallocate.
 601                          * Store virtual address of page we don't want,
 602                          * to be freed later.
 603                          */
 604                         if (!tmp_p) {
 605                                 mac_control->zerodma_virt_addr = tmp_v;
 606                                 DBG_PRINT(INIT_DBG,
 607                                 "%s: Zero DMA address for TxDL. ", dev->name);
 608                                 DBG_PRINT(INIT_DBG,
 609                                 "Virtual address %p\n", tmp_v);
 610                                 tmp_v = pci_alloc_consistent(nic->pdev,
 611                                                      PAGE_SIZE, &tmp_p);
 612                                 if (!tmp_v) {
 613                                         DBG_PRINT(INFO_DBG,
 614                                           "pci_alloc_consistent ");
 615                                         DBG_PRINT(INFO_DBG, "failed for TxDL\n");
 616                                         return -ENOMEM;
 617                                 }
 618                                 mem_allocated += PAGE_SIZE;
 619                         }
 620                         while (k < lst_per_page) {
 621                                 int l = (j * lst_per_page) + k;
 622                                 if (l == config->tx_cfg[i].fifo_len)
 623                                         break;
 624                                 mac_control->fifos[i].list_info[l].list_virt_addr =
 625                                     tmp_v + (k * lst_size);
 626                                 mac_control->fifos[i].list_info[l].list_phy_addr =
 627                                     tmp_p + (k * lst_size);
 628                                 k++;
 629                         }
 630                 }
 631         }
 632
 633         nic->ufo_in_band_v = kcalloc(size, sizeof(u64), GFP_KERNEL);
 634         if (!nic->ufo_in_band_v)
 635                 return -ENOMEM;
 636          mem_allocated += (size * sizeof(u64));
 637
 638         /* Allocation and initialization of RXDs in Rings */
 639         size = 0;
 640         for (i = 0; i < config->rx_ring_num; i++) {
 641                 if (config->rx_cfg[i].num_rxd %
 642                     (rxd_count[nic->rxd_mode] + 1)) {
 643                         DBG_PRINT(ERR_DBG, "%s: RxD count of ", dev->name);
 644                         DBG_PRINT(ERR_DBG, "Ring%d is not a multiple of ",
 645                                   i);
 646                         DBG_PRINT(ERR_DBG, "RxDs per Block");
 647                         return FAILURE;
 648                 }
 649                 size += config->rx_cfg[i].num_rxd;
 650                 mac_control->rings[i].block_count =
 651                         config->rx_cfg[i].num_rxd /
 652                         (rxd_count[nic->rxd_mode] + 1 );
 653                 mac_control->rings[i].pkt_cnt = config->rx_cfg[i].num_rxd -
 654                         mac_control->rings[i].block_count;
 655         }
 656         if (nic->rxd_mode == RXD_MODE_1)
 657                 size = (size * (sizeof(struct RxD1)));
 658         else
 659                 size = (size * (sizeof(struct RxD3)));
 660
 661         for (i = 0; i < config->rx_ring_num; i++) {
 662                 mac_control->rings[i].rx_curr_get_info.block_index = 0;
 663                 mac_control->rings[i].rx_curr_get_info.offset = 0;
 664                 mac_control->rings[i].rx_curr_get_info.ring_len =
 665                     config->rx_cfg[i].num_rxd - 1;
 666                 mac_control->rings[i].rx_curr_put_info.block_index = 0;
 667                 mac_control->rings[i].rx_curr_put_info.offset = 0;
 668                 mac_control->rings[i].rx_curr_put_info.ring_len =
 669                     config->rx_cfg[i].num_rxd - 1;
 670                 mac_control->rings[i].nic = nic;
 671                 mac_control->rings[i].ring_no = i;
 672
 673                 blk_cnt = config->rx_cfg[i].num_rxd /
 674                                 (rxd_count[nic->rxd_mode] + 1);
 675                 /*  Allocating all the Rx blocks */
 676                 for (j = 0; j < blk_cnt; j++) {
 677                         struct rx_block_info *rx_blocks;
 678                         int l;
 679
 680                         rx_blocks = &mac_control->rings[i].rx_blocks[j];
 681                         size = SIZE_OF_BLOCK; //size is always page size
 682                         tmp_v_addr = pci_alloc_consistent(nic->pdev, size,
 683                                                           &tmp_p_addr);
 684                         if (tmp_v_addr == NULL) {
 685                                 /*
 686                                  * In case of failure, free_shared_mem()
 687                                  * is called, which should free any
 688                                  * memory that was alloced till the
 689                                  * failure happened.
 690                                  */
 691                                 rx_blocks->block_virt_addr = tmp_v_addr;
 692                                 return -ENOMEM;
 693                         }
 694                         mem_allocated += size;
 695                         memset(tmp_v_addr, 0, size);
 696                         rx_blocks->block_virt_addr = tmp_v_addr;
 697                         rx_blocks->block_dma_addr = tmp_p_addr;
 698                         rx_blocks->rxds = kmalloc(sizeof(struct rxd_info)*
 699                                                   rxd_count[nic->rxd_mode],
 700                                                   GFP_KERNEL);
 701                         if (!rx_blocks->rxds)
 702                                 return -ENOMEM;
 703                         mem_allocated +=
 704                         (sizeof(struct rxd_info)* rxd_count[nic->rxd_mode]);
 705                         for (l=0; l<rxd_count[nic->rxd_mode];l++) {
 706                                 rx_blocks->rxds[l].virt_addr =
 707                                         rx_blocks->block_virt_addr +
 708                                         (rxd_size[nic->rxd_mode] * l);
 709                                 rx_blocks->rxds[l].dma_addr =
 710                                         rx_blocks->block_dma_addr +
 711                                         (rxd_size[nic->rxd_mode] * l);
 712                         }
 713                 }
 714                 /* Interlinking all Rx Blocks */
 715                 for (j = 0; j < blk_cnt; j++) {
 716                         tmp_v_addr =
 717                                 mac_control->rings[i].rx_blocks[j].block_virt_addr;
 718                         tmp_v_addr_next =
 719                                 mac_control->rings[i].rx_blocks[(j + 1) %
 720                                               blk_cnt].block_virt_addr;
 721                         tmp_p_addr =
 722                                 mac_control->rings[i].rx_blocks[j].block_dma_addr;
 723                         tmp_p_addr_next =
 724                                 mac_control->rings[i].rx_blocks[(j + 1) %
 725                                               blk_cnt].block_dma_addr;
 726
 727                         pre_rxd_blk = (struct RxD_block *) tmp_v_addr;
 728                         pre_rxd_blk->reserved_2_pNext_RxD_block =
 729                             (unsigned long) tmp_v_addr_next;
 730                         pre_rxd_blk->pNext_RxD_Blk_physical =
 731                             (u64) tmp_p_addr_next;
 732                 }
 733         }
 734         if (nic->rxd_mode == RXD_MODE_3B) {
 735                 /*
 736                  * Allocation of Storages for buffer addresses in 2BUFF mode
 737                  * and the buffers as well.
 738                  */
 739                 for (i = 0; i < config->rx_ring_num; i++) {
 740                         blk_cnt = config->rx_cfg[i].num_rxd /
 741                            (rxd_count[nic->rxd_mode]+ 1);
 742                         mac_control->rings[i].ba =
 743                                 kmalloc((sizeof(struct buffAdd *) * blk_cnt),
 744                                      GFP_KERNEL);
 745                         if (!mac_control->rings[i].ba)
 746                                 return -ENOMEM;
 747                         mem_allocated +=(sizeof(struct buffAdd *) * blk_cnt);
 748                         for (j = 0; j < blk_cnt; j++) {
 749                                 int k = 0;
 750                                 mac_control->rings[i].ba[j] =
 751                                         kmalloc((sizeof(struct buffAdd) *
 752                                                 (rxd_count[nic->rxd_mode] + 1)),
 753                                                 GFP_KERNEL);
 754                                 if (!mac_control->rings[i].ba[j])
 755                                         return -ENOMEM;
 756                                 mem_allocated += (sizeof(struct buffAdd) *  \
 757                                         (rxd_count[nic->rxd_mode] + 1));
 758                                 while (k != rxd_count[nic->rxd_mode]) {
 759                                         ba = &mac_control->rings[i].ba[j][k];
 760
 761                                         ba->ba_0_org = (void *) kmalloc
 762                                             (BUF0_LEN + ALIGN_SIZE, GFP_KERNEL);
 763                                         if (!ba->ba_0_org)
 764                                                 return -ENOMEM;
 765                                         mem_allocated +=
 766                                                 (BUF0_LEN + ALIGN_SIZE);
 767                                         tmp = (unsigned long)ba->ba_0_org;
 768                                         tmp += ALIGN_SIZE;
 769                                         tmp &= ~((unsigned long) ALIGN_SIZE);
 770                                         ba->ba_0 = (void *) tmp;
 771
 772                                         ba->ba_1_org = (void *) kmalloc
 773                                             (BUF1_LEN + ALIGN_SIZE, GFP_KERNEL);
 774                                         if (!ba->ba_1_org)
 775                                                 return -ENOMEM;
 776                                         mem_allocated
 777                                                 += (BUF1_LEN + ALIGN_SIZE);
 778                                         tmp = (unsigned long) ba->ba_1_org;
 779                                         tmp += ALIGN_SIZE;
 780                                         tmp &= ~((unsigned long) ALIGN_SIZE);
 781                                         ba->ba_1 = (void *) tmp;
 782                                         k++;
 783                                 }
 784                         }
 785                 }
 786         }
 787
 788         /* Allocation and initialization of Statistics block */
 789         size = sizeof(struct stat_block);
 790         mac_control->stats_mem = pci_alloc_consistent
 791             (nic->pdev, size, &mac_control->stats_mem_phy);
 792
 793         if (!mac_control->stats_mem) {
 794                 /*
 795                  * In case of failure, free_shared_mem() is called, which
 796                  * should free any memory that was alloced till the
 797                  * failure happened.
 798                  */
 799                 return -ENOMEM;
 800         }
 801         mem_allocated += size;
 802         mac_control->stats_mem_sz = size;
 803
 804         tmp_v_addr = mac_control->stats_mem;
 805         mac_control->stats_info = (struct stat_block *) tmp_v_addr;
 806         memset(tmp_v_addr, 0, size);
 807         DBG_PRINT(INIT_DBG, "%s:Ring Mem PHY: 0x%llx\n", dev->name,
 808                   (unsigned long long) tmp_p_addr);
 809         mac_control->stats_info->sw_stat.mem_allocated += mem_allocated;
 810         return SUCCESS;
 811 }
 812
 813 /**
 814  * free_shared_mem - Free the allocated Memory
 815  * @nic:  Device private variable.
 816  * Description: This function is to free all memory locations allocated by
 817  * the init_shared_mem() function and return it to the kernel.
 818  */
 819
 820 static void free_shared_mem(struct s2io_nic *nic)
 821 {
 822         int i, j, blk_cnt, size;
 823         u32 ufo_size = 0;
 824         void *tmp_v_addr;
 825         dma_addr_t tmp_p_addr;
 826         struct mac_info *mac_control;
 827         struct config_param *config;
 828         int lst_size, lst_per_page;
 829         struct net_device *dev;
 830         int page_num = 0;
 831
 832         if (!nic)
 833                 return;
 834
 835         dev = nic->dev;
 836
 837         mac_control = &nic->mac_control;
 838         config = &nic->config;
 839
 840         lst_size = (sizeof(struct TxD) * config->max_txds);
 841         lst_per_page = PAGE_SIZE / lst_size;
 842
 843         for (i = 0; i < config->tx_fifo_num; i++) {
 844                 ufo_size += config->tx_cfg[i].fifo_len;
 845                 page_num = TXD_MEM_PAGE_CNT(config->tx_cfg[i].fifo_len,
 846                                                         lst_per_page);
 847                 for (j = 0; j < page_num; j++) {
 848                         int mem_blks = (j * lst_per_page);
 849                         if (!mac_control->fifos[i].list_info)
 850                                 return;
 851                         if (!mac_control->fifos[i].list_info[mem_blks].
 852                                  list_virt_addr)
 853                                 break;
 854                         pci_free_consistent(nic->pdev, PAGE_SIZE,
 855                                             mac_control->fifos[i].
 856                                             list_info[mem_blks].
 857                                             list_virt_addr,
 858                                             mac_control->fifos[i].
 859                                             list_info[mem_blks].
 860                                             list_phy_addr);
 861                         nic->mac_control.stats_info->sw_stat.mem_freed
 862                                                 += PAGE_SIZE;
 863                 }
 864                 /* If we got a zero DMA address during allocation,
 865                  * free the page now
 866                  */
 867                 if (mac_control->zerodma_virt_addr) {
 868                         pci_free_consistent(nic->pdev, PAGE_SIZE,
 869                                             mac_control->zerodma_virt_addr,
 870                                             (dma_addr_t)0);
 871                         DBG_PRINT(INIT_DBG,
 872                                 "%s: Freeing TxDL with zero DMA addr. ",
 873                                 dev->name);
 874                         DBG_PRINT(INIT_DBG, "Virtual address %p\n",
 875                                 mac_control->zerodma_virt_addr);
 876                         nic->mac_control.stats_info->sw_stat.mem_freed
 877                                                 += PAGE_SIZE;
 878                 }
 879                 kfree(mac_control->fifos[i].list_info);
 880                 nic->mac_control.stats_info->sw_stat.mem_freed +=
 881                 (nic->config.tx_cfg[i].fifo_len *sizeof(struct list_info_hold));
 882         }
 883
 884         size = SIZE_OF_BLOCK;
 885         for (i = 0; i < config->rx_ring_num; i++) {
 886                 blk_cnt = mac_control->rings[i].block_count;
 887                 for (j = 0; j < blk_cnt; j++) {
 888                         tmp_v_addr = mac_control->rings[i].rx_blocks[j].
 889                                 block_virt_addr;
 890                         tmp_p_addr = mac_control->rings[i].rx_blocks[j].
 891                                 block_dma_addr;
 892                         if (tmp_v_addr == NULL)
 893                                 break;
 894                         pci_free_consistent(nic->pdev, size,
 895                                             tmp_v_addr, tmp_p_addr);
 896                         nic->mac_control.stats_info->sw_stat.mem_freed += size;
 897                         kfree(mac_control->rings[i].rx_blocks[j].rxds);
 898                         nic->mac_control.stats_info->sw_stat.mem_freed +=
 899                         ( sizeof(struct rxd_info)* rxd_count[nic->rxd_mode]);
 900                 }
 901         }
 902
 903         if (nic->rxd_mode == RXD_MODE_3B) {
 904                 /* Freeing buffer storage addresses in 2BUFF mode. */
 905                 for (i = 0; i < config->rx_ring_num; i++) {
 906                         blk_cnt = config->rx_cfg[i].num_rxd /
 907                             (rxd_count[nic->rxd_mode] + 1);
 908                         for (j = 0; j < blk_cnt; j++) {
 909                                 int k = 0;
 910                                 if (!mac_control->rings[i].ba[j])
 911                                         continue;
 912                                 while (k != rxd_count[nic->rxd_mode]) {
 913                                         struct buffAdd *ba =
 914                                                 &mac_control->rings[i].ba[j][k];
 915                                         kfree(ba->ba_0_org);
 916                                         nic->mac_control.stats_info->sw_stat.\
 917                                         mem_freed += (BUF0_LEN + ALIGN_SIZE);
 918                                         kfree(ba->ba_1_org);
 919                                         nic->mac_control.stats_info->sw_stat.\
 920                                         mem_freed += (BUF1_LEN + ALIGN_SIZE);
 921                                         k++;
 922                                 }
 923                                 kfree(mac_control->rings[i].ba[j]);
 924                                 nic->mac_control.stats_info->sw_stat.mem_freed +=
 925                                         (sizeof(struct buffAdd) *
 926                                         (rxd_count[nic->rxd_mode] + 1));
 927                         }
 928                         kfree(mac_control->rings[i].ba);
 929                         nic->mac_control.stats_info->sw_stat.mem_freed +=
 930                         (sizeof(struct buffAdd *) * blk_cnt);
 931                 }
 932         }
 933
 934         if (mac_control->stats_mem) {
 935                 pci_free_consistent(nic->pdev,
 936                                     mac_control->stats_mem_sz,
 937                                     mac_control->stats_mem,
 938                                     mac_control->stats_mem_phy);
 939                 nic->mac_control.stats_info->sw_stat.mem_freed +=
 940                         mac_control->stats_mem_sz;
 941         }
 942         if (nic->ufo_in_band_v) {
 943                 kfree(nic->ufo_in_band_v);
 944                 nic->mac_control.stats_info->sw_stat.mem_freed
 945                         += (ufo_size * sizeof(u64));
 946         }
 947 }
 948
 949 /**
 950  * s2io_verify_pci_mode -
 951  */
 952
 953 static int s2io_verify_pci_mode(struct s2io_nic *nic)
 954 {
 955         struct XENA_dev_config __iomem *bar0 = nic->bar0;
 956         register u64 val64 = 0;
 957         int     mode;
 958
 959         val64 = readq(&bar0->pci_mode);
 960         mode = (u8)GET_PCI_MODE(val64);
 961
 962         if ( val64 & PCI_MODE_UNKNOWN_MODE)
 963                 return -1;      /* Unknown PCI mode */
 964         return mode;
 965 }
 966
 967 #define NEC_VENID   0x1033
 968 #define NEC_DEVID   0x0125
 969 static int s2io_on_nec_bridge(struct pci_dev *s2io_pdev)
 970 {
 971         struct pci_dev *tdev = NULL;
 972         while ((tdev = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, tdev)) != NULL) {
 973                 if (tdev->vendor == NEC_VENID && tdev->device == NEC_DEVID) {
 974                         if (tdev->bus == s2io_pdev->bus->parent)
 975                                 pci_dev_put(tdev);
 976                                 return 1;
 977                 }
 978         }
 979         return 0;
 980 }
 981
 982 static int bus_speed[8] = {33, 133, 133, 200, 266, 133, 200, 266};
 983 /**
 984  * s2io_print_pci_mode -
 985  */
 986 static int s2io_print_pci_mode(struct s2io_nic *nic)
 987 {
 988         struct XENA_dev_config __iomem *bar0 = nic->bar0;
 989         register u64 val64 = 0;
 990         int     mode;
 991         struct config_param *config = &nic->config;
 992
 993         val64 = readq(&bar0->pci_mode);
 994         mode = (u8)GET_PCI_MODE(val64);
 995
 996         if ( val64 & PCI_MODE_UNKNOWN_MODE)
 997                 return -1;      /* Unknown PCI mode */
 998
 999         config->bus_speed = bus_speed[mode];
1000
1001         if (s2io_on_nec_bridge(nic->pdev)) {
1002                 DBG_PRINT(ERR_DBG, "%s: Device is on PCI-E bus\n",
1003                                                         nic->dev->name);
1004                 return mode;
1005         }
1006
1007         if (val64 & PCI_MODE_32_BITS) {
1008                 DBG_PRINT(ERR_DBG, "%s: Device is on 32 bit ", nic->dev->name);
1009         } else {
1010                 DBG_PRINT(ERR_DBG, "%s: Device is on 64 bit ", nic->dev->name);
1011         }
1012
1013         switch(mode) {
1014                 case PCI_MODE_PCI_33:
1015                         DBG_PRINT(ERR_DBG, "33MHz PCI bus\n");
1016                         break;
1017                 case PCI_MODE_PCI_66:
1018                         DBG_PRINT(ERR_DBG, "66MHz PCI bus\n");
1019                         break;
1020                 case PCI_MODE_PCIX_M1_66:
1021                         DBG_PRINT(ERR_DBG, "66MHz PCIX(M1) bus\n");
1022                         break;
1023                 case PCI_MODE_PCIX_M1_100:
1024                         DBG_PRINT(ERR_DBG, "100MHz PCIX(M1) bus\n");
1025                         break;
1026                 case PCI_MODE_PCIX_M1_133:
1027                         DBG_PRINT(ERR_DBG, "133MHz PCIX(M1) bus\n");
1028                         break;
1029                 case PCI_MODE_PCIX_M2_66:
1030                         DBG_PRINT(ERR_DBG, "133MHz PCIX(M2) bus\n");
1031                         break;
1032                 case PCI_MODE_PCIX_M2_100:
1033                         DBG_PRINT(ERR_DBG, "200MHz PCIX(M2) bus\n");
1034                         break;
1035                 case PCI_MODE_PCIX_M2_133:
1036                         DBG_PRINT(ERR_DBG, "266MHz PCIX(M2) bus\n");
1037                         break;
1038                 default:
1039                         return -1;      /* Unsupported bus speed */
1040         }
1041
1042         return mode;
1043 }
1044
1045 /**
1046  *  init_nic - Initialization of hardware
1047  *  @nic: device peivate variable
1048  *  Description: The function sequentially configures every block
1049  *  of the H/W from their reset values.
1050  *  Return Value:  SUCCESS on success and
1051  *  '-1' on failure (endian settings incorrect).
1052  */
1053
1054 static int init_nic(struct s2io_nic *nic)
1055 {
1056         struct XENA_dev_config __iomem *bar0 = nic->bar0;
1057         struct net_device *dev = nic->dev;
1058         register u64 val64 = 0;
1059         void __iomem *add;
1060         u32 time;
1061         int i, j;
1062         struct mac_info *mac_control;
1063         struct config_param *config;
1064         int dtx_cnt = 0;
1065         unsigned long long mem_share;
1066         int mem_size;
1067
1068         mac_control = &nic->mac_control;
1069         config = &nic->config;
1070
1071         /* to set the swapper controle on the card */
1072         if(s2io_set_swapper(nic)) {
1073                 DBG_PRINT(ERR_DBG,"ERROR: Setting Swapper failed\n");
1074                 return -1;
1075         }
1076
1077         /*
1078          * Herc requires EOI to be removed from reset before XGXS, so..
1079          */
1080         if (nic->device_type & XFRAME_II_DEVICE) {
1081                 val64 = 0xA500000000ULL;
1082                 writeq(val64, &bar0->sw_reset);
1083                 msleep(500);
1084                 val64 = readq(&bar0->sw_reset);
1085         }
1086
1087         /* Remove XGXS from reset state */
1088         val64 = 0;
1089         writeq(val64, &bar0->sw_reset);
1090         msleep(500);
1091         val64 = readq(&bar0->sw_reset);
1092
1093         /*  Enable Receiving broadcasts */
1094         add = &bar0->mac_cfg;
1095         val64 = readq(&bar0->mac_cfg);
1096         val64 |= MAC_RMAC_BCAST_ENABLE;
1097         writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
1098         writel((u32) val64, add);
1099         writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
1100         writel((u32) (val64 >> 32), (add + 4));
1101
1102         /* Read registers in all blocks */
1103         val64 = readq(&bar0->mac_int_mask);
1104         val64 = readq(&bar0->mc_int_mask);
1105         val64 = readq(&bar0->xgxs_int_mask);
1106
1107         /*  Set MTU */
1108         val64 = dev->mtu;
1109         writeq(vBIT(val64, 2, 14), &bar0->rmac_max_pyld_len);
1110
1111         if (nic->device_type & XFRAME_II_DEVICE) {
1112                 while (herc_act_dtx_cfg[dtx_cnt] != END_SIGN) {
1113                         SPECIAL_REG_WRITE(herc_act_dtx_cfg[dtx_cnt],
1114                                           &bar0->dtx_control, UF);
1115                         if (dtx_cnt & 0x1)
1116                                 msleep(1); /* Necessary!! */
1117                         dtx_cnt++;
1118                 }
1119         } else {
1120                 while (xena_dtx_cfg[dtx_cnt] != END_SIGN) {
1121                         SPECIAL_REG_WRITE(xena_dtx_cfg[dtx_cnt],
1122                                           &bar0->dtx_control, UF);
1123                         val64 = readq(&bar0->dtx_control);
1124                         dtx_cnt++;
1125                 }
1126         }
1127
1128         /*  Tx DMA Initialization */
1129         val64 = 0;
1130         writeq(val64, &bar0->tx_fifo_partition_0);
1131         writeq(val64, &bar0->tx_fifo_partition_1);
1132         writeq(val64, &bar0->tx_fifo_partition_2);
1133         writeq(val64, &bar0->tx_fifo_partition_3);
1134
1135
1136         for (i = 0, j = 0; i < config->tx_fifo_num; i++) {
1137                 val64 |=
1138                     vBIT(config->tx_cfg[i].fifo_len - 1, ((i * 32) + 19),
1139                          13) | vBIT(config->tx_cfg[i].fifo_priority,
1140                                     ((i * 32) + 5), 3);
1141
1142                 if (i == (config->tx_fifo_num - 1)) {
1143                         if (i % 2 == 0)
1144                                 i++;
1145                 }
1146
1147                 switch (i) {
1148                 case 1:
1149                         writeq(val64, &bar0->tx_fifo_partition_0);
1150                         val64 = 0;
1151                         break;
1152                 case 3:
1153                         writeq(val64, &bar0->tx_fifo_partition_1);
1154                         val64 = 0;
1155                         break;
1156                 case 5:
1157                         writeq(val64, &bar0->tx_fifo_partition_2);
1158                         val64 = 0;
1159                         break;
1160                 case 7:
1161                         writeq(val64, &bar0->tx_fifo_partition_3);
1162                         break;
1163                 }
1164         }
1165
1166         /*
1167          * Disable 4 PCCs for Xena1, 2 and 3 as per H/W bug
1168          * SXE-008 TRANSMIT DMA ARBITRATION ISSUE.
1169          */
1170         if ((nic->device_type == XFRAME_I_DEVICE) &&
1171                 (nic->pdev->revision < 4))
1172                 writeq(PCC_ENABLE_FOUR, &bar0->pcc_enable);
1173
1174         val64 = readq(&bar0->tx_fifo_partition_0);
1175         DBG_PRINT(INIT_DBG, "Fifo partition at: 0x%p is: 0x%llx\n",
1176                   &bar0->tx_fifo_partition_0, (unsigned long long) val64);
1177
1178         /*
1179          * Initialization of Tx_PA_CONFIG register to ignore packet
1180          * integrity checking.
1181          */
1182         val64 = readq(&bar0->tx_pa_cfg);
1183         val64 |= TX_PA_CFG_IGNORE_FRM_ERR | TX_PA_CFG_IGNORE_SNAP_OUI |
1184             TX_PA_CFG_IGNORE_LLC_CTRL | TX_PA_CFG_IGNORE_L2_ERR;
1185         writeq(val64, &bar0->tx_pa_cfg);
1186
1187         /* Rx DMA intialization. */
1188         val64 = 0;
1189         for (i = 0; i < config->rx_ring_num; i++) {
1190                 val64 |=
1191                     vBIT(config->rx_cfg[i].ring_priority, (5 + (i * 8)),
1192                          3);
1193         }
1194         writeq(val64, &bar0->rx_queue_priority);
1195
1196         /*
1197          * Allocating equal share of memory to all the
1198          * configured Rings.
1199          */
1200         val64 = 0;
1201         if (nic->device_type & XFRAME_II_DEVICE)
1202                 mem_size = 32;
1203         else
1204                 mem_size = 64;
1205
1206         for (i = 0; i < config->rx_ring_num; i++) {
1207                 switch (i) {
1208                 case 0:
1209                         mem_share = (mem_size / config->rx_ring_num +
1210                                      mem_size % config->rx_ring_num);
1211                         val64 |= RX_QUEUE_CFG_Q0_SZ(mem_share);
1212                         continue;
1213                 case 1:
1214                         mem_share = (mem_size / config->rx_ring_num);
1215                         val64 |= RX_QUEUE_CFG_Q1_SZ(mem_share);
1216                         continue;
1217                 case 2:
1218                         mem_share = (mem_size / config->rx_ring_num);
1219                         val64 |= RX_QUEUE_CFG_Q2_SZ(mem_share);
1220                         continue;
1221                 case 3:
1222                         mem_share = (mem_size / config->rx_ring_num);
1223                         val64 |= RX_QUEUE_CFG_Q3_SZ(mem_share);
1224                         continue;
1225                 case 4:
1226                         mem_share = (mem_size / config->rx_ring_num);
1227                         val64 |= RX_QUEUE_CFG_Q4_SZ(mem_share);
1228                         continue;
1229                 case 5:
1230                         mem_share = (mem_size / config->rx_ring_num);
1231                         val64 |= RX_QUEUE_CFG_Q5_SZ(mem_share);
1232                         continue;
1233                 case 6:
1234                         mem_share = (mem_size / config->rx_ring_num);
1235                         val64 |= RX_QUEUE_CFG_Q6_SZ(mem_share);
1236                         continue;
1237                 case 7:
1238                         mem_share = (mem_size / config->rx_ring_num);
1239                         val64 |= RX_QUEUE_CFG_Q7_SZ(mem_share);
1240                         continue;
1241                 }
1242         }
1243         writeq(val64, &bar0->rx_queue_cfg);
1244
1245         /*
1246          * Filling Tx round robin registers
1247          * as per the number of FIFOs
1248          */
1249         switch (config->tx_fifo_num) {
1250         case 1:
1251                 val64 = 0x0000000000000000ULL;
1252                 writeq(val64, &bar0->tx_w_round_robin_0);
1253                 writeq(val64, &bar0->tx_w_round_robin_1);
1254                 writeq(val64, &bar0->tx_w_round_robin_2);
1255                 writeq(val64, &bar0->tx_w_round_robin_3);
1256                 writeq(val64, &bar0->tx_w_round_robin_4);
1257                 break;
1258         case 2:
1259                 val64 = 0x0000010000010000ULL;
1260                 writeq(val64, &bar0->tx_w_round_robin_0);
1261                 val64 = 0x0100000100000100ULL;
1262                 writeq(val64, &bar0->tx_w_round_robin_1);
1263                 val64 = 0x0001000001000001ULL;
1264                 writeq(val64, &bar0->tx_w_round_robin_2);
1265                 val64 = 0x0000010000010000ULL;
1266                 writeq(val64, &bar0->tx_w_round_robin_3);
1267                 val64 = 0x0100000000000000ULL;
1268                 writeq(val64, &bar0->tx_w_round_robin_4);
1269                 break;
1270         case 3:
1271                 val64 = 0x0001000102000001ULL;
1272                 writeq(val64, &bar0->tx_w_round_robin_0);
1273                 val64 = 0x0001020000010001ULL;
1274                 writeq(val64, &bar0->tx_w_round_robin_1);
1275                 val64 = 0x0200000100010200ULL;
1276                 writeq(val64, &bar0->tx_w_round_robin_2);
1277                 val64 = 0x0001000102000001ULL;
1278                 writeq(val64, &bar0->tx_w_round_robin_3);
1279                 val64 = 0x0001020000000000ULL;
1280                 writeq(val64, &bar0->tx_w_round_robin_4);
1281                 break;
1282         case 4:
1283                 val64 = 0x0001020300010200ULL;
1284                 writeq(val64, &bar0->tx_w_round_robin_0);
1285                 val64 = 0x0100000102030001ULL;
1286                 writeq(val64, &bar0->tx_w_round_robin_1);
1287                 val64 = 0x0200010000010203ULL;
1288                 writeq(val64, &bar0->tx_w_round_robin_2);
1289                 val64 = 0x0001020001000001ULL;
1290                 writeq(val64, &bar0->tx_w_round_robin_3);
1291                 val64 = 0x0203000100000000ULL;
1292                 writeq(val64, &bar0->tx_w_round_robin_4);
1293                 break;
1294         case 5:
1295                 val64 = 0x0001000203000102ULL;
1296                 writeq(val64, &bar0->tx_w_round_robin_0);
1297                 val64 = 0x0001020001030004ULL;
1298                 writeq(val64, &bar0->tx_w_round_robin_1);
1299                 val64 = 0x0001000203000102ULL;
1300                 writeq(val64, &bar0->tx_w_round_robin_2);
1301                 val64 = 0x0001020001030004ULL;
1302                 writeq(val64, &bar0->tx_w_round_robin_3);
1303                 val64 = 0x0001000000000000ULL;
1304                 writeq(val64, &bar0->tx_w_round_robin_4);
1305                 break;
1306         case 6:
1307                 val64 = 0x0001020304000102ULL;
1308                 writeq(val64, &bar0->tx_w_round_robin_0);
1309                 val64 = 0x0304050001020001ULL;
1310                 writeq(val64, &bar0->tx_w_round_robin_1);
1311                 val64 = 0x0203000100000102ULL;
1312                 writeq(val64, &bar0->tx_w_round_robin_2);
1313                 val64 = 0x0304000102030405ULL;
1314                 writeq(val64, &bar0->tx_w_round_robin_3);
1315                 val64 = 0x0001000200000000ULL;
1316                 writeq(val64, &bar0->tx_w_round_robin_4);
1317                 break;
1318         case 7:
1319                 val64 = 0x0001020001020300ULL;
1320                 writeq(val64, &bar0->tx_w_round_robin_0);
1321                 val64 = 0x0102030400010203ULL;
1322                 writeq(val64, &bar0->tx_w_round_robin_1);
1323                 val64 = 0x0405060001020001ULL;
1324                 writeq(val64, &bar0->tx_w_round_robin_2);
1325                 val64 = 0x0304050000010200ULL;
1326                 writeq(val64, &bar0->tx_w_round_robin_3);
1327                 val64 = 0x0102030000000000ULL;
1328                 writeq(val64, &bar0->tx_w_round_robin_4);
1329                 break;
1330         case 8:
1331                 val64 = 0x0001020300040105ULL;
1332                 writeq(val64, &bar0->tx_w_round_robin_0);
1333                 val64 = 0x0200030106000204ULL;
1334                 writeq(val64, &bar0->tx_w_round_robin_1);
1335                 val64 = 0x0103000502010007ULL;
1336                 writeq(val64, &bar0->tx_w_round_robin_2);
1337                 val64 = 0x0304010002060500ULL;
1338                 writeq(val64, &bar0->tx_w_round_robin_3);
1339                 val64 = 0x0103020400000000ULL;
1340                 writeq(val64, &bar0->tx_w_round_robin_4);
1341                 break;
1342         }
1343
1344         /* Enable all configured Tx FIFO partitions */
1345         val64 = readq(&bar0->tx_fifo_partition_0);
1346         val64 |= (TX_FIFO_PARTITION_EN);
1347         writeq(val64, &bar0->tx_fifo_partition_0);
1348
1349         /* Filling the Rx round robin registers as per the
1350          * number of Rings and steering based on QoS.
1351          */
1352         switch (config->rx_ring_num) {
1353         case 1:
1354                 val64 = 0x8080808080808080ULL;
1355                 writeq(val64, &bar0->rts_qos_steering);
1356                 break;
1357         case 2:
1358                 val64 = 0x0000010000010000ULL;
1359                 writeq(val64, &bar0->rx_w_round_robin_0);
1360                 val64 = 0x0100000100000100ULL;
1361                 writeq(val64, &bar0->rx_w_round_robin_1);
1362                 val64 = 0x0001000001000001ULL;
1363                 writeq(val64, &bar0->rx_w_round_robin_2);
1364                 val64 = 0x0000010000010000ULL;
1365                 writeq(val64, &bar0->rx_w_round_robin_3);
1366                 val64 = 0x0100000000000000ULL;
1367                 writeq(val64, &bar0->rx_w_round_robin_4);
1368
1369                 val64 = 0x8080808040404040ULL;
1370                 writeq(val64, &bar0->rts_qos_steering);
1371                 break;
1372         case 3:
1373                 val64 = 0x0001000102000001ULL;
1374                 writeq(val64, &bar0->rx_w_round_robin_0);
1375                 val64 = 0x0001020000010001ULL;
1376                 writeq(val64, &bar0->rx_w_round_robin_1);
1377                 val64 = 0x0200000100010200ULL;
1378                 writeq(val64, &bar0->rx_w_round_robin_2);
1379                 val64 = 0x0001000102000001ULL;
1380                 writeq(val64, &bar0->rx_w_round_robin_3);
1381                 val64 = 0x0001020000000000ULL;
1382                 writeq(val64, &bar0->rx_w_round_robin_4);
1383
1384                 val64 = 0x8080804040402020ULL;
1385                 writeq(val64, &bar0->rts_qos_steering);
1386                 break;
1387         case 4:
1388                 val64 = 0x0001020300010200ULL;
1389                 writeq(val64, &bar0->rx_w_round_robin_0);
1390                 val64 = 0x0100000102030001ULL;
1391                 writeq(val64, &bar0->rx_w_round_robin_1);
1392                 val64 = 0x0200010000010203ULL;
1393                 writeq(val64, &bar0->rx_w_round_robin_2);
1394                 val64 = 0x0001020001000001ULL;
1395                 writeq(val64, &bar0->rx_w_round_robin_3);
1396                 val64 = 0x0203000100000000ULL;
1397                 writeq(val64, &bar0->rx_w_round_robin_4);
1398
1399                 val64 = 0x8080404020201010ULL;
1400                 writeq(val64, &bar0->rts_qos_steering);
1401                 break;
1402         case 5:
1403                 val64 = 0x0001000203000102ULL;
1404                 writeq(val64, &bar0->rx_w_round_robin_0);
1405                 val64 = 0x0001020001030004ULL;
1406                 writeq(val64, &bar0->rx_w_round_robin_1);
1407                 val64 = 0x0001000203000102ULL;
1408                 writeq(val64, &bar0->rx_w_round_robin_2);
1409                 val64 = 0x0001020001030004ULL;
1410                 writeq(val64, &bar0->rx_w_round_robin_3);
1411                 val64 = 0x0001000000000000ULL;
1412                 writeq(val64, &bar0->rx_w_round_robin_4);
1413
1414                 val64 = 0x8080404020201008ULL;
1415                 writeq(val64, &bar0->rts_qos_steering);
1416                 break;
1417         case 6:
1418                 val64 = 0x0001020304000102ULL;
1419                 writeq(val64, &bar0->rx_w_round_robin_0);
1420                 val64 = 0x0304050001020001ULL;
1421                 writeq(val64, &bar0->rx_w_round_robin_1);
1422                 val64 = 0x0203000100000102ULL;
1423                 writeq(val64, &bar0->rx_w_round_robin_2);
1424                 val64 = 0x0304000102030405ULL;
1425                 writeq(val64, &bar0->rx_w_round_robin_3);
1426                 val64 = 0x0001000200000000ULL;
1427                 writeq(val64, &bar0->rx_w_round_robin_4);
1428
1429                 val64 = 0x8080404020100804ULL;
1430                 writeq(val64, &bar0->rts_qos_steering);
1431                 break;
1432         case 7:
1433                 val64 = 0x0001020001020300ULL;
1434                 writeq(val64, &bar0->rx_w_round_robin_0);
1435                 val64 = 0x0102030400010203ULL;
1436                 writeq(val64, &bar0->rx_w_round_robin_1);
1437                 val64 = 0x0405060001020001ULL;
1438                 writeq(val64, &bar0->rx_w_round_robin_2);
1439                 val64 = 0x0304050000010200ULL;
1440                 writeq(val64, &bar0->rx_w_round_robin_3);
1441                 val64 = 0x0102030000000000ULL;
1442                 writeq(val64, &bar0->rx_w_round_robin_4);
1443
1444                 val64 = 0x8080402010080402ULL;
1445                 writeq(val64, &bar0->rts_qos_steering);
1446                 break;
1447         case 8:
1448                 val64 = 0x0001020300040105ULL;
1449                 writeq(val64, &bar0->rx_w_round_robin_0);
1450                 val64 = 0x0200030106000204ULL;
1451                 writeq(val64, &bar0->rx_w_round_robin_1);
1452                 val64 = 0x0103000502010007ULL;
1453                 writeq(val64, &bar0->rx_w_round_robin_2);
1454                 val64 = 0x0304010002060500ULL;
1455                 writeq(val64, &bar0->rx_w_round_robin_3);
1456                 val64 = 0x0103020400000000ULL;
1457                 writeq(val64, &bar0->rx_w_round_robin_4);
1458
1459                 val64 = 0x8040201008040201ULL;
1460                 writeq(val64, &bar0->rts_qos_steering);
1461                 break;
1462         }
1463
1464         /* UDP Fix */
1465         val64 = 0;
1466         for (i = 0; i < 8; i++)
1467                 writeq(val64, &bar0->rts_frm_len_n[i]);
1468
1469         /* Set the default rts frame length for the rings configured */
1470         val64 = MAC_RTS_FRM_LEN_SET(dev->mtu+22);
1471         for (i = 0 ; i < config->rx_ring_num ; i++)
1472                 writeq(val64, &bar0->rts_frm_len_n[i]);
1473
1474         /* Set the frame length for the configured rings
1475          * desired by the user
1476          */
1477         for (i = 0; i < config->rx_ring_num; i++) {
1478                 /* If rts_frm_len[i] == 0 then it is assumed that user not
1479                  * specified frame length steering.
1480                  * If the user provides the frame length then program
1481                  * the rts_frm_len register for those values or else
1482                  * leave it as it is.
1483                  */
1484                 if (rts_frm_len[i] != 0) {
1485                         writeq(MAC_RTS_FRM_LEN_SET(rts_frm_len[i]),
1486                                 &bar0->rts_frm_len_n[i]);
1487                 }
1488         }
1489
1490         /* Disable differentiated services steering logic */
1491         for (i = 0; i < 64; i++) {
1492                 if (rts_ds_steer(nic, i, 0) == FAILURE) {
1493                         DBG_PRINT(ERR_DBG, "%s: failed rts ds steering",
1494                                 dev->name);
1495                         DBG_PRINT(ERR_DBG, "set on codepoint %d\n", i);
1496                         return FAILURE;
1497                 }
1498         }
1499
1500         /* Program statistics memory */
1501         writeq(mac_control->stats_mem_phy, &bar0->stat_addr);
1502
1503         if (nic->device_type == XFRAME_II_DEVICE) {
1504                 val64 = STAT_BC(0x320);
1505                 writeq(val64, &bar0->stat_byte_cnt);
1506         }
1507
1508         /*
1509          * Initializing the sampling rate for the device to calculate the
1510          * bandwidth utilization.
1511          */
1512         val64 = MAC_TX_LINK_UTIL_VAL(tmac_util_period) |
1513             MAC_RX_LINK_UTIL_VAL(rmac_util_period);
1514         writeq(val64, &bar0->mac_link_util);
1515
1516
1517         /*
1518          * Initializing the Transmit and Receive Traffic Interrupt
1519          * Scheme.
1520          */
1521         /*
1522          * TTI Initialization. Default Tx timer gets us about
1523          * 250 interrupts per sec. Continuous interrupts are enabled
1524          * by default.
1525          */
1526         if (nic->device_type == XFRAME_II_DEVICE) {
1527                 int count = (nic->config.bus_speed * 125)/2;
1528                 val64 = TTI_DATA1_MEM_TX_TIMER_VAL(count);
1529         } else {
1530
1531                 val64 = TTI_DATA1_MEM_TX_TIMER_VAL(0x2078);
1532         }
1533         val64 |= TTI_DATA1_MEM_TX_URNG_A(0xA) |
1534             TTI_DATA1_MEM_TX_URNG_B(0x10) |
1535             TTI_DATA1_MEM_TX_URNG_C(0x30) | TTI_DATA1_MEM_TX_TIMER_AC_EN;
1536                 if (use_continuous_tx_intrs)
1537                         val64 |= TTI_DATA1_MEM_TX_TIMER_CI_EN;
1538         writeq(val64, &bar0->tti_data1_mem);
1539
1540         val64 = TTI_DATA2_MEM_TX_UFC_A(0x10) |
1541             TTI_DATA2_MEM_TX_UFC_B(0x20) |
1542             TTI_DATA2_MEM_TX_UFC_C(0x40) | TTI_DATA2_MEM_TX_UFC_D(0x80);
1543         writeq(val64, &bar0->tti_data2_mem);
1544
1545         val64 = TTI_CMD_MEM_WE | TTI_CMD_MEM_STROBE_NEW_CMD;
1546         writeq(val64, &bar0->tti_command_mem);
1547
1548         /*
1549          * Once the operation completes, the Strobe bit of the command
1550          * register will be reset. We poll for this particular condition
1551          * We wait for a maximum of 500ms for the operation to complete,
1552          * if it's not complete by then we return error.
1553          */
1554         time = 0;
1555         while (TRUE) {
1556                 val64 = readq(&bar0->tti_command_mem);
1557                 if (!(val64 & TTI_CMD_MEM_STROBE_NEW_CMD)) {
1558                         break;
1559                 }
1560                 if (time > 10) {
1561                         DBG_PRINT(ERR_DBG, "%s: TTI init Failed\n",
1562                                   dev->name);
1563                         return -1;
1564                 }
1565                 msleep(50);
1566                 time++;
1567         }
1568
1569         if (nic->config.bimodal) {
1570                 int k = 0;
1571                 for (k = 0; k < config->rx_ring_num; k++) {
1572                         val64 = TTI_CMD_MEM_WE | TTI_CMD_MEM_STROBE_NEW_CMD;
1573                         val64 |= TTI_CMD_MEM_OFFSET(0x38+k);
1574                         writeq(val64, &bar0->tti_command_mem);
1575
1576                 /*
1577                  * Once the operation completes, the Strobe bit of the command
1578                  * register will be reset. We poll for this particular condition
1579                  * We wait for a maximum of 500ms for the operation to complete,
1580                  * if it's not complete by then we return error.
1581                 */
1582                         time = 0;
1583                         while (TRUE) {
1584                                 val64 = readq(&bar0->tti_command_mem);
1585                                 if (!(val64 & TTI_CMD_MEM_STROBE_NEW_CMD)) {
1586                                         break;
1587                                 }
1588                                 if (time > 10) {
1589                                         DBG_PRINT(ERR_DBG,
1590                                                 "%s: TTI init Failed\n",
1591                                         dev->name);
1592                                         return -1;
1593                                 }
1594                                 time++;
1595                                 msleep(50);
1596                         }
1597                 }
1598         } else {
1599
1600                 /* RTI Initialization */
1601                 if (nic->device_type == XFRAME_II_DEVICE) {
1602                         /*
1603                          * Programmed to generate Apprx 500 Intrs per
1604                          * second
1605                          */
1606                         int count = (nic->config.bus_speed * 125)/4;
1607                         val64 = RTI_DATA1_MEM_RX_TIMER_VAL(count);
1608                 } else {
1609                         val64 = RTI_DATA1_MEM_RX_TIMER_VAL(0xFFF);
1610                 }
1611                 val64 |= RTI_DATA1_MEM_RX_URNG_A(0xA) |
1612                     RTI_DATA1_MEM_RX_URNG_B(0x10) |
1613                     RTI_DATA1_MEM_RX_URNG_C(0x30) | RTI_DATA1_MEM_RX_TIMER_AC_EN;
1614
1615                 writeq(val64, &bar0->rti_data1_mem);
1616
1617                 val64 = RTI_DATA2_MEM_RX_UFC_A(0x1) |
1618                     RTI_DATA2_MEM_RX_UFC_B(0x2) ;
1619                 if (nic->config.intr_type == MSI_X)
1620                     val64 |= (RTI_DATA2_MEM_RX_UFC_C(0x20) | \
1621                                 RTI_DATA2_MEM_RX_UFC_D(0x40));
1622                 else
1623                     val64 |= (RTI_DATA2_MEM_RX_UFC_C(0x40) | \
1624                                 RTI_DATA2_MEM_RX_UFC_D(0x80));
1625                 writeq(val64, &bar0->rti_data2_mem);
1626
1627                 for (i = 0; i < config->rx_ring_num; i++) {
1628                         val64 = RTI_CMD_MEM_WE | RTI_CMD_MEM_STROBE_NEW_CMD
1629                                         | RTI_CMD_MEM_OFFSET(i);
1630                         writeq(val64, &bar0->rti_command_mem);
1631
1632                         /*
1633                          * Once the operation completes, the Strobe bit of the
1634                          * command register will be reset. We poll for this
1635                          * particular condition. We wait for a maximum of 500ms
1636                          * for the operation to complete, if it's not complete
1637                          * by then we return error.
1638                          */
1639                         time = 0;
1640                         while (TRUE) {
1641                                 val64 = readq(&bar0->rti_command_mem);
1642                                 if (!(val64 & RTI_CMD_MEM_STROBE_NEW_CMD)) {
1643                                         break;
1644                                 }
1645                                 if (time > 10) {
1646                                         DBG_PRINT(ERR_DBG, "%s: RTI init Failed\n",
1647                                                   dev->name);
1648                                         return -1;
1649                                 }
1650                                 time++;
1651                                 msleep(50);
1652                         }
1653                 }
1654         }
1655
1656         /*
1657          * Initializing proper values as Pause threshold into all
1658          * the 8 Queues on Rx side.
1659          */
1660         writeq(0xffbbffbbffbbffbbULL, &bar0->mc_pause_thresh_q0q3);
1661         writeq(0xffbbffbbffbbffbbULL, &bar0->mc_pause_thresh_q4q7);
1662
1663         /* Disable RMAC PAD STRIPPING */
1664         add = &bar0->mac_cfg;
1665         val64 = readq(&bar0->mac_cfg);
1666         val64 &= ~(MAC_CFG_RMAC_STRIP_PAD);
1667         writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
1668         writel((u32) (val64), add);
1669         writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
1670         writel((u32) (val64 >> 32), (add + 4));
1671         val64 = readq(&bar0->mac_cfg);
1672
1673         /* Enable FCS stripping by adapter */
1674         add = &bar0->mac_cfg;
1675         val64 = readq(&bar0->mac_cfg);
1676         val64 |= MAC_CFG_RMAC_STRIP_FCS;
1677         if (nic->device_type == XFRAME_II_DEVICE)
1678                 writeq(val64, &bar0->mac_cfg);
1679         else {
1680                 writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
1681                 writel((u32) (val64), add);
1682                 writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
1683                 writel((u32) (val64 >> 32), (add + 4));
1684         }
1685
1686         /*
1687          * Set the time value to be inserted in the pause frame
1688          * generated by xena.
1689          */
1690         val64 = readq(&bar0->rmac_pause_cfg);
1691         val64 &= ~(RMAC_PAUSE_HG_PTIME(0xffff));
1692         val64 |= RMAC_PAUSE_HG_PTIME(nic->mac_control.rmac_pause_time);
1693         writeq(val64, &bar0->rmac_pause_cfg);
1694
1695         /*
1696          * Set the Threshold Limit for Generating the pause frame
1697          * If the amount of data in any Queue exceeds ratio of
1698          * (mac_control.mc_pause_threshold_q0q3 or q4q7)/256
1699          * pause frame is generated
1700          */
1701         val64 = 0;
1702         for (i = 0; i < 4; i++) {
1703                 val64 |=
1704                     (((u64) 0xFF00 | nic->mac_control.
1705                       mc_pause_threshold_q0q3)
1706                      << (i * 2 * 8));
1707         }
1708         writeq(val64, &bar0->mc_pause_thresh_q0q3);
1709
1710         val64 = 0;
1711         for (i = 0; i < 4; i++) {
1712                 val64 |=
1713                     (((u64) 0xFF00 | nic->mac_control.
1714                       mc_pause_threshold_q4q7)
1715                      << (i * 2 * 8));
1716         }
1717         writeq(val64, &bar0->mc_pause_thresh_q4q7);
1718
1719         /*
1720          * TxDMA will stop Read request if the number of read split has
1721          * exceeded the limit pointed by shared_splits
1722          */
1723         val64 = readq(&bar0->pic_control);
1724         val64 |= PIC_CNTL_SHARED_SPLITS(shared_splits);
1725         writeq(val64, &bar0->pic_control);
1726
1727         if (nic->config.bus_speed == 266) {
1728                 writeq(TXREQTO_VAL(0x7f) | TXREQTO_EN, &bar0->txreqtimeout);
1729                 writeq(0x0, &bar0->read_retry_delay);
1730                 writeq(0x0, &bar0->write_retry_delay);
1731         }
1732
1733         /*
1734          * Programming the Herc to split every write transaction
1735          * that does not start on an ADB to reduce disconnects.
1736          */
1737         if (nic->device_type == XFRAME_II_DEVICE) {
1738                 val64 = FAULT_BEHAVIOUR | EXT_REQ_EN |
1739                         MISC_LINK_STABILITY_PRD(3);
1740                 writeq(val64, &bar0->misc_control);
1741                 val64 = readq(&bar0->pic_control2);
1742                 val64 &= ~(BIT(13)|BIT(14)|BIT(15));
1743                 writeq(val64, &bar0->pic_control2);
1744         }
1745         if (strstr(nic->product_name, "CX4")) {
1746                 val64 = TMAC_AVG_IPG(0x17);
1747                 writeq(val64, &bar0->tmac_avg_ipg);
1748         }
1749
1750         return SUCCESS;
1751 }
1752 #define LINK_UP_DOWN_INTERRUPT          1
1753 #define MAC_RMAC_ERR_TIMER              2
1754
1755 static int s2io_link_fault_indication(struct s2io_nic *nic)
1756 {
1757         if (nic->config.intr_type != INTA)
1758                 return MAC_RMAC_ERR_TIMER;
1759         if (nic->device_type == XFRAME_II_DEVICE)
1760                 return LINK_UP_DOWN_INTERRUPT;
1761         else
1762                 return MAC_RMAC_ERR_TIMER;
1763 }
1764
1765 /**
1766  *  do_s2io_write_bits -  update alarm bits in alarm register
1767  *  @value: alarm bits
1768  *  @flag: interrupt status
1769  *  @addr: address value
1770  *  Description: update alarm bits in alarm register
1771  *  Return Value:
1772  *  NONE.
1773  */
1774 static void do_s2io_write_bits(u64 value, int flag, void __iomem *addr)
1775 {
1776         u64 temp64;
1777
1778         temp64 = readq(addr);
1779
1780         if(flag == ENABLE_INTRS)
1781                 temp64 &= ~((u64) value);
1782         else
1783                 temp64 |= ((u64) value);
1784         writeq(temp64, addr);
1785 }
1786
1787 void en_dis_err_alarms(struct s2io_nic *nic, u16 mask, int flag)
1788 {
1789         struct XENA_dev_config __iomem *bar0 = nic->bar0;
1790         register u64 gen_int_mask = 0;
1791
1792         if (mask & TX_DMA_INTR) {
1793
1794                 gen_int_mask |= TXDMA_INT_M;
1795
1796                 do_s2io_write_bits(TXDMA_TDA_INT | TXDMA_PFC_INT |
1797                                 TXDMA_PCC_INT | TXDMA_TTI_INT |
1798                                 TXDMA_LSO_INT | TXDMA_TPA_INT |
1799                                 TXDMA_SM_INT, flag, &bar0->txdma_int_mask);
1800
1801                 do_s2io_write_bits(PFC_ECC_DB_ERR | PFC_SM_ERR_ALARM |
1802                                 PFC_MISC_0_ERR | PFC_MISC_1_ERR |
1803                                 PFC_PCIX_ERR | PFC_ECC_SG_ERR, flag,
1804                                 &bar0->pfc_err_mask);
1805
1806                 do_s2io_write_bits(TDA_Fn_ECC_DB_ERR | TDA_SM0_ERR_ALARM |
1807                                 TDA_SM1_ERR_ALARM | TDA_Fn_ECC_SG_ERR |
1808                                 TDA_PCIX_ERR, flag, &bar0->tda_err_mask);
1809
1810                 do_s2io_write_bits(PCC_FB_ECC_DB_ERR | PCC_TXB_ECC_DB_ERR |
1811                                 PCC_SM_ERR_ALARM | PCC_WR_ERR_ALARM |
1812                                 PCC_N_SERR | PCC_6_COF_OV_ERR |
1813                                 PCC_7_COF_OV_ERR | PCC_6_LSO_OV_ERR |
1814                                 PCC_7_LSO_OV_ERR | PCC_FB_ECC_SG_ERR |
1815                                 PCC_TXB_ECC_SG_ERR, flag, &bar0->pcc_err_mask);
1816
1817                 do_s2io_write_bits(TTI_SM_ERR_ALARM | TTI_ECC_SG_ERR |
1818                                 TTI_ECC_DB_ERR, flag, &bar0->tti_err_mask);
1819
1820                 do_s2io_write_bits(LSO6_ABORT | LSO7_ABORT |
1821                                 LSO6_SM_ERR_ALARM | LSO7_SM_ERR_ALARM |
1822                                 LSO6_SEND_OFLOW | LSO7_SEND_OFLOW,
1823                                 flag, &bar0->lso_err_mask);
1824
1825                 do_s2io_write_bits(TPA_SM_ERR_ALARM | TPA_TX_FRM_DROP,
1826                                 flag, &bar0->tpa_err_mask);
1827
1828                 do_s2io_write_bits(SM_SM_ERR_ALARM, flag, &bar0->sm_err_mask);
1829
1830         }
1831
1832         if (mask & TX_MAC_INTR) {
1833                 gen_int_mask |= TXMAC_INT_M;
1834                 do_s2io_write_bits(MAC_INT_STATUS_TMAC_INT, flag,
1835                                 &bar0->mac_int_mask);
1836                 do_s2io_write_bits(TMAC_TX_BUF_OVRN | TMAC_TX_SM_ERR |
1837                                 TMAC_ECC_SG_ERR | TMAC_ECC_DB_ERR |
1838                                 TMAC_DESC_ECC_SG_ERR | TMAC_DESC_ECC_DB_ERR,
1839                                 flag, &bar0->mac_tmac_err_mask);
1840         }
1841
1842         if (mask & TX_XGXS_INTR) {
1843                 gen_int_mask |= TXXGXS_INT_M;
1844                 do_s2io_write_bits(XGXS_INT_STATUS_TXGXS, flag,
1845                                 &bar0->xgxs_int_mask);
1846                 do_s2io_write_bits(TXGXS_ESTORE_UFLOW | TXGXS_TX_SM_ERR |
1847                                 TXGXS_ECC_SG_ERR | TXGXS_ECC_DB_ERR,
1848                                 flag, &bar0->xgxs_txgxs_err_mask);
1849         }
1850
1851         if (mask & RX_DMA_INTR) {
1852                 gen_int_mask |= RXDMA_INT_M;
1853                 do_s2io_write_bits(RXDMA_INT_RC_INT_M | RXDMA_INT_RPA_INT_M |
1854                                 RXDMA_INT_RDA_INT_M | RXDMA_INT_RTI_INT_M,
1855                                 flag, &bar0->rxdma_int_mask);
1856                 do_s2io_write_bits(RC_PRCn_ECC_DB_ERR | RC_FTC_ECC_DB_ERR |
1857                                 RC_PRCn_SM_ERR_ALARM | RC_FTC_SM_ERR_ALARM |
1858                                 RC_PRCn_ECC_SG_ERR | RC_FTC_ECC_SG_ERR |
1859                                 RC_RDA_FAIL_WR_Rn, flag, &bar0->rc_err_mask);
1860                 do_s2io_write_bits(PRC_PCI_AB_RD_Rn | PRC_PCI_AB_WR_Rn |
1861                                 PRC_PCI_AB_F_WR_Rn | PRC_PCI_DP_RD_Rn |
1862                                 PRC_PCI_DP_WR_Rn | PRC_PCI_DP_F_WR_Rn, flag,
1863                                 &bar0->prc_pcix_err_mask);
1864                 do_s2io_write_bits(RPA_SM_ERR_ALARM | RPA_CREDIT_ERR |
1865                                 RPA_ECC_SG_ERR | RPA_ECC_DB_ERR, flag,
1866                                 &bar0->rpa_err_mask);
1867                 do_s2io_write_bits(RDA_RXDn_ECC_DB_ERR | RDA_FRM_ECC_DB_N_AERR |
1868                                 RDA_SM1_ERR_ALARM | RDA_SM0_ERR_ALARM |
1869                                 RDA_RXD_ECC_DB_SERR | RDA_RXDn_ECC_SG_ERR |
1870                                 RDA_FRM_ECC_SG_ERR | RDA_MISC_ERR|RDA_PCIX_ERR,
1871                                 flag, &bar0->rda_err_mask);
1872                 do_s2io_write_bits(RTI_SM_ERR_ALARM |
1873                                 RTI_ECC_SG_ERR | RTI_ECC_DB_ERR,
1874                                 flag, &bar0->rti_err_mask);
1875         }
1876
1877         if (mask & RX_MAC_INTR) {
1878                 gen_int_mask |= RXMAC_INT_M;
1879                 do_s2io_write_bits(MAC_INT_STATUS_RMAC_INT, flag,
1880                                 &bar0->mac_int_mask);
1881                 do_s2io_write_bits(RMAC_RX_BUFF_OVRN | RMAC_RX_SM_ERR |
1882                                 RMAC_UNUSED_INT | RMAC_SINGLE_ECC_ERR |
1883                                 RMAC_DOUBLE_ECC_ERR |
1884                                 RMAC_LINK_STATE_CHANGE_INT,
1885                                 flag, &bar0->mac_rmac_err_mask);
1886         }
1887
1888         if (mask & RX_XGXS_INTR)
1889         {
1890                 gen_int_mask |= RXXGXS_INT_M;
1891                 do_s2io_write_bits(XGXS_INT_STATUS_RXGXS, flag,
1892                                 &bar0->xgxs_int_mask);
1893                 do_s2io_write_bits(RXGXS_ESTORE_OFLOW | RXGXS_RX_SM_ERR, flag,
1894                                 &bar0->xgxs_rxgxs_err_mask);
1895         }
1896
1897         if (mask & MC_INTR) {
1898                 gen_int_mask |= MC_INT_M;
1899                 do_s2io_write_bits(MC_INT_MASK_MC_INT, flag, &bar0->mc_int_mask);
1900                 do_s2io_write_bits(MC_ERR_REG_SM_ERR | MC_ERR_REG_ECC_ALL_SNG |
1901                                 MC_ERR_REG_ECC_ALL_DBL | PLL_LOCK_N, flag,
1902                                 &bar0->mc_err_mask);
1903         }
1904         nic->general_int_mask = gen_int_mask;
1905
1906         /* Remove this line when alarm interrupts are enabled */
1907         nic->general_int_mask = 0;
1908 }
1909 /**
1910  *  en_dis_able_nic_intrs - Enable or Disable the interrupts
1911  *  @nic: device private variable,
1912  *  @mask: A mask indicating which Intr block must be modified and,
1913  *  @flag: A flag indicating whether to enable or disable the Intrs.
1914  *  Description: This function will either disable or enable the interrupts
1915  *  depending on the flag argument. The mask argument can be used to
1916  *  enable/disable any Intr block.
1917  *  Return Value: NONE.
1918  */
1919
1920 static void en_dis_able_nic_intrs(struct s2io_nic *nic, u16 mask, int flag)
1921 {
1922         struct XENA_dev_config __iomem *bar0 = nic->bar0;
1923         register u64 temp64 = 0, intr_mask = 0;
1924
1925         intr_mask = nic->general_int_mask;
1926
1927         /*  Top level interrupt classification */
1928         /*  PIC Interrupts */
1929         if (mask & TX_PIC_INTR) {
1930                 /*  Enable PIC Intrs in the general intr mask register */
1931                 intr_mask |= TXPIC_INT_M;
1932                 if (flag == ENABLE_INTRS) {
1933                         /*
1934                          * If Hercules adapter enable GPIO otherwise
1935                          * disable all PCIX, Flash, MDIO, IIC and GPIO
1936                          * interrupts for now.
1937                          * TODO
1938                          */
1939                         if (s2io_link_fault_indication(nic) ==
1940                                         LINK_UP_DOWN_INTERRUPT ) {
1941                                 do_s2io_write_bits(PIC_INT_GPIO, flag,
1942                                                 &bar0->pic_int_mask);
1943                                 do_s2io_write_bits(GPIO_INT_MASK_LINK_UP, flag,
1944                                                 &bar0->gpio_int_mask);
1945                         } else
1946                                 writeq(DISABLE_ALL_INTRS, &bar0->pic_int_mask);
1947                 } else if (flag == DISABLE_INTRS) {
1948                         /*
1949                          * Disable PIC Intrs in the general
1950                          * intr mask register
1951                          */
1952                         writeq(DISABLE_ALL_INTRS, &bar0->pic_int_mask);
1953                 }
1954         }
1955
1956         /*  Tx traffic interrupts */
1957         if (mask & TX_TRAFFIC_INTR) {
1958                 intr_mask |= TXTRAFFIC_INT_M;
1959                 if (flag == ENABLE_INTRS) {
1960                         /*
1961                          * Enable all the Tx side interrupts
1962                          * writing 0 Enables all 64 TX interrupt levels
1963                          */
1964                         writeq(0x0, &bar0->tx_traffic_mask);
1965                 } else if (flag == DISABLE_INTRS) {
1966                         /*
1967                          * Disable Tx Traffic Intrs in the general intr mask
1968                          * register.
1969                          */
1970                         writeq(DISABLE_ALL_INTRS, &bar0->tx_traffic_mask);
1971                 }
1972         }
1973
1974         /*  Rx traffic interrupts */
1975         if (mask & RX_TRAFFIC_INTR) {
1976                 intr_mask |= RXTRAFFIC_INT_M;
1977                 if (flag == ENABLE_INTRS) {
1978                         /* writing 0 Enables all 8 RX interrupt levels */
1979                         writeq(0x0, &bar0->rx_traffic_mask);
1980                 } else if (flag == DISABLE_INTRS) {
1981                         /*
1982                          * Disable Rx Traffic Intrs in the general intr mask
1983                          * register.
1984                          */
1985                         writeq(DISABLE_ALL_INTRS, &bar0->rx_traffic_mask);
1986                 }
1987         }
1988
1989         temp64 = readq(&bar0->general_int_mask);
1990         if (flag == ENABLE_INTRS)
1991                 temp64 &= ~((u64) intr_mask);
1992         else
1993                 temp64 = DISABLE_ALL_INTRS;
1994         writeq(temp64, &bar0->general_int_mask);
1995
1996         nic->general_int_mask = readq(&bar0->general_int_mask);
1997 }
1998
1999 /**
2000  *  verify_pcc_quiescent- Checks for PCC quiescent state
2001  *  Return: 1 If PCC is quiescence
2002  *          0 If PCC is not quiescence
2003  */
2004 static int verify_pcc_quiescent(struct s2io_nic *sp, int flag)
2005 {
2006         int ret = 0, herc;
2007         struct XENA_dev_config __iomem *bar0 = sp->bar0;
2008         u64 val64 = readq(&bar0->adapter_status);
2009
2010         herc = (sp->device_type == XFRAME_II_DEVICE);
2011
2012         if (flag == FALSE) {
2013                 if ((!herc && (sp->pdev->revision >= 4)) || herc) {
2014                         if (!(val64 & ADAPTER_STATUS_RMAC_PCC_IDLE))
2015                                 ret = 1;
2016                 } else {
2017                         if (!(val64 & ADAPTER_STATUS_RMAC_PCC_FOUR_IDLE))
2018                                 ret = 1;
2019                 }
2020         } else {
2021                 if ((!herc && (sp->pdev->revision >= 4)) || herc) {
2022                         if (((val64 & ADAPTER_STATUS_RMAC_PCC_IDLE) ==
2023                              ADAPTER_STATUS_RMAC_PCC_IDLE))
2024                                 ret = 1;
2025                 } else {
2026                         if (((val64 & ADAPTER_STATUS_RMAC_PCC_FOUR_IDLE) ==
2027                              ADAPTER_STATUS_RMAC_PCC_FOUR_IDLE))
2028                                 ret = 1;
2029                 }
2030         }
2031
2032         return ret;
2033 }
2034 /**
2035  *  verify_xena_quiescence - Checks whether the H/W is ready
2036  *  Description: Returns whether the H/W is ready to go or not. Depending
2037  *  on whether adapter enable bit was written or not the comparison
2038  *  differs and the calling function passes the input argument flag to
2039  *  indicate this.
2040  *  Return: 1 If xena is quiescence
2041  *          0 If Xena is not quiescence
2042  */
2043
2044 static int verify_xena_quiescence(struct s2io_nic *sp)
2045 {
2046         int  mode;
2047         struct XENA_dev_config __iomem *bar0 = sp->bar0;
2048         u64 val64 = readq(&bar0->adapter_status);
2049         mode = s2io_verify_pci_mode(sp);
2050
2051         if (!(val64 & ADAPTER_STATUS_TDMA_READY)) {
2052                 DBG_PRINT(ERR_DBG, "%s", "TDMA is not ready!");
2053                 return 0;
2054         }
2055         if (!(val64 & ADAPTER_STATUS_RDMA_READY)) {
2056         DBG_PRINT(ERR_DBG, "%s", "RDMA is not ready!");
2057                 return 0;
2058         }
2059         if (!(val64 & ADAPTER_STATUS_PFC_READY)) {
2060                 DBG_PRINT(ERR_DBG, "%s", "PFC is not ready!");
2061                 return 0;
2062         }
2063         if (!(val64 & ADAPTER_STATUS_TMAC_BUF_EMPTY)) {
2064                 DBG_PRINT(ERR_DBG, "%s", "TMAC BUF is not empty!");
2065                 return 0;
2066         }
2067         if (!(val64 & ADAPTER_STATUS_PIC_QUIESCENT)) {
2068                 DBG_PRINT(ERR_DBG, "%s", "PIC is not QUIESCENT!");
2069                 return 0;
2070         }
2071         if (!(val64 & ADAPTER_STATUS_MC_DRAM_READY)) {
2072                 DBG_PRINT(ERR_DBG, "%s", "MC_DRAM is not ready!");
2073                 return 0;
2074         }
2075         if (!(val64 & ADAPTER_STATUS_MC_QUEUES_READY)) {
2076                 DBG_PRINT(ERR_DBG, "%s", "MC_QUEUES is not ready!");
2077                 return 0;
2078         }
2079         if (!(val64 & ADAPTER_STATUS_M_PLL_LOCK)) {
2080                 DBG_PRINT(ERR_DBG, "%s", "M_PLL is not locked!");
2081                 return 0;
2082         }
2083
2084         /*
2085          * In PCI 33 mode, the P_PLL is not used, and therefore,
2086          * the the P_PLL_LOCK bit in the adapter_status register will
2087          * not be asserted.
2088          */
2089         if (!(val64 & ADAPTER_STATUS_P_PLL_LOCK) &&
2090                 sp->device_type == XFRAME_II_DEVICE && mode !=
2091                 PCI_MODE_PCI_33) {
2092                 DBG_PRINT(ERR_DBG, "%s", "P_PLL is not locked!");
2093                 return 0;
2094         }
2095         if (!((val64 & ADAPTER_STATUS_RC_PRC_QUIESCENT) ==
2096                         ADAPTER_STATUS_RC_PRC_QUIESCENT)) {
2097                 DBG_PRINT(ERR_DBG, "%s", "RC_PRC is not QUIESCENT!");
2098                 return 0;
2099         }
2100         return 1;
2101 }
2102
2103 /**
2104  * fix_mac_address -  Fix for Mac addr problem on Alpha platforms
2105  * @sp: Pointer to device specifc structure
2106  * Description :
2107  * New procedure to clear mac address reading  problems on Alpha platforms
2108  *
2109  */
2110
2111 static void fix_mac_address(struct s2io_nic * sp)
2112 {
2113         struct XENA_dev_config __iomem *bar0 = sp->bar0;
2114         u64 val64;
2115         int i = 0;
2116
2117         while (fix_mac[i] != END_SIGN) {
2118                 writeq(fix_mac[i++], &bar0->gpio_control);
2119                 udelay(10);
2120                 val64 = readq(&bar0->gpio_control);
2121         }
2122 }
2123
2124 /**
2125  *  start_nic - Turns the device on
2126  *  @nic : device private variable.
2127  *  Description:
2128  *  This function actually turns the device on. Before this  function is
2129  *  called,all Registers are configured from their reset states
2130  *  and shared memory is allocated but the NIC is still quiescent. On
2131  *  calling this function, the device interrupts are cleared and the NIC is
2132  *  literally switched on by writing into the adapter control register.
2133  *  Return Value:
2134  *  SUCCESS on success and -1 on failure.
2135  */
2136
2137 static int start_nic(struct s2io_nic *nic)
2138 {
2139         struct XENA_dev_config __iomem *bar0 = nic->bar0;
2140         struct net_device *dev = nic->dev;
2141         register u64 val64 = 0;
2142         u16 subid, i;
2143         struct mac_info *mac_control;
2144         struct config_param *config;
2145
2146         mac_control = &nic->mac_control;
2147         config = &nic->config;
2148
2149         /*  PRC Initialization and configuration */
2150         for (i = 0; i < config->rx_ring_num; i++) {
2151                 writeq((u64) mac_control->rings[i].rx_blocks[0].block_dma_addr,
2152                        &bar0->prc_rxd0_n[i]);
2153
2154                 val64 = readq(&bar0->prc_ctrl_n[i]);
2155                 if (nic->config.bimodal)
2156                         val64 |= PRC_CTRL_BIMODAL_INTERRUPT;
2157                 if (nic->rxd_mode == RXD_MODE_1)
2158                         val64 |= PRC_CTRL_RC_ENABLED;
2159                 else
2160                         val64 |= PRC_CTRL_RC_ENABLED | PRC_CTRL_RING_MODE_3;
2161                 if (nic->device_type == XFRAME_II_DEVICE)
2162                         val64 |= PRC_CTRL_GROUP_READS;
2163                 val64 &= ~PRC_CTRL_RXD_BACKOFF_INTERVAL(0xFFFFFF);
2164                 val64 |= PRC_CTRL_RXD_BACKOFF_INTERVAL(0x1000);
2165                 writeq(val64, &bar0->prc_ctrl_n[i]);
2166         }
2167
2168         if (nic->rxd_mode == RXD_MODE_3B) {
2169                 /* Enabling 2 buffer mode by writing into Rx_pa_cfg reg. */
2170                 val64 = readq(&bar0->rx_pa_cfg);
2171                 val64 |= RX_PA_CFG_IGNORE_L2_ERR;
2172                 writeq(val64, &bar0->rx_pa_cfg);
2173         }
2174
2175         if (vlan_tag_strip == 0) {
2176                 val64 = readq(&bar0->rx_pa_cfg);
2177                 val64 &= ~RX_PA_CFG_STRIP_VLAN_TAG;
2178                 writeq(val64, &bar0->rx_pa_cfg);
2179                 vlan_strip_flag = 0;
2180         }
2181
2182         /*
2183          * Enabling MC-RLDRAM. After enabling the device, we timeout
2184          * for around 100ms, which is approximately the time required
2185          * for the device to be ready for operation.
2186          */
2187         val64 = readq(&bar0->mc_rldram_mrs);
2188         val64 |= MC_RLDRAM_QUEUE_SIZE_ENABLE | MC_RLDRAM_MRS_ENABLE;
2189         SPECIAL_REG_WRITE(val64, &bar0->mc_rldram_mrs, UF);
2190         val64 = readq(&bar0->mc_rldram_mrs);
2191
2192         msleep(100);    /* Delay by around 100 ms. */
2193
2194         /* Enabling ECC Protection. */
2195         val64 = readq(&bar0->adapter_control);
2196         val64 &= ~ADAPTER_ECC_EN;
2197         writeq(val64, &bar0->adapter_control);
2198
2199         /*
2200          * Verify if the device is ready to be enabled, if so enable
2201          * it.
2202          */
2203         val64 = readq(&bar0->adapter_status);
2204         if (!verify_xena_quiescence(nic)) {
2205                 DBG_PRINT(ERR_DBG, "%s: device is not ready, ", dev->name);
2206                 DBG_PRINT(ERR_DBG, "Adapter status reads: 0x%llx\n",
2207                           (unsigned long long) val64);
2208                 return FAILURE;
2209         }
2210
2211         /*
2212          * With some switches, link might be already up at this point.
2213          * Because of this weird behavior, when we enable laser,
2214          * we may not get link. We need to handle this. We cannot
2215          * figure out which switch is misbehaving. So we are forced to
2216          * make a global change.
2217          */
2218
2219         /* Enabling Laser. */
2220         val64 = readq(&bar0->adapter_control);
2221         val64 |= ADAPTER_EOI_TX_ON;
2222         writeq(val64, &bar0->adapter_control);
2223
2224         if (s2io_link_fault_indication(nic) == MAC_RMAC_ERR_TIMER) {
2225                 /*
2226                  * Dont see link state interrupts initally on some switches,
2227                  * so directly scheduling the link state task here.
2228                  */
2229                 schedule_work(&nic->set_link_task);
2230         }
2231         /* SXE-002: Initialize link and activity LED */
2232         subid = nic->pdev->subsystem_device;
2233         if (((subid & 0xFF) >= 0x07) &&
2234             (nic->device_type == XFRAME_I_DEVICE)) {
2235                 val64 = readq(&bar0->gpio_control);
2236                 val64 |= 0x0000800000000000ULL;
2237                 writeq(val64, &bar0->gpio_control);
2238                 val64 = 0x0411040400000000ULL;
2239                 writeq(val64, (void __iomem *)bar0 + 0x2700);
2240         }
2241
2242         return SUCCESS;
2243 }
2244 /**
2245  * s2io_txdl_getskb - Get the skb from txdl, unmap and return skb
2246  */
2247 static struct sk_buff *s2io_txdl_getskb(struct fifo_info *fifo_data, struct \
2248                                         TxD *txdlp, int get_off)
2249 {
2250         struct s2io_nic *nic = fifo_data->nic;
2251         struct sk_buff *skb;
2252         struct TxD *txds;
2253         u16 j, frg_cnt;
2254
2255         txds = txdlp;
2256         if (txds->Host_Control == (u64)(long)nic->ufo_in_band_v) {
2257                 pci_unmap_single(nic->pdev, (dma_addr_t)
2258                         txds->Buffer_Pointer, sizeof(u64),
2259                         PCI_DMA_TODEVICE);
2260                 txds++;
2261         }
2262
2263         skb = (struct sk_buff *) ((unsigned long)
2264                         txds->Host_Control);
2265         if (!skb) {
2266                 memset(txdlp, 0, (sizeof(struct TxD) * fifo_data->max_txds));
2267                 return NULL;
2268         }
2269         pci_unmap_single(nic->pdev, (dma_addr_t)
2270                          txds->Buffer_Pointer,
2271                          skb->len - skb->data_len,
2272                          PCI_DMA_TODEVICE);
2273         frg_cnt = skb_shinfo(skb)->nr_frags;
2274         if (frg_cnt) {
2275                 txds++;
2276                 for (j = 0; j < frg_cnt; j++, txds++) {
2277                         skb_frag_t *frag = &skb_shinfo(skb)->frags[j];
2278                         if (!txds->Buffer_Pointer)
2279                                 break;
2280                         pci_unmap_page(nic->pdev, (dma_addr_t)
2281                                         txds->Buffer_Pointer,
2282                                        frag->size, PCI_DMA_TODEVICE);
2283                 }
2284         }
2285         memset(txdlp,0, (sizeof(struct TxD) * fifo_data->max_txds));
2286         return(skb);
2287 }
2288
2289 /**
2290  *  free_tx_buffers - Free all queued Tx buffers
2291  *  @nic : device private variable.
2292  *  Description:
2293  *  Free all queued Tx buffers.
2294  *  Return Value: void
2295 */
2296
2297 static void free_tx_buffers(struct s2io_nic *nic)
2298 {
2299         struct net_device *dev = nic->dev;
2300         struct sk_buff *skb;
2301         struct TxD *txdp;
2302         int i, j;
2303         struct mac_info *mac_control;
2304         struct config_param *config;
2305         int cnt = 0;
2306
2307         mac_control = &nic->mac_control;
2308         config = &nic->config;
2309
2310         for (i = 0; i < config->tx_fifo_num; i++) {
2311                 for (j = 0; j < config->tx_cfg[i].fifo_len - 1; j++) {
2312                         txdp = (struct TxD *) \
2313                         mac_control->fifos[i].list_info[j].list_virt_addr;
2314                         skb = s2io_txdl_getskb(&mac_control->fifos[i], txdp, j);
2315                         if (skb) {
2316                                 nic->mac_control.stats_info->sw_stat.mem_freed
2317                                         += skb->truesize;
2318                                 dev_kfree_skb(skb);
2319                                 cnt++;
2320                         }
2321                 }
2322                 DBG_PRINT(INTR_DBG,
2323                           "%s:forcibly freeing %d skbs on FIFO%d\n",
2324                           dev->name, cnt, i);
2325                 mac_control->fifos[i].tx_curr_get_info.offset = 0;
2326                 mac_control->fifos[i].tx_curr_put_info.offset = 0;
2327         }
2328 }
2329
2330 /**
2331  *   stop_nic -  To stop the nic
2332  *   @nic ; device private variable.
2333  *   Description:
2334  *   This function does exactly the opposite of what the start_nic()
2335  *   function does. This function is called to stop the device.
2336  *   Return Value:
2337  *   void.
2338  */
2339
2340 static void stop_nic(struct s2io_nic *nic)
2341 {
2342         struct XENA_dev_config __iomem *bar0 = nic->bar0;
2343         register u64 val64 = 0;
2344         u16 interruptible;
2345         struct mac_info *mac_control;
2346         struct config_param *config;
2347
2348         mac_control = &nic->mac_control;
2349         config = &nic->config;
2350
2351         /*  Disable all interrupts */
2352         en_dis_err_alarms(nic, ENA_ALL_INTRS, DISABLE_INTRS);
2353         interruptible = TX_TRAFFIC_INTR | RX_TRAFFIC_INTR;
2354         interruptible |= TX_PIC_INTR;
2355         en_dis_able_nic_intrs(nic, interruptible, DISABLE_INTRS);
2356
2357         /* Clearing Adapter_En bit of ADAPTER_CONTROL Register */
2358         val64 = readq(&bar0->adapter_control);
2359         val64 &= ~(ADAPTER_CNTL_EN);
2360         writeq(val64, &bar0->adapter_control);
2361 }
2362
2363 /**
2364  *  fill_rx_buffers - Allocates the Rx side skbs
2365  *  @nic:  device private variable
2366  *  @ring_no: ring number
2367  *  Description:
2368  *  The function allocates Rx side skbs and puts the physical
2369  *  address of these buffers into the RxD buffer pointers, so that the NIC
2370  *  can DMA the received frame into these locations.
2371  *  The NIC supports 3 receive modes, viz
2372  *  1. single buffer,
2373  *  2. three buffer and
2374  *  3. Five buffer modes.
2375  *  Each mode defines how many fragments the received frame will be split
2376  *  up into by the NIC. The frame is split into L3 header, L4 Header,
2377  *  L4 payload in three buffer mode and in 5 buffer mode, L4 payload itself
2378  *  is split into 3 fragments. As of now only single buffer mode is
2379  *  supported.
2380  *   Return Value:
2381  *  SUCCESS on success or an appropriate -ve value on failure.
2382  */
2383
2384 static int fill_rx_buffers(struct s2io_nic *nic, int ring_no)
2385 {
2386         struct net_device *dev = nic->dev;
2387         struct sk_buff *skb;
2388         struct RxD_t *rxdp;
2389         int off, off1, size, block_no, block_no1;
2390         u32 alloc_tab = 0;
2391         u32 alloc_cnt;
2392         struct mac_info *mac_control;
2393         struct config_param *config;
2394         u64 tmp;
2395         struct buffAdd *ba;
2396         unsigned long flags;
2397         struct RxD_t *first_rxdp = NULL;
2398         u64 Buffer0_ptr = 0, Buffer1_ptr = 0;
2399         struct RxD1 *rxdp1;
2400         struct RxD3 *rxdp3;
2401         struct swStat *stats = &nic->mac_control.stats_info->sw_stat;
2402
2403         mac_control = &nic->mac_control;
2404         config = &nic->config;
2405         alloc_cnt = mac_control->rings[ring_no].pkt_cnt -
2406             atomic_read(&nic->rx_bufs_left[ring_no]);
2407
2408         block_no1 = mac_control->rings[ring_no].rx_curr_get_info.block_index;
2409         off1 = mac_control->rings[ring_no].rx_curr_get_info.offset;
2410         while (alloc_tab < alloc_cnt) {
2411                 block_no = mac_control->rings[ring_no].rx_curr_put_info.
2412                     block_index;
2413                 off = mac_control->rings[ring_no].rx_curr_put_info.offset;
2414
2415                 rxdp = mac_control->rings[ring_no].
2416                                 rx_blocks[block_no].rxds[off].virt_addr;
2417
2418                 if ((block_no == block_no1) && (off == off1) &&
2419                                         (rxdp->Host_Control)) {
2420                         DBG_PRINT(INTR_DBG, "%s: Get and Put",
2421                                   dev->name);
2422                         DBG_PRINT(INTR_DBG, " info equated\n");
2423                         goto end;
2424                 }
2425                 if (off && (off == rxd_count[nic->rxd_mode])) {
2426                         mac_control->rings[ring_no].rx_curr_put_info.
2427                             block_index++;
2428                         if (mac_control->rings[ring_no].rx_curr_put_info.
2429                             block_index == mac_control->rings[ring_no].
2430                                         block_count)
2431                                 mac_control->rings[ring_no].rx_curr_put_info.
2432                                         block_index = 0;
2433                         block_no = mac_control->rings[ring_no].
2434                                         rx_curr_put_info.block_index;
2435                         if (off == rxd_count[nic->rxd_mode])
2436                                 off = 0;
2437                         mac_control->rings[ring_no].rx_curr_put_info.
2438                                 offset = off;
2439                         rxdp = mac_control->rings[ring_no].
2440                                 rx_blocks[block_no].block_virt_addr;
2441                         DBG_PRINT(INTR_DBG, "%s: Next block at: %p\n",
2442                                   dev->name, rxdp);
2443                 }
2444                 if(!napi) {
2445                         spin_lock_irqsave(&nic->put_lock, flags);
2446                         mac_control->rings[ring_no].put_pos =
2447                         (block_no * (rxd_count[nic->rxd_mode] + 1)) + off;
2448                         spin_unlock_irqrestore(&nic->put_lock, flags);
2449                 } else {
2450                         mac_control->rings[ring_no].put_pos =
2451                         (block_no * (rxd_count[nic->rxd_mode] + 1)) + off;
2452                 }
2453                 if ((rxdp->Control_1 & RXD_OWN_XENA) &&
2454                         ((nic->rxd_mode == RXD_MODE_3B) &&
2455                                 (rxdp->Control_2 & BIT(0)))) {
2456                         mac_control->rings[ring_no].rx_curr_put_info.
2457                                         offset = off;
2458                         goto end;
2459                 }
2460                 /* calculate size of skb based on ring mode */
2461                 size = dev->mtu + HEADER_ETHERNET_II_802_3_SIZE +
2462                                 HEADER_802_2_SIZE + HEADER_SNAP_SIZE;
2463                 if (nic->rxd_mode == RXD_MODE_1)
2464                         size += NET_IP_ALIGN;
2465                 else
2466                         size = dev->mtu + ALIGN_SIZE + BUF0_LEN + 4;
2467
2468                 /* allocate skb */
2469                 skb = dev_alloc_skb(size);
2470                 if(!skb) {
2471                         DBG_PRINT(INFO_DBG, "%s: Out of ", dev->name);
2472                         DBG_PRINT(INFO_DBG, "memory to allocate SKBs\n");
2473                         if (first_rxdp) {
2474                                 wmb();
2475                                 first_rxdp->Control_1 |= RXD_OWN_XENA;
2476                         }
2477                         nic->mac_control.stats_info->sw_stat. \
2478                                 mem_alloc_fail_cnt++;
2479                         return -ENOMEM ;
2480                 }
2481                 nic->mac_control.stats_info->sw_stat.mem_allocated
2482                         += skb->truesize;
2483                 if (nic->rxd_mode == RXD_MODE_1) {
2484                         /* 1 buffer mode - normal operation mode */
2485                         rxdp1 = (struct RxD1*)rxdp;
2486                         memset(rxdp, 0, sizeof(struct RxD1));
2487                         skb_reserve(skb, NET_IP_ALIGN);
2488                         rxdp1->Buffer0_ptr = pci_map_single
2489                             (nic->pdev, skb->data, size - NET_IP_ALIGN,
2490                                 PCI_DMA_FROMDEVICE);
2491                         if( (rxdp1->Buffer0_ptr == 0) ||
2492                                 (rxdp1->Buffer0_ptr ==
2493                                 DMA_ERROR_CODE))
2494                                 goto pci_map_failed;
2495
2496                         rxdp->Control_2 =
2497                                 SET_BUFFER0_SIZE_1(size - NET_IP_ALIGN);
2498
2499                 } else if (nic->rxd_mode == RXD_MODE_3B) {
2500                         /*
2501                          * 2 buffer mode -
2502                          * 2 buffer mode provides 128
2503                          * byte aligned receive buffers.
2504                          */
2505
2506                         rxdp3 = (struct RxD3*)rxdp;
2507                         /* save buffer pointers to avoid frequent dma mapping */
2508                         Buffer0_ptr = rxdp3->Buffer0_ptr;
2509                         Buffer1_ptr = rxdp3->Buffer1_ptr;
2510                         memset(rxdp, 0, sizeof(struct RxD3));
2511                         /* restore the buffer pointers for dma sync*/
2512                         rxdp3->Buffer0_ptr = Buffer0_ptr;
2513                         rxdp3->Buffer1_ptr = Buffer1_ptr;
2514
2515                         ba = &mac_control->rings[ring_no].ba[block_no][off];
2516                         skb_reserve(skb, BUF0_LEN);
2517                         tmp = (u64)(unsigned long) skb->data;
2518                         tmp += ALIGN_SIZE;
2519                         tmp &= ~ALIGN_SIZE;
2520                         skb->data = (void *) (unsigned long)tmp;
2521                         skb_reset_tail_pointer(skb);
2522
2523                         if (!(rxdp3->Buffer0_ptr))
2524                                 rxdp3->Buffer0_ptr =
2525                                    pci_map_single(nic->pdev, ba->ba_0, BUF0_LEN,
2526                                            PCI_DMA_FROMDEVICE);
2527                         else
2528                                 pci_dma_sync_single_for_device(nic->pdev,
2529                                 (dma_addr_t) rxdp3->Buffer0_ptr,
2530                                     BUF0_LEN, PCI_DMA_FROMDEVICE);
2531                         if( (rxdp3->Buffer0_ptr == 0) ||
2532                                 (rxdp3->Buffer0_ptr == DMA_ERROR_CODE))
2533                                 goto pci_map_failed;
2534
2535                         rxdp->Control_2 = SET_BUFFER0_SIZE_3(BUF0_LEN);
2536                         if (nic->rxd_mode == RXD_MODE_3B) {
2537                                 /* Two buffer mode */
2538
2539                                 /*
2540                                  * Buffer2 will have L3/L4 header plus
2541                                  * L4 payload
2542                                  */
2543                                 rxdp3->Buffer2_ptr = pci_map_single
2544                                 (nic->pdev, skb->data, dev->mtu + 4,
2545                                                 PCI_DMA_FROMDEVICE);
2546
2547                                 if( (rxdp3->Buffer2_ptr == 0) ||
2548                                         (rxdp3->Buffer2_ptr == DMA_ERROR_CODE))
2549                                         goto pci_map_failed;
2550
2551                                 rxdp3->Buffer1_ptr =
2552                                                 pci_map_single(nic->pdev,
2553                                                 ba->ba_1, BUF1_LEN,
2554                                                 PCI_DMA_FROMDEVICE);
2555                                 if( (rxdp3->Buffer1_ptr == 0) ||
2556                                         (rxdp3->Buffer1_ptr == DMA_ERROR_CODE)) {
2557                                         pci_unmap_single
2558                                                 (nic->pdev,
2559                                                 (dma_addr_t)rxdp3->Buffer2_ptr,
2560                                                 dev->mtu + 4,
2561                                                 PCI_DMA_FROMDEVICE);
2562                                         goto pci_map_failed;
2563                                 }
2564                                 rxdp->Control_2 |= SET_BUFFER1_SIZE_3(1);
2565                                 rxdp->Control_2 |= SET_BUFFER2_SIZE_3
2566                                                                 (dev->mtu + 4);
2567                         }
2568                         rxdp->Control_2 |= BIT(0);
2569                 }
2570                 rxdp->Host_Control = (unsigned long) (skb);
2571                 if (alloc_tab & ((1 << rxsync_frequency) - 1))
2572                         rxdp->Control_1 |= RXD_OWN_XENA;
2573                 off++;
2574                 if (off == (rxd_count[nic->rxd_mode] + 1))
2575                         off = 0;
2576                 mac_control->rings[ring_no].rx_curr_put_info.offset = off;
2577
2578                 rxdp->Control_2 |= SET_RXD_MARKER;
2579                 if (!(alloc_tab & ((1 << rxsync_frequency) - 1))) {
2580                         if (first_rxdp) {
2581                                 wmb();
2582                                 first_rxdp->Control_1 |= RXD_OWN_XENA;
2583                         }
2584                         first_rxdp = rxdp;
2585                 }
2586                 atomic_inc(&nic->rx_bufs_left[ring_no]);
2587                 alloc_tab++;
2588         }
2589
2590       end:
2591         /* Transfer ownership of first descriptor to adapter just before
2592          * exiting. Before that, use memory barrier so that ownership
2593          * and other fields are seen by adapter correctly.
2594          */
2595         if (first_rxdp) {
2596                 wmb();
2597                 first_rxdp->Control_1 |= RXD_OWN_XENA;
2598         }
2599
2600         return SUCCESS;
2601 pci_map_failed:
2602         stats->pci_map_fail_cnt++;
2603         stats->mem_freed += skb->truesize;
2604         dev_kfree_skb_irq(skb);
2605         return -ENOMEM;
2606 }
2607
2608 static void free_rxd_blk(struct s2io_nic *sp, int ring_no, int blk)
2609 {
2610         struct net_device *dev = sp->dev;
2611         int j;
2612         struct sk_buff *skb;
2613         struct RxD_t *rxdp;
2614         struct mac_info *mac_control;
2615         struct buffAdd *ba;
2616         struct RxD1 *rxdp1;
2617         struct RxD3 *rxdp3;
2618
2619         mac_control = &sp->mac_control;
2620         for (j = 0 ; j < rxd_count[sp->rxd_mode]; j++) {
2621                 rxdp = mac_control->rings[ring_no].
2622                                 rx_blocks[blk].rxds[j].virt_addr;
2623                 skb = (struct sk_buff *)
2624                         ((unsigned long) rxdp->Host_Control);
2625                 if (!skb) {
2626                         continue;
2627                 }
2628                 if (sp->rxd_mode == RXD_MODE_1) {
2629                         rxdp1 = (struct RxD1*)rxdp;
2630                         pci_unmap_single(sp->pdev, (dma_addr_t)
2631                                 rxdp1->Buffer0_ptr,
2632                                 dev->mtu +
2633                                 HEADER_ETHERNET_II_802_3_SIZE
2634                                 + HEADER_802_2_SIZE +
2635                                 HEADER_SNAP_SIZE,
2636                                 PCI_DMA_FROMDEVICE);
2637                         memset(rxdp, 0, sizeof(struct RxD1));
2638                 } else if(sp->rxd_mode == RXD_MODE_3B) {
2639                         rxdp3 = (struct RxD3*)rxdp;
2640                         ba = &mac_control->rings[ring_no].
2641                                 ba[blk][j];
2642                         pci_unmap_single(sp->pdev, (dma_addr_t)
2643                                 rxdp3->Buffer0_ptr,
2644                                 BUF0_LEN,
2645                                 PCI_DMA_FROMDEVICE);
2646                         pci_unmap_single(sp->pdev, (dma_addr_t)
2647                                 rxdp3->Buffer1_ptr,
2648                                 BUF1_LEN,
2649                                 PCI_DMA_FROMDEVICE);
2650                         pci_unmap_single(sp->pdev, (dma_addr_t)
2651                                 rxdp3->Buffer2_ptr,
2652                                 dev->mtu + 4,
2653                                 PCI_DMA_FROMDEVICE);
2654                         memset(rxdp, 0, sizeof(struct RxD3));
2655                 }
2656                 sp->mac_control.stats_info->sw_stat.mem_freed += skb->truesize;
2657                 dev_kfree_skb(skb);
2658                 atomic_dec(&sp->rx_bufs_left[ring_no]);
2659         }
2660 }
2661
2662 /**
2663  *  free_rx_buffers - Frees all Rx buffers
2664  *  @sp: device private variable.
2665  *  Description:
2666  *  This function will free all Rx buffers allocated by host.
2667  *  Return Value:
2668  *  NONE.
2669  */
2670
2671 static void free_rx_buffers(struct s2io_nic *sp)
2672 {
2673         struct net_device *dev = sp->dev;
2674         int i, blk = 0, buf_cnt = 0;
2675         struct mac_info *mac_control;
2676         struct config_param *config;
2677
2678         mac_control = &sp->mac_control;
2679         config = &sp->config;
2680
2681         for (i = 0; i < config->rx_ring_num; i++) {
2682                 for (blk = 0; blk < rx_ring_sz[i]; blk++)
2683                         free_rxd_blk(sp,i,blk);
2684
2685                 mac_control->rings[i].rx_curr_put_info.block_index = 0;
2686                 mac_control->rings[i].rx_curr_get_info.block_index = 0;
2687                 mac_control->rings[i].rx_curr_put_info.offset = 0;
2688                 mac_control->rings[i].rx_curr_get_info.offset = 0;
2689                 atomic_set(&sp->rx_bufs_left[i], 0);
2690                 DBG_PRINT(INIT_DBG, "%s:Freed 0x%x Rx Buffers on ring%d\n",
2691                           dev->name, buf_cnt, i);
2692         }
2693 }
2694
2695 /**
2696  * s2io_poll - Rx interrupt handler for NAPI support
2697  * @napi : pointer to the napi structure.
2698  * @budget : The number of packets that were budgeted to be processed
2699  * during  one pass through the 'Poll" function.
2700  * Description:
2701  * Comes into picture only if NAPI support has been incorporated. It does
2702  * the same thing that rx_intr_handler does, but not in a interrupt context
2703  * also It will process only a given number of packets.
2704  * Return value:
2705  * 0 on success and 1 if there are No Rx packets to be processed.
2706  */
2707
2708 static int s2io_poll(struct napi_struct *napi, int budget)
2709 {
2710         struct s2io_nic *nic = container_of(napi, struct s2io_nic, napi);
2711         struct net_device *dev = nic->dev;
2712         int pkt_cnt = 0, org_pkts_to_process;
2713         struct mac_info *mac_control;
2714         struct config_param *config;
2715         struct XENA_dev_config __iomem *bar0 = nic->bar0;
2716         int i;
2717
2718         atomic_inc(&nic->isr_cnt);
2719
2720         if (!is_s2io_card_up(nic)) {
2721                 atomic_dec(&nic->isr_cnt);
2722                 return 0;
2723         }
2724
2725         mac_control = &nic->mac_control;
2726         config = &nic->config;
2727
2728         nic->pkts_to_process = budget;
2729         org_pkts_to_process = nic->pkts_to_process;
2730
2731         writeq(S2IO_MINUS_ONE, &bar0->rx_traffic_int);
2732         readl(&bar0->rx_traffic_int);
2733
2734         for (i = 0; i < config->rx_ring_num; i++) {
2735                 rx_intr_handler(&mac_control->rings[i]);
2736                 pkt_cnt = org_pkts_to_process - nic->pkts_to_process;
2737                 if (!nic->pkts_to_process) {
2738                         /* Quota for the current iteration has been met */
2739                         goto no_rx;
2740                 }
2741         }
2742
2743         netif_rx_complete(dev, napi);
2744
2745         for (i = 0; i < config->rx_ring_num; i++) {
2746                 if (fill_rx_buffers(nic, i) == -ENOMEM) {
2747                         DBG_PRINT(INFO_DBG, "%s:Out of memory", dev->name);
2748                         DBG_PRINT(INFO_DBG, " in Rx Poll!!\n");
2749                         break;
2750                 }
2751         }
2752         /* Re enable the Rx interrupts. */
2753         writeq(0x0, &bar0->rx_traffic_mask);
2754         readl(&bar0->rx_traffic_mask);
2755         atomic_dec(&nic->isr_cnt);
2756         return pkt_cnt;
2757
2758 no_rx:
2759         for (i = 0; i < config->rx_ring_num; i++) {
2760                 if (fill_rx_buffers(nic, i) == -ENOMEM) {
2761                         DBG_PRINT(INFO_DBG, "%s:Out of memory", dev->name);
2762                         DBG_PRINT(INFO_DBG, " in Rx Poll!!\n");
2763                         break;
2764                 }
2765         }
2766         atomic_dec(&nic->isr_cnt);
2767         return pkt_cnt;
2768 }
2769
2770 #ifdef CONFIG_NET_POLL_CONTROLLER
2771 /**
2772  * s2io_netpoll - netpoll event handler entry point
2773  * @dev : pointer to the device structure.
2774  * Description:
2775  *      This function will be called by upper layer to check for events on the
2776  * interface in situations where interrupts are disabled. It is used for
2777  * specific in-kernel networking tasks, such as remote consoles and kernel
2778  * debugging over the network (example netdump in RedHat).
2779  */
2780 static void s2io_netpoll(struct net_device *dev)
2781 {
2782         struct s2io_nic *nic = dev->priv;
2783         struct mac_info *mac_control;
2784         struct config_param *config;
2785         struct XENA_dev_config __iomem *bar0 = nic->bar0;
2786         u64 val64 = 0xFFFFFFFFFFFFFFFFULL;
2787         int i;
2788
2789         if (pci_channel_offline(nic->pdev))
2790                 return;
2791
2792         disable_irq(dev->irq);
2793
2794         atomic_inc(&nic->isr_cnt);
2795         mac_control = &nic->mac_control;
2796         config = &nic->config;
2797
2798         writeq(val64, &bar0->rx_traffic_int);
2799         writeq(val64, &bar0->tx_traffic_int);
2800
2801         /* we need to free up the transmitted skbufs or else netpoll will
2802          * run out of skbs and will fail and eventually netpoll application such
2803          * as netdump will fail.
2804          */
2805         for (i = 0; i < config->tx_fifo_num; i++)
2806                 tx_intr_handler(&mac_control->fifos[i]);
2807
2808         /* check for received packet and indicate up to network */
2809         for (i = 0; i < config->rx_ring_num; i++)
2810                 rx_intr_handler(&mac_control->rings[i]);
2811
2812         for (i = 0; i < config->rx_ring_num; i++) {
2813                 if (fill_rx_buffers(nic, i) == -ENOMEM) {
2814                         DBG_PRINT(INFO_DBG, "%s:Out of memory", dev->name);
2815                         DBG_PRINT(INFO_DBG, " in Rx Netpoll!!\n");
2816                         break;
2817                 }
2818         }
2819         atomic_dec(&nic->isr_cnt);
2820         enable_irq(dev->irq);
2821         return;
2822 }
2823 #endif
2824
2825 /**
2826  *  rx_intr_handler - Rx interrupt handler
2827  *  @nic: device private variable.
2828  *  Description:
2829  *  If the interrupt is because of a received frame or if the
2830  *  receive ring contains fresh as yet un-processed frames,this function is
2831  *  called. It picks out the RxD at which place the last Rx processing had
2832  *  stopped and sends the skb to the OSM's Rx handler and then increments
2833  *  the offset.
2834  *  Return Value:
2835  *  NONE.
2836  */
2837 static void rx_intr_handler(struct ring_info *ring_data)
2838 {
2839         struct s2io_nic *nic = ring_data->nic;
2840         struct net_device *dev = (struct net_device *) nic->dev;
2841         int get_block, put_block, put_offset;
2842         struct rx_curr_get_info get_info, put_info;
2843         struct RxD_t *rxdp;
2844         struct sk_buff *skb;
2845         int pkt_cnt = 0;
2846         int i;
2847         struct RxD1* rxdp1;
2848         struct RxD3* rxdp3;
2849
2850         spin_lock(&nic->rx_lock);
2851
2852         get_info = ring_data->rx_curr_get_info;
2853         get_block = get_info.block_index;
2854         memcpy(&put_info, &ring_data->rx_curr_put_info, sizeof(put_info));
2855         put_block = put_info.block_index;
2856         rxdp = ring_data->rx_blocks[get_block].rxds[get_info.offset].virt_addr;
2857         if (!napi) {
2858                 spin_lock(&nic->put_lock);
2859                 put_offset = ring_data->put_pos;
2860                 spin_unlock(&nic->put_lock);
2861         } else
2862                 put_offset = ring_data->put_pos;
2863
2864         while (RXD_IS_UP2DT(rxdp)) {
2865                 /*
2866                  * If your are next to put index then it's
2867                  * FIFO full condition
2868                  */
2869                 if ((get_block == put_block) &&
2870                     (get_info.offset + 1) == put_info.offset) {
2871                         DBG_PRINT(INTR_DBG, "%s: Ring Full\n",dev->name);
2872                         break;
2873                 }
2874                 skb = (struct sk_buff *) ((unsigned long)rxdp->Host_Control);
2875                 if (skb == NULL) {
2876                         DBG_PRINT(ERR_DBG, "%s: The skb is ",
2877                                   dev->name);
2878                         DBG_PRINT(ERR_DBG, "Null in Rx Intr\n");
2879                         spin_unlock(&nic->rx_lock);
2880                         return;
2881                 }
2882                 if (nic->rxd_mode == RXD_MODE_1) {
2883                         rxdp1 = (struct RxD1*)rxdp;
2884                         pci_unmap_single(nic->pdev, (dma_addr_t)
2885                                 rxdp1->Buffer0_ptr,
2886                                 dev->mtu +
2887                                 HEADER_ETHERNET_II_802_3_SIZE +
2888                                 HEADER_802_2_SIZE +
2889                                 HEADER_SNAP_SIZE,
2890                                 PCI_DMA_FROMDEVICE);
2891                 } else if (nic->rxd_mode == RXD_MODE_3B) {
2892                         rxdp3 = (struct RxD3*)rxdp;
2893                         pci_dma_sync_single_for_cpu(nic->pdev, (dma_addr_t)
2894                                 rxdp3->Buffer0_ptr,
2895                                 BUF0_LEN, PCI_DMA_FROMDEVICE);
2896                         pci_unmap_single(nic->pdev, (dma_addr_t)
2897                                 rxdp3->Buffer2_ptr,
2898                                 dev->mtu + 4,
2899                                 PCI_DMA_FROMDEVICE);
2900                 }
2901                 prefetch(skb->data);
2902                 rx_osm_handler(ring_data, rxdp);
2903                 get_info.offset++;
2904                 ring_data->rx_curr_get_info.offset = get_info.offset;
2905                 rxdp = ring_data->rx_blocks[get_block].
2906                                 rxds[get_info.offset].virt_addr;
2907                 if (get_info.offset == rxd_count[nic->rxd_mode]) {
2908                         get_info.offset = 0;
2909                         ring_data->rx_curr_get_info.offset = get_info.offset;
2910                         get_block++;
2911                         if (get_block == ring_data->block_count)
2912                                 get_block = 0;
2913                         ring_data->rx_curr_get_info.block_index = get_block;
2914                         rxdp = ring_data->rx_blocks[get_block].block_virt_addr;
2915                 }
2916
2917                 nic->pkts_to_process -= 1;
2918                 if ((napi) && (!nic->pkts_to_process))
2919                         break;
2920                 pkt_cnt++;
2921                 if ((indicate_max_pkts) && (pkt_cnt > indicate_max_pkts))
2922                         break;
2923         }
2924         if (nic->lro) {
2925                 /* Clear all LRO sessions before exiting */
2926                 for (i=0; i<MAX_LRO_SESSIONS; i++) {
2927                         struct lro *lro = &nic->lro0_n[i];
2928                         if (lro->in_use) {
2929                                 update_L3L4_header(nic, lro);
2930                                 queue_rx_frame(lro->parent);
2931                                 clear_lro_session(lro);
2932                         }
2933                 }
2934         }
2935
2936         spin_unlock(&nic->rx_lock);
2937 }
2938
2939 /**
2940  *  tx_intr_handler - Transmit interrupt handler
2941  *  @nic : device private variable
2942  *  Description:
2943  *  If an interrupt was raised to indicate DMA complete of the
2944  *  Tx packet, this function is called. It identifies the last TxD
2945  *  whose buffer was freed and frees all skbs whose data have already
2946  *  DMA'ed into the NICs internal memory.
2947  *  Return Value:
2948  *  NONE
2949  */
2950
2951 static void tx_intr_handler(struct fifo_info *fifo_data)
2952 {
2953         struct s2io_nic *nic = fifo_data->nic;
2954         struct net_device *dev = (struct net_device *) nic->dev;
2955         struct tx_curr_get_info get_info, put_info;
2956         struct sk_buff *skb;
2957         struct TxD *txdlp;
2958         u8 err_mask;
2959
2960         get_info = fifo_data->tx_curr_get_info;
2961         memcpy(&put_info, &fifo_data->tx_curr_put_info, sizeof(put_info));
2962         txdlp = (struct TxD *) fifo_data->list_info[get_info.offset].
2963             list_virt_addr;
2964         while ((!(txdlp->Control_1 & TXD_LIST_OWN_XENA)) &&
2965                (get_info.offset != put_info.offset) &&
2966                (txdlp->Host_Control)) {
2967                 /* Check for TxD errors */
2968                 if (txdlp->Control_1 & TXD_T_CODE) {
2969                         unsigned long long err;
2970                         err = txdlp->Control_1 & TXD_T_CODE;
2971                         if (err & 0x1) {
2972                                 nic->mac_control.stats_info->sw_stat.
2973                                                 parity_err_cnt++;
2974                         }
2975
2976                         /* update t_code statistics */
2977                         err_mask = err >> 48;
2978                         switch(err_mask) {
2979                                 case 2:
2980                                         nic->mac_control.stats_info->sw_stat.
2981                                                         tx_buf_abort_cnt++;
2982                                 break;
2983
2984                                 case 3:
2985                                         nic->mac_control.stats_info->sw_stat.
2986                                                         tx_desc_abort_cnt++;
2987                                 break;
2988
2989                                 case 7:
2990                                         nic->mac_control.stats_info->sw_stat.
2991                                                         tx_parity_err_cnt++;
2992                                 break;
2993
2994                                 case 10:
2995                                         nic->mac_control.stats_info->sw_stat.
2996                                                         tx_link_loss_cnt++;
2997                                 break;
2998
2999                                 case 15:
3000                                         nic->mac_control.stats_info->sw_stat.
3001                                                         tx_list_proc_err_cnt++;
3002                                 break;
3003                         }
3004                 }
3005
3006                 skb = s2io_txdl_getskb(fifo_data, txdlp, get_info.offset);
3007                 if (skb == NULL) {
3008                         DBG_PRINT(ERR_DBG, "%s: Null skb ",
3009                         __FUNCTION__);
3010                         DBG_PRINT(ERR_DBG, "in Tx Free Intr\n");
3011                         return;
3012                 }
3013
3014                 /* Updating the statistics block */
3015                 nic->stats.tx_bytes += skb->len;
3016                 nic->mac_control.stats_info->sw_stat.mem_freed += skb->truesize;
3017                 dev_kfree_skb_irq(skb);
3018
3019                 get_info.offset++;
3020                 if (get_info.offset == get_info.fifo_len + 1)
3021                         get_info.offset = 0;
3022                 txdlp = (struct TxD *) fifo_data->list_info
3023                     [get_info.offset].list_virt_addr;
3024                 fifo_data->tx_curr_get_info.offset =
3025                     get_info.offset;
3026         }
3027
3028         spin_lock(&nic->tx_lock);
3029         if (netif_queue_stopped(dev))
3030                 netif_wake_queue(dev);
3031         spin_unlock(&nic->tx_lock);
3032 }
3033
3034 /**
3035  *  s2io_mdio_write - Function to write in to MDIO registers
3036  *  @mmd_type : MMD type value (PMA/PMD/WIS/PCS/PHYXS)
3037  *  @addr     : address value
3038  *  @value    : data value
3039  *  @dev      : pointer to net_device structure
3040  *  Description:
3041  *  This function is used to write values to the MDIO registers
3042  *  NONE
3043  */
3044 static void s2io_mdio_write(u32 mmd_type, u64 addr, u16 value, struct net_device *dev)
3045 {
3046         u64 val64 = 0x0;
3047         struct s2io_nic *sp = dev->priv;
3048         struct XENA_dev_config __iomem *bar0 = sp->bar0;
3049
3050         //address transaction
3051         val64 = val64 | MDIO_MMD_INDX_ADDR(addr)
3052                         | MDIO_MMD_DEV_ADDR(mmd_type)
3053                         | MDIO_MMS_PRT_ADDR(0x0);
3054         writeq(val64, &bar0->mdio_control);
3055         val64 = val64 | MDIO_CTRL_START_TRANS(0xE);
3056         writeq(val64, &bar0->mdio_control);
3057         udelay(100);
3058
3059         //Data transaction
3060         val64 = 0x0;
3061         val64 = val64 | MDIO_MMD_INDX_ADDR(addr)
3062                         | MDIO_MMD_DEV_ADDR(mmd_type)
3063                         | MDIO_MMS_PRT_ADDR(0x0)
3064                         | MDIO_MDIO_DATA(value)
3065                         | MDIO_OP(MDIO_OP_WRITE_TRANS);
3066         writeq(val64, &bar0->mdio_control);
3067         val64 = val64 | MDIO_CTRL_START_TRANS(0xE);
3068         writeq(val64, &bar0->mdio_control);
3069         udelay(100);
3070
3071         val64 = 0x0;
3072         val64 = val64 | MDIO_MMD_INDX_ADDR(addr)
3073         | MDIO_MMD_DEV_ADDR(mmd_type)
3074         | MDIO_MMS_PRT_ADDR(0x0)
3075         | MDIO_OP(MDIO_OP_READ_TRANS);
3076         writeq(val64, &bar0->mdio_control);
3077         val64 = val64 | MDIO_CTRL_START_TRANS(0xE);
3078         writeq(val64, &bar0->mdio_control);
3079         udelay(100);
3080
3081 }
3082
3083 /**
3084  *  s2io_mdio_read - Function to write in to MDIO registers
3085  *  @mmd_type : MMD type value (PMA/PMD/WIS/PCS/PHYXS)
3086  *  @addr     : address value
3087  *  @dev      : pointer to net_device structure
3088  *  Description:
3089  *  This function is used to read values to the MDIO registers
3090  *  NONE
3091  */
3092 static u64 s2io_mdio_read(u32 mmd_type, u64 addr, struct net_device *dev)
3093 {
3094         u64 val64 = 0x0;
3095         u64 rval64 = 0x0;
3096         struct s2io_nic *sp = dev->priv;
3097         struct XENA_dev_config __iomem *bar0 = sp->bar0;
3098
3099         /* address transaction */
3100         val64 = val64 | MDIO_MMD_INDX_ADDR(addr)
3101                         | MDIO_MMD_DEV_ADDR(mmd_type)
3102                         | MDIO_MMS_PRT_ADDR(0x0);
3103         writeq(val64, &bar0->mdio_control);
3104         val64 = val64 | MDIO_CTRL_START_TRANS(0xE);
3105         writeq(val64, &bar0->mdio_control);
3106         udelay(100);
3107
3108         /* Data transaction */
3109         val64 = 0x0;
3110         val64 = val64 | MDIO_MMD_INDX_ADDR(addr)
3111                         | MDIO_MMD_DEV_ADDR(mmd_type)
3112                         | MDIO_MMS_PRT_ADDR(0x0)
3113                         | MDIO_OP(MDIO_OP_READ_TRANS);
3114         writeq(val64, &bar0->mdio_control);
3115         val64 = val64 | MDIO_CTRL_START_TRANS(0xE);
3116         writeq(val64, &bar0->mdio_control);
3117         udelay(100);
3118
3119         /* Read the value from regs */
3120         rval64 = readq(&bar0->mdio_control);
3121         rval64 = rval64 & 0xFFFF0000;
3122         rval64 = rval64 >> 16;
3123         return rval64;
3124 }
3125 /**
3126  *  s2io_chk_xpak_counter - Function to check the status of the xpak counters
3127  *  @counter      : couter value to be updated
3128  *  @flag         : flag to indicate the status
3129  *  @type         : counter type
3130  *  Description:
3131  *  This function is to check the status of the xpak counters value
3132  *  NONE
3133  */
3134
3135 static void s2io_chk_xpak_counter(u64 *counter, u64 * regs_stat, u32 index, u16 flag, u16 type)
3136 {
3137         u64 mask = 0x3;
3138         u64 val64;
3139         int i;
3140         for(i = 0; i <index; i++)
3141                 mask = mask << 0x2;
3142
3143         if(flag > 0)
3144         {
3145                 *counter = *counter + 1;
3146                 val64 = *regs_stat & mask;
3147                 val64 = val64 >> (index * 0x2);
3148                 val64 = val64 + 1;
3149                 if(val64 == 3)
3150                 {
3151                         switch(type)
3152                         {
3153                         case 1:
3154                                 DBG_PRINT(ERR_DBG, "Take Xframe NIC out of "
3155                                           "service. Excessive temperatures may "
3156                                           "result in premature transceiver "
3157                                           "failure \n");
3158                         break;
3159                         case 2:
3160                                 DBG_PRINT(ERR_DBG, "Take Xframe NIC out of "
3161                                           "service Excessive bias currents may "
3162                                           "indicate imminent laser diode "
3163                                           "failure \n");
3164                         break;
3165                         case 3:
3166                                 DBG_PRINT(ERR_DBG, "Take Xframe NIC out of "
3167                                           "service Excessive laser output "
3168                                           "power may saturate far-end "
3169                                           "receiver\n");
3170                         break;
3171                         default:
3172                                 DBG_PRINT(ERR_DBG, "Incorrect XPAK Alarm "
3173                                           "type \n");
3174                         }
3175                         val64 = 0x0;
3176                 }
3177                 val64 = val64 << (index * 0x2);
3178                 *regs_stat = (*regs_stat & (~mask)) | (val64);
3179
3180         } else {
3181                 *regs_stat = *regs_stat & (~mask);
3182         }
3183 }
3184
3185 /**
3186  *  s2io_updt_xpak_counter - Function to update the xpak counters
3187  *  @dev         : pointer to net_device struct
3188  *  Description:
3189  *  This function is to upate the status of the xpak counters value
3190  *  NONE
3191  */
3192 static void s2io_updt_xpak_counter(struct net_device *dev)
3193 {
3194         u16 flag  = 0x0;
3195         u16 type  = 0x0;
3196         u16 val16 = 0x0;
3197         u64 val64 = 0x0;
3198         u64 addr  = 0x0;
3199
3200         struct s2io_nic *sp = dev->priv;
3201         struct stat_block *stat_info = sp->mac_control.stats_info;
3202
3203         /* Check the communication with the MDIO slave */
3204         addr = 0x0000;
3205         val64 = 0x0;
3206         val64 = s2io_mdio_read(MDIO_MMD_PMA_DEV_ADDR, addr, dev);
3207         if((val64 == 0xFFFF) || (val64 == 0x0000))
3208         {
3209                 DBG_PRINT(ERR_DBG, "ERR: MDIO slave access failed - "
3210                           "Returned %llx\n", (unsigned long long)val64);
3211                 return;
3212         }
3213
3214         /* Check for the expecte value of 2040 at PMA address 0x0000 */
3215         if(val64 != 0x2040)
3216         {
3217                 DBG_PRINT(ERR_DBG, "Incorrect value at PMA address 0x0000 - ");
3218                 DBG_PRINT(ERR_DBG, "Returned: %llx- Expected: 0x2040\n",
3219                           (unsigned long long)val64);
3220                 return;
3221         }
3222
3223         /* Loading the DOM register to MDIO register */
3224         addr = 0xA100;
3225         s2io_mdio_write(MDIO_MMD_PMA_DEV_ADDR, addr, val16, dev);
3226         val64 = s2io_mdio_read(MDIO_MMD_PMA_DEV_ADDR, addr, dev);
3227
3228         /* Reading the Alarm flags */
3229         addr = 0xA070;
3230         val64 = 0x0;
3231         val64 = s2io_mdio_read(MDIO_MMD_PMA_DEV_ADDR, addr, dev);
3232
3233         flag = CHECKBIT(val64, 0x7);
3234         type = 1;
3235         s2io_chk_xpak_counter(&stat_info->xpak_stat.alarm_transceiver_temp_high,
3236                                 &stat_info->xpak_stat.xpak_regs_stat,
3237                                 0x0, flag, type);
3238
3239         if(CHECKBIT(val64, 0x6))
3240                 stat_info->xpak_stat.alarm_transceiver_temp_low++;
3241
3242         flag = CHECKBIT(val64, 0x3);
3243         type = 2;
3244         s2io_chk_xpak_counter(&stat_info->xpak_stat.alarm_laser_bias_current_high,
3245                                 &stat_info->xpak_stat.xpak_regs_stat,
3246                                 0x2, flag, type);
3247
3248         if(CHECKBIT(val64, 0x2))
3249                 stat_info->xpak_stat.alarm_laser_bias_current_low++;
3250
3251         flag = CHECKBIT(val64, 0x1);
3252         type = 3;
3253         s2io_chk_xpak_counter(&stat_info->xpak_stat.alarm_laser_output_power_high,
3254                                 &stat_info->xpak_stat.xpak_regs_stat,
3255                                 0x4, flag, type);
3256
3257         if(CHECKBIT(val64, 0x0))
3258                 stat_info->xpak_stat.alarm_laser_output_power_low++;
3259
3260         /* Reading the Warning flags */
3261         addr = 0xA074;
3262         val64 = 0x0;
3263         val64 = s2io_mdio_read(MDIO_MMD_PMA_DEV_ADDR, addr, dev);
3264
3265         if(CHECKBIT(val64, 0x7))
3266                 stat_info->xpak_stat.warn_transceiver_temp_high++;
3267
3268         if(CHECKBIT(val64, 0x6))
3269                 stat_info->xpak_stat.warn_transceiver_temp_low++;
3270
3271         if(CHECKBIT(val64, 0x3))
3272                 stat_info->xpak_stat.warn_laser_bias_current_high++;
3273
3274         if(CHECKBIT(val64, 0x2))
3275                 stat_info->xpak_stat.warn_laser_bias_current_low++;
3276
3277         if(CHECKBIT(val64, 0x1))
3278                 stat_info->xpak_stat.warn_laser_output_power_high++;
3279
3280         if(CHECKBIT(val64, 0x0))
3281                 stat_info->xpak_stat.warn_laser_output_power_low++;
3282 }
3283
3284 /**
3285  *  wait_for_cmd_complete - waits for a command to complete.
3286  *  @sp : private member of the device structure, which is a pointer to the
3287  *  s2io_nic structure.
3288  *  Description: Function that waits for a command to Write into RMAC
3289  *  ADDR DATA registers to be completed and returns either success or
3290  *  error depending on whether the command was complete or not.
3291  *  Return value:
3292  *   SUCCESS on success and FAILURE on failure.
3293  */
3294
3295 static int wait_for_cmd_complete(void __iomem *addr, u64 busy_bit,
3296                                 int bit_state)
3297 {
3298         int ret = FAILURE, cnt = 0, delay = 1;
3299         u64 val64;
3300
3301         if ((bit_state != S2IO_BIT_RESET) && (bit_state != S2IO_BIT_SET))
3302                 return FAILURE;
3303
3304         do {
3305                 val64 = readq(addr);
3306                 if (bit_state == S2IO_BIT_RESET) {
3307                         if (!(val64 & busy_bit)) {
3308                                 ret = SUCCESS;
3309                                 break;
3310                         }
3311                 } else {
3312                         if (!(val64 & busy_bit)) {
3313                                 ret = SUCCESS;
3314                                 break;
3315                         }
3316                 }
3317
3318                 if(in_interrupt())
3319                         mdelay(delay);
3320                 else
3321                         msleep(delay);
3322
3323                 if (++cnt >= 10)
3324                         delay = 50;
3325         } while (cnt < 20);
3326         return ret;
3327 }
3328 /*
3329  * check_pci_device_id - Checks if the device id is supported
3330  * @id : device id
3331  * Description: Function to check if the pci device id is supported by driver.
3332  * Return value: Actual device id if supported else PCI_ANY_ID
3333  */
3334 static u16 check_pci_device_id(u16 id)
3335 {
3336         switch (id) {
3337         case PCI_DEVICE_ID_HERC_WIN:
3338         case PCI_DEVICE_ID_HERC_UNI:
3339                 return XFRAME_II_DEVICE;
3340         case PCI_DEVICE_ID_S2IO_UNI:
3341         case PCI_DEVICE_ID_S2IO_WIN:
3342                 return XFRAME_I_DEVICE;
3343         default:
3344                 return PCI_ANY_ID;
3345         }
3346 }
3347
3348 /**
3349  *  s2io_reset - Resets the card.
3350  *  @sp : private member of the device structure.
3351  *  Description: Function to Reset the card. This function then also
3352  *  restores the previously saved PCI configuration space registers as
3353  *  the card reset also resets the configuration space.
3354  *  Return value:
3355  *  void.
3356  */
3357
3358 static void s2io_reset(struct s2io_nic * sp)
3359 {
3360         struct XENA_dev_config __iomem *bar0 = sp->bar0;
3361         u64 val64;
3362         u16 subid, pci_cmd;
3363         int i;
3364         u16 val16;
3365         unsigned long long up_cnt, down_cnt, up_time, down_time, reset_cnt;
3366         unsigned long long mem_alloc_cnt, mem_free_cnt, watchdog_cnt;
3367
3368         DBG_PRINT(INIT_DBG,"%s - Resetting XFrame card %s\n",
3369                         __FUNCTION__, sp->dev->name);
3370
3371         /* Back up  the PCI-X CMD reg, dont want to lose MMRBC, OST settings */
3372         pci_read_config_word(sp->pdev, PCIX_COMMAND_REGISTER, &(pci_cmd));
3373
3374         val64 = SW_RESET_ALL;
3375         writeq(val64, &bar0->sw_reset);
3376         if (strstr(sp->product_name, "CX4")) {
3377                 msleep(750);
3378         }
3379         msleep(250);
3380         for (i = 0; i < S2IO_MAX_PCI_CONFIG_SPACE_REINIT; i++) {
3381
3382                 /* Restore the PCI state saved during initialization. */
3383                 pci_restore_state(sp->pdev);
3384                 pci_read_config_word(sp->pdev, 0x2, &val16);
3385                 if (check_pci_device_id(val16) != (u16)PCI_ANY_ID)
3386                         break;
3387                 msleep(200);
3388         }
3389
3390         if (check_pci_device_id(val16) == (u16)PCI_ANY_ID) {
3391                 DBG_PRINT(ERR_DBG,"%s SW_Reset failed!\n", __FUNCTION__);
3392         }
3393
3394         pci_write_config_word(sp->pdev, PCIX_COMMAND_REGISTER, pci_cmd);
3395
3396         s2io_init_pci(sp);
3397
3398         /* Set swapper to enable I/O register access */
3399         s2io_set_swapper(sp);
3400
3401         /* Restore the MSIX table entries from local variables */
3402         restore_xmsi_data(sp);
3403
3404         /* Clear certain PCI/PCI-X fields after reset */
3405         if (sp->device_type == XFRAME_II_DEVICE) {
3406                 /* Clear "detected parity error" bit */
3407                 pci_write_config_word(sp->pdev, PCI_STATUS, 0x8000);
3408
3409                 /* Clearing PCIX Ecc status register */
3410                 pci_write_config_dword(sp->pdev, 0x68, 0x7C);
3411
3412                 /* Clearing PCI_STATUS error reflected here */
3413                 writeq(BIT(62), &bar0->txpic_int_reg);
3414         }
3415
3416         /* Reset device statistics maintained by OS */
3417         memset(&sp->stats, 0, sizeof (struct net_device_stats));
3418
3419         up_cnt = sp->mac_control.stats_info->sw_stat.link_up_cnt;
3420         down_cnt = sp->mac_control.stats_info->sw_stat.link_down_cnt;
3421         up_time = sp->mac_control.stats_info->sw_stat.link_up_time;
3422         down_time = sp->mac_control.stats_info->sw_stat.link_down_time;
3423         reset_cnt = sp->mac_control.stats_info->sw_stat.soft_reset_cnt;
3424         mem_alloc_cnt = sp->mac_control.stats_info->sw_stat.mem_allocated;
3425         mem_free_cnt = sp->mac_control.stats_info->sw_stat.mem_freed;
3426         watchdog_cnt = sp->mac_control.stats_info->sw_stat.watchdog_timer_cnt;
3427         /* save link up/down time/cnt, reset/memory/watchdog cnt */
3428         memset(sp->mac_control.stats_info, 0, sizeof(struct stat_block));
3429         /* restore link up/down time/cnt, reset/memory/watchdog cnt */
3430         sp->mac_control.stats_info->sw_stat.link_up_cnt = up_cnt;
3431         sp->mac_control.stats_info->sw_stat.link_down_cnt = down_cnt;
3432         sp->mac_control.stats_info->sw_stat.link_up_time = up_time;
3433         sp->mac_control.stats_info->sw_stat.link_down_time = down_time;
3434         sp->mac_control.stats_info->sw_stat.soft_reset_cnt = reset_cnt;
3435         sp->mac_control.stats_info->sw_stat.mem_allocated = mem_alloc_cnt;
3436         sp->mac_control.stats_info->sw_stat.mem_freed = mem_free_cnt;
3437         sp->mac_control.stats_info->sw_stat.watchdog_timer_cnt = watchdog_cnt;
3438
3439         /* SXE-002: Configure link and activity LED to turn it off */
3440         subid = sp->pdev->subsystem_device;
3441         if (((subid & 0xFF) >= 0x07) &&
3442             (sp->device_type == XFRAME_I_DEVICE)) {
3443                 val64 = readq(&bar0->gpio_control);
3444                 val64 |= 0x0000800000000000ULL;
3445                 writeq(val64, &bar0->gpio_control);
3446                 val64 = 0x0411040400000000ULL;
3447                 writeq(val64, (void __iomem *)bar0 + 0x2700);
3448         }
3449
3450         /*
3451          * Clear spurious ECC interrupts that would have occured on
3452          * XFRAME II cards after reset.
3453          */
3454         if (sp->device_type == XFRAME_II_DEVICE) {
3455                 val64 = readq(&bar0->pcc_err_reg);
3456                 writeq(val64, &bar0->pcc_err_reg);
3457         }
3458
3459         /* restore the previously assigned mac address */
3460         s2io_set_mac_addr(sp->dev, (u8 *)&sp->def_mac_addr[0].mac_addr);
3461
3462         sp->device_enabled_once = FALSE;
3463 }
3464
3465 /**
3466  *  s2io_set_swapper - to set the swapper controle on the card
3467  *  @sp : private member of the device structure,
3468  *  pointer to the s2io_nic structure.
3469  *  Description: Function to set the swapper control on the card
3470  *  correctly depending on the 'endianness' of the system.
3471  *  Return value:
3472  *  SUCCESS on success and FAILURE on failure.
3473  */
3474
3475 static int s2io_set_swapper(struct s2io_nic * sp)
3476 {
3477         struct net_device *dev = sp->dev;
3478         struct XENA_dev_config __iomem *bar0 = sp->bar0;
3479         u64 val64, valt, valr;
3480
3481         /*
3482          * Set proper endian settings and verify the same by reading
3483          * the PIF Feed-back register.
3484          */
3485
3486         val64 = readq(&bar0->pif_rd_swapper_fb);
3487         if (val64 != 0x0123456789ABCDEFULL) {
3488                 int i = 0;
3489                 u64 value[] = { 0xC30000C3C30000C3ULL,   /* FE=1, SE=1 */
3490                                 0x8100008181000081ULL,  /* FE=1, SE=0 */
3491                                 0x4200004242000042ULL,  /* FE=0, SE=1 */
3492                                 0};                     /* FE=0, SE=0 */
3493
3494                 while(i<4) {
3495                         writeq(value[i], &bar0->swapper_ctrl);
3496                         val64 = readq(&bar0->pif_rd_swapper_fb);
3497                         if (val64 == 0x0123456789ABCDEFULL)
3498                                 break;
3499                         i++;
3500                 }
3501                 if (i == 4) {
3502                         DBG_PRINT(ERR_DBG, "%s: Endian settings are wrong, ",
3503                                 dev->name);
3504                         DBG_PRINT(ERR_DBG, "feedback read %llx\n",
3505                                 (unsigned long long) val64);
3506                         return FAILURE;
3507                 }
3508                 valr = value[i];
3509         } else {
3510                 valr = readq(&bar0->swapper_ctrl);
3511         }
3512
3513         valt = 0x0123456789ABCDEFULL;
3514         writeq(valt, &bar0->xmsi_address);
3515         val64 = readq(&bar0->xmsi_address);
3516
3517         if(val64 != valt) {
3518                 int i = 0;
3519                 u64 value[] = { 0x00C3C30000C3C300ULL,  /* FE=1, SE=1 */
3520                                 0x0081810000818100ULL,  /* FE=1, SE=0 */
3521                                 0x0042420000424200ULL,  /* FE=0, SE=1 */
3522                                 0};                     /* FE=0, SE=0 */
3523
3524                 while(i<4) {
3525                         writeq((value[i] | valr), &bar0->swapper_ctrl);
3526                         writeq(valt, &bar0->xmsi_address);
3527                         val64 = readq(&bar0->xmsi_address);
3528                         if(val64 == valt)
3529                                 break;
3530                         i++;
3531                 }
3532                 if(i == 4) {
3533                         unsigned long long x = val64;
3534                         DBG_PRINT(ERR_DBG, "Write failed, Xmsi_addr ");
3535                         DBG_PRINT(ERR_DBG, "reads:0x%llx\n", x);
3536                         return FAILURE;
3537                 }
3538         }
3539         val64 = readq(&bar0->swapper_ctrl);
3540         val64 &= 0xFFFF000000000000ULL;
3541
3542 #ifdef  __BIG_ENDIAN
3543         /*
3544          * The device by default set to a big endian format, so a
3545          * big endian driver need not set anything.
3546          */
3547         val64 |= (SWAPPER_CTRL_TXP_FE |
3548                  SWAPPER_CTRL_TXP_SE |
3549                  SWAPPER_CTRL_TXD_R_FE |
3550                  SWAPPER_CTRL_TXD_W_FE |
3551                  SWAPPER_CTRL_TXF_R_FE |
3552                  SWAPPER_CTRL_RXD_R_FE |
3553                  SWAPPER_CTRL_RXD_W_FE |
3554                  SWAPPER_CTRL_RXF_W_FE |
3555                  SWAPPER_CTRL_XMSI_FE |
3556                  SWAPPER_CTRL_STATS_FE | SWAPPER_CTRL_STATS_SE);
3557         if (sp->config.intr_type == INTA)
3558                 val64 |= SWAPPER_CTRL_XMSI_SE;
3559         writeq(val64, &bar0->swapper_ctrl);
3560 #else
3561         /*
3562          * Initially we enable all bits to make it accessible by the
3563          * driver, then we selectively enable only those bits that
3564          * we want to set.
3565          */
3566         val64 |= (SWAPPER_CTRL_TXP_FE |
3567                  SWAPPER_CTRL_TXP_SE |
3568                  SWAPPER_CTRL_TXD_R_FE |
3569                  SWAPPER_CTRL_TXD_R_SE |
3570                  SWAPPER_CTRL_TXD_W_FE |
3571                  SWAPPER_CTRL_TXD_W_SE |
3572                  SWAPPER_CTRL_TXF_R_FE |
3573                  SWAPPER_CTRL_RXD_R_FE |
3574                  SWAPPER_CTRL_RXD_R_SE |
3575                  SWAPPER_CTRL_RXD_W_FE |
3576                  SWAPPER_CTRL_RXD_W_SE |
3577                  SWAPPER_CTRL_RXF_W_FE |
3578                  SWAPPER_CTRL_XMSI_FE |
3579                  SWAPPER_CTRL_STATS_FE | SWAPPER_CTRL_STATS_SE);
3580         if (sp->config.intr_type == INTA)
3581                 val64 |= SWAPPER_CTRL_XMSI_SE;
3582         writeq(val64, &bar0->swapper_ctrl);
3583 #endif
3584         val64 = readq(&bar0->swapper_ctrl);
3585
3586         /*
3587          * Verifying if endian settings are accurate by reading a
3588          * feedback register.
3589          */
3590         val64 = readq(&bar0->pif_rd_swapper_fb);
3591         if (val64 != 0x0123456789ABCDEFULL) {
3592                 /* Endian settings are incorrect, calls for another dekko. */
3593                 DBG_PRINT(ERR_DBG, "%s: Endian settings are wrong, ",
3594                           dev->name);
3595                 DBG_PRINT(ERR_DBG, "feedback read %llx\n",
3596                           (unsigned long long) val64);
3597                 return FAILURE;
3598         }
3599
3600         return SUCCESS;
3601 }
3602
3603 static int wait_for_msix_trans(struct s2io_nic *nic, int i)
3604 {
3605         struct XENA_dev_config __iomem *bar0 = nic->bar0;
3606         u64 val64;
3607         int ret = 0, cnt = 0;
3608
3609         do {
3610                 val64 = readq(&bar0->xmsi_access);
3611                 if (!(val64 & BIT(15)))
3612                         break;
3613                 mdelay(1);
3614                 cnt++;
3615         } while(cnt < 5);
3616         if (cnt == 5) {
3617                 DBG_PRINT(ERR_DBG, "XMSI # %d Access failed\n", i);
3618                 ret = 1;
3619         }
3620
3621         return ret;
3622 }
3623
3624 static void restore_xmsi_data(struct s2io_nic *nic)
3625 {
3626         struct XENA_dev_config __iomem *bar0 = nic->bar0;
3627         u64 val64;
3628         int i;
3629
3630         for (i=0; i < MAX_REQUESTED_MSI_X; i++) {
3631                 writeq(nic->msix_info[i].addr, &bar0->xmsi_address);
3632                 writeq(nic->msix_info[i].data, &bar0->xmsi_data);
3633                 val64 = (BIT(7) | BIT(15) | vBIT(i, 26, 6));
3634                 writeq(val64, &bar0->xmsi_access);
3635                 if (wait_for_msix_trans(nic, i)) {
3636                         DBG_PRINT(ERR_DBG, "failed in %s\n", __FUNCTION__);
3637                         continue;
3638                 }
3639         }
3640 }
3641
3642 static void store_xmsi_data(struct s2io_nic *nic)
3643 {
3644         struct XENA_dev_config __iomem *bar0 = nic->bar0;
3645         u64 val64, addr, data;
3646         int i;
3647
3648         /* Store and display */
3649         for (i=0; i < MAX_REQUESTED_MSI_X; i++) {
3650                 val64 = (BIT(15) | vBIT(i, 26, 6));
3651                 writeq(val64, &bar0->xmsi_access);
3652                 if (wait_for_msix_trans(nic, i)) {
3653                         DBG_PRINT(ERR_DBG, "failed in %s\n", __FUNCTION__);
3654                         continue;
3655                 }
3656                 addr = readq(&bar0->xmsi_address);
3657                 data = readq(&bar0->xmsi_data);
3658                 if (addr && data) {
3659                         nic->msix_info[i].addr = addr;
3660                         nic->msix_info[i].data = data;
3661                 }
3662         }
3663 }
3664
3665 static int s2io_enable_msi_x(struct s2io_nic *nic)
3666 {
3667         struct XENA_dev_config __iomem *bar0 = nic->bar0;
3668         u64 tx_mat, rx_mat;
3669         u16 msi_control; /* Temp variable */
3670         int ret, i, j, msix_indx = 1;
3671
3672         nic->entries = kmalloc(MAX_REQUESTED_MSI_X * sizeof(struct msix_entry),
3673                                GFP_KERNEL);
3674         if (nic->entries == NULL) {
3675                 DBG_PRINT(INFO_DBG, "%s: Memory allocation failed\n", \
3676                         __FUNCTION__);
3677                 nic->mac_control.stats_info->sw_stat.mem_alloc_fail_cnt++;
3678                 return -ENOMEM;
3679         }
3680         nic->mac_control.stats_info->sw_stat.mem_allocated
3681                 += (MAX_REQUESTED_MSI_X * sizeof(struct msix_entry));
3682         memset(nic->entries, 0,MAX_REQUESTED_MSI_X * sizeof(struct msix_entry));
3683
3684         nic->s2io_entries =
3685                 kmalloc(MAX_REQUESTED_MSI_X * sizeof(struct s2io_msix_entry),
3686                                    GFP_KERNEL);
3687         if (nic->s2io_entries == NULL) {
3688                 DBG_PRINT(INFO_DBG, "%s: Memory allocation failed\n",
3689                         __FUNCTION__);
3690                 nic->mac_control.stats_info->sw_stat.mem_alloc_fail_cnt++;
3691                 kfree(nic->entries);
3692                 nic->mac_control.stats_info->sw_stat.mem_freed
3693                         += (MAX_REQUESTED_MSI_X * sizeof(struct msix_entry));
3694                 return -ENOMEM;
3695         }
3696          nic->mac_control.stats_info->sw_stat.mem_allocated
3697                 += (MAX_REQUESTED_MSI_X * sizeof(struct s2io_msix_entry));
3698         memset(nic->s2io_entries, 0,
3699                MAX_REQUESTED_MSI_X * sizeof(struct s2io_msix_entry));
3700
3701         for (i=0; i< MAX_REQUESTED_MSI_X; i++) {
3702                 nic->entries[i].entry = i;
3703                 nic->s2io_entries[i].entry = i;
3704                 nic->s2io_entries[i].arg = NULL;
3705                 nic->s2io_entries[i].in_use = 0;
3706         }
3707
3708         tx_mat = readq(&bar0->tx_mat0_n[0]);
3709         for (i=0; i<nic->config.tx_fifo_num; i++, msix_indx++) {
3710                 tx_mat |= TX_MAT_SET(i, msix_indx);
3711                 nic->s2io_entries[msix_indx].arg = &nic->mac_control.fifos[i];
3712                 nic->s2io_entries[msix_indx].type = MSIX_FIFO_TYPE;
3713                 nic->s2io_entries[msix_indx].in_use = MSIX_FLG;
3714         }
3715         writeq(tx_mat, &bar0->tx_mat0_n[0]);
3716
3717         if (!nic->config.bimodal) {
3718                 rx_mat = readq(&bar0->rx_mat);
3719                 for (j=0; j<nic->config.rx_ring_num; j++, msix_indx++) {
3720                         rx_mat |= RX_MAT_SET(j, msix_indx);
3721                         nic->s2io_entries[msix_indx].arg
3722                                 = &nic->mac_control.rings[j];
3723                         nic->s2io_entries[msix_indx].type = MSIX_RING_TYPE;
3724                         nic->s2io_entries[msix_indx].in_use = MSIX_FLG;
3725                 }
3726                 writeq(rx_mat, &bar0->rx_mat);
3727         } else {
3728                 tx_mat = readq(&bar0->tx_mat0_n[7]);
3729                 for (j=0; j<nic->config.rx_ring_num; j++, msix_indx++) {
3730                         tx_mat |= TX_MAT_SET(i, msix_indx);
3731                         nic->s2io_entries[msix_indx].arg
3732                                 = &nic->mac_control.rings[j];
3733                         nic->s2io_entries[msix_indx].type = MSIX_RING_TYPE;
3734                         nic->s2io_entries[msix_indx].in_use = MSIX_FLG;
3735                 }
3736                 writeq(tx_mat, &bar0->tx_mat0_n[7]);
3737         }
3738
3739         nic->avail_msix_vectors = 0;
3740         ret = pci_enable_msix(nic->pdev, nic->entries, MAX_REQUESTED_MSI_X);
3741         /* We fail init if error or we get less vectors than min required */
3742         if (ret >= (nic->config.tx_fifo_num + nic->config.rx_ring_num + 1)) {
3743                 nic->avail_msix_vectors = ret;
3744                 ret = pci_enable_msix(nic->pdev, nic->entries, ret);
3745         }
3746         if (ret) {
3747                 DBG_PRINT(ERR_DBG, "%s: Enabling MSIX failed\n", nic->dev->name);
3748                 kfree(nic->entries);
3749                 nic->mac_control.stats_info->sw_stat.mem_freed
3750                         += (MAX_REQUESTED_MSI_X * sizeof(struct msix_entry));
3751                 kfree(nic->s2io_entries);
3752                 nic->mac_control.stats_info->sw_stat.mem_freed
3753                 += (MAX_REQUESTED_MSI_X * sizeof(struct s2io_msix_entry));
3754                 nic->entries = NULL;
3755                 nic->s2io_entries = NULL;
3756                 nic->avail_msix_vectors = 0;
3757                 return -ENOMEM;
3758         }
3759         if (!nic->avail_msix_vectors)
3760                 nic->avail_msix_vectors = MAX_REQUESTED_MSI_X;
3761
3762         /*
3763          * To enable MSI-X, MSI also needs to be enabled, due to a bug
3764          * in the herc NIC. (Temp change, needs to be removed later)
3765          */
3766         pci_read_config_word(nic->pdev, 0x42, &msi_control);
3767         msi_control |= 0x1; /* Enable MSI */
3768         pci_write_config_word(nic->pdev, 0x42, msi_control);
3769
3770         return 0;
3771 }
3772
3773 /* Handle software interrupt used during MSI(X) test */
3774 static irqreturn_t __devinit s2io_test_intr(int irq, void *dev_id)
3775 {
3776         struct s2io_nic *sp = dev_id;
3777
3778         sp->msi_detected = 1;
3779         wake_up(&sp->msi_wait);
3780
3781         return IRQ_HANDLED;
3782 }
3783
3784 /* Test interrupt path by forcing a a software IRQ */
3785 static int __devinit s2io_test_msi(struct s2io_nic *sp)
3786 {
3787         struct pci_dev *pdev = sp->pdev;
3788         struct XENA_dev_config __iomem *bar0 = sp->bar0;
3789         int err;
3790         u64 val64, saved64;
3791
3792         err = request_irq(sp->entries[1].vector, s2io_test_intr, 0,
3793                         sp->name, sp);
3794         if (err) {
3795                 DBG_PRINT(ERR_DBG, "%s: PCI %s: cannot assign irq %d\n",
3796                        sp->dev->name, pci_name(pdev), pdev->irq);
3797                 return err;
3798         }
3799
3800         init_waitqueue_head (&sp->msi_wait);
3801         sp->msi_detected = 0;
3802
3803         saved64 = val64 = readq(&bar0->scheduled_int_ctrl);
3804         val64 |= SCHED_INT_CTRL_ONE_SHOT;
3805         val64 |= SCHED_INT_CTRL_TIMER_EN;
3806         val64 |= SCHED_INT_CTRL_INT2MSI(1);
3807         writeq(val64, &bar0->scheduled_int_ctrl);
3808
3809         wait_event_timeout(sp->msi_wait, sp->msi_detected, HZ/10);
3810
3811         if (!sp->msi_detected) {
3812                 /* MSI(X) test failed, go back to INTx mode */
3813                 DBG_PRINT(ERR_DBG, "%s: PCI %s: No interrupt was generated"
3814                         "using MSI(X) during test\n", sp->dev->name,
3815                         pci_name(pdev));
3816
3817                 err = -EOPNOTSUPP;
3818         }
3819
3820         free_irq(sp->entries[1].vector, sp);
3821
3822         writeq(saved64, &bar0->scheduled_int_ctrl);
3823
3824         return err;
3825 }
3826 /* ********************************************************* *
3827  * Functions defined below concern the OS part of the driver *
3828  * ********************************************************* */
3829
3830 /**
3831  *  s2io_open - open entry point of the driver
3832  *  @dev : pointer to the device structure.
3833  *  Description:
3834  *  This function is the open entry point of the driver. It mainly calls a
3835  *  function to allocate Rx buffers and inserts them into the buffer
3836  *  descriptors and then enables the Rx part of the NIC.
3837  *  Return value:
3838  *  0 on success and an appropriate (-)ve integer as defined in errno.h
3839  *   file on failure.
3840  */
3841
3842 static int s2io_open(struct net_device *dev)
3843 {
3844         struct s2io_nic *sp = dev->priv;
3845         int err = 0;
3846
3847         /*
3848          * Make sure you have link off by default every time
3849          * Nic is initialized
3850          */
3851         netif_carrier_off(dev);
3852         sp->last_link_state = 0;
3853
3854         napi_enable(&sp->napi);
3855
3856         if (sp->config.intr_type == MSI_X) {
3857                 int ret = s2io_enable_msi_x(sp);
3858
3859                 if (!ret) {
3860                         u16 msi_control;
3861
3862                         ret = s2io_test_msi(sp);
3863
3864                         /* rollback MSI-X, will re-enable during add_isr() */
3865                         kfree(sp->entries);
3866                         sp->mac_control.stats_info->sw_stat.mem_freed +=
3867                                 (MAX_REQUESTED_MSI_X *
3868                                 sizeof(struct msix_entry));
3869                         kfree(sp->s2io_entries);
3870                         sp->mac_control.stats_info->sw_stat.mem_freed +=
3871                                 (MAX_REQUESTED_MSI_X *
3872                                 sizeof(struct s2io_msix_entry));
3873                         sp->entries = NULL;
3874                         sp->s2io_entries = NULL;
3875
3876                         pci_read_config_word(sp->pdev, 0x42, &msi_control);
3877                         msi_control &= 0xFFFE; /* Disable MSI */
3878                         pci_write_config_word(sp->pdev, 0x42, msi_control);
3879
3880                         pci_disable_msix(sp->pdev);
3881
3882                 }
3883                 if (ret) {
3884
3885                         DBG_PRINT(ERR_DBG,
3886                           "%s: MSI-X requested but failed to enable\n",
3887                           dev->name);
3888                         sp->config.intr_type = INTA;
3889                 }
3890         }
3891
3892         /* NAPI doesn't work well with MSI(X) */
3893          if (sp->config.intr_type != INTA) {
3894                 if(sp->config.napi)
3895                         sp->config.napi = 0;
3896         }
3897
3898         /* Initialize H/W and enable interrupts */
3899         err = s2io_card_up(sp);
3900         if (err) {
3901                 DBG_PRINT(ERR_DBG, "%s: H/W initialization failed\n",
3902                           dev->name);
3903                 goto hw_init_failed;
3904         }
3905
3906         if (s2io_set_mac_addr(dev, dev->dev_addr) == FAILURE) {
3907                 DBG_PRINT(ERR_DBG, "Set Mac Address Failed\n");
3908                 s2io_card_down(sp);
3909                 err = -ENODEV;
3910                 goto hw_init_failed;
3911         }
3912
3913         netif_start_queue(dev);
3914         return 0;
3915
3916 hw_init_failed:
3917         napi_disable(&sp->napi);
3918         if (sp->config.intr_type == MSI_X) {
3919                 if (sp->entries) {
3920                         kfree(sp->entries);
3921                         sp->mac_control.stats_info->sw_stat.mem_freed
3922                         += (MAX_REQUESTED_MSI_X * sizeof(struct msix_entry));
3923                 }
3924                 if (sp->s2io_entries) {
3925                         kfree(sp->s2io_entries);
3926                         sp->mac_control.stats_info->sw_stat.mem_freed
3927                         += (MAX_REQUESTED_MSI_X * sizeof(struct s2io_msix_entry));
3928                 }
3929         }
3930         return err;
3931 }
3932
3933 /**
3934  *  s2io_close -close entry point of the driver
3935  *  @dev : device pointer.
3936  *  Description:
3937  *  This is the stop entry point of the driver. It needs to undo exactly
3938  *  whatever was done by the open entry point,thus it's usually referred to
3939  *  as the close function.Among other things this function mainly stops the
3940  *  Rx side of the NIC and frees all the Rx buffers in the Rx rings.
3941  *  Return value:
3942  *  0 on success and an appropriate (-)ve integer as defined in errno.h
3943  *  file on failure.
3944  */
3945
3946 static int s2io_close(struct net_device *dev)
3947 {
3948         struct s2io_nic *sp = dev->priv;
3949
3950         netif_stop_queue(dev);
3951         napi_disable(&sp->napi);
3952         /* Reset card, kill tasklet and free Tx and Rx buffers. */
3953         s2io_card_down(sp);
3954
3955         return 0;
3956 }
3957
3958 /**
3959  *  s2io_xmit - Tx entry point of te driver
3960  *  @skb : the socket buffer containing the Tx data.
3961  *  @dev : device pointer.
3962  *  Description :
3963  *  This function is the Tx entry point of the driver. S2IO NIC supports
3964  *  certain protocol assist features on Tx side, namely  CSO, S/G, LSO.
3965  *  NOTE: when device cant queue the pkt,just the trans_start variable will
3966  *  not be upadted.
3967  *  Return value:
3968  *  0 on success & 1 on failure.
3969  */
3970
3971 static int s2io_xmit(struct sk_buff *skb, struct net_device *dev)
3972 {
3973         struct s2io_nic *sp = dev->priv;
3974         u16 frg_cnt, frg_len, i, queue, queue_len, put_off, get_off;
3975         register u64 val64;
3976         struct TxD *txdp;
3977         struct TxFIFO_element __iomem *tx_fifo;
3978         unsigned long flags;
3979         u16 vlan_tag = 0;
3980         int vlan_priority = 0;
3981         struct mac_info *mac_control;
3982         struct config_param *config;
3983         int offload_type;
3984         struct swStat *stats = &sp->mac_control.stats_info->sw_stat;
3985
3986         mac_control = &sp->mac_control;
3987         config = &sp->config;
3988
3989         DBG_PRINT(TX_DBG, "%s: In Neterion Tx routine\n", dev->name);
3990
3991         if (unlikely(skb->len <= 0)) {
3992                 DBG_PRINT(TX_DBG, "%s:Buffer has no data..\n", dev->name);
3993                 dev_kfree_skb_any(skb);
3994                 return 0;
3995 }
3996
3997         spin_lock_irqsave(&sp->tx_lock, flags);
3998         if (!is_s2io_card_up(sp)) {
3999                 DBG_PRINT(TX_DBG, "%s: Card going down for reset\n",
4000                           dev->name);
4001                 spin_unlock_irqrestore(&sp->tx_lock, flags);
4002                 dev_kfree_skb(skb);
4003                 return 0;
4004         }
4005
4006         queue = 0;
4007         /* Get Fifo number to Transmit based on vlan priority */
4008         if (sp->vlgrp && vlan_tx_tag_present(skb)) {
4009                 vlan_tag = vlan_tx_tag_get(skb);
4010                 vlan_priority = vlan_tag >> 13;
4011                 queue = config->fifo_mapping[vlan_priority];
4012         }
4013
4014         put_off = (u16) mac_control->fifos[queue].tx_curr_put_info.offset;
4015         get_off = (u16) mac_control->fifos[queue].tx_curr_get_info.offset;
4016         txdp = (struct TxD *) mac_control->fifos[queue].list_info[put_off].
4017                 list_virt_addr;
4018
4019         queue_len = mac_control->fifos[queue].tx_curr_put_info.fifo_len + 1;
4020         /* Avoid "put" pointer going beyond "get" pointer */
4021         if (txdp->Host_Control ||
4022                    ((put_off+1) == queue_len ? 0 : (put_off+1)) == get_off) {
4023                 DBG_PRINT(TX_DBG, "Error in xmit, No free TXDs.\n");
4024                 netif_stop_queue(dev);
4025                 dev_kfree_skb(skb);
4026                 spin_unlock_irqrestore(&sp->tx_lock, flags);
4027                 return 0;
4028         }
4029
4030         offload_type = s2io_offload_type(skb);
4031         if (offload_type & (SKB_GSO_TCPV4 | SKB_GSO_TCPV6)) {
4032                 txdp->Control_1 |= TXD_TCP_LSO_EN;
4033                 txdp->Control_1 |= TXD_TCP_LSO_MSS(s2io_tcp_mss(skb));
4034         }
4035         if (skb->ip_summed == CHECKSUM_PARTIAL) {
4036                 txdp->Control_2 |=
4037                     (TXD_TX_CKO_IPV4_EN | TXD_TX_CKO_TCP_EN |
4038                      TXD_TX_CKO_UDP_EN);
4039         }
4040         txdp->Control_1 |= TXD_GATHER_CODE_FIRST;
4041         txdp->Control_1 |= TXD_LIST_OWN_XENA;
4042         txdp->Control_2 |= config->tx_intr_type;
4043
4044         if (sp->vlgrp && vlan_tx_tag_present(skb)) {
4045                 txdp->Control_2 |= TXD_VLAN_ENABLE;
4046                 txdp->Control_2 |= TXD_VLAN_TAG(vlan_tag);
4047         }
4048
4049         frg_len = skb->len - skb->data_len;
4050         if (offload_type == SKB_GSO_UDP) {
4051                 int ufo_size;
4052
4053                 ufo_size = s2io_udp_mss(skb);
4054                 ufo_size &= ~7;
4055                 txdp->Control_1 |= TXD_UFO_EN;
4056                 txdp->Control_1 |= TXD_UFO_MSS(ufo_size);
4057                 txdp->Control_1 |= TXD_BUFFER0_SIZE(8);
4058 #ifdef __BIG_ENDIAN
4059                 sp->ufo_in_band_v[put_off] =
4060                                 (u64)skb_shinfo(skb)->ip6_frag_id;
4061 #else
4062                 sp->ufo_in_band_v[put_off] =
4063                                 (u64)skb_shinfo(skb)->ip6_frag_id << 32;
4064 #endif
4065                 txdp->Host_Control = (unsigned long)sp->ufo_in_band_v;
4066                 txdp->Buffer_Pointer = pci_map_single(sp->pdev,
4067                                         sp->ufo_in_band_v,
4068                                         sizeof(u64), PCI_DMA_TODEVICE);
4069                 if((txdp->Buffer_Pointer == 0) ||
4070                         (txdp->Buffer_Pointer == DMA_ERROR_CODE))
4071                         goto pci_map_failed;
4072                 txdp++;
4073         }
4074
4075         txdp->Buffer_Pointer = pci_map_single
4076             (sp->pdev, skb->data, frg_len, PCI_DMA_TODEVICE);
4077         if((txdp->Buffer_Pointer == 0) ||
4078                 (txdp->Buffer_Pointer == DMA_ERROR_CODE))
4079                 goto pci_map_failed;
4080
4081         txdp->Host_Control = (unsigned long) skb;
4082         txdp->Control_1 |= TXD_BUFFER0_SIZE(frg_len);
4083         if (offload_type == SKB_GSO_UDP)
4084                 txdp->Control_1 |= TXD_UFO_EN;
4085
4086         frg_cnt = skb_shinfo(skb)->nr_frags;
4087         /* For fragmented SKB. */
4088         for (i = 0; i < frg_cnt; i++) {
4089                 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
4090                 /* A '0' length fragment will be ignored */
4091                 if (!frag->size)
4092                         continue;
4093                 txdp++;
4094                 txdp->Buffer_Pointer = (u64) pci_map_page
4095                     (sp->pdev, frag->page, frag->page_offset,
4096                      frag->size, PCI_DMA_TODEVICE);
4097                 txdp->Control_1 = TXD_BUFFER0_SIZE(frag->size);
4098                 if (offload_type == SKB_GSO_UDP)
4099                         txdp->Control_1 |= TXD_UFO_EN;
4100         }
4101         txdp->Control_1 |= TXD_GATHER_CODE_LAST;
4102
4103         if (offload_type == SKB_GSO_UDP)
4104                 frg_cnt++; /* as Txd0 was used for inband header */
4105
4106         tx_fifo = mac_control->tx_FIFO_start[queue];
4107         val64 = mac_control->fifos[queue].list_info[put_off].list_phy_addr;
4108         writeq(val64, &tx_fifo->TxDL_Pointer);
4109
4110         val64 = (TX_FIFO_LAST_TXD_NUM(frg_cnt) | TX_FIFO_FIRST_LIST |
4111                  TX_FIFO_LAST_LIST);
4112         if (offload_type)
4113                 val64 |= TX_FIFO_SPECIAL_FUNC;
4114
4115         writeq(val64, &tx_fifo->List_Control);
4116
4117         mmiowb();
4118
4119         put_off++;
4120         if (put_off == mac_control->fifos[queue].tx_curr_put_info.fifo_len + 1)
4121                 put_off = 0;
4122         mac_control->fifos[queue].tx_curr_put_info.offset = put_off;
4123
4124         /* Avoid "put" pointer going beyond "get" pointer */
4125         if (((put_off+1) == queue_len ? 0 : (put_off+1)) == get_off) {
4126                 sp->mac_control.stats_info->sw_stat.fifo_full_cnt++;
4127                 DBG_PRINT(TX_DBG,
4128                           "No free TxDs for xmit, Put: 0x%x Get:0x%x\n",
4129                           put_off, get_off);
4130                 netif_stop_queue(dev);
4131         }
4132         mac_control->stats_info->sw_stat.mem_allocated += skb->truesize;
4133         dev->trans_start = jiffies;
4134         spin_unlock_irqrestore(&sp->tx_lock, flags);
4135
4136         return 0;
4137 pci_map_failed:
4138         stats->pci_map_fail_cnt++;
4139         netif_stop_queue(dev);
4140         stats->mem_freed += skb->truesize;
4141         dev_kfree_skb(skb);
4142         spin_unlock_irqrestore(&sp->tx_lock, flags);
4143         return 0;
4144 }
4145
4146 static void
4147 s2io_alarm_handle(unsigned long data)
4148 {
4149         struct s2io_nic *sp = (struct s2io_nic *)data;
4150         struct net_device *dev = sp->dev;
4151
4152         s2io_handle_errors(dev);
4153         mod_timer(&sp->alarm_timer, jiffies + HZ / 2);
4154 }
4155
4156 static int s2io_chk_rx_buffers(struct s2io_nic *sp, int rng_n)
4157 {
4158         int rxb_size, level;
4159
4160         if (!sp->lro) {
4161                 rxb_size = atomic_read(&sp->rx_bufs_left[rng_n]);
4162                 level = rx_buffer_level(sp, rxb_size, rng_n);
4163
4164                 if ((level == PANIC) && (!TASKLET_IN_USE)) {
4165                         int ret;
4166                         DBG_PRINT(INTR_DBG, "%s: Rx BD hit ", __FUNCTION__);
4167                         DBG_PRINT(INTR_DBG, "PANIC levels\n");
4168                         if ((ret = fill_rx_buffers(sp, rng_n)) == -ENOMEM) {
4169                                 DBG_PRINT(INFO_DBG, "Out of memory in %s",
4170                                           __FUNCTION__);
4171                                 clear_bit(0, (&sp->tasklet_status));
4172                                 return -1;
4173                         }
4174                         clear_bit(0, (&sp->tasklet_status));
4175                 } else if (level == LOW)
4176                         tasklet_schedule(&sp->task);
4177
4178         } else if (fill_rx_buffers(sp, rng_n) == -ENOMEM) {
4179                         DBG_PRINT(INFO_DBG, "%s:Out of memory", sp->dev->name);
4180                         DBG_PRINT(INFO_DBG, " in Rx Intr!!\n");
4181         }
4182         return 0;
4183 }
4184
4185 static irqreturn_t s2io_msix_ring_handle(int irq, void *dev_id)
4186 {
4187         struct ring_info *ring = (struct ring_info *)dev_id;
4188         struct s2io_nic *sp = ring->nic;
4189
4190         atomic_inc(&sp->isr_cnt);
4191
4192         if (!is_s2io_card_up(sp)) {
4193                 atomic_dec(&sp->isr_cnt);
4194                 return IRQ_HANDLED;
4195         }
4196
4197         rx_intr_handler(ring);
4198         s2io_chk_rx_buffers(sp, ring->ring_no);
4199
4200         atomic_dec(&sp->isr_cnt);
4201         return IRQ_HANDLED;
4202 }
4203
4204 static irqreturn_t s2io_msix_fifo_handle(int irq, void *dev_id)
4205 {
4206         struct fifo_info *fifo = (struct fifo_info *)dev_id;
4207         struct s2io_nic *sp = fifo->nic;
4208
4209         atomic_inc(&sp->isr_cnt);
4210
4211         if (!is_s2io_card_up(sp)) {
4212                 atomic_dec(&sp->isr_cnt);
4213                 return IRQ_HANDLED;
4214         }
4215
4216         tx_intr_handler(fifo);
4217         atomic_dec(&sp->isr_cnt);
4218         return IRQ_HANDLED;
4219 }
4220 static void s2io_txpic_intr_handle(struct s2io_nic *sp)
4221 {
4222         struct XENA_dev_config __iomem *bar0 = sp->bar0;
4223         u64 val64;
4224
4225         val64 = readq(&bar0->pic_int_status);
4226         if (val64 & PIC_INT_GPIO) {
4227                 val64 = readq(&bar0->gpio_int_reg);
4228                 if ((val64 & GPIO_INT_REG_LINK_DOWN) &&
4229                     (val64 & GPIO_INT_REG_LINK_UP)) {
4230                         /*
4231                          * This is unstable state so clear both up/down
4232                          * interrupt and adapter to re-evaluate the link state.
4233                          */
4234                         val64 |=  GPIO_INT_REG_LINK_DOWN;
4235                         val64 |= GPIO_INT_REG_LINK_UP;
4236                         writeq(val64, &bar0->gpio_int_reg);
4237                         val64 = readq(&bar0->gpio_int_mask);
4238                         val64 &= ~(GPIO_INT_MASK_LINK_UP |
4239                                    GPIO_INT_MASK_LINK_DOWN);
4240                         writeq(val64, &bar0->gpio_int_mask);
4241                 }
4242                 else if (val64 & GPIO_INT_REG_LINK_UP) {
4243                         val64 = readq(&bar0->adapter_status);
4244                                 /* Enable Adapter */
4245                         val64 = readq(&bar0->adapter_control);
4246                         val64 |= ADAPTER_CNTL_EN;
4247                         writeq(val64, &bar0->adapter_control);
4248                         val64 |= ADAPTER_LED_ON;
4249                         writeq(val64, &bar0->adapter_control);
4250                         if (!sp->device_enabled_once)
4251                                 sp->device_enabled_once = 1;
4252
4253                         s2io_link(sp, LINK_UP);
4254                         /*
4255                          * unmask link down interrupt and mask link-up
4256                          * intr
4257                          */
4258                         val64 = readq(&bar0->gpio_int_mask);
4259                         val64 &= ~GPIO_INT_MASK_LINK_DOWN;
4260                         val64 |= GPIO_INT_MASK_LINK_UP;
4261                         writeq(val64, &bar0->gpio_int_mask);
4262
4263                 }else if (val64 & GPIO_INT_REG_LINK_DOWN) {
4264                         val64 = readq(&bar0->adapter_status);
4265                         s2io_link(sp, LINK_DOWN);
4266                         /* Link is down so unmaks link up interrupt */
4267                         val64 = readq(&bar0->gpio_int_mask);
4268                         val64 &= ~GPIO_INT_MASK_LINK_UP;
4269                         val64 |= GPIO_INT_MASK_LINK_DOWN;
4270                         writeq(val64, &bar0->gpio_int_mask);
4271
4272                         /* turn off LED */
4273                         val64 = readq(&bar0->adapter_control);
4274                         val64 = val64 &(~ADAPTER_LED_ON);
4275                         writeq(val64, &bar0->adapter_control);
4276                 }
4277         }
4278         val64 = readq(&bar0->gpio_int_mask);
4279 }
4280
4281 /**
4282  *  do_s2io_chk_alarm_bit - Check for alarm and incrment the counter
4283  *  @value: alarm bits
4284  *  @addr: address value
4285  *  @cnt: counter variable
4286  *  Description: Check for alarm and increment the counter
4287  *  Return Value:
4288  *  1 - if alarm bit set
4289  *  0 - if alarm bit is not set
4290  */
4291 int do_s2io_chk_alarm_bit(u64 value, void __iomem * addr,
4292                           unsigned long long *cnt)
4293 {
4294         u64 val64;
4295         val64 = readq(addr);
4296         if ( val64 & value ) {
4297                 writeq(val64, addr);
4298                 (*cnt)++;
4299                 return 1;
4300         }
4301         return 0;
4302
4303 }
4304
4305 /**
4306  *  s2io_handle_errors - Xframe error indication handler
4307  *  @nic: device private variable
4308  *  Description: Handle alarms such as loss of link, single or
4309  *  double ECC errors, critical and serious errors.
4310  *  Return Value:
4311  *  NONE
4312  */
4313 static void s2io_handle_errors(void * dev_id)
4314 {
4315         struct net_device *dev = (struct net_device *) dev_id;
4316         struct s2io_nic *sp = dev->priv;
4317         struct XENA_dev_config __iomem *bar0 = sp->bar0;
4318         u64 temp64 = 0,val64=0;
4319         int i = 0;
4320
4321         struct swStat *sw_stat = &sp->mac_control.stats_info->sw_stat;
4322         struct xpakStat *stats = &sp->mac_control.stats_info->xpak_stat;
4323
4324         if (!is_s2io_card_up(sp))
4325                 return;
4326
4327         if (pci_channel_offline(sp->pdev))
4328                 return;
4329
4330         memset(&sw_stat->ring_full_cnt, 0,
4331                 sizeof(sw_stat->ring_full_cnt));
4332
4333         /* Handling the XPAK counters update */
4334         if(stats->xpak_timer_count < 72000) {
4335                 /* waiting for an hour */
4336                 stats->xpak_timer_count++;
4337         } else {
4338                 s2io_updt_xpak_counter(dev);
4339                 /* reset the count to zero */
4340                 stats->xpak_timer_count = 0;
4341         }
4342
4343         /* Handling link status change error Intr */
4344         if (s2io_link_fault_indication(sp) == MAC_RMAC_ERR_TIMER) {
4345                 val64 = readq(&bar0->mac_rmac_err_reg);
4346                 writeq(val64, &bar0->mac_rmac_err_reg);
4347                 if (val64 & RMAC_LINK_STATE_CHANGE_INT)
4348                         schedule_work(&sp->set_link_task);
4349         }
4350
4351         /* In case of a serious error, the device will be Reset. */
4352         if (do_s2io_chk_alarm_bit(SERR_SOURCE_ANY, &bar0->serr_source,
4353                                 &sw_stat->serious_err_cnt))
4354                 goto reset;
4355
4356         /* Check for data parity error */
4357         if (do_s2io_chk_alarm_bit(GPIO_INT_REG_DP_ERR_INT, &bar0->gpio_int_reg,
4358                                 &sw_stat->parity_err_cnt))
4359                 goto reset;
4360
4361         /* Check for ring full counter */
4362         if (sp->device_type == XFRAME_II_DEVICE) {
4363                 val64 = readq(&bar0->ring_bump_counter1);
4364                 for (i=0; i<4; i++) {
4365                         temp64 = ( val64 & vBIT(0xFFFF,(i*16),16));
4366                         temp64 >>= 64 - ((i+1)*16);
4367                         sw_stat->ring_full_cnt[i] += temp64;
4368                 }
4369
4370                 val64 = readq(&bar0->ring_bump_counter2);
4371                 for (i=0; i<4; i++) {
4372                         temp64 = ( val64 & vBIT(0xFFFF,(i*16),16));
4373                         temp64 >>= 64 - ((i+1)*16);
4374                          sw_stat->ring_full_cnt[i+4] += temp64;
4375                 }
4376         }
4377
4378         val64 = readq(&bar0->txdma_int_status);
4379         /*check for pfc_err*/
4380         if (val64 & TXDMA_PFC_INT) {
4381                 if (do_s2io_chk_alarm_bit(PFC_ECC_DB_ERR | PFC_SM_ERR_ALARM|
4382                                 PFC_MISC_0_ERR | PFC_MISC_1_ERR|
4383                                 PFC_PCIX_ERR, &bar0->pfc_err_reg,
4384                                 &sw_stat->pfc_err_cnt))
4385                         goto reset;
4386                 do_s2io_chk_alarm_bit(PFC_ECC_SG_ERR, &bar0->pfc_err_reg,
4387                                 &sw_stat->pfc_err_cnt);
4388         }
4389
4390         /*check for tda_err*/
4391         if (val64 & TXDMA_TDA_INT) {
4392                 if(do_s2io_chk_alarm_bit(TDA_Fn_ECC_DB_ERR | TDA_SM0_ERR_ALARM |
4393                                 TDA_SM1_ERR_ALARM, &bar0->tda_err_reg,
4394                                 &sw_stat->tda_err_cnt))
4395                         goto reset;
4396                 do_s2io_chk_alarm_bit(TDA_Fn_ECC_SG_ERR | TDA_PCIX_ERR,
4397                                 &bar0->tda_err_reg, &sw_stat->tda_err_cnt);
4398         }
4399         /*check for pcc_err*/
4400         if (val64 & TXDMA_PCC_INT) {
4401                 if (do_s2io_chk_alarm_bit(PCC_SM_ERR_ALARM | PCC_WR_ERR_ALARM
4402                                 | PCC_N_SERR | PCC_6_COF_OV_ERR
4403                                 | PCC_7_COF_OV_ERR | PCC_6_LSO_OV_ERR
4404                                 | PCC_7_LSO_OV_ERR | PCC_FB_ECC_DB_ERR
4405                                 | PCC_TXB_ECC_DB_ERR, &bar0->pcc_err_reg,
4406                                 &sw_stat->pcc_err_cnt))
4407                         goto reset;
4408                 do_s2io_chk_alarm_bit(PCC_FB_ECC_SG_ERR | PCC_TXB_ECC_SG_ERR,
4409                                 &bar0->pcc_err_reg, &sw_stat->pcc_err_cnt);
4410         }
4411
4412         /*check for tti_err*/
4413         if (val64 & TXDMA_TTI_INT) {
4414                 if (do_s2io_chk_alarm_bit(TTI_SM_ERR_ALARM, &bar0->tti_err_reg,
4415                                 &sw_stat->tti_err_cnt))
4416                         goto reset;
4417                 do_s2io_chk_alarm_bit(TTI_ECC_SG_ERR | TTI_ECC_DB_ERR,
4418                                 &bar0->tti_err_reg, &sw_stat->tti_err_cnt);
4419         }
4420
4421         /*check for lso_err*/
4422         if (val64 & TXDMA_LSO_INT) {
4423                 if (do_s2io_chk_alarm_bit(LSO6_ABORT | LSO7_ABORT
4424                                 | LSO6_SM_ERR_ALARM | LSO7_SM_ERR_ALARM,
4425                                 &bar0->lso_err_reg, &sw_stat->lso_err_cnt))
4426                         goto reset;
4427                 do_s2io_chk_alarm_bit(LSO6_SEND_OFLOW | LSO7_SEND_OFLOW,
4428                                 &bar0->lso_err_reg, &sw_stat->lso_err_cnt);
4429         }
4430
4431         /*check for tpa_err*/
4432         if (val64 & TXDMA_TPA_INT) {
4433                 if (do_s2io_chk_alarm_bit(TPA_SM_ERR_ALARM, &bar0->tpa_err_reg,
4434                         &sw_stat->tpa_err_cnt))
4435                         goto reset;
4436                 do_s2io_chk_alarm_bit(TPA_TX_FRM_DROP, &bar0->tpa_err_reg,
4437                         &sw_stat->tpa_err_cnt);
4438         }
4439
4440         /*check for sm_err*/
4441         if (val64 & TXDMA_SM_INT) {
4442                 if (do_s2io_chk_alarm_bit(SM_SM_ERR_ALARM, &bar0->sm_err_reg,
4443                         &sw_stat->sm_err_cnt))
4444                         goto reset;
4445         }
4446
4447         val64 = readq(&bar0->mac_int_status);
4448         if (val64 & MAC_INT_STATUS_TMAC_INT) {
4449                 if (do_s2io_chk_alarm_bit(TMAC_TX_BUF_OVRN | TMAC_TX_SM_ERR,
4450                                 &bar0->mac_tmac_err_reg,
4451                                 &sw_stat->mac_tmac_err_cnt))
4452                         goto reset;
4453                 do_s2io_chk_alarm_bit(TMAC_ECC_SG_ERR | TMAC_ECC_DB_ERR
4454                                 | TMAC_DESC_ECC_SG_ERR | TMAC_DESC_ECC_DB_ERR,
4455                                 &bar0->mac_tmac_err_reg,
4456                                 &sw_stat->mac_tmac_err_cnt);
4457         }
4458
4459         val64 = readq(&bar0->xgxs_int_status);
4460         if (val64 & XGXS_INT_STATUS_TXGXS) {
4461                 if (do_s2io_chk_alarm_bit(TXGXS_ESTORE_UFLOW | TXGXS_TX_SM_ERR,
4462                                 &bar0->xgxs_txgxs_err_reg,
4463                                 &sw_stat->xgxs_txgxs_err_cnt))
4464                         goto reset;
4465                 do_s2io_chk_alarm_bit(TXGXS_ECC_SG_ERR | TXGXS_ECC_DB_ERR,
4466                                 &bar0->xgxs_txgxs_err_reg,
4467                                 &sw_stat->xgxs_txgxs_err_cnt);
4468         }
4469
4470         val64 = readq(&bar0->rxdma_int_status);
4471         if (val64 & RXDMA_INT_RC_INT_M) {
4472                 if (do_s2io_chk_alarm_bit(RC_PRCn_ECC_DB_ERR | RC_FTC_ECC_DB_ERR
4473                                 | RC_PRCn_SM_ERR_ALARM |RC_FTC_SM_ERR_ALARM,
4474                                 &bar0->rc_err_reg, &sw_stat->rc_err_cnt))
4475                         goto reset;
4476                 do_s2io_chk_alarm_bit(RC_PRCn_ECC_SG_ERR | RC_FTC_ECC_SG_ERR
4477                                 | RC_RDA_FAIL_WR_Rn, &bar0->rc_err_reg,
4478                                 &sw_stat->rc_err_cnt);
4479                 if (do_s2io_chk_alarm_bit(PRC_PCI_AB_RD_Rn | PRC_PCI_AB_WR_Rn
4480                                 | PRC_PCI_AB_F_WR_Rn, &bar0->prc_pcix_err_reg,
4481                                 &sw_stat->prc_pcix_err_cnt))
4482                         goto reset;
4483                 do_s2io_chk_alarm_bit(PRC_PCI_DP_RD_Rn | PRC_PCI_DP_WR_Rn
4484                                 | PRC_PCI_DP_F_WR_Rn, &bar0->prc_pcix_err_reg,
4485                                 &sw_stat->prc_pcix_err_cnt);
4486         }
4487
4488         if (val64 & RXDMA_INT_RPA_INT_M) {
4489                 if (do_s2io_chk_alarm_bit(RPA_SM_ERR_ALARM | RPA_CREDIT_ERR,
4490                                 &bar0->rpa_err_reg, &sw_stat->rpa_err_cnt))
4491                         goto reset;
4492                 do_s2io_chk_alarm_bit(RPA_ECC_SG_ERR | RPA_ECC_DB_ERR,
4493                                 &bar0->rpa_err_reg, &sw_stat->rpa_err_cnt);
4494         }
4495
4496         if (val64 & RXDMA_INT_RDA_INT_M) {
4497                 if (do_s2io_chk_alarm_bit(RDA_RXDn_ECC_DB_ERR
4498                                 | RDA_FRM_ECC_DB_N_AERR | RDA_SM1_ERR_ALARM
4499                                 | RDA_SM0_ERR_ALARM | RDA_RXD_ECC_DB_SERR,
4500                                 &bar0->rda_err_reg, &sw_stat->rda_err_cnt))
4501                         goto reset;
4502                 do_s2io_chk_alarm_bit(RDA_RXDn_ECC_SG_ERR | RDA_FRM_ECC_SG_ERR
4503                                 | RDA_MISC_ERR | RDA_PCIX_ERR,
4504                                 &bar0->rda_err_reg, &sw_stat->rda_err_cnt);
4505         }
4506
4507         if (val64 & RXDMA_INT_RTI_INT_M) {
4508                 if (do_s2io_chk_alarm_bit(RTI_SM_ERR_ALARM, &bar0->rti_err_reg,
4509                                 &sw_stat->rti_err_cnt))
4510                         goto reset;
4511                 do_s2io_chk_alarm_bit(RTI_ECC_SG_ERR | RTI_ECC_DB_ERR,
4512                                 &bar0->rti_err_reg, &sw_stat->rti_err_cnt);
4513         }
4514
4515         val64 = readq(&bar0->mac_int_status);
4516         if (val64 & MAC_INT_STATUS_RMAC_INT) {
4517                 if (do_s2io_chk_alarm_bit(RMAC_RX_BUFF_OVRN | RMAC_RX_SM_ERR,
4518                                 &bar0->mac_rmac_err_reg,
4519                                 &sw_stat->mac_rmac_err_cnt))
4520                         goto reset;
4521                 do_s2io_chk_alarm_bit(RMAC_UNUSED_INT|RMAC_SINGLE_ECC_ERR|
4522                                 RMAC_DOUBLE_ECC_ERR, &bar0->mac_rmac_err_reg,
4523                                 &sw_stat->mac_rmac_err_cnt);
4524         }
4525
4526         val64 = readq(&bar0->xgxs_int_status);
4527         if (val64 & XGXS_INT_STATUS_RXGXS) {
4528                 if (do_s2io_chk_alarm_bit(RXGXS_ESTORE_OFLOW | RXGXS_RX_SM_ERR,
4529                                 &bar0->xgxs_rxgxs_err_reg,
4530                                 &sw_stat->xgxs_rxgxs_err_cnt))
4531                         goto reset;
4532         }
4533
4534         val64 = readq(&bar0->mc_int_status);
4535         if(val64 & MC_INT_STATUS_MC_INT) {
4536                 if (do_s2io_chk_alarm_bit(MC_ERR_REG_SM_ERR, &bar0->mc_err_reg,
4537                                 &sw_stat->mc_err_cnt))
4538                         goto reset;
4539
4540                 /* Handling Ecc errors */
4541                 if (val64 & (MC_ERR_REG_ECC_ALL_SNG | MC_ERR_REG_ECC_ALL_DBL)) {
4542                         writeq(val64, &bar0->mc_err_reg);
4543                         if (val64 & MC_ERR_REG_ECC_ALL_DBL) {
4544                                 sw_stat->double_ecc_errs++;
4545                                 if (sp->device_type != XFRAME_II_DEVICE) {
4546                                         /*
4547                                          * Reset XframeI only if critical error
4548                                          */
4549                                         if (val64 &
4550                                                 (MC_ERR_REG_MIRI_ECC_DB_ERR_0 |
4551                                                 MC_ERR_REG_MIRI_ECC_DB_ERR_1))
4552                                                                 goto reset;
4553                                         }
4554                         } else
4555                                 sw_stat->single_ecc_errs++;
4556                 }
4557         }
4558         return;
4559
4560 reset:
4561         netif_stop_queue(dev);
4562         schedule_work(&sp->rst_timer_task);
4563         sw_stat->soft_reset_cnt++;
4564         return;
4565 }
4566
4567 /**
4568  *  s2io_isr - ISR handler of the device .
4569  *  @irq: the irq of the device.
4570  *  @dev_id: a void pointer to the dev structure of the NIC.
4571  *  Description:  This function is the ISR handler of the device. It
4572  *  identifies the reason for the interrupt and calls the relevant
4573  *  service routines. As a contongency measure, this ISR allocates the
4574  *  recv buffers, if their numbers are below the panic value which is
4575  *  presently set to 25% of the original number of rcv buffers allocated.
4576  *  Return value:
4577  *   IRQ_HANDLED: will be returned if IRQ was handled by this routine
4578  *   IRQ_NONE: will be returned if interrupt is not from our device
4579  */
4580 static irqreturn_t s2io_isr(int irq, void *dev_id)
4581 {
4582         struct net_device *dev = (struct net_device *) dev_id;
4583         struct s2io_nic *sp = dev->priv;
4584         struct XENA_dev_config __iomem *bar0 = sp->bar0;
4585         int i;
4586         u64 reason = 0;
4587         struct mac_info *mac_control;
4588         struct config_param *config;
4589
4590         /* Pretend we handled any irq's from a disconnected card */
4591         if (pci_channel_offline(sp->pdev))
4592                 return IRQ_NONE;
4593
4594         atomic_inc(&sp->isr_cnt);
4595
4596         if (!is_s2io_card_up(sp)) {
4597                 atomic_dec(&sp->isr_cnt);
4598                 return IRQ_NONE;
4599         }
4600
4601         mac_control = &sp->mac_control;
4602         config = &sp->config;
4603
4604         /*
4605          * Identify the cause for interrupt and call the appropriate
4606          * interrupt handler. Causes for the interrupt could be;
4607          * 1. Rx of packet.
4608          * 2. Tx complete.
4609          * 3. Link down.
4610          * 4. Error in any functional blocks of the NIC.
4611          */
4612         reason = readq(&bar0->general_int_status);
4613
4614         if (!reason) {
4615                 /* The interrupt was not raised by us. */
4616                 atomic_dec(&sp->isr_cnt);
4617                 return IRQ_NONE;
4618         }
4619         else if (unlikely(reason == S2IO_MINUS_ONE) ) {
4620                 /* Disable device and get out */
4621                 atomic_dec(&sp->isr_cnt);
4622                 return IRQ_NONE;
4623         }
4624
4625         if (napi) {
4626                 if (reason & GEN_INTR_RXTRAFFIC) {
4627                         if (likely (netif_rx_schedule_prep(dev, &sp->napi))) {
4628                                 __netif_rx_schedule(dev, &sp->napi);
4629                                 writeq(S2IO_MINUS_ONE, &bar0->rx_traffic_mask);
4630                         }
4631                         else
4632                                 writeq(S2IO_MINUS_ONE, &bar0->rx_traffic_int);
4633                 }
4634         } else {
4635                 /*
4636                  * Rx handler is called by default, without checking for the
4637                  * cause of interrupt.
4638                  * rx_traffic_int reg is an R1 register, writing all 1's
4639                  * will ensure that the actual interrupt causing bit get's
4640                  * cleared and hence a read can be avoided.
4641                  */
4642                 if (reason & GEN_INTR_RXTRAFFIC)
4643                         writeq(S2IO_MINUS_ONE, &bar0->rx_traffic_int);
4644
4645                 for (i = 0; i < config->rx_ring_num; i++) {
4646                         rx_intr_handler(&mac_control->rings[i]);
4647                 }
4648         }
4649
4650         /*
4651          * tx_traffic_int reg is an R1 register, writing all 1's
4652          * will ensure that the actual interrupt causing bit get's
4653          * cleared and hence a read can be avoided.
4654          */
4655         if (reason & GEN_INTR_TXTRAFFIC)
4656                 writeq(S2IO_MINUS_ONE, &bar0->tx_traffic_int);
4657
4658         for (i = 0; i < config->tx_fifo_num; i++)
4659                 tx_intr_handler(&mac_control->fifos[i]);
4660
4661         if (reason & GEN_INTR_TXPIC)
4662                 s2io_txpic_intr_handle(sp);
4663         /*
4664          * If the Rx buffer count is below the panic threshold then
4665          * reallocate the buffers from the interrupt handler itself,
4666          * else schedule a tasklet to reallocate the buffers.
4667          */
4668         if (!napi) {
4669                 for (i = 0; i < config->rx_ring_num; i++)
4670                         s2io_chk_rx_buffers(sp, i);
4671         }
4672
4673         writeq(0, &bar0->general_int_mask);
4674         readl(&bar0->general_int_status);
4675
4676         atomic_dec(&sp->isr_cnt);
4677         return IRQ_HANDLED;
4678 }
4679
4680 /**
4681  * s2io_updt_stats -
4682  */
4683 static void s2io_updt_stats(struct s2io_nic *sp)
4684 {
4685         struct XENA_dev_config __iomem *bar0 = sp->bar0;
4686         u64 val64;
4687         int cnt = 0;
4688
4689         if (is_s2io_card_up(sp)) {
4690                 /* Apprx 30us on a 133 MHz bus */
4691                 val64 = SET_UPDT_CLICKS(10) |
4692                         STAT_CFG_ONE_SHOT_EN | STAT_CFG_STAT_EN;
4693                 writeq(val64, &bar0->stat_cfg);
4694                 do {
4695                         udelay(100);
4696                         val64 = readq(&bar0->stat_cfg);
4697                         if (!(val64 & BIT(0)))
4698                                 break;
4699                         cnt++;
4700                         if (cnt == 5)
4701                                 break; /* Updt failed */
4702                 } while(1);
4703         }
4704 }
4705
4706 /**
4707  *  s2io_get_stats - Updates the device statistics structure.
4708  *  @dev : pointer to the device structure.
4709  *  Description:
4710  *  This function updates the device statistics structure in the s2io_nic
4711  *  structure and returns a pointer to the same.
4712  *  Return value:
4713  *  pointer to the updated net_device_stats structure.
4714  */
4715
4716 static struct net_device_stats *s2io_get_stats(struct net_device *dev)
4717 {
4718         struct s2io_nic *sp = dev->priv;
4719         struct mac_info *mac_control;
4720         struct config_param *config;
4721
4722
4723         mac_control = &sp->mac_control;
4724         config = &sp->config;
4725
4726         /* Configure Stats for immediate updt */
4727         s2io_updt_stats(sp);
4728
4729         sp->stats.tx_packets =
4730                 le32_to_cpu(mac_control->stats_info->tmac_frms);
4731         sp->stats.tx_errors =
4732                 le32_to_cpu(mac_control->stats_info->tmac_any_err_frms);
4733         sp->stats.rx_errors =
4734                 le64_to_cpu(mac_control->stats_info->rmac_drop_frms);
4735         sp->stats.multicast =
4736                 le32_to_cpu(mac_control->stats_info->rmac_vld_mcst_frms);
4737         sp->stats.rx_length_errors =
4738                 le64_to_cpu(mac_control->stats_info->rmac_long_frms);
4739
4740         return (&sp->stats);
4741 }
4742
4743 /**
4744  *  s2io_set_multicast - entry point for multicast address enable/disable.
4745  *  @dev : pointer to the device structure
4746  *  Description:
4747  *  This function is a driver entry point which gets called by the kernel
4748  *  whenever multicast addresses must be enabled/disabled. This also gets
4749  *  called to set/reset promiscuous mode. Depending on the deivce flag, we
4750  *  determine, if multicast address must be enabled or if promiscuous mode
4751  *  is to be disabled etc.
4752  *  Return value:
4753  *  void.
4754  */
4755
4756 static void s2io_set_multicast(struct net_device *dev)
4757 {
4758         int i, j, prev_cnt;
4759         struct dev_mc_list *mclist;
4760         struct s2io_nic *sp = dev->priv;
4761         struct XENA_dev_config __iomem *bar0 = sp->bar0;
4762         u64 val64 = 0, multi_mac = 0x010203040506ULL, mask =
4763             0xfeffffffffffULL;
4764         u64 dis_addr = 0xffffffffffffULL, mac_addr = 0;
4765         void __iomem *add;
4766
4767         if ((dev->flags & IFF_ALLMULTI) && (!sp->m_cast_flg)) {
4768                 /*  Enable all Multicast addresses */
4769                 writeq(RMAC_ADDR_DATA0_MEM_ADDR(multi_mac),
4770                        &bar0->rmac_addr_data0_mem);
4771                 writeq(RMAC_ADDR_DATA1_MEM_MASK(mask),
4772                        &bar0->rmac_addr_data1_mem);
4773                 val64 = RMAC_ADDR_CMD_MEM_WE |
4774                     RMAC_ADDR_CMD_MEM_STROBE_NEW_CMD |
4775                     RMAC_ADDR_CMD_MEM_OFFSET(MAC_MC_ALL_MC_ADDR_OFFSET);
4776                 writeq(val64, &bar0->rmac_addr_cmd_mem);
4777                 /* Wait till command completes */
4778                 wait_for_cmd_complete(&bar0->rmac_addr_cmd_mem,
4779                                         RMAC_ADDR_CMD_MEM_STROBE_CMD_EXECUTING,
4780                                         S2IO_BIT_RESET);
4781
4782                 sp->m_cast_flg = 1;
4783                 sp->all_multi_pos = MAC_MC_ALL_MC_ADDR_OFFSET;
4784         } else if ((dev->flags & IFF_ALLMULTI) && (sp->m_cast_flg)) {
4785                 /*  Disable all Multicast addresses */
4786                 writeq(RMAC_ADDR_DATA0_MEM_ADDR(dis_addr),
4787                        &bar0->rmac_addr_data0_mem);
4788                 writeq(RMAC_ADDR_DATA1_MEM_MASK(0x0),
4789                        &bar0->rmac_addr_data1_mem);
4790                 val64 = RMAC_ADDR_CMD_MEM_WE |
4791                     RMAC_ADDR_CMD_MEM_STROBE_NEW_CMD |
4792                     RMAC_ADDR_CMD_MEM_OFFSET(sp->all_multi_pos);
4793                 writeq(val64, &bar0->rmac_addr_cmd_mem);
4794                 /* Wait till command completes */
4795                 wait_for_cmd_complete(&bar0->rmac_addr_cmd_mem,
4796                                         RMAC_ADDR_CMD_MEM_STROBE_CMD_EXECUTING,
4797                                         S2IO_BIT_RESET);
4798
4799                 sp->m_cast_flg = 0;
4800                 sp->all_multi_pos = 0;
4801         }
4802
4803         if ((dev->flags & IFF_PROMISC) && (!sp->promisc_flg)) {
4804                 /*  Put the NIC into promiscuous mode */
4805                 add = &bar0->mac_cfg;
4806                 val64 = readq(&bar0->mac_cfg);
4807                 val64 |= MAC_CFG_RMAC_PROM_ENABLE;
4808
4809                 writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
4810                 writel((u32) val64, add);
4811                 writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
4812                 writel((u32) (val64 >> 32), (add + 4));
4813
4814                 if (vlan_tag_strip != 1) {
4815                         val64 = readq(&bar0->rx_pa_cfg);
4816                         val64 &= ~RX_PA_CFG_STRIP_VLAN_TAG;
4817                         writeq(val64, &bar0->rx_pa_cfg);
4818                         vlan_strip_flag = 0;
4819                 }
4820
4821                 val64 = readq(&bar0->mac_cfg);
4822                 sp->promisc_flg = 1;
4823                 DBG_PRINT(INFO_DBG, "%s: entered promiscuous mode\n",
4824                           dev->name);
4825         } else if (!(dev->flags & IFF_PROMISC) && (sp->promisc_flg)) {
4826                 /*  Remove the NIC from promiscuous mode */
4827                 add = &bar0->mac_cfg;
4828                 val64 = readq(&bar0->mac_cfg);
4829                 val64 &= ~MAC_CFG_RMAC_PROM_ENABLE;
4830
4831                 writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
4832                 writel((u32) val64, add);
4833                 writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
4834                 writel((u32) (val64 >> 32), (add + 4));
4835
4836                 if (vlan_tag_strip != 0) {
4837                         val64 = readq(&bar0->rx_pa_cfg);
4838                         val64 |= RX_PA_CFG_STRIP_VLAN_TAG;
4839                         writeq(val64, &bar0->rx_pa_cfg);
4840                         vlan_strip_flag = 1;
4841                 }
4842
4843                 val64 = readq(&bar0->mac_cfg);
4844                 sp->promisc_flg = 0;
4845                 DBG_PRINT(INFO_DBG, "%s: left promiscuous mode\n",
4846                           dev->name);
4847         }
4848
4849         /*  Update individual M_CAST address list */
4850         if ((!sp->m_cast_flg) && dev->mc_count) {
4851                 if (dev->mc_count >
4852                     (MAX_ADDRS_SUPPORTED - MAC_MC_ADDR_START_OFFSET - 1)) {
4853                         DBG_PRINT(ERR_DBG, "%s: No more Rx filters ",
4854                                   dev->name);
4855                         DBG_PRINT(ERR_DBG, "can be added, please enable ");
4856                         DBG_PRINT(ERR_DBG, "ALL_MULTI instead\n");
4857                         return;
4858                 }
4859
4860                 prev_cnt = sp->mc_addr_count;
4861                 sp->mc_addr_count = dev->mc_count;
4862
4863                 /* Clear out the previous list of Mc in the H/W. */
4864                 for (i = 0; i < prev_cnt; i++) {
4865                         writeq(RMAC_ADDR_DATA0_MEM_ADDR(dis_addr),
4866                                &bar0->rmac_addr_data0_mem);
4867                         writeq(RMAC_ADDR_DATA1_MEM_MASK(0ULL),
4868                                 &bar0->rmac_addr_data1_mem);
4869                         val64 = RMAC_ADDR_CMD_MEM_WE |
4870                             RMAC_ADDR_CMD_MEM_STROBE_NEW_CMD |
4871                             RMAC_ADDR_CMD_MEM_OFFSET
4872                             (MAC_MC_ADDR_START_OFFSET + i);
4873                         writeq(val64, &bar0->rmac_addr_cmd_mem);
4874
4875                         /* Wait for command completes */
4876                         if (wait_for_cmd_complete(&bar0->rmac_addr_cmd_mem,
4877                                         RMAC_ADDR_CMD_MEM_STROBE_CMD_EXECUTING,
4878                                         S2IO_BIT_RESET)) {
4879                                 DBG_PRINT(ERR_DBG, "%s: Adding ",
4880                                           dev->name);
4881                                 DBG_PRINT(ERR_DBG, "Multicasts failed\n");
4882                                 return;
4883                         }
4884                 }
4885
4886                 /* Create the new Rx filter list and update the same in H/W. */
4887                 for (i = 0, mclist = dev->mc_list; i < dev->mc_count;
4888                      i++, mclist = mclist->next) {
4889                         memcpy(sp->usr_addrs[i].addr, mclist->dmi_addr,
4890                                ETH_ALEN);
4891                         mac_addr = 0;
4892                         for (j = 0; j < ETH_ALEN; j++) {
4893                                 mac_addr |= mclist->dmi_addr[j];
4894                                 mac_addr <<= 8;
4895                         }
4896                         mac_addr >>= 8;
4897                         writeq(RMAC_ADDR_DATA0_MEM_ADDR(mac_addr),
4898                                &bar0->rmac_addr_data0_mem);
4899                         writeq(RMAC_ADDR_DATA1_MEM_MASK(0ULL),
4900                                 &bar0->rmac_addr_data1_mem);
4901                         val64 = RMAC_ADDR_CMD_MEM_WE |
4902                             RMAC_ADDR_CMD_MEM_STROBE_NEW_CMD |
4903                             RMAC_ADDR_CMD_MEM_OFFSET
4904                             (i + MAC_MC_ADDR_START_OFFSET);
4905                         writeq(val64, &bar0->rmac_addr_cmd_mem);
4906
4907                         /* Wait for command completes */
4908                         if (wait_for_cmd_complete(&bar0->rmac_addr_cmd_mem,
4909                                         RMAC_ADDR_CMD_MEM_STROBE_CMD_EXECUTING,
4910                                         S2IO_BIT_RESET)) {
4911                                 DBG_PRINT(ERR_DBG, "%s: Adding ",
4912                                           dev->name);
4913                                 DBG_PRINT(ERR_DBG, "Multicasts failed\n");
4914                                 return;
4915                         }
4916                 }
4917         }
4918 }
4919
4920 /**
4921  *  s2io_set_mac_addr - Programs the Xframe mac address
4922  *  @dev : pointer to the device structure.
4923  *  @addr: a uchar pointer to the new mac address which is to be set.
4924  *  Description : This procedure will program the Xframe to receive
4925  *  frames with new Mac Address
4926  *  Return value: SUCCESS on success and an appropriate (-)ve integer
4927  *  as defined in errno.h file on failure.
4928  */
4929
4930 static int s2io_set_mac_addr(struct net_device *dev, u8 * addr)
4931 {
4932         struct s2io_nic *sp = dev->priv;
4933         struct XENA_dev_config __iomem *bar0 = sp->bar0;
4934         register u64 val64, mac_addr = 0;
4935         int i;
4936         u64 old_mac_addr = 0;
4937
4938         /*
4939          * Set the new MAC address as the new unicast filter and reflect this
4940          * change on the device address registered with the OS. It will be
4941          * at offset 0.
4942          */
4943         for (i = 0; i < ETH_ALEN; i++) {
4944                 mac_addr <<= 8;
4945                 mac_addr |= addr[i];
4946                 old_mac_addr <<= 8;
4947                 old_mac_addr |= sp->def_mac_addr[0].mac_addr[i];
4948         }
4949
4950         if(0 == mac_addr)
4951                 return SUCCESS;
4952
4953         /* Update the internal structure with this new mac address */
4954         if(mac_addr != old_mac_addr) {
4955                 memset(sp->def_mac_addr[0].mac_addr, 0, sizeof(ETH_ALEN));
4956                 sp->def_mac_addr[0].mac_addr[5] = (u8) (mac_addr);
4957                 sp->def_mac_addr[0].mac_addr[4] = (u8) (mac_addr >> 8);
4958                 sp->def_mac_addr[0].mac_addr[3] = (u8) (mac_addr >> 16);
4959                 sp->def_mac_addr[0].mac_addr[2] = (u8) (mac_addr >> 24);
4960                 sp->def_mac_addr[0].mac_addr[1] = (u8) (mac_addr >> 32);
4961                 sp->def_mac_addr[0].mac_addr[0] = (u8) (mac_addr >> 40);
4962         }
4963
4964         writeq(RMAC_ADDR_DATA0_MEM_ADDR(mac_addr),
4965                &bar0->rmac_addr_data0_mem);
4966
4967         val64 =
4968             RMAC_ADDR_CMD_MEM_WE | RMAC_ADDR_CMD_MEM_STROBE_NEW_CMD |
4969             RMAC_ADDR_CMD_MEM_OFFSET(0);
4970         writeq(val64, &bar0->rmac_addr_cmd_mem);
4971         /* Wait till command completes */
4972         if (wait_for_cmd_complete(&bar0->rmac_addr_cmd_mem,
4973                       RMAC_ADDR_CMD_MEM_STROBE_CMD_EXECUTING, S2IO_BIT_RESET)) {
4974                 DBG_PRINT(ERR_DBG, "%s: set_mac_addr failed\n", dev->name);
4975                 return FAILURE;
4976         }
4977
4978         return SUCCESS;
4979 }
4980
4981 /**
4982  * s2io_ethtool_sset - Sets different link parameters.
4983  * @sp : private member of the device structure, which is a pointer to the  * s2io_nic structure.
4984  * @info: pointer to the structure with parameters given by ethtool to set
4985  * link information.
4986  * Description:
4987  * The function sets different link parameters provided by the user onto
4988  * the NIC.
4989  * Return value:
4990  * 0 on success.
4991 */
4992
4993 static int s2io_ethtool_sset(struct net_device *dev,
4994                              struct ethtool_cmd *info)
4995 {
4996         struct s2io_nic *sp = dev->priv;
4997         if ((info->autoneg == AUTONEG_ENABLE) ||
4998             (info->speed != SPEED_10000) || (info->duplex != DUPLEX_FULL))
4999                 return -EINVAL;
5000         else {
5001                 s2io_close(sp->dev);
5002                 s2io_open(sp->dev);
5003         }
5004
5005         return 0;
5006 }
5007
5008 /**
5009  * s2io_ethtol_gset - Return link specific information.
5010  * @sp : private member of the device structure, pointer to the
5011  *      s2io_nic structure.
5012  * @info : pointer to the structure with parameters given by ethtool
5013  * to return link information.
5014  * Description:
5015  * Returns link specific information like speed, duplex etc.. to ethtool.
5016  * Return value :
5017  * return 0 on success.
5018  */
5019
5020 static int s2io_ethtool_gset(struct net_device *dev, struct ethtool_cmd *info)
5021 {
5022         struct s2io_nic *sp = dev->priv;
5023         info->supported = (SUPPORTED_10000baseT_Full | SUPPORTED_FIBRE);
5024         info->advertising = (SUPPORTED_10000baseT_Full | SUPPORTED_FIBRE);
5025         info->port = PORT_FIBRE;
5026         /* info->transceiver?? TODO */
5027
5028         if (netif_carrier_ok(sp->dev)) {
5029                 info->speed = 10000;
5030                 info->duplex = DUPLEX_FULL;
5031         } else {
5032                 info->speed = -1;
5033                 info->duplex = -1;
5034         }
5035
5036         info->autoneg = AUTONEG_DISABLE;
5037         return 0;
5038 }
5039
5040 /**
5041  * s2io_ethtool_gdrvinfo - Returns driver specific information.
5042  * @sp : private member of the device structure, which is a pointer to the
5043  * s2io_nic structure.
5044  * @info : pointer to the structure with parameters given by ethtool to
5045  * return driver information.
5046  * Description:
5047  * Returns driver specefic information like name, version etc.. to ethtool.
5048  * Return value:
5049  *  void
5050  */
5051
5052 static void s2io_ethtool_gdrvinfo(struct net_device *dev,
5053                                   struct ethtool_drvinfo *info)
5054 {
5055         struct s2io_nic *sp = dev->priv;
5056
5057         strncpy(info->driver, s2io_driver_name, sizeof(info->driver));
5058         strncpy(info->version, s2io_driver_version, sizeof(info->version));
5059         strncpy(info->fw_version, "", sizeof(info->fw_version));
5060         strncpy(info->bus_info, pci_name(sp->pdev), sizeof(info->bus_info));
5061         info->regdump_len = XENA_REG_SPACE;
5062         info->eedump_len = XENA_EEPROM_SPACE;
5063         info->testinfo_len = S2IO_TEST_LEN;
5064
5065         if (sp->device_type == XFRAME_I_DEVICE)
5066                 info->n_stats = XFRAME_I_STAT_LEN;
5067         else
5068                 info->n_stats = XFRAME_II_STAT_LEN;
5069 }
5070
5071 /**
5072  *  s2io_ethtool_gregs - dumps the entire space of Xfame into the buffer.
5073  *  @sp: private member of the device structure, which is a pointer to the
5074  *  s2io_nic structure.
5075  *  @regs : pointer to the structure with parameters given by ethtool for
5076  *  dumping the registers.
5077  *  @reg_space: The input argumnet into which all the registers are dumped.
5078  *  Description:
5079  *  Dumps the entire register space of xFrame NIC into the user given
5080  *  buffer area.
5081  * Return value :
5082  * void .
5083 */
5084
5085 static void s2io_ethtool_gregs(struct net_device *dev,
5086                                struct ethtool_regs *regs, void *space)
5087 {
5088         int i;
5089         u64 reg;
5090         u8 *reg_space = (u8 *) space;
5091         struct s2io_nic *sp = dev->priv;
5092
5093         regs->len = XENA_REG_SPACE;
5094         regs->version = sp->pdev->subsystem_device;
5095
5096         for (i = 0; i < regs->len; i += 8) {
5097                 reg = readq(sp->bar0 + i);
5098                 memcpy((reg_space + i), &reg, 8);
5099         }
5100 }
5101
5102 /**
5103  *  s2io_phy_id  - timer function that alternates adapter LED.
5104  *  @data : address of the private member of the device structure, which
5105  *  is a pointer to the s2io_nic structure, provided as an u32.
5106  * Description: This is actually the timer function that alternates the
5107  * adapter LED bit of the adapter control bit to set/reset every time on
5108  * invocation. The timer is set for 1/2 a second, hence tha NIC blinks
5109  *  once every second.
5110 */
5111 static void s2io_phy_id(unsigned long data)
5112 {
5113         struct s2io_nic *sp = (struct s2io_nic *) data;
5114         struct XENA_dev_config __iomem *bar0 = sp->bar0;
5115         u64 val64 = 0;
5116         u16 subid;
5117
5118         subid = sp->pdev->subsystem_device;
5119         if ((sp->device_type == XFRAME_II_DEVICE) ||
5120                    ((subid & 0xFF) >= 0x07)) {
5121                 val64 = readq(&bar0->gpio_control);
5122                 val64 ^= GPIO_CTRL_GPIO_0;
5123                 writeq(val64, &bar0->gpio_control);
5124         } else {
5125                 val64 = readq(&bar0->adapter_control);
5126                 val64 ^= ADAPTER_LED_ON;
5127                 writeq(val64, &bar0->adapter_control);
5128         }
5129
5130         mod_timer(&sp->id_timer, jiffies + HZ / 2);
5131 }
5132
5133 /**
5134  * s2io_ethtool_idnic - To physically identify the nic on the system.
5135  * @sp : private member of the device structure, which is a pointer to the
5136  * s2io_nic structure.
5137  * @id : pointer to the structure with identification parameters given by
5138  * ethtool.
5139  * Description: Used to physically identify the NIC on the system.
5140  * The Link LED will blink for a time specified by the user for
5141  * identification.
5142  * NOTE: The Link has to be Up to be able to blink the LED. Hence
5143  * identification is possible only if it's link is up.
5144  * Return value:
5145  * int , returns 0 on success
5146  */
5147
5148 static int s2io_ethtool_idnic(struct net_device *dev, u32 data)
5149 {
5150         u64 val64 = 0, last_gpio_ctrl_val;
5151         struct s2io_nic *sp = dev->priv;
5152         struct XENA_dev_config __iomem *bar0 = sp->bar0;
5153         u16 subid;
5154
5155         subid = sp->pdev->subsystem_device;
5156         last_gpio_ctrl_val = readq(&bar0->gpio_control);
5157         if ((sp->device_type == XFRAME_I_DEVICE) &&
5158                 ((subid & 0xFF) < 0x07)) {
5159                 val64 = readq(&bar0->adapter_control);
5160                 if (!(val64 & ADAPTER_CNTL_EN)) {
5161                         printk(KERN_ERR
5162                                "Adapter Link down, cannot blink LED\n");
5163                         return -EFAULT;
5164                 }
5165         }
5166         if (sp->id_timer.function == NULL) {
5167                 init_timer(&sp->id_timer);
5168                 sp->id_timer.function = s2io_phy_id;
5169                 sp->id_timer.data = (unsigned long) sp;
5170         }
5171         mod_timer(&sp->id_timer, jiffies);
5172         if (data)
5173                 msleep_interruptible(data * HZ);
5174         else
5175                 msleep_interruptible(MAX_FLICKER_TIME);
5176         del_timer_sync(&sp->id_timer);
5177
5178         if (CARDS_WITH_FAULTY_LINK_INDICATORS(sp->device_type, subid)) {
5179                 writeq(last_gpio_ctrl_val, &bar0->gpio_control);
5180                 last_gpio_ctrl_val = readq(&bar0->gpio_control);
5181         }
5182
5183         return 0;
5184 }
5185
5186 static void s2io_ethtool_gringparam(struct net_device *dev,
5187                                     struct ethtool_ringparam *ering)
5188 {
5189         struct s2io_nic *sp = dev->priv;
5190         int i,tx_desc_count=0,rx_desc_count=0;
5191
5192         if (sp->rxd_mode == RXD_MODE_1)
5193                 ering->rx_max_pending = MAX_RX_DESC_1;
5194         else if (sp->rxd_mode == RXD_MODE_3B)
5195                 ering->rx_max_pending = MAX_RX_DESC_2;
5196
5197         ering->tx_max_pending = MAX_TX_DESC;
5198         for (i = 0 ; i < sp->config.tx_fifo_num ; i++)
5199                 tx_desc_count += sp->config.tx_cfg[i].fifo_len;
5200
5201         DBG_PRINT(INFO_DBG,"\nmax txds : %d\n",sp->config.max_txds);
5202         ering->tx_pending = tx_desc_count;
5203         rx_desc_count = 0;
5204         for (i = 0 ; i < sp->config.rx_ring_num ; i++)
5205                 rx_desc_count += sp->config.rx_cfg[i].num_rxd;
5206
5207         ering->rx_pending = rx_desc_count;
5208
5209         ering->rx_mini_max_pending = 0;
5210         ering->rx_mini_pending = 0;
5211         if(sp->rxd_mode == RXD_MODE_1)
5212                 ering->rx_jumbo_max_pending = MAX_RX_DESC_1;
5213         else if (sp->rxd_mode == RXD_MODE_3B)
5214                 ering->rx_jumbo_max_pending = MAX_RX_DESC_2;
5215         ering->rx_jumbo_pending = rx_desc_count;
5216 }
5217
5218 /**
5219  * s2io_ethtool_getpause_data -Pause frame frame generation and reception.
5220  * @sp : private member of the device structure, which is a pointer to the
5221  *      s2io_nic structure.
5222  * @ep : pointer to the structure with pause parameters given by ethtool.
5223  * Description:
5224  * Returns the Pause frame generation and reception capability of the NIC.
5225  * Return value:
5226  *  void
5227  */
5228 static void s2io_ethtool_getpause_data(struct net_device *dev,
5229                                        struct ethtool_pauseparam *ep)
5230 {
5231         u64 val64;
5232         struct s2io_nic *sp = dev->priv;
5233         struct XENA_dev_config __iomem *bar0 = sp->bar0;
5234
5235         val64 = readq(&bar0->rmac_pause_cfg);
5236         if (val64 & RMAC_PAUSE_GEN_ENABLE)
5237                 ep->tx_pause = TRUE;
5238         if (val64 & RMAC_PAUSE_RX_ENABLE)
5239                 ep->rx_pause = TRUE;
5240         ep->autoneg = FALSE;
5241 }
5242
5243 /**
5244  * s2io_ethtool_setpause_data -  set/reset pause frame generation.
5245  * @sp : private member of the device structure, which is a pointer to the
5246  *      s2io_nic structure.
5247  * @ep : pointer to the structure with pause parameters given by ethtool.
5248  * Description:
5249  * It can be used to set or reset Pause frame generation or reception
5250  * support of the NIC.
5251  * Return value:
5252  * int, returns 0 on Success
5253  */
5254
5255 static int s2io_ethtool_setpause_data(struct net_device *dev,
5256                                struct ethtool_pauseparam *ep)
5257 {
5258         u64 val64;
5259         struct s2io_nic *sp = dev->priv;
5260         struct XENA_dev_config __iomem *bar0 = sp->bar0;
5261
5262         val64 = readq(&bar0->rmac_pause_cfg);
5263         if (ep->tx_pause)
5264                 val64 |= RMAC_PAUSE_GEN_ENABLE;
5265         else
5266                 val64 &= ~RMAC_PAUSE_GEN_ENABLE;
5267         if (ep->rx_pause)
5268                 val64 |= RMAC_PAUSE_RX_ENABLE;
5269         else
5270                 val64 &= ~RMAC_PAUSE_RX_ENABLE;
5271         writeq(val64, &bar0->rmac_pause_cfg);
5272         return 0;
5273 }
5274
5275 /**
5276  * read_eeprom - reads 4 bytes of data from user given offset.
5277  * @sp : private member of the device structure, which is a pointer to the
5278  *      s2io_nic structure.
5279  * @off : offset at which the data must be written
5280  * @data : Its an output parameter where the data read at the given
5281  *      offset is stored.
5282  * Description:
5283  * Will read 4 bytes of data from the user given offset and return the
5284  * read data.
5285  * NOTE: Will allow to read only part of the EEPROM visible through the
5286  *   I2C bus.
5287  * Return value:
5288  *  -1 on failure and 0 on success.
5289  */
5290
5291 #define S2IO_DEV_ID             5
5292 static int read_eeprom(struct s2io_nic * sp, int off, u64 * data)
5293 {
5294         int ret = -1;
5295         u32 exit_cnt = 0;
5296         u64 val64;
5297         struct XENA_dev_config __iomem *bar0 = sp->bar0;
5298
5299         if (sp->device_type == XFRAME_I_DEVICE) {
5300                 val64 = I2C_CONTROL_DEV_ID(S2IO_DEV_ID) | I2C_CONTROL_ADDR(off) |
5301                     I2C_CONTROL_BYTE_CNT(0x3) | I2C_CONTROL_READ |
5302                     I2C_CONTROL_CNTL_START;
5303                 SPECIAL_REG_WRITE(val64, &bar0->i2c_control, LF);
5304
5305                 while (exit_cnt < 5) {
5306                         val64 = readq(&bar0->i2c_control);
5307                         if (I2C_CONTROL_CNTL_END(val64)) {
5308                                 *data = I2C_CONTROL_GET_DATA(val64);
5309                                 ret = 0;
5310                                 break;
5311                         }
5312                         msleep(50);
5313                         exit_cnt++;
5314                 }
5315         }
5316
5317         if (sp->device_type == XFRAME_II_DEVICE) {
5318                 val64 = SPI_CONTROL_KEY(0x9) | SPI_CONTROL_SEL1 |
5319                         SPI_CONTROL_BYTECNT(0x3) |
5320                         SPI_CONTROL_CMD(0x3) | SPI_CONTROL_ADDR(off);
5321                 SPECIAL_REG_WRITE(val64, &bar0->spi_control, LF);
5322                 val64 |= SPI_CONTROL_REQ;
5323                 SPECIAL_REG_WRITE(val64, &bar0->spi_control, LF);
5324                 while (exit_cnt < 5) {
5325                         val64 = readq(&bar0->spi_control);
5326                         if (val64 & SPI_CONTROL_NACK) {
5327                                 ret = 1;
5328                                 break;
5329                         } else if (val64 & SPI_CONTROL_DONE) {
5330                                 *data = readq(&bar0->spi_data);
5331                                 *data &= 0xffffff;
5332                                 ret = 0;
5333                                 break;
5334                         }
5335                         msleep(50);
5336                         exit_cnt++;
5337                 }
5338         }
5339         return ret;
5340 }
5341
5342 /**
5343  *  write_eeprom - actually writes the relevant part of the data value.
5344  *  @sp : private member of the device structure, which is a pointer to the
5345  *       s2io_nic structure.
5346  *  @off : offset at which the data must be written
5347  *  @data : The data that is to be written
5348  *  @cnt : Number of bytes of the data that are actually to be written into
5349  *  the Eeprom. (max of 3)
5350  * Description:
5351  *  Actually writes the relevant part of the data value into the Eeprom
5352  *  through the I2C bus.
5353  * Return value:
5354  *  0 on success, -1 on failure.
5355  */
5356
5357 static int write_eeprom(struct s2io_nic * sp, int off, u64 data, int cnt)
5358 {
5359         int exit_cnt = 0, ret = -1;
5360         u64 val64;
5361         struct XENA_dev_config __iomem *bar0 = sp->bar0;
5362
5363         if (sp->device_type == XFRAME_I_DEVICE) {
5364                 val64 = I2C_CONTROL_DEV_ID(S2IO_DEV_ID) | I2C_CONTROL_ADDR(off) |
5365                     I2C_CONTROL_BYTE_CNT(cnt) | I2C_CONTROL_SET_DATA((u32)data) |
5366                     I2C_CONTROL_CNTL_START;
5367                 SPECIAL_REG_WRITE(val64, &bar0->i2c_control, LF);
5368
5369                 while (exit_cnt < 5) {
5370                         val64 = readq(&bar0->i2c_control);
5371                         if (I2C_CONTROL_CNTL_END(val64)) {
5372                                 if (!(val64 & I2C_CONTROL_NACK))
5373                                         ret = 0;
5374                                 break;
5375                         }
5376                         msleep(50);
5377                         exit_cnt++;
5378                 }
5379         }
5380
5381         if (sp->device_type == XFRAME_II_DEVICE) {
5382                 int write_cnt = (cnt == 8) ? 0 : cnt;
5383                 writeq(SPI_DATA_WRITE(data,(cnt<<3)), &bar0->spi_data);
5384
5385                 val64 = SPI_CONTROL_KEY(0x9) | SPI_CONTROL_SEL1 |
5386                         SPI_CONTROL_BYTECNT(write_cnt) |
5387                         SPI_CONTROL_CMD(0x2) | SPI_CONTROL_ADDR(off);
5388                 SPECIAL_REG_WRITE(val64, &bar0->spi_control, LF);
5389                 val64 |= SPI_CONTROL_REQ;
5390                 SPECIAL_REG_WRITE(val64, &bar0->spi_control, LF);
5391                 while (exit_cnt < 5) {
5392                         val64 = readq(&bar0->spi_control);
5393                         if (val64 & SPI_CONTROL_NACK) {
5394                                 ret = 1;
5395                                 break;
5396                         } else if (val64 & SPI_CONTROL_DONE) {
5397                                 ret = 0;
5398                                 break;
5399                         }
5400                         msleep(50);
5401                         exit_cnt++;
5402                 }
5403         }
5404         return ret;
5405 }
5406 static void s2io_vpd_read(struct s2io_nic *nic)
5407 {
5408         u8 *vpd_data;
5409         u8 data;
5410         int i=0, cnt, fail = 0;
5411         int vpd_addr = 0x80;
5412
5413         if (nic->device_type == XFRAME_II_DEVICE) {
5414                 strcpy(nic->product_name, "Xframe II 10GbE network adapter");
5415                 vpd_addr = 0x80;
5416         }
5417         else {
5418                 strcpy(nic->product_name, "Xframe I 10GbE network adapter");
5419                 vpd_addr = 0x50;
5420         }
5421         strcpy(nic->serial_num, "NOT AVAILABLE");
5422
5423         vpd_data = kmalloc(256, GFP_KERNEL);
5424         if (!vpd_data) {
5425                 nic->mac_control.stats_info->sw_stat.mem_alloc_fail_cnt++;
5426                 return;
5427         }
5428         nic->mac_control.stats_info->sw_stat.mem_allocated += 256;
5429
5430         for (i = 0; i < 256; i +=4 ) {
5431                 pci_write_config_byte(nic->pdev, (vpd_addr + 2), i);
5432                 pci_read_config_byte(nic->pdev,  (vpd_addr + 2), &data);
5433                 pci_write_config_byte(nic->pdev, (vpd_addr + 3), 0);
5434                 for (cnt = 0; cnt <5; cnt++) {
5435                         msleep(2);
5436                         pci_read_config_byte(nic->pdev, (vpd_addr + 3), &data);
5437                         if (data == 0x80)
5438                                 break;
5439                 }
5440                 if (cnt >= 5) {
5441                         DBG_PRINT(ERR_DBG, "Read of VPD data failed\n");
5442                         fail = 1;
5443                         break;
5444                 }
5445                 pci_read_config_dword(nic->pdev,  (vpd_addr + 4),
5446                                       (u32 *)&vpd_data[i]);
5447         }
5448
5449         if(!fail) {
5450                 /* read serial number of adapter */
5451                 for (cnt = 0; cnt < 256; cnt++) {
5452                 if ((vpd_data[cnt] == 'S') &&
5453                         (vpd_data[cnt+1] == 'N') &&
5454                         (vpd_data[cnt+2] < VPD_STRING_LEN)) {
5455                                 memset(nic->serial_num, 0, VPD_STRING_LEN);
5456                                 memcpy(nic->serial_num, &vpd_data[cnt + 3],
5457                                         vpd_data[cnt+2]);
5458                                 break;
5459                         }
5460                 }
5461         }
5462
5463         if ((!fail) && (vpd_data[1] < VPD_STRING_LEN)) {
5464                 memset(nic->product_name, 0, vpd_data[1]);
5465                 memcpy(nic->product_name, &vpd_data[3], vpd_data[1]);
5466         }
5467         kfree(vpd_data);
5468         nic->mac_control.stats_info->sw_stat.mem_freed += 256;
5469 }
5470
5471 /**
5472  *  s2io_ethtool_geeprom  - reads the value stored in the Eeprom.
5473  *  @sp : private member of the device structure, which is a pointer to the *       s2io_nic structure.
5474  *  @eeprom : pointer to the user level structure provided by ethtool,
5475  *  containing all relevant information.
5476  *  @data_buf : user defined value to be written into Eeprom.
5477  *  Description: Reads the values stored in the Eeprom at given offset
5478  *  for a given length. Stores these values int the input argument data
5479  *  buffer 'data_buf' and returns these to the caller (ethtool.)
5480  *  Return value:
5481  *  int  0 on success
5482  */
5483
5484 static int s2io_ethtool_geeprom(struct net_device *dev,
5485                          struct ethtool_eeprom *eeprom, u8 * data_buf)
5486 {
5487         u32 i, valid;
5488         u64 data;
5489         struct s2io_nic *sp = dev->priv;
5490
5491         eeprom->magic = sp->pdev->vendor | (sp->pdev->device << 16);
5492
5493         if ((eeprom->offset + eeprom->len) > (XENA_EEPROM_SPACE))
5494                 eeprom->len = XENA_EEPROM_SPACE - eeprom->offset;
5495
5496         for (i = 0; i < eeprom->len; i += 4) {
5497                 if (read_eeprom(sp, (eeprom->offset + i), &data)) {
5498                         DBG_PRINT(ERR_DBG, "Read of EEPROM failed\n");
5499                         return -EFAULT;
5500                 }
5501                 valid = INV(data);
5502                 memcpy((data_buf + i), &valid, 4);
5503         }
5504         return 0;
5505 }
5506
5507 /**
5508  *  s2io_ethtool_seeprom - tries to write the user provided value in Eeprom
5509  *  @sp : private member of the device structure, which is a pointer to the
5510  *  s2io_nic structure.
5511  *  @eeprom : pointer to the user level structure provided by ethtool,
5512  *  containing all relevant information.
5513  *  @data_buf ; user defined value to be written into Eeprom.
5514  *  Description:
5515  *  Tries to write the user provided value in the Eeprom, at the offset
5516  *  given by the user.
5517  *  Return value:
5518  *  0 on success, -EFAULT on failure.
5519  */
5520
5521 static int s2io_ethtool_seeprom(struct net_device *dev,
5522                                 struct ethtool_eeprom *eeprom,
5523                                 u8 * data_buf)
5524 {
5525         int len = eeprom->len, cnt = 0;
5526         u64 valid = 0, data;
5527         struct s2io_nic *sp = dev->priv;
5528
5529         if (eeprom->magic != (sp->pdev->vendor | (sp->pdev->device << 16))) {
5530                 DBG_PRINT(ERR_DBG,
5531                           "ETHTOOL_WRITE_EEPROM Err: Magic value ");
5532                 DBG_PRINT(ERR_DBG, "is wrong, Its not 0x%x\n",
5533                           eeprom->magic);
5534                 return -EFAULT;
5535         }
5536
5537         while (len) {
5538                 data = (u32) data_buf[cnt] & 0x000000FF;
5539                 if (data) {
5540                         valid = (u32) (data << 24);
5541                 } else
5542                         valid = data;
5543
5544                 if (write_eeprom(sp, (eeprom->offset + cnt), valid, 0)) {
5545                         DBG_PRINT(ERR_DBG,
5546                                   "ETHTOOL_WRITE_EEPROM Err: Cannot ");
5547                         DBG_PRINT(ERR_DBG,
5548                                   "write into the specified offset\n");
5549                         return -EFAULT;
5550                 }
5551                 cnt++;
5552                 len--;
5553         }
5554
5555         return 0;
5556 }
5557
5558 /**
5559  * s2io_register_test - reads and writes into all clock domains.
5560  * @sp : private member of the device structure, which is a pointer to the
5561  * s2io_nic structure.
5562  * @data : variable that returns the result of each of the test conducted b
5563  * by the driver.
5564  * Description:
5565  * Read and write into all clock domains. The NIC has 3 clock domains,
5566  * see that registers in all the three regions are accessible.
5567  * Return value:
5568  * 0 on success.
5569  */
5570
5571 static int s2io_register_test(struct s2io_nic * sp, uint64_t * data)
5572 {
5573         struct XENA_dev_config __iomem *bar0 = sp->bar0;
5574         u64 val64 = 0, exp_val;
5575         int fail = 0;
5576
5577         val64 = readq(&bar0->pif_rd_swapper_fb);
5578         if (val64 != 0x123456789abcdefULL) {
5579                 fail = 1;
5580                 DBG_PRINT(INFO_DBG, "Read Test level 1 fails\n");
5581         }
5582
5583         val64 = readq(&bar0->rmac_pause_cfg);
5584         if (val64 != 0xc000ffff00000000ULL) {
5585                 fail = 1;
5586                 DBG_PRINT(INFO_DBG, "Read Test level 2 fails\n");
5587         }
5588
5589         val64 = readq(&bar0->rx_queue_cfg);
5590         if (sp->device_type == XFRAME_II_DEVICE)
5591                 exp_val = 0x0404040404040404ULL;
5592         else
5593                 exp_val = 0x0808080808080808ULL;
5594         if (val64 != exp_val) {
5595                 fail = 1;
5596                 DBG_PRINT(INFO_DBG, "Read Test level 3 fails\n");
5597         }
5598
5599         val64 = readq(&bar0->xgxs_efifo_cfg);
5600         if (val64 != 0x000000001923141EULL) {
5601                 fail = 1;
5602                 DBG_PRINT(INFO_DBG, "Read Test level 4 fails\n");
5603         }
5604
5605         val64 = 0x5A5A5A5A5A5A5A5AULL;
5606         writeq(val64, &bar0->xmsi_data);
5607         val64 = readq(&bar0->xmsi_data);
5608         if (val64 != 0x5A5A5A5A5A5A5A5AULL) {
5609                 fail = 1;
5610                 DBG_PRINT(ERR_DBG, "Write Test level 1 fails\n");
5611         }
5612
5613         val64 = 0xA5A5A5A5A5A5A5A5ULL;
5614         writeq(val64, &bar0->xmsi_data);
5615         val64 = readq(&bar0->xmsi_data);
5616         if (val64 != 0xA5A5A5A5A5A5A5A5ULL) {
5617                 fail = 1;
5618                 DBG_PRINT(ERR_DBG, "Write Test level 2 fails\n");
5619         }
5620
5621         *data = fail;
5622         return fail;
5623 }
5624
5625 /**
5626  * s2io_eeprom_test - to verify that EEprom in the xena can be programmed.
5627  * @sp : private member of the device structure, which is a pointer to the
5628  * s2io_nic structure.
5629  * @data:variable that returns the result of each of the test conducted by
5630  * the driver.
5631  * Description:
5632  * Verify that EEPROM in the xena can be programmed using I2C_CONTROL
5633  * register.
5634  * Return value:
5635  * 0 on success.
5636  */
5637
5638 static int s2io_eeprom_test(struct s2io_nic * sp, uint64_t * data)
5639 {
5640         int fail = 0;
5641         u64 ret_data, org_4F0, org_7F0;
5642         u8 saved_4F0 = 0, saved_7F0 = 0;
5643         struct net_device *dev = sp->dev;
5644
5645         /* Test Write Error at offset 0 */
5646         /* Note that SPI interface allows write access to all areas
5647          * of EEPROM. Hence doing all negative testing only for Xframe I.
5648          */
5649         if (sp->device_type == XFRAME_I_DEVICE)
5650                 if (!write_eeprom(sp, 0, 0, 3))
5651                         fail = 1;
5652
5653         /* Save current values at offsets 0x4F0 and 0x7F0 */
5654         if (!read_eeprom(sp, 0x4F0, &org_4F0))
5655                 saved_4F0 = 1;
5656         if (!read_eeprom(sp, 0x7F0, &org_7F0))
5657                 saved_7F0 = 1;
5658
5659         /* Test Write at offset 4f0 */
5660         if (write_eeprom(sp, 0x4F0, 0x012345, 3))
5661                 fail = 1;
5662         if (read_eeprom(sp, 0x4F0, &ret_data))
5663                 fail = 1;
5664
5665         if (ret_data != 0x012345) {
5666                 DBG_PRINT(ERR_DBG, "%s: eeprom test error at offset 0x4F0. "
5667                         "Data written %llx Data read %llx\n",
5668                         dev->name, (unsigned long long)0x12345,
5669                         (unsigned long long)ret_data);
5670                 fail = 1;
5671         }
5672
5673         /* Reset the EEPROM data go FFFF */
5674         write_eeprom(sp, 0x4F0, 0xFFFFFF, 3);
5675
5676         /* Test Write Request Error at offset 0x7c */
5677         if (sp->device_type == XFRAME_I_DEVICE)
5678                 if (!write_eeprom(sp, 0x07C, 0, 3))
5679                         fail = 1;
5680
5681         /* Test Write Request at offset 0x7f0 */
5682         if (write_eeprom(sp, 0x7F0, 0x012345, 3))
5683                 fail = 1;
5684         if (read_eeprom(sp, 0x7F0, &ret_data))
5685                 fail = 1;
5686
5687         if (ret_data != 0x012345) {
5688                 DBG_PRINT(ERR_DBG, "%s: eeprom test error at offset 0x7F0. "
5689                         "Data written %llx Data read %llx\n",
5690                         dev->name, (unsigned long long)0x12345,
5691                         (unsigned long long)ret_data);
5692                 fail = 1;
5693         }
5694
5695         /* Reset the EEPROM data go FFFF */
5696         write_eeprom(sp, 0x7F0, 0xFFFFFF, 3);
5697
5698         if (sp->device_type == XFRAME_I_DEVICE) {
5699                 /* Test Write Error at offset 0x80 */
5700                 if (!write_eeprom(sp, 0x080, 0, 3))
5701                         fail = 1;
5702
5703                 /* Test Write Error at offset 0xfc */
5704                 if (!write_eeprom(sp, 0x0FC, 0, 3))
5705                         fail = 1;
5706
5707                 /* Test Write Error at offset 0x100 */
5708                 if (!write_eeprom(sp, 0x100, 0, 3))
5709                         fail = 1;
5710
5711                 /* Test Write Error at offset 4ec */
5712                 if (!write_eeprom(sp, 0x4EC, 0, 3))
5713                         fail = 1;
5714         }
5715
5716         /* Restore values at offsets 0x4F0 and 0x7F0 */
5717         if (saved_4F0)
5718                 write_eeprom(sp, 0x4F0, org_4F0, 3);
5719         if (saved_7F0)
5720                 write_eeprom(sp, 0x7F0, org_7F0, 3);
5721
5722         *data = fail;
5723         return fail;
5724 }
5725
5726 /**
5727  * s2io_bist_test - invokes the MemBist test of the card .
5728  * @sp : private member of the device structure, which is a pointer to the
5729  * s2io_nic structure.
5730  * @data:variable that returns the result of each of the test conducted by
5731  * the driver.
5732  * Description:
5733  * This invokes the MemBist test of the card. We give around
5734  * 2 secs time for the Test to complete. If it's still not complete
5735  * within this peiod, we consider that the test failed.
5736  * Return value:
5737  * 0 on success and -1 on failure.
5738  */
5739
5740 static int s2io_bist_test(struct s2io_nic * sp, uint64_t * data)
5741 {
5742         u8 bist = 0;
5743         int cnt = 0, ret = -1;
5744
5745         pci_read_config_byte(sp->pdev, PCI_BIST, &bist);
5746         bist |= PCI_BIST_START;
5747         pci_write_config_word(sp->pdev, PCI_BIST, bist);
5748
5749         while (cnt < 20) {
5750                 pci_read_config_byte(sp->pdev, PCI_BIST, &bist);
5751                 if (!(bist & PCI_BIST_START)) {
5752                         *data = (bist & PCI_BIST_CODE_MASK);
5753                         ret = 0;
5754                         break;
5755                 }
5756                 msleep(100);
5757                 cnt++;
5758         }
5759
5760         return ret;
5761 }
5762
5763 /**
5764  * s2io-link_test - verifies the link state of the nic
5765  * @sp ; private member of the device structure, which is a pointer to the
5766  * s2io_nic structure.
5767  * @data: variable that returns the result of each of the test conducted by
5768  * the driver.
5769  * Description:
5770  * The function verifies the link state of the NIC and updates the input
5771  * argument 'data' appropriately.
5772  * Return value:
5773  * 0 on success.
5774  */
5775
5776 static int s2io_link_test(struct s2io_nic * sp, uint64_t * data)
5777 {
5778         struct XENA_dev_config __iomem *bar0 = sp->bar0;
5779         u64 val64;
5780
5781         val64 = readq(&bar0->adapter_status);
5782         if(!(LINK_IS_UP(val64)))
5783                 *data = 1;
5784         else
5785                 *data = 0;
5786
5787         return *data;
5788 }
5789
5790 /**
5791  * s2io_rldram_test - offline test for access to the RldRam chip on the NIC
5792  * @sp - private member of the device structure, which is a pointer to the
5793  * s2io_nic structure.
5794  * @data - variable that returns the result of each of the test
5795  * conducted by the driver.
5796  * Description:
5797  *  This is one of the offline test that tests the read and write
5798  *  access to the RldRam chip on the NIC.
5799  * Return value:
5800  *  0 on success.
5801  */
5802
5803 static int s2io_rldram_test(struct s2io_nic * sp, uint64_t * data)
5804 {
5805         struct XENA_dev_config __iomem *bar0 = sp->bar0;
5806         u64 val64;
5807         int cnt, iteration = 0, test_fail = 0;
5808
5809         val64 = readq(&bar0->adapter_control);
5810         val64 &= ~ADAPTER_ECC_EN;
5811         writeq(val64, &bar0->adapter_control);
5812
5813         val64 = readq(&bar0->mc_rldram_test_ctrl);
5814         val64 |= MC_RLDRAM_TEST_MODE;
5815         SPECIAL_REG_WRITE(val64, &bar0->mc_rldram_test_ctrl, LF);
5816
5817         val64 = readq(&bar0->mc_rldram_mrs);
5818         val64 |= MC_RLDRAM_QUEUE_SIZE_ENABLE;
5819         SPECIAL_REG_WRITE(val64, &bar0->mc_rldram_mrs, UF);
5820
5821         val64 |= MC_RLDRAM_MRS_ENABLE;
5822         SPECIAL_REG_WRITE(val64, &bar0->mc_rldram_mrs, UF);
5823
5824         while (iteration < 2) {
5825                 val64 = 0x55555555aaaa0000ULL;
5826                 if (iteration == 1) {
5827                         val64 ^= 0xFFFFFFFFFFFF0000ULL;
5828                 }
5829                 writeq(val64, &bar0->mc_rldram_test_d0);
5830
5831                 val64 = 0xaaaa5a5555550000ULL;
5832                 if (iteration == 1) {
5833                         val64 ^= 0xFFFFFFFFFFFF0000ULL;
5834                 }
5835                 writeq(val64, &bar0->mc_rldram_test_d1);
5836
5837                 val64 = 0x55aaaaaaaa5a0000ULL;
5838                 if (iteration == 1) {
5839                         val64 ^= 0xFFFFFFFFFFFF0000ULL;
5840                 }
5841                 writeq(val64, &bar0->mc_rldram_test_d2);
5842
5843                 val64 = (u64) (0x0000003ffffe0100ULL);
5844                 writeq(val64, &bar0->mc_rldram_test_add);
5845
5846                 val64 = MC_RLDRAM_TEST_MODE | MC_RLDRAM_TEST_WRITE |
5847                         MC_RLDRAM_TEST_GO;
5848                 SPECIAL_REG_WRITE(val64, &bar0->mc_rldram_test_ctrl, LF);
5849
5850                 for (cnt = 0; cnt < 5; cnt++) {
5851                         val64 = readq(&bar0->mc_rldram_test_ctrl);
5852                         if (val64 & MC_RLDRAM_TEST_DONE)
5853                                 break;
5854                         msleep(200);
5855                 }
5856
5857                 if (cnt == 5)
5858                         break;
5859
5860                 val64 = MC_RLDRAM_TEST_MODE | MC_RLDRAM_TEST_GO;
5861                 SPECIAL_REG_WRITE(val64, &bar0->mc_rldram_test_ctrl, LF);
5862
5863                 for (cnt = 0; cnt < 5; cnt++) {
5864                         val64 = readq(&bar0->mc_rldram_test_ctrl);
5865                         if (val64 & MC_RLDRAM_TEST_DONE)
5866                                 break;
5867                         msleep(500);
5868                 }
5869
5870                 if (cnt == 5)
5871                         break;
5872
5873                 val64 = readq(&bar0->mc_rldram_test_ctrl);
5874                 if (!(val64 & MC_RLDRAM_TEST_PASS))
5875                         test_fail = 1;
5876
5877                 iteration++;
5878         }
5879
5880         *data = test_fail;
5881
5882         /* Bring the adapter out of test mode */
5883         SPECIAL_REG_WRITE(0, &bar0->mc_rldram_test_ctrl, LF);
5884
5885         return test_fail;
5886 }
5887
5888 /**
5889  *  s2io_ethtool_test - conducts 6 tsets to determine the health of card.
5890  *  @sp : private member of the device structure, which is a pointer to the
5891  *  s2io_nic structure.
5892  *  @ethtest : pointer to a ethtool command specific structure that will be
5893  *  returned to the user.
5894  *  @data : variable that returns the result of each of the test
5895  * conducted by the driver.
5896  * Description:
5897  *  This function conducts 6 tests ( 4 offline and 2 online) to determine
5898  *  the health of the card.
5899  * Return value:
5900  *  void
5901  */
5902
5903 static void s2io_ethtool_test(struct net_device *dev,
5904                               struct ethtool_test *ethtest,
5905                               uint64_t * data)
5906 {
5907         struct s2io_nic *sp = dev->priv;
5908         int orig_state = netif_running(sp->dev);
5909
5910         if (ethtest->flags == ETH_TEST_FL_OFFLINE) {
5911                 /* Offline Tests. */
5912                 if (orig_state)
5913                         s2io_close(sp->dev);
5914
5915                 if (s2io_register_test(sp, &data[0]))
5916                         ethtest->flags |= ETH_TEST_FL_FAILED;
5917
5918                 s2io_reset(sp);
5919
5920                 if (s2io_rldram_test(sp, &data[3]))
5921                         ethtest->flags |= ETH_TEST_FL_FAILED;
5922
5923                 s2io_reset(sp);
5924
5925                 if (s2io_eeprom_test(sp, &data[1]))
5926                         ethtest->flags |= ETH_TEST_FL_FAILED;
5927
5928                 if (s2io_bist_test(sp, &data[4]))
5929                         ethtest->flags |= ETH_TEST_FL_FAILED;
5930
5931                 if (orig_state)
5932                         s2io_open(sp->dev);
5933
5934                 data[2] = 0;
5935         } else {
5936                 /* Online Tests. */
5937                 if (!orig_state) {
5938                         DBG_PRINT(ERR_DBG,
5939                                   "%s: is not up, cannot run test\n",
5940                                   dev->name);
5941                         data[0] = -1;
5942                         data[1] = -1;
5943                         data[2] = -1;
5944                         data[3] = -1;
5945                         data[4] = -1;
5946                 }
5947
5948                 if (s2io_link_test(sp, &data[2]))
5949                         ethtest->flags |= ETH_TEST_FL_FAILED;
5950
5951                 data[0] = 0;
5952                 data[1] = 0;
5953                 data[3] = 0;
5954                 data[4] = 0;
5955         }
5956 }
5957
5958 static void s2io_get_ethtool_stats(struct net_device *dev,
5959                                    struct ethtool_stats *estats,
5960                                    u64 * tmp_stats)
5961 {
5962         int i = 0, k;
5963         struct s2io_nic *sp = dev->priv;
5964         struct stat_block *stat_info = sp->mac_control.stats_info;
5965
5966         s2io_updt_stats(sp);
5967         tmp_stats[i++] =
5968                 (u64)le32_to_cpu(stat_info->tmac_frms_oflow) << 32  |
5969                 le32_to_cpu(stat_info->tmac_frms);
5970         tmp_stats[i++] =
5971                 (u64)le32_to_cpu(stat_info->tmac_data_octets_oflow) << 32 |
5972                 le32_to_cpu(stat_info->tmac_data_octets);
5973         tmp_stats[i++] = le64_to_cpu(stat_info->tmac_drop_frms);
5974         tmp_stats[i++] =
5975                 (u64)le32_to_cpu(stat_info->tmac_mcst_frms_oflow) << 32 |
5976                 le32_to_cpu(stat_info->tmac_mcst_frms);
5977         tmp_stats[i++] =
5978                 (u64)le32_to_cpu(stat_info->tmac_bcst_frms_oflow) << 32 |
5979                 le32_to_cpu(stat_info->tmac_bcst_frms);
5980         tmp_stats[i++] = le64_to_cpu(stat_info->tmac_pause_ctrl_frms);
5981         tmp_stats[i++] =
5982                 (u64)le32_to_cpu(stat_info->tmac_ttl_octets_oflow) << 32 |
5983                 le32_to_cpu(stat_info->tmac_ttl_octets);
5984         tmp_stats[i++] =
5985                 (u64)le32_to_cpu(stat_info->tmac_ucst_frms_oflow) << 32 |
5986                 le32_to_cpu(stat_info->tmac_ucst_frms);
5987         tmp_stats[i++] =
5988                 (u64)le32_to_cpu(stat_info->tmac_nucst_frms_oflow) << 32 |
5989                 le32_to_cpu(stat_info->tmac_nucst_frms);
5990         tmp_stats[i++] =
5991                 (u64)le32_to_cpu(stat_info->tmac_any_err_frms_oflow) << 32 |
5992                 le32_to_cpu(stat_info->tmac_any_err_frms);
5993         tmp_stats[i++] = le64_to_cpu(stat_info->tmac_ttl_less_fb_octets);
5994         tmp_stats[i++] = le64_to_cpu(stat_info->tmac_vld_ip_octets);
5995         tmp_stats[i++] =
5996                 (u64)le32_to_cpu(stat_info->tmac_vld_ip_oflow) << 32 |
5997                 le32_to_cpu(stat_info->tmac_vld_ip);
5998         tmp_stats[i++] =
5999                 (u64)le32_to_cpu(stat_info->tmac_drop_ip_oflow) << 32 |
6000                 le32_to_cpu(stat_info->tmac_drop_ip);
6001         tmp_stats[i++] =
6002                 (u64)le32_to_cpu(stat_info->tmac_icmp_oflow) << 32 |
6003                 le32_to_cpu(stat_info->tmac_icmp);
6004         tmp_stats[i++] =
6005                 (u64)le32_to_cpu(stat_info->tmac_rst_tcp_oflow) << 32 |
6006                 le32_to_cpu(stat_info->tmac_rst_tcp);
6007         tmp_stats[i++] = le64_to_cpu(stat_info->tmac_tcp);
6008         tmp_stats[i++] = (u64)le32_to_cpu(stat_info->tmac_udp_oflow) << 32 |
6009                 le32_to_cpu(stat_info->tmac_udp);
6010         tmp_stats[i++] =
6011                 (u64)le32_to_cpu(stat_info->rmac_vld_frms_oflow) << 32 |
6012                 le32_to_cpu(stat_info->rmac_vld_frms);
6013         tmp_stats[i++] =
6014                 (u64)le32_to_cpu(stat_info->rmac_data_octets_oflow) << 32 |
6015                 le32_to_cpu(stat_info->rmac_data_octets);
6016         tmp_stats[i++] = le64_to_cpu(stat_info->rmac_fcs_err_frms);
6017         tmp_stats[i++] = le64_to_cpu(stat_info->rmac_drop_frms);
6018         tmp_stats[i++] =
6019                 (u64)le32_to_cpu(stat_info->rmac_vld_mcst_frms_oflow) << 32 |
6020                 le32_to_cpu(stat_info->rmac_vld_mcst_frms);
6021         tmp_stats[i++] =
6022                 (u64)le32_to_cpu(stat_info->rmac_vld_bcst_frms_oflow) << 32 |
6023                 le32_to_cpu(stat_info->rmac_vld_bcst_frms);
6024         tmp_stats[i++] = le32_to_cpu(stat_info->rmac_in_rng_len_err_frms);
6025         tmp_stats[i++] = le32_to_cpu(stat_info->rmac_out_rng_len_err_frms);
6026         tmp_stats[i++] = le64_to_cpu(stat_info->rmac_long_frms);
6027         tmp_stats[i++] = le64_to_cpu(stat_info->rmac_pause_ctrl_frms);
6028         tmp_stats[i++] = le64_to_cpu(stat_info->rmac_unsup_ctrl_frms);
6029         tmp_stats[i++] =
6030                 (u64)le32_to_cpu(stat_info->rmac_ttl_octets_oflow) << 32 |
6031                 le32_to_cpu(stat_info->rmac_ttl_octets);
6032         tmp_stats[i++] =
6033                 (u64)le32_to_cpu(stat_info->rmac_accepted_ucst_frms_oflow)
6034                 << 32 | le32_to_cpu(stat_info->rmac_accepted_ucst_frms);
6035         tmp_stats[i++] =
6036                 (u64)le32_to_cpu(stat_info->rmac_accepted_nucst_frms_oflow)
6037                  << 32 | le32_to_cpu(stat_info->rmac_accepted_nucst_frms);
6038         tmp_stats[i++] =
6039                 (u64)le32_to_cpu(stat_info->rmac_discarded_frms_oflow) << 32 |
6040                 le32_to_cpu(stat_info->rmac_discarded_frms);
6041         tmp_stats[i++] =
6042                 (u64)le32_to_cpu(stat_info->rmac_drop_events_oflow)
6043                  << 32 | le32_to_cpu(stat_info->rmac_drop_events);
6044         tmp_stats[i++] = le64_to_cpu(stat_info->rmac_ttl_less_fb_octets);
6045         tmp_stats[i++] = le64_to_cpu(stat_info->rmac_ttl_frms);
6046         tmp_stats[i++] =
6047                 (u64)le32_to_cpu(stat_info->rmac_usized_frms_oflow) << 32 |
6048                 le32_to_cpu(stat_info->rmac_usized_frms);
6049         tmp_stats[i++] =
6050                 (u64)le32_to_cpu(stat_info->rmac_osized_frms_oflow) << 32 |
6051                 le32_to_cpu(stat_info->rmac_osized_frms);
6052         tmp_stats[i++] =
6053                 (u64)le32_to_cpu(stat_info->rmac_frag_frms_oflow) << 32 |
6054                 le32_to_cpu(stat_info->rmac_frag_frms);
6055         tmp_stats[i++] =
6056                 (u64)le32_to_cpu(stat_info->rmac_jabber_frms_oflow) << 32 |
6057                 le32_to_cpu(stat_info->rmac_jabber_frms);
6058         tmp_stats[i++] = le64_to_cpu(stat_info->rmac_ttl_64_frms);
6059         tmp_stats[i++] = le64_to_cpu(stat_info->rmac_ttl_65_127_frms);
6060         tmp_stats[i++] = le64_to_cpu(stat_info->rmac_ttl_128_255_frms);
6061         tmp_stats[i++] = le64_to_cpu(stat_info->rmac_ttl_256_511_frms);
6062         tmp_stats[i++] = le64_to_cpu(stat_info->rmac_ttl_512_1023_frms);
6063         tmp_stats[i++] = le64_to_cpu(stat_info->rmac_ttl_1024_1518_frms);
6064         tmp_stats[i++] =
6065                 (u64)le32_to_cpu(stat_info->rmac_ip_oflow) << 32 |
6066                 le32_to_cpu(stat_info->rmac_ip);
6067         tmp_stats[i++] = le64_to_cpu(stat_info->rmac_ip_octets);
6068         tmp_stats[i++] = le32_to_cpu(stat_info->rmac_hdr_err_ip);
6069         tmp_stats[i++] =
6070                 (u64)le32_to_cpu(stat_info->rmac_drop_ip_oflow) << 32 |
6071                 le32_to_cpu(stat_info->rmac_drop_ip);
6072         tmp_stats[i++] =
6073                 (u64)le32_to_cpu(stat_info->rmac_icmp_oflow) << 32 |
6074                 le32_to_cpu(stat_info->rmac_icmp);
6075         tmp_stats[i++] = le64_to_cpu(stat_info->rmac_tcp);
6076         tmp_stats[i++] =
6077                 (u64)le32_to_cpu(stat_info->rmac_udp_oflow) << 32 |
6078                 le32_to_cpu(stat_info->rmac_udp);
6079         tmp_stats[i++] =
6080                 (u64)le32_to_cpu(stat_info->rmac_err_drp_udp_oflow) << 32 |
6081                 le32_to_cpu(stat_info->rmac_err_drp_udp);
6082         tmp_stats[i++] = le64_to_cpu(stat_info->rmac_xgmii_err_sym);
6083         tmp_stats[i++] = le64_to_cpu(stat_info->rmac_frms_q0);
6084         tmp_stats[i++] = le64_to_cpu(stat_info->rmac_frms_q1);
6085         tmp_stats[i++] = le64_to_cpu(stat_info->rmac_frms_q2);
6086         tmp_stats[i++] = le64_to_cpu(stat_info->rmac_frms_q3);
6087         tmp_stats[i++] = le64_to_cpu(stat_info->rmac_frms_q4);
6088         tmp_stats[i++] = le64_to_cpu(stat_info->rmac_frms_q5);
6089         tmp_stats[i++] = le64_to_cpu(stat_info->rmac_frms_q6);
6090         tmp_stats[i++] = le64_to_cpu(stat_info->rmac_frms_q7);
6091         tmp_stats[i++] = le16_to_cpu(stat_info->rmac_full_q0);
6092         tmp_stats[i++] = le16_to_cpu(stat_info->rmac_full_q1);
6093         tmp_stats[i++] = le16_to_cpu(stat_info->rmac_full_q2);
6094         tmp_stats[i++] = le16_to_cpu(stat_info->rmac_full_q3);
6095         tmp_stats[i++] = le16_to_cpu(stat_info->rmac_full_q4);
6096         tmp_stats[i++] = le16_to_cpu(stat_info->rmac_full_q5);
6097         tmp_stats[i++] = le16_to_cpu(stat_info->rmac_full_q6);
6098         tmp_stats[i++] = le16_to_cpu(stat_info->rmac_full_q7);
6099         tmp_stats[i++] =
6100                 (u64)le32_to_cpu(stat_info->rmac_pause_cnt_oflow) << 32 |
6101                 le32_to_cpu(stat_info->rmac_pause_cnt);
6102         tmp_stats[i++] = le64_to_cpu(stat_info->rmac_xgmii_data_err_cnt);
6103         tmp_stats[i++] = le64_to_cpu(stat_info->rmac_xgmii_ctrl_err_cnt);
6104         tmp_stats[i++] =
6105                 (u64)le32_to_cpu(stat_info->rmac_accepted_ip_oflow) << 32 |
6106                 le32_to_cpu(stat_info->rmac_accepted_ip);
6107         tmp_stats[i++] = le32_to_cpu(stat_info->rmac_err_tcp);
6108         tmp_stats[i++] = le32_to_cpu(stat_info->rd_req_cnt);
6109         tmp_stats[i++] = le32_to_cpu(stat_info->new_rd_req_cnt);
6110         tmp_stats[i++] = le32_to_cpu(stat_info->new_rd_req_rtry_cnt);
6111         tmp_stats[i++] = le32_to_cpu(stat_info->rd_rtry_cnt);
6112         tmp_stats[i++] = le32_to_cpu(stat_info->wr_rtry_rd_ack_cnt);
6113         tmp_stats[i++] = le32_to_cpu(stat_info->wr_req_cnt);
6114         tmp_stats[i++] = le32_to_cpu(stat_info->new_wr_req_cnt);
6115         tmp_stats[i++] = le32_to_cpu(stat_info->new_wr_req_rtry_cnt);
6116         tmp_stats[i++] = le32_to_cpu(stat_info->wr_rtry_cnt);
6117         tmp_stats[i++] = le32_to_cpu(stat_info->wr_disc_cnt);
6118         tmp_stats[i++] = le32_to_cpu(stat_info->rd_rtry_wr_ack_cnt);
6119         tmp_stats[i++] = le32_to_cpu(stat_info->txp_wr_cnt);
6120         tmp_stats[i++] = le32_to_cpu(stat_info->txd_rd_cnt);
6121         tmp_stats[i++] = le32_to_cpu(stat_info->txd_wr_cnt);
6122         tmp_stats[i++] = le32_to_cpu(stat_info->rxd_rd_cnt);
6123         tmp_stats[i++] = le32_to_cpu(stat_info->rxd_wr_cnt);
6124         tmp_stats[i++] = le32_to_cpu(stat_info->txf_rd_cnt);
6125         tmp_stats[i++] = le32_to_cpu(stat_info->rxf_wr_cnt);
6126
6127         /* Enhanced statistics exist only for Hercules */
6128         if(sp->device_type == XFRAME_II_DEVICE) {
6129                 tmp_stats[i++] =
6130                                 le64_to_cpu(stat_info->rmac_ttl_1519_4095_frms);
6131                 tmp_stats[i++] =
6132                                 le64_to_cpu(stat_info->rmac_ttl_4096_8191_frms);
6133                 tmp_stats[i++] =
6134                                 le64_to_cpu(stat_info->rmac_ttl_8192_max_frms);
6135                 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_ttl_gt_max_frms);
6136                 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_osized_alt_frms);
6137                 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_jabber_alt_frms);
6138                 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_gt_max_alt_frms);
6139                 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_vlan_frms);
6140                 tmp_stats[i++] = le32_to_cpu(stat_info->rmac_len_discard);
6141                 tmp_stats[i++] = le32_to_cpu(stat_info->rmac_fcs_discard);
6142                 tmp_stats[i++] = le32_to_cpu(stat_info->rmac_pf_discard);
6143                 tmp_stats[i++] = le32_to_cpu(stat_info->rmac_da_discard);
6144                 tmp_stats[i++] = le32_to_cpu(stat_info->rmac_red_discard);
6145                 tmp_stats[i++] = le32_to_cpu(stat_info->rmac_rts_discard);
6146                 tmp_stats[i++] = le32_to_cpu(stat_info->rmac_ingm_full_discard);
6147                 tmp_stats[i++] = le32_to_cpu(stat_info->link_fault_cnt);
6148         }
6149
6150         tmp_stats[i++] = 0;
6151         tmp_stats[i++] = stat_info->sw_stat.single_ecc_errs;
6152         tmp_stats[i++] = stat_info->sw_stat.double_ecc_errs;
6153         tmp_stats[i++] = stat_info->sw_stat.parity_err_cnt;
6154         tmp_stats[i++] = stat_info->sw_stat.serious_err_cnt;
6155         tmp_stats[i++] = stat_info->sw_stat.soft_reset_cnt;
6156         tmp_stats[i++] = stat_info->sw_stat.fifo_full_cnt;
6157         for (k = 0; k < MAX_RX_RINGS; k++)
6158                 tmp_stats[i++] = stat_info->sw_stat.ring_full_cnt[k];
6159         tmp_stats[i++] = stat_info->xpak_stat.alarm_transceiver_temp_high;
6160         tmp_stats[i++] = stat_info->xpak_stat.alarm_transceiver_temp_low;
6161         tmp_stats[i++] = stat_info->xpak_stat.alarm_laser_bias_current_high;
6162         tmp_stats[i++] = stat_info->xpak_stat.alarm_laser_bias_current_low;
6163         tmp_stats[i++] = stat_info->xpak_stat.alarm_laser_output_power_high;
6164         tmp_stats[i++] = stat_info->xpak_stat.alarm_laser_output_power_low;
6165         tmp_stats[i++] = stat_info->xpak_stat.warn_transceiver_temp_high;
6166         tmp_stats[i++] = stat_info->xpak_stat.warn_transceiver_temp_low;
6167         tmp_stats[i++] = stat_info->xpak_stat.warn_laser_bias_current_high;
6168         tmp_stats[i++] = stat_info->xpak_stat.warn_laser_bias_current_low;
6169         tmp_stats[i++] = stat_info->xpak_stat.warn_laser_output_power_high;
6170         tmp_stats[i++] = stat_info->xpak_stat.warn_laser_output_power_low;
6171         tmp_stats[i++] = stat_info->sw_stat.clubbed_frms_cnt;
6172         tmp_stats[i++] = stat_info->sw_stat.sending_both;
6173         tmp_stats[i++] = stat_info->sw_stat.outof_sequence_pkts;
6174         tmp_stats[i++] = stat_info->sw_stat.flush_max_pkts;
6175         if (stat_info->sw_stat.num_aggregations) {
6176                 u64 tmp = stat_info->sw_stat.sum_avg_pkts_aggregated;
6177                 int count = 0;
6178                 /*
6179                  * Since 64-bit divide does not work on all platforms,
6180                  * do repeated subtraction.
6181                  */
6182                 while (tmp >= stat_info->sw_stat.num_aggregations) {
6183                         tmp -= stat_info->sw_stat.num_aggregations;
6184                         count++;
6185                 }
6186                 tmp_stats[i++] = count;
6187         }
6188         else
6189                 tmp_stats[i++] = 0;
6190         tmp_stats[i++] = stat_info->sw_stat.mem_alloc_fail_cnt;
6191         tmp_stats[i++] = stat_info->sw_stat.pci_map_fail_cnt;
6192         tmp_stats[i++] = stat_info->sw_stat.watchdog_timer_cnt;
6193         tmp_stats[i++] = stat_info->sw_stat.mem_allocated;
6194         tmp_stats[i++] = stat_info->sw_stat.mem_freed;
6195         tmp_stats[i++] = stat_info->sw_stat.link_up_cnt;
6196         tmp_stats[i++] = stat_info->sw_stat.link_down_cnt;
6197         tmp_stats[i++] = stat_info->sw_stat.link_up_time;
6198         tmp_stats[i++] = stat_info->sw_stat.link_down_time;
6199
6200         tmp_stats[i++] = stat_info->sw_stat.tx_buf_abort_cnt;
6201         tmp_stats[i++] = stat_info->sw_stat.tx_desc_abort_cnt;
6202         tmp_stats[i++] = stat_info->sw_stat.tx_parity_err_cnt;
6203         tmp_stats[i++] = stat_info->sw_stat.tx_link_loss_cnt;
6204         tmp_stats[i++] = stat_info->sw_stat.tx_list_proc_err_cnt;
6205
6206         tmp_stats[i++] = stat_info->sw_stat.rx_parity_err_cnt;
6207         tmp_stats[i++] = stat_info->sw_stat.rx_abort_cnt;
6208         tmp_stats[i++] = stat_info->sw_stat.rx_parity_abort_cnt;
6209         tmp_stats[i++] = stat_info->sw_stat.rx_rda_fail_cnt;
6210         tmp_stats[i++] = stat_info->sw_stat.rx_unkn_prot_cnt;
6211         tmp_stats[i++] = stat_info->sw_stat.rx_fcs_err_cnt;
6212         tmp_stats[i++] = stat_info->sw_stat.rx_buf_size_err_cnt;
6213         tmp_stats[i++] = stat_info->sw_stat.rx_rxd_corrupt_cnt;
6214         tmp_stats[i++] = stat_info->sw_stat.rx_unkn_err_cnt;
6215         tmp_stats[i++] = stat_info->sw_stat.tda_err_cnt;
6216         tmp_stats[i++] = stat_info->sw_stat.pfc_err_cnt;
6217         tmp_stats[i++] = stat_info->sw_stat.pcc_err_cnt;
6218         tmp_stats[i++] = stat_info->sw_stat.tti_err_cnt;
6219         tmp_stats[i++] = stat_info->sw_stat.tpa_err_cnt;
6220         tmp_stats[i++] = stat_info->sw_stat.sm_err_cnt;
6221         tmp_stats[i++] = stat_info->sw_stat.lso_err_cnt;
6222         tmp_stats[i++] = stat_info->sw_stat.mac_tmac_err_cnt;
6223         tmp_stats[i++] = stat_info->sw_stat.mac_rmac_err_cnt;
6224         tmp_stats[i++] = stat_info->sw_stat.xgxs_txgxs_err_cnt;
6225         tmp_stats[i++] = stat_info->sw_stat.xgxs_rxgxs_err_cnt;
6226         tmp_stats[i++] = stat_info->sw_stat.rc_err_cnt;
6227         tmp_stats[i++] = stat_info->sw_stat.prc_pcix_err_cnt;
6228         tmp_stats[i++] = stat_info->sw_stat.rpa_err_cnt;
6229         tmp_stats[i++] = stat_info->sw_stat.rda_err_cnt;
6230         tmp_stats[i++] = stat_info->sw_stat.rti_err_cnt;
6231         tmp_stats[i++] = stat_info->sw_stat.mc_err_cnt;
6232 }
6233
6234 static int s2io_ethtool_get_regs_len(struct net_device *dev)
6235 {
6236         return (XENA_REG_SPACE);
6237 }
6238
6239
6240 static u32 s2io_ethtool_get_rx_csum(struct net_device * dev)
6241 {
6242         struct s2io_nic *sp = dev->priv;
6243
6244         return (sp->rx_csum);
6245 }
6246
6247 static int s2io_ethtool_set_rx_csum(struct net_device *dev, u32 data)
6248 {
6249         struct s2io_nic *sp = dev->priv;
6250
6251         if (data)
6252                 sp->rx_csum = 1;
6253         else
6254                 sp->rx_csum = 0;
6255
6256         return 0;
6257 }
6258
6259 static int s2io_get_eeprom_len(struct net_device *dev)
6260 {
6261         return (XENA_EEPROM_SPACE);
6262 }
6263
6264 static int s2io_ethtool_self_test_count(struct net_device *dev)
6265 {
6266         return (S2IO_TEST_LEN);
6267 }
6268
6269 static void s2io_ethtool_get_strings(struct net_device *dev,
6270                                      u32 stringset, u8 * data)
6271 {
6272         int stat_size = 0;
6273         struct s2io_nic *sp = dev->priv;
6274
6275         switch (stringset) {
6276         case ETH_SS_TEST:
6277                 memcpy(data, s2io_gstrings, S2IO_STRINGS_LEN);
6278                 break;
6279         case ETH_SS_STATS:
6280                 stat_size = sizeof(ethtool_xena_stats_keys);
6281                 memcpy(data, &ethtool_xena_stats_keys,stat_size);
6282                 if(sp->device_type == XFRAME_II_DEVICE) {
6283                         memcpy(data + stat_size,
6284                                 &ethtool_enhanced_stats_keys,
6285                                 sizeof(ethtool_enhanced_stats_keys));
6286                         stat_size += sizeof(ethtool_enhanced_stats_keys);
6287                 }
6288
6289                 memcpy(data + stat_size, &ethtool_driver_stats_keys,
6290                         sizeof(ethtool_driver_stats_keys));
6291         }
6292 }
6293 static int s2io_ethtool_get_stats_count(struct net_device *dev)
6294 {
6295         struct s2io_nic *sp = dev->priv;
6296         int stat_count = 0;
6297         switch(sp->device_type) {
6298         case XFRAME_I_DEVICE:
6299                 stat_count = XFRAME_I_STAT_LEN;
6300         break;
6301
6302         case XFRAME_II_DEVICE:
6303                 stat_count = XFRAME_II_STAT_LEN;
6304         break;
6305         }
6306
6307         return stat_count;
6308 }
6309
6310 static int s2io_ethtool_op_set_tx_csum(struct net_device *dev, u32 data)
6311 {
6312         if (data)
6313                 dev->features |= NETIF_F_IP_CSUM;
6314         else
6315                 dev->features &= ~NETIF_F_IP_CSUM;
6316
6317         return 0;
6318 }
6319
6320 static u32 s2io_ethtool_op_get_tso(struct net_device *dev)
6321 {
6322         return (dev->features & NETIF_F_TSO) != 0;
6323 }
6324 static int s2io_ethtool_op_set_tso(struct net_device *dev, u32 data)
6325 {
6326         if (data)
6327                 dev->features |= (NETIF_F_TSO | NETIF_F_TSO6);
6328         else
6329                 dev->features &= ~(NETIF_F_TSO | NETIF_F_TSO6);
6330
6331         return 0;
6332 }
6333
6334 static const struct ethtool_ops netdev_ethtool_ops = {
6335         .get_settings = s2io_ethtool_gset,
6336         .set_settings = s2io_ethtool_sset,
6337         .get_drvinfo = s2io_ethtool_gdrvinfo,
6338         .get_regs_len = s2io_ethtool_get_regs_len,
6339         .get_regs = s2io_ethtool_gregs,
6340         .get_link = ethtool_op_get_link,
6341         .get_eeprom_len = s2io_get_eeprom_len,
6342         .get_eeprom = s2io_ethtool_geeprom,
6343         .set_eeprom = s2io_ethtool_seeprom,
6344         .get_ringparam = s2io_ethtool_gringparam,
6345         .get_pauseparam = s2io_ethtool_getpause_data,
6346         .set_pauseparam = s2io_ethtool_setpause_data,
6347         .get_rx_csum = s2io_ethtool_get_rx_csum,
6348         .set_rx_csum = s2io_ethtool_set_rx_csum,
6349         .get_tx_csum = ethtool_op_get_tx_csum,
6350         .set_tx_csum = s2io_ethtool_op_set_tx_csum,
6351         .get_sg = ethtool_op_get_sg,
6352         .set_sg = ethtool_op_set_sg,
6353         .get_tso = s2io_ethtool_op_get_tso,
6354         .set_tso = s2io_ethtool_op_set_tso,
6355         .get_ufo = ethtool_op_get_ufo,
6356         .set_ufo = ethtool_op_set_ufo,
6357         .self_test_count = s2io_ethtool_self_test_count,
6358         .self_test = s2io_ethtool_test,
6359         .get_strings = s2io_ethtool_get_strings,
6360         .phys_id = s2io_ethtool_idnic,
6361         .get_stats_count = s2io_ethtool_get_stats_count,
6362         .get_ethtool_stats = s2io_get_ethtool_stats
6363 };
6364
6365 /**
6366  *  s2io_ioctl - Entry point for the Ioctl
6367  *  @dev :  Device pointer.
6368  *  @ifr :  An IOCTL specefic structure, that can contain a pointer to
6369  *  a proprietary structure used to pass information to the driver.
6370  *  @cmd :  This is used to distinguish between the different commands that
6371  *  can be passed to the IOCTL functions.
6372  *  Description:
6373  *  Currently there are no special functionality supported in IOCTL, hence
6374  *  function always return EOPNOTSUPPORTED
6375  */
6376
6377 static int s2io_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
6378 {
6379         return -EOPNOTSUPP;
6380 }
6381
6382 /**
6383  *  s2io_change_mtu - entry point to change MTU size for the device.
6384  *   @dev : device pointer.
6385  *   @new_mtu : the new MTU size for the device.
6386  *   Description: A driver entry point to change MTU size for the device.
6387  *   Before changing the MTU the device must be stopped.
6388  *  Return value:
6389  *   0 on success and an appropriate (-)ve integer as defined in errno.h
6390  *   file on failure.
6391  */
6392
6393 static int s2io_change_mtu(struct net_device *dev, int new_mtu)
6394 {
6395         struct s2io_nic *sp = dev->priv;
6396
6397         if ((new_mtu < MIN_MTU) || (new_mtu > S2IO_JUMBO_SIZE)) {
6398                 DBG_PRINT(ERR_DBG, "%s: MTU size is invalid.\n",
6399                           dev->name);
6400                 return -EPERM;
6401         }
6402
6403         dev->mtu = new_mtu;
6404         if (netif_running(dev)) {
6405                 s2io_card_down(sp);
6406                 netif_stop_queue(dev);
6407                 if (s2io_card_up(sp)) {
6408                         DBG_PRINT(ERR_DBG, "%s: Device bring up failed\n",
6409                                   __FUNCTION__);
6410                 }
6411                 if (netif_queue_stopped(dev))
6412                         netif_wake_queue(dev);
6413         } else { /* Device is down */
6414                 struct XENA_dev_config __iomem *bar0 = sp->bar0;
6415                 u64 val64 = new_mtu;
6416
6417                 writeq(vBIT(val64, 2, 14), &bar0->rmac_max_pyld_len);
6418         }
6419
6420         return 0;
6421 }
6422
6423 /**
6424  *  s2io_tasklet - Bottom half of the ISR.
6425  *  @dev_adr : address of the device structure in dma_addr_t format.
6426  *  Description:
6427  *  This is the tasklet or the bottom half of the ISR. This is
6428  *  an extension of the ISR which is scheduled by the scheduler to be run
6429  *  when the load on the CPU is low. All low priority tasks of the ISR can
6430  *  be pushed into the tasklet. For now the tasklet is used only to
6431  *  replenish the Rx buffers in the Rx buffer descriptors.
6432  *  Return value:
6433  *  void.
6434  */
6435
6436 static void s2io_tasklet(unsigned long dev_addr)
6437 {
6438         struct net_device *dev = (struct net_device *) dev_addr;
6439         struct s2io_nic *sp = dev->priv;
6440         int i, ret;
6441         struct mac_info *mac_control;
6442         struct config_param *config;
6443
6444         mac_control = &sp->mac_control;
6445         config = &sp->config;
6446
6447         if (!TASKLET_IN_USE) {
6448                 for (i = 0; i < config->rx_ring_num; i++) {
6449                         ret = fill_rx_buffers(sp, i);
6450                         if (ret == -ENOMEM) {
6451                                 DBG_PRINT(INFO_DBG, "%s: Out of ",
6452                                           dev->name);
6453                                 DBG_PRINT(INFO_DBG, "memory in tasklet\n");
6454                                 break;
6455                         } else if (ret == -EFILL) {
6456                                 DBG_PRINT(INFO_DBG,
6457                                           "%s: Rx Ring %d is full\n",
6458                                           dev->name, i);
6459                                 break;
6460                         }
6461                 }
6462                 clear_bit(0, (&sp->tasklet_status));
6463         }
6464 }
6465
6466 /**
6467  * s2io_set_link - Set the LInk status
6468  * @data: long pointer to device private structue
6469  * Description: Sets the link status for the adapter
6470  */
6471
6472 static void s2io_set_link(struct work_struct *work)
6473 {
6474         struct s2io_nic *nic = container_of(work, struct s2io_nic, set_link_task);
6475         struct net_device *dev = nic->dev;
6476         struct XENA_dev_config __iomem *bar0 = nic->bar0;
6477         register u64 val64;
6478         u16 subid;
6479
6480         rtnl_lock();
6481
6482         if (!netif_running(dev))
6483                 goto out_unlock;
6484
6485         if (test_and_set_bit(__S2IO_STATE_LINK_TASK, &(nic->state))) {
6486                 /* The card is being reset, no point doing anything */
6487                 goto out_unlock;
6488         }
6489
6490         subid = nic->pdev->subsystem_device;
6491         if (s2io_link_fault_indication(nic) == MAC_RMAC_ERR_TIMER) {
6492                 /*
6493                  * Allow a small delay for the NICs self initiated
6494                  * cleanup to complete.
6495                  */
6496                 msleep(100);
6497         }
6498
6499         val64 = readq(&bar0->adapter_status);
6500         if (LINK_IS_UP(val64)) {
6501                 if (!(readq(&bar0->adapter_control) & ADAPTER_CNTL_EN)) {
6502                         if (verify_xena_quiescence(nic)) {
6503                                 val64 = readq(&bar0->adapter_control);
6504                                 val64 |= ADAPTER_CNTL_EN;
6505                                 writeq(val64, &bar0->adapter_control);
6506                                 if (CARDS_WITH_FAULTY_LINK_INDICATORS(
6507                                         nic->device_type, subid)) {
6508                                         val64 = readq(&bar0->gpio_control);
6509                                         val64 |= GPIO_CTRL_GPIO_0;
6510                                         writeq(val64, &bar0->gpio_control);
6511                                         val64 = readq(&bar0->gpio_control);
6512                                 } else {
6513                                         val64 |= ADAPTER_LED_ON;
6514                                         writeq(val64, &bar0->adapter_control);
6515                                 }
6516                                 nic->device_enabled_once = TRUE;
6517                         } else {
6518                                 DBG_PRINT(ERR_DBG, "%s: Error: ", dev->name);
6519                                 DBG_PRINT(ERR_DBG, "device is not Quiescent\n");
6520                                 netif_stop_queue(dev);
6521                         }
6522                 }
6523                 val64 = readq(&bar0->adapter_control);
6524                 val64 |= ADAPTER_LED_ON;
6525                 writeq(val64, &bar0->adapter_control);
6526                 s2io_link(nic, LINK_UP);
6527         } else {
6528                 if (CARDS_WITH_FAULTY_LINK_INDICATORS(nic->device_type,
6529                                                       subid)) {
6530                         val64 = readq(&bar0->gpio_control);
6531                         val64 &= ~GPIO_CTRL_GPIO_0;
6532                         writeq(val64, &bar0->gpio_control);
6533                         val64 = readq(&bar0->gpio_control);
6534                 }
6535                 /* turn off LED */
6536                 val64 = readq(&bar0->adapter_control);
6537                 val64 = val64 &(~ADAPTER_LED_ON);
6538                 writeq(val64, &bar0->adapter_control);
6539                 s2io_link(nic, LINK_DOWN);
6540         }
6541         clear_bit(__S2IO_STATE_LINK_TASK, &(nic->state));
6542
6543 out_unlock:
6544         rtnl_unlock();
6545 }
6546
6547 static int set_rxd_buffer_pointer(struct s2io_nic *sp, struct RxD_t *rxdp,
6548                                 struct buffAdd *ba,
6549                                 struct sk_buff **skb, u64 *temp0, u64 *temp1,
6550                                 u64 *temp2, int size)
6551 {
6552         struct net_device *dev = sp->dev;
6553         struct swStat *stats = &sp->mac_control.stats_info->sw_stat;
6554
6555         if ((sp->rxd_mode == RXD_MODE_1) && (rxdp->Host_Control == 0)) {
6556                 struct RxD1 *rxdp1 = (struct RxD1 *)rxdp;
6557                 /* allocate skb */
6558                 if (*skb) {
6559                         DBG_PRINT(INFO_DBG, "SKB is not NULL\n");
6560                         /*
6561                          * As Rx frame are not going to be processed,
6562                          * using same mapped address for the Rxd
6563                          * buffer pointer
6564                          */
6565                         rxdp1->Buffer0_ptr = *temp0;
6566                 } else {
6567                         *skb = dev_alloc_skb(size);
6568                         if (!(*skb)) {
6569                                 DBG_PRINT(INFO_DBG, "%s: Out of ", dev->name);
6570                                 DBG_PRINT(INFO_DBG, "memory to allocate ");
6571                                 DBG_PRINT(INFO_DBG, "1 buf mode SKBs\n");
6572                                 sp->mac_control.stats_info->sw_stat. \
6573                                         mem_alloc_fail_cnt++;
6574                                 return -ENOMEM ;
6575                         }
6576                         sp->mac_control.stats_info->sw_stat.mem_allocated
6577                                 += (*skb)->truesize;
6578                         /* storing the mapped addr in a temp variable
6579                          * such it will be used for next rxd whose
6580                          * Host Control is NULL
6581                          */
6582                         rxdp1->Buffer0_ptr = *temp0 =
6583                                 pci_map_single( sp->pdev, (*skb)->data,
6584                                         size - NET_IP_ALIGN,
6585                                         PCI_DMA_FROMDEVICE);
6586                         if( (rxdp1->Buffer0_ptr == 0) ||
6587                                 (rxdp1->Buffer0_ptr == DMA_ERROR_CODE)) {
6588                                 goto memalloc_failed;
6589                         }
6590                         rxdp->Host_Control = (unsigned long) (*skb);
6591                 }
6592         } else if ((sp->rxd_mode == RXD_MODE_3B) && (rxdp->Host_Control == 0)) {
6593                 struct RxD3 *rxdp3 = (struct RxD3 *)rxdp;
6594                 /* Two buffer Mode */
6595                 if (*skb) {
6596                         rxdp3->Buffer2_ptr = *temp2;
6597                         rxdp3->Buffer0_ptr = *temp0;
6598                         rxdp3->Buffer1_ptr = *temp1;
6599                 } else {
6600                         *skb = dev_alloc_skb(size);
6601                         if (!(*skb)) {
6602                                 DBG_PRINT(INFO_DBG, "%s: Out of ", dev->name);
6603                                 DBG_PRINT(INFO_DBG, "memory to allocate ");
6604                                 DBG_PRINT(INFO_DBG, "2 buf mode SKBs\n");
6605                                 sp->mac_control.stats_info->sw_stat. \
6606                                         mem_alloc_fail_cnt++;
6607                                 return -ENOMEM;
6608                         }
6609                         sp->mac_control.stats_info->sw_stat.mem_allocated
6610                                 += (*skb)->truesize;
6611                         rxdp3->Buffer2_ptr = *temp2 =
6612                                 pci_map_single(sp->pdev, (*skb)->data,
6613                                                dev->mtu + 4,
6614                                                PCI_DMA_FROMDEVICE);
6615                         if( (rxdp3->Buffer2_ptr == 0) ||
6616                                 (rxdp3->Buffer2_ptr == DMA_ERROR_CODE)) {
6617                                 goto memalloc_failed;
6618                         }
6619                         rxdp3->Buffer0_ptr = *temp0 =
6620                                 pci_map_single( sp->pdev, ba->ba_0, BUF0_LEN,
6621                                                 PCI_DMA_FROMDEVICE);
6622                         if( (rxdp3->Buffer0_ptr == 0) ||
6623                                 (rxdp3->Buffer0_ptr == DMA_ERROR_CODE)) {
6624                                 pci_unmap_single (sp->pdev,
6625                                         (dma_addr_t)rxdp3->Buffer2_ptr,
6626                                         dev->mtu + 4, PCI_DMA_FROMDEVICE);
6627                                 goto memalloc_failed;
6628                         }
6629                         rxdp->Host_Control = (unsigned long) (*skb);
6630
6631                         /* Buffer-1 will be dummy buffer not used */
6632                         rxdp3->Buffer1_ptr = *temp1 =
6633                                 pci_map_single(sp->pdev, ba->ba_1, BUF1_LEN,
6634                                                 PCI_DMA_FROMDEVICE);
6635                         if( (rxdp3->Buffer1_ptr == 0) ||
6636                                 (rxdp3->Buffer1_ptr == DMA_ERROR_CODE)) {
6637                                 pci_unmap_single (sp->pdev,
6638                                         (dma_addr_t)rxdp3->Buffer0_ptr,
6639                                         BUF0_LEN, PCI_DMA_FROMDEVICE);
6640                                 pci_unmap_single (sp->pdev,
6641                                         (dma_addr_t)rxdp3->Buffer2_ptr,
6642                                         dev->mtu + 4, PCI_DMA_FROMDEVICE);
6643                                 goto memalloc_failed;
6644                         }
6645                 }
6646         }
6647         return 0;
6648         memalloc_failed:
6649                 stats->pci_map_fail_cnt++;
6650                 stats->mem_freed += (*skb)->truesize;
6651                 dev_kfree_skb(*skb);
6652                 return -ENOMEM;
6653 }
6654
6655 static void set_rxd_buffer_size(struct s2io_nic *sp, struct RxD_t *rxdp,
6656                                 int size)
6657 {
6658         struct net_device *dev = sp->dev;
6659         if (sp->rxd_mode == RXD_MODE_1) {
6660                 rxdp->Control_2 = SET_BUFFER0_SIZE_1( size - NET_IP_ALIGN);
6661         } else if (sp->rxd_mode == RXD_MODE_3B) {
6662                 rxdp->Control_2 = SET_BUFFER0_SIZE_3(BUF0_LEN);
6663                 rxdp->Control_2 |= SET_BUFFER1_SIZE_3(1);
6664                 rxdp->Control_2 |= SET_BUFFER2_SIZE_3( dev->mtu + 4);
6665         }
6666 }
6667
6668 static  int rxd_owner_bit_reset(struct s2io_nic *sp)
6669 {
6670         int i, j, k, blk_cnt = 0, size;
6671         struct mac_info * mac_control = &sp->mac_control;
6672         struct config_param *config = &sp->config;
6673         struct net_device *dev = sp->dev;
6674         struct RxD_t *rxdp = NULL;
6675         struct sk_buff *skb = NULL;
6676         struct buffAdd *ba = NULL;
6677         u64 temp0_64 = 0, temp1_64 = 0, temp2_64 = 0;
6678
6679         /* Calculate the size based on ring mode */
6680         size = dev->mtu + HEADER_ETHERNET_II_802_3_SIZE +
6681                 HEADER_802_2_SIZE + HEADER_SNAP_SIZE;
6682         if (sp->rxd_mode == RXD_MODE_1)
6683                 size += NET_IP_ALIGN;
6684         else if (sp->rxd_mode == RXD_MODE_3B)
6685                 size = dev->mtu + ALIGN_SIZE + BUF0_LEN + 4;
6686
6687         for (i = 0; i < config->rx_ring_num; i++) {
6688                 blk_cnt = config->rx_cfg[i].num_rxd /
6689                         (rxd_count[sp->rxd_mode] +1);
6690
6691                 for (j = 0; j < blk_cnt; j++) {
6692                         for (k = 0; k < rxd_count[sp->rxd_mode]; k++) {
6693                                 rxdp = mac_control->rings[i].
6694                                         rx_blocks[j].rxds[k].virt_addr;
6695                                 if(sp->rxd_mode == RXD_MODE_3B)
6696                                         ba = &mac_control->rings[i].ba[j][k];
6697                                 if (set_rxd_buffer_pointer(sp, rxdp, ba,
6698                                                        &skb,(u64 *)&temp0_64,
6699                                                        (u64 *)&temp1_64,
6700                                                        (u64 *)&temp2_64,
6701                                                         size) == ENOMEM) {
6702                                         return 0;
6703                                 }
6704
6705                                 set_rxd_buffer_size(sp, rxdp, size);
6706                                 wmb();
6707                                 /* flip the Ownership bit to Hardware */
6708                                 rxdp->Control_1 |= RXD_OWN_XENA;
6709                         }
6710                 }
6711         }
6712         return 0;
6713
6714 }
6715
6716 static int s2io_add_isr(struct s2io_nic * sp)
6717 {
6718         int ret = 0;
6719         struct net_device *dev = sp->dev;
6720         int err = 0;
6721
6722         if (sp->config.intr_type == MSI_X)
6723                 ret = s2io_enable_msi_x(sp);
6724         if (ret) {
6725                 DBG_PRINT(ERR_DBG, "%s: Defaulting to INTA\n", dev->name);
6726                 sp->config.intr_type = INTA;
6727         }
6728
6729         /* Store the values of the MSIX table in the struct s2io_nic structure */
6730         store_xmsi_data(sp);
6731
6732         /* After proper initialization of H/W, register ISR */
6733         if (sp->config.intr_type == MSI_X) {
6734                 int i, msix_tx_cnt=0,msix_rx_cnt=0;
6735
6736                 for (i=1; (sp->s2io_entries[i].in_use == MSIX_FLG); i++) {
6737                         if (sp->s2io_entries[i].type == MSIX_FIFO_TYPE) {
6738                                 sprintf(sp->desc[i], "%s:MSI-X-%d-TX",
6739                                         dev->name, i);
6740                                 err = request_irq(sp->entries[i].vector,
6741                                           s2io_msix_fifo_handle, 0, sp->desc[i],
6742                                                   sp->s2io_entries[i].arg);
6743                                 /* If either data or addr is zero print it */
6744                                 if(!(sp->msix_info[i].addr &&
6745                                         sp->msix_info[i].data)) {
6746                                         DBG_PRINT(ERR_DBG, "%s @ Addr:0x%llx"
6747                                                 "Data:0x%lx\n",sp->desc[i],
6748                                                 (unsigned long long)
6749                                                 sp->msix_info[i].addr,
6750                                                 (unsigned long)
6751                                                 ntohl(sp->msix_info[i].data));
6752                                 } else {
6753                                         msix_tx_cnt++;
6754                                 }
6755                         } else {
6756                                 sprintf(sp->desc[i], "%s:MSI-X-%d-RX",
6757                                         dev->name, i);
6758                                 err = request_irq(sp->entries[i].vector,
6759                                           s2io_msix_ring_handle, 0, sp->desc[i],
6760                                                   sp->s2io_entries[i].arg);
6761                                 /* If either data or addr is zero print it */
6762                                 if(!(sp->msix_info[i].addr &&
6763                                         sp->msix_info[i].data)) {
6764                                         DBG_PRINT(ERR_DBG, "%s @ Addr:0x%llx"
6765                                                 "Data:0x%lx\n",sp->desc[i],
6766                                                 (unsigned long long)
6767                                                 sp->msix_info[i].addr,
6768                                                 (unsigned long)
6769                                                 ntohl(sp->msix_info[i].data));
6770                                 } else {
6771                                         msix_rx_cnt++;
6772                                 }
6773                         }
6774                         if (err) {
6775                                 DBG_PRINT(ERR_DBG,"%s:MSI-X-%d registration "
6776                                           "failed\n", dev->name, i);
6777                                 DBG_PRINT(ERR_DBG, "Returned: %d\n", err);
6778                                 return -1;
6779                         }
6780                         sp->s2io_entries[i].in_use = MSIX_REGISTERED_SUCCESS;
6781                 }
6782                 printk("MSI-X-TX %d entries enabled\n",msix_tx_cnt);
6783                 printk("MSI-X-RX %d entries enabled\n",msix_rx_cnt);
6784         }
6785         if (sp->config.intr_type == INTA) {
6786                 err = request_irq((int) sp->pdev->irq, s2io_isr, IRQF_SHARED,
6787                                 sp->name, dev);
6788                 if (err) {
6789                         DBG_PRINT(ERR_DBG, "%s: ISR registration failed\n",
6790                                   dev->name);
6791                         return -1;
6792                 }
6793         }
6794         return 0;
6795 }
6796 static void s2io_rem_isr(struct s2io_nic * sp)
6797 {
6798         int cnt = 0;
6799         struct net_device *dev = sp->dev;
6800         struct swStat *stats = &sp->mac_control.stats_info->sw_stat;
6801
6802         if (sp->config.intr_type == MSI_X) {
6803                 int i;
6804                 u16 msi_control;
6805
6806                 for (i=1; (sp->s2io_entries[i].in_use ==
6807                         MSIX_REGISTERED_SUCCESS); i++) {
6808                         int vector = sp->entries[i].vector;
6809                         void *arg = sp->s2io_entries[i].arg;
6810
6811                         free_irq(vector, arg);
6812                 }
6813
6814                 kfree(sp->entries);
6815                 stats->mem_freed +=
6816                         (MAX_REQUESTED_MSI_X * sizeof(struct msix_entry));
6817                 kfree(sp->s2io_entries);
6818                 stats->mem_freed +=
6819                         (MAX_REQUESTED_MSI_X * sizeof(struct s2io_msix_entry));
6820                 sp->entries = NULL;
6821                 sp->s2io_entries = NULL;
6822
6823                 pci_read_config_word(sp->pdev, 0x42, &msi_control);
6824                 msi_control &= 0xFFFE; /* Disable MSI */
6825                 pci_write_config_word(sp->pdev, 0x42, msi_control);
6826
6827                 pci_disable_msix(sp->pdev);
6828         } else {
6829                 free_irq(sp->pdev->irq, dev);
6830         }
6831         /* Waiting till all Interrupt handlers are complete */
6832         cnt = 0;
6833         do {
6834                 msleep(10);
6835                 if (!atomic_read(&sp->isr_cnt))
6836                         break;
6837                 cnt++;
6838         } while(cnt < 5);
6839 }
6840
6841 static void do_s2io_card_down(struct s2io_nic * sp, int do_io)
6842 {
6843         int cnt = 0;
6844         struct XENA_dev_config __iomem *bar0 = sp->bar0;
6845         unsigned long flags;
6846         register u64 val64 = 0;
6847
6848         del_timer_sync(&sp->alarm_timer);
6849         /* If s2io_set_link task is executing, wait till it completes. */
6850         while (test_and_set_bit(__S2IO_STATE_LINK_TASK, &(sp->state))) {
6851                 msleep(50);
6852         }
6853         clear_bit(__S2IO_STATE_CARD_UP, &sp->state);
6854
6855         /* disable Tx and Rx traffic on the NIC */
6856         if (do_io)
6857                 stop_nic(sp);
6858
6859         s2io_rem_isr(sp);
6860
6861         /* Kill tasklet. */
6862         tasklet_kill(&sp->task);
6863
6864         /* Check if the device is Quiescent and then Reset the NIC */
6865         while(do_io) {
6866                 /* As per the HW requirement we need to replenish the
6867                  * receive buffer to avoid the ring bump. Since there is
6868                  * no intention of processing the Rx frame at this pointwe are
6869                  * just settting the ownership bit of rxd in Each Rx
6870                  * ring to HW and set the appropriate buffer size
6871                  * based on the ring mode
6872                  */
6873                 rxd_owner_bit_reset(sp);
6874
6875                 val64 = readq(&bar0->adapter_status);
6876                 if (verify_xena_quiescence(sp)) {
6877                         if(verify_pcc_quiescent(sp, sp->device_enabled_once))
6878                         break;
6879                 }
6880
6881                 msleep(50);
6882                 cnt++;
6883                 if (cnt == 10) {
6884                         DBG_PRINT(ERR_DBG,
6885                                   "s2io_close:Device not Quiescent ");
6886                         DBG_PRINT(ERR_DBG, "adaper status reads 0x%llx\n",
6887                                   (unsigned long long) val64);
6888                         break;
6889                 }
6890         }
6891         if (do_io)
6892                 s2io_reset(sp);
6893
6894         spin_lock_irqsave(&sp->tx_lock, flags);
6895         /* Free all Tx buffers */
6896         free_tx_buffers(sp);
6897         spin_unlock_irqrestore(&sp->tx_lock, flags);
6898
6899         /* Free all Rx buffers */
6900         spin_lock_irqsave(&sp->rx_lock, flags);
6901         free_rx_buffers(sp);
6902         spin_unlock_irqrestore(&sp->rx_lock, flags);
6903
6904         clear_bit(__S2IO_STATE_LINK_TASK, &(sp->state));
6905 }
6906
6907 static void s2io_card_down(struct s2io_nic * sp)
6908 {
6909         do_s2io_card_down(sp, 1);
6910 }
6911
6912 static int s2io_card_up(struct s2io_nic * sp)
6913 {
6914         int i, ret = 0;
6915         struct mac_info *mac_control;
6916         struct config_param *config;
6917         struct net_device *dev = (struct net_device *) sp->dev;
6918         u16 interruptible;
6919
6920         /* Initialize the H/W I/O registers */
6921         if (init_nic(sp) != 0) {
6922                 DBG_PRINT(ERR_DBG, "%s: H/W initialization failed\n",
6923                           dev->name);
6924                 s2io_reset(sp);
6925                 return -ENODEV;
6926         }
6927
6928         /*
6929          * Initializing the Rx buffers. For now we are considering only 1
6930          * Rx ring and initializing buffers into 30 Rx blocks
6931          */
6932         mac_control = &sp->mac_control;
6933         config = &sp->config;
6934
6935         for (i = 0; i < config->rx_ring_num; i++) {
6936                 if ((ret = fill_rx_buffers(sp, i))) {
6937                         DBG_PRINT(ERR_DBG, "%s: Out of memory in Open\n",
6938                                   dev->name);
6939                         s2io_reset(sp);
6940                         free_rx_buffers(sp);
6941                         return -ENOMEM;
6942                 }
6943                 DBG_PRINT(INFO_DBG, "Buf in ring:%d is %d:\n", i,
6944                           atomic_read(&sp->rx_bufs_left[i]));
6945         }
6946         /* Maintain the state prior to the open */
6947         if (sp->promisc_flg)
6948                 sp->promisc_flg = 0;
6949         if (sp->m_cast_flg) {
6950                 sp->m_cast_flg = 0;
6951                 sp->all_multi_pos= 0;
6952         }
6953
6954         /* Setting its receive mode */
6955         s2io_set_multicast(dev);
6956
6957         if (sp->lro) {
6958                 /* Initialize max aggregatable pkts per session based on MTU */
6959                 sp->lro_max_aggr_per_sess = ((1<<16) - 1) / dev->mtu;
6960                 /* Check if we can use(if specified) user provided value */
6961                 if (lro_max_pkts < sp->lro_max_aggr_per_sess)
6962                         sp->lro_max_aggr_per_sess = lro_max_pkts;
6963         }
6964
6965         /* Enable Rx Traffic and interrupts on the NIC */
6966         if (start_nic(sp)) {
6967                 DBG_PRINT(ERR_DBG, "%s: Starting NIC failed\n", dev->name);
6968                 s2io_reset(sp);
6969                 free_rx_buffers(sp);
6970                 return -ENODEV;
6971         }
6972
6973         /* Add interrupt service routine */
6974         if (s2io_add_isr(sp) != 0) {
6975                 if (sp->config.intr_type == MSI_X)
6976                         s2io_rem_isr(sp);
6977                 s2io_reset(sp);
6978                 free_rx_buffers(sp);
6979                 return -ENODEV;
6980         }
6981
6982         S2IO_TIMER_CONF(sp->alarm_timer, s2io_alarm_handle, sp, (HZ/2));
6983
6984         /* Enable tasklet for the device */
6985         tasklet_init(&sp->task, s2io_tasklet, (unsigned long) dev);
6986
6987         /*  Enable select interrupts */
6988         en_dis_err_alarms(sp, ENA_ALL_INTRS, ENABLE_INTRS);
6989         if (sp->config.intr_type != INTA)
6990                 en_dis_able_nic_intrs(sp, ENA_ALL_INTRS, DISABLE_INTRS);
6991         else {
6992                 interruptible = TX_TRAFFIC_INTR | RX_TRAFFIC_INTR;
6993                 interruptible |= TX_PIC_INTR;
6994                 en_dis_able_nic_intrs(sp, interruptible, ENABLE_INTRS);
6995         }
6996
6997         set_bit(__S2IO_STATE_CARD_UP, &sp->state);
6998         return 0;
6999 }
7000
7001 /**
7002  * s2io_restart_nic - Resets the NIC.
7003  * @data : long pointer to the device private structure
7004  * Description:
7005  * This function is scheduled to be run by the s2io_tx_watchdog
7006  * function after 0.5 secs to reset the NIC. The idea is to reduce
7007  * the run time of the watch dog routine which is run holding a
7008  * spin lock.
7009  */
7010
7011 static void s2io_restart_nic(struct work_struct *work)
7012 {
7013         struct s2io_nic *sp = container_of(work, struct s2io_nic, rst_timer_task);
7014         struct net_device *dev = sp->dev;
7015
7016         rtnl_lock();
7017
7018         if (!netif_running(dev))
7019                 goto out_unlock;
7020
7021         s2io_card_down(sp);
7022         if (s2io_card_up(sp)) {
7023                 DBG_PRINT(ERR_DBG, "%s: Device bring up failed\n",
7024                           dev->name);
7025         }
7026         netif_wake_queue(dev);
7027         DBG_PRINT(ERR_DBG, "%s: was reset by Tx watchdog timer\n",
7028                   dev->name);
7029 out_unlock:
7030         rtnl_unlock();
7031 }
7032
7033 /**
7034  *  s2io_tx_watchdog - Watchdog for transmit side.
7035  *  @dev : Pointer to net device structure
7036  *  Description:
7037  *  This function is triggered if the Tx Queue is stopped
7038  *  for a pre-defined amount of time when the Interface is still up.
7039  *  If the Interface is jammed in such a situation, the hardware is
7040  *  reset (by s2io_close) and restarted again (by s2io_open) to
7041  *  overcome any problem that might have been caused in the hardware.
7042  *  Return value:
7043  *  void
7044  */
7045
7046 static void s2io_tx_watchdog(struct net_device *dev)
7047 {
7048         struct s2io_nic *sp = dev->priv;
7049
7050         if (netif_carrier_ok(dev)) {
7051                 sp->mac_control.stats_info->sw_stat.watchdog_timer_cnt++;
7052                 schedule_work(&sp->rst_timer_task);
7053                 sp->mac_control.stats_info->sw_stat.soft_reset_cnt++;
7054         }
7055 }
7056
7057 /**
7058  *   rx_osm_handler - To perform some OS related operations on SKB.
7059  *   @sp: private member of the device structure,pointer to s2io_nic structure.
7060  *   @skb : the socket buffer pointer.
7061  *   @len : length of the packet
7062  *   @cksum : FCS checksum of the frame.
7063  *   @ring_no : the ring from which this RxD was extracted.
7064  *   Description:
7065  *   This function is called by the Rx interrupt serivce routine to perform
7066  *   some OS related operations on the SKB before passing it to the upper
7067  *   layers. It mainly checks if the checksum is OK, if so adds it to the
7068  *   SKBs cksum variable, increments the Rx packet count and passes the SKB
7069  *   to the upper layer. If the checksum is wrong, it increments the Rx
7070  *   packet error count, frees the SKB and returns error.
7071  *   Return value:
7072  *   SUCCESS on success and -1 on failure.
7073  */
7074 static int rx_osm_handler(struct ring_info *ring_data, struct RxD_t * rxdp)
7075 {
7076         struct s2io_nic *sp = ring_data->nic;
7077         struct net_device *dev = (struct net_device *) sp->dev;
7078         struct sk_buff *skb = (struct sk_buff *)
7079                 ((unsigned long) rxdp->Host_Control);
7080         int ring_no = ring_data->ring_no;
7081         u16 l3_csum, l4_csum;
7082         unsigned long long err = rxdp->Control_1 & RXD_T_CODE;
7083         struct lro *lro;
7084         u8 err_mask;
7085
7086         skb->dev = dev;
7087
7088         if (err) {
7089                 /* Check for parity error */
7090                 if (err & 0x1) {
7091                         sp->mac_control.stats_info->sw_stat.parity_err_cnt++;
7092                 }
7093                 err_mask = err >> 48;
7094                 switch(err_mask) {
7095                         case 1:
7096                                 sp->mac_control.stats_info->sw_stat.
7097                                 rx_parity_err_cnt++;
7098                         break;
7099
7100                         case 2:
7101                                 sp->mac_control.stats_info->sw_stat.
7102                                 rx_abort_cnt++;
7103                         break;
7104
7105                         case 3:
7106                                 sp->mac_control.stats_info->sw_stat.
7107                                 rx_parity_abort_cnt++;
7108                         break;
7109
7110                         case 4:
7111                                 sp->mac_control.stats_info->sw_stat.
7112                                 rx_rda_fail_cnt++;
7113                         break;
7114
7115                         case 5:
7116                                 sp->mac_control.stats_info->sw_stat.
7117                                 rx_unkn_prot_cnt++;
7118                         break;
7119
7120                         case 6:
7121                                 sp->mac_control.stats_info->sw_stat.
7122                                 rx_fcs_err_cnt++;
7123                         break;
7124
7125                         case 7:
7126                                 sp->mac_control.stats_info->sw_stat.
7127                                 rx_buf_size_err_cnt++;
7128                         break;
7129
7130                         case 8:
7131                                 sp->mac_control.stats_info->sw_stat.
7132                                 rx_rxd_corrupt_cnt++;
7133                         break;
7134
7135                         case 15:
7136                                 sp->mac_control.stats_info->sw_stat.
7137                                 rx_unkn_err_cnt++;
7138                         break;
7139                 }
7140                 /*
7141                 * Drop the packet if bad transfer code. Exception being
7142                 * 0x5, which could be due to unsupported IPv6 extension header.
7143                 * In this case, we let stack handle the packet.
7144                 * Note that in this case, since checksum will be incorrect,
7145                 * stack will validate the same.
7146                 */
7147                 if (err_mask != 0x5) {
7148                         DBG_PRINT(ERR_DBG, "%s: Rx error Value: 0x%x\n",
7149                                 dev->name, err_mask);
7150                         sp->stats.rx_crc_errors++;
7151                         sp->mac_control.stats_info->sw_stat.mem_freed
7152                                 += skb->truesize;
7153                         dev_kfree_skb(skb);
7154                         atomic_dec(&sp->rx_bufs_left[ring_no]);
7155                         rxdp->Host_Control = 0;
7156                         return 0;
7157                 }
7158         }
7159
7160         /* Updating statistics */
7161         sp->stats.rx_packets++;
7162         rxdp->Host_Control = 0;
7163         if (sp->rxd_mode == RXD_MODE_1) {
7164                 int len = RXD_GET_BUFFER0_SIZE_1(rxdp->Control_2);
7165
7166                 sp->stats.rx_bytes += len;
7167                 skb_put(skb, len);
7168
7169         } else if (sp->rxd_mode == RXD_MODE_3B) {
7170                 int get_block = ring_data->rx_curr_get_info.block_index;
7171                 int get_off = ring_data->rx_curr_get_info.offset;
7172                 int buf0_len = RXD_GET_BUFFER0_SIZE_3(rxdp->Control_2);
7173                 int buf2_len = RXD_GET_BUFFER2_SIZE_3(rxdp->Control_2);
7174                 unsigned char *buff = skb_push(skb, buf0_len);
7175
7176                 struct buffAdd *ba = &ring_data->ba[get_block][get_off];
7177                 sp->stats.rx_bytes += buf0_len + buf2_len;
7178                 memcpy(buff, ba->ba_0, buf0_len);
7179                 skb_put(skb, buf2_len);
7180         }
7181
7182         if ((rxdp->Control_1 & TCP_OR_UDP_FRAME) && ((!sp->lro) ||
7183             (sp->lro && (!(rxdp->Control_1 & RXD_FRAME_IP_FRAG)))) &&
7184             (sp->rx_csum)) {
7185                 l3_csum = RXD_GET_L3_CKSUM(rxdp->Control_1);
7186                 l4_csum = RXD_GET_L4_CKSUM(rxdp->Control_1);
7187                 if ((l3_csum == L3_CKSUM_OK) && (l4_csum == L4_CKSUM_OK)) {
7188                         /*
7189                          * NIC verifies if the Checksum of the received
7190                          * frame is Ok or not and accordingly returns
7191                          * a flag in the RxD.
7192                          */
7193                         skb->ip_summed = CHECKSUM_UNNECESSARY;
7194                         if (sp->lro) {
7195                                 u32 tcp_len;
7196                                 u8 *tcp;
7197                                 int ret = 0;
7198
7199                                 ret = s2io_club_tcp_session(skb->data, &tcp,
7200                                                 &tcp_len, &lro, rxdp, sp);
7201                                 switch (ret) {
7202                                         case 3: /* Begin anew */
7203                                                 lro->parent = skb;
7204                                                 goto aggregate;
7205                                         case 1: /* Aggregate */
7206                                         {
7207                                                 lro_append_pkt(sp, lro,
7208                                                         skb, tcp_len);
7209                                                 goto aggregate;
7210                                         }
7211                                         case 4: /* Flush session */
7212                                         {
7213                                                 lro_append_pkt(sp, lro,
7214                                                         skb, tcp_len);
7215                                                 queue_rx_frame(lro->parent);
7216                                                 clear_lro_session(lro);
7217                                                 sp->mac_control.stats_info->
7218                                                     sw_stat.flush_max_pkts++;
7219                                                 goto aggregate;
7220                                         }
7221                                         case 2: /* Flush both */
7222                                                 lro->parent->data_len =
7223                                                         lro->frags_len;
7224                                                 sp->mac_control.stats_info->
7225                                                      sw_stat.sending_both++;
7226                                                 queue_rx_frame(lro->parent);
7227                                                 clear_lro_session(lro);
7228                                                 goto send_up;
7229                                         case 0: /* sessions exceeded */
7230                                         case -1: /* non-TCP or not
7231                                                   * L2 aggregatable
7232                                                   */
7233                                         case 5: /*
7234                                                  * First pkt in session not
7235                                                  * L3/L4 aggregatable
7236                                                  */
7237                                                 break;
7238                                         default:
7239                                                 DBG_PRINT(ERR_DBG,
7240                                                         "%s: Samadhana!!\n",
7241                                                          __FUNCTION__);
7242                                                 BUG();
7243                                 }
7244                         }
7245                 } else {
7246                         /*
7247                          * Packet with erroneous checksum, let the
7248                          * upper layers deal with it.
7249                          */
7250                         skb->ip_summed = CHECKSUM_NONE;
7251                 }
7252         } else {
7253                 skb->ip_summed = CHECKSUM_NONE;
7254         }
7255         sp->mac_control.stats_info->sw_stat.mem_freed += skb->truesize;
7256         if (!sp->lro) {
7257                 skb->protocol = eth_type_trans(skb, dev);
7258                 if ((sp->vlgrp && RXD_GET_VLAN_TAG(rxdp->Control_2) &&
7259                         vlan_strip_flag)) {
7260                         /* Queueing the vlan frame to the upper layer */
7261                         if (napi)
7262                                 vlan_hwaccel_receive_skb(skb, sp->vlgrp,
7263                                         RXD_GET_VLAN_TAG(rxdp->Control_2));
7264                         else
7265                                 vlan_hwaccel_rx(skb, sp->vlgrp,
7266                                         RXD_GET_VLAN_TAG(rxdp->Control_2));
7267                 } else {
7268                         if (napi)
7269                                 netif_receive_skb(skb);
7270                         else
7271                                 netif_rx(skb);
7272                 }
7273         } else {
7274 send_up:
7275                 queue_rx_frame(skb);
7276         }
7277         dev->last_rx = jiffies;
7278 aggregate:
7279         atomic_dec(&sp->rx_bufs_left[ring_no]);
7280         return SUCCESS;
7281 }
7282
7283 /**
7284  *  s2io_link - stops/starts the Tx queue.
7285  *  @sp : private member of the device structure, which is a pointer to the
7286  *  s2io_nic structure.
7287  *  @link : inidicates whether link is UP/DOWN.
7288  *  Description:
7289  *  This function stops/starts the Tx queue depending on whether the link
7290  *  status of the NIC is is down or up. This is called by the Alarm
7291  *  interrupt handler whenever a link change interrupt comes up.
7292  *  Return value:
7293  *  void.
7294  */
7295
7296 static void s2io_link(struct s2io_nic * sp, int link)
7297 {
7298         struct net_device *dev = (struct net_device *) sp->dev;
7299
7300         if (link != sp->last_link_state) {
7301                 if (link == LINK_DOWN) {
7302                         DBG_PRINT(ERR_DBG, "%s: Link down\n", dev->name);
7303                         netif_carrier_off(dev);
7304                         if(sp->mac_control.stats_info->sw_stat.link_up_cnt)
7305                         sp->mac_control.stats_info->sw_stat.link_up_time =
7306                                 jiffies - sp->start_time;
7307                         sp->mac_control.stats_info->sw_stat.link_down_cnt++;
7308                 } else {
7309                         DBG_PRINT(ERR_DBG, "%s: Link Up\n", dev->name);
7310                         if (sp->mac_control.stats_info->sw_stat.link_down_cnt)
7311                         sp->mac_control.stats_info->sw_stat.link_down_time =
7312                                 jiffies - sp->start_time;
7313                         sp->mac_control.stats_info->sw_stat.link_up_cnt++;
7314                         netif_carrier_on(dev);
7315                 }
7316         }
7317         sp->last_link_state = link;
7318         sp->start_time = jiffies;
7319 }
7320
7321 /**
7322  *  s2io_init_pci -Initialization of PCI and PCI-X configuration registers .
7323  *  @sp : private member of the device structure, which is a pointer to the
7324  *  s2io_nic structure.
7325  *  Description:
7326  *  This function initializes a few of the PCI and PCI-X configuration registers
7327  *  with recommended values.
7328  *  Return value:
7329  *  void
7330  */
7331
7332 static void s2io_init_pci(struct s2io_nic * sp)
7333 {
7334         u16 pci_cmd = 0, pcix_cmd = 0;
7335
7336         /* Enable Data Parity Error Recovery in PCI-X command register. */
7337         pci_read_config_word(sp->pdev, PCIX_COMMAND_REGISTER,
7338                              &(pcix_cmd));
7339         pci_write_config_word(sp->pdev, PCIX_COMMAND_REGISTER,
7340                               (pcix_cmd | 1));
7341         pci_read_config_word(sp->pdev, PCIX_COMMAND_REGISTER,
7342                              &(pcix_cmd));
7343
7344         /* Set the PErr Response bit in PCI command register. */
7345         pci_read_config_word(sp->pdev, PCI_COMMAND, &pci_cmd);
7346         pci_write_config_word(sp->pdev, PCI_COMMAND,
7347                               (pci_cmd | PCI_COMMAND_PARITY));
7348         pci_read_config_word(sp->pdev, PCI_COMMAND, &pci_cmd);
7349 }
7350
7351 static int s2io_verify_parm(struct pci_dev *pdev, u8 *dev_intr_type)
7352 {
7353         if ( tx_fifo_num > 8) {
7354                 DBG_PRINT(ERR_DBG, "s2io: Requested number of Tx fifos not "
7355                          "supported\n");
7356                 DBG_PRINT(ERR_DBG, "s2io: Default to 8 Tx fifos\n");
7357                 tx_fifo_num = 8;
7358         }
7359         if ( rx_ring_num > 8) {
7360                 DBG_PRINT(ERR_DBG, "s2io: Requested number of Rx rings not "
7361                          "supported\n");
7362                 DBG_PRINT(ERR_DBG, "s2io: Default to 8 Rx rings\n");
7363                 rx_ring_num = 8;
7364         }
7365         if (*dev_intr_type != INTA)
7366                 napi = 0;
7367
7368 #ifndef CONFIG_PCI_MSI
7369         if (*dev_intr_type != INTA) {
7370                 DBG_PRINT(ERR_DBG, "s2io: This kernel does not support"
7371                           "MSI/MSI-X. Defaulting to INTA\n");
7372                 *dev_intr_type = INTA;
7373         }
7374 #else
7375         if ((*dev_intr_type != INTA) && (*dev_intr_type != MSI_X)) {
7376                 DBG_PRINT(ERR_DBG, "s2io: Wrong intr_type requested. "
7377                           "Defaulting to INTA\n");
7378                 *dev_intr_type = INTA;
7379         }
7380 #endif
7381         if ((*dev_intr_type == MSI_X) &&
7382                         ((pdev->device != PCI_DEVICE_ID_HERC_WIN) &&
7383                         (pdev->device != PCI_DEVICE_ID_HERC_UNI))) {
7384                 DBG_PRINT(ERR_DBG, "s2io: Xframe I does not support MSI_X. "
7385                                         "Defaulting to INTA\n");
7386                 *dev_intr_type = INTA;
7387         }
7388
7389         if ((rx_ring_mode != 1) && (rx_ring_mode != 2)) {
7390                 DBG_PRINT(ERR_DBG, "s2io: Requested ring mode not supported\n");
7391                 DBG_PRINT(ERR_DBG, "s2io: Defaulting to 1-buffer mode\n");
7392                 rx_ring_mode = 1;
7393         }
7394         return SUCCESS;
7395 }
7396
7397 /**
7398  * rts_ds_steer - Receive traffic steering based on IPv4 or IPv6 TOS
7399  * or Traffic class respectively.
7400  * @nic: device peivate variable
7401  * Description: The function configures the receive steering to
7402  * desired receive ring.
7403  * Return Value:  SUCCESS on success and
7404  * '-1' on failure (endian settings incorrect).
7405  */
7406 static int rts_ds_steer(struct s2io_nic *nic, u8 ds_codepoint, u8 ring)
7407 {
7408         struct XENA_dev_config __iomem *bar0 = nic->bar0;
7409         register u64 val64 = 0;
7410
7411         if (ds_codepoint > 63)
7412                 return FAILURE;
7413
7414         val64 = RTS_DS_MEM_DATA(ring);
7415         writeq(val64, &bar0->rts_ds_mem_data);
7416
7417         val64 = RTS_DS_MEM_CTRL_WE |
7418                 RTS_DS_MEM_CTRL_STROBE_NEW_CMD |
7419                 RTS_DS_MEM_CTRL_OFFSET(ds_codepoint);
7420
7421         writeq(val64, &bar0->rts_ds_mem_ctrl);
7422
7423         return wait_for_cmd_complete(&bar0->rts_ds_mem_ctrl,
7424                                 RTS_DS_MEM_CTRL_STROBE_CMD_BEING_EXECUTED,
7425                                 S2IO_BIT_RESET);
7426 }
7427
7428 /**
7429  *  s2io_init_nic - Initialization of the adapter .
7430  *  @pdev : structure containing the PCI related information of the device.
7431  *  @pre: List of PCI devices supported by the driver listed in s2io_tbl.
7432  *  Description:
7433  *  The function initializes an adapter identified by the pci_dec structure.
7434  *  All OS related initialization including memory and device structure and
7435  *  initlaization of the device private variable is done. Also the swapper
7436  *  control register is initialized to enable read and write into the I/O
7437  *  registers of the device.
7438  *  Return value:
7439  *  returns 0 on success and negative on failure.
7440  */
7441
7442 static int __devinit
7443 s2io_init_nic(struct pci_dev *pdev, const struct pci_device_id *pre)
7444 {
7445         struct s2io_nic *sp;
7446         struct net_device *dev;
7447         int i, j, ret;
7448         int dma_flag = FALSE;
7449         u32 mac_up, mac_down;
7450         u64 val64 = 0, tmp64 = 0;
7451         struct XENA_dev_config __iomem *bar0 = NULL;
7452         u16 subid;
7453         struct mac_info *mac_control;
7454         struct config_param *config;
7455         int mode;
7456         u8 dev_intr_type = intr_type;
7457
7458         if ((ret = s2io_verify_parm(pdev, &dev_intr_type)))
7459                 return ret;
7460
7461         if ((ret = pci_enable_device(pdev))) {
7462                 DBG_PRINT(ERR_DBG,
7463                           "s2io_init_nic: pci_enable_device failed\n");
7464                 return ret;
7465         }
7466
7467         if (!pci_set_dma_mask(pdev, DMA_64BIT_MASK)) {
7468                 DBG_PRINT(INIT_DBG, "s2io_init_nic: Using 64bit DMA\n");
7469                 dma_flag = TRUE;
7470                 if (pci_set_consistent_dma_mask
7471                     (pdev, DMA_64BIT_MASK)) {
7472                         DBG_PRINT(ERR_DBG,
7473                                   "Unable to obtain 64bit DMA for \
7474                                         consistent allocations\n");
7475                         pci_disable_device(pdev);
7476                         return -ENOMEM;
7477                 }
7478         } else if (!pci_set_dma_mask(pdev, DMA_32BIT_MASK)) {
7479                 DBG_PRINT(INIT_DBG, "s2io_init_nic: Using 32bit DMA\n");
7480         } else {
7481                 pci_disable_device(pdev);
7482                 return -ENOMEM;
7483         }
7484         if ((ret = pci_request_regions(pdev, s2io_driver_name))) {
7485                 DBG_PRINT(ERR_DBG, "%s: Request Regions failed - %x \n", __FUNCTION__, ret);
7486                 pci_disable_device(pdev);
7487                 return -ENODEV;
7488         }
7489
7490         dev = alloc_etherdev(sizeof(struct s2io_nic));
7491         if (dev == NULL) {
7492                 DBG_PRINT(ERR_DBG, "Device allocation failed\n");
7493                 pci_disable_device(pdev);
7494                 pci_release_regions(pdev);
7495                 return -ENODEV;
7496         }
7497
7498         pci_set_master(pdev);
7499         pci_set_drvdata(pdev, dev);
7500         SET_MODULE_OWNER(dev);
7501         SET_NETDEV_DEV(dev, &pdev->dev);
7502
7503         /*  Private member variable initialized to s2io NIC structure */
7504         sp = dev->priv;
7505         memset(sp, 0, sizeof(struct s2io_nic));
7506         sp->dev = dev;
7507         sp->pdev = pdev;
7508         sp->high_dma_flag = dma_flag;
7509         sp->device_enabled_once = FALSE;
7510         if (rx_ring_mode == 1)
7511                 sp->rxd_mode = RXD_MODE_1;
7512         if (rx_ring_mode == 2)
7513                 sp->rxd_mode = RXD_MODE_3B;
7514
7515         sp->config.intr_type = dev_intr_type;
7516
7517         if ((pdev->device == PCI_DEVICE_ID_HERC_WIN) ||
7518                 (pdev->device == PCI_DEVICE_ID_HERC_UNI))
7519                 sp->device_type = XFRAME_II_DEVICE;
7520         else
7521                 sp->device_type = XFRAME_I_DEVICE;
7522
7523         sp->lro = lro;
7524
7525         /* Initialize some PCI/PCI-X fields of the NIC. */
7526         s2io_init_pci(sp);
7527
7528         /*
7529          * Setting the device configuration parameters.
7530          * Most of these parameters can be specified by the user during
7531          * module insertion as they are module loadable parameters. If
7532          * these parameters are not not specified during load time, they
7533          * are initialized with default values.
7534          */
7535         mac_control = &sp->mac_control;
7536         config = &sp->config;
7537
7538         /* Tx side parameters. */
7539         config->tx_fifo_num = tx_fifo_num;
7540         for (i = 0; i < MAX_TX_FIFOS; i++) {
7541                 config->tx_cfg[i].fifo_len = tx_fifo_len[i];
7542                 config->tx_cfg[i].fifo_priority = i;
7543         }
7544
7545         /* mapping the QoS priority to the configured fifos */
7546         for (i = 0; i < MAX_TX_FIFOS; i++)
7547                 config->fifo_mapping[i] = fifo_map[config->tx_fifo_num][i];
7548
7549         config->tx_intr_type = TXD_INT_TYPE_UTILZ;
7550         for (i = 0; i < config->tx_fifo_num; i++) {
7551                 config->tx_cfg[i].f_no_snoop =
7552                     (NO_SNOOP_TXD | NO_SNOOP_TXD_BUFFER);
7553                 if (config->tx_cfg[i].fifo_len < 65) {
7554                         config->tx_intr_type = TXD_INT_TYPE_PER_LIST;
7555                         break;
7556                 }
7557         }
7558         /* + 2 because one Txd for skb->data and one Txd for UFO */
7559         config->max_txds = MAX_SKB_FRAGS + 2;
7560
7561         /* Rx side parameters. */
7562         config->rx_ring_num = rx_ring_num;
7563         for (i = 0; i < MAX_RX_RINGS; i++) {
7564                 config->rx_cfg[i].num_rxd = rx_ring_sz[i] *
7565                     (rxd_count[sp->rxd_mode] + 1);
7566                 config->rx_cfg[i].ring_priority = i;
7567         }
7568
7569         for (i = 0; i < rx_ring_num; i++) {
7570                 config->rx_cfg[i].ring_org = RING_ORG_BUFF1;
7571                 config->rx_cfg[i].f_no_snoop =
7572                     (NO_SNOOP_RXD | NO_SNOOP_RXD_BUFFER);
7573         }
7574
7575         /*  Setting Mac Control parameters */
7576         mac_control->rmac_pause_time = rmac_pause_time;
7577         mac_control->mc_pause_threshold_q0q3 = mc_pause_threshold_q0q3;
7578         mac_control->mc_pause_threshold_q4q7 = mc_pause_threshold_q4q7;
7579
7580
7581         /* Initialize Ring buffer parameters. */
7582         for (i = 0; i < config->rx_ring_num; i++)
7583                 atomic_set(&sp->rx_bufs_left[i], 0);
7584
7585         /* Initialize the number of ISRs currently running */
7586         atomic_set(&sp->isr_cnt, 0);
7587
7588         /*  initialize the shared memory used by the NIC and the host */
7589         if (init_shared_mem(sp)) {
7590                 DBG_PRINT(ERR_DBG, "%s: Memory allocation failed\n",
7591                           dev->name);
7592                 ret = -ENOMEM;
7593                 goto mem_alloc_failed;
7594         }
7595
7596         sp->bar0 = ioremap(pci_resource_start(pdev, 0),
7597                                      pci_resource_len(pdev, 0));
7598         if (!sp->bar0) {
7599                 DBG_PRINT(ERR_DBG, "%s: Neterion: cannot remap io mem1\n",
7600                           dev->name);
7601                 ret = -ENOMEM;
7602                 goto bar0_remap_failed;
7603         }
7604
7605         sp->bar1 = ioremap(pci_resource_start(pdev, 2),
7606                                      pci_resource_len(pdev, 2));
7607         if (!sp->bar1) {
7608                 DBG_PRINT(ERR_DBG, "%s: Neterion: cannot remap io mem2\n",
7609                           dev->name);
7610                 ret = -ENOMEM;
7611                 goto bar1_remap_failed;
7612         }
7613
7614         dev->irq = pdev->irq;
7615         dev->base_addr = (unsigned long) sp->bar0;
7616
7617         /* Initializing the BAR1 address as the start of the FIFO pointer. */
7618         for (j = 0; j < MAX_TX_FIFOS; j++) {
7619                 mac_control->tx_FIFO_start[j] = (struct TxFIFO_element __iomem *)
7620                     (sp->bar1 + (j * 0x00020000));
7621         }
7622
7623         /*  Driver entry points */
7624         dev->open = &s2io_open;
7625         dev->stop = &s2io_close;
7626         dev->hard_start_xmit = &s2io_xmit;
7627         dev->get_stats = &s2io_get_stats;
7628         dev->set_multicast_list = &s2io_set_multicast;
7629         dev->do_ioctl = &s2io_ioctl;
7630         dev->change_mtu = &s2io_change_mtu;
7631         SET_ETHTOOL_OPS(dev, &netdev_ethtool_ops);
7632         dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
7633         dev->vlan_rx_register = s2io_vlan_rx_register;
7634
7635         /*
7636          * will use eth_mac_addr() for  dev->set_mac_address
7637          * mac address will be set every time dev->open() is called
7638          */
7639         netif_napi_add(dev, &sp->napi, s2io_poll, 32);
7640
7641 #ifdef CONFIG_NET_POLL_CONTROLLER
7642         dev->poll_controller = s2io_netpoll;
7643 #endif
7644
7645         dev->features |= NETIF_F_SG | NETIF_F_IP_CSUM;
7646         if (sp->high_dma_flag == TRUE)
7647                 dev->features |= NETIF_F_HIGHDMA;
7648         dev->features |= NETIF_F_TSO;
7649         dev->features |= NETIF_F_TSO6;
7650         if ((sp->device_type & XFRAME_II_DEVICE) && (ufo))  {
7651                 dev->features |= NETIF_F_UFO;
7652                 dev->features |= NETIF_F_HW_CSUM;
7653         }
7654
7655         dev->tx_timeout = &s2io_tx_watchdog;
7656         dev->watchdog_timeo = WATCH_DOG_TIMEOUT;
7657         INIT_WORK(&sp->rst_timer_task, s2io_restart_nic);
7658         INIT_WORK(&sp->set_link_task, s2io_set_link);
7659
7660         pci_save_state(sp->pdev);
7661
7662         /* Setting swapper control on the NIC, for proper reset operation */
7663         if (s2io_set_swapper(sp)) {
7664                 DBG_PRINT(ERR_DBG, "%s:swapper settings are wrong\n",
7665                           dev->name);
7666                 ret = -EAGAIN;
7667                 goto set_swap_failed;
7668         }
7669
7670         /* Verify if the Herc works on the slot its placed into */
7671         if (sp->device_type & XFRAME_II_DEVICE) {
7672                 mode = s2io_verify_pci_mode(sp);
7673                 if (mode < 0) {
7674                         DBG_PRINT(ERR_DBG, "%s: ", __FUNCTION__);
7675                         DBG_PRINT(ERR_DBG, " Unsupported PCI bus mode\n");
7676                         ret = -EBADSLT;
7677                         goto set_swap_failed;
7678                 }
7679         }
7680
7681         /* Not needed for Herc */
7682         if (sp->device_type & XFRAME_I_DEVICE) {
7683                 /*
7684                  * Fix for all "FFs" MAC address problems observed on
7685                  * Alpha platforms
7686                  */
7687                 fix_mac_address(sp);
7688                 s2io_reset(sp);
7689         }
7690
7691         /*
7692          * MAC address initialization.
7693          * For now only one mac address will be read and used.
7694          */
7695         bar0 = sp->bar0;
7696         val64 = RMAC_ADDR_CMD_MEM_RD | RMAC_ADDR_CMD_MEM_STROBE_NEW_CMD |
7697             RMAC_ADDR_CMD_MEM_OFFSET(0 + MAC_MAC_ADDR_START_OFFSET);
7698         writeq(val64, &bar0->rmac_addr_cmd_mem);
7699         wait_for_cmd_complete(&bar0->rmac_addr_cmd_mem,
7700                       RMAC_ADDR_CMD_MEM_STROBE_CMD_EXECUTING, S2IO_BIT_RESET);
7701         tmp64 = readq(&bar0->rmac_addr_data0_mem);
7702         mac_down = (u32) tmp64;
7703         mac_up = (u32) (tmp64 >> 32);
7704
7705         sp->def_mac_addr[0].mac_addr[3] = (u8) (mac_up);
7706         sp->def_mac_addr[0].mac_addr[2] = (u8) (mac_up >> 8);
7707         sp->def_mac_addr[0].mac_addr[1] = (u8) (mac_up >> 16);
7708         sp->def_mac_addr[0].mac_addr[0] = (u8) (mac_up >> 24);
7709         sp->def_mac_addr[0].mac_addr[5] = (u8) (mac_down >> 16);
7710         sp->def_mac_addr[0].mac_addr[4] = (u8) (mac_down >> 24);
7711
7712         /*  Set the factory defined MAC address initially   */
7713         dev->addr_len = ETH_ALEN;
7714         memcpy(dev->dev_addr, sp->def_mac_addr, ETH_ALEN);
7715
7716          /* Store the values of the MSIX table in the s2io_nic structure */
7717         store_xmsi_data(sp);
7718         /* reset Nic and bring it to known state */
7719         s2io_reset(sp);
7720
7721         /*
7722          * Initialize the tasklet status and link state flags
7723          * and the card state parameter
7724          */
7725         sp->tasklet_status = 0;
7726         sp->state = 0;
7727
7728         /* Initialize spinlocks */
7729         spin_lock_init(&sp->tx_lock);
7730
7731         if (!napi)
7732                 spin_lock_init(&sp->put_lock);
7733         spin_lock_init(&sp->rx_lock);
7734
7735         /*
7736          * SXE-002: Configure link and activity LED to init state
7737          * on driver load.
7738          */
7739         subid = sp->pdev->subsystem_device;
7740         if ((subid & 0xFF) >= 0x07) {
7741                 val64 = readq(&bar0->gpio_control);
7742                 val64 |= 0x0000800000000000ULL;
7743                 writeq(val64, &bar0->gpio_control);
7744                 val64 = 0x0411040400000000ULL;
7745                 writeq(val64, (void __iomem *) bar0 + 0x2700);
7746                 val64 = readq(&bar0->gpio_control);
7747         }
7748
7749         sp->rx_csum = 1;        /* Rx chksum verify enabled by default */
7750
7751         if (register_netdev(dev)) {
7752                 DBG_PRINT(ERR_DBG, "Device registration failed\n");
7753                 ret = -ENODEV;
7754                 goto register_failed;
7755         }
7756         s2io_vpd_read(sp);
7757         DBG_PRINT(ERR_DBG, "Copyright(c) 2002-2007 Neterion Inc.\n");
7758         DBG_PRINT(ERR_DBG, "%s: Neterion %s (rev %d)\n",dev->name,
7759                   sp->product_name, pdev->revision);
7760         DBG_PRINT(ERR_DBG, "%s: Driver version %s\n", dev->name,
7761                   s2io_driver_version);
7762         DBG_PRINT(ERR_DBG, "%s: MAC ADDR: "
7763                           "%02x:%02x:%02x:%02x:%02x:%02x", dev->name,
7764                           sp->def_mac_addr[0].mac_addr[0],
7765                           sp->def_mac_addr[0].mac_addr[1],
7766                           sp->def_mac_addr[0].mac_addr[2],
7767                           sp->def_mac_addr[0].mac_addr[3],
7768                           sp->def_mac_addr[0].mac_addr[4],
7769                           sp->def_mac_addr[0].mac_addr[5]);
7770         DBG_PRINT(ERR_DBG, "SERIAL NUMBER: %s\n", sp->serial_num);
7771         if (sp->device_type & XFRAME_II_DEVICE) {
7772                 mode = s2io_print_pci_mode(sp);
7773                 if (mode < 0) {
7774                         DBG_PRINT(ERR_DBG, " Unsupported PCI bus mode\n");
7775                         ret = -EBADSLT;
7776                         unregister_netdev(dev);
7777                         goto set_swap_failed;
7778                 }
7779         }
7780         switch(sp->rxd_mode) {
7781                 case RXD_MODE_1:
7782                     DBG_PRINT(ERR_DBG, "%s: 1-Buffer receive mode enabled\n",
7783                                                 dev->name);
7784                     break;
7785                 case RXD_MODE_3B:
7786                     DBG_PRINT(ERR_DBG, "%s: 2-Buffer receive mode enabled\n",
7787                                                 dev->name);
7788                     break;
7789         }
7790
7791         if (napi)
7792                 DBG_PRINT(ERR_DBG, "%s: NAPI enabled\n", dev->name);
7793         switch(sp->config.intr_type) {
7794                 case INTA:
7795                     DBG_PRINT(ERR_DBG, "%s: Interrupt type INTA\n", dev->name);
7796                     break;
7797                 case MSI_X:
7798                     DBG_PRINT(ERR_DBG, "%s: Interrupt type MSI-X\n", dev->name);
7799                     break;
7800         }
7801         if (sp->lro)
7802                 DBG_PRINT(ERR_DBG, "%s: Large receive offload enabled\n",
7803                           dev->name);
7804         if (ufo)
7805                 DBG_PRINT(ERR_DBG, "%s: UDP Fragmentation Offload(UFO)"
7806                                         " enabled\n", dev->name);
7807         /* Initialize device name */
7808         sprintf(sp->name, "%s Neterion %s", dev->name, sp->product_name);
7809
7810         /* Initialize bimodal Interrupts */
7811         sp->config.bimodal = bimodal;
7812         if (!(sp->device_type & XFRAME_II_DEVICE) && bimodal) {
7813                 sp->config.bimodal = 0;
7814                 DBG_PRINT(ERR_DBG,"%s:Bimodal intr not supported by Xframe I\n",
7815                         dev->name);
7816         }
7817
7818         /*
7819          * Make Link state as off at this point, when the Link change
7820          * interrupt comes the state will be automatically changed to
7821          * the right state.
7822          */
7823         netif_carrier_off(dev);
7824
7825         return 0;
7826
7827       register_failed:
7828       set_swap_failed:
7829         iounmap(sp->bar1);
7830       bar1_remap_failed:
7831         iounmap(sp->bar0);
7832       bar0_remap_failed:
7833       mem_alloc_failed:
7834         free_shared_mem(sp);
7835         pci_disable_device(pdev);
7836         pci_release_regions(pdev);
7837         pci_set_drvdata(pdev, NULL);
7838         free_netdev(dev);
7839
7840         return ret;
7841 }
7842
7843 /**
7844  * s2io_rem_nic - Free the PCI device
7845  * @pdev: structure containing the PCI related information of the device.
7846  * Description: This function is called by the Pci subsystem to release a
7847  * PCI device and free up all resource held up by the device. This could
7848  * be in response to a Hot plug event or when the driver is to be removed
7849  * from memory.
7850  */
7851
7852 static void __devexit s2io_rem_nic(struct pci_dev *pdev)
7853 {
7854         struct net_device *dev =
7855             (struct net_device *) pci_get_drvdata(pdev);
7856         struct s2io_nic *sp;
7857
7858         if (dev == NULL) {
7859                 DBG_PRINT(ERR_DBG, "Driver Data is NULL!!\n");
7860                 return;
7861         }
7862
7863         flush_scheduled_work();
7864
7865         sp = dev->priv;
7866         unregister_netdev(dev);
7867
7868         free_shared_mem(sp);
7869         iounmap(sp->bar0);
7870         iounmap(sp->bar1);
7871         pci_release_regions(pdev);
7872         pci_set_drvdata(pdev, NULL);
7873         free_netdev(dev);
7874         pci_disable_device(pdev);
7875 }
7876
7877 /**
7878  * s2io_starter - Entry point for the driver
7879  * Description: This function is the entry point for the driver. It verifies
7880  * the module loadable parameters and initializes PCI configuration space.
7881  */
7882
7883 int __init s2io_starter(void)
7884 {
7885         return pci_register_driver(&s2io_driver);
7886 }
7887
7888 /**
7889  * s2io_closer - Cleanup routine for the driver
7890  * Description: This function is the cleanup routine for the driver. It unregist * ers the driver.
7891  */
7892
7893 static __exit void s2io_closer(void)
7894 {
7895         pci_unregister_driver(&s2io_driver);
7896         DBG_PRINT(INIT_DBG, "cleanup done\n");
7897 }
7898
7899 module_init(s2io_starter);
7900 module_exit(s2io_closer);
7901
7902 static int check_L2_lro_capable(u8 *buffer, struct iphdr **ip,
7903                 struct tcphdr **tcp, struct RxD_t *rxdp)
7904 {
7905         int ip_off;
7906         u8 l2_type = (u8)((rxdp->Control_1 >> 37) & 0x7), ip_len;
7907
7908         if (!(rxdp->Control_1 & RXD_FRAME_PROTO_TCP)) {
7909                 DBG_PRINT(INIT_DBG,"%s: Non-TCP frames not supported for LRO\n",
7910                           __FUNCTION__);
7911                 return -1;
7912         }
7913
7914         /* TODO:
7915          * By default the VLAN field in the MAC is stripped by the card, if this
7916          * feature is turned off in rx_pa_cfg register, then the ip_off field
7917          * has to be shifted by a further 2 bytes
7918          */
7919         switch (l2_type) {
7920                 case 0: /* DIX type */
7921                 case 4: /* DIX type with VLAN */
7922                         ip_off = HEADER_ETHERNET_II_802_3_SIZE;
7923                         break;
7924                 /* LLC, SNAP etc are considered non-mergeable */
7925                 default:
7926                         return -1;
7927         }
7928
7929         *ip = (struct iphdr *)((u8 *)buffer + ip_off);
7930         ip_len = (u8)((*ip)->ihl);
7931         ip_len <<= 2;
7932         *tcp = (struct tcphdr *)((unsigned long)*ip + ip_len);
7933
7934         return 0;
7935 }
7936
7937 static int check_for_socket_match(struct lro *lro, struct iphdr *ip,
7938                                   struct tcphdr *tcp)
7939 {
7940         DBG_PRINT(INFO_DBG,"%s: Been here...\n", __FUNCTION__);
7941         if ((lro->iph->saddr != ip->saddr) || (lro->iph->daddr != ip->daddr) ||
7942            (lro->tcph->source != tcp->source) || (lro->tcph->dest != tcp->dest))
7943                 return -1;
7944         return 0;
7945 }
7946
7947 static inline int get_l4_pyld_length(struct iphdr *ip, struct tcphdr *tcp)
7948 {
7949         return(ntohs(ip->tot_len) - (ip->ihl << 2) - (tcp->doff << 2));
7950 }
7951
7952 static void initiate_new_session(struct lro *lro, u8 *l2h,
7953                      struct iphdr *ip, struct tcphdr *tcp, u32 tcp_pyld_len)
7954 {
7955         DBG_PRINT(INFO_DBG,"%s: Been here...\n", __FUNCTION__);
7956         lro->l2h = l2h;
7957         lro->iph = ip;
7958         lro->tcph = tcp;
7959         lro->tcp_next_seq = tcp_pyld_len + ntohl(tcp->seq);
7960         lro->tcp_ack = ntohl(tcp->ack_seq);
7961         lro->sg_num = 1;
7962         lro->total_len = ntohs(ip->tot_len);
7963         lro->frags_len = 0;
7964         /*
7965          * check if we saw TCP timestamp. Other consistency checks have
7966          * already been done.
7967          */
7968         if (tcp->doff == 8) {
7969                 u32 *ptr;
7970                 ptr = (u32 *)(tcp+1);
7971                 lro->saw_ts = 1;
7972                 lro->cur_tsval = *(ptr+1);
7973                 lro->cur_tsecr = *(ptr+2);
7974         }
7975         lro->in_use = 1;
7976 }
7977
7978 static void update_L3L4_header(struct s2io_nic *sp, struct lro *lro)
7979 {
7980         struct iphdr *ip = lro->iph;
7981         struct tcphdr *tcp = lro->tcph;
7982         __sum16 nchk;
7983         struct stat_block *statinfo = sp->mac_control.stats_info;
7984         DBG_PRINT(INFO_DBG,"%s: Been here...\n", __FUNCTION__);
7985
7986         /* Update L3 header */
7987         ip->tot_len = htons(lro->total_len);
7988         ip->check = 0;
7989         nchk = ip_fast_csum((u8 *)lro->iph, ip->ihl);
7990         ip->check = nchk;
7991
7992         /* Update L4 header */
7993         tcp->ack_seq = lro->tcp_ack;
7994         tcp->window = lro->window;
7995
7996         /* Update tsecr field if this session has timestamps enabled */
7997         if (lro->saw_ts) {
7998                 u32 *ptr = (u32 *)(tcp + 1);
7999                 *(ptr+2) = lro->cur_tsecr;
8000         }
8001
8002         /* Update counters required for calculation of
8003          * average no. of packets aggregated.
8004          */
8005         statinfo->sw_stat.sum_avg_pkts_aggregated += lro->sg_num;
8006         statinfo->sw_stat.num_aggregations++;
8007 }
8008
8009 static void aggregate_new_rx(struct lro *lro, struct iphdr *ip,
8010                 struct tcphdr *tcp, u32 l4_pyld)
8011 {
8012         DBG_PRINT(INFO_DBG,"%s: Been here...\n", __FUNCTION__);
8013         lro->total_len += l4_pyld;
8014         lro->frags_len += l4_pyld;
8015         lro->tcp_next_seq += l4_pyld;
8016         lro->sg_num++;
8017
8018         /* Update ack seq no. and window ad(from this pkt) in LRO object */
8019         lro->tcp_ack = tcp->ack_seq;
8020         lro->window = tcp->window;
8021
8022         if (lro->saw_ts) {
8023                 u32 *ptr;
8024                 /* Update tsecr and tsval from this packet */
8025                 ptr = (u32 *) (tcp + 1);
8026                 lro->cur_tsval = *(ptr + 1);
8027                 lro->cur_tsecr = *(ptr + 2);
8028         }
8029 }
8030
8031 static int verify_l3_l4_lro_capable(struct lro *l_lro, struct iphdr *ip,
8032                                     struct tcphdr *tcp, u32 tcp_pyld_len)
8033 {
8034         u8 *ptr;
8035
8036         DBG_PRINT(INFO_DBG,"%s: Been here...\n", __FUNCTION__);
8037
8038         if (!tcp_pyld_len) {
8039                 /* Runt frame or a pure ack */
8040                 return -1;
8041         }
8042
8043         if (ip->ihl != 5) /* IP has options */
8044                 return -1;
8045
8046         /* If we see CE codepoint in IP header, packet is not mergeable */
8047         if (INET_ECN_is_ce(ipv4_get_dsfield(ip)))
8048                 return -1;
8049
8050         /* If we see ECE or CWR flags in TCP header, packet is not mergeable */
8051         if (tcp->urg || tcp->psh || tcp->rst || tcp->syn || tcp->fin ||
8052                                     tcp->ece || tcp->cwr || !tcp->ack) {
8053                 /*
8054                  * Currently recognize only the ack control word and
8055                  * any other control field being set would result in
8056                  * flushing the LRO session
8057                  */
8058                 return -1;
8059         }
8060
8061         /*
8062          * Allow only one TCP timestamp option. Don't aggregate if
8063          * any other options are detected.
8064          */
8065         if (tcp->doff != 5 && tcp->doff != 8)
8066                 return -1;
8067
8068         if (tcp->doff == 8) {
8069                 ptr = (u8 *)(tcp + 1);
8070                 while (*ptr == TCPOPT_NOP)
8071                         ptr++;
8072                 if (*ptr != TCPOPT_TIMESTAMP || *(ptr+1) != TCPOLEN_TIMESTAMP)
8073                         return -1;
8074
8075                 /* Ensure timestamp value increases monotonically */
8076                 if (l_lro)
8077                         if (l_lro->cur_tsval > *((u32 *)(ptr+2)))
8078                                 return -1;
8079
8080                 /* timestamp echo reply should be non-zero */
8081                 if (*((u32 *)(ptr+6)) == 0)
8082                         return -1;
8083         }
8084
8085         return 0;
8086 }
8087
8088 static int
8089 s2io_club_tcp_session(u8 *buffer, u8 **tcp, u32 *tcp_len, struct lro **lro,
8090                       struct RxD_t *rxdp, struct s2io_nic *sp)
8091 {
8092         struct iphdr *ip;
8093         struct tcphdr *tcph;
8094         int ret = 0, i;
8095
8096         if (!(ret = check_L2_lro_capable(buffer, &ip, (struct tcphdr **)tcp,
8097                                          rxdp))) {
8098                 DBG_PRINT(INFO_DBG,"IP Saddr: %x Daddr: %x\n",
8099                           ip->saddr, ip->daddr);
8100         } else {
8101                 return ret;
8102         }
8103
8104         tcph = (struct tcphdr *)*tcp;
8105         *tcp_len = get_l4_pyld_length(ip, tcph);
8106         for (i=0; i<MAX_LRO_SESSIONS; i++) {
8107                 struct lro *l_lro = &sp->lro0_n[i];
8108                 if (l_lro->in_use) {
8109                         if (check_for_socket_match(l_lro, ip, tcph))
8110                                 continue;
8111                         /* Sock pair matched */
8112                         *lro = l_lro;
8113
8114                         if ((*lro)->tcp_next_seq != ntohl(tcph->seq)) {
8115                                 DBG_PRINT(INFO_DBG, "%s:Out of order. expected "
8116                                           "0x%x, actual 0x%x\n", __FUNCTION__,
8117                                           (*lro)->tcp_next_seq,
8118                                           ntohl(tcph->seq));
8119
8120                                 sp->mac_control.stats_info->
8121                                    sw_stat.outof_sequence_pkts++;
8122                                 ret = 2;
8123                                 break;
8124                         }
8125
8126                         if (!verify_l3_l4_lro_capable(l_lro, ip, tcph,*tcp_len))
8127                                 ret = 1; /* Aggregate */
8128                         else
8129                                 ret = 2; /* Flush both */
8130                         break;
8131                 }
8132         }
8133
8134         if (ret == 0) {
8135                 /* Before searching for available LRO objects,
8136                  * check if the pkt is L3/L4 aggregatable. If not
8137                  * don't create new LRO session. Just send this
8138                  * packet up.
8139                  */
8140                 if (verify_l3_l4_lro_capable(NULL, ip, tcph, *tcp_len)) {
8141                         return 5;
8142                 }
8143
8144                 for (i=0; i<MAX_LRO_SESSIONS; i++) {
8145                         struct lro *l_lro = &sp->lro0_n[i];
8146                         if (!(l_lro->in_use)) {
8147                                 *lro = l_lro;
8148                                 ret = 3; /* Begin anew */
8149                                 break;
8150                         }
8151                 }
8152         }
8153
8154         if (ret == 0) { /* sessions exceeded */
8155                 DBG_PRINT(INFO_DBG,"%s:All LRO sessions already in use\n",
8156                           __FUNCTION__);
8157                 *lro = NULL;
8158                 return ret;
8159         }
8160
8161         switch (ret) {
8162                 case 3:
8163                         initiate_new_session(*lro, buffer, ip, tcph, *tcp_len);
8164                         break;
8165                 case 2:
8166                         update_L3L4_header(sp, *lro);
8167                         break;
8168                 case 1:
8169                         aggregate_new_rx(*lro, ip, tcph, *tcp_len);
8170                         if ((*lro)->sg_num == sp->lro_max_aggr_per_sess) {
8171                                 update_L3L4_header(sp, *lro);
8172                                 ret = 4; /* Flush the LRO */
8173                         }
8174                         break;
8175                 default:
8176                         DBG_PRINT(ERR_DBG,"%s:Dont know, can't say!!\n",
8177                                 __FUNCTION__);
8178                         break;
8179         }
8180
8181         return ret;
8182 }
8183
8184 static void clear_lro_session(struct lro *lro)
8185 {
8186         static u16 lro_struct_size = sizeof(struct lro);
8187
8188         memset(lro, 0, lro_struct_size);
8189 }
8190
8191 static void queue_rx_frame(struct sk_buff *skb)
8192 {
8193         struct net_device *dev = skb->dev;
8194
8195         skb->protocol = eth_type_trans(skb, dev);
8196         if (napi)
8197                 netif_receive_skb(skb);
8198         else
8199                 netif_rx(skb);
8200 }
8201
8202 static void lro_append_pkt(struct s2io_nic *sp, struct lro *lro,
8203                            struct sk_buff *skb,
8204                            u32 tcp_len)
8205 {
8206         struct sk_buff *first = lro->parent;
8207
8208         first->len += tcp_len;
8209         first->data_len = lro->frags_len;
8210         skb_pull(skb, (skb->len - tcp_len));
8211         if (skb_shinfo(first)->frag_list)
8212                 lro->last_frag->next = skb;
8213         else
8214                 skb_shinfo(first)->frag_list = skb;
8215         first->truesize += skb->truesize;
8216         lro->last_frag = skb;
8217         sp->mac_control.stats_info->sw_stat.clubbed_frms_cnt++;
8218         return;
8219 }
8220
8221 /**
8222  * s2io_io_error_detected - called when PCI error is detected
8223  * @pdev: Pointer to PCI device
8224  * @state: The current pci connection state
8225  *
8226  * This function is called after a PCI bus error affecting
8227  * this device has been detected.
8228  */
8229 static pci_ers_result_t s2io_io_error_detected(struct pci_dev *pdev,
8230                                                pci_channel_state_t state)
8231 {
8232         struct net_device *netdev = pci_get_drvdata(pdev);
8233         struct s2io_nic *sp = netdev->priv;
8234
8235         netif_device_detach(netdev);
8236
8237         if (netif_running(netdev)) {
8238                 /* Bring down the card, while avoiding PCI I/O */
8239                 do_s2io_card_down(sp, 0);
8240         }
8241         pci_disable_device(pdev);
8242
8243         return PCI_ERS_RESULT_NEED_RESET;
8244 }
8245
8246 /**
8247  * s2io_io_slot_reset - called after the pci bus has been reset.
8248  * @pdev: Pointer to PCI device
8249  *
8250  * Restart the card from scratch, as if from a cold-boot.
8251  * At this point, the card has exprienced a hard reset,
8252  * followed by fixups by BIOS, and has its config space
8253  * set up identically to what it was at cold boot.
8254  */
8255 static pci_ers_result_t s2io_io_slot_reset(struct pci_dev *pdev)
8256 {
8257         struct net_device *netdev = pci_get_drvdata(pdev);
8258         struct s2io_nic *sp = netdev->priv;
8259
8260         if (pci_enable_device(pdev)) {
8261                 printk(KERN_ERR "s2io: "
8262                        "Cannot re-enable PCI device after reset.\n");
8263                 return PCI_ERS_RESULT_DISCONNECT;
8264         }
8265
8266         pci_set_master(pdev);
8267         s2io_reset(sp);
8268
8269         return PCI_ERS_RESULT_RECOVERED;
8270 }
8271
8272 /**
8273  * s2io_io_resume - called when traffic can start flowing again.
8274  * @pdev: Pointer to PCI device
8275  *
8276  * This callback is called when the error recovery driver tells
8277  * us that its OK to resume normal operation.
8278  */
8279 static void s2io_io_resume(struct pci_dev *pdev)
8280 {
8281         struct net_device *netdev = pci_get_drvdata(pdev);
8282         struct s2io_nic *sp = netdev->priv;
8283
8284         if (netif_running(netdev)) {
8285                 if (s2io_card_up(sp)) {
8286                         printk(KERN_ERR "s2io: "
8287                                "Can't bring device back up after reset.\n");
8288                         return;
8289                 }
8290
8291                 if (s2io_set_mac_addr(netdev, netdev->dev_addr) == FAILURE) {
8292                         s2io_card_down(sp);
8293                         printk(KERN_ERR "s2io: "
8294                                "Can't resetore mac addr after reset.\n");
8295                         return;
8296                 }
8297         }
8298
8299         netif_device_attach(netdev);
8300         netif_wake_queue(netdev);
8301 }