2 * r8169.c: RealTek 8169/8168/8101 ethernet driver.
4 * Copyright (c) 2002 ShuChen <shuchen@realtek.com.tw>
5 * Copyright (c) 2003 - 2007 Francois Romieu <romieu@fr.zoreil.com>
6 * Copyright (c) a lot of people too. Please respect their work.
8 * See MAINTAINERS file for support contact information.
11 #include <linux/module.h>
12 #include <linux/moduleparam.h>
13 #include <linux/pci.h>
14 #include <linux/netdevice.h>
15 #include <linux/etherdevice.h>
16 #include <linux/delay.h>
17 #include <linux/ethtool.h>
18 #include <linux/mii.h>
19 #include <linux/if_vlan.h>
20 #include <linux/crc32.h>
23 #include <linux/tcp.h>
24 #include <linux/init.h>
25 #include <linux/dma-mapping.h>
27 #include <asm/system.h>
31 #ifdef CONFIG_R8169_NAPI
32 #define NAPI_SUFFIX "-NAPI"
34 #define NAPI_SUFFIX ""
37 #define RTL8169_VERSION "2.2LK" NAPI_SUFFIX
38 #define MODULENAME "r8169"
39 #define PFX MODULENAME ": "
42 #define assert(expr) \
44 printk( "Assertion failed! %s,%s,%s,line=%d\n", \
45 #expr,__FILE__,__FUNCTION__,__LINE__); \
47 #define dprintk(fmt, args...) \
48 do { printk(KERN_DEBUG PFX fmt, ## args); } while (0)
50 #define assert(expr) do {} while (0)
51 #define dprintk(fmt, args...) do {} while (0)
52 #endif /* RTL8169_DEBUG */
54 #define R8169_MSG_DEFAULT \
55 (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN)
57 #define TX_BUFFS_AVAIL(tp) \
58 (tp->dirty_tx + NUM_TX_DESC - tp->cur_tx - 1)
60 #ifdef CONFIG_R8169_NAPI
61 #define rtl8169_rx_skb netif_receive_skb
62 #define rtl8169_rx_hwaccel_skb vlan_hwaccel_receive_skb
63 #define rtl8169_rx_quota(count, quota) min(count, quota)
65 #define rtl8169_rx_skb netif_rx
66 #define rtl8169_rx_hwaccel_skb vlan_hwaccel_rx
67 #define rtl8169_rx_quota(count, quota) count
70 /* Maximum events (Rx packets, etc.) to handle at each interrupt. */
71 static const int max_interrupt_work = 20;
73 /* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).
74 The RTL chips use a 64 element hash table based on the Ethernet CRC. */
75 static const int multicast_filter_limit = 32;
77 /* MAC address length */
78 #define MAC_ADDR_LEN 6
80 #define RX_FIFO_THRESH 7 /* 7 means NO threshold, Rx buffer level before first PCI xfer. */
81 #define RX_DMA_BURST 6 /* Maximum PCI burst, '6' is 1024 */
82 #define TX_DMA_BURST 6 /* Maximum PCI burst, '6' is 1024 */
83 #define EarlyTxThld 0x3F /* 0x3F means NO early transmit */
84 #define RxPacketMaxSize 0x3FE8 /* 16K - 1 - ETH_HLEN - VLAN - CRC... */
85 #define SafeMtu 0x1c20 /* ... actually life sucks beyond ~7k */
86 #define InterFrameGap 0x03 /* 3 means InterFrameGap = the shortest one */
88 #define R8169_REGS_SIZE 256
89 #define R8169_NAPI_WEIGHT 64
90 #define NUM_TX_DESC 64 /* Number of Tx descriptor registers */
91 #define NUM_RX_DESC 256 /* Number of Rx descriptor registers */
92 #define RX_BUF_SIZE 1536 /* Rx Buffer size */
93 #define R8169_TX_RING_BYTES (NUM_TX_DESC * sizeof(struct TxDesc))
94 #define R8169_RX_RING_BYTES (NUM_RX_DESC * sizeof(struct RxDesc))
96 #define RTL8169_TX_TIMEOUT (6*HZ)
97 #define RTL8169_PHY_TIMEOUT (10*HZ)
99 /* write/read MMIO register */
100 #define RTL_W8(reg, val8) writeb ((val8), ioaddr + (reg))
101 #define RTL_W16(reg, val16) writew ((val16), ioaddr + (reg))
102 #define RTL_W32(reg, val32) writel ((val32), ioaddr + (reg))
103 #define RTL_R8(reg) readb (ioaddr + (reg))
104 #define RTL_R16(reg) readw (ioaddr + (reg))
105 #define RTL_R32(reg) ((unsigned long) readl (ioaddr + (reg)))
108 RTL_GIGA_MAC_VER_01 = 0x01, // 8169
109 RTL_GIGA_MAC_VER_02 = 0x02, // 8169S
110 RTL_GIGA_MAC_VER_03 = 0x03, // 8110S
111 RTL_GIGA_MAC_VER_04 = 0x04, // 8169SB
112 RTL_GIGA_MAC_VER_05 = 0x05, // 8110SCd
113 RTL_GIGA_MAC_VER_06 = 0x06, // 8110SCe
114 RTL_GIGA_MAC_VER_11 = 0x0b, // 8168Bb
115 RTL_GIGA_MAC_VER_12 = 0x0c, // 8168Be 8168Bf
116 RTL_GIGA_MAC_VER_13 = 0x0d, // 8101Eb 8101Ec
117 RTL_GIGA_MAC_VER_14 = 0x0e, // 8101
118 RTL_GIGA_MAC_VER_15 = 0x0f // 8101
122 RTL_GIGA_PHY_VER_C = 0x03, /* PHY Reg 0x03 bit0-3 == 0x0000 */
123 RTL_GIGA_PHY_VER_D = 0x04, /* PHY Reg 0x03 bit0-3 == 0x0000 */
124 RTL_GIGA_PHY_VER_E = 0x05, /* PHY Reg 0x03 bit0-3 == 0x0000 */
125 RTL_GIGA_PHY_VER_F = 0x06, /* PHY Reg 0x03 bit0-3 == 0x0001 */
126 RTL_GIGA_PHY_VER_G = 0x07, /* PHY Reg 0x03 bit0-3 == 0x0002 */
127 RTL_GIGA_PHY_VER_H = 0x08, /* PHY Reg 0x03 bit0-3 == 0x0003 */
130 #define _R(NAME,MAC,MASK) \
131 { .name = NAME, .mac_version = MAC, .RxConfigMask = MASK }
133 static const struct {
136 u32 RxConfigMask; /* Clears the bits supported by this chip */
137 } rtl_chip_info[] = {
138 _R("RTL8169", RTL_GIGA_MAC_VER_01, 0xff7e1880), // 8169
139 _R("RTL8169s", RTL_GIGA_MAC_VER_02, 0xff7e1880), // 8169S
140 _R("RTL8110s", RTL_GIGA_MAC_VER_03, 0xff7e1880), // 8110S
141 _R("RTL8169sb/8110sb", RTL_GIGA_MAC_VER_04, 0xff7e1880), // 8169SB
142 _R("RTL8169sc/8110sc", RTL_GIGA_MAC_VER_05, 0xff7e1880), // 8110SCd
143 _R("RTL8169sc/8110sc", RTL_GIGA_MAC_VER_06, 0xff7e1880), // 8110SCe
144 _R("RTL8168b/8111b", RTL_GIGA_MAC_VER_11, 0xff7e1880), // PCI-E
145 _R("RTL8168b/8111b", RTL_GIGA_MAC_VER_12, 0xff7e1880), // PCI-E
146 _R("RTL8101e", RTL_GIGA_MAC_VER_13, 0xff7e1880), // PCI-E 8139
147 _R("RTL8100e", RTL_GIGA_MAC_VER_14, 0xff7e1880), // PCI-E 8139
148 _R("RTL8100e", RTL_GIGA_MAC_VER_15, 0xff7e1880) // PCI-E 8139
158 static void rtl_hw_start_8169(struct net_device *);
159 static void rtl_hw_start_8168(struct net_device *);
160 static void rtl_hw_start_8101(struct net_device *);
162 static struct pci_device_id rtl8169_pci_tbl[] = {
163 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8129), 0, 0, RTL_CFG_0 },
164 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8136), 0, 0, RTL_CFG_2 },
165 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8167), 0, 0, RTL_CFG_0 },
166 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8168), 0, 0, RTL_CFG_1 },
167 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8169), 0, 0, RTL_CFG_0 },
168 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4300), 0, 0, RTL_CFG_0 },
169 { PCI_DEVICE(0x1259, 0xc107), 0, 0, RTL_CFG_0 },
170 { PCI_DEVICE(0x16ec, 0x0116), 0, 0, RTL_CFG_0 },
171 { PCI_VENDOR_ID_LINKSYS, 0x1032,
172 PCI_ANY_ID, 0x0024, 0, 0, RTL_CFG_0 },
176 MODULE_DEVICE_TABLE(pci, rtl8169_pci_tbl);
178 static int rx_copybreak = 200;
185 MAC0 = 0, /* Ethernet hardware address. */
187 MAR0 = 8, /* Multicast filter. */
188 CounterAddrLow = 0x10,
189 CounterAddrHigh = 0x14,
190 TxDescStartAddrLow = 0x20,
191 TxDescStartAddrHigh = 0x24,
192 TxHDescStartAddrLow = 0x28,
193 TxHDescStartAddrHigh = 0x2c,
219 RxDescAddrLow = 0xe4,
220 RxDescAddrHigh = 0xe8,
223 FuncEventMask = 0xf4,
224 FuncPresetState = 0xf8,
225 FuncForceEvent = 0xfc,
228 enum rtl_register_content {
229 /* InterruptStatusBits */
233 TxDescUnavail = 0x0080,
255 /* TXPoll register p.5 */
256 HPQ = 0x80, /* Poll cmd on the high prio queue */
257 NPQ = 0x40, /* Poll cmd on the low prio queue */
258 FSWInt = 0x01, /* Forced software interrupt */
262 Cfg9346_Unlock = 0xc0,
267 AcceptBroadcast = 0x08,
268 AcceptMulticast = 0x04,
270 AcceptAllPhys = 0x01,
277 TxInterFrameGapShift = 24,
278 TxDMAShift = 8, /* DMA burst value (0-7) is shift this many bits */
280 /* Config1 register p.24 */
281 MSIEnable = (1 << 5), /* Enable Message Signaled Interrupt */
282 PMEnable = (1 << 0), /* Power Management Enable */
284 /* Config2 register p. 25 */
285 PCI_Clock_66MHz = 0x01,
286 PCI_Clock_33MHz = 0x00,
288 /* Config3 register p.25 */
289 MagicPacket = (1 << 5), /* Wake up when receives a Magic Packet */
290 LinkUp = (1 << 4), /* Wake up when the cable connection is re-established */
292 /* Config5 register p.27 */
293 BWF = (1 << 6), /* Accept Broadcast wakeup frame */
294 MWF = (1 << 5), /* Accept Multicast wakeup frame */
295 UWF = (1 << 4), /* Accept Unicast wakeup frame */
296 LanWake = (1 << 1), /* LanWake enable/disable */
297 PMEStatus = (1 << 0), /* PME status can be reset by PCI RST# */
300 TBIReset = 0x80000000,
301 TBILoopback = 0x40000000,
302 TBINwEnable = 0x20000000,
303 TBINwRestart = 0x10000000,
304 TBILinkOk = 0x02000000,
305 TBINwComplete = 0x01000000,
308 PktCntrDisable = (1 << 7), // 8168
313 INTT_0 = 0x0000, // 8168
314 INTT_1 = 0x0001, // 8168
315 INTT_2 = 0x0002, // 8168
316 INTT_3 = 0x0003, // 8168
318 /* rtl8169_PHYstatus */
329 TBILinkOK = 0x02000000,
331 /* DumpCounterCommand */
335 enum desc_status_bit {
336 DescOwn = (1 << 31), /* Descriptor is owned by NIC */
337 RingEnd = (1 << 30), /* End of descriptor ring */
338 FirstFrag = (1 << 29), /* First segment of a packet */
339 LastFrag = (1 << 28), /* Final segment of a packet */
342 LargeSend = (1 << 27), /* TCP Large Send Offload (TSO) */
343 MSSShift = 16, /* MSS value position */
344 MSSMask = 0xfff, /* MSS value + LargeSend bit: 12 bits */
345 IPCS = (1 << 18), /* Calculate IP checksum */
346 UDPCS = (1 << 17), /* Calculate UDP/IP checksum */
347 TCPCS = (1 << 16), /* Calculate TCP/IP checksum */
348 TxVlanTag = (1 << 17), /* Add VLAN tag */
351 PID1 = (1 << 18), /* Protocol ID bit 1/2 */
352 PID0 = (1 << 17), /* Protocol ID bit 2/2 */
354 #define RxProtoUDP (PID1)
355 #define RxProtoTCP (PID0)
356 #define RxProtoIP (PID1 | PID0)
357 #define RxProtoMask RxProtoIP
359 IPFail = (1 << 16), /* IP checksum failed */
360 UDPFail = (1 << 15), /* UDP/IP checksum failed */
361 TCPFail = (1 << 14), /* TCP/IP checksum failed */
362 RxVlanTag = (1 << 16), /* VLAN tag available */
365 #define RsvdMask 0x3fffc000
382 u8 __pad[sizeof(void *) - sizeof(u32)];
386 RTL_FEATURE_WOL = (1 << 0),
387 RTL_FEATURE_MSI = (1 << 1),
390 struct rtl8169_private {
391 void __iomem *mmio_addr; /* memory map physical address */
392 struct pci_dev *pci_dev; /* Index of PCI device */
393 struct net_device *dev;
394 struct napi_struct napi;
395 struct net_device_stats stats; /* statistics of net device */
396 spinlock_t lock; /* spin lock flag */
401 u32 cur_rx; /* Index into the Rx descriptor buffer of next Rx pkt. */
402 u32 cur_tx; /* Index into the Tx descriptor buffer of next Rx pkt. */
405 struct TxDesc *TxDescArray; /* 256-aligned Tx descriptor ring */
406 struct RxDesc *RxDescArray; /* 256-aligned Rx descriptor ring */
407 dma_addr_t TxPhyAddr;
408 dma_addr_t RxPhyAddr;
409 struct sk_buff *Rx_skbuff[NUM_RX_DESC]; /* Rx data buffers */
410 struct ring_info tx_skb[NUM_TX_DESC]; /* Tx data buffers */
413 struct timer_list timer;
418 int phy_auto_nego_reg;
419 int phy_1000_ctrl_reg;
420 #ifdef CONFIG_R8169_VLAN
421 struct vlan_group *vlgrp;
423 int (*set_speed)(struct net_device *, u8 autoneg, u16 speed, u8 duplex);
424 void (*get_settings)(struct net_device *, struct ethtool_cmd *);
425 void (*phy_reset_enable)(void __iomem *);
426 void (*hw_start)(struct net_device *);
427 unsigned int (*phy_reset_pending)(void __iomem *);
428 unsigned int (*link_ok)(void __iomem *);
429 struct delayed_work task;
433 MODULE_AUTHOR("Realtek and the Linux r8169 crew <netdev@vger.kernel.org>");
434 MODULE_DESCRIPTION("RealTek RTL-8169 Gigabit Ethernet driver");
435 module_param(rx_copybreak, int, 0);
436 MODULE_PARM_DESC(rx_copybreak, "Copy breakpoint for copy-only-tiny-frames");
437 module_param(use_dac, int, 0);
438 MODULE_PARM_DESC(use_dac, "Enable PCI DAC. Unsafe on 32 bit PCI slot.");
439 module_param_named(debug, debug.msg_enable, int, 0);
440 MODULE_PARM_DESC(debug, "Debug verbosity level (0=none, ..., 16=all)");
441 MODULE_LICENSE("GPL");
442 MODULE_VERSION(RTL8169_VERSION);
444 static int rtl8169_open(struct net_device *dev);
445 static int rtl8169_start_xmit(struct sk_buff *skb, struct net_device *dev);
446 static irqreturn_t rtl8169_interrupt(int irq, void *dev_instance);
447 static int rtl8169_init_ring(struct net_device *dev);
448 static void rtl_hw_start(struct net_device *dev);
449 static int rtl8169_close(struct net_device *dev);
450 static void rtl_set_rx_mode(struct net_device *dev);
451 static void rtl8169_tx_timeout(struct net_device *dev);
452 static struct net_device_stats *rtl8169_get_stats(struct net_device *dev);
453 static int rtl8169_rx_interrupt(struct net_device *, struct rtl8169_private *,
454 void __iomem *, u32 budget);
455 static int rtl8169_change_mtu(struct net_device *dev, int new_mtu);
456 static void rtl8169_down(struct net_device *dev);
457 static void rtl8169_rx_clear(struct rtl8169_private *tp);
459 #ifdef CONFIG_R8169_NAPI
460 static int rtl8169_poll(struct napi_struct *napi, int budget);
463 static const unsigned int rtl8169_rx_config =
464 (RX_FIFO_THRESH << RxCfgFIFOShift) | (RX_DMA_BURST << RxCfgDMAShift);
466 static void mdio_write(void __iomem *ioaddr, int reg_addr, int value)
470 RTL_W32(PHYAR, 0x80000000 | (reg_addr & 0xFF) << 16 | value);
472 for (i = 20; i > 0; i--) {
474 * Check if the RTL8169 has completed writing to the specified
477 if (!(RTL_R32(PHYAR) & 0x80000000))
483 static int mdio_read(void __iomem *ioaddr, int reg_addr)
487 RTL_W32(PHYAR, 0x0 | (reg_addr & 0xFF) << 16);
489 for (i = 20; i > 0; i--) {
491 * Check if the RTL8169 has completed retrieving data from
492 * the specified MII register.
494 if (RTL_R32(PHYAR) & 0x80000000) {
495 value = (int) (RTL_R32(PHYAR) & 0xFFFF);
503 static void rtl8169_irq_mask_and_ack(void __iomem *ioaddr)
505 RTL_W16(IntrMask, 0x0000);
507 RTL_W16(IntrStatus, 0xffff);
510 static void rtl8169_asic_down(void __iomem *ioaddr)
512 RTL_W8(ChipCmd, 0x00);
513 rtl8169_irq_mask_and_ack(ioaddr);
517 static unsigned int rtl8169_tbi_reset_pending(void __iomem *ioaddr)
519 return RTL_R32(TBICSR) & TBIReset;
522 static unsigned int rtl8169_xmii_reset_pending(void __iomem *ioaddr)
524 return mdio_read(ioaddr, MII_BMCR) & BMCR_RESET;
527 static unsigned int rtl8169_tbi_link_ok(void __iomem *ioaddr)
529 return RTL_R32(TBICSR) & TBILinkOk;
532 static unsigned int rtl8169_xmii_link_ok(void __iomem *ioaddr)
534 return RTL_R8(PHYstatus) & LinkStatus;
537 static void rtl8169_tbi_reset_enable(void __iomem *ioaddr)
539 RTL_W32(TBICSR, RTL_R32(TBICSR) | TBIReset);
542 static void rtl8169_xmii_reset_enable(void __iomem *ioaddr)
546 val = mdio_read(ioaddr, MII_BMCR) | BMCR_RESET;
547 mdio_write(ioaddr, MII_BMCR, val & 0xffff);
550 static void rtl8169_check_link_status(struct net_device *dev,
551 struct rtl8169_private *tp,
552 void __iomem *ioaddr)
556 spin_lock_irqsave(&tp->lock, flags);
557 if (tp->link_ok(ioaddr)) {
558 netif_carrier_on(dev);
559 if (netif_msg_ifup(tp))
560 printk(KERN_INFO PFX "%s: link up\n", dev->name);
562 if (netif_msg_ifdown(tp))
563 printk(KERN_INFO PFX "%s: link down\n", dev->name);
564 netif_carrier_off(dev);
566 spin_unlock_irqrestore(&tp->lock, flags);
569 static void rtl8169_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
571 struct rtl8169_private *tp = netdev_priv(dev);
572 void __iomem *ioaddr = tp->mmio_addr;
577 #define WAKE_ANY (WAKE_PHY | WAKE_MAGIC | WAKE_UCAST | WAKE_BCAST | WAKE_MCAST)
578 wol->supported = WAKE_ANY;
580 spin_lock_irq(&tp->lock);
582 options = RTL_R8(Config1);
583 if (!(options & PMEnable))
586 options = RTL_R8(Config3);
587 if (options & LinkUp)
588 wol->wolopts |= WAKE_PHY;
589 if (options & MagicPacket)
590 wol->wolopts |= WAKE_MAGIC;
592 options = RTL_R8(Config5);
594 wol->wolopts |= WAKE_UCAST;
596 wol->wolopts |= WAKE_BCAST;
598 wol->wolopts |= WAKE_MCAST;
601 spin_unlock_irq(&tp->lock);
604 static int rtl8169_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
606 struct rtl8169_private *tp = netdev_priv(dev);
607 void __iomem *ioaddr = tp->mmio_addr;
614 { WAKE_ANY, Config1, PMEnable },
615 { WAKE_PHY, Config3, LinkUp },
616 { WAKE_MAGIC, Config3, MagicPacket },
617 { WAKE_UCAST, Config5, UWF },
618 { WAKE_BCAST, Config5, BWF },
619 { WAKE_MCAST, Config5, MWF },
620 { WAKE_ANY, Config5, LanWake }
623 spin_lock_irq(&tp->lock);
625 RTL_W8(Cfg9346, Cfg9346_Unlock);
627 for (i = 0; i < ARRAY_SIZE(cfg); i++) {
628 u8 options = RTL_R8(cfg[i].reg) & ~cfg[i].mask;
629 if (wol->wolopts & cfg[i].opt)
630 options |= cfg[i].mask;
631 RTL_W8(cfg[i].reg, options);
634 RTL_W8(Cfg9346, Cfg9346_Lock);
637 tp->features |= RTL_FEATURE_WOL;
639 tp->features &= ~RTL_FEATURE_WOL;
641 spin_unlock_irq(&tp->lock);
646 static void rtl8169_get_drvinfo(struct net_device *dev,
647 struct ethtool_drvinfo *info)
649 struct rtl8169_private *tp = netdev_priv(dev);
651 strcpy(info->driver, MODULENAME);
652 strcpy(info->version, RTL8169_VERSION);
653 strcpy(info->bus_info, pci_name(tp->pci_dev));
656 static int rtl8169_get_regs_len(struct net_device *dev)
658 return R8169_REGS_SIZE;
661 static int rtl8169_set_speed_tbi(struct net_device *dev,
662 u8 autoneg, u16 speed, u8 duplex)
664 struct rtl8169_private *tp = netdev_priv(dev);
665 void __iomem *ioaddr = tp->mmio_addr;
669 reg = RTL_R32(TBICSR);
670 if ((autoneg == AUTONEG_DISABLE) && (speed == SPEED_1000) &&
671 (duplex == DUPLEX_FULL)) {
672 RTL_W32(TBICSR, reg & ~(TBINwEnable | TBINwRestart));
673 } else if (autoneg == AUTONEG_ENABLE)
674 RTL_W32(TBICSR, reg | TBINwEnable | TBINwRestart);
676 if (netif_msg_link(tp)) {
677 printk(KERN_WARNING "%s: "
678 "incorrect speed setting refused in TBI mode\n",
687 static int rtl8169_set_speed_xmii(struct net_device *dev,
688 u8 autoneg, u16 speed, u8 duplex)
690 struct rtl8169_private *tp = netdev_priv(dev);
691 void __iomem *ioaddr = tp->mmio_addr;
692 int auto_nego, giga_ctrl;
694 auto_nego = mdio_read(ioaddr, MII_ADVERTISE);
695 auto_nego &= ~(ADVERTISE_10HALF | ADVERTISE_10FULL |
696 ADVERTISE_100HALF | ADVERTISE_100FULL);
697 giga_ctrl = mdio_read(ioaddr, MII_CTRL1000);
698 giga_ctrl &= ~(ADVERTISE_1000FULL | ADVERTISE_1000HALF);
700 if (autoneg == AUTONEG_ENABLE) {
701 auto_nego |= (ADVERTISE_10HALF | ADVERTISE_10FULL |
702 ADVERTISE_100HALF | ADVERTISE_100FULL);
703 giga_ctrl |= ADVERTISE_1000FULL | ADVERTISE_1000HALF;
705 if (speed == SPEED_10)
706 auto_nego |= ADVERTISE_10HALF | ADVERTISE_10FULL;
707 else if (speed == SPEED_100)
708 auto_nego |= ADVERTISE_100HALF | ADVERTISE_100FULL;
709 else if (speed == SPEED_1000)
710 giga_ctrl |= ADVERTISE_1000FULL | ADVERTISE_1000HALF;
712 if (duplex == DUPLEX_HALF)
713 auto_nego &= ~(ADVERTISE_10FULL | ADVERTISE_100FULL);
715 if (duplex == DUPLEX_FULL)
716 auto_nego &= ~(ADVERTISE_10HALF | ADVERTISE_100HALF);
718 /* This tweak comes straight from Realtek's driver. */
719 if ((speed == SPEED_100) && (duplex == DUPLEX_HALF) &&
720 (tp->mac_version == RTL_GIGA_MAC_VER_13)) {
721 auto_nego = ADVERTISE_100HALF | ADVERTISE_CSMA;
725 /* The 8100e/8101e do Fast Ethernet only. */
726 if ((tp->mac_version == RTL_GIGA_MAC_VER_13) ||
727 (tp->mac_version == RTL_GIGA_MAC_VER_14) ||
728 (tp->mac_version == RTL_GIGA_MAC_VER_15)) {
729 if ((giga_ctrl & (ADVERTISE_1000FULL | ADVERTISE_1000HALF)) &&
730 netif_msg_link(tp)) {
731 printk(KERN_INFO "%s: PHY does not support 1000Mbps.\n",
734 giga_ctrl &= ~(ADVERTISE_1000FULL | ADVERTISE_1000HALF);
737 auto_nego |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
739 if (tp->mac_version == RTL_GIGA_MAC_VER_12) {
740 /* Vendor specific (0x1f) and reserved (0x0e) MII registers. */
741 mdio_write(ioaddr, 0x1f, 0x0000);
742 mdio_write(ioaddr, 0x0e, 0x0000);
745 tp->phy_auto_nego_reg = auto_nego;
746 tp->phy_1000_ctrl_reg = giga_ctrl;
748 mdio_write(ioaddr, MII_ADVERTISE, auto_nego);
749 mdio_write(ioaddr, MII_CTRL1000, giga_ctrl);
750 mdio_write(ioaddr, MII_BMCR, BMCR_ANENABLE | BMCR_ANRESTART);
754 static int rtl8169_set_speed(struct net_device *dev,
755 u8 autoneg, u16 speed, u8 duplex)
757 struct rtl8169_private *tp = netdev_priv(dev);
760 ret = tp->set_speed(dev, autoneg, speed, duplex);
762 if (netif_running(dev) && (tp->phy_1000_ctrl_reg & ADVERTISE_1000FULL))
763 mod_timer(&tp->timer, jiffies + RTL8169_PHY_TIMEOUT);
768 static int rtl8169_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
770 struct rtl8169_private *tp = netdev_priv(dev);
774 spin_lock_irqsave(&tp->lock, flags);
775 ret = rtl8169_set_speed(dev, cmd->autoneg, cmd->speed, cmd->duplex);
776 spin_unlock_irqrestore(&tp->lock, flags);
781 static u32 rtl8169_get_rx_csum(struct net_device *dev)
783 struct rtl8169_private *tp = netdev_priv(dev);
785 return tp->cp_cmd & RxChkSum;
788 static int rtl8169_set_rx_csum(struct net_device *dev, u32 data)
790 struct rtl8169_private *tp = netdev_priv(dev);
791 void __iomem *ioaddr = tp->mmio_addr;
794 spin_lock_irqsave(&tp->lock, flags);
797 tp->cp_cmd |= RxChkSum;
799 tp->cp_cmd &= ~RxChkSum;
801 RTL_W16(CPlusCmd, tp->cp_cmd);
804 spin_unlock_irqrestore(&tp->lock, flags);
809 #ifdef CONFIG_R8169_VLAN
811 static inline u32 rtl8169_tx_vlan_tag(struct rtl8169_private *tp,
814 return (tp->vlgrp && vlan_tx_tag_present(skb)) ?
815 TxVlanTag | swab16(vlan_tx_tag_get(skb)) : 0x00;
818 static void rtl8169_vlan_rx_register(struct net_device *dev,
819 struct vlan_group *grp)
821 struct rtl8169_private *tp = netdev_priv(dev);
822 void __iomem *ioaddr = tp->mmio_addr;
825 spin_lock_irqsave(&tp->lock, flags);
828 tp->cp_cmd |= RxVlan;
830 tp->cp_cmd &= ~RxVlan;
831 RTL_W16(CPlusCmd, tp->cp_cmd);
833 spin_unlock_irqrestore(&tp->lock, flags);
836 static int rtl8169_rx_vlan_skb(struct rtl8169_private *tp, struct RxDesc *desc,
839 u32 opts2 = le32_to_cpu(desc->opts2);
842 if (tp->vlgrp && (opts2 & RxVlanTag)) {
843 rtl8169_rx_hwaccel_skb(skb, tp->vlgrp, swab16(opts2 & 0xffff));
851 #else /* !CONFIG_R8169_VLAN */
853 static inline u32 rtl8169_tx_vlan_tag(struct rtl8169_private *tp,
859 static int rtl8169_rx_vlan_skb(struct rtl8169_private *tp, struct RxDesc *desc,
867 static void rtl8169_gset_tbi(struct net_device *dev, struct ethtool_cmd *cmd)
869 struct rtl8169_private *tp = netdev_priv(dev);
870 void __iomem *ioaddr = tp->mmio_addr;
874 SUPPORTED_1000baseT_Full | SUPPORTED_Autoneg | SUPPORTED_FIBRE;
875 cmd->port = PORT_FIBRE;
876 cmd->transceiver = XCVR_INTERNAL;
878 status = RTL_R32(TBICSR);
879 cmd->advertising = (status & TBINwEnable) ? ADVERTISED_Autoneg : 0;
880 cmd->autoneg = !!(status & TBINwEnable);
882 cmd->speed = SPEED_1000;
883 cmd->duplex = DUPLEX_FULL; /* Always set */
886 static void rtl8169_gset_xmii(struct net_device *dev, struct ethtool_cmd *cmd)
888 struct rtl8169_private *tp = netdev_priv(dev);
889 void __iomem *ioaddr = tp->mmio_addr;
892 cmd->supported = SUPPORTED_10baseT_Half |
893 SUPPORTED_10baseT_Full |
894 SUPPORTED_100baseT_Half |
895 SUPPORTED_100baseT_Full |
896 SUPPORTED_1000baseT_Full |
901 cmd->advertising = ADVERTISED_TP | ADVERTISED_Autoneg;
903 if (tp->phy_auto_nego_reg & ADVERTISE_10HALF)
904 cmd->advertising |= ADVERTISED_10baseT_Half;
905 if (tp->phy_auto_nego_reg & ADVERTISE_10FULL)
906 cmd->advertising |= ADVERTISED_10baseT_Full;
907 if (tp->phy_auto_nego_reg & ADVERTISE_100HALF)
908 cmd->advertising |= ADVERTISED_100baseT_Half;
909 if (tp->phy_auto_nego_reg & ADVERTISE_100FULL)
910 cmd->advertising |= ADVERTISED_100baseT_Full;
911 if (tp->phy_1000_ctrl_reg & ADVERTISE_1000FULL)
912 cmd->advertising |= ADVERTISED_1000baseT_Full;
914 status = RTL_R8(PHYstatus);
916 if (status & _1000bpsF)
917 cmd->speed = SPEED_1000;
918 else if (status & _100bps)
919 cmd->speed = SPEED_100;
920 else if (status & _10bps)
921 cmd->speed = SPEED_10;
923 if (status & TxFlowCtrl)
924 cmd->advertising |= ADVERTISED_Asym_Pause;
925 if (status & RxFlowCtrl)
926 cmd->advertising |= ADVERTISED_Pause;
928 cmd->duplex = ((status & _1000bpsF) || (status & FullDup)) ?
929 DUPLEX_FULL : DUPLEX_HALF;
932 static int rtl8169_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
934 struct rtl8169_private *tp = netdev_priv(dev);
937 spin_lock_irqsave(&tp->lock, flags);
939 tp->get_settings(dev, cmd);
941 spin_unlock_irqrestore(&tp->lock, flags);
945 static void rtl8169_get_regs(struct net_device *dev, struct ethtool_regs *regs,
948 struct rtl8169_private *tp = netdev_priv(dev);
951 if (regs->len > R8169_REGS_SIZE)
952 regs->len = R8169_REGS_SIZE;
954 spin_lock_irqsave(&tp->lock, flags);
955 memcpy_fromio(p, tp->mmio_addr, regs->len);
956 spin_unlock_irqrestore(&tp->lock, flags);
959 static u32 rtl8169_get_msglevel(struct net_device *dev)
961 struct rtl8169_private *tp = netdev_priv(dev);
963 return tp->msg_enable;
966 static void rtl8169_set_msglevel(struct net_device *dev, u32 value)
968 struct rtl8169_private *tp = netdev_priv(dev);
970 tp->msg_enable = value;
973 static const char rtl8169_gstrings[][ETH_GSTRING_LEN] = {
980 "tx_single_collisions",
981 "tx_multi_collisions",
989 struct rtl8169_counters {
996 __le32 tx_one_collision;
997 __le32 tx_multi_collision;
1000 __le32 rx_multicast;
1005 static int rtl8169_get_sset_count(struct net_device *dev, int sset)
1009 return ARRAY_SIZE(rtl8169_gstrings);
1015 static void rtl8169_get_ethtool_stats(struct net_device *dev,
1016 struct ethtool_stats *stats, u64 *data)
1018 struct rtl8169_private *tp = netdev_priv(dev);
1019 void __iomem *ioaddr = tp->mmio_addr;
1020 struct rtl8169_counters *counters;
1026 counters = pci_alloc_consistent(tp->pci_dev, sizeof(*counters), &paddr);
1030 RTL_W32(CounterAddrHigh, (u64)paddr >> 32);
1031 cmd = (u64)paddr & DMA_32BIT_MASK;
1032 RTL_W32(CounterAddrLow, cmd);
1033 RTL_W32(CounterAddrLow, cmd | CounterDump);
1035 while (RTL_R32(CounterAddrLow) & CounterDump) {
1036 if (msleep_interruptible(1))
1040 RTL_W32(CounterAddrLow, 0);
1041 RTL_W32(CounterAddrHigh, 0);
1043 data[0] = le64_to_cpu(counters->tx_packets);
1044 data[1] = le64_to_cpu(counters->rx_packets);
1045 data[2] = le64_to_cpu(counters->tx_errors);
1046 data[3] = le32_to_cpu(counters->rx_errors);
1047 data[4] = le16_to_cpu(counters->rx_missed);
1048 data[5] = le16_to_cpu(counters->align_errors);
1049 data[6] = le32_to_cpu(counters->tx_one_collision);
1050 data[7] = le32_to_cpu(counters->tx_multi_collision);
1051 data[8] = le64_to_cpu(counters->rx_unicast);
1052 data[9] = le64_to_cpu(counters->rx_broadcast);
1053 data[10] = le32_to_cpu(counters->rx_multicast);
1054 data[11] = le16_to_cpu(counters->tx_aborted);
1055 data[12] = le16_to_cpu(counters->tx_underun);
1057 pci_free_consistent(tp->pci_dev, sizeof(*counters), counters, paddr);
1060 static void rtl8169_get_strings(struct net_device *dev, u32 stringset, u8 *data)
1064 memcpy(data, *rtl8169_gstrings, sizeof(rtl8169_gstrings));
1069 static const struct ethtool_ops rtl8169_ethtool_ops = {
1070 .get_drvinfo = rtl8169_get_drvinfo,
1071 .get_regs_len = rtl8169_get_regs_len,
1072 .get_link = ethtool_op_get_link,
1073 .get_settings = rtl8169_get_settings,
1074 .set_settings = rtl8169_set_settings,
1075 .get_msglevel = rtl8169_get_msglevel,
1076 .set_msglevel = rtl8169_set_msglevel,
1077 .get_rx_csum = rtl8169_get_rx_csum,
1078 .set_rx_csum = rtl8169_set_rx_csum,
1079 .set_tx_csum = ethtool_op_set_tx_csum,
1080 .set_sg = ethtool_op_set_sg,
1081 .set_tso = ethtool_op_set_tso,
1082 .get_regs = rtl8169_get_regs,
1083 .get_wol = rtl8169_get_wol,
1084 .set_wol = rtl8169_set_wol,
1085 .get_strings = rtl8169_get_strings,
1086 .get_sset_count = rtl8169_get_sset_count,
1087 .get_ethtool_stats = rtl8169_get_ethtool_stats,
1090 static void rtl8169_write_gmii_reg_bit(void __iomem *ioaddr, int reg,
1091 int bitnum, int bitval)
1095 val = mdio_read(ioaddr, reg);
1096 val = (bitval == 1) ?
1097 val | (bitval << bitnum) : val & ~(0x0001 << bitnum);
1098 mdio_write(ioaddr, reg, val & 0xffff);
1101 static void rtl8169_get_mac_version(struct rtl8169_private *tp,
1102 void __iomem *ioaddr)
1105 * The driver currently handles the 8168Bf and the 8168Be identically
1106 * but they can be identified more specifically through the test below
1109 * (RTL_R32(TxConfig) & 0x700000) == 0x500000 ? 8168Bf : 8168Be
1111 * Same thing for the 8101Eb and the 8101Ec:
1113 * (RTL_R32(TxConfig) & 0x700000) == 0x200000 ? 8101Eb : 8101Ec
1119 { 0x38800000, RTL_GIGA_MAC_VER_15 },
1120 { 0x38000000, RTL_GIGA_MAC_VER_12 },
1121 { 0x34000000, RTL_GIGA_MAC_VER_13 },
1122 { 0x30800000, RTL_GIGA_MAC_VER_14 },
1123 { 0x30000000, RTL_GIGA_MAC_VER_11 },
1124 { 0x98000000, RTL_GIGA_MAC_VER_06 },
1125 { 0x18000000, RTL_GIGA_MAC_VER_05 },
1126 { 0x10000000, RTL_GIGA_MAC_VER_04 },
1127 { 0x04000000, RTL_GIGA_MAC_VER_03 },
1128 { 0x00800000, RTL_GIGA_MAC_VER_02 },
1129 { 0x00000000, RTL_GIGA_MAC_VER_01 } /* Catch-all */
1133 reg = RTL_R32(TxConfig) & 0xfc800000;
1134 while ((reg & p->mask) != p->mask)
1136 tp->mac_version = p->mac_version;
1139 static void rtl8169_print_mac_version(struct rtl8169_private *tp)
1141 dprintk("mac_version = 0x%02x\n", tp->mac_version);
1144 static void rtl8169_get_phy_version(struct rtl8169_private *tp,
1145 void __iomem *ioaddr)
1152 { 0x000f, 0x0002, RTL_GIGA_PHY_VER_G },
1153 { 0x000f, 0x0001, RTL_GIGA_PHY_VER_F },
1154 { 0x000f, 0x0000, RTL_GIGA_PHY_VER_E },
1155 { 0x0000, 0x0000, RTL_GIGA_PHY_VER_D } /* Catch-all */
1159 reg = mdio_read(ioaddr, MII_PHYSID2) & 0xffff;
1160 while ((reg & p->mask) != p->set)
1162 tp->phy_version = p->phy_version;
1165 static void rtl8169_print_phy_version(struct rtl8169_private *tp)
1172 { RTL_GIGA_PHY_VER_G, "RTL_GIGA_PHY_VER_G", 0x0002 },
1173 { RTL_GIGA_PHY_VER_F, "RTL_GIGA_PHY_VER_F", 0x0001 },
1174 { RTL_GIGA_PHY_VER_E, "RTL_GIGA_PHY_VER_E", 0x0000 },
1175 { RTL_GIGA_PHY_VER_D, "RTL_GIGA_PHY_VER_D", 0x0000 },
1179 for (p = phy_print; p->msg; p++) {
1180 if (tp->phy_version == p->version) {
1181 dprintk("phy_version == %s (%04x)\n", p->msg, p->reg);
1185 dprintk("phy_version == Unknown\n");
1188 static void rtl8169_hw_phy_config(struct net_device *dev)
1190 struct rtl8169_private *tp = netdev_priv(dev);
1191 void __iomem *ioaddr = tp->mmio_addr;
1193 u16 regs[5]; /* Beware of bit-sign propagation */
1194 } phy_magic[5] = { {
1195 { 0x0000, //w 4 15 12 0
1196 0x00a1, //w 3 15 0 00a1
1197 0x0008, //w 2 15 0 0008
1198 0x1020, //w 1 15 0 1020
1199 0x1000 } },{ //w 0 15 0 1000
1200 { 0x7000, //w 4 15 12 7
1201 0xff41, //w 3 15 0 ff41
1202 0xde60, //w 2 15 0 de60
1203 0x0140, //w 1 15 0 0140
1204 0x0077 } },{ //w 0 15 0 0077
1205 { 0xa000, //w 4 15 12 a
1206 0xdf01, //w 3 15 0 df01
1207 0xdf20, //w 2 15 0 df20
1208 0xff95, //w 1 15 0 ff95
1209 0xfa00 } },{ //w 0 15 0 fa00
1210 { 0xb000, //w 4 15 12 b
1211 0xff41, //w 3 15 0 ff41
1212 0xde20, //w 2 15 0 de20
1213 0x0140, //w 1 15 0 0140
1214 0x00bb } },{ //w 0 15 0 00bb
1215 { 0xf000, //w 4 15 12 f
1216 0xdf01, //w 3 15 0 df01
1217 0xdf20, //w 2 15 0 df20
1218 0xff95, //w 1 15 0 ff95
1219 0xbf00 } //w 0 15 0 bf00
1224 rtl8169_print_mac_version(tp);
1225 rtl8169_print_phy_version(tp);
1227 if (tp->mac_version <= RTL_GIGA_MAC_VER_01)
1229 if (tp->phy_version >= RTL_GIGA_PHY_VER_H)
1232 dprintk("MAC version != 0 && PHY version == 0 or 1\n");
1233 dprintk("Do final_reg2.cfg\n");
1237 if (tp->mac_version == RTL_GIGA_MAC_VER_04) {
1238 mdio_write(ioaddr, 31, 0x0002);
1239 mdio_write(ioaddr, 1, 0x90d0);
1240 mdio_write(ioaddr, 31, 0x0000);
1244 if ((tp->mac_version != RTL_GIGA_MAC_VER_02) &&
1245 (tp->mac_version != RTL_GIGA_MAC_VER_03))
1248 mdio_write(ioaddr, 31, 0x0001); //w 31 2 0 1
1249 mdio_write(ioaddr, 21, 0x1000); //w 21 15 0 1000
1250 mdio_write(ioaddr, 24, 0x65c7); //w 24 15 0 65c7
1251 rtl8169_write_gmii_reg_bit(ioaddr, 4, 11, 0); //w 4 11 11 0
1253 for (i = 0; i < ARRAY_SIZE(phy_magic); i++, p++) {
1256 val = (mdio_read(ioaddr, pos) & 0x0fff) | (p->regs[0] & 0xffff);
1257 mdio_write(ioaddr, pos, val);
1259 mdio_write(ioaddr, pos, p->regs[4 - pos] & 0xffff);
1260 rtl8169_write_gmii_reg_bit(ioaddr, 4, 11, 1); //w 4 11 11 1
1261 rtl8169_write_gmii_reg_bit(ioaddr, 4, 11, 0); //w 4 11 11 0
1263 mdio_write(ioaddr, 31, 0x0000); //w 31 2 0 0
1266 static void rtl8169_phy_timer(unsigned long __opaque)
1268 struct net_device *dev = (struct net_device *)__opaque;
1269 struct rtl8169_private *tp = netdev_priv(dev);
1270 struct timer_list *timer = &tp->timer;
1271 void __iomem *ioaddr = tp->mmio_addr;
1272 unsigned long timeout = RTL8169_PHY_TIMEOUT;
1274 assert(tp->mac_version > RTL_GIGA_MAC_VER_01);
1275 assert(tp->phy_version < RTL_GIGA_PHY_VER_H);
1277 if (!(tp->phy_1000_ctrl_reg & ADVERTISE_1000FULL))
1280 spin_lock_irq(&tp->lock);
1282 if (tp->phy_reset_pending(ioaddr)) {
1284 * A busy loop could burn quite a few cycles on nowadays CPU.
1285 * Let's delay the execution of the timer for a few ticks.
1291 if (tp->link_ok(ioaddr))
1294 if (netif_msg_link(tp))
1295 printk(KERN_WARNING "%s: PHY reset until link up\n", dev->name);
1297 tp->phy_reset_enable(ioaddr);
1300 mod_timer(timer, jiffies + timeout);
1302 spin_unlock_irq(&tp->lock);
1305 static inline void rtl8169_delete_timer(struct net_device *dev)
1307 struct rtl8169_private *tp = netdev_priv(dev);
1308 struct timer_list *timer = &tp->timer;
1310 if ((tp->mac_version <= RTL_GIGA_MAC_VER_01) ||
1311 (tp->phy_version >= RTL_GIGA_PHY_VER_H))
1314 del_timer_sync(timer);
1317 static inline void rtl8169_request_timer(struct net_device *dev)
1319 struct rtl8169_private *tp = netdev_priv(dev);
1320 struct timer_list *timer = &tp->timer;
1322 if ((tp->mac_version <= RTL_GIGA_MAC_VER_01) ||
1323 (tp->phy_version >= RTL_GIGA_PHY_VER_H))
1326 mod_timer(timer, jiffies + RTL8169_PHY_TIMEOUT);
1329 #ifdef CONFIG_NET_POLL_CONTROLLER
1331 * Polling 'interrupt' - used by things like netconsole to send skbs
1332 * without having to re-enable interrupts. It's not called while
1333 * the interrupt routine is executing.
1335 static void rtl8169_netpoll(struct net_device *dev)
1337 struct rtl8169_private *tp = netdev_priv(dev);
1338 struct pci_dev *pdev = tp->pci_dev;
1340 disable_irq(pdev->irq);
1341 rtl8169_interrupt(pdev->irq, dev);
1342 enable_irq(pdev->irq);
1346 static void rtl8169_release_board(struct pci_dev *pdev, struct net_device *dev,
1347 void __iomem *ioaddr)
1350 pci_release_regions(pdev);
1351 pci_disable_device(pdev);
1355 static void rtl8169_phy_reset(struct net_device *dev,
1356 struct rtl8169_private *tp)
1358 void __iomem *ioaddr = tp->mmio_addr;
1361 tp->phy_reset_enable(ioaddr);
1362 for (i = 0; i < 100; i++) {
1363 if (!tp->phy_reset_pending(ioaddr))
1367 if (netif_msg_link(tp))
1368 printk(KERN_ERR "%s: PHY reset failed.\n", dev->name);
1371 static void rtl8169_init_phy(struct net_device *dev, struct rtl8169_private *tp)
1373 void __iomem *ioaddr = tp->mmio_addr;
1375 rtl8169_hw_phy_config(dev);
1377 dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
1380 pci_write_config_byte(tp->pci_dev, PCI_LATENCY_TIMER, 0x40);
1382 if (tp->mac_version <= RTL_GIGA_MAC_VER_06)
1383 pci_write_config_byte(tp->pci_dev, PCI_CACHE_LINE_SIZE, 0x08);
1385 if (tp->mac_version == RTL_GIGA_MAC_VER_02) {
1386 dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
1388 dprintk("Set PHY Reg 0x0bh = 0x00h\n");
1389 mdio_write(ioaddr, 0x0b, 0x0000); //w 0x0b 15 0 0
1392 rtl8169_phy_reset(dev, tp);
1395 * rtl8169_set_speed_xmii takes good care of the Fast Ethernet
1396 * only 8101. Don't panic.
1398 rtl8169_set_speed(dev, AUTONEG_ENABLE, SPEED_1000, DUPLEX_FULL);
1400 if ((RTL_R8(PHYstatus) & TBI_Enable) && netif_msg_link(tp))
1401 printk(KERN_INFO PFX "%s: TBI auto-negotiating\n", dev->name);
1404 static void rtl_rar_set(struct rtl8169_private *tp, u8 *addr)
1406 void __iomem *ioaddr = tp->mmio_addr;
1410 low = addr[0] | (addr[1] << 8) | (addr[2] << 16) | (addr[3] << 24);
1411 high = addr[4] | (addr[5] << 8);
1413 spin_lock_irq(&tp->lock);
1415 RTL_W8(Cfg9346, Cfg9346_Unlock);
1417 RTL_W32(MAC4, high);
1418 RTL_W8(Cfg9346, Cfg9346_Lock);
1420 spin_unlock_irq(&tp->lock);
1423 static int rtl_set_mac_address(struct net_device *dev, void *p)
1425 struct rtl8169_private *tp = netdev_priv(dev);
1426 struct sockaddr *addr = p;
1428 if (!is_valid_ether_addr(addr->sa_data))
1429 return -EADDRNOTAVAIL;
1431 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
1433 rtl_rar_set(tp, dev->dev_addr);
1438 static int rtl8169_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
1440 struct rtl8169_private *tp = netdev_priv(dev);
1441 struct mii_ioctl_data *data = if_mii(ifr);
1443 if (!netif_running(dev))
1448 data->phy_id = 32; /* Internal PHY */
1452 data->val_out = mdio_read(tp->mmio_addr, data->reg_num & 0x1f);
1456 if (!capable(CAP_NET_ADMIN))
1458 mdio_write(tp->mmio_addr, data->reg_num & 0x1f, data->val_in);
1464 static const struct rtl_cfg_info {
1465 void (*hw_start)(struct net_device *);
1466 unsigned int region;
1471 } rtl_cfg_infos [] = {
1473 .hw_start = rtl_hw_start_8169,
1476 .intr_event = SYSErr | LinkChg | RxOverflow |
1477 RxFIFOOver | TxErr | TxOK | RxOK | RxErr,
1478 .napi_event = RxFIFOOver | TxErr | TxOK | RxOK | RxOverflow,
1482 .hw_start = rtl_hw_start_8168,
1485 .intr_event = SYSErr | LinkChg | RxOverflow |
1486 TxErr | TxOK | RxOK | RxErr,
1487 .napi_event = TxErr | TxOK | RxOK | RxOverflow,
1488 .msi = RTL_FEATURE_MSI
1491 .hw_start = rtl_hw_start_8101,
1494 .intr_event = SYSErr | LinkChg | RxOverflow | PCSTimeout |
1495 RxFIFOOver | TxErr | TxOK | RxOK | RxErr,
1496 .napi_event = RxFIFOOver | TxErr | TxOK | RxOK | RxOverflow,
1497 .msi = RTL_FEATURE_MSI
1501 /* Cfg9346_Unlock assumed. */
1502 static unsigned rtl_try_msi(struct pci_dev *pdev, void __iomem *ioaddr,
1503 const struct rtl_cfg_info *cfg)
1508 cfg2 = RTL_R8(Config2) & ~MSIEnable;
1510 if (pci_enable_msi(pdev)) {
1511 dev_info(&pdev->dev, "no MSI. Back to INTx.\n");
1514 msi = RTL_FEATURE_MSI;
1517 RTL_W8(Config2, cfg2);
1521 static void rtl_disable_msi(struct pci_dev *pdev, struct rtl8169_private *tp)
1523 if (tp->features & RTL_FEATURE_MSI) {
1524 pci_disable_msi(pdev);
1525 tp->features &= ~RTL_FEATURE_MSI;
1529 static int __devinit
1530 rtl8169_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
1532 const struct rtl_cfg_info *cfg = rtl_cfg_infos + ent->driver_data;
1533 const unsigned int region = cfg->region;
1534 struct rtl8169_private *tp;
1535 struct net_device *dev;
1536 void __iomem *ioaddr;
1540 if (netif_msg_drv(&debug)) {
1541 printk(KERN_INFO "%s Gigabit Ethernet driver %s loaded\n",
1542 MODULENAME, RTL8169_VERSION);
1545 dev = alloc_etherdev(sizeof (*tp));
1547 if (netif_msg_drv(&debug))
1548 dev_err(&pdev->dev, "unable to alloc new ethernet\n");
1553 SET_NETDEV_DEV(dev, &pdev->dev);
1554 tp = netdev_priv(dev);
1556 tp->msg_enable = netif_msg_init(debug.msg_enable, R8169_MSG_DEFAULT);
1558 /* enable device (incl. PCI PM wakeup and hotplug setup) */
1559 rc = pci_enable_device(pdev);
1561 if (netif_msg_probe(tp))
1562 dev_err(&pdev->dev, "enable failure\n");
1563 goto err_out_free_dev_1;
1566 rc = pci_set_mwi(pdev);
1568 goto err_out_disable_2;
1570 /* make sure PCI base addr 1 is MMIO */
1571 if (!(pci_resource_flags(pdev, region) & IORESOURCE_MEM)) {
1572 if (netif_msg_probe(tp)) {
1574 "region #%d not an MMIO resource, aborting\n",
1581 /* check for weird/broken PCI region reporting */
1582 if (pci_resource_len(pdev, region) < R8169_REGS_SIZE) {
1583 if (netif_msg_probe(tp)) {
1585 "Invalid PCI region size(s), aborting\n");
1591 rc = pci_request_regions(pdev, MODULENAME);
1593 if (netif_msg_probe(tp))
1594 dev_err(&pdev->dev, "could not request regions.\n");
1598 tp->cp_cmd = PCIMulRW | RxChkSum;
1600 if ((sizeof(dma_addr_t) > 4) &&
1601 !pci_set_dma_mask(pdev, DMA_64BIT_MASK) && use_dac) {
1602 tp->cp_cmd |= PCIDAC;
1603 dev->features |= NETIF_F_HIGHDMA;
1605 rc = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
1607 if (netif_msg_probe(tp)) {
1609 "DMA configuration failed.\n");
1611 goto err_out_free_res_4;
1615 pci_set_master(pdev);
1617 /* ioremap MMIO region */
1618 ioaddr = ioremap(pci_resource_start(pdev, region), R8169_REGS_SIZE);
1620 if (netif_msg_probe(tp))
1621 dev_err(&pdev->dev, "cannot remap MMIO, aborting\n");
1623 goto err_out_free_res_4;
1626 /* Unneeded ? Don't mess with Mrs. Murphy. */
1627 rtl8169_irq_mask_and_ack(ioaddr);
1629 /* Soft reset the chip. */
1630 RTL_W8(ChipCmd, CmdReset);
1632 /* Check that the chip has finished the reset. */
1633 for (i = 0; i < 100; i++) {
1634 if ((RTL_R8(ChipCmd) & CmdReset) == 0)
1636 msleep_interruptible(1);
1639 /* Identify chip attached to board */
1640 rtl8169_get_mac_version(tp, ioaddr);
1641 rtl8169_get_phy_version(tp, ioaddr);
1643 rtl8169_print_mac_version(tp);
1644 rtl8169_print_phy_version(tp);
1646 for (i = ARRAY_SIZE(rtl_chip_info) - 1; i >= 0; i--) {
1647 if (tp->mac_version == rtl_chip_info[i].mac_version)
1651 /* Unknown chip: assume array element #0, original RTL-8169 */
1652 if (netif_msg_probe(tp)) {
1653 dev_printk(KERN_DEBUG, &pdev->dev,
1654 "unknown chip version, assuming %s\n",
1655 rtl_chip_info[0].name);
1661 RTL_W8(Cfg9346, Cfg9346_Unlock);
1662 RTL_W8(Config1, RTL_R8(Config1) | PMEnable);
1663 RTL_W8(Config5, RTL_R8(Config5) & PMEStatus);
1664 tp->features |= rtl_try_msi(pdev, ioaddr, cfg);
1665 RTL_W8(Cfg9346, Cfg9346_Lock);
1667 if (RTL_R8(PHYstatus) & TBI_Enable) {
1668 tp->set_speed = rtl8169_set_speed_tbi;
1669 tp->get_settings = rtl8169_gset_tbi;
1670 tp->phy_reset_enable = rtl8169_tbi_reset_enable;
1671 tp->phy_reset_pending = rtl8169_tbi_reset_pending;
1672 tp->link_ok = rtl8169_tbi_link_ok;
1674 tp->phy_1000_ctrl_reg = ADVERTISE_1000FULL; /* Implied by TBI */
1676 tp->set_speed = rtl8169_set_speed_xmii;
1677 tp->get_settings = rtl8169_gset_xmii;
1678 tp->phy_reset_enable = rtl8169_xmii_reset_enable;
1679 tp->phy_reset_pending = rtl8169_xmii_reset_pending;
1680 tp->link_ok = rtl8169_xmii_link_ok;
1682 dev->do_ioctl = rtl8169_ioctl;
1685 /* Get MAC address. FIXME: read EEPROM */
1686 for (i = 0; i < MAC_ADDR_LEN; i++)
1687 dev->dev_addr[i] = RTL_R8(MAC0 + i);
1688 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
1690 dev->open = rtl8169_open;
1691 dev->hard_start_xmit = rtl8169_start_xmit;
1692 dev->get_stats = rtl8169_get_stats;
1693 SET_ETHTOOL_OPS(dev, &rtl8169_ethtool_ops);
1694 dev->stop = rtl8169_close;
1695 dev->tx_timeout = rtl8169_tx_timeout;
1696 dev->set_multicast_list = rtl_set_rx_mode;
1697 dev->watchdog_timeo = RTL8169_TX_TIMEOUT;
1698 dev->irq = pdev->irq;
1699 dev->base_addr = (unsigned long) ioaddr;
1700 dev->change_mtu = rtl8169_change_mtu;
1701 dev->set_mac_address = rtl_set_mac_address;
1703 #ifdef CONFIG_R8169_NAPI
1704 netif_napi_add(dev, &tp->napi, rtl8169_poll, R8169_NAPI_WEIGHT);
1707 #ifdef CONFIG_R8169_VLAN
1708 dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
1709 dev->vlan_rx_register = rtl8169_vlan_rx_register;
1712 #ifdef CONFIG_NET_POLL_CONTROLLER
1713 dev->poll_controller = rtl8169_netpoll;
1716 tp->intr_mask = 0xffff;
1718 tp->mmio_addr = ioaddr;
1719 tp->align = cfg->align;
1720 tp->hw_start = cfg->hw_start;
1721 tp->intr_event = cfg->intr_event;
1722 tp->napi_event = cfg->napi_event;
1724 init_timer(&tp->timer);
1725 tp->timer.data = (unsigned long) dev;
1726 tp->timer.function = rtl8169_phy_timer;
1728 spin_lock_init(&tp->lock);
1730 rc = register_netdev(dev);
1734 pci_set_drvdata(pdev, dev);
1736 if (netif_msg_probe(tp)) {
1737 u32 xid = RTL_R32(TxConfig) & 0x7cf0f8ff;
1739 printk(KERN_INFO "%s: %s at 0x%lx, "
1740 "%2.2x:%2.2x:%2.2x:%2.2x:%2.2x:%2.2x, "
1741 "XID %08x IRQ %d\n",
1743 rtl_chip_info[tp->chipset].name,
1745 dev->dev_addr[0], dev->dev_addr[1],
1746 dev->dev_addr[2], dev->dev_addr[3],
1747 dev->dev_addr[4], dev->dev_addr[5], xid, dev->irq);
1750 rtl8169_init_phy(dev, tp);
1756 rtl_disable_msi(pdev, tp);
1759 pci_release_regions(pdev);
1761 pci_clear_mwi(pdev);
1763 pci_disable_device(pdev);
1769 static void __devexit rtl8169_remove_one(struct pci_dev *pdev)
1771 struct net_device *dev = pci_get_drvdata(pdev);
1772 struct rtl8169_private *tp = netdev_priv(dev);
1774 flush_scheduled_work();
1776 unregister_netdev(dev);
1777 rtl_disable_msi(pdev, tp);
1778 rtl8169_release_board(pdev, dev, tp->mmio_addr);
1779 pci_set_drvdata(pdev, NULL);
1782 static void rtl8169_set_rxbufsize(struct rtl8169_private *tp,
1783 struct net_device *dev)
1785 unsigned int mtu = dev->mtu;
1787 tp->rx_buf_sz = (mtu > RX_BUF_SIZE) ? mtu + ETH_HLEN + 8 : RX_BUF_SIZE;
1790 static int rtl8169_open(struct net_device *dev)
1792 struct rtl8169_private *tp = netdev_priv(dev);
1793 struct pci_dev *pdev = tp->pci_dev;
1794 int retval = -ENOMEM;
1797 rtl8169_set_rxbufsize(tp, dev);
1800 * Rx and Tx desscriptors needs 256 bytes alignment.
1801 * pci_alloc_consistent provides more.
1803 tp->TxDescArray = pci_alloc_consistent(pdev, R8169_TX_RING_BYTES,
1805 if (!tp->TxDescArray)
1808 tp->RxDescArray = pci_alloc_consistent(pdev, R8169_RX_RING_BYTES,
1810 if (!tp->RxDescArray)
1813 retval = rtl8169_init_ring(dev);
1817 INIT_DELAYED_WORK(&tp->task, NULL);
1821 retval = request_irq(dev->irq, rtl8169_interrupt,
1822 (tp->features & RTL_FEATURE_MSI) ? 0 : IRQF_SHARED,
1825 goto err_release_ring_2;
1827 #ifdef CONFIG_R8169_NAPI
1828 napi_enable(&tp->napi);
1833 rtl8169_request_timer(dev);
1835 rtl8169_check_link_status(dev, tp, tp->mmio_addr);
1840 rtl8169_rx_clear(tp);
1842 pci_free_consistent(pdev, R8169_RX_RING_BYTES, tp->RxDescArray,
1845 pci_free_consistent(pdev, R8169_TX_RING_BYTES, tp->TxDescArray,
1850 static void rtl8169_hw_reset(void __iomem *ioaddr)
1852 /* Disable interrupts */
1853 rtl8169_irq_mask_and_ack(ioaddr);
1855 /* Reset the chipset */
1856 RTL_W8(ChipCmd, CmdReset);
1862 static void rtl_set_rx_tx_config_registers(struct rtl8169_private *tp)
1864 void __iomem *ioaddr = tp->mmio_addr;
1865 u32 cfg = rtl8169_rx_config;
1867 cfg |= (RTL_R32(RxConfig) & rtl_chip_info[tp->chipset].RxConfigMask);
1868 RTL_W32(RxConfig, cfg);
1870 /* Set DMA burst size and Interframe Gap Time */
1871 RTL_W32(TxConfig, (TX_DMA_BURST << TxDMAShift) |
1872 (InterFrameGap << TxInterFrameGapShift));
1875 static void rtl_hw_start(struct net_device *dev)
1877 struct rtl8169_private *tp = netdev_priv(dev);
1878 void __iomem *ioaddr = tp->mmio_addr;
1881 /* Soft reset the chip. */
1882 RTL_W8(ChipCmd, CmdReset);
1884 /* Check that the chip has finished the reset. */
1885 for (i = 0; i < 100; i++) {
1886 if ((RTL_R8(ChipCmd) & CmdReset) == 0)
1888 msleep_interruptible(1);
1893 netif_start_queue(dev);
1897 static void rtl_set_rx_tx_desc_registers(struct rtl8169_private *tp,
1898 void __iomem *ioaddr)
1901 * Magic spell: some iop3xx ARM board needs the TxDescAddrHigh
1902 * register to be written before TxDescAddrLow to work.
1903 * Switching from MMIO to I/O access fixes the issue as well.
1905 RTL_W32(TxDescStartAddrHigh, ((u64) tp->TxPhyAddr) >> 32);
1906 RTL_W32(TxDescStartAddrLow, ((u64) tp->TxPhyAddr) & DMA_32BIT_MASK);
1907 RTL_W32(RxDescAddrHigh, ((u64) tp->RxPhyAddr) >> 32);
1908 RTL_W32(RxDescAddrLow, ((u64) tp->RxPhyAddr) & DMA_32BIT_MASK);
1911 static u16 rtl_rw_cpluscmd(void __iomem *ioaddr)
1915 cmd = RTL_R16(CPlusCmd);
1916 RTL_W16(CPlusCmd, cmd);
1920 static void rtl_set_rx_max_size(void __iomem *ioaddr)
1922 /* Low hurts. Let's disable the filtering. */
1923 RTL_W16(RxMaxSize, 16383);
1926 static void rtl8169_set_magic_reg(void __iomem *ioaddr, unsigned mac_version)
1933 { RTL_GIGA_MAC_VER_05, PCI_Clock_33MHz, 0x000fff00 }, // 8110SCd
1934 { RTL_GIGA_MAC_VER_05, PCI_Clock_66MHz, 0x000fffff },
1935 { RTL_GIGA_MAC_VER_06, PCI_Clock_33MHz, 0x00ffff00 }, // 8110SCe
1936 { RTL_GIGA_MAC_VER_06, PCI_Clock_66MHz, 0x00ffffff }
1941 clk = RTL_R8(Config2) & PCI_Clock_66MHz;
1942 for (i = 0; i < ARRAY_SIZE(cfg2_info); i++) {
1943 if ((p->mac_version == mac_version) && (p->clk == clk)) {
1944 RTL_W32(0x7c, p->val);
1950 static void rtl_hw_start_8169(struct net_device *dev)
1952 struct rtl8169_private *tp = netdev_priv(dev);
1953 void __iomem *ioaddr = tp->mmio_addr;
1954 struct pci_dev *pdev = tp->pci_dev;
1956 if (tp->mac_version == RTL_GIGA_MAC_VER_05) {
1957 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) | PCIMulRW);
1958 pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE, 0x08);
1961 RTL_W8(Cfg9346, Cfg9346_Unlock);
1962 if ((tp->mac_version == RTL_GIGA_MAC_VER_01) ||
1963 (tp->mac_version == RTL_GIGA_MAC_VER_02) ||
1964 (tp->mac_version == RTL_GIGA_MAC_VER_03) ||
1965 (tp->mac_version == RTL_GIGA_MAC_VER_04))
1966 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
1968 RTL_W8(EarlyTxThres, EarlyTxThld);
1970 rtl_set_rx_max_size(ioaddr);
1972 if ((tp->mac_version == RTL_GIGA_MAC_VER_01) ||
1973 (tp->mac_version == RTL_GIGA_MAC_VER_02) ||
1974 (tp->mac_version == RTL_GIGA_MAC_VER_03) ||
1975 (tp->mac_version == RTL_GIGA_MAC_VER_04))
1976 rtl_set_rx_tx_config_registers(tp);
1978 tp->cp_cmd |= rtl_rw_cpluscmd(ioaddr) | PCIMulRW;
1980 if ((tp->mac_version == RTL_GIGA_MAC_VER_02) ||
1981 (tp->mac_version == RTL_GIGA_MAC_VER_03)) {
1982 dprintk("Set MAC Reg C+CR Offset 0xE0. "
1983 "Bit-3 and bit-14 MUST be 1\n");
1984 tp->cp_cmd |= (1 << 14);
1987 RTL_W16(CPlusCmd, tp->cp_cmd);
1989 rtl8169_set_magic_reg(ioaddr, tp->mac_version);
1992 * Undocumented corner. Supposedly:
1993 * (TxTimer << 12) | (TxPackets << 8) | (RxTimer << 4) | RxPackets
1995 RTL_W16(IntrMitigate, 0x0000);
1997 rtl_set_rx_tx_desc_registers(tp, ioaddr);
1999 if ((tp->mac_version != RTL_GIGA_MAC_VER_01) &&
2000 (tp->mac_version != RTL_GIGA_MAC_VER_02) &&
2001 (tp->mac_version != RTL_GIGA_MAC_VER_03) &&
2002 (tp->mac_version != RTL_GIGA_MAC_VER_04)) {
2003 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
2004 rtl_set_rx_tx_config_registers(tp);
2007 RTL_W8(Cfg9346, Cfg9346_Lock);
2009 /* Initially a 10 us delay. Turned it into a PCI commit. - FR */
2012 RTL_W32(RxMissed, 0);
2014 rtl_set_rx_mode(dev);
2016 /* no early-rx interrupts */
2017 RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xF000);
2019 /* Enable all known interrupts by setting the interrupt mask. */
2020 RTL_W16(IntrMask, tp->intr_event);
2023 static void rtl_hw_start_8168(struct net_device *dev)
2025 struct rtl8169_private *tp = netdev_priv(dev);
2026 void __iomem *ioaddr = tp->mmio_addr;
2027 struct pci_dev *pdev = tp->pci_dev;
2030 RTL_W8(Cfg9346, Cfg9346_Unlock);
2032 RTL_W8(EarlyTxThres, EarlyTxThld);
2034 rtl_set_rx_max_size(ioaddr);
2036 rtl_set_rx_tx_config_registers(tp);
2038 tp->cp_cmd |= RTL_R16(CPlusCmd) | PktCntrDisable | INTT_1;
2040 RTL_W16(CPlusCmd, tp->cp_cmd);
2042 /* Tx performance tweak. */
2043 pci_read_config_byte(pdev, 0x69, &ctl);
2044 ctl = (ctl & ~0x70) | 0x50;
2045 pci_write_config_byte(pdev, 0x69, ctl);
2047 RTL_W16(IntrMitigate, 0x5151);
2049 /* Work around for RxFIFO overflow. */
2050 if (tp->mac_version == RTL_GIGA_MAC_VER_11) {
2051 tp->intr_event |= RxFIFOOver | PCSTimeout;
2052 tp->intr_event &= ~RxOverflow;
2055 rtl_set_rx_tx_desc_registers(tp, ioaddr);
2057 RTL_W8(Cfg9346, Cfg9346_Lock);
2061 RTL_W32(RxMissed, 0);
2063 rtl_set_rx_mode(dev);
2065 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
2067 RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xF000);
2069 RTL_W16(IntrMask, tp->intr_event);
2072 static void rtl_hw_start_8101(struct net_device *dev)
2074 struct rtl8169_private *tp = netdev_priv(dev);
2075 void __iomem *ioaddr = tp->mmio_addr;
2076 struct pci_dev *pdev = tp->pci_dev;
2078 if (tp->mac_version == RTL_GIGA_MAC_VER_13) {
2079 pci_write_config_word(pdev, 0x68, 0x00);
2080 pci_write_config_word(pdev, 0x69, 0x08);
2083 RTL_W8(Cfg9346, Cfg9346_Unlock);
2085 RTL_W8(EarlyTxThres, EarlyTxThld);
2087 rtl_set_rx_max_size(ioaddr);
2089 tp->cp_cmd |= rtl_rw_cpluscmd(ioaddr) | PCIMulRW;
2091 RTL_W16(CPlusCmd, tp->cp_cmd);
2093 RTL_W16(IntrMitigate, 0x0000);
2095 rtl_set_rx_tx_desc_registers(tp, ioaddr);
2097 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
2098 rtl_set_rx_tx_config_registers(tp);
2100 RTL_W8(Cfg9346, Cfg9346_Lock);
2104 RTL_W32(RxMissed, 0);
2106 rtl_set_rx_mode(dev);
2108 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
2110 RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xf000);
2112 RTL_W16(IntrMask, tp->intr_event);
2115 static int rtl8169_change_mtu(struct net_device *dev, int new_mtu)
2117 struct rtl8169_private *tp = netdev_priv(dev);
2120 if (new_mtu < ETH_ZLEN || new_mtu > SafeMtu)
2125 if (!netif_running(dev))
2130 rtl8169_set_rxbufsize(tp, dev);
2132 ret = rtl8169_init_ring(dev);
2136 #ifdef CONFIG_R8169_NAPI
2137 napi_enable(&tp->napi);
2142 rtl8169_request_timer(dev);
2148 static inline void rtl8169_make_unusable_by_asic(struct RxDesc *desc)
2150 desc->addr = 0x0badbadbadbadbadull;
2151 desc->opts1 &= ~cpu_to_le32(DescOwn | RsvdMask);
2154 static void rtl8169_free_rx_skb(struct rtl8169_private *tp,
2155 struct sk_buff **sk_buff, struct RxDesc *desc)
2157 struct pci_dev *pdev = tp->pci_dev;
2159 pci_unmap_single(pdev, le64_to_cpu(desc->addr), tp->rx_buf_sz,
2160 PCI_DMA_FROMDEVICE);
2161 dev_kfree_skb(*sk_buff);
2163 rtl8169_make_unusable_by_asic(desc);
2166 static inline void rtl8169_mark_to_asic(struct RxDesc *desc, u32 rx_buf_sz)
2168 u32 eor = le32_to_cpu(desc->opts1) & RingEnd;
2170 desc->opts1 = cpu_to_le32(DescOwn | eor | rx_buf_sz);
2173 static inline void rtl8169_map_to_asic(struct RxDesc *desc, dma_addr_t mapping,
2176 desc->addr = cpu_to_le64(mapping);
2178 rtl8169_mark_to_asic(desc, rx_buf_sz);
2181 static struct sk_buff *rtl8169_alloc_rx_skb(struct pci_dev *pdev,
2182 struct net_device *dev,
2183 struct RxDesc *desc, int rx_buf_sz,
2186 struct sk_buff *skb;
2190 pad = align ? align : NET_IP_ALIGN;
2192 skb = netdev_alloc_skb(dev, rx_buf_sz + pad);
2196 skb_reserve(skb, align ? ((pad - 1) & (unsigned long)skb->data) : pad);
2198 mapping = pci_map_single(pdev, skb->data, rx_buf_sz,
2199 PCI_DMA_FROMDEVICE);
2201 rtl8169_map_to_asic(desc, mapping, rx_buf_sz);
2206 rtl8169_make_unusable_by_asic(desc);
2210 static void rtl8169_rx_clear(struct rtl8169_private *tp)
2214 for (i = 0; i < NUM_RX_DESC; i++) {
2215 if (tp->Rx_skbuff[i]) {
2216 rtl8169_free_rx_skb(tp, tp->Rx_skbuff + i,
2217 tp->RxDescArray + i);
2222 static u32 rtl8169_rx_fill(struct rtl8169_private *tp, struct net_device *dev,
2227 for (cur = start; end - cur != 0; cur++) {
2228 struct sk_buff *skb;
2229 unsigned int i = cur % NUM_RX_DESC;
2231 WARN_ON((s32)(end - cur) < 0);
2233 if (tp->Rx_skbuff[i])
2236 skb = rtl8169_alloc_rx_skb(tp->pci_dev, dev,
2237 tp->RxDescArray + i,
2238 tp->rx_buf_sz, tp->align);
2242 tp->Rx_skbuff[i] = skb;
2247 static inline void rtl8169_mark_as_last_descriptor(struct RxDesc *desc)
2249 desc->opts1 |= cpu_to_le32(RingEnd);
2252 static void rtl8169_init_ring_indexes(struct rtl8169_private *tp)
2254 tp->dirty_tx = tp->dirty_rx = tp->cur_tx = tp->cur_rx = 0;
2257 static int rtl8169_init_ring(struct net_device *dev)
2259 struct rtl8169_private *tp = netdev_priv(dev);
2261 rtl8169_init_ring_indexes(tp);
2263 memset(tp->tx_skb, 0x0, NUM_TX_DESC * sizeof(struct ring_info));
2264 memset(tp->Rx_skbuff, 0x0, NUM_RX_DESC * sizeof(struct sk_buff *));
2266 if (rtl8169_rx_fill(tp, dev, 0, NUM_RX_DESC) != NUM_RX_DESC)
2269 rtl8169_mark_as_last_descriptor(tp->RxDescArray + NUM_RX_DESC - 1);
2274 rtl8169_rx_clear(tp);
2278 static void rtl8169_unmap_tx_skb(struct pci_dev *pdev, struct ring_info *tx_skb,
2279 struct TxDesc *desc)
2281 unsigned int len = tx_skb->len;
2283 pci_unmap_single(pdev, le64_to_cpu(desc->addr), len, PCI_DMA_TODEVICE);
2290 static void rtl8169_tx_clear(struct rtl8169_private *tp)
2294 for (i = tp->dirty_tx; i < tp->dirty_tx + NUM_TX_DESC; i++) {
2295 unsigned int entry = i % NUM_TX_DESC;
2296 struct ring_info *tx_skb = tp->tx_skb + entry;
2297 unsigned int len = tx_skb->len;
2300 struct sk_buff *skb = tx_skb->skb;
2302 rtl8169_unmap_tx_skb(tp->pci_dev, tx_skb,
2303 tp->TxDescArray + entry);
2308 tp->stats.tx_dropped++;
2311 tp->cur_tx = tp->dirty_tx = 0;
2314 static void rtl8169_schedule_work(struct net_device *dev, work_func_t task)
2316 struct rtl8169_private *tp = netdev_priv(dev);
2318 PREPARE_DELAYED_WORK(&tp->task, task);
2319 schedule_delayed_work(&tp->task, 4);
2322 static void rtl8169_wait_for_quiescence(struct net_device *dev)
2324 struct rtl8169_private *tp = netdev_priv(dev);
2325 void __iomem *ioaddr = tp->mmio_addr;
2327 synchronize_irq(dev->irq);
2329 /* Wait for any pending NAPI task to complete */
2330 #ifdef CONFIG_R8169_NAPI
2331 napi_disable(&tp->napi);
2334 rtl8169_irq_mask_and_ack(ioaddr);
2336 #ifdef CONFIG_R8169_NAPI
2337 napi_enable(&tp->napi);
2341 static void rtl8169_reinit_task(struct work_struct *work)
2343 struct rtl8169_private *tp =
2344 container_of(work, struct rtl8169_private, task.work);
2345 struct net_device *dev = tp->dev;
2350 if (!netif_running(dev))
2353 rtl8169_wait_for_quiescence(dev);
2356 ret = rtl8169_open(dev);
2357 if (unlikely(ret < 0)) {
2358 if (net_ratelimit() && netif_msg_drv(tp)) {
2359 printk(KERN_ERR PFX "%s: reinit failure (status = %d)."
2360 " Rescheduling.\n", dev->name, ret);
2362 rtl8169_schedule_work(dev, rtl8169_reinit_task);
2369 static void rtl8169_reset_task(struct work_struct *work)
2371 struct rtl8169_private *tp =
2372 container_of(work, struct rtl8169_private, task.work);
2373 struct net_device *dev = tp->dev;
2377 if (!netif_running(dev))
2380 rtl8169_wait_for_quiescence(dev);
2382 rtl8169_rx_interrupt(dev, tp, tp->mmio_addr, ~(u32)0);
2383 rtl8169_tx_clear(tp);
2385 if (tp->dirty_rx == tp->cur_rx) {
2386 rtl8169_init_ring_indexes(tp);
2388 netif_wake_queue(dev);
2390 if (net_ratelimit() && netif_msg_intr(tp)) {
2391 printk(KERN_EMERG PFX "%s: Rx buffers shortage\n",
2394 rtl8169_schedule_work(dev, rtl8169_reset_task);
2401 static void rtl8169_tx_timeout(struct net_device *dev)
2403 struct rtl8169_private *tp = netdev_priv(dev);
2405 rtl8169_hw_reset(tp->mmio_addr);
2407 /* Let's wait a bit while any (async) irq lands on */
2408 rtl8169_schedule_work(dev, rtl8169_reset_task);
2411 static int rtl8169_xmit_frags(struct rtl8169_private *tp, struct sk_buff *skb,
2414 struct skb_shared_info *info = skb_shinfo(skb);
2415 unsigned int cur_frag, entry;
2416 struct TxDesc * uninitialized_var(txd);
2419 for (cur_frag = 0; cur_frag < info->nr_frags; cur_frag++) {
2420 skb_frag_t *frag = info->frags + cur_frag;
2425 entry = (entry + 1) % NUM_TX_DESC;
2427 txd = tp->TxDescArray + entry;
2429 addr = ((void *) page_address(frag->page)) + frag->page_offset;
2430 mapping = pci_map_single(tp->pci_dev, addr, len, PCI_DMA_TODEVICE);
2432 /* anti gcc 2.95.3 bugware (sic) */
2433 status = opts1 | len | (RingEnd * !((entry + 1) % NUM_TX_DESC));
2435 txd->opts1 = cpu_to_le32(status);
2436 txd->addr = cpu_to_le64(mapping);
2438 tp->tx_skb[entry].len = len;
2442 tp->tx_skb[entry].skb = skb;
2443 txd->opts1 |= cpu_to_le32(LastFrag);
2449 static inline u32 rtl8169_tso_csum(struct sk_buff *skb, struct net_device *dev)
2451 if (dev->features & NETIF_F_TSO) {
2452 u32 mss = skb_shinfo(skb)->gso_size;
2455 return LargeSend | ((mss & MSSMask) << MSSShift);
2457 if (skb->ip_summed == CHECKSUM_PARTIAL) {
2458 const struct iphdr *ip = ip_hdr(skb);
2460 if (ip->protocol == IPPROTO_TCP)
2461 return IPCS | TCPCS;
2462 else if (ip->protocol == IPPROTO_UDP)
2463 return IPCS | UDPCS;
2464 WARN_ON(1); /* we need a WARN() */
2469 static int rtl8169_start_xmit(struct sk_buff *skb, struct net_device *dev)
2471 struct rtl8169_private *tp = netdev_priv(dev);
2472 unsigned int frags, entry = tp->cur_tx % NUM_TX_DESC;
2473 struct TxDesc *txd = tp->TxDescArray + entry;
2474 void __iomem *ioaddr = tp->mmio_addr;
2478 int ret = NETDEV_TX_OK;
2480 if (unlikely(TX_BUFFS_AVAIL(tp) < skb_shinfo(skb)->nr_frags)) {
2481 if (netif_msg_drv(tp)) {
2483 "%s: BUG! Tx Ring full when queue awake!\n",
2489 if (unlikely(le32_to_cpu(txd->opts1) & DescOwn))
2492 opts1 = DescOwn | rtl8169_tso_csum(skb, dev);
2494 frags = rtl8169_xmit_frags(tp, skb, opts1);
2496 len = skb_headlen(skb);
2501 if (unlikely(len < ETH_ZLEN)) {
2502 if (skb_padto(skb, ETH_ZLEN))
2503 goto err_update_stats;
2507 opts1 |= FirstFrag | LastFrag;
2508 tp->tx_skb[entry].skb = skb;
2511 mapping = pci_map_single(tp->pci_dev, skb->data, len, PCI_DMA_TODEVICE);
2513 tp->tx_skb[entry].len = len;
2514 txd->addr = cpu_to_le64(mapping);
2515 txd->opts2 = cpu_to_le32(rtl8169_tx_vlan_tag(tp, skb));
2519 /* anti gcc 2.95.3 bugware (sic) */
2520 status = opts1 | len | (RingEnd * !((entry + 1) % NUM_TX_DESC));
2521 txd->opts1 = cpu_to_le32(status);
2523 dev->trans_start = jiffies;
2525 tp->cur_tx += frags + 1;
2529 RTL_W8(TxPoll, NPQ); /* set polling bit */
2531 if (TX_BUFFS_AVAIL(tp) < MAX_SKB_FRAGS) {
2532 netif_stop_queue(dev);
2534 if (TX_BUFFS_AVAIL(tp) >= MAX_SKB_FRAGS)
2535 netif_wake_queue(dev);
2542 netif_stop_queue(dev);
2543 ret = NETDEV_TX_BUSY;
2545 tp->stats.tx_dropped++;
2549 static void rtl8169_pcierr_interrupt(struct net_device *dev)
2551 struct rtl8169_private *tp = netdev_priv(dev);
2552 struct pci_dev *pdev = tp->pci_dev;
2553 void __iomem *ioaddr = tp->mmio_addr;
2554 u16 pci_status, pci_cmd;
2556 pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd);
2557 pci_read_config_word(pdev, PCI_STATUS, &pci_status);
2559 if (netif_msg_intr(tp)) {
2561 "%s: PCI error (cmd = 0x%04x, status = 0x%04x).\n",
2562 dev->name, pci_cmd, pci_status);
2566 * The recovery sequence below admits a very elaborated explanation:
2567 * - it seems to work;
2568 * - I did not see what else could be done;
2569 * - it makes iop3xx happy.
2571 * Feel free to adjust to your needs.
2573 if (pdev->broken_parity_status)
2574 pci_cmd &= ~PCI_COMMAND_PARITY;
2576 pci_cmd |= PCI_COMMAND_SERR | PCI_COMMAND_PARITY;
2578 pci_write_config_word(pdev, PCI_COMMAND, pci_cmd);
2580 pci_write_config_word(pdev, PCI_STATUS,
2581 pci_status & (PCI_STATUS_DETECTED_PARITY |
2582 PCI_STATUS_SIG_SYSTEM_ERROR | PCI_STATUS_REC_MASTER_ABORT |
2583 PCI_STATUS_REC_TARGET_ABORT | PCI_STATUS_SIG_TARGET_ABORT));
2585 /* The infamous DAC f*ckup only happens at boot time */
2586 if ((tp->cp_cmd & PCIDAC) && !tp->dirty_rx && !tp->cur_rx) {
2587 if (netif_msg_intr(tp))
2588 printk(KERN_INFO "%s: disabling PCI DAC.\n", dev->name);
2589 tp->cp_cmd &= ~PCIDAC;
2590 RTL_W16(CPlusCmd, tp->cp_cmd);
2591 dev->features &= ~NETIF_F_HIGHDMA;
2594 rtl8169_hw_reset(ioaddr);
2596 rtl8169_schedule_work(dev, rtl8169_reinit_task);
2599 static void rtl8169_tx_interrupt(struct net_device *dev,
2600 struct rtl8169_private *tp,
2601 void __iomem *ioaddr)
2603 unsigned int dirty_tx, tx_left;
2605 dirty_tx = tp->dirty_tx;
2607 tx_left = tp->cur_tx - dirty_tx;
2609 while (tx_left > 0) {
2610 unsigned int entry = dirty_tx % NUM_TX_DESC;
2611 struct ring_info *tx_skb = tp->tx_skb + entry;
2612 u32 len = tx_skb->len;
2616 status = le32_to_cpu(tp->TxDescArray[entry].opts1);
2617 if (status & DescOwn)
2620 tp->stats.tx_bytes += len;
2621 tp->stats.tx_packets++;
2623 rtl8169_unmap_tx_skb(tp->pci_dev, tx_skb, tp->TxDescArray + entry);
2625 if (status & LastFrag) {
2626 dev_kfree_skb_irq(tx_skb->skb);
2633 if (tp->dirty_tx != dirty_tx) {
2634 tp->dirty_tx = dirty_tx;
2636 if (netif_queue_stopped(dev) &&
2637 (TX_BUFFS_AVAIL(tp) >= MAX_SKB_FRAGS)) {
2638 netif_wake_queue(dev);
2641 * 8168 hack: TxPoll requests are lost when the Tx packets are
2642 * too close. Let's kick an extra TxPoll request when a burst
2643 * of start_xmit activity is detected (if it is not detected,
2644 * it is slow enough). -- FR
2647 if (tp->cur_tx != dirty_tx)
2648 RTL_W8(TxPoll, NPQ);
2652 static inline int rtl8169_fragmented_frame(u32 status)
2654 return (status & (FirstFrag | LastFrag)) != (FirstFrag | LastFrag);
2657 static inline void rtl8169_rx_csum(struct sk_buff *skb, struct RxDesc *desc)
2659 u32 opts1 = le32_to_cpu(desc->opts1);
2660 u32 status = opts1 & RxProtoMask;
2662 if (((status == RxProtoTCP) && !(opts1 & TCPFail)) ||
2663 ((status == RxProtoUDP) && !(opts1 & UDPFail)) ||
2664 ((status == RxProtoIP) && !(opts1 & IPFail)))
2665 skb->ip_summed = CHECKSUM_UNNECESSARY;
2667 skb->ip_summed = CHECKSUM_NONE;
2670 static inline bool rtl8169_try_rx_copy(struct sk_buff **sk_buff,
2671 struct rtl8169_private *tp, int pkt_size,
2674 struct sk_buff *skb;
2677 if (pkt_size >= rx_copybreak)
2680 skb = netdev_alloc_skb(tp->dev, pkt_size + NET_IP_ALIGN);
2684 pci_dma_sync_single_for_cpu(tp->pci_dev, addr, pkt_size,
2685 PCI_DMA_FROMDEVICE);
2686 skb_reserve(skb, NET_IP_ALIGN);
2687 skb_copy_from_linear_data(*sk_buff, skb->data, pkt_size);
2694 static int rtl8169_rx_interrupt(struct net_device *dev,
2695 struct rtl8169_private *tp,
2696 void __iomem *ioaddr, u32 budget)
2698 unsigned int cur_rx, rx_left;
2699 unsigned int delta, count;
2701 cur_rx = tp->cur_rx;
2702 rx_left = NUM_RX_DESC + tp->dirty_rx - cur_rx;
2703 rx_left = rtl8169_rx_quota(rx_left, budget);
2705 for (; rx_left > 0; rx_left--, cur_rx++) {
2706 unsigned int entry = cur_rx % NUM_RX_DESC;
2707 struct RxDesc *desc = tp->RxDescArray + entry;
2711 status = le32_to_cpu(desc->opts1);
2713 if (status & DescOwn)
2715 if (unlikely(status & RxRES)) {
2716 if (netif_msg_rx_err(tp)) {
2718 "%s: Rx ERROR. status = %08x\n",
2721 tp->stats.rx_errors++;
2722 if (status & (RxRWT | RxRUNT))
2723 tp->stats.rx_length_errors++;
2725 tp->stats.rx_crc_errors++;
2726 if (status & RxFOVF) {
2727 rtl8169_schedule_work(dev, rtl8169_reset_task);
2728 tp->stats.rx_fifo_errors++;
2730 rtl8169_mark_to_asic(desc, tp->rx_buf_sz);
2732 struct sk_buff *skb = tp->Rx_skbuff[entry];
2733 dma_addr_t addr = le64_to_cpu(desc->addr);
2734 int pkt_size = (status & 0x00001FFF) - 4;
2735 struct pci_dev *pdev = tp->pci_dev;
2738 * The driver does not support incoming fragmented
2739 * frames. They are seen as a symptom of over-mtu
2742 if (unlikely(rtl8169_fragmented_frame(status))) {
2743 tp->stats.rx_dropped++;
2744 tp->stats.rx_length_errors++;
2745 rtl8169_mark_to_asic(desc, tp->rx_buf_sz);
2749 rtl8169_rx_csum(skb, desc);
2751 if (rtl8169_try_rx_copy(&skb, tp, pkt_size, addr)) {
2752 pci_dma_sync_single_for_device(pdev, addr,
2753 pkt_size, PCI_DMA_FROMDEVICE);
2754 rtl8169_mark_to_asic(desc, tp->rx_buf_sz);
2756 pci_unmap_single(pdev, addr, pkt_size,
2757 PCI_DMA_FROMDEVICE);
2758 tp->Rx_skbuff[entry] = NULL;
2761 skb_put(skb, pkt_size);
2762 skb->protocol = eth_type_trans(skb, dev);
2764 if (rtl8169_rx_vlan_skb(tp, desc, skb) < 0)
2765 rtl8169_rx_skb(skb);
2767 dev->last_rx = jiffies;
2768 tp->stats.rx_bytes += pkt_size;
2769 tp->stats.rx_packets++;
2772 /* Work around for AMD plateform. */
2773 if ((desc->opts2 & 0xfffe000) &&
2774 (tp->mac_version == RTL_GIGA_MAC_VER_05)) {
2780 count = cur_rx - tp->cur_rx;
2781 tp->cur_rx = cur_rx;
2783 delta = rtl8169_rx_fill(tp, dev, tp->dirty_rx, tp->cur_rx);
2784 if (!delta && count && netif_msg_intr(tp))
2785 printk(KERN_INFO "%s: no Rx buffer allocated\n", dev->name);
2786 tp->dirty_rx += delta;
2789 * FIXME: until there is periodic timer to try and refill the ring,
2790 * a temporary shortage may definitely kill the Rx process.
2791 * - disable the asic to try and avoid an overflow and kick it again
2793 * - how do others driver handle this condition (Uh oh...).
2795 if ((tp->dirty_rx + NUM_RX_DESC == tp->cur_rx) && netif_msg_intr(tp))
2796 printk(KERN_EMERG "%s: Rx buffers exhausted\n", dev->name);
2801 static irqreturn_t rtl8169_interrupt(int irq, void *dev_instance)
2803 struct net_device *dev = dev_instance;
2804 struct rtl8169_private *tp = netdev_priv(dev);
2805 int boguscnt = max_interrupt_work;
2806 void __iomem *ioaddr = tp->mmio_addr;
2811 status = RTL_R16(IntrStatus);
2813 /* hotplug/major error/no more work/shared irq */
2814 if ((status == 0xFFFF) || !status)
2819 if (unlikely(!netif_running(dev))) {
2820 rtl8169_asic_down(ioaddr);
2824 status &= tp->intr_mask;
2826 (status & RxFIFOOver) ? (status | RxOverflow) : status);
2828 if (!(status & tp->intr_event))
2831 /* Work around for rx fifo overflow */
2832 if (unlikely(status & RxFIFOOver) &&
2833 (tp->mac_version == RTL_GIGA_MAC_VER_11)) {
2834 netif_stop_queue(dev);
2835 rtl8169_tx_timeout(dev);
2839 if (unlikely(status & SYSErr)) {
2840 rtl8169_pcierr_interrupt(dev);
2844 if (status & LinkChg)
2845 rtl8169_check_link_status(dev, tp, ioaddr);
2847 #ifdef CONFIG_R8169_NAPI
2848 if (status & tp->napi_event) {
2849 RTL_W16(IntrMask, tp->intr_event & ~tp->napi_event);
2850 tp->intr_mask = ~tp->napi_event;
2852 if (likely(netif_rx_schedule_prep(dev, &tp->napi)))
2853 __netif_rx_schedule(dev, &tp->napi);
2854 else if (netif_msg_intr(tp)) {
2855 printk(KERN_INFO "%s: interrupt %04x in poll\n",
2862 if (status & (RxOK | RxOverflow | RxFIFOOver))
2863 rtl8169_rx_interrupt(dev, tp, ioaddr, ~(u32)0);
2866 if (status & (TxOK | TxErr))
2867 rtl8169_tx_interrupt(dev, tp, ioaddr);
2871 } while (boguscnt > 0);
2873 if (boguscnt <= 0) {
2874 if (netif_msg_intr(tp) && net_ratelimit() ) {
2876 "%s: Too much work at interrupt!\n", dev->name);
2878 /* Clear all interrupt sources. */
2879 RTL_W16(IntrStatus, 0xffff);
2882 return IRQ_RETVAL(handled);
2885 #ifdef CONFIG_R8169_NAPI
2886 static int rtl8169_poll(struct napi_struct *napi, int budget)
2888 struct rtl8169_private *tp = container_of(napi, struct rtl8169_private, napi);
2889 struct net_device *dev = tp->dev;
2890 void __iomem *ioaddr = tp->mmio_addr;
2893 work_done = rtl8169_rx_interrupt(dev, tp, ioaddr, (u32) budget);
2894 rtl8169_tx_interrupt(dev, tp, ioaddr);
2896 if (work_done < budget) {
2897 netif_rx_complete(dev, napi);
2898 tp->intr_mask = 0xffff;
2900 * 20040426: the barrier is not strictly required but the
2901 * behavior of the irq handler could be less predictable
2902 * without it. Btw, the lack of flush for the posted pci
2903 * write is safe - FR
2906 RTL_W16(IntrMask, tp->intr_event);
2913 static void rtl8169_down(struct net_device *dev)
2915 struct rtl8169_private *tp = netdev_priv(dev);
2916 void __iomem *ioaddr = tp->mmio_addr;
2917 unsigned int poll_locked = 0;
2918 unsigned int intrmask;
2920 rtl8169_delete_timer(dev);
2922 netif_stop_queue(dev);
2925 spin_lock_irq(&tp->lock);
2927 rtl8169_asic_down(ioaddr);
2929 /* Update the error counts. */
2930 tp->stats.rx_missed_errors += RTL_R32(RxMissed);
2931 RTL_W32(RxMissed, 0);
2933 spin_unlock_irq(&tp->lock);
2935 synchronize_irq(dev->irq);
2938 napi_disable(&tp->napi);
2942 /* Give a racing hard_start_xmit a few cycles to complete. */
2943 synchronize_sched(); /* FIXME: should this be synchronize_irq()? */
2946 * And now for the 50k$ question: are IRQ disabled or not ?
2948 * Two paths lead here:
2950 * -> netif_running() is available to sync the current code and the
2951 * IRQ handler. See rtl8169_interrupt for details.
2952 * 2) dev->change_mtu
2953 * -> rtl8169_poll can not be issued again and re-enable the
2954 * interruptions. Let's simply issue the IRQ down sequence again.
2956 * No loop if hotpluged or major error (0xffff).
2958 intrmask = RTL_R16(IntrMask);
2959 if (intrmask && (intrmask != 0xffff))
2962 rtl8169_tx_clear(tp);
2964 rtl8169_rx_clear(tp);
2967 static int rtl8169_close(struct net_device *dev)
2969 struct rtl8169_private *tp = netdev_priv(dev);
2970 struct pci_dev *pdev = tp->pci_dev;
2974 free_irq(dev->irq, dev);
2976 pci_free_consistent(pdev, R8169_RX_RING_BYTES, tp->RxDescArray,
2978 pci_free_consistent(pdev, R8169_TX_RING_BYTES, tp->TxDescArray,
2980 tp->TxDescArray = NULL;
2981 tp->RxDescArray = NULL;
2986 static void rtl_set_rx_mode(struct net_device *dev)
2988 struct rtl8169_private *tp = netdev_priv(dev);
2989 void __iomem *ioaddr = tp->mmio_addr;
2990 unsigned long flags;
2991 u32 mc_filter[2]; /* Multicast hash filter */
2995 if (dev->flags & IFF_PROMISC) {
2996 /* Unconditionally log net taps. */
2997 if (netif_msg_link(tp)) {
2998 printk(KERN_NOTICE "%s: Promiscuous mode enabled.\n",
3002 AcceptBroadcast | AcceptMulticast | AcceptMyPhys |
3004 mc_filter[1] = mc_filter[0] = 0xffffffff;
3005 } else if ((dev->mc_count > multicast_filter_limit)
3006 || (dev->flags & IFF_ALLMULTI)) {
3007 /* Too many to filter perfectly -- accept all multicasts. */
3008 rx_mode = AcceptBroadcast | AcceptMulticast | AcceptMyPhys;
3009 mc_filter[1] = mc_filter[0] = 0xffffffff;
3011 struct dev_mc_list *mclist;
3014 rx_mode = AcceptBroadcast | AcceptMyPhys;
3015 mc_filter[1] = mc_filter[0] = 0;
3016 for (i = 0, mclist = dev->mc_list; mclist && i < dev->mc_count;
3017 i++, mclist = mclist->next) {
3018 int bit_nr = ether_crc(ETH_ALEN, mclist->dmi_addr) >> 26;
3019 mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31);
3020 rx_mode |= AcceptMulticast;
3024 spin_lock_irqsave(&tp->lock, flags);
3026 tmp = rtl8169_rx_config | rx_mode |
3027 (RTL_R32(RxConfig) & rtl_chip_info[tp->chipset].RxConfigMask);
3029 if ((tp->mac_version == RTL_GIGA_MAC_VER_11) ||
3030 (tp->mac_version == RTL_GIGA_MAC_VER_12) ||
3031 (tp->mac_version == RTL_GIGA_MAC_VER_13) ||
3032 (tp->mac_version == RTL_GIGA_MAC_VER_14) ||
3033 (tp->mac_version == RTL_GIGA_MAC_VER_15)) {
3034 mc_filter[0] = 0xffffffff;
3035 mc_filter[1] = 0xffffffff;
3038 RTL_W32(MAR0 + 0, mc_filter[0]);
3039 RTL_W32(MAR0 + 4, mc_filter[1]);
3041 RTL_W32(RxConfig, tmp);
3043 spin_unlock_irqrestore(&tp->lock, flags);
3047 * rtl8169_get_stats - Get rtl8169 read/write statistics
3048 * @dev: The Ethernet Device to get statistics for
3050 * Get TX/RX statistics for rtl8169
3052 static struct net_device_stats *rtl8169_get_stats(struct net_device *dev)
3054 struct rtl8169_private *tp = netdev_priv(dev);
3055 void __iomem *ioaddr = tp->mmio_addr;
3056 unsigned long flags;
3058 if (netif_running(dev)) {
3059 spin_lock_irqsave(&tp->lock, flags);
3060 tp->stats.rx_missed_errors += RTL_R32(RxMissed);
3061 RTL_W32(RxMissed, 0);
3062 spin_unlock_irqrestore(&tp->lock, flags);
3070 static int rtl8169_suspend(struct pci_dev *pdev, pm_message_t state)
3072 struct net_device *dev = pci_get_drvdata(pdev);
3073 struct rtl8169_private *tp = netdev_priv(dev);
3074 void __iomem *ioaddr = tp->mmio_addr;
3076 if (!netif_running(dev))
3077 goto out_pci_suspend;
3079 netif_device_detach(dev);
3080 netif_stop_queue(dev);
3082 spin_lock_irq(&tp->lock);
3084 rtl8169_asic_down(ioaddr);
3086 tp->stats.rx_missed_errors += RTL_R32(RxMissed);
3087 RTL_W32(RxMissed, 0);
3089 spin_unlock_irq(&tp->lock);
3092 pci_save_state(pdev);
3093 pci_enable_wake(pdev, pci_choose_state(pdev, state),
3094 (tp->features & RTL_FEATURE_WOL) ? 1 : 0);
3095 pci_set_power_state(pdev, pci_choose_state(pdev, state));
3100 static int rtl8169_resume(struct pci_dev *pdev)
3102 struct net_device *dev = pci_get_drvdata(pdev);
3104 pci_set_power_state(pdev, PCI_D0);
3105 pci_restore_state(pdev);
3106 pci_enable_wake(pdev, PCI_D0, 0);
3108 if (!netif_running(dev))
3111 netif_device_attach(dev);
3113 rtl8169_schedule_work(dev, rtl8169_reset_task);
3118 #endif /* CONFIG_PM */
3120 static struct pci_driver rtl8169_pci_driver = {
3122 .id_table = rtl8169_pci_tbl,
3123 .probe = rtl8169_init_one,
3124 .remove = __devexit_p(rtl8169_remove_one),
3126 .suspend = rtl8169_suspend,
3127 .resume = rtl8169_resume,
3131 static int __init rtl8169_init_module(void)
3133 return pci_register_driver(&rtl8169_pci_driver);
3136 static void __exit rtl8169_cleanup_module(void)
3138 pci_unregister_driver(&rtl8169_pci_driver);
3141 module_init(rtl8169_init_module);
3142 module_exit(rtl8169_cleanup_module);