2 * QLogic QLA3xxx NIC HBA Driver
3 * Copyright (c) 2003-2006 QLogic Corporation
5 * See LICENSE.qla3xxx for copyright and licensing details.
8 #include <linux/kernel.h>
9 #include <linux/init.h>
10 #include <linux/types.h>
11 #include <linux/module.h>
12 #include <linux/list.h>
13 #include <linux/pci.h>
14 #include <linux/dma-mapping.h>
15 #include <linux/sched.h>
16 #include <linux/slab.h>
17 #include <linux/dmapool.h>
18 #include <linux/mempool.h>
19 #include <linux/spinlock.h>
20 #include <linux/kthread.h>
21 #include <linux/interrupt.h>
22 #include <linux/errno.h>
23 #include <linux/ioport.h>
26 #include <linux/if_arp.h>
27 #include <linux/if_ether.h>
28 #include <linux/netdevice.h>
29 #include <linux/etherdevice.h>
30 #include <linux/ethtool.h>
31 #include <linux/skbuff.h>
32 #include <linux/rtnetlink.h>
33 #include <linux/if_vlan.h>
34 #include <linux/init.h>
35 #include <linux/delay.h>
40 #define DRV_NAME "qla3xxx"
41 #define DRV_STRING "QLogic ISP3XXX Network Driver"
42 #define DRV_VERSION "v2.02.00-k36"
43 #define PFX DRV_NAME " "
45 static const char ql3xxx_driver_name[] = DRV_NAME;
46 static const char ql3xxx_driver_version[] = DRV_VERSION;
48 MODULE_AUTHOR("QLogic Corporation");
49 MODULE_DESCRIPTION("QLogic ISP3XXX Network Driver " DRV_VERSION " ");
50 MODULE_LICENSE("GPL");
51 MODULE_VERSION(DRV_VERSION);
53 static const u32 default_msg
54 = NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_LINK
55 | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN;
57 static int debug = -1; /* defaults above */
58 module_param(debug, int, 0);
59 MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
62 module_param(msi, int, 0);
63 MODULE_PARM_DESC(msi, "Turn on Message Signaled Interrupts.");
65 static struct pci_device_id ql3xxx_pci_tbl[] __devinitdata = {
66 {PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, QL3022_DEVICE_ID)},
67 {PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, QL3032_DEVICE_ID)},
68 /* required last entry */
72 MODULE_DEVICE_TABLE(pci, ql3xxx_pci_tbl);
75 * Caller must take hw_lock.
77 static int ql_sem_spinlock(struct ql3_adapter *qdev,
78 u32 sem_mask, u32 sem_bits)
80 struct ql3xxx_port_registers __iomem *port_regs = qdev->mem_map_registers;
82 unsigned int seconds = 3;
85 writel((sem_mask | sem_bits),
86 &port_regs->CommonRegs.semaphoreReg);
87 value = readl(&port_regs->CommonRegs.semaphoreReg);
88 if ((value & (sem_mask >> 16)) == sem_bits)
95 static void ql_sem_unlock(struct ql3_adapter *qdev, u32 sem_mask)
97 struct ql3xxx_port_registers __iomem *port_regs = qdev->mem_map_registers;
98 writel(sem_mask, &port_regs->CommonRegs.semaphoreReg);
99 readl(&port_regs->CommonRegs.semaphoreReg);
102 static int ql_sem_lock(struct ql3_adapter *qdev, u32 sem_mask, u32 sem_bits)
104 struct ql3xxx_port_registers __iomem *port_regs = qdev->mem_map_registers;
107 writel((sem_mask | sem_bits), &port_regs->CommonRegs.semaphoreReg);
108 value = readl(&port_regs->CommonRegs.semaphoreReg);
109 return ((value & (sem_mask >> 16)) == sem_bits);
113 * Caller holds hw_lock.
115 static int ql_wait_for_drvr_lock(struct ql3_adapter *qdev)
120 if (!ql_sem_lock(qdev,
122 (QL_RESOURCE_BITS_BASE_CODE | (qdev->mac_index)
128 printk(KERN_ERR PFX "%s: Timed out waiting for "
134 printk(KERN_DEBUG PFX
135 "%s: driver lock acquired.\n",
142 static void ql_set_register_page(struct ql3_adapter *qdev, u32 page)
144 struct ql3xxx_port_registers __iomem *port_regs = qdev->mem_map_registers;
146 writel(((ISP_CONTROL_NP_MASK << 16) | page),
147 &port_regs->CommonRegs.ispControlStatus);
148 readl(&port_regs->CommonRegs.ispControlStatus);
149 qdev->current_page = page;
152 static u32 ql_read_common_reg_l(struct ql3_adapter *qdev,
156 unsigned long hw_flags;
158 spin_lock_irqsave(&qdev->hw_lock, hw_flags);
160 spin_unlock_irqrestore(&qdev->hw_lock, hw_flags);
165 static u32 ql_read_common_reg(struct ql3_adapter *qdev,
171 static u32 ql_read_page0_reg_l(struct ql3_adapter *qdev, u32 __iomem *reg)
174 unsigned long hw_flags;
176 spin_lock_irqsave(&qdev->hw_lock, hw_flags);
178 if (qdev->current_page != 0)
179 ql_set_register_page(qdev,0);
182 spin_unlock_irqrestore(&qdev->hw_lock, hw_flags);
186 static u32 ql_read_page0_reg(struct ql3_adapter *qdev, u32 __iomem *reg)
188 if (qdev->current_page != 0)
189 ql_set_register_page(qdev,0);
193 static void ql_write_common_reg_l(struct ql3_adapter *qdev,
194 u32 __iomem *reg, u32 value)
196 unsigned long hw_flags;
198 spin_lock_irqsave(&qdev->hw_lock, hw_flags);
201 spin_unlock_irqrestore(&qdev->hw_lock, hw_flags);
205 static void ql_write_common_reg(struct ql3_adapter *qdev,
206 u32 __iomem *reg, u32 value)
213 static void ql_write_nvram_reg(struct ql3_adapter *qdev,
214 u32 __iomem *reg, u32 value)
222 static void ql_write_page0_reg(struct ql3_adapter *qdev,
223 u32 __iomem *reg, u32 value)
225 if (qdev->current_page != 0)
226 ql_set_register_page(qdev,0);
233 * Caller holds hw_lock. Only called during init.
235 static void ql_write_page1_reg(struct ql3_adapter *qdev,
236 u32 __iomem *reg, u32 value)
238 if (qdev->current_page != 1)
239 ql_set_register_page(qdev,1);
246 * Caller holds hw_lock. Only called during init.
248 static void ql_write_page2_reg(struct ql3_adapter *qdev,
249 u32 __iomem *reg, u32 value)
251 if (qdev->current_page != 2)
252 ql_set_register_page(qdev,2);
258 static void ql_disable_interrupts(struct ql3_adapter *qdev)
260 struct ql3xxx_port_registers __iomem *port_regs = qdev->mem_map_registers;
262 ql_write_common_reg_l(qdev, &port_regs->CommonRegs.ispInterruptMaskReg,
263 (ISP_IMR_ENABLE_INT << 16));
267 static void ql_enable_interrupts(struct ql3_adapter *qdev)
269 struct ql3xxx_port_registers __iomem *port_regs = qdev->mem_map_registers;
271 ql_write_common_reg_l(qdev, &port_regs->CommonRegs.ispInterruptMaskReg,
272 ((0xff << 16) | ISP_IMR_ENABLE_INT));
276 static void ql_release_to_lrg_buf_free_list(struct ql3_adapter *qdev,
277 struct ql_rcv_buf_cb *lrg_buf_cb)
280 lrg_buf_cb->next = NULL;
282 if (qdev->lrg_buf_free_tail == NULL) { /* The list is empty */
283 qdev->lrg_buf_free_head = qdev->lrg_buf_free_tail = lrg_buf_cb;
285 qdev->lrg_buf_free_tail->next = lrg_buf_cb;
286 qdev->lrg_buf_free_tail = lrg_buf_cb;
289 if (!lrg_buf_cb->skb) {
290 lrg_buf_cb->skb = netdev_alloc_skb(qdev->ndev,
291 qdev->lrg_buffer_len);
292 if (unlikely(!lrg_buf_cb->skb)) {
293 printk(KERN_ERR PFX "%s: failed netdev_alloc_skb().\n",
295 qdev->lrg_buf_skb_check++;
298 * We save some space to copy the ethhdr from first
301 skb_reserve(lrg_buf_cb->skb, QL_HEADER_SPACE);
302 map = pci_map_single(qdev->pdev,
303 lrg_buf_cb->skb->data,
304 qdev->lrg_buffer_len -
307 lrg_buf_cb->buf_phy_addr_low =
308 cpu_to_le32(LS_64BITS(map));
309 lrg_buf_cb->buf_phy_addr_high =
310 cpu_to_le32(MS_64BITS(map));
311 pci_unmap_addr_set(lrg_buf_cb, mapaddr, map);
312 pci_unmap_len_set(lrg_buf_cb, maplen,
313 qdev->lrg_buffer_len -
318 qdev->lrg_buf_free_count++;
321 static struct ql_rcv_buf_cb *ql_get_from_lrg_buf_free_list(struct ql3_adapter
324 struct ql_rcv_buf_cb *lrg_buf_cb;
326 if ((lrg_buf_cb = qdev->lrg_buf_free_head) != NULL) {
327 if ((qdev->lrg_buf_free_head = lrg_buf_cb->next) == NULL)
328 qdev->lrg_buf_free_tail = NULL;
329 qdev->lrg_buf_free_count--;
335 static u32 addrBits = EEPROM_NO_ADDR_BITS;
336 static u32 dataBits = EEPROM_NO_DATA_BITS;
338 static void fm93c56a_deselect(struct ql3_adapter *qdev);
339 static void eeprom_readword(struct ql3_adapter *qdev, u32 eepromAddr,
340 unsigned short *value);
343 * Caller holds hw_lock.
345 static void fm93c56a_select(struct ql3_adapter *qdev)
347 struct ql3xxx_port_registers __iomem *port_regs =
348 qdev->mem_map_registers;
350 qdev->eeprom_cmd_data = AUBURN_EEPROM_CS_1;
351 ql_write_nvram_reg(qdev, &port_regs->CommonRegs.serialPortInterfaceReg,
352 ISP_NVRAM_MASK | qdev->eeprom_cmd_data);
353 ql_write_nvram_reg(qdev, &port_regs->CommonRegs.serialPortInterfaceReg,
354 ((ISP_NVRAM_MASK << 16) | qdev->eeprom_cmd_data));
358 * Caller holds hw_lock.
360 static void fm93c56a_cmd(struct ql3_adapter *qdev, u32 cmd, u32 eepromAddr)
366 struct ql3xxx_port_registers __iomem *port_regs =
367 qdev->mem_map_registers;
369 /* Clock in a zero, then do the start bit */
370 ql_write_nvram_reg(qdev, &port_regs->CommonRegs.serialPortInterfaceReg,
371 ISP_NVRAM_MASK | qdev->eeprom_cmd_data |
373 ql_write_nvram_reg(qdev, &port_regs->CommonRegs.serialPortInterfaceReg,
374 ISP_NVRAM_MASK | qdev->
375 eeprom_cmd_data | AUBURN_EEPROM_DO_1 |
376 AUBURN_EEPROM_CLK_RISE);
377 ql_write_nvram_reg(qdev, &port_regs->CommonRegs.serialPortInterfaceReg,
378 ISP_NVRAM_MASK | qdev->
379 eeprom_cmd_data | AUBURN_EEPROM_DO_1 |
380 AUBURN_EEPROM_CLK_FALL);
382 mask = 1 << (FM93C56A_CMD_BITS - 1);
383 /* Force the previous data bit to be different */
384 previousBit = 0xffff;
385 for (i = 0; i < FM93C56A_CMD_BITS; i++) {
387 (cmd & mask) ? AUBURN_EEPROM_DO_1 : AUBURN_EEPROM_DO_0;
388 if (previousBit != dataBit) {
390 * If the bit changed, then change the DO state to
393 ql_write_nvram_reg(qdev,
394 &port_regs->CommonRegs.
395 serialPortInterfaceReg,
396 ISP_NVRAM_MASK | qdev->
397 eeprom_cmd_data | dataBit);
398 previousBit = dataBit;
400 ql_write_nvram_reg(qdev,
401 &port_regs->CommonRegs.
402 serialPortInterfaceReg,
403 ISP_NVRAM_MASK | qdev->
404 eeprom_cmd_data | dataBit |
405 AUBURN_EEPROM_CLK_RISE);
406 ql_write_nvram_reg(qdev,
407 &port_regs->CommonRegs.
408 serialPortInterfaceReg,
409 ISP_NVRAM_MASK | qdev->
410 eeprom_cmd_data | dataBit |
411 AUBURN_EEPROM_CLK_FALL);
415 mask = 1 << (addrBits - 1);
416 /* Force the previous data bit to be different */
417 previousBit = 0xffff;
418 for (i = 0; i < addrBits; i++) {
420 (eepromAddr & mask) ? AUBURN_EEPROM_DO_1 :
422 if (previousBit != dataBit) {
424 * If the bit changed, then change the DO state to
427 ql_write_nvram_reg(qdev,
428 &port_regs->CommonRegs.
429 serialPortInterfaceReg,
430 ISP_NVRAM_MASK | qdev->
431 eeprom_cmd_data | dataBit);
432 previousBit = dataBit;
434 ql_write_nvram_reg(qdev,
435 &port_regs->CommonRegs.
436 serialPortInterfaceReg,
437 ISP_NVRAM_MASK | qdev->
438 eeprom_cmd_data | dataBit |
439 AUBURN_EEPROM_CLK_RISE);
440 ql_write_nvram_reg(qdev,
441 &port_regs->CommonRegs.
442 serialPortInterfaceReg,
443 ISP_NVRAM_MASK | qdev->
444 eeprom_cmd_data | dataBit |
445 AUBURN_EEPROM_CLK_FALL);
446 eepromAddr = eepromAddr << 1;
451 * Caller holds hw_lock.
453 static void fm93c56a_deselect(struct ql3_adapter *qdev)
455 struct ql3xxx_port_registers __iomem *port_regs =
456 qdev->mem_map_registers;
457 qdev->eeprom_cmd_data = AUBURN_EEPROM_CS_0;
458 ql_write_nvram_reg(qdev, &port_regs->CommonRegs.serialPortInterfaceReg,
459 ISP_NVRAM_MASK | qdev->eeprom_cmd_data);
463 * Caller holds hw_lock.
465 static void fm93c56a_datain(struct ql3_adapter *qdev, unsigned short *value)
470 struct ql3xxx_port_registers __iomem *port_regs =
471 qdev->mem_map_registers;
473 /* Read the data bits */
474 /* The first bit is a dummy. Clock right over it. */
475 for (i = 0; i < dataBits; i++) {
476 ql_write_nvram_reg(qdev,
477 &port_regs->CommonRegs.
478 serialPortInterfaceReg,
479 ISP_NVRAM_MASK | qdev->eeprom_cmd_data |
480 AUBURN_EEPROM_CLK_RISE);
481 ql_write_nvram_reg(qdev,
482 &port_regs->CommonRegs.
483 serialPortInterfaceReg,
484 ISP_NVRAM_MASK | qdev->eeprom_cmd_data |
485 AUBURN_EEPROM_CLK_FALL);
489 &port_regs->CommonRegs.
490 serialPortInterfaceReg) & AUBURN_EEPROM_DI_1) ? 1 : 0;
491 data = (data << 1) | dataBit;
497 * Caller holds hw_lock.
499 static void eeprom_readword(struct ql3_adapter *qdev,
500 u32 eepromAddr, unsigned short *value)
502 fm93c56a_select(qdev);
503 fm93c56a_cmd(qdev, (int)FM93C56A_READ, eepromAddr);
504 fm93c56a_datain(qdev, value);
505 fm93c56a_deselect(qdev);
508 static void ql_swap_mac_addr(u8 * macAddress)
512 temp = macAddress[0];
513 macAddress[0] = macAddress[1];
514 macAddress[1] = temp;
515 temp = macAddress[2];
516 macAddress[2] = macAddress[3];
517 macAddress[3] = temp;
518 temp = macAddress[4];
519 macAddress[4] = macAddress[5];
520 macAddress[5] = temp;
524 static int ql_get_nvram_params(struct ql3_adapter *qdev)
529 unsigned long hw_flags;
531 spin_lock_irqsave(&qdev->hw_lock, hw_flags);
533 pEEPROMData = (u16 *) & qdev->nvram_data;
534 qdev->eeprom_cmd_data = 0;
535 if(ql_sem_spinlock(qdev, QL_NVRAM_SEM_MASK,
536 (QL_RESOURCE_BITS_BASE_CODE | (qdev->mac_index) *
538 printk(KERN_ERR PFX"%s: Failed ql_sem_spinlock().\n",
540 spin_unlock_irqrestore(&qdev->hw_lock, hw_flags);
544 for (index = 0; index < EEPROM_SIZE; index++) {
545 eeprom_readword(qdev, index, pEEPROMData);
546 checksum += *pEEPROMData;
549 ql_sem_unlock(qdev, QL_NVRAM_SEM_MASK);
552 printk(KERN_ERR PFX "%s: checksum should be zero, is %x!!\n",
553 qdev->ndev->name, checksum);
554 spin_unlock_irqrestore(&qdev->hw_lock, hw_flags);
559 * We have a problem with endianness for the MAC addresses
560 * and the two 8-bit values version, and numPorts. We
561 * have to swap them on big endian systems.
563 ql_swap_mac_addr(qdev->nvram_data.funcCfg_fn0.macAddress);
564 ql_swap_mac_addr(qdev->nvram_data.funcCfg_fn1.macAddress);
565 ql_swap_mac_addr(qdev->nvram_data.funcCfg_fn2.macAddress);
566 ql_swap_mac_addr(qdev->nvram_data.funcCfg_fn3.macAddress);
567 pEEPROMData = (u16 *) & qdev->nvram_data.version;
568 *pEEPROMData = le16_to_cpu(*pEEPROMData);
570 spin_unlock_irqrestore(&qdev->hw_lock, hw_flags);
574 static const u32 PHYAddr[2] = {
575 PORT0_PHY_ADDRESS, PORT1_PHY_ADDRESS
578 static int ql_wait_for_mii_ready(struct ql3_adapter *qdev)
580 struct ql3xxx_port_registers __iomem *port_regs =
581 qdev->mem_map_registers;
586 temp = ql_read_page0_reg(qdev, &port_regs->macMIIStatusReg);
587 if (!(temp & MAC_MII_STATUS_BSY))
595 static void ql_mii_enable_scan_mode(struct ql3_adapter *qdev)
597 struct ql3xxx_port_registers __iomem *port_regs =
598 qdev->mem_map_registers;
601 if (qdev->numPorts > 1) {
602 /* Auto scan will cycle through multiple ports */
603 scanControl = MAC_MII_CONTROL_AS | MAC_MII_CONTROL_SC;
605 scanControl = MAC_MII_CONTROL_SC;
609 * Scan register 1 of PHY/PETBI,
610 * Set up to scan both devices
611 * The autoscan starts from the first register, completes
612 * the last one before rolling over to the first
614 ql_write_page0_reg(qdev, &port_regs->macMIIMgmtAddrReg,
615 PHYAddr[0] | MII_SCAN_REGISTER);
617 ql_write_page0_reg(qdev, &port_regs->macMIIMgmtControlReg,
619 ((MAC_MII_CONTROL_SC | MAC_MII_CONTROL_AS) << 16));
622 static u8 ql_mii_disable_scan_mode(struct ql3_adapter *qdev)
625 struct ql3xxx_port_registers __iomem *port_regs =
626 qdev->mem_map_registers;
628 /* See if scan mode is enabled before we turn it off */
629 if (ql_read_page0_reg(qdev, &port_regs->macMIIMgmtControlReg) &
630 (MAC_MII_CONTROL_AS | MAC_MII_CONTROL_SC)) {
631 /* Scan is enabled */
634 /* Scan is disabled */
639 * When disabling scan mode you must first change the MII register
642 ql_write_page0_reg(qdev, &port_regs->macMIIMgmtAddrReg,
643 PHYAddr[0] | MII_SCAN_REGISTER);
645 ql_write_page0_reg(qdev, &port_regs->macMIIMgmtControlReg,
646 ((MAC_MII_CONTROL_SC | MAC_MII_CONTROL_AS |
647 MAC_MII_CONTROL_RC) << 16));
652 static int ql_mii_write_reg_ex(struct ql3_adapter *qdev,
653 u16 regAddr, u16 value, u32 mac_index)
655 struct ql3xxx_port_registers __iomem *port_regs =
656 qdev->mem_map_registers;
659 scanWasEnabled = ql_mii_disable_scan_mode(qdev);
661 if (ql_wait_for_mii_ready(qdev)) {
662 if (netif_msg_link(qdev))
663 printk(KERN_WARNING PFX
664 "%s Timed out waiting for management port to "
665 "get free before issuing command.\n",
670 ql_write_page0_reg(qdev, &port_regs->macMIIMgmtAddrReg,
671 PHYAddr[mac_index] | regAddr);
673 ql_write_page0_reg(qdev, &port_regs->macMIIMgmtDataReg, value);
675 /* Wait for write to complete 9/10/04 SJP */
676 if (ql_wait_for_mii_ready(qdev)) {
677 if (netif_msg_link(qdev))
678 printk(KERN_WARNING PFX
679 "%s: Timed out waiting for management port to"
680 "get free before issuing command.\n",
686 ql_mii_enable_scan_mode(qdev);
691 static int ql_mii_read_reg_ex(struct ql3_adapter *qdev, u16 regAddr,
692 u16 * value, u32 mac_index)
694 struct ql3xxx_port_registers __iomem *port_regs =
695 qdev->mem_map_registers;
699 scanWasEnabled = ql_mii_disable_scan_mode(qdev);
701 if (ql_wait_for_mii_ready(qdev)) {
702 if (netif_msg_link(qdev))
703 printk(KERN_WARNING PFX
704 "%s: Timed out waiting for management port to "
705 "get free before issuing command.\n",
710 ql_write_page0_reg(qdev, &port_regs->macMIIMgmtAddrReg,
711 PHYAddr[mac_index] | regAddr);
713 ql_write_page0_reg(qdev, &port_regs->macMIIMgmtControlReg,
714 (MAC_MII_CONTROL_RC << 16));
716 ql_write_page0_reg(qdev, &port_regs->macMIIMgmtControlReg,
717 (MAC_MII_CONTROL_RC << 16) | MAC_MII_CONTROL_RC);
719 /* Wait for the read to complete */
720 if (ql_wait_for_mii_ready(qdev)) {
721 if (netif_msg_link(qdev))
722 printk(KERN_WARNING PFX
723 "%s: Timed out waiting for management port to "
724 "get free after issuing command.\n",
729 temp = ql_read_page0_reg(qdev, &port_regs->macMIIMgmtDataReg);
733 ql_mii_enable_scan_mode(qdev);
738 static int ql_mii_write_reg(struct ql3_adapter *qdev, u16 regAddr, u16 value)
740 struct ql3xxx_port_registers __iomem *port_regs =
741 qdev->mem_map_registers;
743 ql_mii_disable_scan_mode(qdev);
745 if (ql_wait_for_mii_ready(qdev)) {
746 if (netif_msg_link(qdev))
747 printk(KERN_WARNING PFX
748 "%s: Timed out waiting for management port to "
749 "get free before issuing command.\n",
754 ql_write_page0_reg(qdev, &port_regs->macMIIMgmtAddrReg,
755 qdev->PHYAddr | regAddr);
757 ql_write_page0_reg(qdev, &port_regs->macMIIMgmtDataReg, value);
759 /* Wait for write to complete. */
760 if (ql_wait_for_mii_ready(qdev)) {
761 if (netif_msg_link(qdev))
762 printk(KERN_WARNING PFX
763 "%s: Timed out waiting for management port to "
764 "get free before issuing command.\n",
769 ql_mii_enable_scan_mode(qdev);
774 static int ql_mii_read_reg(struct ql3_adapter *qdev, u16 regAddr, u16 *value)
777 struct ql3xxx_port_registers __iomem *port_regs =
778 qdev->mem_map_registers;
780 ql_mii_disable_scan_mode(qdev);
782 if (ql_wait_for_mii_ready(qdev)) {
783 if (netif_msg_link(qdev))
784 printk(KERN_WARNING PFX
785 "%s: Timed out waiting for management port to "
786 "get free before issuing command.\n",
791 ql_write_page0_reg(qdev, &port_regs->macMIIMgmtAddrReg,
792 qdev->PHYAddr | regAddr);
794 ql_write_page0_reg(qdev, &port_regs->macMIIMgmtControlReg,
795 (MAC_MII_CONTROL_RC << 16));
797 ql_write_page0_reg(qdev, &port_regs->macMIIMgmtControlReg,
798 (MAC_MII_CONTROL_RC << 16) | MAC_MII_CONTROL_RC);
800 /* Wait for the read to complete */
801 if (ql_wait_for_mii_ready(qdev)) {
802 if (netif_msg_link(qdev))
803 printk(KERN_WARNING PFX
804 "%s: Timed out waiting for management port to "
805 "get free before issuing command.\n",
810 temp = ql_read_page0_reg(qdev, &port_regs->macMIIMgmtDataReg);
813 ql_mii_enable_scan_mode(qdev);
818 static void ql_petbi_reset(struct ql3_adapter *qdev)
820 ql_mii_write_reg(qdev, PETBI_CONTROL_REG, PETBI_CTRL_SOFT_RESET);
823 static void ql_petbi_start_neg(struct ql3_adapter *qdev)
827 /* Enable Auto-negotiation sense */
828 ql_mii_read_reg(qdev, PETBI_TBI_CTRL, ®);
829 reg |= PETBI_TBI_AUTO_SENSE;
830 ql_mii_write_reg(qdev, PETBI_TBI_CTRL, reg);
832 ql_mii_write_reg(qdev, PETBI_NEG_ADVER,
833 PETBI_NEG_PAUSE | PETBI_NEG_DUPLEX);
835 ql_mii_write_reg(qdev, PETBI_CONTROL_REG,
836 PETBI_CTRL_AUTO_NEG | PETBI_CTRL_RESTART_NEG |
837 PETBI_CTRL_FULL_DUPLEX | PETBI_CTRL_SPEED_1000);
841 static void ql_petbi_reset_ex(struct ql3_adapter *qdev, u32 mac_index)
843 ql_mii_write_reg_ex(qdev, PETBI_CONTROL_REG, PETBI_CTRL_SOFT_RESET,
847 static void ql_petbi_start_neg_ex(struct ql3_adapter *qdev, u32 mac_index)
851 /* Enable Auto-negotiation sense */
852 ql_mii_read_reg_ex(qdev, PETBI_TBI_CTRL, ®, mac_index);
853 reg |= PETBI_TBI_AUTO_SENSE;
854 ql_mii_write_reg_ex(qdev, PETBI_TBI_CTRL, reg, mac_index);
856 ql_mii_write_reg_ex(qdev, PETBI_NEG_ADVER,
857 PETBI_NEG_PAUSE | PETBI_NEG_DUPLEX, mac_index);
859 ql_mii_write_reg_ex(qdev, PETBI_CONTROL_REG,
860 PETBI_CTRL_AUTO_NEG | PETBI_CTRL_RESTART_NEG |
861 PETBI_CTRL_FULL_DUPLEX | PETBI_CTRL_SPEED_1000,
865 static void ql_petbi_init(struct ql3_adapter *qdev)
867 ql_petbi_reset(qdev);
868 ql_petbi_start_neg(qdev);
871 static void ql_petbi_init_ex(struct ql3_adapter *qdev, u32 mac_index)
873 ql_petbi_reset_ex(qdev, mac_index);
874 ql_petbi_start_neg_ex(qdev, mac_index);
877 static int ql_is_petbi_neg_pause(struct ql3_adapter *qdev)
881 if (ql_mii_read_reg(qdev, PETBI_NEG_PARTNER, ®) < 0)
884 return (reg & PETBI_NEG_PAUSE_MASK) == PETBI_NEG_PAUSE;
887 static int ql_phy_get_speed(struct ql3_adapter *qdev)
891 if (ql_mii_read_reg(qdev, AUX_CONTROL_STATUS, ®) < 0)
894 reg = (((reg & 0x18) >> 3) & 3);
906 static int ql_is_full_dup(struct ql3_adapter *qdev)
910 if (ql_mii_read_reg(qdev, AUX_CONTROL_STATUS, ®) < 0)
913 return (reg & PHY_AUX_DUPLEX_STAT) != 0;
916 static int ql_is_phy_neg_pause(struct ql3_adapter *qdev)
920 if (ql_mii_read_reg(qdev, PHY_NEG_PARTNER, ®) < 0)
923 return (reg & PHY_NEG_PAUSE) != 0;
927 * Caller holds hw_lock.
929 static void ql_mac_enable(struct ql3_adapter *qdev, u32 enable)
931 struct ql3xxx_port_registers __iomem *port_regs =
932 qdev->mem_map_registers;
936 value = (MAC_CONFIG_REG_PE | (MAC_CONFIG_REG_PE << 16));
938 value = (MAC_CONFIG_REG_PE << 16);
941 ql_write_page0_reg(qdev, &port_regs->mac1ConfigReg, value);
943 ql_write_page0_reg(qdev, &port_regs->mac0ConfigReg, value);
947 * Caller holds hw_lock.
949 static void ql_mac_cfg_soft_reset(struct ql3_adapter *qdev, u32 enable)
951 struct ql3xxx_port_registers __iomem *port_regs =
952 qdev->mem_map_registers;
956 value = (MAC_CONFIG_REG_SR | (MAC_CONFIG_REG_SR << 16));
958 value = (MAC_CONFIG_REG_SR << 16);
961 ql_write_page0_reg(qdev, &port_regs->mac1ConfigReg, value);
963 ql_write_page0_reg(qdev, &port_regs->mac0ConfigReg, value);
967 * Caller holds hw_lock.
969 static void ql_mac_cfg_gig(struct ql3_adapter *qdev, u32 enable)
971 struct ql3xxx_port_registers __iomem *port_regs =
972 qdev->mem_map_registers;
976 value = (MAC_CONFIG_REG_GM | (MAC_CONFIG_REG_GM << 16));
978 value = (MAC_CONFIG_REG_GM << 16);
981 ql_write_page0_reg(qdev, &port_regs->mac1ConfigReg, value);
983 ql_write_page0_reg(qdev, &port_regs->mac0ConfigReg, value);
987 * Caller holds hw_lock.
989 static void ql_mac_cfg_full_dup(struct ql3_adapter *qdev, u32 enable)
991 struct ql3xxx_port_registers __iomem *port_regs =
992 qdev->mem_map_registers;
996 value = (MAC_CONFIG_REG_FD | (MAC_CONFIG_REG_FD << 16));
998 value = (MAC_CONFIG_REG_FD << 16);
1000 if (qdev->mac_index)
1001 ql_write_page0_reg(qdev, &port_regs->mac1ConfigReg, value);
1003 ql_write_page0_reg(qdev, &port_regs->mac0ConfigReg, value);
1007 * Caller holds hw_lock.
1009 static void ql_mac_cfg_pause(struct ql3_adapter *qdev, u32 enable)
1011 struct ql3xxx_port_registers __iomem *port_regs =
1012 qdev->mem_map_registers;
1017 ((MAC_CONFIG_REG_TF | MAC_CONFIG_REG_RF) |
1018 ((MAC_CONFIG_REG_TF | MAC_CONFIG_REG_RF) << 16));
1020 value = ((MAC_CONFIG_REG_TF | MAC_CONFIG_REG_RF) << 16);
1022 if (qdev->mac_index)
1023 ql_write_page0_reg(qdev, &port_regs->mac1ConfigReg, value);
1025 ql_write_page0_reg(qdev, &port_regs->mac0ConfigReg, value);
1029 * Caller holds hw_lock.
1031 static int ql_is_fiber(struct ql3_adapter *qdev)
1033 struct ql3xxx_port_registers __iomem *port_regs =
1034 qdev->mem_map_registers;
1038 switch (qdev->mac_index) {
1040 bitToCheck = PORT_STATUS_SM0;
1043 bitToCheck = PORT_STATUS_SM1;
1047 temp = ql_read_page0_reg(qdev, &port_regs->portStatus);
1048 return (temp & bitToCheck) != 0;
1051 static int ql_is_auto_cfg(struct ql3_adapter *qdev)
1054 ql_mii_read_reg(qdev, 0x00, ®);
1055 return (reg & 0x1000) != 0;
1059 * Caller holds hw_lock.
1061 static int ql_is_auto_neg_complete(struct ql3_adapter *qdev)
1063 struct ql3xxx_port_registers __iomem *port_regs =
1064 qdev->mem_map_registers;
1068 switch (qdev->mac_index) {
1070 bitToCheck = PORT_STATUS_AC0;
1073 bitToCheck = PORT_STATUS_AC1;
1077 temp = ql_read_page0_reg(qdev, &port_regs->portStatus);
1078 if (temp & bitToCheck) {
1079 if (netif_msg_link(qdev))
1080 printk(KERN_INFO PFX
1081 "%s: Auto-Negotiate complete.\n",
1085 if (netif_msg_link(qdev))
1086 printk(KERN_WARNING PFX
1087 "%s: Auto-Negotiate incomplete.\n",
1094 * ql_is_neg_pause() returns 1 if pause was negotiated to be on
1096 static int ql_is_neg_pause(struct ql3_adapter *qdev)
1098 if (ql_is_fiber(qdev))
1099 return ql_is_petbi_neg_pause(qdev);
1101 return ql_is_phy_neg_pause(qdev);
1104 static int ql_auto_neg_error(struct ql3_adapter *qdev)
1106 struct ql3xxx_port_registers __iomem *port_regs =
1107 qdev->mem_map_registers;
1111 switch (qdev->mac_index) {
1113 bitToCheck = PORT_STATUS_AE0;
1116 bitToCheck = PORT_STATUS_AE1;
1119 temp = ql_read_page0_reg(qdev, &port_regs->portStatus);
1120 return (temp & bitToCheck) != 0;
1123 static u32 ql_get_link_speed(struct ql3_adapter *qdev)
1125 if (ql_is_fiber(qdev))
1128 return ql_phy_get_speed(qdev);
1131 static int ql_is_link_full_dup(struct ql3_adapter *qdev)
1133 if (ql_is_fiber(qdev))
1136 return ql_is_full_dup(qdev);
1140 * Caller holds hw_lock.
1142 static int ql_link_down_detect(struct ql3_adapter *qdev)
1144 struct ql3xxx_port_registers __iomem *port_regs =
1145 qdev->mem_map_registers;
1149 switch (qdev->mac_index) {
1151 bitToCheck = ISP_CONTROL_LINK_DN_0;
1154 bitToCheck = ISP_CONTROL_LINK_DN_1;
1159 ql_read_common_reg(qdev, &port_regs->CommonRegs.ispControlStatus);
1160 return (temp & bitToCheck) != 0;
1164 * Caller holds hw_lock.
1166 static int ql_link_down_detect_clear(struct ql3_adapter *qdev)
1168 struct ql3xxx_port_registers __iomem *port_regs =
1169 qdev->mem_map_registers;
1171 switch (qdev->mac_index) {
1173 ql_write_common_reg(qdev,
1174 &port_regs->CommonRegs.ispControlStatus,
1175 (ISP_CONTROL_LINK_DN_0) |
1176 (ISP_CONTROL_LINK_DN_0 << 16));
1180 ql_write_common_reg(qdev,
1181 &port_regs->CommonRegs.ispControlStatus,
1182 (ISP_CONTROL_LINK_DN_1) |
1183 (ISP_CONTROL_LINK_DN_1 << 16));
1194 * Caller holds hw_lock.
1196 static int ql_this_adapter_controls_port(struct ql3_adapter *qdev,
1199 struct ql3xxx_port_registers __iomem *port_regs =
1200 qdev->mem_map_registers;
1204 switch (mac_index) {
1206 bitToCheck = PORT_STATUS_F1_ENABLED;
1209 bitToCheck = PORT_STATUS_F3_ENABLED;
1215 temp = ql_read_page0_reg(qdev, &port_regs->portStatus);
1216 if (temp & bitToCheck) {
1217 if (netif_msg_link(qdev))
1218 printk(KERN_DEBUG PFX
1219 "%s: is not link master.\n", qdev->ndev->name);
1222 if (netif_msg_link(qdev))
1223 printk(KERN_DEBUG PFX
1224 "%s: is link master.\n", qdev->ndev->name);
1229 static void ql_phy_reset_ex(struct ql3_adapter *qdev, u32 mac_index)
1231 ql_mii_write_reg_ex(qdev, CONTROL_REG, PHY_CTRL_SOFT_RESET, mac_index);
1234 static void ql_phy_start_neg_ex(struct ql3_adapter *qdev, u32 mac_index)
1238 ql_mii_write_reg_ex(qdev, PHY_NEG_ADVER,
1239 PHY_NEG_PAUSE | PHY_NEG_ADV_SPEED | 1, mac_index);
1241 ql_mii_read_reg_ex(qdev, CONTROL_REG, ®, mac_index);
1242 ql_mii_write_reg_ex(qdev, CONTROL_REG, reg | PHY_CTRL_RESTART_NEG,
1246 static void ql_phy_init_ex(struct ql3_adapter *qdev, u32 mac_index)
1248 ql_phy_reset_ex(qdev, mac_index);
1249 ql_phy_start_neg_ex(qdev, mac_index);
1253 * Caller holds hw_lock.
1255 static u32 ql_get_link_state(struct ql3_adapter *qdev)
1257 struct ql3xxx_port_registers __iomem *port_regs =
1258 qdev->mem_map_registers;
1260 u32 temp, linkState;
1262 switch (qdev->mac_index) {
1264 bitToCheck = PORT_STATUS_UP0;
1267 bitToCheck = PORT_STATUS_UP1;
1270 temp = ql_read_page0_reg(qdev, &port_regs->portStatus);
1271 if (temp & bitToCheck) {
1274 linkState = LS_DOWN;
1275 if (netif_msg_link(qdev))
1276 printk(KERN_WARNING PFX
1277 "%s: Link is down.\n", qdev->ndev->name);
1282 static int ql_port_start(struct ql3_adapter *qdev)
1284 if(ql_sem_spinlock(qdev, QL_PHY_GIO_SEM_MASK,
1285 (QL_RESOURCE_BITS_BASE_CODE | (qdev->mac_index) *
1289 if (ql_is_fiber(qdev)) {
1290 ql_petbi_init(qdev);
1293 ql_phy_init_ex(qdev, qdev->mac_index);
1296 ql_sem_unlock(qdev, QL_PHY_GIO_SEM_MASK);
1300 static int ql_finish_auto_neg(struct ql3_adapter *qdev)
1303 if(ql_sem_spinlock(qdev, QL_PHY_GIO_SEM_MASK,
1304 (QL_RESOURCE_BITS_BASE_CODE | (qdev->mac_index) *
1308 if (!ql_auto_neg_error(qdev)) {
1309 if (test_bit(QL_LINK_MASTER,&qdev->flags)) {
1310 /* configure the MAC */
1311 if (netif_msg_link(qdev))
1312 printk(KERN_DEBUG PFX
1313 "%s: Configuring link.\n",
1316 ql_mac_cfg_soft_reset(qdev, 1);
1317 ql_mac_cfg_gig(qdev,
1321 ql_mac_cfg_full_dup(qdev,
1324 ql_mac_cfg_pause(qdev,
1327 ql_mac_cfg_soft_reset(qdev, 0);
1329 /* enable the MAC */
1330 if (netif_msg_link(qdev))
1331 printk(KERN_DEBUG PFX
1332 "%s: Enabling mac.\n",
1335 ql_mac_enable(qdev, 1);
1338 if (netif_msg_link(qdev))
1339 printk(KERN_DEBUG PFX
1340 "%s: Change port_link_state LS_DOWN to LS_UP.\n",
1342 qdev->port_link_state = LS_UP;
1343 netif_start_queue(qdev->ndev);
1344 netif_carrier_on(qdev->ndev);
1345 if (netif_msg_link(qdev))
1346 printk(KERN_INFO PFX
1347 "%s: Link is up at %d Mbps, %s duplex.\n",
1349 ql_get_link_speed(qdev),
1350 ql_is_link_full_dup(qdev)
1353 } else { /* Remote error detected */
1355 if (test_bit(QL_LINK_MASTER,&qdev->flags)) {
1356 if (netif_msg_link(qdev))
1357 printk(KERN_DEBUG PFX
1358 "%s: Remote error detected. "
1359 "Calling ql_port_start().\n",
1363 * ql_port_start() is shared code and needs
1364 * to lock the PHY on it's own.
1366 ql_sem_unlock(qdev, QL_PHY_GIO_SEM_MASK);
1367 if(ql_port_start(qdev)) {/* Restart port */
1373 ql_sem_unlock(qdev, QL_PHY_GIO_SEM_MASK);
1377 static void ql_link_state_machine(struct ql3_adapter *qdev)
1379 u32 curr_link_state;
1380 unsigned long hw_flags;
1382 spin_lock_irqsave(&qdev->hw_lock, hw_flags);
1384 curr_link_state = ql_get_link_state(qdev);
1386 if (test_bit(QL_RESET_ACTIVE,&qdev->flags)) {
1387 if (netif_msg_link(qdev))
1388 printk(KERN_INFO PFX
1389 "%s: Reset in progress, skip processing link "
1390 "state.\n", qdev->ndev->name);
1392 spin_unlock_irqrestore(&qdev->hw_lock, hw_flags);
1396 switch (qdev->port_link_state) {
1398 if (test_bit(QL_LINK_MASTER,&qdev->flags)) {
1399 ql_port_start(qdev);
1401 qdev->port_link_state = LS_DOWN;
1405 if (netif_msg_link(qdev))
1406 printk(KERN_DEBUG PFX
1407 "%s: port_link_state = LS_DOWN.\n",
1409 if (curr_link_state == LS_UP) {
1410 if (netif_msg_link(qdev))
1411 printk(KERN_DEBUG PFX
1412 "%s: curr_link_state = LS_UP.\n",
1414 if (ql_is_auto_neg_complete(qdev))
1415 ql_finish_auto_neg(qdev);
1417 if (qdev->port_link_state == LS_UP)
1418 ql_link_down_detect_clear(qdev);
1425 * See if the link is currently down or went down and came
1428 if ((curr_link_state == LS_DOWN) || ql_link_down_detect(qdev)) {
1429 if (netif_msg_link(qdev))
1430 printk(KERN_INFO PFX "%s: Link is down.\n",
1432 qdev->port_link_state = LS_DOWN;
1436 spin_unlock_irqrestore(&qdev->hw_lock, hw_flags);
1440 * Caller must take hw_lock and QL_PHY_GIO_SEM.
1442 static void ql_get_phy_owner(struct ql3_adapter *qdev)
1444 if (ql_this_adapter_controls_port(qdev, qdev->mac_index))
1445 set_bit(QL_LINK_MASTER,&qdev->flags);
1447 clear_bit(QL_LINK_MASTER,&qdev->flags);
1451 * Caller must take hw_lock and QL_PHY_GIO_SEM.
1453 static void ql_init_scan_mode(struct ql3_adapter *qdev)
1455 ql_mii_enable_scan_mode(qdev);
1457 if (test_bit(QL_LINK_OPTICAL,&qdev->flags)) {
1458 if (ql_this_adapter_controls_port(qdev, qdev->mac_index))
1459 ql_petbi_init_ex(qdev, qdev->mac_index);
1461 if (ql_this_adapter_controls_port(qdev, qdev->mac_index))
1462 ql_phy_init_ex(qdev, qdev->mac_index);
1467 * MII_Setup needs to be called before taking the PHY out of reset so that the
1468 * management interface clock speed can be set properly. It would be better if
1469 * we had a way to disable MDC until after the PHY is out of reset, but we
1470 * don't have that capability.
1472 static int ql_mii_setup(struct ql3_adapter *qdev)
1475 struct ql3xxx_port_registers __iomem *port_regs =
1476 qdev->mem_map_registers;
1478 if(ql_sem_spinlock(qdev, QL_PHY_GIO_SEM_MASK,
1479 (QL_RESOURCE_BITS_BASE_CODE | (qdev->mac_index) *
1483 if (qdev->device_id == QL3032_DEVICE_ID)
1484 ql_write_page0_reg(qdev,
1485 &port_regs->macMIIMgmtControlReg, 0x0f00000);
1487 /* Divide 125MHz clock by 28 to meet PHY timing requirements */
1488 reg = MAC_MII_CONTROL_CLK_SEL_DIV28;
1490 ql_write_page0_reg(qdev, &port_regs->macMIIMgmtControlReg,
1491 reg | ((MAC_MII_CONTROL_CLK_SEL_MASK) << 16));
1493 ql_sem_unlock(qdev, QL_PHY_GIO_SEM_MASK);
1497 static u32 ql_supported_modes(struct ql3_adapter *qdev)
1501 if (test_bit(QL_LINK_OPTICAL,&qdev->flags)) {
1502 supported = SUPPORTED_1000baseT_Full | SUPPORTED_FIBRE
1503 | SUPPORTED_Autoneg;
1505 supported = SUPPORTED_10baseT_Half
1506 | SUPPORTED_10baseT_Full
1507 | SUPPORTED_100baseT_Half
1508 | SUPPORTED_100baseT_Full
1509 | SUPPORTED_1000baseT_Half
1510 | SUPPORTED_1000baseT_Full
1511 | SUPPORTED_Autoneg | SUPPORTED_TP;
1517 static int ql_get_auto_cfg_status(struct ql3_adapter *qdev)
1520 unsigned long hw_flags;
1521 spin_lock_irqsave(&qdev->hw_lock, hw_flags);
1522 if(ql_sem_spinlock(qdev, QL_PHY_GIO_SEM_MASK,
1523 (QL_RESOURCE_BITS_BASE_CODE | (qdev->mac_index) *
1525 spin_unlock_irqrestore(&qdev->hw_lock, hw_flags);
1528 status = ql_is_auto_cfg(qdev);
1529 ql_sem_unlock(qdev, QL_PHY_GIO_SEM_MASK);
1530 spin_unlock_irqrestore(&qdev->hw_lock, hw_flags);
1534 static u32 ql_get_speed(struct ql3_adapter *qdev)
1537 unsigned long hw_flags;
1538 spin_lock_irqsave(&qdev->hw_lock, hw_flags);
1539 if(ql_sem_spinlock(qdev, QL_PHY_GIO_SEM_MASK,
1540 (QL_RESOURCE_BITS_BASE_CODE | (qdev->mac_index) *
1542 spin_unlock_irqrestore(&qdev->hw_lock, hw_flags);
1545 status = ql_get_link_speed(qdev);
1546 ql_sem_unlock(qdev, QL_PHY_GIO_SEM_MASK);
1547 spin_unlock_irqrestore(&qdev->hw_lock, hw_flags);
1551 static int ql_get_full_dup(struct ql3_adapter *qdev)
1554 unsigned long hw_flags;
1555 spin_lock_irqsave(&qdev->hw_lock, hw_flags);
1556 if(ql_sem_spinlock(qdev, QL_PHY_GIO_SEM_MASK,
1557 (QL_RESOURCE_BITS_BASE_CODE | (qdev->mac_index) *
1559 spin_unlock_irqrestore(&qdev->hw_lock, hw_flags);
1562 status = ql_is_link_full_dup(qdev);
1563 ql_sem_unlock(qdev, QL_PHY_GIO_SEM_MASK);
1564 spin_unlock_irqrestore(&qdev->hw_lock, hw_flags);
1569 static int ql_get_settings(struct net_device *ndev, struct ethtool_cmd *ecmd)
1571 struct ql3_adapter *qdev = netdev_priv(ndev);
1573 ecmd->transceiver = XCVR_INTERNAL;
1574 ecmd->supported = ql_supported_modes(qdev);
1576 if (test_bit(QL_LINK_OPTICAL,&qdev->flags)) {
1577 ecmd->port = PORT_FIBRE;
1579 ecmd->port = PORT_TP;
1580 ecmd->phy_address = qdev->PHYAddr;
1582 ecmd->advertising = ql_supported_modes(qdev);
1583 ecmd->autoneg = ql_get_auto_cfg_status(qdev);
1584 ecmd->speed = ql_get_speed(qdev);
1585 ecmd->duplex = ql_get_full_dup(qdev);
1589 static void ql_get_drvinfo(struct net_device *ndev,
1590 struct ethtool_drvinfo *drvinfo)
1592 struct ql3_adapter *qdev = netdev_priv(ndev);
1593 strncpy(drvinfo->driver, ql3xxx_driver_name, 32);
1594 strncpy(drvinfo->version, ql3xxx_driver_version, 32);
1595 strncpy(drvinfo->fw_version, "N/A", 32);
1596 strncpy(drvinfo->bus_info, pci_name(qdev->pdev), 32);
1597 drvinfo->n_stats = 0;
1598 drvinfo->testinfo_len = 0;
1599 drvinfo->regdump_len = 0;
1600 drvinfo->eedump_len = 0;
1603 static u32 ql_get_msglevel(struct net_device *ndev)
1605 struct ql3_adapter *qdev = netdev_priv(ndev);
1606 return qdev->msg_enable;
1609 static void ql_set_msglevel(struct net_device *ndev, u32 value)
1611 struct ql3_adapter *qdev = netdev_priv(ndev);
1612 qdev->msg_enable = value;
1615 static const struct ethtool_ops ql3xxx_ethtool_ops = {
1616 .get_settings = ql_get_settings,
1617 .get_drvinfo = ql_get_drvinfo,
1618 .get_perm_addr = ethtool_op_get_perm_addr,
1619 .get_link = ethtool_op_get_link,
1620 .get_msglevel = ql_get_msglevel,
1621 .set_msglevel = ql_set_msglevel,
1624 static int ql_populate_free_queue(struct ql3_adapter *qdev)
1626 struct ql_rcv_buf_cb *lrg_buf_cb = qdev->lrg_buf_free_head;
1629 while (lrg_buf_cb) {
1630 if (!lrg_buf_cb->skb) {
1631 lrg_buf_cb->skb = netdev_alloc_skb(qdev->ndev,
1632 qdev->lrg_buffer_len);
1633 if (unlikely(!lrg_buf_cb->skb)) {
1634 printk(KERN_DEBUG PFX
1635 "%s: Failed netdev_alloc_skb().\n",
1640 * We save some space to copy the ethhdr from
1643 skb_reserve(lrg_buf_cb->skb, QL_HEADER_SPACE);
1644 map = pci_map_single(qdev->pdev,
1645 lrg_buf_cb->skb->data,
1646 qdev->lrg_buffer_len -
1648 PCI_DMA_FROMDEVICE);
1649 lrg_buf_cb->buf_phy_addr_low =
1650 cpu_to_le32(LS_64BITS(map));
1651 lrg_buf_cb->buf_phy_addr_high =
1652 cpu_to_le32(MS_64BITS(map));
1653 pci_unmap_addr_set(lrg_buf_cb, mapaddr, map);
1654 pci_unmap_len_set(lrg_buf_cb, maplen,
1655 qdev->lrg_buffer_len -
1657 --qdev->lrg_buf_skb_check;
1658 if (!qdev->lrg_buf_skb_check)
1662 lrg_buf_cb = lrg_buf_cb->next;
1668 * Caller holds hw_lock.
1670 static void ql_update_lrg_bufq_prod_index(struct ql3_adapter *qdev)
1672 struct bufq_addr_element *lrg_buf_q_ele;
1674 struct ql_rcv_buf_cb *lrg_buf_cb;
1675 struct ql3xxx_port_registers __iomem *port_regs = qdev->mem_map_registers;
1677 if ((qdev->lrg_buf_free_count >= 8)
1678 && (qdev->lrg_buf_release_cnt >= 16)) {
1680 if (qdev->lrg_buf_skb_check)
1681 if (!ql_populate_free_queue(qdev))
1684 lrg_buf_q_ele = qdev->lrg_buf_next_free;
1686 while ((qdev->lrg_buf_release_cnt >= 16)
1687 && (qdev->lrg_buf_free_count >= 8)) {
1689 for (i = 0; i < 8; i++) {
1691 ql_get_from_lrg_buf_free_list(qdev);
1692 lrg_buf_q_ele->addr_high =
1693 lrg_buf_cb->buf_phy_addr_high;
1694 lrg_buf_q_ele->addr_low =
1695 lrg_buf_cb->buf_phy_addr_low;
1698 qdev->lrg_buf_release_cnt--;
1701 qdev->lrg_buf_q_producer_index++;
1703 if (qdev->lrg_buf_q_producer_index == qdev->num_lbufq_entries)
1704 qdev->lrg_buf_q_producer_index = 0;
1706 if (qdev->lrg_buf_q_producer_index ==
1707 (qdev->num_lbufq_entries - 1)) {
1708 lrg_buf_q_ele = qdev->lrg_buf_q_virt_addr;
1712 qdev->lrg_buf_next_free = lrg_buf_q_ele;
1714 ql_write_common_reg(qdev,
1715 &port_regs->CommonRegs.
1716 rxLargeQProducerIndex,
1717 qdev->lrg_buf_q_producer_index);
1721 static void ql_process_mac_tx_intr(struct ql3_adapter *qdev,
1722 struct ob_mac_iocb_rsp *mac_rsp)
1724 struct ql_tx_buf_cb *tx_cb;
1727 tx_cb = &qdev->tx_buf[mac_rsp->transaction_id];
1728 pci_unmap_single(qdev->pdev,
1729 pci_unmap_addr(&tx_cb->map[0], mapaddr),
1730 pci_unmap_len(&tx_cb->map[0], maplen),
1733 if (tx_cb->seg_count) {
1734 for (i = 1; i < tx_cb->seg_count; i++) {
1735 pci_unmap_page(qdev->pdev,
1736 pci_unmap_addr(&tx_cb->map[i],
1738 pci_unmap_len(&tx_cb->map[i], maplen),
1742 qdev->stats.tx_packets++;
1743 qdev->stats.tx_bytes += tx_cb->skb->len;
1744 dev_kfree_skb_irq(tx_cb->skb);
1746 atomic_inc(&qdev->tx_count);
1749 void ql_get_sbuf(struct ql3_adapter *qdev)
1751 if (++qdev->small_buf_index == NUM_SMALL_BUFFERS)
1752 qdev->small_buf_index = 0;
1753 qdev->small_buf_release_cnt++;
1756 struct ql_rcv_buf_cb *ql_get_lbuf(struct ql3_adapter *qdev)
1758 struct ql_rcv_buf_cb *lrg_buf_cb = NULL;
1759 lrg_buf_cb = &qdev->lrg_buf[qdev->lrg_buf_index];
1760 qdev->lrg_buf_release_cnt++;
1761 if (++qdev->lrg_buf_index == qdev->num_large_buffers)
1762 qdev->lrg_buf_index = 0;
1767 * The difference between 3022 and 3032 for inbound completions:
1768 * 3022 uses two buffers per completion. The first buffer contains
1769 * (some) header info, the second the remainder of the headers plus
1770 * the data. For this chip we reserve some space at the top of the
1771 * receive buffer so that the header info in buffer one can be
1772 * prepended to the buffer two. Buffer two is the sent up while
1773 * buffer one is returned to the hardware to be reused.
1774 * 3032 receives all of it's data and headers in one buffer for a
1775 * simpler process. 3032 also supports checksum verification as
1776 * can be seen in ql_process_macip_rx_intr().
1778 static void ql_process_mac_rx_intr(struct ql3_adapter *qdev,
1779 struct ib_mac_iocb_rsp *ib_mac_rsp_ptr)
1781 struct ql_rcv_buf_cb *lrg_buf_cb1 = NULL;
1782 struct ql_rcv_buf_cb *lrg_buf_cb2 = NULL;
1783 struct sk_buff *skb;
1784 u16 length = le16_to_cpu(ib_mac_rsp_ptr->length);
1787 * Get the inbound address list (small buffer).
1791 if (qdev->device_id == QL3022_DEVICE_ID)
1792 lrg_buf_cb1 = ql_get_lbuf(qdev);
1794 /* start of second buffer */
1795 lrg_buf_cb2 = ql_get_lbuf(qdev);
1796 skb = lrg_buf_cb2->skb;
1798 qdev->stats.rx_packets++;
1799 qdev->stats.rx_bytes += length;
1801 skb_put(skb, length);
1802 pci_unmap_single(qdev->pdev,
1803 pci_unmap_addr(lrg_buf_cb2, mapaddr),
1804 pci_unmap_len(lrg_buf_cb2, maplen),
1805 PCI_DMA_FROMDEVICE);
1806 prefetch(skb->data);
1807 skb->dev = qdev->ndev;
1808 skb->ip_summed = CHECKSUM_NONE;
1809 skb->protocol = eth_type_trans(skb, qdev->ndev);
1811 netif_receive_skb(skb);
1812 qdev->ndev->last_rx = jiffies;
1813 lrg_buf_cb2->skb = NULL;
1815 if (qdev->device_id == QL3022_DEVICE_ID)
1816 ql_release_to_lrg_buf_free_list(qdev, lrg_buf_cb1);
1817 ql_release_to_lrg_buf_free_list(qdev, lrg_buf_cb2);
1820 static void ql_process_macip_rx_intr(struct ql3_adapter *qdev,
1821 struct ib_ip_iocb_rsp *ib_ip_rsp_ptr)
1823 struct ql_rcv_buf_cb *lrg_buf_cb1 = NULL;
1824 struct ql_rcv_buf_cb *lrg_buf_cb2 = NULL;
1825 struct sk_buff *skb1 = NULL, *skb2;
1826 struct net_device *ndev = qdev->ndev;
1827 u16 length = le16_to_cpu(ib_ip_rsp_ptr->length);
1831 * Get the inbound address list (small buffer).
1836 if (qdev->device_id == QL3022_DEVICE_ID) {
1837 /* start of first buffer on 3022 */
1838 lrg_buf_cb1 = ql_get_lbuf(qdev);
1839 skb1 = lrg_buf_cb1->skb;
1841 if (*((u16 *) skb1->data) != 0xFFFF)
1842 size += VLAN_ETH_HLEN - ETH_HLEN;
1845 /* start of second buffer */
1846 lrg_buf_cb2 = ql_get_lbuf(qdev);
1847 skb2 = lrg_buf_cb2->skb;
1849 skb_put(skb2, length); /* Just the second buffer length here. */
1850 pci_unmap_single(qdev->pdev,
1851 pci_unmap_addr(lrg_buf_cb2, mapaddr),
1852 pci_unmap_len(lrg_buf_cb2, maplen),
1853 PCI_DMA_FROMDEVICE);
1854 prefetch(skb2->data);
1856 skb2->ip_summed = CHECKSUM_NONE;
1857 if (qdev->device_id == QL3022_DEVICE_ID) {
1859 * Copy the ethhdr from first buffer to second. This
1860 * is necessary for 3022 IP completions.
1862 memcpy(skb_push(skb2, size), skb1->data + VLAN_ID_LEN, size);
1864 u16 checksum = le16_to_cpu(ib_ip_rsp_ptr->checksum);
1866 (IB_IP_IOCB_RSP_3032_ICE |
1867 IB_IP_IOCB_RSP_3032_CE |
1868 IB_IP_IOCB_RSP_3032_NUC)) {
1870 "%s: Bad checksum for this %s packet, checksum = %x.\n",
1873 IB_IP_IOCB_RSP_3032_TCP) ? "TCP" :
1875 } else if (checksum & IB_IP_IOCB_RSP_3032_TCP) {
1876 skb2->ip_summed = CHECKSUM_UNNECESSARY;
1879 skb2->dev = qdev->ndev;
1880 skb2->protocol = eth_type_trans(skb2, qdev->ndev);
1882 netif_receive_skb(skb2);
1883 qdev->stats.rx_packets++;
1884 qdev->stats.rx_bytes += length;
1885 ndev->last_rx = jiffies;
1886 lrg_buf_cb2->skb = NULL;
1888 if (qdev->device_id == QL3022_DEVICE_ID)
1889 ql_release_to_lrg_buf_free_list(qdev, lrg_buf_cb1);
1890 ql_release_to_lrg_buf_free_list(qdev, lrg_buf_cb2);
1893 static int ql_tx_rx_clean(struct ql3_adapter *qdev,
1894 int *tx_cleaned, int *rx_cleaned, int work_to_do)
1896 struct ql3xxx_port_registers __iomem *port_regs = qdev->mem_map_registers;
1897 struct net_rsp_iocb *net_rsp;
1898 struct net_device *ndev = qdev->ndev;
1899 unsigned long hw_flags;
1901 /* While there are entries in the completion queue. */
1902 while ((cpu_to_le32(*(qdev->prsp_producer_index)) !=
1903 qdev->rsp_consumer_index) && (*rx_cleaned < work_to_do)) {
1905 net_rsp = qdev->rsp_current;
1906 switch (net_rsp->opcode) {
1908 case OPCODE_OB_MAC_IOCB_FN0:
1909 case OPCODE_OB_MAC_IOCB_FN2:
1910 ql_process_mac_tx_intr(qdev, (struct ob_mac_iocb_rsp *)
1915 case OPCODE_IB_MAC_IOCB:
1916 case OPCODE_IB_3032_MAC_IOCB:
1917 ql_process_mac_rx_intr(qdev, (struct ib_mac_iocb_rsp *)
1922 case OPCODE_IB_IP_IOCB:
1923 case OPCODE_IB_3032_IP_IOCB:
1924 ql_process_macip_rx_intr(qdev, (struct ib_ip_iocb_rsp *)
1930 u32 *tmp = (u32 *) net_rsp;
1932 "%s: Hit default case, not "
1934 " dropping the packet, opcode = "
1936 ndev->name, net_rsp->opcode);
1938 "0x%08lx 0x%08lx 0x%08lx 0x%08lx \n",
1939 (unsigned long int)tmp[0],
1940 (unsigned long int)tmp[1],
1941 (unsigned long int)tmp[2],
1942 (unsigned long int)tmp[3]);
1946 qdev->rsp_consumer_index++;
1948 if (qdev->rsp_consumer_index == NUM_RSP_Q_ENTRIES) {
1949 qdev->rsp_consumer_index = 0;
1950 qdev->rsp_current = qdev->rsp_q_virt_addr;
1952 qdev->rsp_current++;
1956 spin_lock_irqsave(&qdev->hw_lock, hw_flags);
1958 ql_update_lrg_bufq_prod_index(qdev);
1960 if (qdev->small_buf_release_cnt >= 16) {
1961 while (qdev->small_buf_release_cnt >= 16) {
1962 qdev->small_buf_q_producer_index++;
1964 if (qdev->small_buf_q_producer_index ==
1966 qdev->small_buf_q_producer_index = 0;
1967 qdev->small_buf_release_cnt -= 8;
1970 ql_write_common_reg(qdev,
1971 &port_regs->CommonRegs.
1972 rxSmallQProducerIndex,
1973 qdev->small_buf_q_producer_index);
1976 ql_write_common_reg(qdev,
1977 &port_regs->CommonRegs.rspQConsumerIndex,
1978 qdev->rsp_consumer_index);
1979 spin_unlock_irqrestore(&qdev->hw_lock, hw_flags);
1981 if (unlikely(netif_queue_stopped(qdev->ndev))) {
1982 if (netif_queue_stopped(qdev->ndev) &&
1983 (atomic_read(&qdev->tx_count) > (NUM_REQ_Q_ENTRIES / 4)))
1984 netif_wake_queue(qdev->ndev);
1987 return *tx_cleaned + *rx_cleaned;
1990 static int ql_poll(struct net_device *ndev, int *budget)
1992 struct ql3_adapter *qdev = netdev_priv(ndev);
1993 int work_to_do = min(*budget, ndev->quota);
1994 int rx_cleaned = 0, tx_cleaned = 0;
1996 if (!netif_carrier_ok(ndev))
1999 ql_tx_rx_clean(qdev, &tx_cleaned, &rx_cleaned, work_to_do);
2000 *budget -= rx_cleaned;
2001 ndev->quota -= rx_cleaned;
2003 if ((!tx_cleaned && !rx_cleaned) || !netif_running(ndev)) {
2005 netif_rx_complete(ndev);
2006 ql_enable_interrupts(qdev);
2012 static irqreturn_t ql3xxx_isr(int irq, void *dev_id)
2015 struct net_device *ndev = dev_id;
2016 struct ql3_adapter *qdev = netdev_priv(ndev);
2017 struct ql3xxx_port_registers __iomem *port_regs = qdev->mem_map_registers;
2022 port_regs = qdev->mem_map_registers;
2025 ql_read_common_reg_l(qdev, &port_regs->CommonRegs.ispControlStatus);
2027 if (value & (ISP_CONTROL_FE | ISP_CONTROL_RI)) {
2028 spin_lock(&qdev->adapter_lock);
2029 netif_stop_queue(qdev->ndev);
2030 netif_carrier_off(qdev->ndev);
2031 ql_disable_interrupts(qdev);
2032 qdev->port_link_state = LS_DOWN;
2033 set_bit(QL_RESET_ACTIVE,&qdev->flags) ;
2035 if (value & ISP_CONTROL_FE) {
2040 ql_read_page0_reg_l(qdev,
2041 &port_regs->PortFatalErrStatus);
2042 printk(KERN_WARNING PFX
2043 "%s: Resetting chip. PortFatalErrStatus "
2044 "register = 0x%x\n", ndev->name, var);
2045 set_bit(QL_RESET_START,&qdev->flags) ;
2048 * Soft Reset Requested.
2050 set_bit(QL_RESET_PER_SCSI,&qdev->flags) ;
2052 "%s: Another function issued a reset to the "
2053 "chip. ISR value = %x.\n", ndev->name, value);
2055 queue_delayed_work(qdev->workqueue, &qdev->reset_work, 0);
2056 spin_unlock(&qdev->adapter_lock);
2057 } else if (value & ISP_IMR_DISABLE_CMPL_INT) {
2058 ql_disable_interrupts(qdev);
2059 if (likely(netif_rx_schedule_prep(ndev)))
2060 __netif_rx_schedule(ndev);
2062 ql_enable_interrupts(qdev);
2067 return IRQ_RETVAL(handled);
2071 * Get the total number of segments needed for the
2072 * given number of fragments. This is necessary because
2073 * outbound address lists (OAL) will be used when more than
2074 * two frags are given. Each address list has 5 addr/len
2075 * pairs. The 5th pair in each AOL is used to point to
2076 * the next AOL if more frags are coming.
2077 * That is why the frags:segment count ratio is not linear.
2079 static int ql_get_seg_count(unsigned short frags)
2082 case 0: return 1; /* just the skb->data seg */
2083 case 1: return 2; /* skb->data + 1 frag */
2084 case 2: return 3; /* skb->data + 2 frags */
2085 case 3: return 5; /* skb->data + 1 frag + 1 AOL containting 2 frags */
2105 static void ql_hw_csum_setup(struct sk_buff *skb,
2106 struct ob_mac_iocb_req *mac_iocb_ptr)
2109 struct iphdr *ip = NULL;
2110 u8 offset = ETH_HLEN;
2112 eth = (struct ethhdr *)(skb->data);
2114 if (eth->h_proto == __constant_htons(ETH_P_IP)) {
2115 ip = (struct iphdr *)&skb->data[ETH_HLEN];
2116 } else if (eth->h_proto == htons(ETH_P_8021Q) &&
2117 ((struct vlan_ethhdr *)skb->data)->
2118 h_vlan_encapsulated_proto == __constant_htons(ETH_P_IP)) {
2119 ip = (struct iphdr *)&skb->data[VLAN_ETH_HLEN];
2120 offset = VLAN_ETH_HLEN;
2124 if (ip->protocol == IPPROTO_TCP) {
2125 mac_iocb_ptr->flags1 |= OB_3032MAC_IOCB_REQ_TC |
2126 OB_3032MAC_IOCB_REQ_IC;
2127 mac_iocb_ptr->ip_hdr_off = offset;
2128 mac_iocb_ptr->ip_hdr_len = ip->ihl;
2129 } else if (ip->protocol == IPPROTO_UDP) {
2130 mac_iocb_ptr->flags1 |= OB_3032MAC_IOCB_REQ_UC |
2131 OB_3032MAC_IOCB_REQ_IC;
2132 mac_iocb_ptr->ip_hdr_off = offset;
2133 mac_iocb_ptr->ip_hdr_len = ip->ihl;
2139 * Map the buffers for this transmit. This will return
2140 * NETDEV_TX_BUSY or NETDEV_TX_OK based on success.
2142 static int ql_send_map(struct ql3_adapter *qdev,
2143 struct ob_mac_iocb_req *mac_iocb_ptr,
2144 struct ql_tx_buf_cb *tx_cb,
2145 struct sk_buff *skb)
2148 struct oal_entry *oal_entry;
2149 int len = skb_headlen(skb);
2151 int seg_cnt, seg = 0;
2152 int frag_cnt = (int)skb_shinfo(skb)->nr_frags;
2154 seg_cnt = tx_cb->seg_count = ql_get_seg_count((skb_shinfo(skb)->nr_frags));
2156 printk(KERN_ERR PFX"%s: invalid segment count!\n",__func__);
2157 return NETDEV_TX_BUSY;
2160 * Map the skb buffer first.
2162 map = pci_map_single(qdev->pdev, skb->data, len, PCI_DMA_TODEVICE);
2163 oal_entry = (struct oal_entry *)&mac_iocb_ptr->buf_addr0_low;
2164 oal_entry->dma_lo = cpu_to_le32(LS_64BITS(map));
2165 oal_entry->dma_hi = cpu_to_le32(MS_64BITS(map));
2166 oal_entry->len = cpu_to_le32(len);
2167 pci_unmap_addr_set(&tx_cb->map[seg], mapaddr, map);
2168 pci_unmap_len_set(&tx_cb->map[seg], maplen, len);
2171 if (!skb_shinfo(skb)->nr_frags) {
2172 /* Terminate the last segment. */
2174 cpu_to_le32(le32_to_cpu(oal_entry->len) | OAL_LAST_ENTRY);
2178 for (i=0; i<frag_cnt; i++,seg++) {
2179 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
2181 if ((seg == 2 && seg_cnt > 3) || /* Check for continuation */
2182 (seg == 7 && seg_cnt > 8) || /* requirements. It's strange */
2183 (seg == 12 && seg_cnt > 13) || /* but necessary. */
2184 (seg == 17 && seg_cnt > 18)) {
2185 /* Continuation entry points to outbound address list. */
2186 map = pci_map_single(qdev->pdev, oal,
2189 oal_entry->dma_lo = cpu_to_le32(LS_64BITS(map));
2190 oal_entry->dma_hi = cpu_to_le32(MS_64BITS(map));
2192 cpu_to_le32(sizeof(struct oal) |
2194 pci_unmap_addr_set(&tx_cb->map[seg], mapaddr,
2196 pci_unmap_len_set(&tx_cb->map[seg], maplen,
2198 oal_entry = (struct oal_entry *)oal;
2204 pci_map_page(qdev->pdev, frag->page,
2205 frag->page_offset, frag->size,
2207 oal_entry->dma_lo = cpu_to_le32(LS_64BITS(map));
2208 oal_entry->dma_hi = cpu_to_le32(MS_64BITS(map));
2209 oal_entry->len = cpu_to_le32(frag->size);
2210 pci_unmap_addr_set(&tx_cb->map[seg], mapaddr, map);
2211 pci_unmap_len_set(&tx_cb->map[seg], maplen,
2214 /* Terminate the last segment. */
2216 cpu_to_le32(le32_to_cpu(oal_entry->len) | OAL_LAST_ENTRY);
2218 return NETDEV_TX_OK;
2222 * The difference between 3022 and 3032 sends:
2223 * 3022 only supports a simple single segment transmission.
2224 * 3032 supports checksumming and scatter/gather lists (fragments).
2225 * The 3032 supports sglists by using the 3 addr/len pairs (ALP)
2226 * in the IOCB plus a chain of outbound address lists (OAL) that
2227 * each contain 5 ALPs. The last ALP of the IOCB (3rd) or OAL (5th)
2228 * will used to point to an OAL when more ALP entries are required.
2229 * The IOCB is always the top of the chain followed by one or more
2230 * OALs (when necessary).
2232 static int ql3xxx_send(struct sk_buff *skb, struct net_device *ndev)
2234 struct ql3_adapter *qdev = (struct ql3_adapter *)netdev_priv(ndev);
2235 struct ql3xxx_port_registers __iomem *port_regs = qdev->mem_map_registers;
2236 struct ql_tx_buf_cb *tx_cb;
2237 u32 tot_len = skb->len;
2238 struct ob_mac_iocb_req *mac_iocb_ptr;
2240 if (unlikely(atomic_read(&qdev->tx_count) < 2)) {
2241 if (!netif_queue_stopped(ndev))
2242 netif_stop_queue(ndev);
2243 return NETDEV_TX_BUSY;
2246 tx_cb = &qdev->tx_buf[qdev->req_producer_index] ;
2247 if((tx_cb->seg_count = ql_get_seg_count((skb_shinfo(skb)->nr_frags))) == -1) {
2248 printk(KERN_ERR PFX"%s: invalid segment count!\n",__func__);
2249 return NETDEV_TX_OK;
2252 mac_iocb_ptr = tx_cb->queue_entry;
2253 mac_iocb_ptr->opcode = qdev->mac_ob_opcode;
2254 mac_iocb_ptr->flags = OB_MAC_IOCB_REQ_X;
2255 mac_iocb_ptr->flags |= qdev->mb_bit_mask;
2256 mac_iocb_ptr->transaction_id = qdev->req_producer_index;
2257 mac_iocb_ptr->data_len = cpu_to_le16((u16) tot_len);
2259 if (skb->ip_summed == CHECKSUM_PARTIAL)
2260 ql_hw_csum_setup(skb, mac_iocb_ptr);
2262 if(ql_send_map(qdev,mac_iocb_ptr,tx_cb,skb) != NETDEV_TX_OK) {
2263 printk(KERN_ERR PFX"%s: Could not map the segments!\n",__func__);
2264 return NETDEV_TX_BUSY;
2268 qdev->req_producer_index++;
2269 if (qdev->req_producer_index == NUM_REQ_Q_ENTRIES)
2270 qdev->req_producer_index = 0;
2272 ql_write_common_reg_l(qdev,
2273 &port_regs->CommonRegs.reqQProducerIndex,
2274 qdev->req_producer_index);
2276 ndev->trans_start = jiffies;
2277 if (netif_msg_tx_queued(qdev))
2278 printk(KERN_DEBUG PFX "%s: tx queued, slot %d, len %d\n",
2279 ndev->name, qdev->req_producer_index, skb->len);
2281 atomic_dec(&qdev->tx_count);
2282 return NETDEV_TX_OK;
2285 static int ql_alloc_net_req_rsp_queues(struct ql3_adapter *qdev)
2288 (u32) (NUM_REQ_Q_ENTRIES * sizeof(struct ob_mac_iocb_req));
2290 qdev->req_q_virt_addr =
2291 pci_alloc_consistent(qdev->pdev,
2292 (size_t) qdev->req_q_size,
2293 &qdev->req_q_phy_addr);
2295 if ((qdev->req_q_virt_addr == NULL) ||
2296 LS_64BITS(qdev->req_q_phy_addr) & (qdev->req_q_size - 1)) {
2297 printk(KERN_ERR PFX "%s: reqQ failed.\n",
2302 qdev->rsp_q_size = NUM_RSP_Q_ENTRIES * sizeof(struct net_rsp_iocb);
2304 qdev->rsp_q_virt_addr =
2305 pci_alloc_consistent(qdev->pdev,
2306 (size_t) qdev->rsp_q_size,
2307 &qdev->rsp_q_phy_addr);
2309 if ((qdev->rsp_q_virt_addr == NULL) ||
2310 LS_64BITS(qdev->rsp_q_phy_addr) & (qdev->rsp_q_size - 1)) {
2312 "%s: rspQ allocation failed\n",
2314 pci_free_consistent(qdev->pdev, (size_t) qdev->req_q_size,
2315 qdev->req_q_virt_addr,
2316 qdev->req_q_phy_addr);
2320 set_bit(QL_ALLOC_REQ_RSP_Q_DONE,&qdev->flags);
2325 static void ql_free_net_req_rsp_queues(struct ql3_adapter *qdev)
2327 if (!test_bit(QL_ALLOC_REQ_RSP_Q_DONE,&qdev->flags)) {
2328 printk(KERN_INFO PFX
2329 "%s: Already done.\n", qdev->ndev->name);
2333 pci_free_consistent(qdev->pdev,
2335 qdev->req_q_virt_addr, qdev->req_q_phy_addr);
2337 qdev->req_q_virt_addr = NULL;
2339 pci_free_consistent(qdev->pdev,
2341 qdev->rsp_q_virt_addr, qdev->rsp_q_phy_addr);
2343 qdev->rsp_q_virt_addr = NULL;
2345 clear_bit(QL_ALLOC_REQ_RSP_Q_DONE,&qdev->flags);
2348 static int ql_alloc_buffer_queues(struct ql3_adapter *qdev)
2350 /* Create Large Buffer Queue */
2351 qdev->lrg_buf_q_size =
2352 qdev->num_lbufq_entries * sizeof(struct lrg_buf_q_entry);
2353 if (qdev->lrg_buf_q_size < PAGE_SIZE)
2354 qdev->lrg_buf_q_alloc_size = PAGE_SIZE;
2356 qdev->lrg_buf_q_alloc_size = qdev->lrg_buf_q_size * 2;
2358 qdev->lrg_buf = kmalloc(qdev->num_large_buffers * sizeof(struct ql_rcv_buf_cb),GFP_KERNEL);
2359 if (qdev->lrg_buf == NULL) {
2361 "%s: qdev->lrg_buf alloc failed.\n", qdev->ndev->name);
2365 qdev->lrg_buf_q_alloc_virt_addr =
2366 pci_alloc_consistent(qdev->pdev,
2367 qdev->lrg_buf_q_alloc_size,
2368 &qdev->lrg_buf_q_alloc_phy_addr);
2370 if (qdev->lrg_buf_q_alloc_virt_addr == NULL) {
2372 "%s: lBufQ failed\n", qdev->ndev->name);
2375 qdev->lrg_buf_q_virt_addr = qdev->lrg_buf_q_alloc_virt_addr;
2376 qdev->lrg_buf_q_phy_addr = qdev->lrg_buf_q_alloc_phy_addr;
2378 /* Create Small Buffer Queue */
2379 qdev->small_buf_q_size =
2380 NUM_SBUFQ_ENTRIES * sizeof(struct lrg_buf_q_entry);
2381 if (qdev->small_buf_q_size < PAGE_SIZE)
2382 qdev->small_buf_q_alloc_size = PAGE_SIZE;
2384 qdev->small_buf_q_alloc_size = qdev->small_buf_q_size * 2;
2386 qdev->small_buf_q_alloc_virt_addr =
2387 pci_alloc_consistent(qdev->pdev,
2388 qdev->small_buf_q_alloc_size,
2389 &qdev->small_buf_q_alloc_phy_addr);
2391 if (qdev->small_buf_q_alloc_virt_addr == NULL) {
2393 "%s: Small Buffer Queue allocation failed.\n",
2395 pci_free_consistent(qdev->pdev, qdev->lrg_buf_q_alloc_size,
2396 qdev->lrg_buf_q_alloc_virt_addr,
2397 qdev->lrg_buf_q_alloc_phy_addr);
2401 qdev->small_buf_q_virt_addr = qdev->small_buf_q_alloc_virt_addr;
2402 qdev->small_buf_q_phy_addr = qdev->small_buf_q_alloc_phy_addr;
2403 set_bit(QL_ALLOC_BUFQS_DONE,&qdev->flags);
2407 static void ql_free_buffer_queues(struct ql3_adapter *qdev)
2409 if (!test_bit(QL_ALLOC_BUFQS_DONE,&qdev->flags)) {
2410 printk(KERN_INFO PFX
2411 "%s: Already done.\n", qdev->ndev->name);
2414 if(qdev->lrg_buf) kfree(qdev->lrg_buf);
2415 pci_free_consistent(qdev->pdev,
2416 qdev->lrg_buf_q_alloc_size,
2417 qdev->lrg_buf_q_alloc_virt_addr,
2418 qdev->lrg_buf_q_alloc_phy_addr);
2420 qdev->lrg_buf_q_virt_addr = NULL;
2422 pci_free_consistent(qdev->pdev,
2423 qdev->small_buf_q_alloc_size,
2424 qdev->small_buf_q_alloc_virt_addr,
2425 qdev->small_buf_q_alloc_phy_addr);
2427 qdev->small_buf_q_virt_addr = NULL;
2429 clear_bit(QL_ALLOC_BUFQS_DONE,&qdev->flags);
2432 static int ql_alloc_small_buffers(struct ql3_adapter *qdev)
2435 struct bufq_addr_element *small_buf_q_entry;
2437 /* Currently we allocate on one of memory and use it for smallbuffers */
2438 qdev->small_buf_total_size =
2439 (QL_ADDR_ELE_PER_BUFQ_ENTRY * NUM_SBUFQ_ENTRIES *
2440 QL_SMALL_BUFFER_SIZE);
2442 qdev->small_buf_virt_addr =
2443 pci_alloc_consistent(qdev->pdev,
2444 qdev->small_buf_total_size,
2445 &qdev->small_buf_phy_addr);
2447 if (qdev->small_buf_virt_addr == NULL) {
2449 "%s: Failed to get small buffer memory.\n",
2454 qdev->small_buf_phy_addr_low = LS_64BITS(qdev->small_buf_phy_addr);
2455 qdev->small_buf_phy_addr_high = MS_64BITS(qdev->small_buf_phy_addr);
2457 small_buf_q_entry = qdev->small_buf_q_virt_addr;
2459 /* Initialize the small buffer queue. */
2460 for (i = 0; i < (QL_ADDR_ELE_PER_BUFQ_ENTRY * NUM_SBUFQ_ENTRIES); i++) {
2461 small_buf_q_entry->addr_high =
2462 cpu_to_le32(qdev->small_buf_phy_addr_high);
2463 small_buf_q_entry->addr_low =
2464 cpu_to_le32(qdev->small_buf_phy_addr_low +
2465 (i * QL_SMALL_BUFFER_SIZE));
2466 small_buf_q_entry++;
2468 qdev->small_buf_index = 0;
2469 set_bit(QL_ALLOC_SMALL_BUF_DONE,&qdev->flags);
2473 static void ql_free_small_buffers(struct ql3_adapter *qdev)
2475 if (!test_bit(QL_ALLOC_SMALL_BUF_DONE,&qdev->flags)) {
2476 printk(KERN_INFO PFX
2477 "%s: Already done.\n", qdev->ndev->name);
2480 if (qdev->small_buf_virt_addr != NULL) {
2481 pci_free_consistent(qdev->pdev,
2482 qdev->small_buf_total_size,
2483 qdev->small_buf_virt_addr,
2484 qdev->small_buf_phy_addr);
2486 qdev->small_buf_virt_addr = NULL;
2490 static void ql_free_large_buffers(struct ql3_adapter *qdev)
2493 struct ql_rcv_buf_cb *lrg_buf_cb;
2495 for (i = 0; i < qdev->num_large_buffers; i++) {
2496 lrg_buf_cb = &qdev->lrg_buf[i];
2497 if (lrg_buf_cb->skb) {
2498 dev_kfree_skb(lrg_buf_cb->skb);
2499 pci_unmap_single(qdev->pdev,
2500 pci_unmap_addr(lrg_buf_cb, mapaddr),
2501 pci_unmap_len(lrg_buf_cb, maplen),
2502 PCI_DMA_FROMDEVICE);
2503 memset(lrg_buf_cb, 0, sizeof(struct ql_rcv_buf_cb));
2510 static void ql_init_large_buffers(struct ql3_adapter *qdev)
2513 struct ql_rcv_buf_cb *lrg_buf_cb;
2514 struct bufq_addr_element *buf_addr_ele = qdev->lrg_buf_q_virt_addr;
2516 for (i = 0; i < qdev->num_large_buffers; i++) {
2517 lrg_buf_cb = &qdev->lrg_buf[i];
2518 buf_addr_ele->addr_high = lrg_buf_cb->buf_phy_addr_high;
2519 buf_addr_ele->addr_low = lrg_buf_cb->buf_phy_addr_low;
2522 qdev->lrg_buf_index = 0;
2523 qdev->lrg_buf_skb_check = 0;
2526 static int ql_alloc_large_buffers(struct ql3_adapter *qdev)
2529 struct ql_rcv_buf_cb *lrg_buf_cb;
2530 struct sk_buff *skb;
2533 for (i = 0; i < qdev->num_large_buffers; i++) {
2534 skb = netdev_alloc_skb(qdev->ndev,
2535 qdev->lrg_buffer_len);
2536 if (unlikely(!skb)) {
2537 /* Better luck next round */
2539 "%s: large buff alloc failed, "
2540 "for %d bytes at index %d.\n",
2542 qdev->lrg_buffer_len * 2, i);
2543 ql_free_large_buffers(qdev);
2547 lrg_buf_cb = &qdev->lrg_buf[i];
2548 memset(lrg_buf_cb, 0, sizeof(struct ql_rcv_buf_cb));
2549 lrg_buf_cb->index = i;
2550 lrg_buf_cb->skb = skb;
2552 * We save some space to copy the ethhdr from first
2555 skb_reserve(skb, QL_HEADER_SPACE);
2556 map = pci_map_single(qdev->pdev,
2558 qdev->lrg_buffer_len -
2560 PCI_DMA_FROMDEVICE);
2561 pci_unmap_addr_set(lrg_buf_cb, mapaddr, map);
2562 pci_unmap_len_set(lrg_buf_cb, maplen,
2563 qdev->lrg_buffer_len -
2565 lrg_buf_cb->buf_phy_addr_low =
2566 cpu_to_le32(LS_64BITS(map));
2567 lrg_buf_cb->buf_phy_addr_high =
2568 cpu_to_le32(MS_64BITS(map));
2574 static void ql_free_send_free_list(struct ql3_adapter *qdev)
2576 struct ql_tx_buf_cb *tx_cb;
2579 tx_cb = &qdev->tx_buf[0];
2580 for (i = 0; i < NUM_REQ_Q_ENTRIES; i++) {
2589 static int ql_create_send_free_list(struct ql3_adapter *qdev)
2591 struct ql_tx_buf_cb *tx_cb;
2593 struct ob_mac_iocb_req *req_q_curr =
2594 qdev->req_q_virt_addr;
2596 /* Create free list of transmit buffers */
2597 for (i = 0; i < NUM_REQ_Q_ENTRIES; i++) {
2599 tx_cb = &qdev->tx_buf[i];
2601 tx_cb->queue_entry = req_q_curr;
2603 tx_cb->oal = kmalloc(512, GFP_KERNEL);
2604 if (tx_cb->oal == NULL)
2610 static int ql_alloc_mem_resources(struct ql3_adapter *qdev)
2612 if (qdev->ndev->mtu == NORMAL_MTU_SIZE) {
2613 qdev->num_lbufq_entries = NUM_LBUFQ_ENTRIES;
2614 qdev->lrg_buffer_len = NORMAL_MTU_SIZE;
2616 else if (qdev->ndev->mtu == JUMBO_MTU_SIZE) {
2618 * Bigger buffers, so less of them.
2620 qdev->num_lbufq_entries = JUMBO_NUM_LBUFQ_ENTRIES;
2621 qdev->lrg_buffer_len = JUMBO_MTU_SIZE;
2624 "%s: Invalid mtu size. Only 1500 and 9000 are accepted.\n",
2628 qdev->num_large_buffers = qdev->num_lbufq_entries * QL_ADDR_ELE_PER_BUFQ_ENTRY;
2629 qdev->lrg_buffer_len += VLAN_ETH_HLEN + VLAN_ID_LEN + QL_HEADER_SPACE;
2630 qdev->max_frame_size =
2631 (qdev->lrg_buffer_len - QL_HEADER_SPACE) + ETHERNET_CRC_SIZE;
2634 * First allocate a page of shared memory and use it for shadow
2635 * locations of Network Request Queue Consumer Address Register and
2636 * Network Completion Queue Producer Index Register
2638 qdev->shadow_reg_virt_addr =
2639 pci_alloc_consistent(qdev->pdev,
2640 PAGE_SIZE, &qdev->shadow_reg_phy_addr);
2642 if (qdev->shadow_reg_virt_addr != NULL) {
2643 qdev->preq_consumer_index = (u16 *) qdev->shadow_reg_virt_addr;
2644 qdev->req_consumer_index_phy_addr_high =
2645 MS_64BITS(qdev->shadow_reg_phy_addr);
2646 qdev->req_consumer_index_phy_addr_low =
2647 LS_64BITS(qdev->shadow_reg_phy_addr);
2649 qdev->prsp_producer_index =
2650 (u32 *) (((u8 *) qdev->preq_consumer_index) + 8);
2651 qdev->rsp_producer_index_phy_addr_high =
2652 qdev->req_consumer_index_phy_addr_high;
2653 qdev->rsp_producer_index_phy_addr_low =
2654 qdev->req_consumer_index_phy_addr_low + 8;
2657 "%s: shadowReg Alloc failed.\n", qdev->ndev->name);
2661 if (ql_alloc_net_req_rsp_queues(qdev) != 0) {
2663 "%s: ql_alloc_net_req_rsp_queues failed.\n",
2668 if (ql_alloc_buffer_queues(qdev) != 0) {
2670 "%s: ql_alloc_buffer_queues failed.\n",
2672 goto err_buffer_queues;
2675 if (ql_alloc_small_buffers(qdev) != 0) {
2677 "%s: ql_alloc_small_buffers failed\n", qdev->ndev->name);
2678 goto err_small_buffers;
2681 if (ql_alloc_large_buffers(qdev) != 0) {
2683 "%s: ql_alloc_large_buffers failed\n", qdev->ndev->name);
2684 goto err_small_buffers;
2687 /* Initialize the large buffer queue. */
2688 ql_init_large_buffers(qdev);
2689 if (ql_create_send_free_list(qdev))
2692 qdev->rsp_current = qdev->rsp_q_virt_addr;
2696 ql_free_send_free_list(qdev);
2698 ql_free_buffer_queues(qdev);
2700 ql_free_net_req_rsp_queues(qdev);
2702 pci_free_consistent(qdev->pdev,
2704 qdev->shadow_reg_virt_addr,
2705 qdev->shadow_reg_phy_addr);
2710 static void ql_free_mem_resources(struct ql3_adapter *qdev)
2712 ql_free_send_free_list(qdev);
2713 ql_free_large_buffers(qdev);
2714 ql_free_small_buffers(qdev);
2715 ql_free_buffer_queues(qdev);
2716 ql_free_net_req_rsp_queues(qdev);
2717 if (qdev->shadow_reg_virt_addr != NULL) {
2718 pci_free_consistent(qdev->pdev,
2720 qdev->shadow_reg_virt_addr,
2721 qdev->shadow_reg_phy_addr);
2722 qdev->shadow_reg_virt_addr = NULL;
2726 static int ql_init_misc_registers(struct ql3_adapter *qdev)
2728 struct ql3xxx_local_ram_registers __iomem *local_ram =
2729 (void __iomem *)qdev->mem_map_registers;
2731 if(ql_sem_spinlock(qdev, QL_DDR_RAM_SEM_MASK,
2732 (QL_RESOURCE_BITS_BASE_CODE | (qdev->mac_index) *
2736 ql_write_page2_reg(qdev,
2737 &local_ram->bufletSize, qdev->nvram_data.bufletSize);
2739 ql_write_page2_reg(qdev,
2740 &local_ram->maxBufletCount,
2741 qdev->nvram_data.bufletCount);
2743 ql_write_page2_reg(qdev,
2744 &local_ram->freeBufletThresholdLow,
2745 (qdev->nvram_data.tcpWindowThreshold25 << 16) |
2746 (qdev->nvram_data.tcpWindowThreshold0));
2748 ql_write_page2_reg(qdev,
2749 &local_ram->freeBufletThresholdHigh,
2750 qdev->nvram_data.tcpWindowThreshold50);
2752 ql_write_page2_reg(qdev,
2753 &local_ram->ipHashTableBase,
2754 (qdev->nvram_data.ipHashTableBaseHi << 16) |
2755 qdev->nvram_data.ipHashTableBaseLo);
2756 ql_write_page2_reg(qdev,
2757 &local_ram->ipHashTableCount,
2758 qdev->nvram_data.ipHashTableSize);
2759 ql_write_page2_reg(qdev,
2760 &local_ram->tcpHashTableBase,
2761 (qdev->nvram_data.tcpHashTableBaseHi << 16) |
2762 qdev->nvram_data.tcpHashTableBaseLo);
2763 ql_write_page2_reg(qdev,
2764 &local_ram->tcpHashTableCount,
2765 qdev->nvram_data.tcpHashTableSize);
2766 ql_write_page2_reg(qdev,
2767 &local_ram->ncbBase,
2768 (qdev->nvram_data.ncbTableBaseHi << 16) |
2769 qdev->nvram_data.ncbTableBaseLo);
2770 ql_write_page2_reg(qdev,
2771 &local_ram->maxNcbCount,
2772 qdev->nvram_data.ncbTableSize);
2773 ql_write_page2_reg(qdev,
2774 &local_ram->drbBase,
2775 (qdev->nvram_data.drbTableBaseHi << 16) |
2776 qdev->nvram_data.drbTableBaseLo);
2777 ql_write_page2_reg(qdev,
2778 &local_ram->maxDrbCount,
2779 qdev->nvram_data.drbTableSize);
2780 ql_sem_unlock(qdev, QL_DDR_RAM_SEM_MASK);
2784 static int ql_adapter_initialize(struct ql3_adapter *qdev)
2787 struct ql3xxx_port_registers __iomem *port_regs = qdev->mem_map_registers;
2788 struct ql3xxx_host_memory_registers __iomem *hmem_regs =
2789 (void __iomem *)port_regs;
2793 if(ql_mii_setup(qdev))
2796 /* Bring out PHY out of reset */
2797 ql_write_common_reg(qdev, &port_regs->CommonRegs.serialPortInterfaceReg,
2798 (ISP_SERIAL_PORT_IF_WE |
2799 (ISP_SERIAL_PORT_IF_WE << 16)));
2801 qdev->port_link_state = LS_DOWN;
2802 netif_carrier_off(qdev->ndev);
2804 /* V2 chip fix for ARS-39168. */
2805 ql_write_common_reg(qdev, &port_regs->CommonRegs.serialPortInterfaceReg,
2806 (ISP_SERIAL_PORT_IF_SDE |
2807 (ISP_SERIAL_PORT_IF_SDE << 16)));
2809 /* Request Queue Registers */
2810 *((u32 *) (qdev->preq_consumer_index)) = 0;
2811 atomic_set(&qdev->tx_count,NUM_REQ_Q_ENTRIES);
2812 qdev->req_producer_index = 0;
2814 ql_write_page1_reg(qdev,
2815 &hmem_regs->reqConsumerIndexAddrHigh,
2816 qdev->req_consumer_index_phy_addr_high);
2817 ql_write_page1_reg(qdev,
2818 &hmem_regs->reqConsumerIndexAddrLow,
2819 qdev->req_consumer_index_phy_addr_low);
2821 ql_write_page1_reg(qdev,
2822 &hmem_regs->reqBaseAddrHigh,
2823 MS_64BITS(qdev->req_q_phy_addr));
2824 ql_write_page1_reg(qdev,
2825 &hmem_regs->reqBaseAddrLow,
2826 LS_64BITS(qdev->req_q_phy_addr));
2827 ql_write_page1_reg(qdev, &hmem_regs->reqLength, NUM_REQ_Q_ENTRIES);
2829 /* Response Queue Registers */
2830 *((u16 *) (qdev->prsp_producer_index)) = 0;
2831 qdev->rsp_consumer_index = 0;
2832 qdev->rsp_current = qdev->rsp_q_virt_addr;
2834 ql_write_page1_reg(qdev,
2835 &hmem_regs->rspProducerIndexAddrHigh,
2836 qdev->rsp_producer_index_phy_addr_high);
2838 ql_write_page1_reg(qdev,
2839 &hmem_regs->rspProducerIndexAddrLow,
2840 qdev->rsp_producer_index_phy_addr_low);
2842 ql_write_page1_reg(qdev,
2843 &hmem_regs->rspBaseAddrHigh,
2844 MS_64BITS(qdev->rsp_q_phy_addr));
2846 ql_write_page1_reg(qdev,
2847 &hmem_regs->rspBaseAddrLow,
2848 LS_64BITS(qdev->rsp_q_phy_addr));
2850 ql_write_page1_reg(qdev, &hmem_regs->rspLength, NUM_RSP_Q_ENTRIES);
2852 /* Large Buffer Queue */
2853 ql_write_page1_reg(qdev,
2854 &hmem_regs->rxLargeQBaseAddrHigh,
2855 MS_64BITS(qdev->lrg_buf_q_phy_addr));
2857 ql_write_page1_reg(qdev,
2858 &hmem_regs->rxLargeQBaseAddrLow,
2859 LS_64BITS(qdev->lrg_buf_q_phy_addr));
2861 ql_write_page1_reg(qdev, &hmem_regs->rxLargeQLength, qdev->num_lbufq_entries);
2863 ql_write_page1_reg(qdev,
2864 &hmem_regs->rxLargeBufferLength,
2865 qdev->lrg_buffer_len);
2867 /* Small Buffer Queue */
2868 ql_write_page1_reg(qdev,
2869 &hmem_regs->rxSmallQBaseAddrHigh,
2870 MS_64BITS(qdev->small_buf_q_phy_addr));
2872 ql_write_page1_reg(qdev,
2873 &hmem_regs->rxSmallQBaseAddrLow,
2874 LS_64BITS(qdev->small_buf_q_phy_addr));
2876 ql_write_page1_reg(qdev, &hmem_regs->rxSmallQLength, NUM_SBUFQ_ENTRIES);
2877 ql_write_page1_reg(qdev,
2878 &hmem_regs->rxSmallBufferLength,
2879 QL_SMALL_BUFFER_SIZE);
2881 qdev->small_buf_q_producer_index = NUM_SBUFQ_ENTRIES - 1;
2882 qdev->small_buf_release_cnt = 8;
2883 qdev->lrg_buf_q_producer_index = qdev->num_lbufq_entries - 1;
2884 qdev->lrg_buf_release_cnt = 8;
2885 qdev->lrg_buf_next_free =
2886 (struct bufq_addr_element *)qdev->lrg_buf_q_virt_addr;
2887 qdev->small_buf_index = 0;
2888 qdev->lrg_buf_index = 0;
2889 qdev->lrg_buf_free_count = 0;
2890 qdev->lrg_buf_free_head = NULL;
2891 qdev->lrg_buf_free_tail = NULL;
2893 ql_write_common_reg(qdev,
2894 &port_regs->CommonRegs.
2895 rxSmallQProducerIndex,
2896 qdev->small_buf_q_producer_index);
2897 ql_write_common_reg(qdev,
2898 &port_regs->CommonRegs.
2899 rxLargeQProducerIndex,
2900 qdev->lrg_buf_q_producer_index);
2903 * Find out if the chip has already been initialized. If it has, then
2904 * we skip some of the initialization.
2906 clear_bit(QL_LINK_MASTER, &qdev->flags);
2907 value = ql_read_page0_reg(qdev, &port_regs->portStatus);
2908 if ((value & PORT_STATUS_IC) == 0) {
2910 /* Chip has not been configured yet, so let it rip. */
2911 if(ql_init_misc_registers(qdev)) {
2916 if (qdev->mac_index)
2917 ql_write_page0_reg(qdev,
2918 &port_regs->mac1MaxFrameLengthReg,
2919 qdev->max_frame_size);
2921 ql_write_page0_reg(qdev,
2922 &port_regs->mac0MaxFrameLengthReg,
2923 qdev->max_frame_size);
2925 value = qdev->nvram_data.tcpMaxWindowSize;
2926 ql_write_page0_reg(qdev, &port_regs->tcpMaxWindow, value);
2928 value = (0xFFFF << 16) | qdev->nvram_data.extHwConfig;
2930 if(ql_sem_spinlock(qdev, QL_FLASH_SEM_MASK,
2931 (QL_RESOURCE_BITS_BASE_CODE | (qdev->mac_index)
2936 ql_write_page0_reg(qdev, &port_regs->ExternalHWConfig, value);
2937 ql_write_page0_reg(qdev, &port_regs->InternalChipConfig,
2938 (((INTERNAL_CHIP_SD | INTERNAL_CHIP_WE) <<
2939 16) | (INTERNAL_CHIP_SD |
2940 INTERNAL_CHIP_WE)));
2941 ql_sem_unlock(qdev, QL_FLASH_SEM_MASK);
2945 if(ql_sem_spinlock(qdev, QL_PHY_GIO_SEM_MASK,
2946 (QL_RESOURCE_BITS_BASE_CODE | (qdev->mac_index) *
2952 ql_init_scan_mode(qdev);
2953 ql_get_phy_owner(qdev);
2955 /* Load the MAC Configuration */
2957 /* Program lower 32 bits of the MAC address */
2958 ql_write_page0_reg(qdev, &port_regs->macAddrIndirectPtrReg,
2959 (MAC_ADDR_INDIRECT_PTR_REG_RP_MASK << 16));
2960 ql_write_page0_reg(qdev, &port_regs->macAddrDataReg,
2961 ((qdev->ndev->dev_addr[2] << 24)
2962 | (qdev->ndev->dev_addr[3] << 16)
2963 | (qdev->ndev->dev_addr[4] << 8)
2964 | qdev->ndev->dev_addr[5]));
2966 /* Program top 16 bits of the MAC address */
2967 ql_write_page0_reg(qdev, &port_regs->macAddrIndirectPtrReg,
2968 ((MAC_ADDR_INDIRECT_PTR_REG_RP_MASK << 16) | 1));
2969 ql_write_page0_reg(qdev, &port_regs->macAddrDataReg,
2970 ((qdev->ndev->dev_addr[0] << 8)
2971 | qdev->ndev->dev_addr[1]));
2973 /* Enable Primary MAC */
2974 ql_write_page0_reg(qdev, &port_regs->macAddrIndirectPtrReg,
2975 ((MAC_ADDR_INDIRECT_PTR_REG_PE << 16) |
2976 MAC_ADDR_INDIRECT_PTR_REG_PE));
2978 /* Clear Primary and Secondary IP addresses */
2979 ql_write_page0_reg(qdev, &port_regs->ipAddrIndexReg,
2980 ((IP_ADDR_INDEX_REG_MASK << 16) |
2981 (qdev->mac_index << 2)));
2982 ql_write_page0_reg(qdev, &port_regs->ipAddrDataReg, 0);
2984 ql_write_page0_reg(qdev, &port_regs->ipAddrIndexReg,
2985 ((IP_ADDR_INDEX_REG_MASK << 16) |
2986 ((qdev->mac_index << 2) + 1)));
2987 ql_write_page0_reg(qdev, &port_regs->ipAddrDataReg, 0);
2989 ql_sem_unlock(qdev, QL_PHY_GIO_SEM_MASK);
2991 /* Indicate Configuration Complete */
2992 ql_write_page0_reg(qdev,
2993 &port_regs->portControl,
2994 ((PORT_CONTROL_CC << 16) | PORT_CONTROL_CC));
2997 value = ql_read_page0_reg(qdev, &port_regs->portStatus);
2998 if (value & PORT_STATUS_IC)
3005 "%s: Hw Initialization timeout.\n", qdev->ndev->name);
3010 /* Enable Ethernet Function */
3011 if (qdev->device_id == QL3032_DEVICE_ID) {
3013 (QL3032_PORT_CONTROL_EF | QL3032_PORT_CONTROL_KIE |
3014 QL3032_PORT_CONTROL_EIv6 | QL3032_PORT_CONTROL_EIv4);
3015 ql_write_page0_reg(qdev, &port_regs->functionControl,
3016 ((value << 16) | value));
3019 (PORT_CONTROL_EF | PORT_CONTROL_ET | PORT_CONTROL_EI |
3021 ql_write_page0_reg(qdev, &port_regs->portControl,
3022 ((value << 16) | value));
3031 * Caller holds hw_lock.
3033 static int ql_adapter_reset(struct ql3_adapter *qdev)
3035 struct ql3xxx_port_registers __iomem *port_regs = qdev->mem_map_registers;
3040 set_bit(QL_RESET_ACTIVE, &qdev->flags);
3041 clear_bit(QL_RESET_DONE, &qdev->flags);
3044 * Issue soft reset to chip.
3046 printk(KERN_DEBUG PFX
3047 "%s: Issue soft reset to chip.\n",
3049 ql_write_common_reg(qdev,
3050 &port_regs->CommonRegs.ispControlStatus,
3051 ((ISP_CONTROL_SR << 16) | ISP_CONTROL_SR));
3053 /* Wait 3 seconds for reset to complete. */
3054 printk(KERN_DEBUG PFX
3055 "%s: Wait 10 milliseconds for reset to complete.\n",
3058 /* Wait until the firmware tells us the Soft Reset is done */
3062 ql_read_common_reg(qdev,
3063 &port_regs->CommonRegs.ispControlStatus);
3064 if ((value & ISP_CONTROL_SR) == 0)
3068 } while ((--max_wait_time));
3071 * Also, make sure that the Network Reset Interrupt bit has been
3072 * cleared after the soft reset has taken place.
3075 ql_read_common_reg(qdev, &port_regs->CommonRegs.ispControlStatus);
3076 if (value & ISP_CONTROL_RI) {
3077 printk(KERN_DEBUG PFX
3078 "ql_adapter_reset: clearing RI after reset.\n");
3079 ql_write_common_reg(qdev,
3080 &port_regs->CommonRegs.
3082 ((ISP_CONTROL_RI << 16) | ISP_CONTROL_RI));
3085 if (max_wait_time == 0) {
3086 /* Issue Force Soft Reset */
3087 ql_write_common_reg(qdev,
3088 &port_regs->CommonRegs.
3090 ((ISP_CONTROL_FSR << 16) |
3093 * Wait until the firmware tells us the Force Soft Reset is
3099 ql_read_common_reg(qdev,
3100 &port_regs->CommonRegs.
3102 if ((value & ISP_CONTROL_FSR) == 0) {
3106 } while ((--max_wait_time));
3108 if (max_wait_time == 0)
3111 clear_bit(QL_RESET_ACTIVE, &qdev->flags);
3112 set_bit(QL_RESET_DONE, &qdev->flags);
3116 static void ql_set_mac_info(struct ql3_adapter *qdev)
3118 struct ql3xxx_port_registers __iomem *port_regs = qdev->mem_map_registers;
3119 u32 value, port_status;
3122 /* Get the function number */
3124 ql_read_common_reg_l(qdev, &port_regs->CommonRegs.ispControlStatus);
3125 func_number = (u8) ((value >> 4) & OPCODE_FUNC_ID_MASK);
3126 port_status = ql_read_page0_reg(qdev, &port_regs->portStatus);
3127 switch (value & ISP_CONTROL_FN_MASK) {
3128 case ISP_CONTROL_FN0_NET:
3129 qdev->mac_index = 0;
3130 qdev->mac_ob_opcode = OUTBOUND_MAC_IOCB | func_number;
3131 qdev->tcp_ob_opcode = OUTBOUND_TCP_IOCB | func_number;
3132 qdev->update_ob_opcode = UPDATE_NCB_IOCB | func_number;
3133 qdev->mb_bit_mask = FN0_MA_BITS_MASK;
3134 qdev->PHYAddr = PORT0_PHY_ADDRESS;
3135 if (port_status & PORT_STATUS_SM0)
3136 set_bit(QL_LINK_OPTICAL,&qdev->flags);
3138 clear_bit(QL_LINK_OPTICAL,&qdev->flags);
3141 case ISP_CONTROL_FN1_NET:
3142 qdev->mac_index = 1;
3143 qdev->mac_ob_opcode = OUTBOUND_MAC_IOCB | func_number;
3144 qdev->tcp_ob_opcode = OUTBOUND_TCP_IOCB | func_number;
3145 qdev->update_ob_opcode = UPDATE_NCB_IOCB | func_number;
3146 qdev->mb_bit_mask = FN1_MA_BITS_MASK;
3147 qdev->PHYAddr = PORT1_PHY_ADDRESS;
3148 if (port_status & PORT_STATUS_SM1)
3149 set_bit(QL_LINK_OPTICAL,&qdev->flags);
3151 clear_bit(QL_LINK_OPTICAL,&qdev->flags);
3154 case ISP_CONTROL_FN0_SCSI:
3155 case ISP_CONTROL_FN1_SCSI:
3157 printk(KERN_DEBUG PFX
3158 "%s: Invalid function number, ispControlStatus = 0x%x\n",
3159 qdev->ndev->name,value);
3162 qdev->numPorts = qdev->nvram_data.numPorts;
3165 static void ql_display_dev_info(struct net_device *ndev)
3167 struct ql3_adapter *qdev = (struct ql3_adapter *)netdev_priv(ndev);
3168 struct pci_dev *pdev = qdev->pdev;
3170 printk(KERN_INFO PFX
3171 "\n%s Adapter %d RevisionID %d found %s on PCI slot %d.\n",
3172 DRV_NAME, qdev->index, qdev->chip_rev_id,
3173 (qdev->device_id == QL3032_DEVICE_ID) ? "QLA3032" : "QLA3022",
3175 printk(KERN_INFO PFX
3177 test_bit(QL_LINK_OPTICAL,&qdev->flags) ? "OPTICAL" : "COPPER");
3180 * Print PCI bus width/type.
3182 printk(KERN_INFO PFX
3183 "Bus interface is %s %s.\n",
3184 ((qdev->pci_width == 64) ? "64-bit" : "32-bit"),
3185 ((qdev->pci_x) ? "PCI-X" : "PCI"));
3187 printk(KERN_INFO PFX
3188 "mem IO base address adjusted = 0x%p\n",
3189 qdev->mem_map_registers);
3190 printk(KERN_INFO PFX "Interrupt number = %d\n", pdev->irq);
3192 if (netif_msg_probe(qdev))
3193 printk(KERN_INFO PFX
3194 "%s: MAC address %02x:%02x:%02x:%02x:%02x:%02x\n",
3195 ndev->name, ndev->dev_addr[0], ndev->dev_addr[1],
3196 ndev->dev_addr[2], ndev->dev_addr[3], ndev->dev_addr[4],
3200 static int ql_adapter_down(struct ql3_adapter *qdev, int do_reset)
3202 struct net_device *ndev = qdev->ndev;
3205 netif_stop_queue(ndev);
3206 netif_carrier_off(ndev);
3208 clear_bit(QL_ADAPTER_UP,&qdev->flags);
3209 clear_bit(QL_LINK_MASTER,&qdev->flags);
3211 ql_disable_interrupts(qdev);
3213 free_irq(qdev->pdev->irq, ndev);
3215 if (qdev->msi && test_bit(QL_MSI_ENABLED,&qdev->flags)) {
3216 printk(KERN_INFO PFX
3217 "%s: calling pci_disable_msi().\n", qdev->ndev->name);
3218 clear_bit(QL_MSI_ENABLED,&qdev->flags);
3219 pci_disable_msi(qdev->pdev);
3222 del_timer_sync(&qdev->adapter_timer);
3224 netif_poll_disable(ndev);
3228 unsigned long hw_flags;
3230 spin_lock_irqsave(&qdev->hw_lock, hw_flags);
3231 if (ql_wait_for_drvr_lock(qdev)) {
3232 if ((soft_reset = ql_adapter_reset(qdev))) {
3234 "%s: ql_adapter_reset(%d) FAILED!\n",
3235 ndev->name, qdev->index);
3238 "%s: Releaseing driver lock via chip reset.\n",ndev->name);
3241 "%s: Could not acquire driver lock to do "
3242 "reset!\n", ndev->name);
3245 spin_unlock_irqrestore(&qdev->hw_lock, hw_flags);
3247 ql_free_mem_resources(qdev);
3251 static int ql_adapter_up(struct ql3_adapter *qdev)
3253 struct net_device *ndev = qdev->ndev;
3255 unsigned long irq_flags = IRQF_SAMPLE_RANDOM | IRQF_SHARED;
3256 unsigned long hw_flags;
3258 if (ql_alloc_mem_resources(qdev)) {
3260 "%s Unable to allocate buffers.\n", ndev->name);
3265 if (pci_enable_msi(qdev->pdev)) {
3267 "%s: User requested MSI, but MSI failed to "
3268 "initialize. Continuing without MSI.\n",
3272 printk(KERN_INFO PFX "%s: MSI Enabled...\n", qdev->ndev->name);
3273 set_bit(QL_MSI_ENABLED,&qdev->flags);
3274 irq_flags &= ~IRQF_SHARED;
3278 if ((err = request_irq(qdev->pdev->irq,
3280 irq_flags, ndev->name, ndev))) {
3282 "%s: Failed to reserve interrupt %d already in use.\n",
3283 ndev->name, qdev->pdev->irq);
3287 spin_lock_irqsave(&qdev->hw_lock, hw_flags);
3289 if ((err = ql_wait_for_drvr_lock(qdev))) {
3290 if ((err = ql_adapter_initialize(qdev))) {
3292 "%s: Unable to initialize adapter.\n",
3297 "%s: Releaseing driver lock.\n",ndev->name);
3298 ql_sem_unlock(qdev, QL_DRVR_SEM_MASK);
3301 "%s: Could not aquire driver lock.\n",
3306 spin_unlock_irqrestore(&qdev->hw_lock, hw_flags);
3308 set_bit(QL_ADAPTER_UP,&qdev->flags);
3310 mod_timer(&qdev->adapter_timer, jiffies + HZ * 1);
3312 netif_poll_enable(ndev);
3313 ql_enable_interrupts(qdev);
3317 ql_sem_unlock(qdev, QL_DRVR_SEM_MASK);
3319 spin_unlock_irqrestore(&qdev->hw_lock, hw_flags);
3320 free_irq(qdev->pdev->irq, ndev);
3322 if (qdev->msi && test_bit(QL_MSI_ENABLED,&qdev->flags)) {
3323 printk(KERN_INFO PFX
3324 "%s: calling pci_disable_msi().\n",
3326 clear_bit(QL_MSI_ENABLED,&qdev->flags);
3327 pci_disable_msi(qdev->pdev);
3332 static int ql_cycle_adapter(struct ql3_adapter *qdev, int reset)
3334 if( ql_adapter_down(qdev,reset) || ql_adapter_up(qdev)) {
3336 "%s: Driver up/down cycle failed, "
3337 "closing device\n",qdev->ndev->name);
3338 dev_close(qdev->ndev);
3344 static int ql3xxx_close(struct net_device *ndev)
3346 struct ql3_adapter *qdev = netdev_priv(ndev);
3349 * Wait for device to recover from a reset.
3350 * (Rarely happens, but possible.)
3352 while (!test_bit(QL_ADAPTER_UP,&qdev->flags))
3355 ql_adapter_down(qdev,QL_DO_RESET);
3359 static int ql3xxx_open(struct net_device *ndev)
3361 struct ql3_adapter *qdev = netdev_priv(ndev);
3362 return (ql_adapter_up(qdev));
3365 static struct net_device_stats *ql3xxx_get_stats(struct net_device *dev)
3367 struct ql3_adapter *qdev = (struct ql3_adapter *)dev->priv;
3368 return &qdev->stats;
3371 static void ql3xxx_set_multicast_list(struct net_device *ndev)
3374 * We are manually parsing the list in the net_device structure.
3379 static int ql3xxx_set_mac_address(struct net_device *ndev, void *p)
3381 struct ql3_adapter *qdev = (struct ql3_adapter *)netdev_priv(ndev);
3382 struct ql3xxx_port_registers __iomem *port_regs =
3383 qdev->mem_map_registers;
3384 struct sockaddr *addr = p;
3385 unsigned long hw_flags;
3387 if (netif_running(ndev))
3390 if (!is_valid_ether_addr(addr->sa_data))
3391 return -EADDRNOTAVAIL;
3393 memcpy(ndev->dev_addr, addr->sa_data, ndev->addr_len);
3395 spin_lock_irqsave(&qdev->hw_lock, hw_flags);
3396 /* Program lower 32 bits of the MAC address */
3397 ql_write_page0_reg(qdev, &port_regs->macAddrIndirectPtrReg,
3398 (MAC_ADDR_INDIRECT_PTR_REG_RP_MASK << 16));
3399 ql_write_page0_reg(qdev, &port_regs->macAddrDataReg,
3400 ((ndev->dev_addr[2] << 24) | (ndev->
3401 dev_addr[3] << 16) |
3402 (ndev->dev_addr[4] << 8) | ndev->dev_addr[5]));
3404 /* Program top 16 bits of the MAC address */
3405 ql_write_page0_reg(qdev, &port_regs->macAddrIndirectPtrReg,
3406 ((MAC_ADDR_INDIRECT_PTR_REG_RP_MASK << 16) | 1));
3407 ql_write_page0_reg(qdev, &port_regs->macAddrDataReg,
3408 ((ndev->dev_addr[0] << 8) | ndev->dev_addr[1]));
3409 spin_unlock_irqrestore(&qdev->hw_lock, hw_flags);
3414 static void ql3xxx_tx_timeout(struct net_device *ndev)
3416 struct ql3_adapter *qdev = (struct ql3_adapter *)netdev_priv(ndev);
3418 printk(KERN_ERR PFX "%s: Resetting...\n", ndev->name);
3420 * Stop the queues, we've got a problem.
3422 netif_stop_queue(ndev);
3425 * Wake up the worker to process this event.
3427 queue_delayed_work(qdev->workqueue, &qdev->tx_timeout_work, 0);
3430 static void ql_reset_work(struct work_struct *work)
3432 struct ql3_adapter *qdev =
3433 container_of(work, struct ql3_adapter, reset_work.work);
3434 struct net_device *ndev = qdev->ndev;
3436 struct ql_tx_buf_cb *tx_cb;
3437 int max_wait_time, i;
3438 struct ql3xxx_port_registers __iomem *port_regs = qdev->mem_map_registers;
3439 unsigned long hw_flags;
3441 if (test_bit((QL_RESET_PER_SCSI | QL_RESET_START),&qdev->flags)) {
3442 clear_bit(QL_LINK_MASTER,&qdev->flags);
3445 * Loop through the active list and return the skb.
3447 for (i = 0; i < NUM_REQ_Q_ENTRIES; i++) {
3449 tx_cb = &qdev->tx_buf[i];
3451 printk(KERN_DEBUG PFX
3452 "%s: Freeing lost SKB.\n",
3454 pci_unmap_single(qdev->pdev,
3455 pci_unmap_addr(&tx_cb->map[0], mapaddr),
3456 pci_unmap_len(&tx_cb->map[0], maplen),
3458 for(j=1;j<tx_cb->seg_count;j++) {
3459 pci_unmap_page(qdev->pdev,
3460 pci_unmap_addr(&tx_cb->map[j],mapaddr),
3461 pci_unmap_len(&tx_cb->map[j],maplen),
3464 dev_kfree_skb(tx_cb->skb);
3470 "%s: Clearing NRI after reset.\n", qdev->ndev->name);
3471 spin_lock_irqsave(&qdev->hw_lock, hw_flags);
3472 ql_write_common_reg(qdev,
3473 &port_regs->CommonRegs.
3475 ((ISP_CONTROL_RI << 16) | ISP_CONTROL_RI));
3477 * Wait the for Soft Reset to Complete.
3481 value = ql_read_common_reg(qdev,
3482 &port_regs->CommonRegs.
3485 if ((value & ISP_CONTROL_SR) == 0) {
3486 printk(KERN_DEBUG PFX
3487 "%s: reset completed.\n",
3492 if (value & ISP_CONTROL_RI) {
3493 printk(KERN_DEBUG PFX
3494 "%s: clearing NRI after reset.\n",
3496 ql_write_common_reg(qdev,
3501 16) | ISP_CONTROL_RI));
3505 } while (--max_wait_time);
3506 spin_unlock_irqrestore(&qdev->hw_lock, hw_flags);
3508 if (value & ISP_CONTROL_SR) {
3511 * Set the reset flags and clear the board again.
3512 * Nothing else to do...
3515 "%s: Timed out waiting for reset to "
3516 "complete.\n", ndev->name);
3518 "%s: Do a reset.\n", ndev->name);
3519 clear_bit(QL_RESET_PER_SCSI,&qdev->flags);
3520 clear_bit(QL_RESET_START,&qdev->flags);
3521 ql_cycle_adapter(qdev,QL_DO_RESET);
3525 clear_bit(QL_RESET_ACTIVE,&qdev->flags);
3526 clear_bit(QL_RESET_PER_SCSI,&qdev->flags);
3527 clear_bit(QL_RESET_START,&qdev->flags);
3528 ql_cycle_adapter(qdev,QL_NO_RESET);
3532 static void ql_tx_timeout_work(struct work_struct *work)
3534 struct ql3_adapter *qdev =
3535 container_of(work, struct ql3_adapter, tx_timeout_work.work);
3537 ql_cycle_adapter(qdev, QL_DO_RESET);
3540 static void ql_get_board_info(struct ql3_adapter *qdev)
3542 struct ql3xxx_port_registers __iomem *port_regs = qdev->mem_map_registers;
3545 value = ql_read_page0_reg_l(qdev, &port_regs->portStatus);
3547 qdev->chip_rev_id = ((value & PORT_STATUS_REV_ID_MASK) >> 12);
3548 if (value & PORT_STATUS_64)
3549 qdev->pci_width = 64;
3551 qdev->pci_width = 32;
3552 if (value & PORT_STATUS_X)
3556 qdev->pci_slot = (u8) PCI_SLOT(qdev->pdev->devfn);
3559 static void ql3xxx_timer(unsigned long ptr)
3561 struct ql3_adapter *qdev = (struct ql3_adapter *)ptr;
3563 if (test_bit(QL_RESET_ACTIVE,&qdev->flags)) {
3564 printk(KERN_DEBUG PFX
3565 "%s: Reset in progress.\n",
3570 ql_link_state_machine(qdev);
3572 /* Restart timer on 2 second interval. */
3574 mod_timer(&qdev->adapter_timer, jiffies + HZ * 1);
3577 static int __devinit ql3xxx_probe(struct pci_dev *pdev,
3578 const struct pci_device_id *pci_entry)
3580 struct net_device *ndev = NULL;
3581 struct ql3_adapter *qdev = NULL;
3582 static int cards_found = 0;
3583 int pci_using_dac, err;
3585 err = pci_enable_device(pdev);
3587 printk(KERN_ERR PFX "%s cannot enable PCI device\n",
3592 err = pci_request_regions(pdev, DRV_NAME);
3594 printk(KERN_ERR PFX "%s cannot obtain PCI resources\n",
3596 goto err_out_disable_pdev;
3599 pci_set_master(pdev);
3601 if (!pci_set_dma_mask(pdev, DMA_64BIT_MASK)) {
3603 err = pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK);
3604 } else if (!(err = pci_set_dma_mask(pdev, DMA_32BIT_MASK))) {
3606 err = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
3610 printk(KERN_ERR PFX "%s no usable DMA configuration\n",
3612 goto err_out_free_regions;
3615 ndev = alloc_etherdev(sizeof(struct ql3_adapter));
3617 printk(KERN_ERR PFX "%s could not alloc etherdev\n",
3620 goto err_out_free_regions;
3623 SET_MODULE_OWNER(ndev);
3624 SET_NETDEV_DEV(ndev, &pdev->dev);
3626 pci_set_drvdata(pdev, ndev);
3628 qdev = netdev_priv(ndev);
3629 qdev->index = cards_found;
3632 qdev->device_id = pci_entry->device;
3633 qdev->port_link_state = LS_DOWN;
3637 qdev->msg_enable = netif_msg_init(debug, default_msg);
3640 ndev->features |= NETIF_F_HIGHDMA;
3641 if (qdev->device_id == QL3032_DEVICE_ID)
3642 ndev->features |= (NETIF_F_HW_CSUM | NETIF_F_SG);
3644 qdev->mem_map_registers =
3645 ioremap_nocache(pci_resource_start(pdev, 1),
3646 pci_resource_len(qdev->pdev, 1));
3647 if (!qdev->mem_map_registers) {
3648 printk(KERN_ERR PFX "%s: cannot map device registers\n",
3651 goto err_out_free_ndev;
3654 spin_lock_init(&qdev->adapter_lock);
3655 spin_lock_init(&qdev->hw_lock);
3657 /* Set driver entry points */
3658 ndev->open = ql3xxx_open;
3659 ndev->hard_start_xmit = ql3xxx_send;
3660 ndev->stop = ql3xxx_close;
3661 ndev->get_stats = ql3xxx_get_stats;
3662 ndev->set_multicast_list = ql3xxx_set_multicast_list;
3663 SET_ETHTOOL_OPS(ndev, &ql3xxx_ethtool_ops);
3664 ndev->set_mac_address = ql3xxx_set_mac_address;
3665 ndev->tx_timeout = ql3xxx_tx_timeout;
3666 ndev->watchdog_timeo = 5 * HZ;
3668 ndev->poll = &ql_poll;
3671 ndev->irq = pdev->irq;
3673 /* make sure the EEPROM is good */
3674 if (ql_get_nvram_params(qdev)) {
3675 printk(KERN_ALERT PFX
3676 "ql3xxx_probe: Adapter #%d, Invalid NVRAM parameters.\n",
3679 goto err_out_iounmap;
3682 ql_set_mac_info(qdev);
3684 /* Validate and set parameters */
3685 if (qdev->mac_index) {
3686 ndev->mtu = qdev->nvram_data.macCfg_port1.etherMtu_mac ;
3687 memcpy(ndev->dev_addr, &qdev->nvram_data.funcCfg_fn2.macAddress,
3690 ndev->mtu = qdev->nvram_data.macCfg_port0.etherMtu_mac ;
3691 memcpy(ndev->dev_addr, &qdev->nvram_data.funcCfg_fn0.macAddress,
3694 memcpy(ndev->perm_addr, ndev->dev_addr, ndev->addr_len);
3696 ndev->tx_queue_len = NUM_REQ_Q_ENTRIES;
3698 /* Turn off support for multicasting */
3699 ndev->flags &= ~IFF_MULTICAST;
3701 /* Record PCI bus information. */
3702 ql_get_board_info(qdev);
3705 * Set the Maximum Memory Read Byte Count value. We do this to handle
3709 pci_write_config_word(pdev, (int)0x4e, (u16) 0x0036);
3712 err = register_netdev(ndev);
3714 printk(KERN_ERR PFX "%s: cannot register net device\n",
3716 goto err_out_iounmap;
3719 /* we're going to reset, so assume we have no link for now */
3721 netif_carrier_off(ndev);
3722 netif_stop_queue(ndev);
3724 qdev->workqueue = create_singlethread_workqueue(ndev->name);
3725 INIT_DELAYED_WORK(&qdev->reset_work, ql_reset_work);
3726 INIT_DELAYED_WORK(&qdev->tx_timeout_work, ql_tx_timeout_work);
3728 init_timer(&qdev->adapter_timer);
3729 qdev->adapter_timer.function = ql3xxx_timer;
3730 qdev->adapter_timer.expires = jiffies + HZ * 2; /* two second delay */
3731 qdev->adapter_timer.data = (unsigned long)qdev;
3734 printk(KERN_ALERT PFX "%s\n", DRV_STRING);
3735 printk(KERN_ALERT PFX "Driver name: %s, Version: %s.\n",
3736 DRV_NAME, DRV_VERSION);
3738 ql_display_dev_info(ndev);
3744 iounmap(qdev->mem_map_registers);
3747 err_out_free_regions:
3748 pci_release_regions(pdev);
3749 err_out_disable_pdev:
3750 pci_disable_device(pdev);
3751 pci_set_drvdata(pdev, NULL);
3756 static void __devexit ql3xxx_remove(struct pci_dev *pdev)
3758 struct net_device *ndev = pci_get_drvdata(pdev);
3759 struct ql3_adapter *qdev = netdev_priv(ndev);
3761 unregister_netdev(ndev);
3762 qdev = netdev_priv(ndev);
3764 ql_disable_interrupts(qdev);
3766 if (qdev->workqueue) {
3767 cancel_delayed_work(&qdev->reset_work);
3768 cancel_delayed_work(&qdev->tx_timeout_work);
3769 destroy_workqueue(qdev->workqueue);
3770 qdev->workqueue = NULL;
3773 iounmap(qdev->mem_map_registers);
3774 pci_release_regions(pdev);
3775 pci_set_drvdata(pdev, NULL);
3779 static struct pci_driver ql3xxx_driver = {
3782 .id_table = ql3xxx_pci_tbl,
3783 .probe = ql3xxx_probe,
3784 .remove = __devexit_p(ql3xxx_remove),
3787 static int __init ql3xxx_init_module(void)
3789 return pci_register_driver(&ql3xxx_driver);
3792 static void __exit ql3xxx_exit(void)
3794 pci_unregister_driver(&ql3xxx_driver);
3797 module_init(ql3xxx_init_module);
3798 module_exit(ql3xxx_exit);