err.no Git - linux-2.6/blob - drivers/net/qla3xxx.c

   1 /*
   2  * QLogic QLA3xxx NIC HBA Driver
   3  * Copyright (c)  2003-2006 QLogic Corporation
   4  *
   5  * See LICENSE.qla3xxx for copyright and licensing details.
   6  */
   7
   8 #include <linux/kernel.h>
   9 #include <linux/init.h>
  10 #include <linux/types.h>
  11 #include <linux/module.h>
  12 #include <linux/list.h>
  13 #include <linux/pci.h>
  14 #include <linux/dma-mapping.h>
  15 #include <linux/sched.h>
  16 #include <linux/slab.h>
  17 #include <linux/dmapool.h>
  18 #include <linux/mempool.h>
  19 #include <linux/spinlock.h>
  20 #include <linux/kthread.h>
  21 #include <linux/interrupt.h>
  22 #include <linux/errno.h>
  23 #include <linux/ioport.h>
  24 #include <linux/ip.h>
  25 #include <linux/in.h>
  26 #include <linux/if_arp.h>
  27 #include <linux/if_ether.h>
  28 #include <linux/netdevice.h>
  29 #include <linux/etherdevice.h>
  30 #include <linux/ethtool.h>
  31 #include <linux/skbuff.h>
  32 #include <linux/rtnetlink.h>
  33 #include <linux/if_vlan.h>
  34 #include <linux/init.h>
  35 #include <linux/delay.h>
  36 #include <linux/mm.h>
  37
  38 #include "qla3xxx.h"
  39
  40 #define DRV_NAME        "qla3xxx"
  41 #define DRV_STRING      "QLogic ISP3XXX Network Driver"
  42 #define DRV_VERSION     "v2.02.00-k36"
  43 #define PFX             DRV_NAME " "
  44
  45 static const char ql3xxx_driver_name[] = DRV_NAME;
  46 static const char ql3xxx_driver_version[] = DRV_VERSION;
  47
  48 MODULE_AUTHOR("QLogic Corporation");
  49 MODULE_DESCRIPTION("QLogic ISP3XXX Network Driver " DRV_VERSION " ");
  50 MODULE_LICENSE("GPL");
  51 MODULE_VERSION(DRV_VERSION);
  52
  53 static const u32 default_msg
  54     = NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_LINK
  55     | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN;
  56
  57 static int debug = -1;          /* defaults above */
  58 module_param(debug, int, 0);
  59 MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
  60
  61 static int msi;
  62 module_param(msi, int, 0);
  63 MODULE_PARM_DESC(msi, "Turn on Message Signaled Interrupts.");
  64
  65 static struct pci_device_id ql3xxx_pci_tbl[] __devinitdata = {
  66         {PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, QL3022_DEVICE_ID)},
  67         {PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, QL3032_DEVICE_ID)},
  68         /* required last entry */
  69         {0,}
  70 };
  71
  72 MODULE_DEVICE_TABLE(pci, ql3xxx_pci_tbl);
  73
  74 /*
  75  * Caller must take hw_lock.
  76  */
  77 static int ql_sem_spinlock(struct ql3_adapter *qdev,
  78                             u32 sem_mask, u32 sem_bits)
  79 {
  80         struct ql3xxx_port_registers __iomem *port_regs = qdev->mem_map_registers;
  81         u32 value;
  82         unsigned int seconds = 3;
  83
  84         do {
  85                 writel((sem_mask | sem_bits),
  86                        &port_regs->CommonRegs.semaphoreReg);
  87                 value = readl(&port_regs->CommonRegs.semaphoreReg);
  88                 if ((value & (sem_mask >> 16)) == sem_bits)
  89                         return 0;
  90                 ssleep(1);
  91         } while(--seconds);
  92         return -1;
  93 }
  94
  95 static void ql_sem_unlock(struct ql3_adapter *qdev, u32 sem_mask)
  96 {
  97         struct ql3xxx_port_registers __iomem *port_regs = qdev->mem_map_registers;
  98         writel(sem_mask, &port_regs->CommonRegs.semaphoreReg);
  99         readl(&port_regs->CommonRegs.semaphoreReg);
 100 }
 101
 102 static int ql_sem_lock(struct ql3_adapter *qdev, u32 sem_mask, u32 sem_bits)
 103 {
 104         struct ql3xxx_port_registers __iomem *port_regs = qdev->mem_map_registers;
 105         u32 value;
 106
 107         writel((sem_mask | sem_bits), &port_regs->CommonRegs.semaphoreReg);
 108         value = readl(&port_regs->CommonRegs.semaphoreReg);
 109         return ((value & (sem_mask >> 16)) == sem_bits);
 110 }
 111
 112 /*
 113  * Caller holds hw_lock.
 114  */
 115 static int ql_wait_for_drvr_lock(struct ql3_adapter *qdev)
 116 {
 117         int i = 0;
 118
 119         while (1) {
 120                 if (!ql_sem_lock(qdev,
 121                                  QL_DRVR_SEM_MASK,
 122                                  (QL_RESOURCE_BITS_BASE_CODE | (qdev->mac_index)
 123                                   * 2) << 1)) {
 124                         if (i < 10) {
 125                                 ssleep(1);
 126                                 i++;
 127                         } else {
 128                                 printk(KERN_ERR PFX "%s: Timed out waiting for "
 129                                        "driver lock...\n",
 130                                        qdev->ndev->name);
 131                                 return 0;
 132                         }
 133                 } else {
 134                         printk(KERN_DEBUG PFX
 135                                "%s: driver lock acquired.\n",
 136                                qdev->ndev->name);
 137                         return 1;
 138                 }
 139         }
 140 }
 141
 142 static void ql_set_register_page(struct ql3_adapter *qdev, u32 page)
 143 {
 144         struct ql3xxx_port_registers __iomem *port_regs = qdev->mem_map_registers;
 145
 146         writel(((ISP_CONTROL_NP_MASK << 16) | page),
 147                         &port_regs->CommonRegs.ispControlStatus);
 148         readl(&port_regs->CommonRegs.ispControlStatus);
 149         qdev->current_page = page;
 150 }
 151
 152 static u32 ql_read_common_reg_l(struct ql3_adapter *qdev,
 153                               u32 __iomem * reg)
 154 {
 155         u32 value;
 156         unsigned long hw_flags;
 157
 158         spin_lock_irqsave(&qdev->hw_lock, hw_flags);
 159         value = readl(reg);
 160         spin_unlock_irqrestore(&qdev->hw_lock, hw_flags);
 161
 162         return value;
 163 }
 164
 165 static u32 ql_read_common_reg(struct ql3_adapter *qdev,
 166                               u32 __iomem * reg)
 167 {
 168         return readl(reg);
 169 }
 170
 171 static u32 ql_read_page0_reg_l(struct ql3_adapter *qdev, u32 __iomem *reg)
 172 {
 173         u32 value;
 174         unsigned long hw_flags;
 175
 176         spin_lock_irqsave(&qdev->hw_lock, hw_flags);
 177
 178         if (qdev->current_page != 0)
 179                 ql_set_register_page(qdev,0);
 180         value = readl(reg);
 181
 182         spin_unlock_irqrestore(&qdev->hw_lock, hw_flags);
 183         return value;
 184 }
 185
 186 static u32 ql_read_page0_reg(struct ql3_adapter *qdev, u32 __iomem *reg)
 187 {
 188         if (qdev->current_page != 0)
 189                 ql_set_register_page(qdev,0);
 190         return readl(reg);
 191 }
 192
 193 static void ql_write_common_reg_l(struct ql3_adapter *qdev,
 194                                 u32 __iomem *reg, u32 value)
 195 {
 196         unsigned long hw_flags;
 197
 198         spin_lock_irqsave(&qdev->hw_lock, hw_flags);
 199         writel(value, reg);
 200         readl(reg);
 201         spin_unlock_irqrestore(&qdev->hw_lock, hw_flags);
 202         return;
 203 }
 204
 205 static void ql_write_common_reg(struct ql3_adapter *qdev,
 206                                 u32 __iomem *reg, u32 value)
 207 {
 208         writel(value, reg);
 209         readl(reg);
 210         return;
 211 }
 212
 213 static void ql_write_nvram_reg(struct ql3_adapter *qdev,
 214                                 u32 __iomem *reg, u32 value)
 215 {
 216         writel(value, reg);
 217         readl(reg);
 218         udelay(1);
 219         return;
 220 }
 221
 222 static void ql_write_page0_reg(struct ql3_adapter *qdev,
 223                                u32 __iomem *reg, u32 value)
 224 {
 225         if (qdev->current_page != 0)
 226                 ql_set_register_page(qdev,0);
 227         writel(value, reg);
 228         readl(reg);
 229         return;
 230 }
 231
 232 /*
 233  * Caller holds hw_lock. Only called during init.
 234  */
 235 static void ql_write_page1_reg(struct ql3_adapter *qdev,
 236                                u32 __iomem *reg, u32 value)
 237 {
 238         if (qdev->current_page != 1)
 239                 ql_set_register_page(qdev,1);
 240         writel(value, reg);
 241         readl(reg);
 242         return;
 243 }
 244
 245 /*
 246  * Caller holds hw_lock. Only called during init.
 247  */
 248 static void ql_write_page2_reg(struct ql3_adapter *qdev,
 249                                u32 __iomem *reg, u32 value)
 250 {
 251         if (qdev->current_page != 2)
 252                 ql_set_register_page(qdev,2);
 253         writel(value, reg);
 254         readl(reg);
 255         return;
 256 }
 257
 258 static void ql_disable_interrupts(struct ql3_adapter *qdev)
 259 {
 260         struct ql3xxx_port_registers __iomem *port_regs = qdev->mem_map_registers;
 261
 262         ql_write_common_reg_l(qdev, &port_regs->CommonRegs.ispInterruptMaskReg,
 263                             (ISP_IMR_ENABLE_INT << 16));
 264
 265 }
 266
 267 static void ql_enable_interrupts(struct ql3_adapter *qdev)
 268 {
 269         struct ql3xxx_port_registers __iomem *port_regs = qdev->mem_map_registers;
 270
 271         ql_write_common_reg_l(qdev, &port_regs->CommonRegs.ispInterruptMaskReg,
 272                             ((0xff << 16) | ISP_IMR_ENABLE_INT));
 273
 274 }
 275
 276 static void ql_release_to_lrg_buf_free_list(struct ql3_adapter *qdev,
 277                                             struct ql_rcv_buf_cb *lrg_buf_cb)
 278 {
 279         dma_addr_t map;
 280         int err;
 281         lrg_buf_cb->next = NULL;
 282
 283         if (qdev->lrg_buf_free_tail == NULL) {  /* The list is empty  */
 284                 qdev->lrg_buf_free_head = qdev->lrg_buf_free_tail = lrg_buf_cb;
 285         } else {
 286                 qdev->lrg_buf_free_tail->next = lrg_buf_cb;
 287                 qdev->lrg_buf_free_tail = lrg_buf_cb;
 288         }
 289
 290         if (!lrg_buf_cb->skb) {
 291                 lrg_buf_cb->skb = netdev_alloc_skb(qdev->ndev,
 292                                                    qdev->lrg_buffer_len);
 293                 if (unlikely(!lrg_buf_cb->skb)) {
 294                         printk(KERN_ERR PFX "%s: failed netdev_alloc_skb().\n",
 295                                qdev->ndev->name);
 296                         qdev->lrg_buf_skb_check++;
 297                 } else {
 298                         /*
 299                          * We save some space to copy the ethhdr from first
 300                          * buffer
 301                          */
 302                         skb_reserve(lrg_buf_cb->skb, QL_HEADER_SPACE);
 303                         map = pci_map_single(qdev->pdev,
 304                                              lrg_buf_cb->skb->data,
 305                                              qdev->lrg_buffer_len -
 306                                              QL_HEADER_SPACE,
 307                                              PCI_DMA_FROMDEVICE);
 308                         err = pci_dma_mapping_error(map);
 309                         if(err) {
 310                                 printk(KERN_ERR "%s: PCI mapping failed with error: %d\n",
 311                                        qdev->ndev->name, err);
 312                                 dev_kfree_skb(lrg_buf_cb->skb);
 313                                 lrg_buf_cb->skb = NULL;
 314
 315                                 qdev->lrg_buf_skb_check++;
 316                                 return;
 317                         }
 318
 319                         lrg_buf_cb->buf_phy_addr_low =
 320                             cpu_to_le32(LS_64BITS(map));
 321                         lrg_buf_cb->buf_phy_addr_high =
 322                             cpu_to_le32(MS_64BITS(map));
 323                         pci_unmap_addr_set(lrg_buf_cb, mapaddr, map);
 324                         pci_unmap_len_set(lrg_buf_cb, maplen,
 325                                           qdev->lrg_buffer_len -
 326                                           QL_HEADER_SPACE);
 327                 }
 328         }
 329
 330         qdev->lrg_buf_free_count++;
 331 }
 332
 333 static struct ql_rcv_buf_cb *ql_get_from_lrg_buf_free_list(struct ql3_adapter
 334                                                            *qdev)
 335 {
 336         struct ql_rcv_buf_cb *lrg_buf_cb;
 337
 338         if ((lrg_buf_cb = qdev->lrg_buf_free_head) != NULL) {
 339                 if ((qdev->lrg_buf_free_head = lrg_buf_cb->next) == NULL)
 340                         qdev->lrg_buf_free_tail = NULL;
 341                 qdev->lrg_buf_free_count--;
 342         }
 343
 344         return lrg_buf_cb;
 345 }
 346
 347 static u32 addrBits = EEPROM_NO_ADDR_BITS;
 348 static u32 dataBits = EEPROM_NO_DATA_BITS;
 349
 350 static void fm93c56a_deselect(struct ql3_adapter *qdev);
 351 static void eeprom_readword(struct ql3_adapter *qdev, u32 eepromAddr,
 352                             unsigned short *value);
 353
 354 /*
 355  * Caller holds hw_lock.
 356  */
 357 static void fm93c56a_select(struct ql3_adapter *qdev)
 358 {
 359         struct ql3xxx_port_registers __iomem *port_regs =
 360                         qdev->mem_map_registers;
 361
 362         qdev->eeprom_cmd_data = AUBURN_EEPROM_CS_1;
 363         ql_write_nvram_reg(qdev, &port_regs->CommonRegs.serialPortInterfaceReg,
 364                             ISP_NVRAM_MASK | qdev->eeprom_cmd_data);
 365         ql_write_nvram_reg(qdev, &port_regs->CommonRegs.serialPortInterfaceReg,
 366                             ((ISP_NVRAM_MASK << 16) | qdev->eeprom_cmd_data));
 367 }
 368
 369 /*
 370  * Caller holds hw_lock.
 371  */
 372 static void fm93c56a_cmd(struct ql3_adapter *qdev, u32 cmd, u32 eepromAddr)
 373 {
 374         int i;
 375         u32 mask;
 376         u32 dataBit;
 377         u32 previousBit;
 378         struct ql3xxx_port_registers __iomem *port_regs =
 379                         qdev->mem_map_registers;
 380
 381         /* Clock in a zero, then do the start bit */
 382         ql_write_nvram_reg(qdev, &port_regs->CommonRegs.serialPortInterfaceReg,
 383                             ISP_NVRAM_MASK | qdev->eeprom_cmd_data |
 384                             AUBURN_EEPROM_DO_1);
 385         ql_write_nvram_reg(qdev, &port_regs->CommonRegs.serialPortInterfaceReg,
 386                             ISP_NVRAM_MASK | qdev->
 387                             eeprom_cmd_data | AUBURN_EEPROM_DO_1 |
 388                             AUBURN_EEPROM_CLK_RISE);
 389         ql_write_nvram_reg(qdev, &port_regs->CommonRegs.serialPortInterfaceReg,
 390                             ISP_NVRAM_MASK | qdev->
 391                             eeprom_cmd_data | AUBURN_EEPROM_DO_1 |
 392                             AUBURN_EEPROM_CLK_FALL);
 393
 394         mask = 1 << (FM93C56A_CMD_BITS - 1);
 395         /* Force the previous data bit to be different */
 396         previousBit = 0xffff;
 397         for (i = 0; i < FM93C56A_CMD_BITS; i++) {
 398                 dataBit =
 399                     (cmd & mask) ? AUBURN_EEPROM_DO_1 : AUBURN_EEPROM_DO_0;
 400                 if (previousBit != dataBit) {
 401                         /*
 402                          * If the bit changed, then change the DO state to
 403                          * match
 404                          */
 405                         ql_write_nvram_reg(qdev,
 406                                             &port_regs->CommonRegs.
 407                                             serialPortInterfaceReg,
 408                                             ISP_NVRAM_MASK | qdev->
 409                                             eeprom_cmd_data | dataBit);
 410                         previousBit = dataBit;
 411                 }
 412                 ql_write_nvram_reg(qdev,
 413                                     &port_regs->CommonRegs.
 414                                     serialPortInterfaceReg,
 415                                     ISP_NVRAM_MASK | qdev->
 416                                     eeprom_cmd_data | dataBit |
 417                                     AUBURN_EEPROM_CLK_RISE);
 418                 ql_write_nvram_reg(qdev,
 419                                     &port_regs->CommonRegs.
 420                                     serialPortInterfaceReg,
 421                                     ISP_NVRAM_MASK | qdev->
 422                                     eeprom_cmd_data | dataBit |
 423                                     AUBURN_EEPROM_CLK_FALL);
 424                 cmd = cmd << 1;
 425         }
 426
 427         mask = 1 << (addrBits - 1);
 428         /* Force the previous data bit to be different */
 429         previousBit = 0xffff;
 430         for (i = 0; i < addrBits; i++) {
 431                 dataBit =
 432                     (eepromAddr & mask) ? AUBURN_EEPROM_DO_1 :
 433                     AUBURN_EEPROM_DO_0;
 434                 if (previousBit != dataBit) {
 435                         /*
 436                          * If the bit changed, then change the DO state to
 437                          * match
 438                          */
 439                         ql_write_nvram_reg(qdev,
 440                                             &port_regs->CommonRegs.
 441                                             serialPortInterfaceReg,
 442                                             ISP_NVRAM_MASK | qdev->
 443                                             eeprom_cmd_data | dataBit);
 444                         previousBit = dataBit;
 445                 }
 446                 ql_write_nvram_reg(qdev,
 447                                     &port_regs->CommonRegs.
 448                                     serialPortInterfaceReg,
 449                                     ISP_NVRAM_MASK | qdev->
 450                                     eeprom_cmd_data | dataBit |
 451                                     AUBURN_EEPROM_CLK_RISE);
 452                 ql_write_nvram_reg(qdev,
 453                                     &port_regs->CommonRegs.
 454                                     serialPortInterfaceReg,
 455                                     ISP_NVRAM_MASK | qdev->
 456                                     eeprom_cmd_data | dataBit |
 457                                     AUBURN_EEPROM_CLK_FALL);
 458                 eepromAddr = eepromAddr << 1;
 459         }
 460 }
 461
 462 /*
 463  * Caller holds hw_lock.
 464  */
 465 static void fm93c56a_deselect(struct ql3_adapter *qdev)
 466 {
 467         struct ql3xxx_port_registers __iomem *port_regs =
 468                         qdev->mem_map_registers;
 469         qdev->eeprom_cmd_data = AUBURN_EEPROM_CS_0;
 470         ql_write_nvram_reg(qdev, &port_regs->CommonRegs.serialPortInterfaceReg,
 471                             ISP_NVRAM_MASK | qdev->eeprom_cmd_data);
 472 }
 473
 474 /*
 475  * Caller holds hw_lock.
 476  */
 477 static void fm93c56a_datain(struct ql3_adapter *qdev, unsigned short *value)
 478 {
 479         int i;
 480         u32 data = 0;
 481         u32 dataBit;
 482         struct ql3xxx_port_registers __iomem *port_regs =
 483                         qdev->mem_map_registers;
 484
 485         /* Read the data bits */
 486         /* The first bit is a dummy.  Clock right over it. */
 487         for (i = 0; i < dataBits; i++) {
 488                 ql_write_nvram_reg(qdev,
 489                                     &port_regs->CommonRegs.
 490                                     serialPortInterfaceReg,
 491                                     ISP_NVRAM_MASK | qdev->eeprom_cmd_data |
 492                                     AUBURN_EEPROM_CLK_RISE);
 493                 ql_write_nvram_reg(qdev,
 494                                     &port_regs->CommonRegs.
 495                                     serialPortInterfaceReg,
 496                                     ISP_NVRAM_MASK | qdev->eeprom_cmd_data |
 497                                     AUBURN_EEPROM_CLK_FALL);
 498                 dataBit =
 499                     (ql_read_common_reg
 500                      (qdev,
 501                       &port_regs->CommonRegs.
 502                       serialPortInterfaceReg) & AUBURN_EEPROM_DI_1) ? 1 : 0;
 503                 data = (data << 1) | dataBit;
 504         }
 505         *value = (u16) data;
 506 }
 507
 508 /*
 509  * Caller holds hw_lock.
 510  */
 511 static void eeprom_readword(struct ql3_adapter *qdev,
 512                             u32 eepromAddr, unsigned short *value)
 513 {
 514         fm93c56a_select(qdev);
 515         fm93c56a_cmd(qdev, (int)FM93C56A_READ, eepromAddr);
 516         fm93c56a_datain(qdev, value);
 517         fm93c56a_deselect(qdev);
 518 }
 519
 520 static void ql_swap_mac_addr(u8 * macAddress)
 521 {
 522 #ifdef __BIG_ENDIAN
 523         u8 temp;
 524         temp = macAddress[0];
 525         macAddress[0] = macAddress[1];
 526         macAddress[1] = temp;
 527         temp = macAddress[2];
 528         macAddress[2] = macAddress[3];
 529         macAddress[3] = temp;
 530         temp = macAddress[4];
 531         macAddress[4] = macAddress[5];
 532         macAddress[5] = temp;
 533 #endif
 534 }
 535
 536 static int ql_get_nvram_params(struct ql3_adapter *qdev)
 537 {
 538         u16 *pEEPROMData;
 539         u16 checksum = 0;
 540         u32 index;
 541         unsigned long hw_flags;
 542
 543         spin_lock_irqsave(&qdev->hw_lock, hw_flags);
 544
 545         pEEPROMData = (u16 *) & qdev->nvram_data;
 546         qdev->eeprom_cmd_data = 0;
 547         if(ql_sem_spinlock(qdev, QL_NVRAM_SEM_MASK,
 548                         (QL_RESOURCE_BITS_BASE_CODE | (qdev->mac_index) *
 549                          2) << 10)) {
 550                 printk(KERN_ERR PFX"%s: Failed ql_sem_spinlock().\n",
 551                         __func__);
 552                 spin_unlock_irqrestore(&qdev->hw_lock, hw_flags);
 553                 return -1;
 554         }
 555
 556         for (index = 0; index < EEPROM_SIZE; index++) {
 557                 eeprom_readword(qdev, index, pEEPROMData);
 558                 checksum += *pEEPROMData;
 559                 pEEPROMData++;
 560         }
 561         ql_sem_unlock(qdev, QL_NVRAM_SEM_MASK);
 562
 563         if (checksum != 0) {
 564                 printk(KERN_ERR PFX "%s: checksum should be zero, is %x!!\n",
 565                        qdev->ndev->name, checksum);
 566                 spin_unlock_irqrestore(&qdev->hw_lock, hw_flags);
 567                 return -1;
 568         }
 569
 570         /*
 571          * We have a problem with endianness for the MAC addresses
 572          * and the two 8-bit values version, and numPorts.  We
 573          * have to swap them on big endian systems.
 574          */
 575         ql_swap_mac_addr(qdev->nvram_data.funcCfg_fn0.macAddress);
 576         ql_swap_mac_addr(qdev->nvram_data.funcCfg_fn1.macAddress);
 577         ql_swap_mac_addr(qdev->nvram_data.funcCfg_fn2.macAddress);
 578         ql_swap_mac_addr(qdev->nvram_data.funcCfg_fn3.macAddress);
 579         pEEPROMData = (u16 *) & qdev->nvram_data.version;
 580         *pEEPROMData = le16_to_cpu(*pEEPROMData);
 581
 582         spin_unlock_irqrestore(&qdev->hw_lock, hw_flags);
 583         return checksum;
 584 }
 585
 586 static const u32 PHYAddr[2] = {
 587         PORT0_PHY_ADDRESS, PORT1_PHY_ADDRESS
 588 };
 589
 590 static int ql_wait_for_mii_ready(struct ql3_adapter *qdev)
 591 {
 592         struct ql3xxx_port_registers __iomem *port_regs =
 593                         qdev->mem_map_registers;
 594         u32 temp;
 595         int count = 1000;
 596
 597         while (count) {
 598                 temp = ql_read_page0_reg(qdev, &port_regs->macMIIStatusReg);
 599                 if (!(temp & MAC_MII_STATUS_BSY))
 600                         return 0;
 601                 udelay(10);
 602                 count--;
 603         }
 604         return -1;
 605 }
 606
 607 static void ql_mii_enable_scan_mode(struct ql3_adapter *qdev)
 608 {
 609         struct ql3xxx_port_registers __iomem *port_regs =
 610                         qdev->mem_map_registers;
 611         u32 scanControl;
 612
 613         if (qdev->numPorts > 1) {
 614                 /* Auto scan will cycle through multiple ports */
 615                 scanControl = MAC_MII_CONTROL_AS | MAC_MII_CONTROL_SC;
 616         } else {
 617                 scanControl = MAC_MII_CONTROL_SC;
 618         }
 619
 620         /*
 621          * Scan register 1 of PHY/PETBI,
 622          * Set up to scan both devices
 623          * The autoscan starts from the first register, completes
 624          * the last one before rolling over to the first
 625          */
 626         ql_write_page0_reg(qdev, &port_regs->macMIIMgmtAddrReg,
 627                            PHYAddr[0] | MII_SCAN_REGISTER);
 628
 629         ql_write_page0_reg(qdev, &port_regs->macMIIMgmtControlReg,
 630                            (scanControl) |
 631                            ((MAC_MII_CONTROL_SC | MAC_MII_CONTROL_AS) << 16));
 632 }
 633
 634 static u8 ql_mii_disable_scan_mode(struct ql3_adapter *qdev)
 635 {
 636         u8 ret;
 637         struct ql3xxx_port_registers __iomem *port_regs =
 638                                         qdev->mem_map_registers;
 639
 640         /* See if scan mode is enabled before we turn it off */
 641         if (ql_read_page0_reg(qdev, &port_regs->macMIIMgmtControlReg) &
 642             (MAC_MII_CONTROL_AS | MAC_MII_CONTROL_SC)) {
 643                 /* Scan is enabled */
 644                 ret = 1;
 645         } else {
 646                 /* Scan is disabled */
 647                 ret = 0;
 648         }
 649
 650         /*
 651          * When disabling scan mode you must first change the MII register
 652          * address
 653          */
 654         ql_write_page0_reg(qdev, &port_regs->macMIIMgmtAddrReg,
 655                            PHYAddr[0] | MII_SCAN_REGISTER);
 656
 657         ql_write_page0_reg(qdev, &port_regs->macMIIMgmtControlReg,
 658                            ((MAC_MII_CONTROL_SC | MAC_MII_CONTROL_AS |
 659                              MAC_MII_CONTROL_RC) << 16));
 660
 661         return ret;
 662 }
 663
 664 static int ql_mii_write_reg_ex(struct ql3_adapter *qdev,
 665                                u16 regAddr, u16 value, u32 mac_index)
 666 {
 667         struct ql3xxx_port_registers __iomem *port_regs =
 668                         qdev->mem_map_registers;
 669         u8 scanWasEnabled;
 670
 671         scanWasEnabled = ql_mii_disable_scan_mode(qdev);
 672
 673         if (ql_wait_for_mii_ready(qdev)) {
 674                 if (netif_msg_link(qdev))
 675                         printk(KERN_WARNING PFX
 676                                "%s Timed out waiting for management port to "
 677                                "get free before issuing command.\n",
 678                                qdev->ndev->name);
 679                 return -1;
 680         }
 681
 682         ql_write_page0_reg(qdev, &port_regs->macMIIMgmtAddrReg,
 683                            PHYAddr[mac_index] | regAddr);
 684
 685         ql_write_page0_reg(qdev, &port_regs->macMIIMgmtDataReg, value);
 686
 687         /* Wait for write to complete 9/10/04 SJP */
 688         if (ql_wait_for_mii_ready(qdev)) {
 689                 if (netif_msg_link(qdev))
 690                         printk(KERN_WARNING PFX
 691                                "%s: Timed out waiting for management port to"
 692                                "get free before issuing command.\n",
 693                                qdev->ndev->name);
 694                 return -1;
 695         }
 696
 697         if (scanWasEnabled)
 698                 ql_mii_enable_scan_mode(qdev);
 699
 700         return 0;
 701 }
 702
 703 static int ql_mii_read_reg_ex(struct ql3_adapter *qdev, u16 regAddr,
 704                               u16 * value, u32 mac_index)
 705 {
 706         struct ql3xxx_port_registers __iomem *port_regs =
 707                         qdev->mem_map_registers;
 708         u8 scanWasEnabled;
 709         u32 temp;
 710
 711         scanWasEnabled = ql_mii_disable_scan_mode(qdev);
 712
 713         if (ql_wait_for_mii_ready(qdev)) {
 714                 if (netif_msg_link(qdev))
 715                         printk(KERN_WARNING PFX
 716                                "%s: Timed out waiting for management port to "
 717                                "get free before issuing command.\n",
 718                                qdev->ndev->name);
 719                 return -1;
 720         }
 721
 722         ql_write_page0_reg(qdev, &port_regs->macMIIMgmtAddrReg,
 723                            PHYAddr[mac_index] | regAddr);
 724
 725         ql_write_page0_reg(qdev, &port_regs->macMIIMgmtControlReg,
 726                            (MAC_MII_CONTROL_RC << 16));
 727
 728         ql_write_page0_reg(qdev, &port_regs->macMIIMgmtControlReg,
 729                            (MAC_MII_CONTROL_RC << 16) | MAC_MII_CONTROL_RC);
 730
 731         /* Wait for the read to complete */
 732         if (ql_wait_for_mii_ready(qdev)) {
 733                 if (netif_msg_link(qdev))
 734                         printk(KERN_WARNING PFX
 735                                "%s: Timed out waiting for management port to "
 736                                "get free after issuing command.\n",
 737                                qdev->ndev->name);
 738                 return -1;
 739         }
 740
 741         temp = ql_read_page0_reg(qdev, &port_regs->macMIIMgmtDataReg);
 742         *value = (u16) temp;
 743
 744         if (scanWasEnabled)
 745                 ql_mii_enable_scan_mode(qdev);
 746
 747         return 0;
 748 }
 749
 750 static int ql_mii_write_reg(struct ql3_adapter *qdev, u16 regAddr, u16 value)
 751 {
 752         struct ql3xxx_port_registers __iomem *port_regs =
 753                         qdev->mem_map_registers;
 754
 755         ql_mii_disable_scan_mode(qdev);
 756
 757         if (ql_wait_for_mii_ready(qdev)) {
 758                 if (netif_msg_link(qdev))
 759                         printk(KERN_WARNING PFX
 760                                "%s: Timed out waiting for management port to "
 761                                "get free before issuing command.\n",
 762                                qdev->ndev->name);
 763                 return -1;
 764         }
 765
 766         ql_write_page0_reg(qdev, &port_regs->macMIIMgmtAddrReg,
 767                            qdev->PHYAddr | regAddr);
 768
 769         ql_write_page0_reg(qdev, &port_regs->macMIIMgmtDataReg, value);
 770
 771         /* Wait for write to complete. */
 772         if (ql_wait_for_mii_ready(qdev)) {
 773                 if (netif_msg_link(qdev))
 774                         printk(KERN_WARNING PFX
 775                                "%s: Timed out waiting for management port to "
 776                                "get free before issuing command.\n",
 777                                qdev->ndev->name);
 778                 return -1;
 779         }
 780
 781         ql_mii_enable_scan_mode(qdev);
 782
 783         return 0;
 784 }
 785
 786 static int ql_mii_read_reg(struct ql3_adapter *qdev, u16 regAddr, u16 *value)
 787 {
 788         u32 temp;
 789         struct ql3xxx_port_registers __iomem *port_regs =
 790                         qdev->mem_map_registers;
 791
 792         ql_mii_disable_scan_mode(qdev);
 793
 794         if (ql_wait_for_mii_ready(qdev)) {
 795                 if (netif_msg_link(qdev))
 796                         printk(KERN_WARNING PFX
 797                                "%s: Timed out waiting for management port to "
 798                                "get free before issuing command.\n",
 799                                qdev->ndev->name);
 800                 return -1;
 801         }
 802
 803         ql_write_page0_reg(qdev, &port_regs->macMIIMgmtAddrReg,
 804                            qdev->PHYAddr | regAddr);
 805
 806         ql_write_page0_reg(qdev, &port_regs->macMIIMgmtControlReg,
 807                            (MAC_MII_CONTROL_RC << 16));
 808
 809         ql_write_page0_reg(qdev, &port_regs->macMIIMgmtControlReg,
 810                            (MAC_MII_CONTROL_RC << 16) | MAC_MII_CONTROL_RC);
 811
 812         /* Wait for the read to complete */
 813         if (ql_wait_for_mii_ready(qdev)) {
 814                 if (netif_msg_link(qdev))
 815                         printk(KERN_WARNING PFX
 816                                "%s: Timed out waiting for management port to "
 817                                "get free before issuing command.\n",
 818                                qdev->ndev->name);
 819                 return -1;
 820         }
 821
 822         temp = ql_read_page0_reg(qdev, &port_regs->macMIIMgmtDataReg);
 823         *value = (u16) temp;
 824
 825         ql_mii_enable_scan_mode(qdev);
 826
 827         return 0;
 828 }
 829
 830 static void ql_petbi_reset(struct ql3_adapter *qdev)
 831 {
 832         ql_mii_write_reg(qdev, PETBI_CONTROL_REG, PETBI_CTRL_SOFT_RESET);
 833 }
 834
 835 static void ql_petbi_start_neg(struct ql3_adapter *qdev)
 836 {
 837         u16 reg;
 838
 839         /* Enable Auto-negotiation sense */
 840         ql_mii_read_reg(qdev, PETBI_TBI_CTRL, &reg);
 841         reg |= PETBI_TBI_AUTO_SENSE;
 842         ql_mii_write_reg(qdev, PETBI_TBI_CTRL, reg);
 843
 844         ql_mii_write_reg(qdev, PETBI_NEG_ADVER,
 845                          PETBI_NEG_PAUSE | PETBI_NEG_DUPLEX);
 846
 847         ql_mii_write_reg(qdev, PETBI_CONTROL_REG,
 848                          PETBI_CTRL_AUTO_NEG | PETBI_CTRL_RESTART_NEG |
 849                          PETBI_CTRL_FULL_DUPLEX | PETBI_CTRL_SPEED_1000);
 850
 851 }
 852
 853 static void ql_petbi_reset_ex(struct ql3_adapter *qdev, u32 mac_index)
 854 {
 855         ql_mii_write_reg_ex(qdev, PETBI_CONTROL_REG, PETBI_CTRL_SOFT_RESET,
 856                             mac_index);
 857 }
 858
 859 static void ql_petbi_start_neg_ex(struct ql3_adapter *qdev, u32 mac_index)
 860 {
 861         u16 reg;
 862
 863         /* Enable Auto-negotiation sense */
 864         ql_mii_read_reg_ex(qdev, PETBI_TBI_CTRL, &reg, mac_index);
 865         reg |= PETBI_TBI_AUTO_SENSE;
 866         ql_mii_write_reg_ex(qdev, PETBI_TBI_CTRL, reg, mac_index);
 867
 868         ql_mii_write_reg_ex(qdev, PETBI_NEG_ADVER,
 869                             PETBI_NEG_PAUSE | PETBI_NEG_DUPLEX, mac_index);
 870
 871         ql_mii_write_reg_ex(qdev, PETBI_CONTROL_REG,
 872                             PETBI_CTRL_AUTO_NEG | PETBI_CTRL_RESTART_NEG |
 873                             PETBI_CTRL_FULL_DUPLEX | PETBI_CTRL_SPEED_1000,
 874                             mac_index);
 875 }
 876
 877 static void ql_petbi_init(struct ql3_adapter *qdev)
 878 {
 879         ql_petbi_reset(qdev);
 880         ql_petbi_start_neg(qdev);
 881 }
 882
 883 static void ql_petbi_init_ex(struct ql3_adapter *qdev, u32 mac_index)
 884 {
 885         ql_petbi_reset_ex(qdev, mac_index);
 886         ql_petbi_start_neg_ex(qdev, mac_index);
 887 }
 888
 889 static int ql_is_petbi_neg_pause(struct ql3_adapter *qdev)
 890 {
 891         u16 reg;
 892
 893         if (ql_mii_read_reg(qdev, PETBI_NEG_PARTNER, &reg) < 0)
 894                 return 0;
 895
 896         return (reg & PETBI_NEG_PAUSE_MASK) == PETBI_NEG_PAUSE;
 897 }
 898
 899 static int ql_phy_get_speed(struct ql3_adapter *qdev)
 900 {
 901         u16 reg;
 902
 903         if (ql_mii_read_reg(qdev, AUX_CONTROL_STATUS, &reg) < 0)
 904                 return 0;
 905
 906         reg = (((reg & 0x18) >> 3) & 3);
 907
 908         if (reg == 2)
 909                 return SPEED_1000;
 910         else if (reg == 1)
 911                 return SPEED_100;
 912         else if (reg == 0)
 913                 return SPEED_10;
 914         else
 915                 return -1;
 916 }
 917
 918 static int ql_is_full_dup(struct ql3_adapter *qdev)
 919 {
 920         u16 reg;
 921
 922         if (ql_mii_read_reg(qdev, AUX_CONTROL_STATUS, &reg) < 0)
 923                 return 0;
 924
 925         return (reg & PHY_AUX_DUPLEX_STAT) != 0;
 926 }
 927
 928 static int ql_is_phy_neg_pause(struct ql3_adapter *qdev)
 929 {
 930         u16 reg;
 931
 932         if (ql_mii_read_reg(qdev, PHY_NEG_PARTNER, &reg) < 0)
 933                 return 0;
 934
 935         return (reg & PHY_NEG_PAUSE) != 0;
 936 }
 937
 938 /*
 939  * Caller holds hw_lock.
 940  */
 941 static void ql_mac_enable(struct ql3_adapter *qdev, u32 enable)
 942 {
 943         struct ql3xxx_port_registers __iomem *port_regs =
 944                         qdev->mem_map_registers;
 945         u32 value;
 946
 947         if (enable)
 948                 value = (MAC_CONFIG_REG_PE | (MAC_CONFIG_REG_PE << 16));
 949         else
 950                 value = (MAC_CONFIG_REG_PE << 16);
 951
 952         if (qdev->mac_index)
 953                 ql_write_page0_reg(qdev, &port_regs->mac1ConfigReg, value);
 954         else
 955                 ql_write_page0_reg(qdev, &port_regs->mac0ConfigReg, value);
 956 }
 957
 958 /*
 959  * Caller holds hw_lock.
 960  */
 961 static void ql_mac_cfg_soft_reset(struct ql3_adapter *qdev, u32 enable)
 962 {
 963         struct ql3xxx_port_registers __iomem *port_regs =
 964                         qdev->mem_map_registers;
 965         u32 value;
 966
 967         if (enable)
 968                 value = (MAC_CONFIG_REG_SR | (MAC_CONFIG_REG_SR << 16));
 969         else
 970                 value = (MAC_CONFIG_REG_SR << 16);
 971
 972         if (qdev->mac_index)
 973                 ql_write_page0_reg(qdev, &port_regs->mac1ConfigReg, value);
 974         else
 975                 ql_write_page0_reg(qdev, &port_regs->mac0ConfigReg, value);
 976 }
 977
 978 /*
 979  * Caller holds hw_lock.
 980  */
 981 static void ql_mac_cfg_gig(struct ql3_adapter *qdev, u32 enable)
 982 {
 983         struct ql3xxx_port_registers __iomem *port_regs =
 984                         qdev->mem_map_registers;
 985         u32 value;
 986
 987         if (enable)
 988                 value = (MAC_CONFIG_REG_GM | (MAC_CONFIG_REG_GM << 16));
 989         else
 990                 value = (MAC_CONFIG_REG_GM << 16);
 991
 992         if (qdev->mac_index)
 993                 ql_write_page0_reg(qdev, &port_regs->mac1ConfigReg, value);
 994         else
 995                 ql_write_page0_reg(qdev, &port_regs->mac0ConfigReg, value);
 996 }
 997
 998 /*
 999  * Caller holds hw_lock.
1000  */
1001 static void ql_mac_cfg_full_dup(struct ql3_adapter *qdev, u32 enable)
1002 {
1003         struct ql3xxx_port_registers __iomem *port_regs =
1004                         qdev->mem_map_registers;
1005         u32 value;
1006
1007         if (enable)
1008                 value = (MAC_CONFIG_REG_FD | (MAC_CONFIG_REG_FD << 16));
1009         else
1010                 value = (MAC_CONFIG_REG_FD << 16);
1011
1012         if (qdev->mac_index)
1013                 ql_write_page0_reg(qdev, &port_regs->mac1ConfigReg, value);
1014         else
1015                 ql_write_page0_reg(qdev, &port_regs->mac0ConfigReg, value);
1016 }
1017
1018 /*
1019  * Caller holds hw_lock.
1020  */
1021 static void ql_mac_cfg_pause(struct ql3_adapter *qdev, u32 enable)
1022 {
1023         struct ql3xxx_port_registers __iomem *port_regs =
1024                         qdev->mem_map_registers;
1025         u32 value;
1026
1027         if (enable)
1028                 value =
1029                     ((MAC_CONFIG_REG_TF | MAC_CONFIG_REG_RF) |
1030                      ((MAC_CONFIG_REG_TF | MAC_CONFIG_REG_RF) << 16));
1031         else
1032                 value = ((MAC_CONFIG_REG_TF | MAC_CONFIG_REG_RF) << 16);
1033
1034         if (qdev->mac_index)
1035                 ql_write_page0_reg(qdev, &port_regs->mac1ConfigReg, value);
1036         else
1037                 ql_write_page0_reg(qdev, &port_regs->mac0ConfigReg, value);
1038 }
1039
1040 /*
1041  * Caller holds hw_lock.
1042  */
1043 static int ql_is_fiber(struct ql3_adapter *qdev)
1044 {
1045         struct ql3xxx_port_registers __iomem *port_regs =
1046                         qdev->mem_map_registers;
1047         u32 bitToCheck = 0;
1048         u32 temp;
1049
1050         switch (qdev->mac_index) {
1051         case 0:
1052                 bitToCheck = PORT_STATUS_SM0;
1053                 break;
1054         case 1:
1055                 bitToCheck = PORT_STATUS_SM1;
1056                 break;
1057         }
1058
1059         temp = ql_read_page0_reg(qdev, &port_regs->portStatus);
1060         return (temp & bitToCheck) != 0;
1061 }
1062
1063 static int ql_is_auto_cfg(struct ql3_adapter *qdev)
1064 {
1065         u16 reg;
1066         ql_mii_read_reg(qdev, 0x00, &reg);
1067         return (reg & 0x1000) != 0;
1068 }
1069
1070 /*
1071  * Caller holds hw_lock.
1072  */
1073 static int ql_is_auto_neg_complete(struct ql3_adapter *qdev)
1074 {
1075         struct ql3xxx_port_registers __iomem *port_regs =
1076                         qdev->mem_map_registers;
1077         u32 bitToCheck = 0;
1078         u32 temp;
1079
1080         switch (qdev->mac_index) {
1081         case 0:
1082                 bitToCheck = PORT_STATUS_AC0;
1083                 break;
1084         case 1:
1085                 bitToCheck = PORT_STATUS_AC1;
1086                 break;
1087         }
1088
1089         temp = ql_read_page0_reg(qdev, &port_regs->portStatus);
1090         if (temp & bitToCheck) {
1091                 if (netif_msg_link(qdev))
1092                         printk(KERN_INFO PFX
1093                                "%s: Auto-Negotiate complete.\n",
1094                                qdev->ndev->name);
1095                 return 1;
1096         } else {
1097                 if (netif_msg_link(qdev))
1098                         printk(KERN_WARNING PFX
1099                                "%s: Auto-Negotiate incomplete.\n",
1100                                qdev->ndev->name);
1101                 return 0;
1102         }
1103 }
1104
1105 /*
1106  *  ql_is_neg_pause() returns 1 if pause was negotiated to be on
1107  */
1108 static int ql_is_neg_pause(struct ql3_adapter *qdev)
1109 {
1110         if (ql_is_fiber(qdev))
1111                 return ql_is_petbi_neg_pause(qdev);
1112         else
1113                 return ql_is_phy_neg_pause(qdev);
1114 }
1115
1116 static int ql_auto_neg_error(struct ql3_adapter *qdev)
1117 {
1118         struct ql3xxx_port_registers __iomem *port_regs =
1119                         qdev->mem_map_registers;
1120         u32 bitToCheck = 0;
1121         u32 temp;
1122
1123         switch (qdev->mac_index) {
1124         case 0:
1125                 bitToCheck = PORT_STATUS_AE0;
1126                 break;
1127         case 1:
1128                 bitToCheck = PORT_STATUS_AE1;
1129                 break;
1130         }
1131         temp = ql_read_page0_reg(qdev, &port_regs->portStatus);
1132         return (temp & bitToCheck) != 0;
1133 }
1134
1135 static u32 ql_get_link_speed(struct ql3_adapter *qdev)
1136 {
1137         if (ql_is_fiber(qdev))
1138                 return SPEED_1000;
1139         else
1140                 return ql_phy_get_speed(qdev);
1141 }
1142
1143 static int ql_is_link_full_dup(struct ql3_adapter *qdev)
1144 {
1145         if (ql_is_fiber(qdev))
1146                 return 1;
1147         else
1148                 return ql_is_full_dup(qdev);
1149 }
1150
1151 /*
1152  * Caller holds hw_lock.
1153  */
1154 static int ql_link_down_detect(struct ql3_adapter *qdev)
1155 {
1156         struct ql3xxx_port_registers __iomem *port_regs =
1157                         qdev->mem_map_registers;
1158         u32 bitToCheck = 0;
1159         u32 temp;
1160
1161         switch (qdev->mac_index) {
1162         case 0:
1163                 bitToCheck = ISP_CONTROL_LINK_DN_0;
1164                 break;
1165         case 1:
1166                 bitToCheck = ISP_CONTROL_LINK_DN_1;
1167                 break;
1168         }
1169
1170         temp =
1171             ql_read_common_reg(qdev, &port_regs->CommonRegs.ispControlStatus);
1172         return (temp & bitToCheck) != 0;
1173 }
1174
1175 /*
1176  * Caller holds hw_lock.
1177  */
1178 static int ql_link_down_detect_clear(struct ql3_adapter *qdev)
1179 {
1180         struct ql3xxx_port_registers __iomem *port_regs =
1181                         qdev->mem_map_registers;
1182
1183         switch (qdev->mac_index) {
1184         case 0:
1185                 ql_write_common_reg(qdev,
1186                                     &port_regs->CommonRegs.ispControlStatus,
1187                                     (ISP_CONTROL_LINK_DN_0) |
1188                                     (ISP_CONTROL_LINK_DN_0 << 16));
1189                 break;
1190
1191         case 1:
1192                 ql_write_common_reg(qdev,
1193                                     &port_regs->CommonRegs.ispControlStatus,
1194                                     (ISP_CONTROL_LINK_DN_1) |
1195                                     (ISP_CONTROL_LINK_DN_1 << 16));
1196                 break;
1197
1198         default:
1199                 return 1;
1200         }
1201
1202         return 0;
1203 }
1204
1205 /*
1206  * Caller holds hw_lock.
1207  */
1208 static int ql_this_adapter_controls_port(struct ql3_adapter *qdev,
1209                                          u32 mac_index)
1210 {
1211         struct ql3xxx_port_registers __iomem *port_regs =
1212                         qdev->mem_map_registers;
1213         u32 bitToCheck = 0;
1214         u32 temp;
1215
1216         switch (mac_index) {
1217         case 0:
1218                 bitToCheck = PORT_STATUS_F1_ENABLED;
1219                 break;
1220         case 1:
1221                 bitToCheck = PORT_STATUS_F3_ENABLED;
1222                 break;
1223         default:
1224                 break;
1225         }
1226
1227         temp = ql_read_page0_reg(qdev, &port_regs->portStatus);
1228         if (temp & bitToCheck) {
1229                 if (netif_msg_link(qdev))
1230                         printk(KERN_DEBUG PFX
1231                                "%s: is not link master.\n", qdev->ndev->name);
1232                 return 0;
1233         } else {
1234                 if (netif_msg_link(qdev))
1235                         printk(KERN_DEBUG PFX
1236                                "%s: is link master.\n", qdev->ndev->name);
1237                 return 1;
1238         }
1239 }
1240
1241 static void ql_phy_reset_ex(struct ql3_adapter *qdev, u32 mac_index)
1242 {
1243         ql_mii_write_reg_ex(qdev, CONTROL_REG, PHY_CTRL_SOFT_RESET, mac_index);
1244 }
1245
1246 static void ql_phy_start_neg_ex(struct ql3_adapter *qdev, u32 mac_index)
1247 {
1248         u16 reg;
1249
1250         ql_mii_write_reg_ex(qdev, PHY_NEG_ADVER,
1251                             PHY_NEG_PAUSE | PHY_NEG_ADV_SPEED | 1, mac_index);
1252
1253         ql_mii_read_reg_ex(qdev, CONTROL_REG, &reg, mac_index);
1254         ql_mii_write_reg_ex(qdev, CONTROL_REG, reg | PHY_CTRL_RESTART_NEG,
1255                             mac_index);
1256 }
1257
1258 static void ql_phy_init_ex(struct ql3_adapter *qdev, u32 mac_index)
1259 {
1260         ql_phy_reset_ex(qdev, mac_index);
1261         ql_phy_start_neg_ex(qdev, mac_index);
1262 }
1263
1264 /*
1265  * Caller holds hw_lock.
1266  */
1267 static u32 ql_get_link_state(struct ql3_adapter *qdev)
1268 {
1269         struct ql3xxx_port_registers __iomem *port_regs =
1270                         qdev->mem_map_registers;
1271         u32 bitToCheck = 0;
1272         u32 temp, linkState;
1273
1274         switch (qdev->mac_index) {
1275         case 0:
1276                 bitToCheck = PORT_STATUS_UP0;
1277                 break;
1278         case 1:
1279                 bitToCheck = PORT_STATUS_UP1;
1280                 break;
1281         }
1282         temp = ql_read_page0_reg(qdev, &port_regs->portStatus);
1283         if (temp & bitToCheck) {
1284                 linkState = LS_UP;
1285         } else {
1286                 linkState = LS_DOWN;
1287                 if (netif_msg_link(qdev))
1288                         printk(KERN_WARNING PFX
1289                                "%s: Link is down.\n", qdev->ndev->name);
1290         }
1291         return linkState;
1292 }
1293
1294 static int ql_port_start(struct ql3_adapter *qdev)
1295 {
1296         if(ql_sem_spinlock(qdev, QL_PHY_GIO_SEM_MASK,
1297                 (QL_RESOURCE_BITS_BASE_CODE | (qdev->mac_index) *
1298                          2) << 7))
1299                 return -1;
1300
1301         if (ql_is_fiber(qdev)) {
1302                 ql_petbi_init(qdev);
1303         } else {
1304                 /* Copper port */
1305                 ql_phy_init_ex(qdev, qdev->mac_index);
1306         }
1307
1308         ql_sem_unlock(qdev, QL_PHY_GIO_SEM_MASK);
1309         return 0;
1310 }
1311
1312 static int ql_finish_auto_neg(struct ql3_adapter *qdev)
1313 {
1314
1315         if(ql_sem_spinlock(qdev, QL_PHY_GIO_SEM_MASK,
1316                 (QL_RESOURCE_BITS_BASE_CODE | (qdev->mac_index) *
1317                          2) << 7))
1318                 return -1;
1319
1320         if (!ql_auto_neg_error(qdev)) {
1321                 if (test_bit(QL_LINK_MASTER,&qdev->flags)) {
1322                         /* configure the MAC */
1323                         if (netif_msg_link(qdev))
1324                                 printk(KERN_DEBUG PFX
1325                                        "%s: Configuring link.\n",
1326                                        qdev->ndev->
1327                                        name);
1328                         ql_mac_cfg_soft_reset(qdev, 1);
1329                         ql_mac_cfg_gig(qdev,
1330                                        (ql_get_link_speed
1331                                         (qdev) ==
1332                                         SPEED_1000));
1333                         ql_mac_cfg_full_dup(qdev,
1334                                             ql_is_link_full_dup
1335                                             (qdev));
1336                         ql_mac_cfg_pause(qdev,
1337                                          ql_is_neg_pause
1338                                          (qdev));
1339                         ql_mac_cfg_soft_reset(qdev, 0);
1340
1341                         /* enable the MAC */
1342                         if (netif_msg_link(qdev))
1343                                 printk(KERN_DEBUG PFX
1344                                        "%s: Enabling mac.\n",
1345                                        qdev->ndev->
1346                                                name);
1347                         ql_mac_enable(qdev, 1);
1348                 }
1349
1350                 if (netif_msg_link(qdev))
1351                         printk(KERN_DEBUG PFX
1352                                "%s: Change port_link_state LS_DOWN to LS_UP.\n",
1353                                qdev->ndev->name);
1354                 qdev->port_link_state = LS_UP;
1355                 netif_start_queue(qdev->ndev);
1356                 netif_carrier_on(qdev->ndev);
1357                 if (netif_msg_link(qdev))
1358                         printk(KERN_INFO PFX
1359                                "%s: Link is up at %d Mbps, %s duplex.\n",
1360                                qdev->ndev->name,
1361                                ql_get_link_speed(qdev),
1362                                ql_is_link_full_dup(qdev)
1363                                ? "full" : "half");
1364
1365         } else {        /* Remote error detected */
1366
1367                 if (test_bit(QL_LINK_MASTER,&qdev->flags)) {
1368                         if (netif_msg_link(qdev))
1369                                 printk(KERN_DEBUG PFX
1370                                        "%s: Remote error detected. "
1371                                        "Calling ql_port_start().\n",
1372                                        qdev->ndev->
1373                                        name);
1374                         /*
1375                          * ql_port_start() is shared code and needs
1376                          * to lock the PHY on it's own.
1377                          */
1378                         ql_sem_unlock(qdev, QL_PHY_GIO_SEM_MASK);
1379                         if(ql_port_start(qdev)) {/* Restart port */
1380                                 return -1;
1381                         } else
1382                                 return 0;
1383                 }
1384         }
1385         ql_sem_unlock(qdev, QL_PHY_GIO_SEM_MASK);
1386         return 0;
1387 }
1388
1389 static void ql_link_state_machine(struct ql3_adapter *qdev)
1390 {
1391         u32 curr_link_state;
1392         unsigned long hw_flags;
1393
1394         spin_lock_irqsave(&qdev->hw_lock, hw_flags);
1395
1396         curr_link_state = ql_get_link_state(qdev);
1397
1398         if (test_bit(QL_RESET_ACTIVE,&qdev->flags)) {
1399                 if (netif_msg_link(qdev))
1400                         printk(KERN_INFO PFX
1401                                "%s: Reset in progress, skip processing link "
1402                                "state.\n", qdev->ndev->name);
1403
1404                 spin_unlock_irqrestore(&qdev->hw_lock, hw_flags);
1405                 return;
1406         }
1407
1408         switch (qdev->port_link_state) {
1409         default:
1410                 if (test_bit(QL_LINK_MASTER,&qdev->flags)) {
1411                         ql_port_start(qdev);
1412                 }
1413                 qdev->port_link_state = LS_DOWN;
1414                 /* Fall Through */
1415
1416         case LS_DOWN:
1417                 if (netif_msg_link(qdev))
1418                         printk(KERN_DEBUG PFX
1419                                "%s: port_link_state = LS_DOWN.\n",
1420                                qdev->ndev->name);
1421                 if (curr_link_state == LS_UP) {
1422                         if (netif_msg_link(qdev))
1423                                 printk(KERN_DEBUG PFX
1424                                        "%s: curr_link_state = LS_UP.\n",
1425                                        qdev->ndev->name);
1426                         if (ql_is_auto_neg_complete(qdev))
1427                                 ql_finish_auto_neg(qdev);
1428
1429                         if (qdev->port_link_state == LS_UP)
1430                                 ql_link_down_detect_clear(qdev);
1431
1432                 }
1433                 break;
1434
1435         case LS_UP:
1436                 /*
1437                  * See if the link is currently down or went down and came
1438                  * back up
1439                  */
1440                 if ((curr_link_state == LS_DOWN) || ql_link_down_detect(qdev)) {
1441                         if (netif_msg_link(qdev))
1442                                 printk(KERN_INFO PFX "%s: Link is down.\n",
1443                                        qdev->ndev->name);
1444                         qdev->port_link_state = LS_DOWN;
1445                 }
1446                 break;
1447         }
1448         spin_unlock_irqrestore(&qdev->hw_lock, hw_flags);
1449 }
1450
1451 /*
1452  * Caller must take hw_lock and QL_PHY_GIO_SEM.
1453  */
1454 static void ql_get_phy_owner(struct ql3_adapter *qdev)
1455 {
1456         if (ql_this_adapter_controls_port(qdev, qdev->mac_index))
1457                 set_bit(QL_LINK_MASTER,&qdev->flags);
1458         else
1459                 clear_bit(QL_LINK_MASTER,&qdev->flags);
1460 }
1461
1462 /*
1463  * Caller must take hw_lock and QL_PHY_GIO_SEM.
1464  */
1465 static void ql_init_scan_mode(struct ql3_adapter *qdev)
1466 {
1467         ql_mii_enable_scan_mode(qdev);
1468
1469         if (test_bit(QL_LINK_OPTICAL,&qdev->flags)) {
1470                 if (ql_this_adapter_controls_port(qdev, qdev->mac_index))
1471                         ql_petbi_init_ex(qdev, qdev->mac_index);
1472         } else {
1473                 if (ql_this_adapter_controls_port(qdev, qdev->mac_index))
1474                         ql_phy_init_ex(qdev, qdev->mac_index);
1475         }
1476 }
1477
1478 /*
1479  * MII_Setup needs to be called before taking the PHY out of reset so that the
1480  * management interface clock speed can be set properly.  It would be better if
1481  * we had a way to disable MDC until after the PHY is out of reset, but we
1482  * don't have that capability.
1483  */
1484 static int ql_mii_setup(struct ql3_adapter *qdev)
1485 {
1486         u32 reg;
1487         struct ql3xxx_port_registers __iomem *port_regs =
1488                         qdev->mem_map_registers;
1489
1490         if(ql_sem_spinlock(qdev, QL_PHY_GIO_SEM_MASK,
1491                         (QL_RESOURCE_BITS_BASE_CODE | (qdev->mac_index) *
1492                          2) << 7))
1493                 return -1;
1494
1495         if (qdev->device_id == QL3032_DEVICE_ID)
1496                 ql_write_page0_reg(qdev,
1497                         &port_regs->macMIIMgmtControlReg, 0x0f00000);
1498
1499         /* Divide 125MHz clock by 28 to meet PHY timing requirements */
1500         reg = MAC_MII_CONTROL_CLK_SEL_DIV28;
1501
1502         ql_write_page0_reg(qdev, &port_regs->macMIIMgmtControlReg,
1503                            reg | ((MAC_MII_CONTROL_CLK_SEL_MASK) << 16));
1504
1505         ql_sem_unlock(qdev, QL_PHY_GIO_SEM_MASK);
1506         return 0;
1507 }
1508
1509 static u32 ql_supported_modes(struct ql3_adapter *qdev)
1510 {
1511         u32 supported;
1512
1513         if (test_bit(QL_LINK_OPTICAL,&qdev->flags)) {
1514                 supported = SUPPORTED_1000baseT_Full | SUPPORTED_FIBRE
1515                     | SUPPORTED_Autoneg;
1516         } else {
1517                 supported = SUPPORTED_10baseT_Half
1518                     | SUPPORTED_10baseT_Full
1519                     | SUPPORTED_100baseT_Half
1520                     | SUPPORTED_100baseT_Full
1521                     | SUPPORTED_1000baseT_Half
1522                     | SUPPORTED_1000baseT_Full
1523                     | SUPPORTED_Autoneg | SUPPORTED_TP;
1524         }
1525
1526         return supported;
1527 }
1528
1529 static int ql_get_auto_cfg_status(struct ql3_adapter *qdev)
1530 {
1531         int status;
1532         unsigned long hw_flags;
1533         spin_lock_irqsave(&qdev->hw_lock, hw_flags);
1534         if(ql_sem_spinlock(qdev, QL_PHY_GIO_SEM_MASK,
1535                 (QL_RESOURCE_BITS_BASE_CODE | (qdev->mac_index) *
1536                          2) << 7)) {
1537                 spin_unlock_irqrestore(&qdev->hw_lock, hw_flags);
1538                 return 0;
1539         }
1540         status = ql_is_auto_cfg(qdev);
1541         ql_sem_unlock(qdev, QL_PHY_GIO_SEM_MASK);
1542         spin_unlock_irqrestore(&qdev->hw_lock, hw_flags);
1543         return status;
1544 }
1545
1546 static u32 ql_get_speed(struct ql3_adapter *qdev)
1547 {
1548         u32 status;
1549         unsigned long hw_flags;
1550         spin_lock_irqsave(&qdev->hw_lock, hw_flags);
1551         if(ql_sem_spinlock(qdev, QL_PHY_GIO_SEM_MASK,
1552                 (QL_RESOURCE_BITS_BASE_CODE | (qdev->mac_index) *
1553                          2) << 7)) {
1554                 spin_unlock_irqrestore(&qdev->hw_lock, hw_flags);
1555                 return 0;
1556         }
1557         status = ql_get_link_speed(qdev);
1558         ql_sem_unlock(qdev, QL_PHY_GIO_SEM_MASK);
1559         spin_unlock_irqrestore(&qdev->hw_lock, hw_flags);
1560         return status;
1561 }
1562
1563 static int ql_get_full_dup(struct ql3_adapter *qdev)
1564 {
1565         int status;
1566         unsigned long hw_flags;
1567         spin_lock_irqsave(&qdev->hw_lock, hw_flags);
1568         if(ql_sem_spinlock(qdev, QL_PHY_GIO_SEM_MASK,
1569                 (QL_RESOURCE_BITS_BASE_CODE | (qdev->mac_index) *
1570                          2) << 7)) {
1571                 spin_unlock_irqrestore(&qdev->hw_lock, hw_flags);
1572                 return 0;
1573         }
1574         status = ql_is_link_full_dup(qdev);
1575         ql_sem_unlock(qdev, QL_PHY_GIO_SEM_MASK);
1576         spin_unlock_irqrestore(&qdev->hw_lock, hw_flags);
1577         return status;
1578 }
1579
1580
1581 static int ql_get_settings(struct net_device *ndev, struct ethtool_cmd *ecmd)
1582 {
1583         struct ql3_adapter *qdev = netdev_priv(ndev);
1584
1585         ecmd->transceiver = XCVR_INTERNAL;
1586         ecmd->supported = ql_supported_modes(qdev);
1587
1588         if (test_bit(QL_LINK_OPTICAL,&qdev->flags)) {
1589                 ecmd->port = PORT_FIBRE;
1590         } else {
1591                 ecmd->port = PORT_TP;
1592                 ecmd->phy_address = qdev->PHYAddr;
1593         }
1594         ecmd->advertising = ql_supported_modes(qdev);
1595         ecmd->autoneg = ql_get_auto_cfg_status(qdev);
1596         ecmd->speed = ql_get_speed(qdev);
1597         ecmd->duplex = ql_get_full_dup(qdev);
1598         return 0;
1599 }
1600
1601 static void ql_get_drvinfo(struct net_device *ndev,
1602                            struct ethtool_drvinfo *drvinfo)
1603 {
1604         struct ql3_adapter *qdev = netdev_priv(ndev);
1605         strncpy(drvinfo->driver, ql3xxx_driver_name, 32);
1606         strncpy(drvinfo->version, ql3xxx_driver_version, 32);
1607         strncpy(drvinfo->fw_version, "N/A", 32);
1608         strncpy(drvinfo->bus_info, pci_name(qdev->pdev), 32);
1609         drvinfo->n_stats = 0;
1610         drvinfo->testinfo_len = 0;
1611         drvinfo->regdump_len = 0;
1612         drvinfo->eedump_len = 0;
1613 }
1614
1615 static u32 ql_get_msglevel(struct net_device *ndev)
1616 {
1617         struct ql3_adapter *qdev = netdev_priv(ndev);
1618         return qdev->msg_enable;
1619 }
1620
1621 static void ql_set_msglevel(struct net_device *ndev, u32 value)
1622 {
1623         struct ql3_adapter *qdev = netdev_priv(ndev);
1624         qdev->msg_enable = value;
1625 }
1626
1627 static const struct ethtool_ops ql3xxx_ethtool_ops = {
1628         .get_settings = ql_get_settings,
1629         .get_drvinfo = ql_get_drvinfo,
1630         .get_perm_addr = ethtool_op_get_perm_addr,
1631         .get_link = ethtool_op_get_link,
1632         .get_msglevel = ql_get_msglevel,
1633         .set_msglevel = ql_set_msglevel,
1634 };
1635
1636 static int ql_populate_free_queue(struct ql3_adapter *qdev)
1637 {
1638         struct ql_rcv_buf_cb *lrg_buf_cb = qdev->lrg_buf_free_head;
1639         dma_addr_t map;
1640         int err;
1641
1642         while (lrg_buf_cb) {
1643                 if (!lrg_buf_cb->skb) {
1644                         lrg_buf_cb->skb = netdev_alloc_skb(qdev->ndev,
1645                                                            qdev->lrg_buffer_len);
1646                         if (unlikely(!lrg_buf_cb->skb)) {
1647                                 printk(KERN_DEBUG PFX
1648                                        "%s: Failed netdev_alloc_skb().\n",
1649                                        qdev->ndev->name);
1650                                 break;
1651                         } else {
1652                                 /*
1653                                  * We save some space to copy the ethhdr from
1654                                  * first buffer
1655                                  */
1656                                 skb_reserve(lrg_buf_cb->skb, QL_HEADER_SPACE);
1657                                 map = pci_map_single(qdev->pdev,
1658                                                      lrg_buf_cb->skb->data,
1659                                                      qdev->lrg_buffer_len -
1660                                                      QL_HEADER_SPACE,
1661                                                      PCI_DMA_FROMDEVICE);
1662
1663                                 err = pci_dma_mapping_error(map);
1664                                 if(err) {
1665                                         printk(KERN_ERR "%s: PCI mapping failed with error: %d\n",
1666                                                qdev->ndev->name, err);
1667                                         dev_kfree_skb(lrg_buf_cb->skb);
1668                                         lrg_buf_cb->skb = NULL;
1669                                         break;
1670                                 }
1671
1672
1673                                 lrg_buf_cb->buf_phy_addr_low =
1674                                     cpu_to_le32(LS_64BITS(map));
1675                                 lrg_buf_cb->buf_phy_addr_high =
1676                                     cpu_to_le32(MS_64BITS(map));
1677                                 pci_unmap_addr_set(lrg_buf_cb, mapaddr, map);
1678                                 pci_unmap_len_set(lrg_buf_cb, maplen,
1679                                                   qdev->lrg_buffer_len -
1680                                                   QL_HEADER_SPACE);
1681                                 --qdev->lrg_buf_skb_check;
1682                                 if (!qdev->lrg_buf_skb_check)
1683                                         return 1;
1684                         }
1685                 }
1686                 lrg_buf_cb = lrg_buf_cb->next;
1687         }
1688         return 0;
1689 }
1690
1691 /*
1692  * Caller holds hw_lock.
1693  */
1694 static void ql_update_lrg_bufq_prod_index(struct ql3_adapter *qdev)
1695 {
1696         struct bufq_addr_element *lrg_buf_q_ele;
1697         int i;
1698         struct ql_rcv_buf_cb *lrg_buf_cb;
1699         struct ql3xxx_port_registers __iomem *port_regs = qdev->mem_map_registers;
1700
1701         if ((qdev->lrg_buf_free_count >= 8)
1702             && (qdev->lrg_buf_release_cnt >= 16)) {
1703
1704                 if (qdev->lrg_buf_skb_check)
1705                         if (!ql_populate_free_queue(qdev))
1706                                 return;
1707
1708                 lrg_buf_q_ele = qdev->lrg_buf_next_free;
1709
1710                 while ((qdev->lrg_buf_release_cnt >= 16)
1711                        && (qdev->lrg_buf_free_count >= 8)) {
1712
1713                         for (i = 0; i < 8; i++) {
1714                                 lrg_buf_cb =
1715                                     ql_get_from_lrg_buf_free_list(qdev);
1716                                 lrg_buf_q_ele->addr_high =
1717                                     lrg_buf_cb->buf_phy_addr_high;
1718                                 lrg_buf_q_ele->addr_low =
1719                                     lrg_buf_cb->buf_phy_addr_low;
1720                                 lrg_buf_q_ele++;
1721
1722                                 qdev->lrg_buf_release_cnt--;
1723                         }
1724
1725                         qdev->lrg_buf_q_producer_index++;
1726
1727                         if (qdev->lrg_buf_q_producer_index == qdev->num_lbufq_entries)
1728                                 qdev->lrg_buf_q_producer_index = 0;
1729
1730                         if (qdev->lrg_buf_q_producer_index ==
1731                             (qdev->num_lbufq_entries - 1)) {
1732                                 lrg_buf_q_ele = qdev->lrg_buf_q_virt_addr;
1733                         }
1734                 }
1735
1736                 qdev->lrg_buf_next_free = lrg_buf_q_ele;
1737
1738                 ql_write_common_reg(qdev,
1739                                     &port_regs->CommonRegs.
1740                                     rxLargeQProducerIndex,
1741                                     qdev->lrg_buf_q_producer_index);
1742         }
1743 }
1744
1745 static void ql_process_mac_tx_intr(struct ql3_adapter *qdev,
1746                                    struct ob_mac_iocb_rsp *mac_rsp)
1747 {
1748         struct ql_tx_buf_cb *tx_cb;
1749         int i;
1750
1751         tx_cb = &qdev->tx_buf[mac_rsp->transaction_id];
1752         pci_unmap_single(qdev->pdev,
1753                          pci_unmap_addr(&tx_cb->map[0], mapaddr),
1754                          pci_unmap_len(&tx_cb->map[0], maplen),
1755                          PCI_DMA_TODEVICE);
1756         tx_cb->seg_count--;
1757         if (tx_cb->seg_count) {
1758                 for (i = 1; i < tx_cb->seg_count; i++) {
1759                         pci_unmap_page(qdev->pdev,
1760                                        pci_unmap_addr(&tx_cb->map[i],
1761                                                       mapaddr),
1762                                        pci_unmap_len(&tx_cb->map[i], maplen),
1763                                        PCI_DMA_TODEVICE);
1764                 }
1765         }
1766         qdev->stats.tx_packets++;
1767         qdev->stats.tx_bytes += tx_cb->skb->len;
1768         dev_kfree_skb_irq(tx_cb->skb);
1769         tx_cb->skb = NULL;
1770         atomic_inc(&qdev->tx_count);
1771 }
1772
1773 void ql_get_sbuf(struct ql3_adapter *qdev)
1774 {
1775         if (++qdev->small_buf_index == NUM_SMALL_BUFFERS)
1776                 qdev->small_buf_index = 0;
1777         qdev->small_buf_release_cnt++;
1778 }
1779
1780 struct ql_rcv_buf_cb *ql_get_lbuf(struct ql3_adapter *qdev)
1781 {
1782         struct ql_rcv_buf_cb *lrg_buf_cb = NULL;
1783         lrg_buf_cb = &qdev->lrg_buf[qdev->lrg_buf_index];
1784         qdev->lrg_buf_release_cnt++;
1785         if (++qdev->lrg_buf_index == qdev->num_large_buffers)
1786                 qdev->lrg_buf_index = 0;
1787         return(lrg_buf_cb);
1788 }
1789
1790 /*
1791  * The difference between 3022 and 3032 for inbound completions:
1792  * 3022 uses two buffers per completion.  The first buffer contains
1793  * (some) header info, the second the remainder of the headers plus
1794  * the data.  For this chip we reserve some space at the top of the
1795  * receive buffer so that the header info in buffer one can be
1796  * prepended to the buffer two.  Buffer two is the sent up while
1797  * buffer one is returned to the hardware to be reused.
1798  * 3032 receives all of it's data and headers in one buffer for a
1799  * simpler process.  3032 also supports checksum verification as
1800  * can be seen in ql_process_macip_rx_intr().
1801  */
1802 static void ql_process_mac_rx_intr(struct ql3_adapter *qdev,
1803                                    struct ib_mac_iocb_rsp *ib_mac_rsp_ptr)
1804 {
1805         struct ql_rcv_buf_cb *lrg_buf_cb1 = NULL;
1806         struct ql_rcv_buf_cb *lrg_buf_cb2 = NULL;
1807         struct sk_buff *skb;
1808         u16 length = le16_to_cpu(ib_mac_rsp_ptr->length);
1809
1810         /*
1811          * Get the inbound address list (small buffer).
1812          */
1813         ql_get_sbuf(qdev);
1814
1815         if (qdev->device_id == QL3022_DEVICE_ID)
1816                 lrg_buf_cb1 = ql_get_lbuf(qdev);
1817
1818         /* start of second buffer */
1819         lrg_buf_cb2 = ql_get_lbuf(qdev);
1820         skb = lrg_buf_cb2->skb;
1821
1822         qdev->stats.rx_packets++;
1823         qdev->stats.rx_bytes += length;
1824
1825         skb_put(skb, length);
1826         pci_unmap_single(qdev->pdev,
1827                          pci_unmap_addr(lrg_buf_cb2, mapaddr),
1828                          pci_unmap_len(lrg_buf_cb2, maplen),
1829                          PCI_DMA_FROMDEVICE);
1830         prefetch(skb->data);
1831         skb->dev = qdev->ndev;
1832         skb->ip_summed = CHECKSUM_NONE;
1833         skb->protocol = eth_type_trans(skb, qdev->ndev);
1834
1835         netif_receive_skb(skb);
1836         qdev->ndev->last_rx = jiffies;
1837         lrg_buf_cb2->skb = NULL;
1838
1839         if (qdev->device_id == QL3022_DEVICE_ID)
1840                 ql_release_to_lrg_buf_free_list(qdev, lrg_buf_cb1);
1841         ql_release_to_lrg_buf_free_list(qdev, lrg_buf_cb2);
1842 }
1843
1844 static void ql_process_macip_rx_intr(struct ql3_adapter *qdev,
1845                                      struct ib_ip_iocb_rsp *ib_ip_rsp_ptr)
1846 {
1847         struct ql_rcv_buf_cb *lrg_buf_cb1 = NULL;
1848         struct ql_rcv_buf_cb *lrg_buf_cb2 = NULL;
1849         struct sk_buff *skb1 = NULL, *skb2;
1850         struct net_device *ndev = qdev->ndev;
1851         u16 length = le16_to_cpu(ib_ip_rsp_ptr->length);
1852         u16 size = 0;
1853
1854         /*
1855          * Get the inbound address list (small buffer).
1856          */
1857
1858         ql_get_sbuf(qdev);
1859
1860         if (qdev->device_id == QL3022_DEVICE_ID) {
1861                 /* start of first buffer on 3022 */
1862                 lrg_buf_cb1 = ql_get_lbuf(qdev);
1863                 skb1 = lrg_buf_cb1->skb;
1864                 size = ETH_HLEN;
1865                 if (*((u16 *) skb1->data) != 0xFFFF)
1866                         size += VLAN_ETH_HLEN - ETH_HLEN;
1867         }
1868
1869         /* start of second buffer */
1870         lrg_buf_cb2 = ql_get_lbuf(qdev);
1871         skb2 = lrg_buf_cb2->skb;
1872
1873         skb_put(skb2, length);  /* Just the second buffer length here. */
1874         pci_unmap_single(qdev->pdev,
1875                          pci_unmap_addr(lrg_buf_cb2, mapaddr),
1876                          pci_unmap_len(lrg_buf_cb2, maplen),
1877                          PCI_DMA_FROMDEVICE);
1878         prefetch(skb2->data);
1879
1880         skb2->ip_summed = CHECKSUM_NONE;
1881         if (qdev->device_id == QL3022_DEVICE_ID) {
1882                 /*
1883                  * Copy the ethhdr from first buffer to second. This
1884                  * is necessary for 3022 IP completions.
1885                  */
1886                 memcpy(skb_push(skb2, size), skb1->data + VLAN_ID_LEN, size);
1887         } else {
1888                 u16 checksum = le16_to_cpu(ib_ip_rsp_ptr->checksum);
1889                 if (checksum &
1890                         (IB_IP_IOCB_RSP_3032_ICE |
1891                          IB_IP_IOCB_RSP_3032_CE |
1892                          IB_IP_IOCB_RSP_3032_NUC)) {
1893                         printk(KERN_ERR
1894                                "%s: Bad checksum for this %s packet, checksum = %x.\n",
1895                                __func__,
1896                                ((checksum &
1897                                 IB_IP_IOCB_RSP_3032_TCP) ? "TCP" :
1898                                 "UDP"),checksum);
1899                 } else if (checksum & IB_IP_IOCB_RSP_3032_TCP) {
1900                         skb2->ip_summed = CHECKSUM_UNNECESSARY;
1901                 }
1902         }
1903         skb2->dev = qdev->ndev;
1904         skb2->protocol = eth_type_trans(skb2, qdev->ndev);
1905
1906         netif_receive_skb(skb2);
1907         qdev->stats.rx_packets++;
1908         qdev->stats.rx_bytes += length;
1909         ndev->last_rx = jiffies;
1910         lrg_buf_cb2->skb = NULL;
1911
1912         if (qdev->device_id == QL3022_DEVICE_ID)
1913                 ql_release_to_lrg_buf_free_list(qdev, lrg_buf_cb1);
1914         ql_release_to_lrg_buf_free_list(qdev, lrg_buf_cb2);
1915 }
1916
1917 static int ql_tx_rx_clean(struct ql3_adapter *qdev,
1918                           int *tx_cleaned, int *rx_cleaned, int work_to_do)
1919 {
1920         struct ql3xxx_port_registers __iomem *port_regs = qdev->mem_map_registers;
1921         struct net_rsp_iocb *net_rsp;
1922         struct net_device *ndev = qdev->ndev;
1923         unsigned long hw_flags;
1924
1925         /* While there are entries in the completion queue. */
1926         while ((cpu_to_le32(*(qdev->prsp_producer_index)) !=
1927                 qdev->rsp_consumer_index) && (*rx_cleaned < work_to_do)) {
1928
1929                 net_rsp = qdev->rsp_current;
1930                 switch (net_rsp->opcode) {
1931
1932                 case OPCODE_OB_MAC_IOCB_FN0:
1933                 case OPCODE_OB_MAC_IOCB_FN2:
1934                         ql_process_mac_tx_intr(qdev, (struct ob_mac_iocb_rsp *)
1935                                                net_rsp);
1936                         (*tx_cleaned)++;
1937                         break;
1938
1939                 case OPCODE_IB_MAC_IOCB:
1940                 case OPCODE_IB_3032_MAC_IOCB:
1941                         ql_process_mac_rx_intr(qdev, (struct ib_mac_iocb_rsp *)
1942                                                net_rsp);
1943                         (*rx_cleaned)++;
1944                         break;
1945
1946                 case OPCODE_IB_IP_IOCB:
1947                 case OPCODE_IB_3032_IP_IOCB:
1948                         ql_process_macip_rx_intr(qdev, (struct ib_ip_iocb_rsp *)
1949                                                  net_rsp);
1950                         (*rx_cleaned)++;
1951                         break;
1952                 default:
1953                         {
1954                                 u32 *tmp = (u32 *) net_rsp;
1955                                 printk(KERN_ERR PFX
1956                                        "%s: Hit default case, not "
1957                                        "handled!\n"
1958                                        "        dropping the packet, opcode = "
1959                                        "%x.\n",
1960                                        ndev->name, net_rsp->opcode);
1961                                 printk(KERN_ERR PFX
1962                                        "0x%08lx 0x%08lx 0x%08lx 0x%08lx \n",
1963                                        (unsigned long int)tmp[0],
1964                                        (unsigned long int)tmp[1],
1965                                        (unsigned long int)tmp[2],
1966                                        (unsigned long int)tmp[3]);
1967                         }
1968                 }
1969
1970                 qdev->rsp_consumer_index++;
1971
1972                 if (qdev->rsp_consumer_index == NUM_RSP_Q_ENTRIES) {
1973                         qdev->rsp_consumer_index = 0;
1974                         qdev->rsp_current = qdev->rsp_q_virt_addr;
1975                 } else {
1976                         qdev->rsp_current++;
1977                 }
1978         }
1979
1980         spin_lock_irqsave(&qdev->hw_lock, hw_flags);
1981
1982         ql_update_lrg_bufq_prod_index(qdev);
1983
1984         if (qdev->small_buf_release_cnt >= 16) {
1985                 while (qdev->small_buf_release_cnt >= 16) {
1986                         qdev->small_buf_q_producer_index++;
1987
1988                         if (qdev->small_buf_q_producer_index ==
1989                             NUM_SBUFQ_ENTRIES)
1990                                 qdev->small_buf_q_producer_index = 0;
1991                         qdev->small_buf_release_cnt -= 8;
1992                 }
1993
1994                 ql_write_common_reg(qdev,
1995                                     &port_regs->CommonRegs.
1996                                     rxSmallQProducerIndex,
1997                                     qdev->small_buf_q_producer_index);
1998         }
1999
2000         ql_write_common_reg(qdev,
2001                             &port_regs->CommonRegs.rspQConsumerIndex,
2002                             qdev->rsp_consumer_index);
2003         spin_unlock_irqrestore(&qdev->hw_lock, hw_flags);
2004
2005         if (unlikely(netif_queue_stopped(qdev->ndev))) {
2006                 if (netif_queue_stopped(qdev->ndev) &&
2007                     (atomic_read(&qdev->tx_count) > (NUM_REQ_Q_ENTRIES / 4)))
2008                         netif_wake_queue(qdev->ndev);
2009         }
2010
2011         return *tx_cleaned + *rx_cleaned;
2012 }
2013
2014 static int ql_poll(struct net_device *ndev, int *budget)
2015 {
2016         struct ql3_adapter *qdev = netdev_priv(ndev);
2017         int work_to_do = min(*budget, ndev->quota);
2018         int rx_cleaned = 0, tx_cleaned = 0;
2019
2020         if (!netif_carrier_ok(ndev))
2021                 goto quit_polling;
2022
2023         ql_tx_rx_clean(qdev, &tx_cleaned, &rx_cleaned, work_to_do);
2024         *budget -= rx_cleaned;
2025         ndev->quota -= rx_cleaned;
2026
2027         if ((!tx_cleaned && !rx_cleaned) || !netif_running(ndev)) {
2028 quit_polling:
2029                 netif_rx_complete(ndev);
2030                 ql_enable_interrupts(qdev);
2031                 return 0;
2032         }
2033         return 1;
2034 }
2035
2036 static irqreturn_t ql3xxx_isr(int irq, void *dev_id)
2037 {
2038
2039         struct net_device *ndev = dev_id;
2040         struct ql3_adapter *qdev = netdev_priv(ndev);
2041         struct ql3xxx_port_registers __iomem *port_regs = qdev->mem_map_registers;
2042         u32 value;
2043         int handled = 1;
2044         u32 var;
2045
2046         port_regs = qdev->mem_map_registers;
2047
2048         value =
2049             ql_read_common_reg_l(qdev, &port_regs->CommonRegs.ispControlStatus);
2050
2051         if (value & (ISP_CONTROL_FE | ISP_CONTROL_RI)) {
2052                 spin_lock(&qdev->adapter_lock);
2053                 netif_stop_queue(qdev->ndev);
2054                 netif_carrier_off(qdev->ndev);
2055                 ql_disable_interrupts(qdev);
2056                 qdev->port_link_state = LS_DOWN;
2057                 set_bit(QL_RESET_ACTIVE,&qdev->flags) ;
2058
2059                 if (value & ISP_CONTROL_FE) {
2060                         /*
2061                          * Chip Fatal Error.
2062                          */
2063                         var =
2064                             ql_read_page0_reg_l(qdev,
2065                                               &port_regs->PortFatalErrStatus);
2066                         printk(KERN_WARNING PFX
2067                                "%s: Resetting chip. PortFatalErrStatus "
2068                                "register = 0x%x\n", ndev->name, var);
2069                         set_bit(QL_RESET_START,&qdev->flags) ;
2070                 } else {
2071                         /*
2072                          * Soft Reset Requested.
2073                          */
2074                         set_bit(QL_RESET_PER_SCSI,&qdev->flags) ;
2075                         printk(KERN_ERR PFX
2076                                "%s: Another function issued a reset to the "
2077                                "chip. ISR value = %x.\n", ndev->name, value);
2078                 }
2079                 queue_delayed_work(qdev->workqueue, &qdev->reset_work, 0);
2080                 spin_unlock(&qdev->adapter_lock);
2081         } else if (value & ISP_IMR_DISABLE_CMPL_INT) {
2082                 ql_disable_interrupts(qdev);
2083                 if (likely(netif_rx_schedule_prep(ndev)))
2084                         __netif_rx_schedule(ndev);
2085                 else
2086                         ql_enable_interrupts(qdev);
2087         } else {
2088                 return IRQ_NONE;
2089         }
2090
2091         return IRQ_RETVAL(handled);
2092 }
2093
2094 /*
2095  * Get the total number of segments needed for the
2096  * given number of fragments.  This is necessary because
2097  * outbound address lists (OAL) will be used when more than
2098  * two frags are given.  Each address list has 5 addr/len
2099  * pairs.  The 5th pair in each AOL is used to  point to
2100  * the next AOL if more frags are coming.
2101  * That is why the frags:segment count  ratio is not linear.
2102  */
2103 static int ql_get_seg_count(unsigned short frags)
2104 {
2105         switch(frags) {
2106         case 0: return 1;       /* just the skb->data seg */
2107         case 1: return 2;       /* skb->data + 1 frag */
2108         case 2: return 3;       /* skb->data + 2 frags */
2109         case 3: return 5;       /* skb->data + 1 frag + 1 AOL containting 2 frags */
2110         case 4: return 6;
2111         case 5: return 7;
2112         case 6: return 8;
2113         case 7: return 10;
2114         case 8: return 11;
2115         case 9: return 12;
2116         case 10: return 13;
2117         case 11: return 15;
2118         case 12: return 16;
2119         case 13: return 17;
2120         case 14: return 18;
2121         case 15: return 20;
2122         case 16: return 21;
2123         case 17: return 22;
2124         case 18: return 23;
2125         }
2126         return -1;
2127 }
2128
2129 static void ql_hw_csum_setup(struct sk_buff *skb,
2130                              struct ob_mac_iocb_req *mac_iocb_ptr)
2131 {
2132         struct ethhdr *eth;
2133         struct iphdr *ip = NULL;
2134         u8 offset = ETH_HLEN;
2135
2136         eth = (struct ethhdr *)(skb->data);
2137
2138         if (eth->h_proto == __constant_htons(ETH_P_IP)) {
2139                 ip = (struct iphdr *)&skb->data[ETH_HLEN];
2140         } else if (eth->h_proto == htons(ETH_P_8021Q) &&
2141                    ((struct vlan_ethhdr *)skb->data)->
2142                    h_vlan_encapsulated_proto == __constant_htons(ETH_P_IP)) {
2143                 ip = (struct iphdr *)&skb->data[VLAN_ETH_HLEN];
2144                 offset = VLAN_ETH_HLEN;
2145         }
2146
2147         if (ip) {
2148                 if (ip->protocol == IPPROTO_TCP) {
2149                         mac_iocb_ptr->flags1 |= OB_3032MAC_IOCB_REQ_TC |
2150                         OB_3032MAC_IOCB_REQ_IC;
2151                         mac_iocb_ptr->ip_hdr_off = offset;
2152                         mac_iocb_ptr->ip_hdr_len = ip->ihl;
2153                 } else if (ip->protocol == IPPROTO_UDP) {
2154                         mac_iocb_ptr->flags1 |= OB_3032MAC_IOCB_REQ_UC |
2155                         OB_3032MAC_IOCB_REQ_IC;
2156                         mac_iocb_ptr->ip_hdr_off = offset;
2157                         mac_iocb_ptr->ip_hdr_len = ip->ihl;
2158                 }
2159         }
2160 }
2161
2162 /*
2163  * Map the buffers for this transmit.  This will return
2164  * NETDEV_TX_BUSY or NETDEV_TX_OK based on success.
2165  */
2166 static int ql_send_map(struct ql3_adapter *qdev,
2167                                 struct ob_mac_iocb_req *mac_iocb_ptr,
2168                                 struct ql_tx_buf_cb *tx_cb,
2169                                 struct sk_buff *skb)
2170 {
2171         struct oal *oal;
2172         struct oal_entry *oal_entry;
2173         int len = skb_headlen(skb);
2174         dma_addr_t map;
2175         int err;
2176         int completed_segs, i;
2177         int seg_cnt, seg = 0;
2178         int frag_cnt = (int)skb_shinfo(skb)->nr_frags;
2179
2180         seg_cnt = tx_cb->seg_count = ql_get_seg_count((skb_shinfo(skb)->nr_frags));
2181         if(seg_cnt == -1) {
2182                 printk(KERN_ERR PFX"%s: invalid segment count!\n",__func__);
2183                 return NETDEV_TX_BUSY;
2184         }
2185         /*
2186          * Map the skb buffer first.
2187          */
2188         map = pci_map_single(qdev->pdev, skb->data, len, PCI_DMA_TODEVICE);
2189
2190         err = pci_dma_mapping_error(map);
2191         if(err) {
2192                 printk(KERN_ERR "%s: PCI mapping failed with error: %d\n",
2193                        qdev->ndev->name, err);
2194
2195                 return NETDEV_TX_BUSY;
2196         }
2197
2198         oal_entry = (struct oal_entry *)&mac_iocb_ptr->buf_addr0_low;
2199         oal_entry->dma_lo = cpu_to_le32(LS_64BITS(map));
2200         oal_entry->dma_hi = cpu_to_le32(MS_64BITS(map));
2201         oal_entry->len = cpu_to_le32(len);
2202         pci_unmap_addr_set(&tx_cb->map[seg], mapaddr, map);
2203         pci_unmap_len_set(&tx_cb->map[seg], maplen, len);
2204         seg++;
2205
2206         if (!skb_shinfo(skb)->nr_frags) {
2207                 /* Terminate the last segment. */
2208                 oal_entry->len =
2209                     cpu_to_le32(le32_to_cpu(oal_entry->len) | OAL_LAST_ENTRY);
2210         } else {
2211                 oal = tx_cb->oal;
2212                 for (completed_segs=0; completed_segs<frag_cnt; completed_segs++,seg++) {
2213                         skb_frag_t *frag = &skb_shinfo(skb)->frags[completed_segs];
2214                         oal_entry++;
2215                         if ((seg == 2 && seg_cnt > 3) ||        /* Check for continuation */
2216                             (seg == 7 && seg_cnt > 8) ||        /* requirements. It's strange */
2217                             (seg == 12 && seg_cnt > 13) ||      /* but necessary. */
2218                             (seg == 17 && seg_cnt > 18)) {
2219                                 /* Continuation entry points to outbound address list. */
2220                                 map = pci_map_single(qdev->pdev, oal,
2221                                                      sizeof(struct oal),
2222                                                      PCI_DMA_TODEVICE);
2223
2224                                 err = pci_dma_mapping_error(map);
2225                                 if(err) {
2226
2227                                         printk(KERN_ERR "%s: PCI mapping outbound address list with error: %d\n",
2228                                                qdev->ndev->name, err);
2229                                         goto map_error;
2230                                 }
2231
2232                                 oal_entry->dma_lo = cpu_to_le32(LS_64BITS(map));
2233                                 oal_entry->dma_hi = cpu_to_le32(MS_64BITS(map));
2234                                 oal_entry->len =
2235                                     cpu_to_le32(sizeof(struct oal) |
2236                                                 OAL_CONT_ENTRY);
2237                                 pci_unmap_addr_set(&tx_cb->map[seg], mapaddr,
2238                                                    map);
2239                                 pci_unmap_len_set(&tx_cb->map[seg], maplen,
2240                                                   len);
2241                                 oal_entry = (struct oal_entry *)oal;
2242                                 oal++;
2243                                 seg++;
2244                         }
2245
2246                         map =
2247                             pci_map_page(qdev->pdev, frag->page,
2248                                          frag->page_offset, frag->size,
2249                                          PCI_DMA_TODEVICE);
2250
2251                         err = pci_dma_mapping_error(map);
2252                         if(err) {
2253                                 printk(KERN_ERR "%s: PCI mapping frags failed with error: %d\n",
2254                                        qdev->ndev->name, err);
2255                                 goto map_error;
2256                         }
2257
2258                         oal_entry->dma_lo = cpu_to_le32(LS_64BITS(map));
2259                         oal_entry->dma_hi = cpu_to_le32(MS_64BITS(map));
2260                         oal_entry->len = cpu_to_le32(frag->size);
2261                         pci_unmap_addr_set(&tx_cb->map[seg], mapaddr, map);
2262                         pci_unmap_len_set(&tx_cb->map[seg], maplen,
2263                                           frag->size);
2264                 }
2265                 /* Terminate the last segment. */
2266                 oal_entry->len =
2267                     cpu_to_le32(le32_to_cpu(oal_entry->len) | OAL_LAST_ENTRY);
2268         }
2269
2270         return NETDEV_TX_OK;
2271
2272 map_error:
2273         /* A PCI mapping failed and now we will need to back out
2274          * We need to traverse through the oal's and associated pages which
2275          * have been mapped and now we must unmap them to clean up properly
2276          */
2277
2278         seg = 1;
2279         oal_entry = (struct oal_entry *)&mac_iocb_ptr->buf_addr0_low;
2280         oal = tx_cb->oal;
2281         for (i=0; i<completed_segs; i++,seg++) {
2282                 oal_entry++;
2283
2284                 if((seg == 2 && seg_cnt > 3) ||        /* Check for continuation */
2285                    (seg == 7 && seg_cnt > 8) ||        /* requirements. It's strange */
2286                    (seg == 12 && seg_cnt > 13) ||      /* but necessary. */
2287                    (seg == 17 && seg_cnt > 18)) {
2288                         pci_unmap_single(qdev->pdev,
2289                                 pci_unmap_addr(&tx_cb->map[seg], mapaddr),
2290                                 pci_unmap_len(&tx_cb->map[seg], maplen),
2291                                  PCI_DMA_TODEVICE);
2292                         oal++;
2293                         seg++;
2294                 }
2295
2296                 pci_unmap_page(qdev->pdev,
2297                                pci_unmap_addr(&tx_cb->map[seg], mapaddr),
2298                                pci_unmap_len(&tx_cb->map[seg], maplen),
2299                                PCI_DMA_TODEVICE);
2300         }
2301
2302         pci_unmap_single(qdev->pdev,
2303                          pci_unmap_addr(&tx_cb->map[0], mapaddr),
2304                          pci_unmap_addr(&tx_cb->map[0], maplen),
2305                          PCI_DMA_TODEVICE);
2306
2307         return NETDEV_TX_BUSY;
2308
2309 }
2310
2311 /*
2312  * The difference between 3022 and 3032 sends:
2313  * 3022 only supports a simple single segment transmission.
2314  * 3032 supports checksumming and scatter/gather lists (fragments).
2315  * The 3032 supports sglists by using the 3 addr/len pairs (ALP)
2316  * in the IOCB plus a chain of outbound address lists (OAL) that
2317  * each contain 5 ALPs.  The last ALP of the IOCB (3rd) or OAL (5th)
2318  * will used to point to an OAL when more ALP entries are required.
2319  * The IOCB is always the top of the chain followed by one or more
2320  * OALs (when necessary).
2321  */
2322 static int ql3xxx_send(struct sk_buff *skb, struct net_device *ndev)
2323 {
2324         struct ql3_adapter *qdev = (struct ql3_adapter *)netdev_priv(ndev);
2325         struct ql3xxx_port_registers __iomem *port_regs = qdev->mem_map_registers;
2326         struct ql_tx_buf_cb *tx_cb;
2327         u32 tot_len = skb->len;
2328         struct ob_mac_iocb_req *mac_iocb_ptr;
2329
2330         if (unlikely(atomic_read(&qdev->tx_count) < 2)) {
2331                 if (!netif_queue_stopped(ndev))
2332                         netif_stop_queue(ndev);
2333                 return NETDEV_TX_BUSY;
2334         }
2335
2336         tx_cb = &qdev->tx_buf[qdev->req_producer_index] ;
2337         if((tx_cb->seg_count = ql_get_seg_count((skb_shinfo(skb)->nr_frags))) == -1) {
2338                 printk(KERN_ERR PFX"%s: invalid segment count!\n",__func__);
2339                 return NETDEV_TX_OK;
2340         }
2341
2342         mac_iocb_ptr = tx_cb->queue_entry;
2343         mac_iocb_ptr->opcode = qdev->mac_ob_opcode;
2344         mac_iocb_ptr->flags = OB_MAC_IOCB_REQ_X;
2345         mac_iocb_ptr->flags |= qdev->mb_bit_mask;
2346         mac_iocb_ptr->transaction_id = qdev->req_producer_index;
2347         mac_iocb_ptr->data_len = cpu_to_le16((u16) tot_len);
2348         tx_cb->skb = skb;
2349         if (skb->ip_summed == CHECKSUM_PARTIAL)
2350                 ql_hw_csum_setup(skb, mac_iocb_ptr);
2351
2352         if(ql_send_map(qdev,mac_iocb_ptr,tx_cb,skb) != NETDEV_TX_OK) {
2353                 printk(KERN_ERR PFX"%s: Could not map the segments!\n",__func__);
2354                 return NETDEV_TX_BUSY;
2355         }
2356
2357         wmb();
2358         qdev->req_producer_index++;
2359         if (qdev->req_producer_index == NUM_REQ_Q_ENTRIES)
2360                 qdev->req_producer_index = 0;
2361         wmb();
2362         ql_write_common_reg_l(qdev,
2363                             &port_regs->CommonRegs.reqQProducerIndex,
2364                             qdev->req_producer_index);
2365
2366         ndev->trans_start = jiffies;
2367         if (netif_msg_tx_queued(qdev))
2368                 printk(KERN_DEBUG PFX "%s: tx queued, slot %d, len %d\n",
2369                        ndev->name, qdev->req_producer_index, skb->len);
2370
2371         atomic_dec(&qdev->tx_count);
2372         return NETDEV_TX_OK;
2373 }
2374
2375 static int ql_alloc_net_req_rsp_queues(struct ql3_adapter *qdev)
2376 {
2377         qdev->req_q_size =
2378             (u32) (NUM_REQ_Q_ENTRIES * sizeof(struct ob_mac_iocb_req));
2379
2380         qdev->req_q_virt_addr =
2381             pci_alloc_consistent(qdev->pdev,
2382                                  (size_t) qdev->req_q_size,
2383                                  &qdev->req_q_phy_addr);
2384
2385         if ((qdev->req_q_virt_addr == NULL) ||
2386             LS_64BITS(qdev->req_q_phy_addr) & (qdev->req_q_size - 1)) {
2387                 printk(KERN_ERR PFX "%s: reqQ failed.\n",
2388                        qdev->ndev->name);
2389                 return -ENOMEM;
2390         }
2391
2392         qdev->rsp_q_size = NUM_RSP_Q_ENTRIES * sizeof(struct net_rsp_iocb);
2393
2394         qdev->rsp_q_virt_addr =
2395             pci_alloc_consistent(qdev->pdev,
2396                                  (size_t) qdev->rsp_q_size,
2397                                  &qdev->rsp_q_phy_addr);
2398
2399         if ((qdev->rsp_q_virt_addr == NULL) ||
2400             LS_64BITS(qdev->rsp_q_phy_addr) & (qdev->rsp_q_size - 1)) {
2401                 printk(KERN_ERR PFX
2402                        "%s: rspQ allocation failed\n",
2403                        qdev->ndev->name);
2404                 pci_free_consistent(qdev->pdev, (size_t) qdev->req_q_size,
2405                                     qdev->req_q_virt_addr,
2406                                     qdev->req_q_phy_addr);
2407                 return -ENOMEM;
2408         }
2409
2410         set_bit(QL_ALLOC_REQ_RSP_Q_DONE,&qdev->flags);
2411
2412         return 0;
2413 }
2414
2415 static void ql_free_net_req_rsp_queues(struct ql3_adapter *qdev)
2416 {
2417         if (!test_bit(QL_ALLOC_REQ_RSP_Q_DONE,&qdev->flags)) {
2418                 printk(KERN_INFO PFX
2419                        "%s: Already done.\n", qdev->ndev->name);
2420                 return;
2421         }
2422
2423         pci_free_consistent(qdev->pdev,
2424                             qdev->req_q_size,
2425                             qdev->req_q_virt_addr, qdev->req_q_phy_addr);
2426
2427         qdev->req_q_virt_addr = NULL;
2428
2429         pci_free_consistent(qdev->pdev,
2430                             qdev->rsp_q_size,
2431                             qdev->rsp_q_virt_addr, qdev->rsp_q_phy_addr);
2432
2433         qdev->rsp_q_virt_addr = NULL;
2434
2435         clear_bit(QL_ALLOC_REQ_RSP_Q_DONE,&qdev->flags);
2436 }
2437
2438 static int ql_alloc_buffer_queues(struct ql3_adapter *qdev)
2439 {
2440         /* Create Large Buffer Queue */
2441         qdev->lrg_buf_q_size =
2442             qdev->num_lbufq_entries * sizeof(struct lrg_buf_q_entry);
2443         if (qdev->lrg_buf_q_size < PAGE_SIZE)
2444                 qdev->lrg_buf_q_alloc_size = PAGE_SIZE;
2445         else
2446                 qdev->lrg_buf_q_alloc_size = qdev->lrg_buf_q_size * 2;
2447
2448         qdev->lrg_buf = kmalloc(qdev->num_large_buffers * sizeof(struct ql_rcv_buf_cb),GFP_KERNEL);
2449         if (qdev->lrg_buf == NULL) {
2450                 printk(KERN_ERR PFX
2451                        "%s: qdev->lrg_buf alloc failed.\n", qdev->ndev->name);
2452                 return -ENOMEM;
2453         }
2454
2455         qdev->lrg_buf_q_alloc_virt_addr =
2456             pci_alloc_consistent(qdev->pdev,
2457                                  qdev->lrg_buf_q_alloc_size,
2458                                  &qdev->lrg_buf_q_alloc_phy_addr);
2459
2460         if (qdev->lrg_buf_q_alloc_virt_addr == NULL) {
2461                 printk(KERN_ERR PFX
2462                        "%s: lBufQ failed\n", qdev->ndev->name);
2463                 return -ENOMEM;
2464         }
2465         qdev->lrg_buf_q_virt_addr = qdev->lrg_buf_q_alloc_virt_addr;
2466         qdev->lrg_buf_q_phy_addr = qdev->lrg_buf_q_alloc_phy_addr;
2467
2468         /* Create Small Buffer Queue */
2469         qdev->small_buf_q_size =
2470             NUM_SBUFQ_ENTRIES * sizeof(struct lrg_buf_q_entry);
2471         if (qdev->small_buf_q_size < PAGE_SIZE)
2472                 qdev->small_buf_q_alloc_size = PAGE_SIZE;
2473         else
2474                 qdev->small_buf_q_alloc_size = qdev->small_buf_q_size * 2;
2475
2476         qdev->small_buf_q_alloc_virt_addr =
2477             pci_alloc_consistent(qdev->pdev,
2478                                  qdev->small_buf_q_alloc_size,
2479                                  &qdev->small_buf_q_alloc_phy_addr);
2480
2481         if (qdev->small_buf_q_alloc_virt_addr == NULL) {
2482                 printk(KERN_ERR PFX
2483                        "%s: Small Buffer Queue allocation failed.\n",
2484                        qdev->ndev->name);
2485                 pci_free_consistent(qdev->pdev, qdev->lrg_buf_q_alloc_size,
2486                                     qdev->lrg_buf_q_alloc_virt_addr,
2487                                     qdev->lrg_buf_q_alloc_phy_addr);
2488                 return -ENOMEM;
2489         }
2490
2491         qdev->small_buf_q_virt_addr = qdev->small_buf_q_alloc_virt_addr;
2492         qdev->small_buf_q_phy_addr = qdev->small_buf_q_alloc_phy_addr;
2493         set_bit(QL_ALLOC_BUFQS_DONE,&qdev->flags);
2494         return 0;
2495 }
2496
2497 static void ql_free_buffer_queues(struct ql3_adapter *qdev)
2498 {
2499         if (!test_bit(QL_ALLOC_BUFQS_DONE,&qdev->flags)) {
2500                 printk(KERN_INFO PFX
2501                        "%s: Already done.\n", qdev->ndev->name);
2502                 return;
2503         }
2504         if(qdev->lrg_buf) kfree(qdev->lrg_buf);
2505         pci_free_consistent(qdev->pdev,
2506                             qdev->lrg_buf_q_alloc_size,
2507                             qdev->lrg_buf_q_alloc_virt_addr,
2508                             qdev->lrg_buf_q_alloc_phy_addr);
2509
2510         qdev->lrg_buf_q_virt_addr = NULL;
2511
2512         pci_free_consistent(qdev->pdev,
2513                             qdev->small_buf_q_alloc_size,
2514                             qdev->small_buf_q_alloc_virt_addr,
2515                             qdev->small_buf_q_alloc_phy_addr);
2516
2517         qdev->small_buf_q_virt_addr = NULL;
2518
2519         clear_bit(QL_ALLOC_BUFQS_DONE,&qdev->flags);
2520 }
2521
2522 static int ql_alloc_small_buffers(struct ql3_adapter *qdev)
2523 {
2524         int i;
2525         struct bufq_addr_element *small_buf_q_entry;
2526
2527         /* Currently we allocate on one of memory and use it for smallbuffers */
2528         qdev->small_buf_total_size =
2529             (QL_ADDR_ELE_PER_BUFQ_ENTRY * NUM_SBUFQ_ENTRIES *
2530              QL_SMALL_BUFFER_SIZE);
2531
2532         qdev->small_buf_virt_addr =
2533             pci_alloc_consistent(qdev->pdev,
2534                                  qdev->small_buf_total_size,
2535                                  &qdev->small_buf_phy_addr);
2536
2537         if (qdev->small_buf_virt_addr == NULL) {
2538                 printk(KERN_ERR PFX
2539                        "%s: Failed to get small buffer memory.\n",
2540                        qdev->ndev->name);
2541                 return -ENOMEM;
2542         }
2543
2544         qdev->small_buf_phy_addr_low = LS_64BITS(qdev->small_buf_phy_addr);
2545         qdev->small_buf_phy_addr_high = MS_64BITS(qdev->small_buf_phy_addr);
2546
2547         small_buf_q_entry = qdev->small_buf_q_virt_addr;
2548
2549         /* Initialize the small buffer queue. */
2550         for (i = 0; i < (QL_ADDR_ELE_PER_BUFQ_ENTRY * NUM_SBUFQ_ENTRIES); i++) {
2551                 small_buf_q_entry->addr_high =
2552                     cpu_to_le32(qdev->small_buf_phy_addr_high);
2553                 small_buf_q_entry->addr_low =
2554                     cpu_to_le32(qdev->small_buf_phy_addr_low +
2555                                 (i * QL_SMALL_BUFFER_SIZE));
2556                 small_buf_q_entry++;
2557         }
2558         qdev->small_buf_index = 0;
2559         set_bit(QL_ALLOC_SMALL_BUF_DONE,&qdev->flags);
2560         return 0;
2561 }
2562
2563 static void ql_free_small_buffers(struct ql3_adapter *qdev)
2564 {
2565         if (!test_bit(QL_ALLOC_SMALL_BUF_DONE,&qdev->flags)) {
2566                 printk(KERN_INFO PFX
2567                        "%s: Already done.\n", qdev->ndev->name);
2568                 return;
2569         }
2570         if (qdev->small_buf_virt_addr != NULL) {
2571                 pci_free_consistent(qdev->pdev,
2572                                     qdev->small_buf_total_size,
2573                                     qdev->small_buf_virt_addr,
2574                                     qdev->small_buf_phy_addr);
2575
2576                 qdev->small_buf_virt_addr = NULL;
2577         }
2578 }
2579
2580 static void ql_free_large_buffers(struct ql3_adapter *qdev)
2581 {
2582         int i = 0;
2583         struct ql_rcv_buf_cb *lrg_buf_cb;
2584
2585         for (i = 0; i < qdev->num_large_buffers; i++) {
2586                 lrg_buf_cb = &qdev->lrg_buf[i];
2587                 if (lrg_buf_cb->skb) {
2588                         dev_kfree_skb(lrg_buf_cb->skb);
2589                         pci_unmap_single(qdev->pdev,
2590                                          pci_unmap_addr(lrg_buf_cb, mapaddr),
2591                                          pci_unmap_len(lrg_buf_cb, maplen),
2592                                          PCI_DMA_FROMDEVICE);
2593                         memset(lrg_buf_cb, 0, sizeof(struct ql_rcv_buf_cb));
2594                 } else {
2595                         break;
2596                 }
2597         }
2598 }
2599
2600 static void ql_init_large_buffers(struct ql3_adapter *qdev)
2601 {
2602         int i;
2603         struct ql_rcv_buf_cb *lrg_buf_cb;
2604         struct bufq_addr_element *buf_addr_ele = qdev->lrg_buf_q_virt_addr;
2605
2606         for (i = 0; i < qdev->num_large_buffers; i++) {
2607                 lrg_buf_cb = &qdev->lrg_buf[i];
2608                 buf_addr_ele->addr_high = lrg_buf_cb->buf_phy_addr_high;
2609                 buf_addr_ele->addr_low = lrg_buf_cb->buf_phy_addr_low;
2610                 buf_addr_ele++;
2611         }
2612         qdev->lrg_buf_index = 0;
2613         qdev->lrg_buf_skb_check = 0;
2614 }
2615
2616 static int ql_alloc_large_buffers(struct ql3_adapter *qdev)
2617 {
2618         int i;
2619         struct ql_rcv_buf_cb *lrg_buf_cb;
2620         struct sk_buff *skb;
2621         dma_addr_t map;
2622         int err;
2623
2624         for (i = 0; i < qdev->num_large_buffers; i++) {
2625                 skb = netdev_alloc_skb(qdev->ndev,
2626                                        qdev->lrg_buffer_len);
2627                 if (unlikely(!skb)) {
2628                         /* Better luck next round */
2629                         printk(KERN_ERR PFX
2630                                "%s: large buff alloc failed, "
2631                                "for %d bytes at index %d.\n",
2632                                qdev->ndev->name,
2633                                qdev->lrg_buffer_len * 2, i);
2634                         ql_free_large_buffers(qdev);
2635                         return -ENOMEM;
2636                 } else {
2637
2638                         lrg_buf_cb = &qdev->lrg_buf[i];
2639                         memset(lrg_buf_cb, 0, sizeof(struct ql_rcv_buf_cb));
2640                         lrg_buf_cb->index = i;
2641                         lrg_buf_cb->skb = skb;
2642                         /*
2643                          * We save some space to copy the ethhdr from first
2644                          * buffer
2645                          */
2646                         skb_reserve(skb, QL_HEADER_SPACE);
2647                         map = pci_map_single(qdev->pdev,
2648                                              skb->data,
2649                                              qdev->lrg_buffer_len -
2650                                              QL_HEADER_SPACE,
2651                                              PCI_DMA_FROMDEVICE);
2652
2653                         err = pci_dma_mapping_error(map);
2654                         if(err) {
2655                                 printk(KERN_ERR "%s: PCI mapping failed with error: %d\n",
2656                                        qdev->ndev->name, err);
2657                                 ql_free_large_buffers(qdev);
2658                                 return -ENOMEM;
2659                         }
2660
2661                         pci_unmap_addr_set(lrg_buf_cb, mapaddr, map);
2662                         pci_unmap_len_set(lrg_buf_cb, maplen,
2663                                           qdev->lrg_buffer_len -
2664                                           QL_HEADER_SPACE);
2665                         lrg_buf_cb->buf_phy_addr_low =
2666                             cpu_to_le32(LS_64BITS(map));
2667                         lrg_buf_cb->buf_phy_addr_high =
2668                             cpu_to_le32(MS_64BITS(map));
2669                 }
2670         }
2671         return 0;
2672 }
2673
2674 static void ql_free_send_free_list(struct ql3_adapter *qdev)
2675 {
2676         struct ql_tx_buf_cb *tx_cb;
2677         int i;
2678
2679         tx_cb = &qdev->tx_buf[0];
2680         for (i = 0; i < NUM_REQ_Q_ENTRIES; i++) {
2681                 if (tx_cb->oal) {
2682                         kfree(tx_cb->oal);
2683                         tx_cb->oal = NULL;
2684                 }
2685                 tx_cb++;
2686         }
2687 }
2688
2689 static int ql_create_send_free_list(struct ql3_adapter *qdev)
2690 {
2691         struct ql_tx_buf_cb *tx_cb;
2692         int i;
2693         struct ob_mac_iocb_req *req_q_curr =
2694                                         qdev->req_q_virt_addr;
2695
2696         /* Create free list of transmit buffers */
2697         for (i = 0; i < NUM_REQ_Q_ENTRIES; i++) {
2698
2699                 tx_cb = &qdev->tx_buf[i];
2700                 tx_cb->skb = NULL;
2701                 tx_cb->queue_entry = req_q_curr;
2702                 req_q_curr++;
2703                 tx_cb->oal = kmalloc(512, GFP_KERNEL);
2704                 if (tx_cb->oal == NULL)
2705                         return -1;
2706         }
2707         return 0;
2708 }
2709
2710 static int ql_alloc_mem_resources(struct ql3_adapter *qdev)
2711 {
2712         if (qdev->ndev->mtu == NORMAL_MTU_SIZE) {
2713                 qdev->num_lbufq_entries = NUM_LBUFQ_ENTRIES;
2714                 qdev->lrg_buffer_len = NORMAL_MTU_SIZE;
2715         }
2716         else if (qdev->ndev->mtu == JUMBO_MTU_SIZE) {
2717                 /*
2718                  * Bigger buffers, so less of them.
2719                  */
2720                 qdev->num_lbufq_entries = JUMBO_NUM_LBUFQ_ENTRIES;
2721                 qdev->lrg_buffer_len = JUMBO_MTU_SIZE;
2722         } else {
2723                 printk(KERN_ERR PFX
2724                        "%s: Invalid mtu size.  Only 1500 and 9000 are accepted.\n",
2725                        qdev->ndev->name);
2726                 return -ENOMEM;
2727         }
2728         qdev->num_large_buffers = qdev->num_lbufq_entries * QL_ADDR_ELE_PER_BUFQ_ENTRY;
2729         qdev->lrg_buffer_len += VLAN_ETH_HLEN + VLAN_ID_LEN + QL_HEADER_SPACE;
2730         qdev->max_frame_size =
2731             (qdev->lrg_buffer_len - QL_HEADER_SPACE) + ETHERNET_CRC_SIZE;
2732
2733         /*
2734          * First allocate a page of shared memory and use it for shadow
2735          * locations of Network Request Queue Consumer Address Register and
2736          * Network Completion Queue Producer Index Register
2737          */
2738         qdev->shadow_reg_virt_addr =
2739             pci_alloc_consistent(qdev->pdev,
2740                                  PAGE_SIZE, &qdev->shadow_reg_phy_addr);
2741
2742         if (qdev->shadow_reg_virt_addr != NULL) {
2743                 qdev->preq_consumer_index = (u16 *) qdev->shadow_reg_virt_addr;
2744                 qdev->req_consumer_index_phy_addr_high =
2745                     MS_64BITS(qdev->shadow_reg_phy_addr);
2746                 qdev->req_consumer_index_phy_addr_low =
2747                     LS_64BITS(qdev->shadow_reg_phy_addr);
2748
2749                 qdev->prsp_producer_index =
2750                     (u32 *) (((u8 *) qdev->preq_consumer_index) + 8);
2751                 qdev->rsp_producer_index_phy_addr_high =
2752                     qdev->req_consumer_index_phy_addr_high;
2753                 qdev->rsp_producer_index_phy_addr_low =
2754                     qdev->req_consumer_index_phy_addr_low + 8;
2755         } else {
2756                 printk(KERN_ERR PFX
2757                        "%s: shadowReg Alloc failed.\n", qdev->ndev->name);
2758                 return -ENOMEM;
2759         }
2760
2761         if (ql_alloc_net_req_rsp_queues(qdev) != 0) {
2762                 printk(KERN_ERR PFX
2763                        "%s: ql_alloc_net_req_rsp_queues failed.\n",
2764                        qdev->ndev->name);
2765                 goto err_req_rsp;
2766         }
2767
2768         if (ql_alloc_buffer_queues(qdev) != 0) {
2769                 printk(KERN_ERR PFX
2770                        "%s: ql_alloc_buffer_queues failed.\n",
2771                        qdev->ndev->name);
2772                 goto err_buffer_queues;
2773         }
2774
2775         if (ql_alloc_small_buffers(qdev) != 0) {
2776                 printk(KERN_ERR PFX
2777                        "%s: ql_alloc_small_buffers failed\n", qdev->ndev->name);
2778                 goto err_small_buffers;
2779         }
2780
2781         if (ql_alloc_large_buffers(qdev) != 0) {
2782                 printk(KERN_ERR PFX
2783                        "%s: ql_alloc_large_buffers failed\n", qdev->ndev->name);
2784                 goto err_small_buffers;
2785         }
2786
2787         /* Initialize the large buffer queue. */
2788         ql_init_large_buffers(qdev);
2789         if (ql_create_send_free_list(qdev))
2790                 goto err_free_list;
2791
2792         qdev->rsp_current = qdev->rsp_q_virt_addr;
2793
2794         return 0;
2795 err_free_list:
2796         ql_free_send_free_list(qdev);
2797 err_small_buffers:
2798         ql_free_buffer_queues(qdev);
2799 err_buffer_queues:
2800         ql_free_net_req_rsp_queues(qdev);
2801 err_req_rsp:
2802         pci_free_consistent(qdev->pdev,
2803                             PAGE_SIZE,
2804                             qdev->shadow_reg_virt_addr,
2805                             qdev->shadow_reg_phy_addr);
2806
2807         return -ENOMEM;
2808 }
2809
2810 static void ql_free_mem_resources(struct ql3_adapter *qdev)
2811 {
2812         ql_free_send_free_list(qdev);
2813         ql_free_large_buffers(qdev);
2814         ql_free_small_buffers(qdev);
2815         ql_free_buffer_queues(qdev);
2816         ql_free_net_req_rsp_queues(qdev);
2817         if (qdev->shadow_reg_virt_addr != NULL) {
2818                 pci_free_consistent(qdev->pdev,
2819                                     PAGE_SIZE,
2820                                     qdev->shadow_reg_virt_addr,
2821                                     qdev->shadow_reg_phy_addr);
2822                 qdev->shadow_reg_virt_addr = NULL;
2823         }
2824 }
2825
2826 static int ql_init_misc_registers(struct ql3_adapter *qdev)
2827 {
2828         struct ql3xxx_local_ram_registers __iomem *local_ram =
2829             (void __iomem *)qdev->mem_map_registers;
2830
2831         if(ql_sem_spinlock(qdev, QL_DDR_RAM_SEM_MASK,
2832                         (QL_RESOURCE_BITS_BASE_CODE | (qdev->mac_index) *
2833                          2) << 4))
2834                 return -1;
2835
2836         ql_write_page2_reg(qdev,
2837                            &local_ram->bufletSize, qdev->nvram_data.bufletSize);
2838
2839         ql_write_page2_reg(qdev,
2840                            &local_ram->maxBufletCount,
2841                            qdev->nvram_data.bufletCount);
2842
2843         ql_write_page2_reg(qdev,
2844                            &local_ram->freeBufletThresholdLow,
2845                            (qdev->nvram_data.tcpWindowThreshold25 << 16) |
2846                            (qdev->nvram_data.tcpWindowThreshold0));
2847
2848         ql_write_page2_reg(qdev,
2849                            &local_ram->freeBufletThresholdHigh,
2850                            qdev->nvram_data.tcpWindowThreshold50);
2851
2852         ql_write_page2_reg(qdev,
2853                            &local_ram->ipHashTableBase,
2854                            (qdev->nvram_data.ipHashTableBaseHi << 16) |
2855                            qdev->nvram_data.ipHashTableBaseLo);
2856         ql_write_page2_reg(qdev,
2857                            &local_ram->ipHashTableCount,
2858                            qdev->nvram_data.ipHashTableSize);
2859         ql_write_page2_reg(qdev,
2860                            &local_ram->tcpHashTableBase,
2861                            (qdev->nvram_data.tcpHashTableBaseHi << 16) |
2862                            qdev->nvram_data.tcpHashTableBaseLo);
2863         ql_write_page2_reg(qdev,
2864                            &local_ram->tcpHashTableCount,
2865                            qdev->nvram_data.tcpHashTableSize);
2866         ql_write_page2_reg(qdev,
2867                            &local_ram->ncbBase,
2868                            (qdev->nvram_data.ncbTableBaseHi << 16) |
2869                            qdev->nvram_data.ncbTableBaseLo);
2870         ql_write_page2_reg(qdev,
2871                            &local_ram->maxNcbCount,
2872                            qdev->nvram_data.ncbTableSize);
2873         ql_write_page2_reg(qdev,
2874                            &local_ram->drbBase,
2875                            (qdev->nvram_data.drbTableBaseHi << 16) |
2876                            qdev->nvram_data.drbTableBaseLo);
2877         ql_write_page2_reg(qdev,
2878                            &local_ram->maxDrbCount,
2879                            qdev->nvram_data.drbTableSize);
2880         ql_sem_unlock(qdev, QL_DDR_RAM_SEM_MASK);
2881         return 0;
2882 }
2883
2884 static int ql_adapter_initialize(struct ql3_adapter *qdev)
2885 {
2886         u32 value;
2887         struct ql3xxx_port_registers __iomem *port_regs = qdev->mem_map_registers;
2888         struct ql3xxx_host_memory_registers __iomem *hmem_regs =
2889                                                 (void __iomem *)port_regs;
2890         u32 delay = 10;
2891         int status = 0;
2892
2893         if(ql_mii_setup(qdev))
2894                 return -1;
2895
2896         /* Bring out PHY out of reset */
2897         ql_write_common_reg(qdev, &port_regs->CommonRegs.serialPortInterfaceReg,
2898                             (ISP_SERIAL_PORT_IF_WE |
2899                              (ISP_SERIAL_PORT_IF_WE << 16)));
2900
2901         qdev->port_link_state = LS_DOWN;
2902         netif_carrier_off(qdev->ndev);
2903
2904         /* V2 chip fix for ARS-39168. */
2905         ql_write_common_reg(qdev, &port_regs->CommonRegs.serialPortInterfaceReg,
2906                             (ISP_SERIAL_PORT_IF_SDE |
2907                              (ISP_SERIAL_PORT_IF_SDE << 16)));
2908
2909         /* Request Queue Registers */
2910         *((u32 *) (qdev->preq_consumer_index)) = 0;
2911         atomic_set(&qdev->tx_count,NUM_REQ_Q_ENTRIES);
2912         qdev->req_producer_index = 0;
2913
2914         ql_write_page1_reg(qdev,
2915                            &hmem_regs->reqConsumerIndexAddrHigh,
2916                            qdev->req_consumer_index_phy_addr_high);
2917         ql_write_page1_reg(qdev,
2918                            &hmem_regs->reqConsumerIndexAddrLow,
2919                            qdev->req_consumer_index_phy_addr_low);
2920
2921         ql_write_page1_reg(qdev,
2922                            &hmem_regs->reqBaseAddrHigh,
2923                            MS_64BITS(qdev->req_q_phy_addr));
2924         ql_write_page1_reg(qdev,
2925                            &hmem_regs->reqBaseAddrLow,
2926                            LS_64BITS(qdev->req_q_phy_addr));
2927         ql_write_page1_reg(qdev, &hmem_regs->reqLength, NUM_REQ_Q_ENTRIES);
2928
2929         /* Response Queue Registers */
2930         *((u16 *) (qdev->prsp_producer_index)) = 0;
2931         qdev->rsp_consumer_index = 0;
2932         qdev->rsp_current = qdev->rsp_q_virt_addr;
2933
2934         ql_write_page1_reg(qdev,
2935                            &hmem_regs->rspProducerIndexAddrHigh,
2936                            qdev->rsp_producer_index_phy_addr_high);
2937
2938         ql_write_page1_reg(qdev,
2939                            &hmem_regs->rspProducerIndexAddrLow,
2940                            qdev->rsp_producer_index_phy_addr_low);
2941
2942         ql_write_page1_reg(qdev,
2943                            &hmem_regs->rspBaseAddrHigh,
2944                            MS_64BITS(qdev->rsp_q_phy_addr));
2945
2946         ql_write_page1_reg(qdev,
2947                            &hmem_regs->rspBaseAddrLow,
2948                            LS_64BITS(qdev->rsp_q_phy_addr));
2949
2950         ql_write_page1_reg(qdev, &hmem_regs->rspLength, NUM_RSP_Q_ENTRIES);
2951
2952         /* Large Buffer Queue */
2953         ql_write_page1_reg(qdev,
2954                            &hmem_regs->rxLargeQBaseAddrHigh,
2955                            MS_64BITS(qdev->lrg_buf_q_phy_addr));
2956
2957         ql_write_page1_reg(qdev,
2958                            &hmem_regs->rxLargeQBaseAddrLow,
2959                            LS_64BITS(qdev->lrg_buf_q_phy_addr));
2960
2961         ql_write_page1_reg(qdev, &hmem_regs->rxLargeQLength, qdev->num_lbufq_entries);
2962
2963         ql_write_page1_reg(qdev,
2964                            &hmem_regs->rxLargeBufferLength,
2965                            qdev->lrg_buffer_len);
2966
2967         /* Small Buffer Queue */
2968         ql_write_page1_reg(qdev,
2969                            &hmem_regs->rxSmallQBaseAddrHigh,
2970                            MS_64BITS(qdev->small_buf_q_phy_addr));
2971
2972         ql_write_page1_reg(qdev,
2973                            &hmem_regs->rxSmallQBaseAddrLow,
2974                            LS_64BITS(qdev->small_buf_q_phy_addr));
2975
2976         ql_write_page1_reg(qdev, &hmem_regs->rxSmallQLength, NUM_SBUFQ_ENTRIES);
2977         ql_write_page1_reg(qdev,
2978                            &hmem_regs->rxSmallBufferLength,
2979                            QL_SMALL_BUFFER_SIZE);
2980
2981         qdev->small_buf_q_producer_index = NUM_SBUFQ_ENTRIES - 1;
2982         qdev->small_buf_release_cnt = 8;
2983         qdev->lrg_buf_q_producer_index = qdev->num_lbufq_entries - 1;
2984         qdev->lrg_buf_release_cnt = 8;
2985         qdev->lrg_buf_next_free =
2986             (struct bufq_addr_element *)qdev->lrg_buf_q_virt_addr;
2987         qdev->small_buf_index = 0;
2988         qdev->lrg_buf_index = 0;
2989         qdev->lrg_buf_free_count = 0;
2990         qdev->lrg_buf_free_head = NULL;
2991         qdev->lrg_buf_free_tail = NULL;
2992
2993         ql_write_common_reg(qdev,
2994                             &port_regs->CommonRegs.
2995                             rxSmallQProducerIndex,
2996                             qdev->small_buf_q_producer_index);
2997         ql_write_common_reg(qdev,
2998                             &port_regs->CommonRegs.
2999                             rxLargeQProducerIndex,
3000                             qdev->lrg_buf_q_producer_index);
3001
3002         /*
3003          * Find out if the chip has already been initialized.  If it has, then
3004          * we skip some of the initialization.
3005          */
3006         clear_bit(QL_LINK_MASTER, &qdev->flags);
3007         value = ql_read_page0_reg(qdev, &port_regs->portStatus);
3008         if ((value & PORT_STATUS_IC) == 0) {
3009
3010                 /* Chip has not been configured yet, so let it rip. */
3011                 if(ql_init_misc_registers(qdev)) {
3012                         status = -1;
3013                         goto out;
3014                 }
3015
3016                 if (qdev->mac_index)
3017                         ql_write_page0_reg(qdev,
3018                                            &port_regs->mac1MaxFrameLengthReg,
3019                                            qdev->max_frame_size);
3020                 else
3021                         ql_write_page0_reg(qdev,
3022                                            &port_regs->mac0MaxFrameLengthReg,
3023                                            qdev->max_frame_size);
3024
3025                 value = qdev->nvram_data.tcpMaxWindowSize;
3026                 ql_write_page0_reg(qdev, &port_regs->tcpMaxWindow, value);
3027
3028                 value = (0xFFFF << 16) | qdev->nvram_data.extHwConfig;
3029
3030                 if(ql_sem_spinlock(qdev, QL_FLASH_SEM_MASK,
3031                                 (QL_RESOURCE_BITS_BASE_CODE | (qdev->mac_index)
3032                                  * 2) << 13)) {
3033                         status = -1;
3034                         goto out;
3035                 }
3036                 ql_write_page0_reg(qdev, &port_regs->ExternalHWConfig, value);
3037                 ql_write_page0_reg(qdev, &port_regs->InternalChipConfig,
3038                                    (((INTERNAL_CHIP_SD | INTERNAL_CHIP_WE) <<
3039                                      16) | (INTERNAL_CHIP_SD |
3040                                             INTERNAL_CHIP_WE)));
3041                 ql_sem_unlock(qdev, QL_FLASH_SEM_MASK);
3042         }
3043
3044
3045         if(ql_sem_spinlock(qdev, QL_PHY_GIO_SEM_MASK,
3046                         (QL_RESOURCE_BITS_BASE_CODE | (qdev->mac_index) *
3047                          2) << 7)) {
3048                 status = -1;
3049                 goto out;
3050         }
3051
3052         ql_init_scan_mode(qdev);
3053         ql_get_phy_owner(qdev);
3054
3055         /* Load the MAC Configuration */
3056
3057         /* Program lower 32 bits of the MAC address */
3058         ql_write_page0_reg(qdev, &port_regs->macAddrIndirectPtrReg,
3059                            (MAC_ADDR_INDIRECT_PTR_REG_RP_MASK << 16));
3060         ql_write_page0_reg(qdev, &port_regs->macAddrDataReg,
3061                            ((qdev->ndev->dev_addr[2] << 24)
3062                             | (qdev->ndev->dev_addr[3] << 16)
3063                             | (qdev->ndev->dev_addr[4] << 8)
3064                             | qdev->ndev->dev_addr[5]));
3065
3066         /* Program top 16 bits of the MAC address */
3067         ql_write_page0_reg(qdev, &port_regs->macAddrIndirectPtrReg,
3068                            ((MAC_ADDR_INDIRECT_PTR_REG_RP_MASK << 16) | 1));
3069         ql_write_page0_reg(qdev, &port_regs->macAddrDataReg,
3070                            ((qdev->ndev->dev_addr[0] << 8)
3071                             | qdev->ndev->dev_addr[1]));
3072
3073         /* Enable Primary MAC */
3074         ql_write_page0_reg(qdev, &port_regs->macAddrIndirectPtrReg,
3075                            ((MAC_ADDR_INDIRECT_PTR_REG_PE << 16) |
3076                             MAC_ADDR_INDIRECT_PTR_REG_PE));
3077
3078         /* Clear Primary and Secondary IP addresses */
3079         ql_write_page0_reg(qdev, &port_regs->ipAddrIndexReg,
3080                            ((IP_ADDR_INDEX_REG_MASK << 16) |
3081                             (qdev->mac_index << 2)));
3082         ql_write_page0_reg(qdev, &port_regs->ipAddrDataReg, 0);
3083
3084         ql_write_page0_reg(qdev, &port_regs->ipAddrIndexReg,
3085                            ((IP_ADDR_INDEX_REG_MASK << 16) |
3086                             ((qdev->mac_index << 2) + 1)));
3087         ql_write_page0_reg(qdev, &port_regs->ipAddrDataReg, 0);
3088
3089         ql_sem_unlock(qdev, QL_PHY_GIO_SEM_MASK);
3090
3091         /* Indicate Configuration Complete */
3092         ql_write_page0_reg(qdev,
3093                            &port_regs->portControl,
3094                            ((PORT_CONTROL_CC << 16) | PORT_CONTROL_CC));
3095
3096         do {
3097                 value = ql_read_page0_reg(qdev, &port_regs->portStatus);
3098                 if (value & PORT_STATUS_IC)
3099                         break;
3100                 msleep(500);
3101         } while (--delay);
3102
3103         if (delay == 0) {
3104                 printk(KERN_ERR PFX
3105                        "%s: Hw Initialization timeout.\n", qdev->ndev->name);
3106                 status = -1;
3107                 goto out;
3108         }
3109
3110         /* Enable Ethernet Function */
3111         if (qdev->device_id == QL3032_DEVICE_ID) {
3112                 value =
3113                     (QL3032_PORT_CONTROL_EF | QL3032_PORT_CONTROL_KIE |
3114                      QL3032_PORT_CONTROL_EIv6 | QL3032_PORT_CONTROL_EIv4);
3115                 ql_write_page0_reg(qdev, &port_regs->functionControl,
3116                                    ((value << 16) | value));
3117         } else {
3118                 value =
3119                     (PORT_CONTROL_EF | PORT_CONTROL_ET | PORT_CONTROL_EI |
3120                      PORT_CONTROL_HH);
3121                 ql_write_page0_reg(qdev, &port_regs->portControl,
3122                                    ((value << 16) | value));
3123         }
3124
3125
3126 out:
3127         return status;
3128 }
3129
3130 /*
3131  * Caller holds hw_lock.
3132  */
3133 static int ql_adapter_reset(struct ql3_adapter *qdev)
3134 {
3135         struct ql3xxx_port_registers __iomem *port_regs = qdev->mem_map_registers;
3136         int status = 0;
3137         u16 value;
3138         int max_wait_time;
3139
3140         set_bit(QL_RESET_ACTIVE, &qdev->flags);
3141         clear_bit(QL_RESET_DONE, &qdev->flags);
3142
3143         /*
3144          * Issue soft reset to chip.
3145          */
3146         printk(KERN_DEBUG PFX
3147                "%s: Issue soft reset to chip.\n",
3148                qdev->ndev->name);
3149         ql_write_common_reg(qdev,
3150                             &port_regs->CommonRegs.ispControlStatus,
3151                             ((ISP_CONTROL_SR << 16) | ISP_CONTROL_SR));
3152
3153         /* Wait 3 seconds for reset to complete. */
3154         printk(KERN_DEBUG PFX
3155                "%s: Wait 10 milliseconds for reset to complete.\n",
3156                qdev->ndev->name);
3157
3158         /* Wait until the firmware tells us the Soft Reset is done */
3159         max_wait_time = 5;
3160         do {
3161                 value =
3162                     ql_read_common_reg(qdev,
3163                                        &port_regs->CommonRegs.ispControlStatus);
3164                 if ((value & ISP_CONTROL_SR) == 0)
3165                         break;
3166
3167                 ssleep(1);
3168         } while ((--max_wait_time));
3169
3170         /*
3171          * Also, make sure that the Network Reset Interrupt bit has been
3172          * cleared after the soft reset has taken place.
3173          */
3174         value =
3175             ql_read_common_reg(qdev, &port_regs->CommonRegs.ispControlStatus);
3176         if (value & ISP_CONTROL_RI) {
3177                 printk(KERN_DEBUG PFX
3178                        "ql_adapter_reset: clearing RI after reset.\n");
3179                 ql_write_common_reg(qdev,
3180                                     &port_regs->CommonRegs.
3181                                     ispControlStatus,
3182                                     ((ISP_CONTROL_RI << 16) | ISP_CONTROL_RI));
3183         }
3184
3185         if (max_wait_time == 0) {
3186                 /* Issue Force Soft Reset */
3187                 ql_write_common_reg(qdev,
3188                                     &port_regs->CommonRegs.
3189                                     ispControlStatus,
3190                                     ((ISP_CONTROL_FSR << 16) |
3191                                      ISP_CONTROL_FSR));
3192                 /*
3193                  * Wait until the firmware tells us the Force Soft Reset is
3194                  * done
3195                  */
3196                 max_wait_time = 5;
3197                 do {
3198                         value =
3199                             ql_read_common_reg(qdev,
3200                                                &port_regs->CommonRegs.
3201                                                ispControlStatus);
3202                         if ((value & ISP_CONTROL_FSR) == 0) {
3203                                 break;
3204                         }
3205                         ssleep(1);
3206                 } while ((--max_wait_time));
3207         }
3208         if (max_wait_time == 0)
3209                 status = 1;
3210
3211         clear_bit(QL_RESET_ACTIVE, &qdev->flags);
3212         set_bit(QL_RESET_DONE, &qdev->flags);
3213         return status;
3214 }
3215
3216 static void ql_set_mac_info(struct ql3_adapter *qdev)
3217 {
3218         struct ql3xxx_port_registers __iomem *port_regs = qdev->mem_map_registers;
3219         u32 value, port_status;
3220         u8 func_number;
3221
3222         /* Get the function number */
3223         value =
3224             ql_read_common_reg_l(qdev, &port_regs->CommonRegs.ispControlStatus);
3225         func_number = (u8) ((value >> 4) & OPCODE_FUNC_ID_MASK);
3226         port_status = ql_read_page0_reg(qdev, &port_regs->portStatus);
3227         switch (value & ISP_CONTROL_FN_MASK) {
3228         case ISP_CONTROL_FN0_NET:
3229                 qdev->mac_index = 0;
3230                 qdev->mac_ob_opcode = OUTBOUND_MAC_IOCB | func_number;
3231                 qdev->tcp_ob_opcode = OUTBOUND_TCP_IOCB | func_number;
3232                 qdev->update_ob_opcode = UPDATE_NCB_IOCB | func_number;
3233                 qdev->mb_bit_mask = FN0_MA_BITS_MASK;
3234                 qdev->PHYAddr = PORT0_PHY_ADDRESS;
3235                 if (port_status & PORT_STATUS_SM0)
3236                         set_bit(QL_LINK_OPTICAL,&qdev->flags);
3237                 else
3238                         clear_bit(QL_LINK_OPTICAL,&qdev->flags);
3239                 break;
3240
3241         case ISP_CONTROL_FN1_NET:
3242                 qdev->mac_index = 1;
3243                 qdev->mac_ob_opcode = OUTBOUND_MAC_IOCB | func_number;
3244                 qdev->tcp_ob_opcode = OUTBOUND_TCP_IOCB | func_number;
3245                 qdev->update_ob_opcode = UPDATE_NCB_IOCB | func_number;
3246                 qdev->mb_bit_mask = FN1_MA_BITS_MASK;
3247                 qdev->PHYAddr = PORT1_PHY_ADDRESS;
3248                 if (port_status & PORT_STATUS_SM1)
3249                         set_bit(QL_LINK_OPTICAL,&qdev->flags);
3250                 else
3251                         clear_bit(QL_LINK_OPTICAL,&qdev->flags);
3252                 break;
3253
3254         case ISP_CONTROL_FN0_SCSI:
3255         case ISP_CONTROL_FN1_SCSI:
3256         default:
3257                 printk(KERN_DEBUG PFX
3258                        "%s: Invalid function number, ispControlStatus = 0x%x\n",
3259                        qdev->ndev->name,value);
3260                 break;
3261         }
3262         qdev->numPorts = qdev->nvram_data.numPorts;
3263 }
3264
3265 static void ql_display_dev_info(struct net_device *ndev)
3266 {
3267         struct ql3_adapter *qdev = (struct ql3_adapter *)netdev_priv(ndev);
3268         struct pci_dev *pdev = qdev->pdev;
3269
3270         printk(KERN_INFO PFX
3271                "\n%s Adapter %d RevisionID %d found %s on PCI slot %d.\n",
3272                DRV_NAME, qdev->index, qdev->chip_rev_id,
3273                (qdev->device_id == QL3032_DEVICE_ID) ? "QLA3032" : "QLA3022",
3274                qdev->pci_slot);
3275         printk(KERN_INFO PFX
3276                "%s Interface.\n",
3277                test_bit(QL_LINK_OPTICAL,&qdev->flags) ? "OPTICAL" : "COPPER");
3278
3279         /*
3280          * Print PCI bus width/type.
3281          */
3282         printk(KERN_INFO PFX
3283                "Bus interface is %s %s.\n",
3284                ((qdev->pci_width == 64) ? "64-bit" : "32-bit"),
3285                ((qdev->pci_x) ? "PCI-X" : "PCI"));
3286
3287         printk(KERN_INFO PFX
3288                "mem  IO base address adjusted = 0x%p\n",
3289                qdev->mem_map_registers);
3290         printk(KERN_INFO PFX "Interrupt number = %d\n", pdev->irq);
3291
3292         if (netif_msg_probe(qdev))
3293                 printk(KERN_INFO PFX
3294                        "%s: MAC address %02x:%02x:%02x:%02x:%02x:%02x\n",
3295                        ndev->name, ndev->dev_addr[0], ndev->dev_addr[1],
3296                        ndev->dev_addr[2], ndev->dev_addr[3], ndev->dev_addr[4],
3297                        ndev->dev_addr[5]);
3298 }
3299
3300 static int ql_adapter_down(struct ql3_adapter *qdev, int do_reset)
3301 {
3302         struct net_device *ndev = qdev->ndev;
3303         int retval = 0;
3304
3305         netif_stop_queue(ndev);
3306         netif_carrier_off(ndev);
3307
3308         clear_bit(QL_ADAPTER_UP,&qdev->flags);
3309         clear_bit(QL_LINK_MASTER,&qdev->flags);
3310
3311         ql_disable_interrupts(qdev);
3312
3313         free_irq(qdev->pdev->irq, ndev);
3314
3315         if (qdev->msi && test_bit(QL_MSI_ENABLED,&qdev->flags)) {
3316                 printk(KERN_INFO PFX
3317                        "%s: calling pci_disable_msi().\n", qdev->ndev->name);
3318                 clear_bit(QL_MSI_ENABLED,&qdev->flags);
3319                 pci_disable_msi(qdev->pdev);
3320         }
3321
3322         del_timer_sync(&qdev->adapter_timer);
3323
3324         netif_poll_disable(ndev);
3325
3326         if (do_reset) {
3327                 int soft_reset;
3328                 unsigned long hw_flags;
3329
3330                 spin_lock_irqsave(&qdev->hw_lock, hw_flags);
3331                 if (ql_wait_for_drvr_lock(qdev)) {
3332                         if ((soft_reset = ql_adapter_reset(qdev))) {
3333                                 printk(KERN_ERR PFX
3334                                        "%s: ql_adapter_reset(%d) FAILED!\n",
3335                                        ndev->name, qdev->index);
3336                         }
3337                         printk(KERN_ERR PFX
3338                                 "%s: Releaseing driver lock via chip reset.\n",ndev->name);
3339                 } else {
3340                         printk(KERN_ERR PFX
3341                                "%s: Could not acquire driver lock to do "
3342                                "reset!\n", ndev->name);
3343                         retval = -1;
3344                 }
3345                 spin_unlock_irqrestore(&qdev->hw_lock, hw_flags);
3346         }
3347         ql_free_mem_resources(qdev);
3348         return retval;
3349 }
3350
3351 static int ql_adapter_up(struct ql3_adapter *qdev)
3352 {
3353         struct net_device *ndev = qdev->ndev;
3354         int err;
3355         unsigned long irq_flags = IRQF_SAMPLE_RANDOM | IRQF_SHARED;
3356         unsigned long hw_flags;
3357
3358         if (ql_alloc_mem_resources(qdev)) {
3359                 printk(KERN_ERR PFX
3360                        "%s Unable to  allocate buffers.\n", ndev->name);
3361                 return -ENOMEM;
3362         }
3363
3364         if (qdev->msi) {
3365                 if (pci_enable_msi(qdev->pdev)) {
3366                         printk(KERN_ERR PFX
3367                                "%s: User requested MSI, but MSI failed to "
3368                                "initialize.  Continuing without MSI.\n",
3369                                qdev->ndev->name);
3370                         qdev->msi = 0;
3371                 } else {
3372                         printk(KERN_INFO PFX "%s: MSI Enabled...\n", qdev->ndev->name);
3373                         set_bit(QL_MSI_ENABLED,&qdev->flags);
3374                         irq_flags &= ~IRQF_SHARED;
3375                 }
3376         }
3377
3378         if ((err = request_irq(qdev->pdev->irq,
3379                                ql3xxx_isr,
3380                                irq_flags, ndev->name, ndev))) {
3381                 printk(KERN_ERR PFX
3382                        "%s: Failed to reserve interrupt %d already in use.\n",
3383                        ndev->name, qdev->pdev->irq);
3384                 goto err_irq;
3385         }
3386
3387         spin_lock_irqsave(&qdev->hw_lock, hw_flags);
3388
3389         if ((err = ql_wait_for_drvr_lock(qdev))) {
3390                 if ((err = ql_adapter_initialize(qdev))) {
3391                         printk(KERN_ERR PFX
3392                                "%s: Unable to initialize adapter.\n",
3393                                ndev->name);
3394                         goto err_init;
3395                 }
3396                 printk(KERN_ERR PFX
3397                                 "%s: Releaseing driver lock.\n",ndev->name);
3398                 ql_sem_unlock(qdev, QL_DRVR_SEM_MASK);
3399         } else {
3400                 printk(KERN_ERR PFX
3401                        "%s: Could not aquire driver lock.\n",
3402                        ndev->name);
3403                 goto err_lock;
3404         }
3405
3406         spin_unlock_irqrestore(&qdev->hw_lock, hw_flags);
3407
3408         set_bit(QL_ADAPTER_UP,&qdev->flags);
3409
3410         mod_timer(&qdev->adapter_timer, jiffies + HZ * 1);
3411
3412         netif_poll_enable(ndev);
3413         ql_enable_interrupts(qdev);
3414         return 0;
3415
3416 err_init:
3417         ql_sem_unlock(qdev, QL_DRVR_SEM_MASK);
3418 err_lock:
3419         spin_unlock_irqrestore(&qdev->hw_lock, hw_flags);
3420         free_irq(qdev->pdev->irq, ndev);
3421 err_irq:
3422         if (qdev->msi && test_bit(QL_MSI_ENABLED,&qdev->flags)) {
3423                 printk(KERN_INFO PFX
3424                        "%s: calling pci_disable_msi().\n",
3425                        qdev->ndev->name);
3426                 clear_bit(QL_MSI_ENABLED,&qdev->flags);
3427                 pci_disable_msi(qdev->pdev);
3428         }
3429         return err;
3430 }
3431
3432 static int ql_cycle_adapter(struct ql3_adapter *qdev, int reset)
3433 {
3434         if( ql_adapter_down(qdev,reset) || ql_adapter_up(qdev)) {
3435                 printk(KERN_ERR PFX
3436                                 "%s: Driver up/down cycle failed, "
3437                                 "closing device\n",qdev->ndev->name);
3438                 dev_close(qdev->ndev);
3439                 return -1;
3440         }
3441         return 0;
3442 }
3443
3444 static int ql3xxx_close(struct net_device *ndev)
3445 {
3446         struct ql3_adapter *qdev = netdev_priv(ndev);
3447
3448         /*
3449          * Wait for device to recover from a reset.
3450          * (Rarely happens, but possible.)
3451          */
3452         while (!test_bit(QL_ADAPTER_UP,&qdev->flags))
3453                 msleep(50);
3454
3455         ql_adapter_down(qdev,QL_DO_RESET);
3456         return 0;
3457 }
3458
3459 static int ql3xxx_open(struct net_device *ndev)
3460 {
3461         struct ql3_adapter *qdev = netdev_priv(ndev);
3462         return (ql_adapter_up(qdev));
3463 }
3464
3465 static struct net_device_stats *ql3xxx_get_stats(struct net_device *dev)
3466 {
3467         struct ql3_adapter *qdev = (struct ql3_adapter *)dev->priv;
3468         return &qdev->stats;
3469 }
3470
3471 static void ql3xxx_set_multicast_list(struct net_device *ndev)
3472 {
3473         /*
3474          * We are manually parsing the list in the net_device structure.
3475          */
3476         return;
3477 }
3478
3479 static int ql3xxx_set_mac_address(struct net_device *ndev, void *p)
3480 {
3481         struct ql3_adapter *qdev = (struct ql3_adapter *)netdev_priv(ndev);
3482         struct ql3xxx_port_registers __iomem *port_regs =
3483                         qdev->mem_map_registers;
3484         struct sockaddr *addr = p;
3485         unsigned long hw_flags;
3486
3487         if (netif_running(ndev))
3488                 return -EBUSY;
3489
3490         if (!is_valid_ether_addr(addr->sa_data))
3491                 return -EADDRNOTAVAIL;
3492
3493         memcpy(ndev->dev_addr, addr->sa_data, ndev->addr_len);
3494
3495         spin_lock_irqsave(&qdev->hw_lock, hw_flags);
3496         /* Program lower 32 bits of the MAC address */
3497         ql_write_page0_reg(qdev, &port_regs->macAddrIndirectPtrReg,
3498                            (MAC_ADDR_INDIRECT_PTR_REG_RP_MASK << 16));
3499         ql_write_page0_reg(qdev, &port_regs->macAddrDataReg,
3500                            ((ndev->dev_addr[2] << 24) | (ndev->
3501                                                          dev_addr[3] << 16) |
3502                             (ndev->dev_addr[4] << 8) | ndev->dev_addr[5]));
3503
3504         /* Program top 16 bits of the MAC address */
3505         ql_write_page0_reg(qdev, &port_regs->macAddrIndirectPtrReg,
3506                            ((MAC_ADDR_INDIRECT_PTR_REG_RP_MASK << 16) | 1));
3507         ql_write_page0_reg(qdev, &port_regs->macAddrDataReg,
3508                            ((ndev->dev_addr[0] << 8) | ndev->dev_addr[1]));
3509         spin_unlock_irqrestore(&qdev->hw_lock, hw_flags);
3510
3511         return 0;
3512 }
3513
3514 static void ql3xxx_tx_timeout(struct net_device *ndev)
3515 {
3516         struct ql3_adapter *qdev = (struct ql3_adapter *)netdev_priv(ndev);
3517
3518         printk(KERN_ERR PFX "%s: Resetting...\n", ndev->name);
3519         /*
3520          * Stop the queues, we've got a problem.
3521          */
3522         netif_stop_queue(ndev);
3523
3524         /*
3525          * Wake up the worker to process this event.
3526          */
3527         queue_delayed_work(qdev->workqueue, &qdev->tx_timeout_work, 0);
3528 }
3529
3530 static void ql_reset_work(struct work_struct *work)
3531 {
3532         struct ql3_adapter *qdev =
3533                 container_of(work, struct ql3_adapter, reset_work.work);
3534         struct net_device *ndev = qdev->ndev;
3535         u32 value;
3536         struct ql_tx_buf_cb *tx_cb;
3537         int max_wait_time, i;
3538         struct ql3xxx_port_registers __iomem *port_regs = qdev->mem_map_registers;
3539         unsigned long hw_flags;
3540
3541         if (test_bit((QL_RESET_PER_SCSI | QL_RESET_START),&qdev->flags)) {
3542                 clear_bit(QL_LINK_MASTER,&qdev->flags);
3543
3544                 /*
3545                  * Loop through the active list and return the skb.
3546                  */
3547                 for (i = 0; i < NUM_REQ_Q_ENTRIES; i++) {
3548                         int j;
3549                         tx_cb = &qdev->tx_buf[i];
3550                         if (tx_cb->skb) {
3551                                 printk(KERN_DEBUG PFX
3552                                        "%s: Freeing lost SKB.\n",
3553                                        qdev->ndev->name);
3554                                 pci_unmap_single(qdev->pdev,
3555                                          pci_unmap_addr(&tx_cb->map[0], mapaddr),
3556                                          pci_unmap_len(&tx_cb->map[0], maplen),
3557                                          PCI_DMA_TODEVICE);
3558                                 for(j=1;j<tx_cb->seg_count;j++) {
3559                                         pci_unmap_page(qdev->pdev,
3560                                                pci_unmap_addr(&tx_cb->map[j],mapaddr),
3561                                                pci_unmap_len(&tx_cb->map[j],maplen),
3562                                                PCI_DMA_TODEVICE);
3563                                 }
3564                                 dev_kfree_skb(tx_cb->skb);
3565                                 tx_cb->skb = NULL;
3566                         }
3567                 }
3568
3569                 printk(KERN_ERR PFX
3570                        "%s: Clearing NRI after reset.\n", qdev->ndev->name);
3571                 spin_lock_irqsave(&qdev->hw_lock, hw_flags);
3572                 ql_write_common_reg(qdev,
3573                                     &port_regs->CommonRegs.
3574                                     ispControlStatus,
3575                                     ((ISP_CONTROL_RI << 16) | ISP_CONTROL_RI));
3576                 /*
3577                  * Wait the for Soft Reset to Complete.
3578                  */
3579                 max_wait_time = 10;
3580                 do {
3581                         value = ql_read_common_reg(qdev,
3582                                                    &port_regs->CommonRegs.
3583
3584                                                    ispControlStatus);
3585                         if ((value & ISP_CONTROL_SR) == 0) {
3586                                 printk(KERN_DEBUG PFX
3587                                        "%s: reset completed.\n",
3588                                        qdev->ndev->name);
3589                                 break;
3590                         }
3591
3592                         if (value & ISP_CONTROL_RI) {
3593                                 printk(KERN_DEBUG PFX
3594                                        "%s: clearing NRI after reset.\n",
3595                                        qdev->ndev->name);
3596                                 ql_write_common_reg(qdev,
3597                                                     &port_regs->
3598                                                     CommonRegs.
3599                                                     ispControlStatus,
3600                                                     ((ISP_CONTROL_RI <<
3601                                                       16) | ISP_CONTROL_RI));
3602                         }
3603
3604                         ssleep(1);
3605                 } while (--max_wait_time);
3606                 spin_unlock_irqrestore(&qdev->hw_lock, hw_flags);
3607
3608                 if (value & ISP_CONTROL_SR) {
3609
3610                         /*
3611                          * Set the reset flags and clear the board again.
3612                          * Nothing else to do...
3613                          */
3614                         printk(KERN_ERR PFX
3615                                "%s: Timed out waiting for reset to "
3616                                "complete.\n", ndev->name);
3617                         printk(KERN_ERR PFX
3618                                "%s: Do a reset.\n", ndev->name);
3619                         clear_bit(QL_RESET_PER_SCSI,&qdev->flags);
3620                         clear_bit(QL_RESET_START,&qdev->flags);
3621                         ql_cycle_adapter(qdev,QL_DO_RESET);
3622                         return;
3623                 }
3624
3625                 clear_bit(QL_RESET_ACTIVE,&qdev->flags);
3626                 clear_bit(QL_RESET_PER_SCSI,&qdev->flags);
3627                 clear_bit(QL_RESET_START,&qdev->flags);
3628                 ql_cycle_adapter(qdev,QL_NO_RESET);
3629         }
3630 }
3631
3632 static void ql_tx_timeout_work(struct work_struct *work)
3633 {
3634         struct ql3_adapter *qdev =
3635                 container_of(work, struct ql3_adapter, tx_timeout_work.work);
3636
3637         ql_cycle_adapter(qdev, QL_DO_RESET);
3638 }
3639
3640 static void ql_get_board_info(struct ql3_adapter *qdev)
3641 {
3642         struct ql3xxx_port_registers __iomem *port_regs = qdev->mem_map_registers;
3643         u32 value;
3644
3645         value = ql_read_page0_reg_l(qdev, &port_regs->portStatus);
3646
3647         qdev->chip_rev_id = ((value & PORT_STATUS_REV_ID_MASK) >> 12);
3648         if (value & PORT_STATUS_64)
3649                 qdev->pci_width = 64;
3650         else
3651                 qdev->pci_width = 32;
3652         if (value & PORT_STATUS_X)
3653                 qdev->pci_x = 1;
3654         else
3655                 qdev->pci_x = 0;
3656         qdev->pci_slot = (u8) PCI_SLOT(qdev->pdev->devfn);
3657 }
3658
3659 static void ql3xxx_timer(unsigned long ptr)
3660 {
3661         struct ql3_adapter *qdev = (struct ql3_adapter *)ptr;
3662
3663         if (test_bit(QL_RESET_ACTIVE,&qdev->flags)) {
3664                 printk(KERN_DEBUG PFX
3665                        "%s: Reset in progress.\n",
3666                        qdev->ndev->name);
3667                 goto end;
3668         }
3669
3670         ql_link_state_machine(qdev);
3671
3672         /* Restart timer on 2 second interval. */
3673 end:
3674         mod_timer(&qdev->adapter_timer, jiffies + HZ * 1);
3675 }
3676
3677 static int __devinit ql3xxx_probe(struct pci_dev *pdev,
3678                                   const struct pci_device_id *pci_entry)
3679 {
3680         struct net_device *ndev = NULL;
3681         struct ql3_adapter *qdev = NULL;
3682         static int cards_found = 0;
3683         int pci_using_dac, err;
3684
3685         err = pci_enable_device(pdev);
3686         if (err) {
3687                 printk(KERN_ERR PFX "%s cannot enable PCI device\n",
3688                        pci_name(pdev));
3689                 goto err_out;
3690         }
3691
3692         err = pci_request_regions(pdev, DRV_NAME);
3693         if (err) {
3694                 printk(KERN_ERR PFX "%s cannot obtain PCI resources\n",
3695                        pci_name(pdev));
3696                 goto err_out_disable_pdev;
3697         }
3698
3699         pci_set_master(pdev);
3700
3701         if (!pci_set_dma_mask(pdev, DMA_64BIT_MASK)) {
3702                 pci_using_dac = 1;
3703                 err = pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK);
3704         } else if (!(err = pci_set_dma_mask(pdev, DMA_32BIT_MASK))) {
3705                 pci_using_dac = 0;
3706                 err = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
3707         }
3708
3709         if (err) {
3710                 printk(KERN_ERR PFX "%s no usable DMA configuration\n",
3711                        pci_name(pdev));
3712                 goto err_out_free_regions;
3713         }
3714
3715         ndev = alloc_etherdev(sizeof(struct ql3_adapter));
3716         if (!ndev) {
3717                 printk(KERN_ERR PFX "%s could not alloc etherdev\n",
3718                        pci_name(pdev));
3719                 err = -ENOMEM;
3720                 goto err_out_free_regions;
3721         }
3722
3723         SET_MODULE_OWNER(ndev);
3724         SET_NETDEV_DEV(ndev, &pdev->dev);
3725
3726         pci_set_drvdata(pdev, ndev);
3727
3728         qdev = netdev_priv(ndev);
3729         qdev->index = cards_found;
3730         qdev->ndev = ndev;
3731         qdev->pdev = pdev;
3732         qdev->device_id = pci_entry->device;
3733         qdev->port_link_state = LS_DOWN;
3734         if (msi)
3735                 qdev->msi = 1;
3736
3737         qdev->msg_enable = netif_msg_init(debug, default_msg);
3738
3739         if (pci_using_dac)
3740                 ndev->features |= NETIF_F_HIGHDMA;
3741         if (qdev->device_id == QL3032_DEVICE_ID)
3742                 ndev->features |= (NETIF_F_HW_CSUM | NETIF_F_SG);
3743
3744         qdev->mem_map_registers =
3745             ioremap_nocache(pci_resource_start(pdev, 1),
3746                             pci_resource_len(qdev->pdev, 1));
3747         if (!qdev->mem_map_registers) {
3748                 printk(KERN_ERR PFX "%s: cannot map device registers\n",
3749                        pci_name(pdev));
3750                 err = -EIO;
3751                 goto err_out_free_ndev;
3752         }
3753
3754         spin_lock_init(&qdev->adapter_lock);
3755         spin_lock_init(&qdev->hw_lock);
3756
3757         /* Set driver entry points */
3758         ndev->open = ql3xxx_open;
3759         ndev->hard_start_xmit = ql3xxx_send;
3760         ndev->stop = ql3xxx_close;
3761         ndev->get_stats = ql3xxx_get_stats;
3762         ndev->set_multicast_list = ql3xxx_set_multicast_list;
3763         SET_ETHTOOL_OPS(ndev, &ql3xxx_ethtool_ops);
3764         ndev->set_mac_address = ql3xxx_set_mac_address;
3765         ndev->tx_timeout = ql3xxx_tx_timeout;
3766         ndev->watchdog_timeo = 5 * HZ;
3767
3768         ndev->poll = &ql_poll;
3769         ndev->weight = 64;
3770
3771         ndev->irq = pdev->irq;
3772
3773         /* make sure the EEPROM is good */
3774         if (ql_get_nvram_params(qdev)) {
3775                 printk(KERN_ALERT PFX
3776                        "ql3xxx_probe: Adapter #%d, Invalid NVRAM parameters.\n",
3777                        qdev->index);
3778                 err = -EIO;
3779                 goto err_out_iounmap;
3780         }
3781
3782         ql_set_mac_info(qdev);
3783
3784         /* Validate and set parameters */
3785         if (qdev->mac_index) {
3786                 ndev->mtu = qdev->nvram_data.macCfg_port1.etherMtu_mac ;
3787                 memcpy(ndev->dev_addr, &qdev->nvram_data.funcCfg_fn2.macAddress,
3788                        ETH_ALEN);
3789         } else {
3790                 ndev->mtu = qdev->nvram_data.macCfg_port0.etherMtu_mac ;
3791                 memcpy(ndev->dev_addr, &qdev->nvram_data.funcCfg_fn0.macAddress,
3792                        ETH_ALEN);
3793         }
3794         memcpy(ndev->perm_addr, ndev->dev_addr, ndev->addr_len);
3795
3796         ndev->tx_queue_len = NUM_REQ_Q_ENTRIES;
3797
3798         /* Turn off support for multicasting */
3799         ndev->flags &= ~IFF_MULTICAST;
3800
3801         /* Record PCI bus information. */
3802         ql_get_board_info(qdev);
3803
3804         /*
3805          * Set the Maximum Memory Read Byte Count value. We do this to handle
3806          * jumbo frames.
3807          */
3808         if (qdev->pci_x) {
3809                 pci_write_config_word(pdev, (int)0x4e, (u16) 0x0036);
3810         }
3811
3812         err = register_netdev(ndev);
3813         if (err) {
3814                 printk(KERN_ERR PFX "%s: cannot register net device\n",
3815                        pci_name(pdev));
3816                 goto err_out_iounmap;
3817         }
3818
3819         /* we're going to reset, so assume we have no link for now */
3820
3821         netif_carrier_off(ndev);
3822         netif_stop_queue(ndev);
3823
3824         qdev->workqueue = create_singlethread_workqueue(ndev->name);
3825         INIT_DELAYED_WORK(&qdev->reset_work, ql_reset_work);
3826         INIT_DELAYED_WORK(&qdev->tx_timeout_work, ql_tx_timeout_work);
3827
3828         init_timer(&qdev->adapter_timer);
3829         qdev->adapter_timer.function = ql3xxx_timer;
3830         qdev->adapter_timer.expires = jiffies + HZ * 2; /* two second delay */
3831         qdev->adapter_timer.data = (unsigned long)qdev;
3832
3833         if(!cards_found) {
3834                 printk(KERN_ALERT PFX "%s\n", DRV_STRING);
3835                 printk(KERN_ALERT PFX "Driver name: %s, Version: %s.\n",
3836                    DRV_NAME, DRV_VERSION);
3837         }
3838         ql_display_dev_info(ndev);
3839
3840         cards_found++;
3841         return 0;
3842
3843 err_out_iounmap:
3844         iounmap(qdev->mem_map_registers);
3845 err_out_free_ndev:
3846         free_netdev(ndev);
3847 err_out_free_regions:
3848         pci_release_regions(pdev);
3849 err_out_disable_pdev:
3850         pci_disable_device(pdev);
3851         pci_set_drvdata(pdev, NULL);
3852 err_out:
3853         return err;
3854 }
3855
3856 static void __devexit ql3xxx_remove(struct pci_dev *pdev)
3857 {
3858         struct net_device *ndev = pci_get_drvdata(pdev);
3859         struct ql3_adapter *qdev = netdev_priv(ndev);
3860
3861         unregister_netdev(ndev);
3862         qdev = netdev_priv(ndev);
3863
3864         ql_disable_interrupts(qdev);
3865
3866         if (qdev->workqueue) {
3867                 cancel_delayed_work(&qdev->reset_work);
3868                 cancel_delayed_work(&qdev->tx_timeout_work);
3869                 destroy_workqueue(qdev->workqueue);
3870                 qdev->workqueue = NULL;
3871         }
3872
3873         iounmap(qdev->mem_map_registers);
3874         pci_release_regions(pdev);
3875         pci_set_drvdata(pdev, NULL);
3876         free_netdev(ndev);
3877 }
3878
3879 static struct pci_driver ql3xxx_driver = {
3880
3881         .name = DRV_NAME,
3882         .id_table = ql3xxx_pci_tbl,
3883         .probe = ql3xxx_probe,
3884         .remove = __devexit_p(ql3xxx_remove),
3885 };
3886
3887 static int __init ql3xxx_init_module(void)
3888 {
3889         return pci_register_driver(&ql3xxx_driver);
3890 }
3891
3892 static void __exit ql3xxx_exit(void)
3893 {
3894         pci_unregister_driver(&ql3xxx_driver);
3895 }
3896
3897 module_init(ql3xxx_init_module);
3898 module_exit(ql3xxx_exit);