1 /*************************************************************************
2 * myri10ge.c: Myricom Myri-10G Ethernet driver.
4 * Copyright (C) 2005 - 2007 Myricom, Inc.
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 * 3. Neither the name of Myricom, Inc. nor the names of its contributors
16 * may be used to endorse or promote products derived from this software
17 * without specific prior written permission.
19 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
20 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
22 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
23 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
29 * POSSIBILITY OF SUCH DAMAGE.
32 * If the eeprom on your board is not recent enough, you will need to get a
33 * newer firmware image at:
34 * http://www.myri.com/scs/download-Myri10GE.html
36 * Contact Information:
38 * Myricom, Inc., 325N Santa Anita Avenue, Arcadia, CA 91006
39 *************************************************************************/
41 #include <linux/tcp.h>
42 #include <linux/netdevice.h>
43 #include <linux/skbuff.h>
44 #include <linux/string.h>
45 #include <linux/module.h>
46 #include <linux/pci.h>
47 #include <linux/dma-mapping.h>
48 #include <linux/etherdevice.h>
49 #include <linux/if_ether.h>
50 #include <linux/if_vlan.h>
51 #include <linux/inet_lro.h>
53 #include <linux/inet.h>
55 #include <linux/ethtool.h>
56 #include <linux/firmware.h>
57 #include <linux/delay.h>
58 #include <linux/version.h>
59 #include <linux/timer.h>
60 #include <linux/vmalloc.h>
61 #include <linux/crc32.h>
62 #include <linux/moduleparam.h>
64 #include <linux/log2.h>
65 #include <net/checksum.h>
68 #include <asm/byteorder.h>
70 #include <asm/processor.h>
75 #include "myri10ge_mcp.h"
76 #include "myri10ge_mcp_gen_header.h"
78 #define MYRI10GE_VERSION_STR "1.3.2-1.287"
80 MODULE_DESCRIPTION("Myricom 10G driver (10GbE)");
81 MODULE_AUTHOR("Maintainer: help@myri.com");
82 MODULE_VERSION(MYRI10GE_VERSION_STR);
83 MODULE_LICENSE("Dual BSD/GPL");
85 #define MYRI10GE_MAX_ETHER_MTU 9014
87 #define MYRI10GE_ETH_STOPPED 0
88 #define MYRI10GE_ETH_STOPPING 1
89 #define MYRI10GE_ETH_STARTING 2
90 #define MYRI10GE_ETH_RUNNING 3
91 #define MYRI10GE_ETH_OPEN_FAILED 4
93 #define MYRI10GE_EEPROM_STRINGS_SIZE 256
94 #define MYRI10GE_MAX_SEND_DESC_TSO ((65536 / 2048) * 2)
95 #define MYRI10GE_MAX_LRO_DESCRIPTORS 8
96 #define MYRI10GE_LRO_MAX_PKTS 64
98 #define MYRI10GE_NO_CONFIRM_DATA htonl(0xffffffff)
99 #define MYRI10GE_NO_RESPONSE_RESULT 0xffffffff
101 #define MYRI10GE_ALLOC_ORDER 0
102 #define MYRI10GE_ALLOC_SIZE ((1 << MYRI10GE_ALLOC_ORDER) * PAGE_SIZE)
103 #define MYRI10GE_MAX_FRAGS_PER_FRAME (MYRI10GE_MAX_ETHER_MTU/MYRI10GE_ALLOC_SIZE + 1)
105 struct myri10ge_rx_buffer_state {
108 DECLARE_PCI_UNMAP_ADDR(bus)
109 DECLARE_PCI_UNMAP_LEN(len)
112 struct myri10ge_tx_buffer_state {
115 DECLARE_PCI_UNMAP_ADDR(bus)
116 DECLARE_PCI_UNMAP_LEN(len)
119 struct myri10ge_cmd {
125 struct myri10ge_rx_buf {
126 struct mcp_kreq_ether_recv __iomem *lanai; /* lanai ptr for recv ring */
127 u8 __iomem *wc_fifo; /* w/c rx dma addr fifo address */
128 struct mcp_kreq_ether_recv *shadow; /* host shadow of recv ring */
129 struct myri10ge_rx_buffer_state *info;
136 int mask; /* number of rx slots -1 */
140 struct myri10ge_tx_buf {
141 struct mcp_kreq_ether_send __iomem *lanai; /* lanai ptr for sendq */
142 u8 __iomem *wc_fifo; /* w/c send fifo address */
143 struct mcp_kreq_ether_send *req_list; /* host shadow of sendq */
145 struct myri10ge_tx_buffer_state *info;
146 int mask; /* number of transmit slots -1 */
147 int req ____cacheline_aligned; /* transmit slots submitted */
148 int pkt_start; /* packets started */
151 int done ____cacheline_aligned; /* transmit slots completed */
152 int pkt_done; /* packets completed */
156 struct myri10ge_rx_done {
157 struct mcp_slot *entry;
161 struct net_lro_mgr lro_mgr;
162 struct net_lro_desc lro_desc[MYRI10GE_MAX_LRO_DESCRIPTORS];
165 struct myri10ge_slice_netstats {
166 unsigned long rx_packets;
167 unsigned long tx_packets;
168 unsigned long rx_bytes;
169 unsigned long tx_bytes;
170 unsigned long rx_dropped;
171 unsigned long tx_dropped;
174 struct myri10ge_slice_state {
175 struct myri10ge_tx_buf tx; /* transmit ring */
176 struct myri10ge_rx_buf rx_small;
177 struct myri10ge_rx_buf rx_big;
178 struct myri10ge_rx_done rx_done;
179 struct net_device *dev;
180 struct napi_struct napi;
181 struct myri10ge_priv *mgp;
182 struct myri10ge_slice_netstats stats;
183 __be32 __iomem *irq_claim;
184 struct mcp_irq_data *fw_stats;
185 dma_addr_t fw_stats_bus;
186 int watchdog_tx_done;
190 struct myri10ge_priv {
191 struct myri10ge_slice_state ss;
192 int tx_boundary; /* boundary transmits cannot cross */
193 int running; /* running? */
194 int csum_flag; /* rx_csums? */
198 struct net_device *dev;
199 struct net_device_stats stats;
200 spinlock_t stats_lock;
203 unsigned long board_span;
204 unsigned long iomem_base;
205 __be32 __iomem *irq_deassert;
206 char *mac_addr_string;
207 struct mcp_cmd_response *cmd;
209 struct pci_dev *pdev;
212 unsigned int rdma_tags_available;
214 __be32 __iomem *intr_coal_delay_ptr;
218 wait_queue_head_t down_wq;
219 struct work_struct watchdog_work;
220 struct timer_list watchdog_timer;
225 char eeprom_strings[MYRI10GE_EEPROM_STRINGS_SIZE];
226 char *product_code_string;
227 char fw_version[128];
231 int adopted_rx_filter_bug;
232 u8 mac_addr[6]; /* eeprom mac address */
233 unsigned long serial_number;
234 int vendor_specific_offset;
235 int fw_multicast_support;
236 unsigned long features;
245 static char *myri10ge_fw_unaligned = "myri10ge_ethp_z8e.dat";
246 static char *myri10ge_fw_aligned = "myri10ge_eth_z8e.dat";
248 static char *myri10ge_fw_name = NULL;
249 module_param(myri10ge_fw_name, charp, S_IRUGO | S_IWUSR);
250 MODULE_PARM_DESC(myri10ge_fw_name, "Firmware image name");
252 static int myri10ge_ecrc_enable = 1;
253 module_param(myri10ge_ecrc_enable, int, S_IRUGO);
254 MODULE_PARM_DESC(myri10ge_ecrc_enable, "Enable Extended CRC on PCI-E");
256 static int myri10ge_small_bytes = -1; /* -1 == auto */
257 module_param(myri10ge_small_bytes, int, S_IRUGO | S_IWUSR);
258 MODULE_PARM_DESC(myri10ge_small_bytes, "Threshold of small packets");
260 static int myri10ge_msi = 1; /* enable msi by default */
261 module_param(myri10ge_msi, int, S_IRUGO | S_IWUSR);
262 MODULE_PARM_DESC(myri10ge_msi, "Enable Message Signalled Interrupts");
264 static int myri10ge_intr_coal_delay = 75;
265 module_param(myri10ge_intr_coal_delay, int, S_IRUGO);
266 MODULE_PARM_DESC(myri10ge_intr_coal_delay, "Interrupt coalescing delay");
268 static int myri10ge_flow_control = 1;
269 module_param(myri10ge_flow_control, int, S_IRUGO);
270 MODULE_PARM_DESC(myri10ge_flow_control, "Pause parameter");
272 static int myri10ge_deassert_wait = 1;
273 module_param(myri10ge_deassert_wait, int, S_IRUGO | S_IWUSR);
274 MODULE_PARM_DESC(myri10ge_deassert_wait,
275 "Wait when deasserting legacy interrupts");
277 static int myri10ge_force_firmware = 0;
278 module_param(myri10ge_force_firmware, int, S_IRUGO);
279 MODULE_PARM_DESC(myri10ge_force_firmware,
280 "Force firmware to assume aligned completions");
282 static int myri10ge_initial_mtu = MYRI10GE_MAX_ETHER_MTU - ETH_HLEN;
283 module_param(myri10ge_initial_mtu, int, S_IRUGO);
284 MODULE_PARM_DESC(myri10ge_initial_mtu, "Initial MTU");
286 static int myri10ge_napi_weight = 64;
287 module_param(myri10ge_napi_weight, int, S_IRUGO);
288 MODULE_PARM_DESC(myri10ge_napi_weight, "Set NAPI weight");
290 static int myri10ge_watchdog_timeout = 1;
291 module_param(myri10ge_watchdog_timeout, int, S_IRUGO);
292 MODULE_PARM_DESC(myri10ge_watchdog_timeout, "Set watchdog timeout");
294 static int myri10ge_max_irq_loops = 1048576;
295 module_param(myri10ge_max_irq_loops, int, S_IRUGO);
296 MODULE_PARM_DESC(myri10ge_max_irq_loops,
297 "Set stuck legacy IRQ detection threshold");
299 #define MYRI10GE_MSG_DEFAULT NETIF_MSG_LINK
301 static int myri10ge_debug = -1; /* defaults above */
302 module_param(myri10ge_debug, int, 0);
303 MODULE_PARM_DESC(myri10ge_debug, "Debug level (0=none,...,16=all)");
305 static int myri10ge_lro = 1;
306 module_param(myri10ge_lro, int, S_IRUGO);
307 MODULE_PARM_DESC(myri10ge_lro, "Enable large receive offload");
309 static int myri10ge_lro_max_pkts = MYRI10GE_LRO_MAX_PKTS;
310 module_param(myri10ge_lro_max_pkts, int, S_IRUGO);
311 MODULE_PARM_DESC(myri10ge_lro_max_pkts,
312 "Number of LRO packets to be aggregated");
314 static int myri10ge_fill_thresh = 256;
315 module_param(myri10ge_fill_thresh, int, S_IRUGO | S_IWUSR);
316 MODULE_PARM_DESC(myri10ge_fill_thresh, "Number of empty rx slots allowed");
318 static int myri10ge_reset_recover = 1;
320 static int myri10ge_wcfifo = 0;
321 module_param(myri10ge_wcfifo, int, S_IRUGO);
322 MODULE_PARM_DESC(myri10ge_wcfifo, "Enable WC Fifo when WC is enabled");
324 #define MYRI10GE_FW_OFFSET 1024*1024
325 #define MYRI10GE_HIGHPART_TO_U32(X) \
326 (sizeof (X) == 8) ? ((u32)((u64)(X) >> 32)) : (0)
327 #define MYRI10GE_LOWPART_TO_U32(X) ((u32)(X))
329 #define myri10ge_pio_copy(to,from,size) __iowrite64_copy(to,from,size/8)
331 static void myri10ge_set_multicast_list(struct net_device *dev);
332 static int myri10ge_sw_tso(struct sk_buff *skb, struct net_device *dev);
334 static inline void put_be32(__be32 val, __be32 __iomem * p)
336 __raw_writel((__force __u32) val, (__force void __iomem *)p);
340 myri10ge_send_cmd(struct myri10ge_priv *mgp, u32 cmd,
341 struct myri10ge_cmd *data, int atomic)
344 char buf_bytes[sizeof(*buf) + 8];
345 struct mcp_cmd_response *response = mgp->cmd;
346 char __iomem *cmd_addr = mgp->sram + MXGEFW_ETH_CMD;
347 u32 dma_low, dma_high, result, value;
350 /* ensure buf is aligned to 8 bytes */
351 buf = (struct mcp_cmd *)ALIGN((unsigned long)buf_bytes, 8);
353 buf->data0 = htonl(data->data0);
354 buf->data1 = htonl(data->data1);
355 buf->data2 = htonl(data->data2);
356 buf->cmd = htonl(cmd);
357 dma_low = MYRI10GE_LOWPART_TO_U32(mgp->cmd_bus);
358 dma_high = MYRI10GE_HIGHPART_TO_U32(mgp->cmd_bus);
360 buf->response_addr.low = htonl(dma_low);
361 buf->response_addr.high = htonl(dma_high);
362 response->result = htonl(MYRI10GE_NO_RESPONSE_RESULT);
364 myri10ge_pio_copy(cmd_addr, buf, sizeof(*buf));
366 /* wait up to 15ms. Longest command is the DMA benchmark,
367 * which is capped at 5ms, but runs from a timeout handler
368 * that runs every 7.8ms. So a 15ms timeout leaves us with
372 /* if atomic is set, do not sleep,
373 * and try to get the completion quickly
374 * (1ms will be enough for those commands) */
375 for (sleep_total = 0;
377 && response->result == htonl(MYRI10GE_NO_RESPONSE_RESULT);
383 /* use msleep for most command */
384 for (sleep_total = 0;
386 && response->result == htonl(MYRI10GE_NO_RESPONSE_RESULT);
391 result = ntohl(response->result);
392 value = ntohl(response->data);
393 if (result != MYRI10GE_NO_RESPONSE_RESULT) {
397 } else if (result == MXGEFW_CMD_UNKNOWN) {
399 } else if (result == MXGEFW_CMD_ERROR_UNALIGNED) {
402 dev_err(&mgp->pdev->dev,
403 "command %d failed, result = %d\n",
409 dev_err(&mgp->pdev->dev, "command %d timed out, result = %d\n",
415 * The eeprom strings on the lanaiX have the format
418 * PT:ddd mmm xx xx:xx:xx xx\0
419 * PV:ddd mmm xx xx:xx:xx xx\0
421 static int myri10ge_read_mac_addr(struct myri10ge_priv *mgp)
426 ptr = mgp->eeprom_strings;
427 limit = mgp->eeprom_strings + MYRI10GE_EEPROM_STRINGS_SIZE;
429 while (*ptr != '\0' && ptr < limit) {
430 if (memcmp(ptr, "MAC=", 4) == 0) {
432 mgp->mac_addr_string = ptr;
433 for (i = 0; i < 6; i++) {
434 if ((ptr + 2) > limit)
437 simple_strtoul(ptr, &ptr, 16);
441 if (memcmp(ptr, "PC=", 3) == 0) {
443 mgp->product_code_string = ptr;
445 if (memcmp((const void *)ptr, "SN=", 3) == 0) {
447 mgp->serial_number = simple_strtoul(ptr, &ptr, 10);
449 while (ptr < limit && *ptr++) ;
455 dev_err(&mgp->pdev->dev, "failed to parse eeprom_strings\n");
460 * Enable or disable periodic RDMAs from the host to make certain
461 * chipsets resend dropped PCIe messages
464 static void myri10ge_dummy_rdma(struct myri10ge_priv *mgp, int enable)
466 char __iomem *submit;
467 __be32 buf[16] __attribute__ ((__aligned__(8)));
468 u32 dma_low, dma_high;
471 /* clear confirmation addr */
475 /* send a rdma command to the PCIe engine, and wait for the
476 * response in the confirmation address. The firmware should
477 * write a -1 there to indicate it is alive and well
479 dma_low = MYRI10GE_LOWPART_TO_U32(mgp->cmd_bus);
480 dma_high = MYRI10GE_HIGHPART_TO_U32(mgp->cmd_bus);
482 buf[0] = htonl(dma_high); /* confirm addr MSW */
483 buf[1] = htonl(dma_low); /* confirm addr LSW */
484 buf[2] = MYRI10GE_NO_CONFIRM_DATA; /* confirm data */
485 buf[3] = htonl(dma_high); /* dummy addr MSW */
486 buf[4] = htonl(dma_low); /* dummy addr LSW */
487 buf[5] = htonl(enable); /* enable? */
489 submit = mgp->sram + MXGEFW_BOOT_DUMMY_RDMA;
491 myri10ge_pio_copy(submit, &buf, sizeof(buf));
492 for (i = 0; mgp->cmd->data != MYRI10GE_NO_CONFIRM_DATA && i < 20; i++)
494 if (mgp->cmd->data != MYRI10GE_NO_CONFIRM_DATA)
495 dev_err(&mgp->pdev->dev, "dummy rdma %s failed\n",
496 (enable ? "enable" : "disable"));
500 myri10ge_validate_firmware(struct myri10ge_priv *mgp,
501 struct mcp_gen_header *hdr)
503 struct device *dev = &mgp->pdev->dev;
505 /* check firmware type */
506 if (ntohl(hdr->mcp_type) != MCP_TYPE_ETH) {
507 dev_err(dev, "Bad firmware type: 0x%x\n", ntohl(hdr->mcp_type));
511 /* save firmware version for ethtool */
512 strncpy(mgp->fw_version, hdr->version, sizeof(mgp->fw_version));
514 sscanf(mgp->fw_version, "%d.%d.%d", &mgp->fw_ver_major,
515 &mgp->fw_ver_minor, &mgp->fw_ver_tiny);
517 if (!(mgp->fw_ver_major == MXGEFW_VERSION_MAJOR
518 && mgp->fw_ver_minor == MXGEFW_VERSION_MINOR)) {
519 dev_err(dev, "Found firmware version %s\n", mgp->fw_version);
520 dev_err(dev, "Driver needs %d.%d\n", MXGEFW_VERSION_MAJOR,
521 MXGEFW_VERSION_MINOR);
527 static int myri10ge_load_hotplug_firmware(struct myri10ge_priv *mgp, u32 * size)
529 unsigned crc, reread_crc;
530 const struct firmware *fw;
531 struct device *dev = &mgp->pdev->dev;
532 struct mcp_gen_header *hdr;
537 if ((status = request_firmware(&fw, mgp->fw_name, dev)) < 0) {
538 dev_err(dev, "Unable to load %s firmware image via hotplug\n",
541 goto abort_with_nothing;
546 if (fw->size >= mgp->sram_size - MYRI10GE_FW_OFFSET ||
547 fw->size < MCP_HEADER_PTR_OFFSET + 4) {
548 dev_err(dev, "Firmware size invalid:%d\n", (int)fw->size);
554 hdr_offset = ntohl(*(__be32 *) (fw->data + MCP_HEADER_PTR_OFFSET));
555 if ((hdr_offset & 3) || hdr_offset + sizeof(*hdr) > fw->size) {
556 dev_err(dev, "Bad firmware file\n");
560 hdr = (void *)(fw->data + hdr_offset);
562 status = myri10ge_validate_firmware(mgp, hdr);
566 crc = crc32(~0, fw->data, fw->size);
567 for (i = 0; i < fw->size; i += 256) {
568 myri10ge_pio_copy(mgp->sram + MYRI10GE_FW_OFFSET + i,
570 min(256U, (unsigned)(fw->size - i)));
574 /* corruption checking is good for parity recovery and buggy chipset */
575 memcpy_fromio(fw->data, mgp->sram + MYRI10GE_FW_OFFSET, fw->size);
576 reread_crc = crc32(~0, fw->data, fw->size);
577 if (crc != reread_crc) {
578 dev_err(dev, "CRC failed(fw-len=%u), got 0x%x (expect 0x%x)\n",
579 (unsigned)fw->size, reread_crc, crc);
583 *size = (u32) fw->size;
586 release_firmware(fw);
592 static int myri10ge_adopt_running_firmware(struct myri10ge_priv *mgp)
594 struct mcp_gen_header *hdr;
595 struct device *dev = &mgp->pdev->dev;
596 const size_t bytes = sizeof(struct mcp_gen_header);
600 /* find running firmware header */
601 hdr_offset = swab32(readl(mgp->sram + MCP_HEADER_PTR_OFFSET));
603 if ((hdr_offset & 3) || hdr_offset + sizeof(*hdr) > mgp->sram_size) {
604 dev_err(dev, "Running firmware has bad header offset (%d)\n",
609 /* copy header of running firmware from SRAM to host memory to
610 * validate firmware */
611 hdr = kmalloc(bytes, GFP_KERNEL);
613 dev_err(dev, "could not malloc firmware hdr\n");
616 memcpy_fromio(hdr, mgp->sram + hdr_offset, bytes);
617 status = myri10ge_validate_firmware(mgp, hdr);
620 /* check to see if adopted firmware has bug where adopting
621 * it will cause broadcasts to be filtered unless the NIC
622 * is kept in ALLMULTI mode */
623 if (mgp->fw_ver_major == 1 && mgp->fw_ver_minor == 4 &&
624 mgp->fw_ver_tiny >= 4 && mgp->fw_ver_tiny <= 11) {
625 mgp->adopted_rx_filter_bug = 1;
626 dev_warn(dev, "Adopting fw %d.%d.%d: "
627 "working around rx filter bug\n",
628 mgp->fw_ver_major, mgp->fw_ver_minor,
634 static int myri10ge_get_firmware_capabilities(struct myri10ge_priv *mgp)
636 struct myri10ge_cmd cmd;
639 /* probe for IPv6 TSO support */
640 mgp->features = NETIF_F_SG | NETIF_F_HW_CSUM | NETIF_F_TSO;
641 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_GET_MAX_TSO6_HDR_SIZE,
644 mgp->max_tso6 = cmd.data0;
645 mgp->features |= NETIF_F_TSO6;
648 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_GET_RX_RING_SIZE, &cmd, 0);
650 dev_err(&mgp->pdev->dev,
651 "failed MXGEFW_CMD_GET_RX_RING_SIZE\n");
655 mgp->max_intr_slots = 2 * (cmd.data0 / sizeof(struct mcp_dma_addr));
660 static int myri10ge_load_firmware(struct myri10ge_priv *mgp)
662 char __iomem *submit;
663 __be32 buf[16] __attribute__ ((__aligned__(8)));
664 u32 dma_low, dma_high, size;
668 status = myri10ge_load_hotplug_firmware(mgp, &size);
670 dev_warn(&mgp->pdev->dev, "hotplug firmware loading failed\n");
672 /* Do not attempt to adopt firmware if there
677 status = myri10ge_adopt_running_firmware(mgp);
679 dev_err(&mgp->pdev->dev,
680 "failed to adopt running firmware\n");
683 dev_info(&mgp->pdev->dev,
684 "Successfully adopted running firmware\n");
685 if (mgp->tx_boundary == 4096) {
686 dev_warn(&mgp->pdev->dev,
687 "Using firmware currently running on NIC"
689 dev_warn(&mgp->pdev->dev,
690 "performance consider loading optimized "
692 dev_warn(&mgp->pdev->dev, "via hotplug\n");
695 mgp->fw_name = "adopted";
696 mgp->tx_boundary = 2048;
697 myri10ge_dummy_rdma(mgp, 1);
698 status = myri10ge_get_firmware_capabilities(mgp);
702 /* clear confirmation addr */
706 /* send a reload command to the bootstrap MCP, and wait for the
707 * response in the confirmation address. The firmware should
708 * write a -1 there to indicate it is alive and well
710 dma_low = MYRI10GE_LOWPART_TO_U32(mgp->cmd_bus);
711 dma_high = MYRI10GE_HIGHPART_TO_U32(mgp->cmd_bus);
713 buf[0] = htonl(dma_high); /* confirm addr MSW */
714 buf[1] = htonl(dma_low); /* confirm addr LSW */
715 buf[2] = MYRI10GE_NO_CONFIRM_DATA; /* confirm data */
717 /* FIX: All newest firmware should un-protect the bottom of
718 * the sram before handoff. However, the very first interfaces
719 * do not. Therefore the handoff copy must skip the first 8 bytes
721 buf[3] = htonl(MYRI10GE_FW_OFFSET + 8); /* where the code starts */
722 buf[4] = htonl(size - 8); /* length of code */
723 buf[5] = htonl(8); /* where to copy to */
724 buf[6] = htonl(0); /* where to jump to */
726 submit = mgp->sram + MXGEFW_BOOT_HANDOFF;
728 myri10ge_pio_copy(submit, &buf, sizeof(buf));
733 while (mgp->cmd->data != MYRI10GE_NO_CONFIRM_DATA && i < 9) {
737 if (mgp->cmd->data != MYRI10GE_NO_CONFIRM_DATA) {
738 dev_err(&mgp->pdev->dev, "handoff failed\n");
741 myri10ge_dummy_rdma(mgp, 1);
742 status = myri10ge_get_firmware_capabilities(mgp);
747 static int myri10ge_update_mac_address(struct myri10ge_priv *mgp, u8 * addr)
749 struct myri10ge_cmd cmd;
752 cmd.data0 = ((addr[0] << 24) | (addr[1] << 16)
753 | (addr[2] << 8) | addr[3]);
755 cmd.data1 = ((addr[4] << 8) | (addr[5]));
757 status = myri10ge_send_cmd(mgp, MXGEFW_SET_MAC_ADDRESS, &cmd, 0);
761 static int myri10ge_change_pause(struct myri10ge_priv *mgp, int pause)
763 struct myri10ge_cmd cmd;
766 ctl = pause ? MXGEFW_ENABLE_FLOW_CONTROL : MXGEFW_DISABLE_FLOW_CONTROL;
767 status = myri10ge_send_cmd(mgp, ctl, &cmd, 0);
771 "myri10ge: %s: Failed to set flow control mode\n",
780 myri10ge_change_promisc(struct myri10ge_priv *mgp, int promisc, int atomic)
782 struct myri10ge_cmd cmd;
785 ctl = promisc ? MXGEFW_ENABLE_PROMISC : MXGEFW_DISABLE_PROMISC;
786 status = myri10ge_send_cmd(mgp, ctl, &cmd, atomic);
788 printk(KERN_ERR "myri10ge: %s: Failed to set promisc mode\n",
792 static int myri10ge_dma_test(struct myri10ge_priv *mgp, int test_type)
794 struct myri10ge_cmd cmd;
797 struct page *dmatest_page;
798 dma_addr_t dmatest_bus;
801 dmatest_page = alloc_page(GFP_KERNEL);
804 dmatest_bus = pci_map_page(mgp->pdev, dmatest_page, 0, PAGE_SIZE,
807 /* Run a small DMA test.
808 * The magic multipliers to the length tell the firmware
809 * to do DMA read, write, or read+write tests. The
810 * results are returned in cmd.data0. The upper 16
811 * bits or the return is the number of transfers completed.
812 * The lower 16 bits is the time in 0.5us ticks that the
813 * transfers took to complete.
816 len = mgp->tx_boundary;
818 cmd.data0 = MYRI10GE_LOWPART_TO_U32(dmatest_bus);
819 cmd.data1 = MYRI10GE_HIGHPART_TO_U32(dmatest_bus);
820 cmd.data2 = len * 0x10000;
821 status = myri10ge_send_cmd(mgp, test_type, &cmd, 0);
826 mgp->read_dma = ((cmd.data0 >> 16) * len * 2) / (cmd.data0 & 0xffff);
827 cmd.data0 = MYRI10GE_LOWPART_TO_U32(dmatest_bus);
828 cmd.data1 = MYRI10GE_HIGHPART_TO_U32(dmatest_bus);
829 cmd.data2 = len * 0x1;
830 status = myri10ge_send_cmd(mgp, test_type, &cmd, 0);
835 mgp->write_dma = ((cmd.data0 >> 16) * len * 2) / (cmd.data0 & 0xffff);
837 cmd.data0 = MYRI10GE_LOWPART_TO_U32(dmatest_bus);
838 cmd.data1 = MYRI10GE_HIGHPART_TO_U32(dmatest_bus);
839 cmd.data2 = len * 0x10001;
840 status = myri10ge_send_cmd(mgp, test_type, &cmd, 0);
845 mgp->read_write_dma = ((cmd.data0 >> 16) * len * 2 * 2) /
846 (cmd.data0 & 0xffff);
849 pci_unmap_page(mgp->pdev, dmatest_bus, PAGE_SIZE, DMA_BIDIRECTIONAL);
850 put_page(dmatest_page);
852 if (status != 0 && test_type != MXGEFW_CMD_UNALIGNED_TEST)
853 dev_warn(&mgp->pdev->dev, "DMA %s benchmark failed: %d\n",
859 static int myri10ge_reset(struct myri10ge_priv *mgp)
861 struct myri10ge_cmd cmd;
865 /* try to send a reset command to the card to see if it
867 memset(&cmd, 0, sizeof(cmd));
868 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_RESET, &cmd, 0);
870 dev_err(&mgp->pdev->dev, "failed reset\n");
874 (void)myri10ge_dma_test(mgp, MXGEFW_DMA_TEST);
876 /* Now exchange information about interrupts */
878 bytes = mgp->max_intr_slots * sizeof(*mgp->ss.rx_done.entry);
879 memset(mgp->ss.rx_done.entry, 0, bytes);
880 cmd.data0 = (u32) bytes;
881 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_SET_INTRQ_SIZE, &cmd, 0);
882 cmd.data0 = MYRI10GE_LOWPART_TO_U32(mgp->ss.rx_done.bus);
883 cmd.data1 = MYRI10GE_HIGHPART_TO_U32(mgp->ss.rx_done.bus);
884 status |= myri10ge_send_cmd(mgp, MXGEFW_CMD_SET_INTRQ_DMA, &cmd, 0);
887 myri10ge_send_cmd(mgp, MXGEFW_CMD_GET_IRQ_ACK_OFFSET, &cmd, 0);
888 mgp->ss.irq_claim = (__iomem __be32 *) (mgp->sram + cmd.data0);
889 status |= myri10ge_send_cmd(mgp, MXGEFW_CMD_GET_IRQ_DEASSERT_OFFSET,
891 mgp->irq_deassert = (__iomem __be32 *) (mgp->sram + cmd.data0);
893 status |= myri10ge_send_cmd
894 (mgp, MXGEFW_CMD_GET_INTR_COAL_DELAY_OFFSET, &cmd, 0);
895 mgp->intr_coal_delay_ptr = (__iomem __be32 *) (mgp->sram + cmd.data0);
897 dev_err(&mgp->pdev->dev, "failed set interrupt parameters\n");
900 put_be32(htonl(mgp->intr_coal_delay), mgp->intr_coal_delay_ptr);
902 memset(mgp->ss.rx_done.entry, 0, bytes);
904 /* reset mcp/driver shared state back to 0 */
907 mgp->ss.tx.pkt_start = 0;
908 mgp->ss.tx.pkt_done = 0;
909 mgp->ss.rx_big.cnt = 0;
910 mgp->ss.rx_small.cnt = 0;
911 mgp->ss.rx_done.idx = 0;
912 mgp->ss.rx_done.cnt = 0;
913 mgp->link_changes = 0;
914 status = myri10ge_update_mac_address(mgp, mgp->dev->dev_addr);
915 myri10ge_change_pause(mgp, mgp->pause);
916 myri10ge_set_multicast_list(mgp->dev);
921 myri10ge_submit_8rx(struct mcp_kreq_ether_recv __iomem * dst,
922 struct mcp_kreq_ether_recv *src)
927 src->addr_low = htonl(DMA_32BIT_MASK);
928 myri10ge_pio_copy(dst, src, 4 * sizeof(*src));
930 myri10ge_pio_copy(dst + 4, src + 4, 4 * sizeof(*src));
933 put_be32(low, &dst->addr_low);
937 static inline void myri10ge_vlan_ip_csum(struct sk_buff *skb, __wsum hw_csum)
939 struct vlan_hdr *vh = (struct vlan_hdr *)(skb->data);
941 if ((skb->protocol == htons(ETH_P_8021Q)) &&
942 (vh->h_vlan_encapsulated_proto == htons(ETH_P_IP) ||
943 vh->h_vlan_encapsulated_proto == htons(ETH_P_IPV6))) {
945 skb->ip_summed = CHECKSUM_COMPLETE;
950 myri10ge_rx_skb_build(struct sk_buff *skb, u8 * va,
951 struct skb_frag_struct *rx_frags, int len, int hlen)
953 struct skb_frag_struct *skb_frags;
955 skb->len = skb->data_len = len;
956 skb->truesize = len + sizeof(struct sk_buff);
957 /* attach the page(s) */
959 skb_frags = skb_shinfo(skb)->frags;
961 memcpy(skb_frags, rx_frags, sizeof(*skb_frags));
962 len -= rx_frags->size;
965 skb_shinfo(skb)->nr_frags++;
968 /* pskb_may_pull is not available in irq context, but
969 * skb_pull() (for ether_pad and eth_type_trans()) requires
970 * the beginning of the packet in skb_headlen(), move it
972 skb_copy_to_linear_data(skb, va, hlen);
973 skb_shinfo(skb)->frags[0].page_offset += hlen;
974 skb_shinfo(skb)->frags[0].size -= hlen;
975 skb->data_len -= hlen;
977 skb_pull(skb, MXGEFW_PAD);
981 myri10ge_alloc_rx_pages(struct myri10ge_priv *mgp, struct myri10ge_rx_buf *rx,
982 int bytes, int watchdog)
987 if (unlikely(rx->watchdog_needed && !watchdog))
990 /* try to refill entire ring */
991 while (rx->fill_cnt != (rx->cnt + rx->mask + 1)) {
992 idx = rx->fill_cnt & rx->mask;
993 if (rx->page_offset + bytes <= MYRI10GE_ALLOC_SIZE) {
994 /* we can use part of previous page */
997 /* we need a new page */
999 alloc_pages(GFP_ATOMIC | __GFP_COMP,
1000 MYRI10GE_ALLOC_ORDER);
1001 if (unlikely(page == NULL)) {
1002 if (rx->fill_cnt - rx->cnt < 16)
1003 rx->watchdog_needed = 1;
1007 rx->page_offset = 0;
1008 rx->bus = pci_map_page(mgp->pdev, page, 0,
1009 MYRI10GE_ALLOC_SIZE,
1010 PCI_DMA_FROMDEVICE);
1012 rx->info[idx].page = rx->page;
1013 rx->info[idx].page_offset = rx->page_offset;
1014 /* note that this is the address of the start of the
1016 pci_unmap_addr_set(&rx->info[idx], bus, rx->bus);
1017 rx->shadow[idx].addr_low =
1018 htonl(MYRI10GE_LOWPART_TO_U32(rx->bus) + rx->page_offset);
1019 rx->shadow[idx].addr_high =
1020 htonl(MYRI10GE_HIGHPART_TO_U32(rx->bus));
1022 /* start next packet on a cacheline boundary */
1023 rx->page_offset += SKB_DATA_ALIGN(bytes);
1025 #if MYRI10GE_ALLOC_SIZE > 4096
1026 /* don't cross a 4KB boundary */
1027 if ((rx->page_offset >> 12) !=
1028 ((rx->page_offset + bytes - 1) >> 12))
1029 rx->page_offset = (rx->page_offset + 4096) & ~4095;
1033 /* copy 8 descriptors to the firmware at a time */
1034 if ((idx & 7) == 7) {
1035 if (rx->wc_fifo == NULL)
1036 myri10ge_submit_8rx(&rx->lanai[idx - 7],
1037 &rx->shadow[idx - 7]);
1040 myri10ge_pio_copy(rx->wc_fifo,
1041 &rx->shadow[idx - 7], 64);
1048 myri10ge_unmap_rx_page(struct pci_dev *pdev,
1049 struct myri10ge_rx_buffer_state *info, int bytes)
1051 /* unmap the recvd page if we're the only or last user of it */
1052 if (bytes >= MYRI10GE_ALLOC_SIZE / 2 ||
1053 (info->page_offset + 2 * bytes) > MYRI10GE_ALLOC_SIZE) {
1054 pci_unmap_page(pdev, (pci_unmap_addr(info, bus)
1055 & ~(MYRI10GE_ALLOC_SIZE - 1)),
1056 MYRI10GE_ALLOC_SIZE, PCI_DMA_FROMDEVICE);
1060 #define MYRI10GE_HLEN 64 /* The number of bytes to copy from a
1061 * page into an skb */
1064 myri10ge_rx_done(struct myri10ge_slice_state *ss, struct myri10ge_rx_buf *rx,
1065 int bytes, int len, __wsum csum)
1067 struct myri10ge_priv *mgp = ss->mgp;
1068 struct sk_buff *skb;
1069 struct skb_frag_struct rx_frags[MYRI10GE_MAX_FRAGS_PER_FRAME];
1070 int i, idx, hlen, remainder;
1071 struct pci_dev *pdev = mgp->pdev;
1072 struct net_device *dev = mgp->dev;
1076 idx = rx->cnt & rx->mask;
1077 va = page_address(rx->info[idx].page) + rx->info[idx].page_offset;
1079 /* Fill skb_frag_struct(s) with data from our receive */
1080 for (i = 0, remainder = len; remainder > 0; i++) {
1081 myri10ge_unmap_rx_page(pdev, &rx->info[idx], bytes);
1082 rx_frags[i].page = rx->info[idx].page;
1083 rx_frags[i].page_offset = rx->info[idx].page_offset;
1084 if (remainder < MYRI10GE_ALLOC_SIZE)
1085 rx_frags[i].size = remainder;
1087 rx_frags[i].size = MYRI10GE_ALLOC_SIZE;
1089 idx = rx->cnt & rx->mask;
1090 remainder -= MYRI10GE_ALLOC_SIZE;
1093 if (mgp->csum_flag && myri10ge_lro) {
1094 rx_frags[0].page_offset += MXGEFW_PAD;
1095 rx_frags[0].size -= MXGEFW_PAD;
1097 lro_receive_frags(&ss->rx_done.lro_mgr, rx_frags,
1099 /* opaque, will come back in get_frag_header */
1100 (void *)(__force unsigned long)csum, csum);
1104 hlen = MYRI10GE_HLEN > len ? len : MYRI10GE_HLEN;
1106 /* allocate an skb to attach the page(s) to. This is done
1107 * after trying LRO, so as to avoid skb allocation overheads */
1109 skb = netdev_alloc_skb(dev, MYRI10GE_HLEN + 16);
1110 if (unlikely(skb == NULL)) {
1111 mgp->stats.rx_dropped++;
1114 put_page(rx_frags[i].page);
1119 /* Attach the pages to the skb, and trim off any padding */
1120 myri10ge_rx_skb_build(skb, va, rx_frags, len, hlen);
1121 if (skb_shinfo(skb)->frags[0].size <= 0) {
1122 put_page(skb_shinfo(skb)->frags[0].page);
1123 skb_shinfo(skb)->nr_frags = 0;
1125 skb->protocol = eth_type_trans(skb, dev);
1127 if (mgp->csum_flag) {
1128 if ((skb->protocol == htons(ETH_P_IP)) ||
1129 (skb->protocol == htons(ETH_P_IPV6))) {
1131 skb->ip_summed = CHECKSUM_COMPLETE;
1133 myri10ge_vlan_ip_csum(skb, csum);
1135 netif_receive_skb(skb);
1136 dev->last_rx = jiffies;
1141 myri10ge_tx_done(struct myri10ge_slice_state *ss, int mcp_index)
1143 struct pci_dev *pdev = ss->mgp->pdev;
1144 struct myri10ge_tx_buf *tx = &ss->tx;
1145 struct sk_buff *skb;
1148 while (tx->pkt_done != mcp_index) {
1149 idx = tx->done & tx->mask;
1150 skb = tx->info[idx].skb;
1153 tx->info[idx].skb = NULL;
1154 if (tx->info[idx].last) {
1156 tx->info[idx].last = 0;
1159 len = pci_unmap_len(&tx->info[idx], len);
1160 pci_unmap_len_set(&tx->info[idx], len, 0);
1162 ss->stats.tx_bytes += skb->len;
1163 ss->stats.tx_packets++;
1164 dev_kfree_skb_irq(skb);
1166 pci_unmap_single(pdev,
1167 pci_unmap_addr(&tx->info[idx],
1172 pci_unmap_page(pdev,
1173 pci_unmap_addr(&tx->info[idx],
1178 /* start the queue if we've stopped it */
1179 if (netif_queue_stopped(ss->dev)
1180 && tx->req - tx->done < (tx->mask >> 1)) {
1182 netif_wake_queue(ss->dev);
1187 myri10ge_clean_rx_done(struct myri10ge_slice_state *ss, int budget)
1189 struct myri10ge_rx_done *rx_done = &ss->rx_done;
1190 struct myri10ge_priv *mgp = ss->mgp;
1191 unsigned long rx_bytes = 0;
1192 unsigned long rx_packets = 0;
1193 unsigned long rx_ok;
1195 int idx = rx_done->idx;
1196 int cnt = rx_done->cnt;
1201 while (rx_done->entry[idx].length != 0 && work_done < budget) {
1202 length = ntohs(rx_done->entry[idx].length);
1203 rx_done->entry[idx].length = 0;
1204 checksum = csum_unfold(rx_done->entry[idx].checksum);
1205 if (length <= mgp->small_bytes)
1206 rx_ok = myri10ge_rx_done(ss, &ss->rx_small,
1210 rx_ok = myri10ge_rx_done(ss, &ss->rx_big,
1213 rx_packets += rx_ok;
1214 rx_bytes += rx_ok * (unsigned long)length;
1216 idx = cnt & (mgp->max_intr_slots - 1);
1221 ss->stats.rx_packets += rx_packets;
1222 ss->stats.rx_bytes += rx_bytes;
1225 lro_flush_all(&rx_done->lro_mgr);
1227 /* restock receive rings if needed */
1228 if (ss->rx_small.fill_cnt - ss->rx_small.cnt < myri10ge_fill_thresh)
1229 myri10ge_alloc_rx_pages(mgp, &ss->rx_small,
1230 mgp->small_bytes + MXGEFW_PAD, 0);
1231 if (ss->rx_big.fill_cnt - ss->rx_big.cnt < myri10ge_fill_thresh)
1232 myri10ge_alloc_rx_pages(mgp, &ss->rx_big, mgp->big_bytes, 0);
1237 static inline void myri10ge_check_statblock(struct myri10ge_priv *mgp)
1239 struct mcp_irq_data *stats = mgp->ss.fw_stats;
1241 if (unlikely(stats->stats_updated)) {
1242 unsigned link_up = ntohl(stats->link_up);
1243 if (mgp->link_state != link_up) {
1244 mgp->link_state = link_up;
1246 if (mgp->link_state == MXGEFW_LINK_UP) {
1247 if (netif_msg_link(mgp))
1249 "myri10ge: %s: link up\n",
1251 netif_carrier_on(mgp->dev);
1252 mgp->link_changes++;
1254 if (netif_msg_link(mgp))
1256 "myri10ge: %s: link %s\n",
1258 (link_up == MXGEFW_LINK_MYRINET ?
1259 "mismatch (Myrinet detected)" :
1261 netif_carrier_off(mgp->dev);
1262 mgp->link_changes++;
1265 if (mgp->rdma_tags_available !=
1266 ntohl(stats->rdma_tags_available)) {
1267 mgp->rdma_tags_available =
1268 ntohl(stats->rdma_tags_available);
1269 printk(KERN_WARNING "myri10ge: %s: RDMA timed out! "
1270 "%d tags left\n", mgp->dev->name,
1271 mgp->rdma_tags_available);
1273 mgp->down_cnt += stats->link_down;
1274 if (stats->link_down)
1275 wake_up(&mgp->down_wq);
1279 static int myri10ge_poll(struct napi_struct *napi, int budget)
1281 struct myri10ge_slice_state *ss =
1282 container_of(napi, struct myri10ge_slice_state, napi);
1283 struct net_device *netdev = ss->mgp->dev;
1286 /* process as many rx events as NAPI will allow */
1287 work_done = myri10ge_clean_rx_done(ss, budget);
1289 if (work_done < budget) {
1290 netif_rx_complete(netdev, napi);
1291 put_be32(htonl(3), ss->irq_claim);
1296 static irqreturn_t myri10ge_intr(int irq, void *arg)
1298 struct myri10ge_slice_state *ss = arg;
1299 struct myri10ge_priv *mgp = ss->mgp;
1300 struct mcp_irq_data *stats = ss->fw_stats;
1301 struct myri10ge_tx_buf *tx = &ss->tx;
1302 u32 send_done_count;
1305 /* make sure it is our IRQ, and that the DMA has finished */
1306 if (unlikely(!stats->valid))
1309 /* low bit indicates receives are present, so schedule
1310 * napi poll handler */
1311 if (stats->valid & 1)
1312 netif_rx_schedule(ss->dev, &ss->napi);
1314 if (!mgp->msi_enabled) {
1315 put_be32(0, mgp->irq_deassert);
1316 if (!myri10ge_deassert_wait)
1322 /* Wait for IRQ line to go low, if using INTx */
1326 /* check for transmit completes and receives */
1327 send_done_count = ntohl(stats->send_done_count);
1328 if (send_done_count != tx->pkt_done)
1329 myri10ge_tx_done(ss, (int)send_done_count);
1330 if (unlikely(i > myri10ge_max_irq_loops)) {
1331 printk(KERN_WARNING "myri10ge: %s: irq stuck?\n",
1334 schedule_work(&mgp->watchdog_work);
1336 if (likely(stats->valid == 0))
1342 myri10ge_check_statblock(mgp);
1344 put_be32(htonl(3), ss->irq_claim + 1);
1345 return (IRQ_HANDLED);
1349 myri10ge_get_settings(struct net_device *netdev, struct ethtool_cmd *cmd)
1351 struct myri10ge_priv *mgp = netdev_priv(netdev);
1355 cmd->autoneg = AUTONEG_DISABLE;
1356 cmd->speed = SPEED_10000;
1357 cmd->duplex = DUPLEX_FULL;
1360 * parse the product code to deterimine the interface type
1361 * (CX4, XFP, Quad Ribbon Fiber) by looking at the character
1362 * after the 3rd dash in the driver's cached copy of the
1363 * EEPROM's product code string.
1365 ptr = mgp->product_code_string;
1367 printk(KERN_ERR "myri10ge: %s: Missing product code\n",
1371 for (i = 0; i < 3; i++, ptr++) {
1372 ptr = strchr(ptr, '-');
1374 printk(KERN_ERR "myri10ge: %s: Invalid product "
1375 "code %s\n", netdev->name,
1376 mgp->product_code_string);
1380 if (*ptr == 'R' || *ptr == 'Q') {
1381 /* We've found either an XFP or quad ribbon fiber */
1382 cmd->port = PORT_FIBRE;
1388 myri10ge_get_drvinfo(struct net_device *netdev, struct ethtool_drvinfo *info)
1390 struct myri10ge_priv *mgp = netdev_priv(netdev);
1392 strlcpy(info->driver, "myri10ge", sizeof(info->driver));
1393 strlcpy(info->version, MYRI10GE_VERSION_STR, sizeof(info->version));
1394 strlcpy(info->fw_version, mgp->fw_version, sizeof(info->fw_version));
1395 strlcpy(info->bus_info, pci_name(mgp->pdev), sizeof(info->bus_info));
1399 myri10ge_get_coalesce(struct net_device *netdev, struct ethtool_coalesce *coal)
1401 struct myri10ge_priv *mgp = netdev_priv(netdev);
1403 coal->rx_coalesce_usecs = mgp->intr_coal_delay;
1408 myri10ge_set_coalesce(struct net_device *netdev, struct ethtool_coalesce *coal)
1410 struct myri10ge_priv *mgp = netdev_priv(netdev);
1412 mgp->intr_coal_delay = coal->rx_coalesce_usecs;
1413 put_be32(htonl(mgp->intr_coal_delay), mgp->intr_coal_delay_ptr);
1418 myri10ge_get_pauseparam(struct net_device *netdev,
1419 struct ethtool_pauseparam *pause)
1421 struct myri10ge_priv *mgp = netdev_priv(netdev);
1424 pause->rx_pause = mgp->pause;
1425 pause->tx_pause = mgp->pause;
1429 myri10ge_set_pauseparam(struct net_device *netdev,
1430 struct ethtool_pauseparam *pause)
1432 struct myri10ge_priv *mgp = netdev_priv(netdev);
1434 if (pause->tx_pause != mgp->pause)
1435 return myri10ge_change_pause(mgp, pause->tx_pause);
1436 if (pause->rx_pause != mgp->pause)
1437 return myri10ge_change_pause(mgp, pause->tx_pause);
1438 if (pause->autoneg != 0)
1444 myri10ge_get_ringparam(struct net_device *netdev,
1445 struct ethtool_ringparam *ring)
1447 struct myri10ge_priv *mgp = netdev_priv(netdev);
1449 ring->rx_mini_max_pending = mgp->ss.rx_small.mask + 1;
1450 ring->rx_max_pending = mgp->ss.rx_big.mask + 1;
1451 ring->rx_jumbo_max_pending = 0;
1452 ring->tx_max_pending = mgp->ss.rx_small.mask + 1;
1453 ring->rx_mini_pending = ring->rx_mini_max_pending;
1454 ring->rx_pending = ring->rx_max_pending;
1455 ring->rx_jumbo_pending = ring->rx_jumbo_max_pending;
1456 ring->tx_pending = ring->tx_max_pending;
1459 static u32 myri10ge_get_rx_csum(struct net_device *netdev)
1461 struct myri10ge_priv *mgp = netdev_priv(netdev);
1469 static int myri10ge_set_rx_csum(struct net_device *netdev, u32 csum_enabled)
1471 struct myri10ge_priv *mgp = netdev_priv(netdev);
1474 mgp->csum_flag = MXGEFW_FLAGS_CKSUM;
1480 static int myri10ge_set_tso(struct net_device *netdev, u32 tso_enabled)
1482 struct myri10ge_priv *mgp = netdev_priv(netdev);
1483 unsigned long flags = mgp->features & (NETIF_F_TSO6 | NETIF_F_TSO);
1486 netdev->features |= flags;
1488 netdev->features &= ~flags;
1492 static const char myri10ge_gstrings_main_stats[][ETH_GSTRING_LEN] = {
1493 "rx_packets", "tx_packets", "rx_bytes", "tx_bytes", "rx_errors",
1494 "tx_errors", "rx_dropped", "tx_dropped", "multicast", "collisions",
1495 "rx_length_errors", "rx_over_errors", "rx_crc_errors",
1496 "rx_frame_errors", "rx_fifo_errors", "rx_missed_errors",
1497 "tx_aborted_errors", "tx_carrier_errors", "tx_fifo_errors",
1498 "tx_heartbeat_errors", "tx_window_errors",
1499 /* device-specific stats */
1500 "tx_boundary", "WC", "irq", "MSI",
1501 "read_dma_bw_MBs", "write_dma_bw_MBs", "read_write_dma_bw_MBs",
1502 "serial_number", "watchdog_resets",
1503 "link_changes", "link_up", "dropped_link_overflow",
1504 "dropped_link_error_or_filtered",
1505 "dropped_pause", "dropped_bad_phy", "dropped_bad_crc32",
1506 "dropped_unicast_filtered", "dropped_multicast_filtered",
1507 "dropped_runt", "dropped_overrun", "dropped_no_small_buffer",
1508 "dropped_no_big_buffer"
1511 static const char myri10ge_gstrings_slice_stats[][ETH_GSTRING_LEN] = {
1512 "----------- slice ---------",
1513 "tx_pkt_start", "tx_pkt_done", "tx_req", "tx_done",
1514 "rx_small_cnt", "rx_big_cnt",
1515 "wake_queue", "stop_queue", "tx_linearized", "LRO aggregated",
1517 "LRO avg aggr", "LRO no_desc"
1520 #define MYRI10GE_NET_STATS_LEN 21
1521 #define MYRI10GE_MAIN_STATS_LEN ARRAY_SIZE(myri10ge_gstrings_main_stats)
1522 #define MYRI10GE_SLICE_STATS_LEN ARRAY_SIZE(myri10ge_gstrings_slice_stats)
1525 myri10ge_get_strings(struct net_device *netdev, u32 stringset, u8 * data)
1527 switch (stringset) {
1529 memcpy(data, *myri10ge_gstrings_main_stats,
1530 sizeof(myri10ge_gstrings_main_stats));
1531 data += sizeof(myri10ge_gstrings_main_stats);
1532 memcpy(data, *myri10ge_gstrings_slice_stats,
1533 sizeof(myri10ge_gstrings_slice_stats));
1534 data += sizeof(myri10ge_gstrings_slice_stats);
1539 static int myri10ge_get_sset_count(struct net_device *netdev, int sset)
1543 return MYRI10GE_MAIN_STATS_LEN + MYRI10GE_SLICE_STATS_LEN;
1550 myri10ge_get_ethtool_stats(struct net_device *netdev,
1551 struct ethtool_stats *stats, u64 * data)
1553 struct myri10ge_priv *mgp = netdev_priv(netdev);
1554 struct myri10ge_slice_state *ss;
1557 for (i = 0; i < MYRI10GE_NET_STATS_LEN; i++)
1558 data[i] = ((unsigned long *)&mgp->stats)[i];
1560 data[i++] = (unsigned int)mgp->tx_boundary;
1561 data[i++] = (unsigned int)mgp->wc_enabled;
1562 data[i++] = (unsigned int)mgp->pdev->irq;
1563 data[i++] = (unsigned int)mgp->msi_enabled;
1564 data[i++] = (unsigned int)mgp->read_dma;
1565 data[i++] = (unsigned int)mgp->write_dma;
1566 data[i++] = (unsigned int)mgp->read_write_dma;
1567 data[i++] = (unsigned int)mgp->serial_number;
1568 data[i++] = (unsigned int)mgp->watchdog_resets;
1569 data[i++] = (unsigned int)mgp->link_changes;
1571 /* firmware stats are useful only in the first slice */
1573 data[i++] = (unsigned int)ntohl(ss->fw_stats->link_up);
1574 data[i++] = (unsigned int)ntohl(ss->fw_stats->dropped_link_overflow);
1576 (unsigned int)ntohl(ss->fw_stats->dropped_link_error_or_filtered);
1577 data[i++] = (unsigned int)ntohl(ss->fw_stats->dropped_pause);
1578 data[i++] = (unsigned int)ntohl(ss->fw_stats->dropped_bad_phy);
1579 data[i++] = (unsigned int)ntohl(ss->fw_stats->dropped_bad_crc32);
1580 data[i++] = (unsigned int)ntohl(ss->fw_stats->dropped_unicast_filtered);
1582 (unsigned int)ntohl(ss->fw_stats->dropped_multicast_filtered);
1583 data[i++] = (unsigned int)ntohl(ss->fw_stats->dropped_runt);
1584 data[i++] = (unsigned int)ntohl(ss->fw_stats->dropped_overrun);
1585 data[i++] = (unsigned int)ntohl(ss->fw_stats->dropped_no_small_buffer);
1586 data[i++] = (unsigned int)ntohl(ss->fw_stats->dropped_no_big_buffer);
1589 data[i++] = (unsigned int)ss->tx.pkt_start;
1590 data[i++] = (unsigned int)ss->tx.pkt_done;
1591 data[i++] = (unsigned int)ss->tx.req;
1592 data[i++] = (unsigned int)ss->tx.done;
1593 data[i++] = (unsigned int)ss->rx_small.cnt;
1594 data[i++] = (unsigned int)ss->rx_big.cnt;
1595 data[i++] = (unsigned int)ss->tx.wake_queue;
1596 data[i++] = (unsigned int)ss->tx.stop_queue;
1597 data[i++] = (unsigned int)ss->tx.linearized;
1598 data[i++] = ss->rx_done.lro_mgr.stats.aggregated;
1599 data[i++] = ss->rx_done.lro_mgr.stats.flushed;
1600 if (ss->rx_done.lro_mgr.stats.flushed)
1601 data[i++] = ss->rx_done.lro_mgr.stats.aggregated /
1602 ss->rx_done.lro_mgr.stats.flushed;
1605 data[i++] = ss->rx_done.lro_mgr.stats.no_desc;
1608 static void myri10ge_set_msglevel(struct net_device *netdev, u32 value)
1610 struct myri10ge_priv *mgp = netdev_priv(netdev);
1611 mgp->msg_enable = value;
1614 static u32 myri10ge_get_msglevel(struct net_device *netdev)
1616 struct myri10ge_priv *mgp = netdev_priv(netdev);
1617 return mgp->msg_enable;
1620 static const struct ethtool_ops myri10ge_ethtool_ops = {
1621 .get_settings = myri10ge_get_settings,
1622 .get_drvinfo = myri10ge_get_drvinfo,
1623 .get_coalesce = myri10ge_get_coalesce,
1624 .set_coalesce = myri10ge_set_coalesce,
1625 .get_pauseparam = myri10ge_get_pauseparam,
1626 .set_pauseparam = myri10ge_set_pauseparam,
1627 .get_ringparam = myri10ge_get_ringparam,
1628 .get_rx_csum = myri10ge_get_rx_csum,
1629 .set_rx_csum = myri10ge_set_rx_csum,
1630 .set_tx_csum = ethtool_op_set_tx_hw_csum,
1631 .set_sg = ethtool_op_set_sg,
1632 .set_tso = myri10ge_set_tso,
1633 .get_link = ethtool_op_get_link,
1634 .get_strings = myri10ge_get_strings,
1635 .get_sset_count = myri10ge_get_sset_count,
1636 .get_ethtool_stats = myri10ge_get_ethtool_stats,
1637 .set_msglevel = myri10ge_set_msglevel,
1638 .get_msglevel = myri10ge_get_msglevel
1641 static int myri10ge_allocate_rings(struct myri10ge_slice_state *ss)
1643 struct myri10ge_priv *mgp = ss->mgp;
1644 struct myri10ge_cmd cmd;
1645 struct net_device *dev = mgp->dev;
1646 int tx_ring_size, rx_ring_size;
1647 int tx_ring_entries, rx_ring_entries;
1651 /* get ring sizes */
1652 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_GET_SEND_RING_SIZE, &cmd, 0);
1653 tx_ring_size = cmd.data0;
1654 status |= myri10ge_send_cmd(mgp, MXGEFW_CMD_GET_RX_RING_SIZE, &cmd, 0);
1657 rx_ring_size = cmd.data0;
1659 tx_ring_entries = tx_ring_size / sizeof(struct mcp_kreq_ether_send);
1660 rx_ring_entries = rx_ring_size / sizeof(struct mcp_dma_addr);
1661 ss->tx.mask = tx_ring_entries - 1;
1662 ss->rx_small.mask = ss->rx_big.mask = rx_ring_entries - 1;
1666 /* allocate the host shadow rings */
1668 bytes = 8 + (MYRI10GE_MAX_SEND_DESC_TSO + 4)
1669 * sizeof(*ss->tx.req_list);
1670 ss->tx.req_bytes = kzalloc(bytes, GFP_KERNEL);
1671 if (ss->tx.req_bytes == NULL)
1672 goto abort_with_nothing;
1674 /* ensure req_list entries are aligned to 8 bytes */
1675 ss->tx.req_list = (struct mcp_kreq_ether_send *)
1676 ALIGN((unsigned long)ss->tx.req_bytes, 8);
1678 bytes = rx_ring_entries * sizeof(*ss->rx_small.shadow);
1679 ss->rx_small.shadow = kzalloc(bytes, GFP_KERNEL);
1680 if (ss->rx_small.shadow == NULL)
1681 goto abort_with_tx_req_bytes;
1683 bytes = rx_ring_entries * sizeof(*ss->rx_big.shadow);
1684 ss->rx_big.shadow = kzalloc(bytes, GFP_KERNEL);
1685 if (ss->rx_big.shadow == NULL)
1686 goto abort_with_rx_small_shadow;
1688 /* allocate the host info rings */
1690 bytes = tx_ring_entries * sizeof(*ss->tx.info);
1691 ss->tx.info = kzalloc(bytes, GFP_KERNEL);
1692 if (ss->tx.info == NULL)
1693 goto abort_with_rx_big_shadow;
1695 bytes = rx_ring_entries * sizeof(*ss->rx_small.info);
1696 ss->rx_small.info = kzalloc(bytes, GFP_KERNEL);
1697 if (ss->rx_small.info == NULL)
1698 goto abort_with_tx_info;
1700 bytes = rx_ring_entries * sizeof(*ss->rx_big.info);
1701 ss->rx_big.info = kzalloc(bytes, GFP_KERNEL);
1702 if (ss->rx_big.info == NULL)
1703 goto abort_with_rx_small_info;
1705 /* Fill the receive rings */
1707 ss->rx_small.cnt = 0;
1708 ss->rx_big.fill_cnt = 0;
1709 ss->rx_small.fill_cnt = 0;
1710 ss->rx_small.page_offset = MYRI10GE_ALLOC_SIZE;
1711 ss->rx_big.page_offset = MYRI10GE_ALLOC_SIZE;
1712 ss->rx_small.watchdog_needed = 0;
1713 ss->rx_big.watchdog_needed = 0;
1714 myri10ge_alloc_rx_pages(mgp, &ss->rx_small,
1715 mgp->small_bytes + MXGEFW_PAD, 0);
1717 if (ss->rx_small.fill_cnt < ss->rx_small.mask + 1) {
1718 printk(KERN_ERR "myri10ge: %s: alloced only %d small bufs\n",
1719 dev->name, ss->rx_small.fill_cnt);
1720 goto abort_with_rx_small_ring;
1723 myri10ge_alloc_rx_pages(mgp, &ss->rx_big, mgp->big_bytes, 0);
1724 if (ss->rx_big.fill_cnt < ss->rx_big.mask + 1) {
1725 printk(KERN_ERR "myri10ge: %s: alloced only %d big bufs\n",
1726 dev->name, ss->rx_big.fill_cnt);
1727 goto abort_with_rx_big_ring;
1732 abort_with_rx_big_ring:
1733 for (i = ss->rx_big.cnt; i < ss->rx_big.fill_cnt; i++) {
1734 int idx = i & ss->rx_big.mask;
1735 myri10ge_unmap_rx_page(mgp->pdev, &ss->rx_big.info[idx],
1737 put_page(ss->rx_big.info[idx].page);
1740 abort_with_rx_small_ring:
1741 for (i = ss->rx_small.cnt; i < ss->rx_small.fill_cnt; i++) {
1742 int idx = i & ss->rx_small.mask;
1743 myri10ge_unmap_rx_page(mgp->pdev, &ss->rx_small.info[idx],
1744 mgp->small_bytes + MXGEFW_PAD);
1745 put_page(ss->rx_small.info[idx].page);
1748 kfree(ss->rx_big.info);
1750 abort_with_rx_small_info:
1751 kfree(ss->rx_small.info);
1756 abort_with_rx_big_shadow:
1757 kfree(ss->rx_big.shadow);
1759 abort_with_rx_small_shadow:
1760 kfree(ss->rx_small.shadow);
1762 abort_with_tx_req_bytes:
1763 kfree(ss->tx.req_bytes);
1764 ss->tx.req_bytes = NULL;
1765 ss->tx.req_list = NULL;
1771 static void myri10ge_free_rings(struct myri10ge_slice_state *ss)
1773 struct myri10ge_priv *mgp = ss->mgp;
1774 struct sk_buff *skb;
1775 struct myri10ge_tx_buf *tx;
1778 for (i = ss->rx_big.cnt; i < ss->rx_big.fill_cnt; i++) {
1779 idx = i & ss->rx_big.mask;
1780 if (i == ss->rx_big.fill_cnt - 1)
1781 ss->rx_big.info[idx].page_offset = MYRI10GE_ALLOC_SIZE;
1782 myri10ge_unmap_rx_page(mgp->pdev, &ss->rx_big.info[idx],
1784 put_page(ss->rx_big.info[idx].page);
1787 for (i = ss->rx_small.cnt; i < ss->rx_small.fill_cnt; i++) {
1788 idx = i & ss->rx_small.mask;
1789 if (i == ss->rx_small.fill_cnt - 1)
1790 ss->rx_small.info[idx].page_offset =
1791 MYRI10GE_ALLOC_SIZE;
1792 myri10ge_unmap_rx_page(mgp->pdev, &ss->rx_small.info[idx],
1793 mgp->small_bytes + MXGEFW_PAD);
1794 put_page(ss->rx_small.info[idx].page);
1797 while (tx->done != tx->req) {
1798 idx = tx->done & tx->mask;
1799 skb = tx->info[idx].skb;
1802 tx->info[idx].skb = NULL;
1804 len = pci_unmap_len(&tx->info[idx], len);
1805 pci_unmap_len_set(&tx->info[idx], len, 0);
1807 ss->stats.tx_dropped++;
1808 dev_kfree_skb_any(skb);
1810 pci_unmap_single(mgp->pdev,
1811 pci_unmap_addr(&tx->info[idx],
1816 pci_unmap_page(mgp->pdev,
1817 pci_unmap_addr(&tx->info[idx],
1822 kfree(ss->rx_big.info);
1824 kfree(ss->rx_small.info);
1828 kfree(ss->rx_big.shadow);
1830 kfree(ss->rx_small.shadow);
1832 kfree(ss->tx.req_bytes);
1833 ss->tx.req_bytes = NULL;
1834 ss->tx.req_list = NULL;
1837 static int myri10ge_request_irq(struct myri10ge_priv *mgp)
1839 struct pci_dev *pdev = mgp->pdev;
1843 status = pci_enable_msi(pdev);
1846 "Error %d setting up MSI; falling back to xPIC\n",
1849 mgp->msi_enabled = 1;
1851 mgp->msi_enabled = 0;
1853 status = request_irq(pdev->irq, myri10ge_intr, IRQF_SHARED,
1854 mgp->dev->name, mgp);
1856 dev_err(&pdev->dev, "failed to allocate IRQ\n");
1857 if (mgp->msi_enabled)
1858 pci_disable_msi(pdev);
1863 static void myri10ge_free_irq(struct myri10ge_priv *mgp)
1865 struct pci_dev *pdev = mgp->pdev;
1867 free_irq(pdev->irq, mgp);
1868 if (mgp->msi_enabled)
1869 pci_disable_msi(pdev);
1873 myri10ge_get_frag_header(struct skb_frag_struct *frag, void **mac_hdr,
1874 void **ip_hdr, void **tcpudp_hdr,
1875 u64 * hdr_flags, void *priv)
1878 struct vlan_ethhdr *veh;
1880 u8 *va = page_address(frag->page) + frag->page_offset;
1881 unsigned long ll_hlen;
1882 /* passed opaque through lro_receive_frags() */
1883 __wsum csum = (__force __wsum) (unsigned long)priv;
1885 /* find the mac header, aborting if not IPv4 */
1887 eh = (struct ethhdr *)va;
1890 if (eh->h_proto != htons(ETH_P_IP)) {
1891 if (eh->h_proto == htons(ETH_P_8021Q)) {
1892 veh = (struct vlan_ethhdr *)va;
1893 if (veh->h_vlan_encapsulated_proto != htons(ETH_P_IP))
1896 ll_hlen += VLAN_HLEN;
1899 * HW checksum starts ETH_HLEN bytes into
1900 * frame, so we must subtract off the VLAN
1901 * header's checksum before csum can be used
1903 csum = csum_sub(csum, csum_partial(va + ETH_HLEN,
1909 *hdr_flags = LRO_IPV4;
1911 iph = (struct iphdr *)(va + ll_hlen);
1913 if (iph->protocol != IPPROTO_TCP)
1915 *hdr_flags |= LRO_TCP;
1916 *tcpudp_hdr = (u8 *) (*ip_hdr) + (iph->ihl << 2);
1918 /* verify the IP checksum */
1919 if (unlikely(ip_fast_csum((u8 *) iph, iph->ihl)))
1922 /* verify the checksum */
1923 if (unlikely(csum_tcpudp_magic(iph->saddr, iph->daddr,
1924 ntohs(iph->tot_len) - (iph->ihl << 2),
1925 IPPROTO_TCP, csum)))
1932 static int myri10ge_get_txrx(struct myri10ge_priv *mgp, int slice)
1934 struct myri10ge_cmd cmd;
1935 struct myri10ge_slice_state *ss;
1938 ss = &mgp->ss[slice];
1939 cmd.data0 = 0; /* single slice for now */
1940 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_GET_SEND_OFFSET, &cmd, 0);
1941 ss->tx.lanai = (struct mcp_kreq_ether_send __iomem *)
1942 (mgp->sram + cmd.data0);
1945 status |= myri10ge_send_cmd(mgp, MXGEFW_CMD_GET_SMALL_RX_OFFSET,
1947 ss->rx_small.lanai = (struct mcp_kreq_ether_recv __iomem *)
1948 (mgp->sram + cmd.data0);
1951 status |= myri10ge_send_cmd(mgp, MXGEFW_CMD_GET_BIG_RX_OFFSET, &cmd, 0);
1952 ss->rx_big.lanai = (struct mcp_kreq_ether_recv __iomem *)
1953 (mgp->sram + cmd.data0);
1955 if (myri10ge_wcfifo && mgp->wc_enabled) {
1956 ss->tx.wc_fifo = (u8 __iomem *)
1957 mgp->sram + MXGEFW_ETH_SEND_4 + 64 * slice;
1958 ss->rx_small.wc_fifo = (u8 __iomem *)
1959 mgp->sram + MXGEFW_ETH_RECV_SMALL + 64 * slice;
1960 ss->rx_big.wc_fifo = (u8 __iomem *)
1961 mgp->sram + MXGEFW_ETH_RECV_BIG + 64 * slice;
1963 ss->tx.wc_fifo = NULL;
1964 ss->rx_small.wc_fifo = NULL;
1965 ss->rx_big.wc_fifo = NULL;
1971 static int myri10ge_set_stats(struct myri10ge_priv *mgp, int slice)
1973 struct myri10ge_cmd cmd;
1974 struct myri10ge_slice_state *ss;
1977 ss = &mgp->ss[slice];
1978 cmd.data0 = MYRI10GE_LOWPART_TO_U32(ss->fw_stats_bus);
1979 cmd.data1 = MYRI10GE_HIGHPART_TO_U32(ss->fw_stats_bus);
1980 cmd.data2 = sizeof(struct mcp_irq_data);
1981 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_SET_STATS_DMA_V2, &cmd, 0);
1982 if (status == -ENOSYS) {
1983 dma_addr_t bus = ss->fw_stats_bus;
1986 bus += offsetof(struct mcp_irq_data, send_done_count);
1987 cmd.data0 = MYRI10GE_LOWPART_TO_U32(bus);
1988 cmd.data1 = MYRI10GE_HIGHPART_TO_U32(bus);
1989 status = myri10ge_send_cmd(mgp,
1990 MXGEFW_CMD_SET_STATS_DMA_OBSOLETE,
1992 /* Firmware cannot support multicast without STATS_DMA_V2 */
1993 mgp->fw_multicast_support = 0;
1995 mgp->fw_multicast_support = 1;
2001 static int myri10ge_open(struct net_device *dev)
2003 struct myri10ge_priv *mgp = netdev_priv(dev);
2004 struct myri10ge_cmd cmd;
2005 struct net_lro_mgr *lro_mgr;
2006 int status, big_pow2;
2008 if (mgp->running != MYRI10GE_ETH_STOPPED)
2011 mgp->running = MYRI10GE_ETH_STARTING;
2012 status = myri10ge_reset(mgp);
2014 printk(KERN_ERR "myri10ge: %s: failed reset\n", dev->name);
2015 goto abort_with_nothing;
2018 status = myri10ge_request_irq(mgp);
2020 goto abort_with_nothing;
2022 /* decide what small buffer size to use. For good TCP rx
2023 * performance, it is important to not receive 1514 byte
2024 * frames into jumbo buffers, as it confuses the socket buffer
2025 * accounting code, leading to drops and erratic performance.
2028 if (dev->mtu <= ETH_DATA_LEN)
2029 /* enough for a TCP header */
2030 mgp->small_bytes = (128 > SMP_CACHE_BYTES)
2031 ? (128 - MXGEFW_PAD)
2032 : (SMP_CACHE_BYTES - MXGEFW_PAD);
2034 /* enough for a vlan encapsulated ETH_DATA_LEN frame */
2035 mgp->small_bytes = VLAN_ETH_FRAME_LEN;
2037 /* Override the small buffer size? */
2038 if (myri10ge_small_bytes > 0)
2039 mgp->small_bytes = myri10ge_small_bytes;
2041 /* get the lanai pointers to the send and receive rings */
2043 status |= myri10ge_send_cmd(mgp, MXGEFW_CMD_GET_SEND_OFFSET, &cmd, 0);
2045 (struct mcp_kreq_ether_send __iomem *)(mgp->sram + cmd.data0);
2048 myri10ge_send_cmd(mgp, MXGEFW_CMD_GET_SMALL_RX_OFFSET, &cmd, 0);
2049 mgp->ss.rx_small.lanai =
2050 (struct mcp_kreq_ether_recv __iomem *)(mgp->sram + cmd.data0);
2052 status |= myri10ge_send_cmd(mgp, MXGEFW_CMD_GET_BIG_RX_OFFSET, &cmd, 0);
2053 mgp->ss.rx_big.lanai =
2054 (struct mcp_kreq_ether_recv __iomem *)(mgp->sram + cmd.data0);
2058 "myri10ge: %s: failed to get ring sizes or locations\n",
2060 mgp->running = MYRI10GE_ETH_STOPPED;
2061 goto abort_with_irq;
2064 if (myri10ge_wcfifo && mgp->wc_enabled) {
2065 mgp->ss.tx.wc_fifo = (u8 __iomem *) mgp->sram + MXGEFW_ETH_SEND_4;
2066 mgp->ss.rx_small.wc_fifo =
2067 (u8 __iomem *) mgp->sram + MXGEFW_ETH_RECV_SMALL;
2068 mgp->ss.rx_big.wc_fifo =
2069 (u8 __iomem *) mgp->sram + MXGEFW_ETH_RECV_BIG;
2071 mgp->ss.tx.wc_fifo = NULL;
2072 mgp->ss.rx_small.wc_fifo = NULL;
2073 mgp->ss.rx_big.wc_fifo = NULL;
2076 /* Firmware needs the big buff size as a power of 2. Lie and
2077 * tell him the buffer is larger, because we only use 1
2078 * buffer/pkt, and the mtu will prevent overruns.
2080 big_pow2 = dev->mtu + ETH_HLEN + VLAN_HLEN + MXGEFW_PAD;
2081 if (big_pow2 < MYRI10GE_ALLOC_SIZE / 2) {
2082 while (!is_power_of_2(big_pow2))
2084 mgp->big_bytes = dev->mtu + ETH_HLEN + VLAN_HLEN + MXGEFW_PAD;
2086 big_pow2 = MYRI10GE_ALLOC_SIZE;
2087 mgp->big_bytes = big_pow2;
2090 status = myri10ge_allocate_rings(&mgp->ss);
2092 goto abort_with_irq;
2094 /* now give firmware buffers sizes, and MTU */
2095 cmd.data0 = dev->mtu + ETH_HLEN + VLAN_HLEN;
2096 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_SET_MTU, &cmd, 0);
2097 cmd.data0 = mgp->small_bytes;
2099 myri10ge_send_cmd(mgp, MXGEFW_CMD_SET_SMALL_BUFFER_SIZE, &cmd, 0);
2100 cmd.data0 = big_pow2;
2102 myri10ge_send_cmd(mgp, MXGEFW_CMD_SET_BIG_BUFFER_SIZE, &cmd, 0);
2104 printk(KERN_ERR "myri10ge: %s: Couldn't set buffer sizes\n",
2106 goto abort_with_rings;
2109 cmd.data0 = MYRI10GE_LOWPART_TO_U32(mgp->ss.fw_stats_bus);
2110 cmd.data1 = MYRI10GE_HIGHPART_TO_U32(mgp->ss.fw_stats_bus);
2111 cmd.data2 = sizeof(struct mcp_irq_data);
2112 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_SET_STATS_DMA_V2, &cmd, 0);
2113 if (status == -ENOSYS) {
2114 dma_addr_t bus = mgp->ss.fw_stats_bus;
2115 bus += offsetof(struct mcp_irq_data, send_done_count);
2116 cmd.data0 = MYRI10GE_LOWPART_TO_U32(bus);
2117 cmd.data1 = MYRI10GE_HIGHPART_TO_U32(bus);
2118 status = myri10ge_send_cmd(mgp,
2119 MXGEFW_CMD_SET_STATS_DMA_OBSOLETE,
2121 /* Firmware cannot support multicast without STATS_DMA_V2 */
2122 mgp->fw_multicast_support = 0;
2124 mgp->fw_multicast_support = 1;
2127 printk(KERN_ERR "myri10ge: %s: Couldn't set stats DMA\n",
2129 goto abort_with_rings;
2132 mgp->link_state = ~0U;
2133 mgp->rdma_tags_available = 15;
2135 lro_mgr = &mgp->ss.rx_done.lro_mgr;
2137 lro_mgr->features = LRO_F_NAPI;
2138 lro_mgr->ip_summed = CHECKSUM_COMPLETE;
2139 lro_mgr->ip_summed_aggr = CHECKSUM_UNNECESSARY;
2140 lro_mgr->max_desc = MYRI10GE_MAX_LRO_DESCRIPTORS;
2141 lro_mgr->lro_arr = mgp->ss.rx_done.lro_desc;
2142 lro_mgr->get_frag_header = myri10ge_get_frag_header;
2143 lro_mgr->max_aggr = myri10ge_lro_max_pkts;
2144 lro_mgr->frag_align_pad = 2;
2145 if (lro_mgr->max_aggr > MAX_SKB_FRAGS)
2146 lro_mgr->max_aggr = MAX_SKB_FRAGS;
2148 napi_enable(&mgp->ss.napi); /* must happen prior to any irq */
2150 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_ETHERNET_UP, &cmd, 0);
2152 printk(KERN_ERR "myri10ge: %s: Couldn't bring up link\n",
2154 goto abort_with_rings;
2157 mgp->ss.tx.wake_queue = 0;
2158 mgp->ss.tx.stop_queue = 0;
2159 mgp->running = MYRI10GE_ETH_RUNNING;
2160 mgp->watchdog_timer.expires = jiffies + myri10ge_watchdog_timeout * HZ;
2161 add_timer(&mgp->watchdog_timer);
2162 netif_wake_queue(dev);
2166 myri10ge_free_rings(&mgp->ss);
2169 myri10ge_free_irq(mgp);
2172 mgp->running = MYRI10GE_ETH_STOPPED;
2176 static int myri10ge_close(struct net_device *dev)
2178 struct myri10ge_priv *mgp = netdev_priv(dev);
2179 struct myri10ge_cmd cmd;
2180 int status, old_down_cnt;
2182 if (mgp->running != MYRI10GE_ETH_RUNNING)
2185 if (mgp->ss.tx.req_bytes == NULL)
2188 del_timer_sync(&mgp->watchdog_timer);
2189 mgp->running = MYRI10GE_ETH_STOPPING;
2190 napi_disable(&mgp->ss.napi);
2191 netif_carrier_off(dev);
2192 netif_stop_queue(dev);
2193 old_down_cnt = mgp->down_cnt;
2195 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_ETHERNET_DOWN, &cmd, 0);
2197 printk(KERN_ERR "myri10ge: %s: Couldn't bring down link\n",
2200 wait_event_timeout(mgp->down_wq, old_down_cnt != mgp->down_cnt, HZ);
2201 if (old_down_cnt == mgp->down_cnt)
2202 printk(KERN_ERR "myri10ge: %s never got down irq\n", dev->name);
2204 netif_tx_disable(dev);
2205 myri10ge_free_irq(mgp);
2206 myri10ge_free_rings(&mgp->ss);
2208 mgp->running = MYRI10GE_ETH_STOPPED;
2212 /* copy an array of struct mcp_kreq_ether_send's to the mcp. Copy
2213 * backwards one at a time and handle ring wraps */
2216 myri10ge_submit_req_backwards(struct myri10ge_tx_buf *tx,
2217 struct mcp_kreq_ether_send *src, int cnt)
2219 int idx, starting_slot;
2220 starting_slot = tx->req;
2223 idx = (starting_slot + cnt) & tx->mask;
2224 myri10ge_pio_copy(&tx->lanai[idx], &src[cnt], sizeof(*src));
2230 * copy an array of struct mcp_kreq_ether_send's to the mcp. Copy
2231 * at most 32 bytes at a time, so as to avoid involving the software
2232 * pio handler in the nic. We re-write the first segment's flags
2233 * to mark them valid only after writing the entire chain.
2237 myri10ge_submit_req(struct myri10ge_tx_buf *tx, struct mcp_kreq_ether_send *src,
2241 struct mcp_kreq_ether_send __iomem *dstp, *dst;
2242 struct mcp_kreq_ether_send *srcp;
2245 idx = tx->req & tx->mask;
2247 last_flags = src->flags;
2250 dst = dstp = &tx->lanai[idx];
2253 if ((idx + cnt) < tx->mask) {
2254 for (i = 0; i < (cnt - 1); i += 2) {
2255 myri10ge_pio_copy(dstp, srcp, 2 * sizeof(*src));
2256 mb(); /* force write every 32 bytes */
2261 /* submit all but the first request, and ensure
2262 * that it is submitted below */
2263 myri10ge_submit_req_backwards(tx, src, cnt);
2267 /* submit the first request */
2268 myri10ge_pio_copy(dstp, srcp, sizeof(*src));
2269 mb(); /* barrier before setting valid flag */
2272 /* re-write the last 32-bits with the valid flags */
2273 src->flags = last_flags;
2274 put_be32(*((__be32 *) src + 3), (__be32 __iomem *) dst + 3);
2280 myri10ge_submit_req_wc(struct myri10ge_tx_buf *tx,
2281 struct mcp_kreq_ether_send *src, int cnt)
2286 myri10ge_pio_copy(tx->wc_fifo, src, 64);
2292 /* pad it to 64 bytes. The src is 64 bytes bigger than it
2293 * needs to be so that we don't overrun it */
2294 myri10ge_pio_copy(tx->wc_fifo + MXGEFW_ETH_SEND_OFFSET(cnt),
2301 * Transmit a packet. We need to split the packet so that a single
2302 * segment does not cross myri10ge->tx_boundary, so this makes segment
2303 * counting tricky. So rather than try to count segments up front, we
2304 * just give up if there are too few segments to hold a reasonably
2305 * fragmented packet currently available. If we run
2306 * out of segments while preparing a packet for DMA, we just linearize
2310 static int myri10ge_xmit(struct sk_buff *skb, struct net_device *dev)
2312 struct myri10ge_priv *mgp = netdev_priv(dev);
2313 struct myri10ge_slice_state *ss;
2314 struct mcp_kreq_ether_send *req;
2315 struct myri10ge_tx_buf *tx;
2316 struct skb_frag_struct *frag;
2319 __be32 high_swapped;
2321 int idx, last_idx, avail, frag_cnt, frag_idx, count, mss, max_segments;
2322 u16 pseudo_hdr_offset, cksum_offset;
2323 int cum_len, seglen, boundary, rdma_count;
2326 /* always transmit through slot 0 */
2331 avail = tx->mask - 1 - (tx->req - tx->done);
2334 max_segments = MXGEFW_MAX_SEND_DESC;
2336 if (skb_is_gso(skb)) {
2337 mss = skb_shinfo(skb)->gso_size;
2338 max_segments = MYRI10GE_MAX_SEND_DESC_TSO;
2341 if ((unlikely(avail < max_segments))) {
2342 /* we are out of transmit resources */
2344 netif_stop_queue(dev);
2348 /* Setup checksum offloading, if needed */
2350 pseudo_hdr_offset = 0;
2352 flags = (MXGEFW_FLAGS_NO_TSO | MXGEFW_FLAGS_FIRST);
2353 if (likely(skb->ip_summed == CHECKSUM_PARTIAL)) {
2354 cksum_offset = skb_transport_offset(skb);
2355 pseudo_hdr_offset = cksum_offset + skb->csum_offset;
2356 /* If the headers are excessively large, then we must
2357 * fall back to a software checksum */
2358 if (unlikely(!mss && (cksum_offset > 255 ||
2359 pseudo_hdr_offset > 127))) {
2360 if (skb_checksum_help(skb))
2363 pseudo_hdr_offset = 0;
2365 odd_flag = MXGEFW_FLAGS_ALIGN_ODD;
2366 flags |= MXGEFW_FLAGS_CKSUM;
2372 if (mss) { /* TSO */
2373 /* this removes any CKSUM flag from before */
2374 flags = (MXGEFW_FLAGS_TSO_HDR | MXGEFW_FLAGS_FIRST);
2376 /* negative cum_len signifies to the
2377 * send loop that we are still in the
2378 * header portion of the TSO packet.
2379 * TSO header can be at most 1KB long */
2380 cum_len = -(skb_transport_offset(skb) + tcp_hdrlen(skb));
2382 /* for IPv6 TSO, the checksum offset stores the
2383 * TCP header length, to save the firmware from
2384 * the need to parse the headers */
2385 if (skb_is_gso_v6(skb)) {
2386 cksum_offset = tcp_hdrlen(skb);
2387 /* Can only handle headers <= max_tso6 long */
2388 if (unlikely(-cum_len > mgp->max_tso6))
2389 return myri10ge_sw_tso(skb, dev);
2391 /* for TSO, pseudo_hdr_offset holds mss.
2392 * The firmware figures out where to put
2393 * the checksum by parsing the header. */
2394 pseudo_hdr_offset = mss;
2396 /* Mark small packets, and pad out tiny packets */
2397 if (skb->len <= MXGEFW_SEND_SMALL_SIZE) {
2398 flags |= MXGEFW_FLAGS_SMALL;
2400 /* pad frames to at least ETH_ZLEN bytes */
2401 if (unlikely(skb->len < ETH_ZLEN)) {
2402 if (skb_padto(skb, ETH_ZLEN)) {
2403 /* The packet is gone, so we must
2405 ss->stats.tx_dropped += 1;
2408 /* adjust the len to account for the zero pad
2409 * so that the nic can know how long it is */
2410 skb->len = ETH_ZLEN;
2414 /* map the skb for DMA */
2415 len = skb->len - skb->data_len;
2416 idx = tx->req & tx->mask;
2417 tx->info[idx].skb = skb;
2418 bus = pci_map_single(mgp->pdev, skb->data, len, PCI_DMA_TODEVICE);
2419 pci_unmap_addr_set(&tx->info[idx], bus, bus);
2420 pci_unmap_len_set(&tx->info[idx], len, len);
2422 frag_cnt = skb_shinfo(skb)->nr_frags;
2427 /* "rdma_count" is the number of RDMAs belonging to the
2428 * current packet BEFORE the current send request. For
2429 * non-TSO packets, this is equal to "count".
2430 * For TSO packets, rdma_count needs to be reset
2431 * to 0 after a segment cut.
2433 * The rdma_count field of the send request is
2434 * the number of RDMAs of the packet starting at
2435 * that request. For TSO send requests with one ore more cuts
2436 * in the middle, this is the number of RDMAs starting
2437 * after the last cut in the request. All previous
2438 * segments before the last cut implicitly have 1 RDMA.
2440 * Since the number of RDMAs is not known beforehand,
2441 * it must be filled-in retroactively - after each
2442 * segmentation cut or at the end of the entire packet.
2446 /* Break the SKB or Fragment up into pieces which
2447 * do not cross mgp->tx_boundary */
2448 low = MYRI10GE_LOWPART_TO_U32(bus);
2449 high_swapped = htonl(MYRI10GE_HIGHPART_TO_U32(bus));
2454 if (unlikely(count == max_segments))
2455 goto abort_linearize;
2458 (low + mgp->tx_boundary) & ~(mgp->tx_boundary - 1);
2459 seglen = boundary - low;
2462 flags_next = flags & ~MXGEFW_FLAGS_FIRST;
2463 cum_len_next = cum_len + seglen;
2464 if (mss) { /* TSO */
2465 (req - rdma_count)->rdma_count = rdma_count + 1;
2467 if (likely(cum_len >= 0)) { /* payload */
2468 int next_is_first, chop;
2470 chop = (cum_len_next > mss);
2471 cum_len_next = cum_len_next % mss;
2472 next_is_first = (cum_len_next == 0);
2473 flags |= chop * MXGEFW_FLAGS_TSO_CHOP;
2474 flags_next |= next_is_first *
2476 rdma_count |= -(chop | next_is_first);
2477 rdma_count += chop & !next_is_first;
2478 } else if (likely(cum_len_next >= 0)) { /* header ends */
2484 small = (mss <= MXGEFW_SEND_SMALL_SIZE);
2485 flags_next = MXGEFW_FLAGS_TSO_PLD |
2486 MXGEFW_FLAGS_FIRST |
2487 (small * MXGEFW_FLAGS_SMALL);
2490 req->addr_high = high_swapped;
2491 req->addr_low = htonl(low);
2492 req->pseudo_hdr_offset = htons(pseudo_hdr_offset);
2493 req->pad = 0; /* complete solid 16-byte block; does this matter? */
2494 req->rdma_count = 1;
2495 req->length = htons(seglen);
2496 req->cksum_offset = cksum_offset;
2497 req->flags = flags | ((cum_len & 1) * odd_flag);
2501 cum_len = cum_len_next;
2506 if (cksum_offset != 0 && !(mss && skb_is_gso_v6(skb))) {
2507 if (unlikely(cksum_offset > seglen))
2508 cksum_offset -= seglen;
2513 if (frag_idx == frag_cnt)
2516 /* map next fragment for DMA */
2517 idx = (count + tx->req) & tx->mask;
2518 frag = &skb_shinfo(skb)->frags[frag_idx];
2521 bus = pci_map_page(mgp->pdev, frag->page, frag->page_offset,
2522 len, PCI_DMA_TODEVICE);
2523 pci_unmap_addr_set(&tx->info[idx], bus, bus);
2524 pci_unmap_len_set(&tx->info[idx], len, len);
2527 (req - rdma_count)->rdma_count = rdma_count;
2531 req->flags |= MXGEFW_FLAGS_TSO_LAST;
2532 } while (!(req->flags & (MXGEFW_FLAGS_TSO_CHOP |
2533 MXGEFW_FLAGS_FIRST)));
2534 idx = ((count - 1) + tx->req) & tx->mask;
2535 tx->info[idx].last = 1;
2536 if (tx->wc_fifo == NULL)
2537 myri10ge_submit_req(tx, tx->req_list, count);
2539 myri10ge_submit_req_wc(tx, tx->req_list, count);
2541 if ((avail - count) < MXGEFW_MAX_SEND_DESC) {
2543 netif_stop_queue(dev);
2545 dev->trans_start = jiffies;
2549 /* Free any DMA resources we've alloced and clear out the skb
2550 * slot so as to not trip up assertions, and to avoid a
2551 * double-free if linearizing fails */
2553 last_idx = (idx + 1) & tx->mask;
2554 idx = tx->req & tx->mask;
2555 tx->info[idx].skb = NULL;
2557 len = pci_unmap_len(&tx->info[idx], len);
2559 if (tx->info[idx].skb != NULL)
2560 pci_unmap_single(mgp->pdev,
2561 pci_unmap_addr(&tx->info[idx],
2565 pci_unmap_page(mgp->pdev,
2566 pci_unmap_addr(&tx->info[idx],
2569 pci_unmap_len_set(&tx->info[idx], len, 0);
2570 tx->info[idx].skb = NULL;
2572 idx = (idx + 1) & tx->mask;
2573 } while (idx != last_idx);
2574 if (skb_is_gso(skb)) {
2576 "myri10ge: %s: TSO but wanted to linearize?!?!?\n",
2581 if (skb_linearize(skb))
2588 dev_kfree_skb_any(skb);
2589 ss->stats.tx_dropped += 1;
2594 static int myri10ge_sw_tso(struct sk_buff *skb, struct net_device *dev)
2596 struct sk_buff *segs, *curr;
2597 struct myri10ge_priv *mgp = netdev_priv(dev);
2600 segs = skb_gso_segment(skb, dev->features & ~NETIF_F_TSO6);
2608 status = myri10ge_xmit(curr, dev);
2610 dev_kfree_skb_any(curr);
2615 dev_kfree_skb_any(segs);
2620 dev_kfree_skb_any(skb);
2624 dev_kfree_skb_any(skb);
2625 mgp->stats.tx_dropped += 1;
2629 static struct net_device_stats *myri10ge_get_stats(struct net_device *dev)
2631 struct myri10ge_priv *mgp = netdev_priv(dev);
2635 static void myri10ge_set_multicast_list(struct net_device *dev)
2637 struct myri10ge_priv *mgp = netdev_priv(dev);
2638 struct myri10ge_cmd cmd;
2639 struct dev_mc_list *mc_list;
2640 __be32 data[2] = { 0, 0 };
2642 DECLARE_MAC_BUF(mac);
2644 /* can be called from atomic contexts,
2645 * pass 1 to force atomicity in myri10ge_send_cmd() */
2646 myri10ge_change_promisc(mgp, dev->flags & IFF_PROMISC, 1);
2648 /* This firmware is known to not support multicast */
2649 if (!mgp->fw_multicast_support)
2652 /* Disable multicast filtering */
2654 err = myri10ge_send_cmd(mgp, MXGEFW_ENABLE_ALLMULTI, &cmd, 1);
2656 printk(KERN_ERR "myri10ge: %s: Failed MXGEFW_ENABLE_ALLMULTI,"
2657 " error status: %d\n", dev->name, err);
2661 if ((dev->flags & IFF_ALLMULTI) || mgp->adopted_rx_filter_bug) {
2662 /* request to disable multicast filtering, so quit here */
2666 /* Flush the filters */
2668 err = myri10ge_send_cmd(mgp, MXGEFW_LEAVE_ALL_MULTICAST_GROUPS,
2672 "myri10ge: %s: Failed MXGEFW_LEAVE_ALL_MULTICAST_GROUPS"
2673 ", error status: %d\n", dev->name, err);
2677 /* Walk the multicast list, and add each address */
2678 for (mc_list = dev->mc_list; mc_list != NULL; mc_list = mc_list->next) {
2679 memcpy(data, &mc_list->dmi_addr, 6);
2680 cmd.data0 = ntohl(data[0]);
2681 cmd.data1 = ntohl(data[1]);
2682 err = myri10ge_send_cmd(mgp, MXGEFW_JOIN_MULTICAST_GROUP,
2686 printk(KERN_ERR "myri10ge: %s: Failed "
2687 "MXGEFW_JOIN_MULTICAST_GROUP, error status:"
2688 "%d\t", dev->name, err);
2689 printk(KERN_ERR "MAC %s\n",
2690 print_mac(mac, mc_list->dmi_addr));
2694 /* Enable multicast filtering */
2695 err = myri10ge_send_cmd(mgp, MXGEFW_DISABLE_ALLMULTI, &cmd, 1);
2697 printk(KERN_ERR "myri10ge: %s: Failed MXGEFW_DISABLE_ALLMULTI,"
2698 "error status: %d\n", dev->name, err);
2708 static int myri10ge_set_mac_address(struct net_device *dev, void *addr)
2710 struct sockaddr *sa = addr;
2711 struct myri10ge_priv *mgp = netdev_priv(dev);
2714 if (!is_valid_ether_addr(sa->sa_data))
2715 return -EADDRNOTAVAIL;
2717 status = myri10ge_update_mac_address(mgp, sa->sa_data);
2720 "myri10ge: %s: changing mac address failed with %d\n",
2725 /* change the dev structure */
2726 memcpy(dev->dev_addr, sa->sa_data, 6);
2730 static int myri10ge_change_mtu(struct net_device *dev, int new_mtu)
2732 struct myri10ge_priv *mgp = netdev_priv(dev);
2735 if ((new_mtu < 68) || (ETH_HLEN + new_mtu > MYRI10GE_MAX_ETHER_MTU)) {
2736 printk(KERN_ERR "myri10ge: %s: new mtu (%d) is not valid\n",
2737 dev->name, new_mtu);
2740 printk(KERN_INFO "%s: changing mtu from %d to %d\n",
2741 dev->name, dev->mtu, new_mtu);
2743 /* if we change the mtu on an active device, we must
2744 * reset the device so the firmware sees the change */
2745 myri10ge_close(dev);
2755 * Enable ECRC to align PCI-E Completion packets on an 8-byte boundary.
2756 * Only do it if the bridge is a root port since we don't want to disturb
2757 * any other device, except if forced with myri10ge_ecrc_enable > 1.
2760 static void myri10ge_enable_ecrc(struct myri10ge_priv *mgp)
2762 struct pci_dev *bridge = mgp->pdev->bus->self;
2763 struct device *dev = &mgp->pdev->dev;
2770 if (!myri10ge_ecrc_enable || !bridge)
2773 /* check that the bridge is a root port */
2774 cap = pci_find_capability(bridge, PCI_CAP_ID_EXP);
2775 pci_read_config_word(bridge, cap + PCI_CAP_FLAGS, &val);
2776 ext_type = (val & PCI_EXP_FLAGS_TYPE) >> 4;
2777 if (ext_type != PCI_EXP_TYPE_ROOT_PORT) {
2778 if (myri10ge_ecrc_enable > 1) {
2779 struct pci_dev *prev_bridge, *old_bridge = bridge;
2781 /* Walk the hierarchy up to the root port
2782 * where ECRC has to be enabled */
2784 prev_bridge = bridge;
2785 bridge = bridge->bus->self;
2786 if (!bridge || prev_bridge == bridge) {
2788 "Failed to find root port"
2789 " to force ECRC\n");
2793 pci_find_capability(bridge, PCI_CAP_ID_EXP);
2794 pci_read_config_word(bridge,
2795 cap + PCI_CAP_FLAGS, &val);
2796 ext_type = (val & PCI_EXP_FLAGS_TYPE) >> 4;
2797 } while (ext_type != PCI_EXP_TYPE_ROOT_PORT);
2800 "Forcing ECRC on non-root port %s"
2801 " (enabling on root port %s)\n",
2802 pci_name(old_bridge), pci_name(bridge));
2805 "Not enabling ECRC on non-root port %s\n",
2811 cap = pci_find_ext_capability(bridge, PCI_EXT_CAP_ID_ERR);
2815 ret = pci_read_config_dword(bridge, cap + PCI_ERR_CAP, &err_cap);
2817 dev_err(dev, "failed reading ext-conf-space of %s\n",
2819 dev_err(dev, "\t pci=nommconf in use? "
2820 "or buggy/incomplete/absent ACPI MCFG attr?\n");
2823 if (!(err_cap & PCI_ERR_CAP_ECRC_GENC))
2826 err_cap |= PCI_ERR_CAP_ECRC_GENE;
2827 pci_write_config_dword(bridge, cap + PCI_ERR_CAP, err_cap);
2828 dev_info(dev, "Enabled ECRC on upstream bridge %s\n", pci_name(bridge));
2832 * The Lanai Z8E PCI-E interface achieves higher Read-DMA throughput
2833 * when the PCI-E Completion packets are aligned on an 8-byte
2834 * boundary. Some PCI-E chip sets always align Completion packets; on
2835 * the ones that do not, the alignment can be enforced by enabling
2836 * ECRC generation (if supported).
2838 * When PCI-E Completion packets are not aligned, it is actually more
2839 * efficient to limit Read-DMA transactions to 2KB, rather than 4KB.
2841 * If the driver can neither enable ECRC nor verify that it has
2842 * already been enabled, then it must use a firmware image which works
2843 * around unaligned completion packets (myri10ge_ethp_z8e.dat), and it
2844 * should also ensure that it never gives the device a Read-DMA which is
2845 * larger than 2KB by setting the tx_boundary to 2KB. If ECRC is
2846 * enabled, then the driver should use the aligned (myri10ge_eth_z8e.dat)
2847 * firmware image, and set tx_boundary to 4KB.
2850 static void myri10ge_firmware_probe(struct myri10ge_priv *mgp)
2852 struct pci_dev *pdev = mgp->pdev;
2853 struct device *dev = &pdev->dev;
2856 mgp->tx_boundary = 4096;
2858 * Verify the max read request size was set to 4KB
2859 * before trying the test with 4KB.
2861 status = pcie_get_readrq(pdev);
2863 dev_err(dev, "Couldn't read max read req size: %d\n", status);
2866 if (status != 4096) {
2867 dev_warn(dev, "Max Read Request size != 4096 (%d)\n", status);
2868 mgp->tx_boundary = 2048;
2871 * load the optimized firmware (which assumes aligned PCIe
2872 * completions) in order to see if it works on this host.
2874 mgp->fw_name = myri10ge_fw_aligned;
2875 status = myri10ge_load_firmware(mgp);
2881 * Enable ECRC if possible
2883 myri10ge_enable_ecrc(mgp);
2886 * Run a DMA test which watches for unaligned completions and
2887 * aborts on the first one seen.
2890 status = myri10ge_dma_test(mgp, MXGEFW_CMD_UNALIGNED_TEST);
2892 return; /* keep the aligned firmware */
2894 if (status != -E2BIG)
2895 dev_warn(dev, "DMA test failed: %d\n", status);
2896 if (status == -ENOSYS)
2897 dev_warn(dev, "Falling back to ethp! "
2898 "Please install up to date fw\n");
2900 /* fall back to using the unaligned firmware */
2901 mgp->tx_boundary = 2048;
2902 mgp->fw_name = myri10ge_fw_unaligned;
2906 static void myri10ge_select_firmware(struct myri10ge_priv *mgp)
2908 if (myri10ge_force_firmware == 0) {
2909 int link_width, exp_cap;
2912 exp_cap = pci_find_capability(mgp->pdev, PCI_CAP_ID_EXP);
2913 pci_read_config_word(mgp->pdev, exp_cap + PCI_EXP_LNKSTA, &lnk);
2914 link_width = (lnk >> 4) & 0x3f;
2916 /* Check to see if Link is less than 8 or if the
2917 * upstream bridge is known to provide aligned
2919 if (link_width < 8) {
2920 dev_info(&mgp->pdev->dev, "PCIE x%d Link\n",
2922 mgp->tx_boundary = 4096;
2923 mgp->fw_name = myri10ge_fw_aligned;
2925 myri10ge_firmware_probe(mgp);
2928 if (myri10ge_force_firmware == 1) {
2929 dev_info(&mgp->pdev->dev,
2930 "Assuming aligned completions (forced)\n");
2931 mgp->tx_boundary = 4096;
2932 mgp->fw_name = myri10ge_fw_aligned;
2934 dev_info(&mgp->pdev->dev,
2935 "Assuming unaligned completions (forced)\n");
2936 mgp->tx_boundary = 2048;
2937 mgp->fw_name = myri10ge_fw_unaligned;
2940 if (myri10ge_fw_name != NULL) {
2941 dev_info(&mgp->pdev->dev, "overriding firmware to %s\n",
2943 mgp->fw_name = myri10ge_fw_name;
2948 static int myri10ge_suspend(struct pci_dev *pdev, pm_message_t state)
2950 struct myri10ge_priv *mgp;
2951 struct net_device *netdev;
2953 mgp = pci_get_drvdata(pdev);
2958 netif_device_detach(netdev);
2959 if (netif_running(netdev)) {
2960 printk(KERN_INFO "myri10ge: closing %s\n", netdev->name);
2962 myri10ge_close(netdev);
2965 myri10ge_dummy_rdma(mgp, 0);
2966 pci_save_state(pdev);
2967 pci_disable_device(pdev);
2969 return pci_set_power_state(pdev, pci_choose_state(pdev, state));
2972 static int myri10ge_resume(struct pci_dev *pdev)
2974 struct myri10ge_priv *mgp;
2975 struct net_device *netdev;
2979 mgp = pci_get_drvdata(pdev);
2983 pci_set_power_state(pdev, 0); /* zeros conf space as a side effect */
2984 msleep(5); /* give card time to respond */
2985 pci_read_config_word(mgp->pdev, PCI_VENDOR_ID, &vendor);
2986 if (vendor == 0xffff) {
2987 printk(KERN_ERR "myri10ge: %s: device disappeared!\n",
2992 status = pci_restore_state(pdev);
2996 status = pci_enable_device(pdev);
2998 dev_err(&pdev->dev, "failed to enable device\n");
3002 pci_set_master(pdev);
3004 myri10ge_reset(mgp);
3005 myri10ge_dummy_rdma(mgp, 1);
3007 /* Save configuration space to be restored if the
3008 * nic resets due to a parity error */
3009 pci_save_state(pdev);
3011 if (netif_running(netdev)) {
3013 status = myri10ge_open(netdev);
3016 goto abort_with_enabled;
3019 netif_device_attach(netdev);
3024 pci_disable_device(pdev);
3028 #endif /* CONFIG_PM */
3030 static u32 myri10ge_read_reboot(struct myri10ge_priv *mgp)
3032 struct pci_dev *pdev = mgp->pdev;
3033 int vs = mgp->vendor_specific_offset;
3036 /*enter read32 mode */
3037 pci_write_config_byte(pdev, vs + 0x10, 0x3);
3039 /*read REBOOT_STATUS (0xfffffff0) */
3040 pci_write_config_dword(pdev, vs + 0x18, 0xfffffff0);
3041 pci_read_config_dword(pdev, vs + 0x14, &reboot);
3046 * This watchdog is used to check whether the board has suffered
3047 * from a parity error and needs to be recovered.
3049 static void myri10ge_watchdog(struct work_struct *work)
3051 struct myri10ge_priv *mgp =
3052 container_of(work, struct myri10ge_priv, watchdog_work);
3053 struct myri10ge_tx_buf *tx;
3058 mgp->watchdog_resets++;
3059 pci_read_config_word(mgp->pdev, PCI_COMMAND, &cmd);
3060 if ((cmd & PCI_COMMAND_MASTER) == 0) {
3061 /* Bus master DMA disabled? Check to see
3062 * if the card rebooted due to a parity error
3063 * For now, just report it */
3064 reboot = myri10ge_read_reboot(mgp);
3066 "myri10ge: %s: NIC rebooted (0x%x),%s resetting\n",
3067 mgp->dev->name, reboot,
3068 myri10ge_reset_recover ? " " : " not");
3069 if (myri10ge_reset_recover == 0)
3072 myri10ge_reset_recover--;
3075 * A rebooted nic will come back with config space as
3076 * it was after power was applied to PCIe bus.
3077 * Attempt to restore config space which was saved
3078 * when the driver was loaded, or the last time the
3079 * nic was resumed from power saving mode.
3081 pci_restore_state(mgp->pdev);
3083 /* save state again for accounting reasons */
3084 pci_save_state(mgp->pdev);
3087 /* if we get back -1's from our slot, perhaps somebody
3088 * powered off our card. Don't try to reset it in
3090 if (cmd == 0xffff) {
3091 pci_read_config_word(mgp->pdev, PCI_VENDOR_ID, &vendor);
3092 if (vendor == 0xffff) {
3094 "myri10ge: %s: device disappeared!\n",
3099 /* Perhaps it is a software error. Try to reset */
3101 printk(KERN_ERR "myri10ge: %s: device timeout, resetting\n",
3104 printk(KERN_INFO "myri10ge: %s: %d %d %d %d %d\n",
3105 mgp->dev->name, tx->req, tx->done,
3106 tx->pkt_start, tx->pkt_done,
3107 (int)ntohl(mgp->ss.fw_stats->send_done_count));
3109 printk(KERN_INFO "myri10ge: %s: %d %d %d %d %d\n",
3110 mgp->dev->name, tx->req, tx->done,
3111 tx->pkt_start, tx->pkt_done,
3112 (int)ntohl(mgp->ss.fw_stats->send_done_count));
3115 myri10ge_close(mgp->dev);
3116 status = myri10ge_load_firmware(mgp);
3118 printk(KERN_ERR "myri10ge: %s: failed to load firmware\n",
3121 myri10ge_open(mgp->dev);
3126 * We use our own timer routine rather than relying upon
3127 * netdev->tx_timeout because we have a very large hardware transmit
3128 * queue. Due to the large queue, the netdev->tx_timeout function
3129 * cannot detect a NIC with a parity error in a timely fashion if the
3130 * NIC is lightly loaded.
3132 static void myri10ge_watchdog_timer(unsigned long arg)
3134 struct myri10ge_priv *mgp;
3135 struct myri10ge_slice_state *ss;
3138 mgp = (struct myri10ge_priv *)arg;
3140 rx_pause_cnt = ntohl(mgp->ss.fw_stats->dropped_pause);
3143 if (ss->rx_small.watchdog_needed) {
3144 myri10ge_alloc_rx_pages(mgp, &ss->rx_small,
3145 mgp->small_bytes + MXGEFW_PAD, 1);
3146 if (ss->rx_small.fill_cnt - ss->rx_small.cnt >=
3147 myri10ge_fill_thresh)
3148 ss->rx_small.watchdog_needed = 0;
3150 if (ss->rx_big.watchdog_needed) {
3151 myri10ge_alloc_rx_pages(mgp, &ss->rx_big, mgp->big_bytes, 1);
3152 if (ss->rx_big.fill_cnt - ss->rx_big.cnt >=
3153 myri10ge_fill_thresh)
3154 ss->rx_big.watchdog_needed = 0;
3157 if (ss->tx.req != ss->tx.done &&
3158 ss->tx.done == ss->watchdog_tx_done &&
3159 ss->watchdog_tx_req != ss->watchdog_tx_done) {
3160 /* nic seems like it might be stuck.. */
3161 if (rx_pause_cnt != mgp->watchdog_pause) {
3162 if (net_ratelimit())
3163 printk(KERN_WARNING "myri10ge %s:"
3164 "TX paused, check link partner\n",
3167 schedule_work(&mgp->watchdog_work);
3172 mod_timer(&mgp->watchdog_timer,
3173 jiffies + myri10ge_watchdog_timeout * HZ);
3174 ss->watchdog_tx_done = ss->tx.done;
3175 ss->watchdog_tx_req = ss->tx.req;
3176 mgp->watchdog_pause = rx_pause_cnt;
3180 static void myri10ge_free_slices(struct myri10ge_priv *mgp)
3182 struct myri10ge_slice_state *ss;
3183 struct pci_dev *pdev = mgp->pdev;
3187 if (mgp->ss == NULL)
3190 for (i = 0; i < mgp->num_slices; i++) {
3192 if (ss->rx_done.entry != NULL) {
3193 bytes = mgp->max_intr_slots *
3194 sizeof(*ss->rx_done.entry);
3195 dma_free_coherent(&pdev->dev, bytes,
3196 ss->rx_done.entry, ss->rx_done.bus);
3197 ss->rx_done.entry = NULL;
3199 if (ss->fw_stats != NULL) {
3200 bytes = sizeof(*ss->fw_stats);
3201 dma_free_coherent(&pdev->dev, bytes,
3202 ss->fw_stats, ss->fw_stats_bus);
3203 ss->fw_stats = NULL;
3210 static int myri10ge_alloc_slices(struct myri10ge_priv *mgp)
3212 struct myri10ge_slice_state *ss;
3213 struct pci_dev *pdev = mgp->pdev;
3217 bytes = sizeof(*mgp->ss) * mgp->num_slices;
3218 mgp->ss = kzalloc(bytes, GFP_KERNEL);
3219 if (mgp->ss == NULL) {
3223 for (i = 0; i < mgp->num_slices; i++) {
3225 bytes = mgp->max_intr_slots * sizeof(*ss->rx_done.entry);
3226 ss->rx_done.entry = dma_alloc_coherent(&pdev->dev, bytes,
3229 if (ss->rx_done.entry == NULL)
3231 memset(ss->rx_done.entry, 0, bytes);
3232 bytes = sizeof(*ss->fw_stats);
3233 ss->fw_stats = dma_alloc_coherent(&pdev->dev, bytes,
3236 if (ss->fw_stats == NULL)
3240 netif_napi_add(ss->dev, &ss->napi, myri10ge_poll,
3241 myri10ge_napi_weight);
3245 myri10ge_free_slices(mgp);
3250 * This function determines the number of slices supported.
3251 * The number slices is the minumum of the number of CPUS,
3252 * the number of MSI-X irqs supported, the number of slices
3253 * supported by the firmware
3255 static void myri10ge_probe_slices(struct myri10ge_priv *mgp)
3257 struct myri10ge_cmd cmd;
3258 struct pci_dev *pdev = mgp->pdev;
3260 int i, status, ncpus, msix_cap;
3262 mgp->num_slices = 1;
3263 msix_cap = pci_find_capability(pdev, PCI_CAP_ID_MSIX);
3264 ncpus = num_online_cpus();
3266 if (myri10ge_max_slices == 1 || msix_cap == 0 ||
3267 (myri10ge_max_slices == -1 && ncpus < 2))
3270 /* try to load the slice aware rss firmware */
3271 old_fw = mgp->fw_name;
3272 if (old_fw == myri10ge_fw_aligned)
3273 mgp->fw_name = myri10ge_fw_rss_aligned;
3275 mgp->fw_name = myri10ge_fw_rss_unaligned;
3276 status = myri10ge_load_firmware(mgp, 0);
3278 dev_info(&pdev->dev, "Rss firmware not found\n");
3282 /* hit the board with a reset to ensure it is alive */
3283 memset(&cmd, 0, sizeof(cmd));
3284 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_RESET, &cmd, 0);
3286 dev_err(&mgp->pdev->dev, "failed reset\n");
3291 mgp->max_intr_slots = cmd.data0 / sizeof(struct mcp_slot);
3293 /* tell it the size of the interrupt queues */
3294 cmd.data0 = mgp->max_intr_slots * sizeof(struct mcp_slot);
3295 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_SET_INTRQ_SIZE, &cmd, 0);
3297 dev_err(&mgp->pdev->dev, "failed MXGEFW_CMD_SET_INTRQ_SIZE\n");
3301 /* ask the maximum number of slices it supports */
3302 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_GET_MAX_RSS_QUEUES, &cmd, 0);
3306 mgp->num_slices = cmd.data0;
3308 /* Only allow multiple slices if MSI-X is usable */
3309 if (!myri10ge_msi) {
3313 /* if the admin did not specify a limit to how many
3314 * slices we should use, cap it automatically to the
3315 * number of CPUs currently online */
3316 if (myri10ge_max_slices == -1)
3317 myri10ge_max_slices = ncpus;
3319 if (mgp->num_slices > myri10ge_max_slices)
3320 mgp->num_slices = myri10ge_max_slices;
3322 /* Now try to allocate as many MSI-X vectors as we have
3323 * slices. We give up on MSI-X if we can only get a single
3326 mgp->msix_vectors = kzalloc(mgp->num_slices *
3327 sizeof(*mgp->msix_vectors), GFP_KERNEL);
3328 if (mgp->msix_vectors == NULL)
3330 for (i = 0; i < mgp->num_slices; i++) {
3331 mgp->msix_vectors[i].entry = i;
3334 while (mgp->num_slices > 1) {
3335 /* make sure it is a power of two */
3336 while (!is_power_of_2(mgp->num_slices))
3338 if (mgp->num_slices == 1)
3340 status = pci_enable_msix(pdev, mgp->msix_vectors,
3343 pci_disable_msix(pdev);
3347 mgp->num_slices = status;
3353 if (mgp->msix_vectors != NULL) {
3354 kfree(mgp->msix_vectors);
3355 mgp->msix_vectors = NULL;
3359 mgp->num_slices = 1;
3360 mgp->fw_name = old_fw;
3361 myri10ge_load_firmware(mgp, 0);
3365 static int myri10ge_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
3367 struct net_device *netdev;
3368 struct myri10ge_priv *mgp;
3369 struct device *dev = &pdev->dev;
3372 int status = -ENXIO;
3375 netdev = alloc_etherdev(sizeof(*mgp));
3376 if (netdev == NULL) {
3377 dev_err(dev, "Could not allocate ethernet device\n");
3381 SET_NETDEV_DEV(netdev, &pdev->dev);
3383 mgp = netdev_priv(netdev);
3385 netif_napi_add(netdev, &mgp->ss.napi, myri10ge_poll, myri10ge_napi_weight);
3387 mgp->csum_flag = MXGEFW_FLAGS_CKSUM;
3388 mgp->pause = myri10ge_flow_control;
3389 mgp->intr_coal_delay = myri10ge_intr_coal_delay;
3390 mgp->msg_enable = netif_msg_init(myri10ge_debug, MYRI10GE_MSG_DEFAULT);
3391 init_waitqueue_head(&mgp->down_wq);
3393 if (pci_enable_device(pdev)) {
3394 dev_err(&pdev->dev, "pci_enable_device call failed\n");
3396 goto abort_with_netdev;
3399 /* Find the vendor-specific cap so we can check
3400 * the reboot register later on */
3401 mgp->vendor_specific_offset
3402 = pci_find_capability(pdev, PCI_CAP_ID_VNDR);
3404 /* Set our max read request to 4KB */
3405 status = pcie_set_readrq(pdev, 4096);
3407 dev_err(&pdev->dev, "Error %d writing PCI_EXP_DEVCTL\n",
3409 goto abort_with_netdev;
3412 pci_set_master(pdev);
3414 status = pci_set_dma_mask(pdev, DMA_64BIT_MASK);
3418 "64-bit pci address mask was refused, "
3420 status = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
3423 dev_err(&pdev->dev, "Error %d setting DMA mask\n", status);
3424 goto abort_with_netdev;
3426 mgp->cmd = dma_alloc_coherent(&pdev->dev, sizeof(*mgp->cmd),
3427 &mgp->cmd_bus, GFP_KERNEL);
3428 if (mgp->cmd == NULL)
3429 goto abort_with_netdev;
3431 mgp->ss.fw_stats = dma_alloc_coherent(&pdev->dev, sizeof(*mgp->ss.fw_stats),
3432 &mgp->ss.fw_stats_bus, GFP_KERNEL);
3433 if (mgp->ss.fw_stats == NULL)
3434 goto abort_with_cmd;
3436 mgp->board_span = pci_resource_len(pdev, 0);
3437 mgp->iomem_base = pci_resource_start(pdev, 0);
3439 mgp->wc_enabled = 0;
3441 mgp->mtrr = mtrr_add(mgp->iomem_base, mgp->board_span,
3442 MTRR_TYPE_WRCOMB, 1);
3444 mgp->wc_enabled = 1;
3446 /* Hack. need to get rid of these magic numbers */
3448 2 * 1024 * 1024 - (2 * (48 * 1024) + (32 * 1024)) - 0x100;
3449 if (mgp->sram_size > mgp->board_span) {
3450 dev_err(&pdev->dev, "board span %ld bytes too small\n",
3454 mgp->sram = ioremap(mgp->iomem_base, mgp->board_span);
3455 if (mgp->sram == NULL) {
3456 dev_err(&pdev->dev, "ioremap failed for %ld bytes at 0x%lx\n",
3457 mgp->board_span, mgp->iomem_base);
3461 memcpy_fromio(mgp->eeprom_strings,
3462 mgp->sram + mgp->sram_size - MYRI10GE_EEPROM_STRINGS_SIZE,
3463 MYRI10GE_EEPROM_STRINGS_SIZE);
3464 memset(mgp->eeprom_strings + MYRI10GE_EEPROM_STRINGS_SIZE - 2, 0, 2);
3465 status = myri10ge_read_mac_addr(mgp);
3467 goto abort_with_ioremap;
3469 for (i = 0; i < ETH_ALEN; i++)
3470 netdev->dev_addr[i] = mgp->mac_addr[i];
3472 /* allocate rx done ring */
3473 bytes = mgp->max_intr_slots * sizeof(*mgp->ss.rx_done.entry);
3474 mgp->ss.rx_done.entry = dma_alloc_coherent(&pdev->dev, bytes,
3475 &mgp->ss.rx_done.bus, GFP_KERNEL);
3476 if (mgp->ss.rx_done.entry == NULL)
3477 goto abort_with_ioremap;
3478 memset(mgp->ss.rx_done.entry, 0, bytes);
3480 myri10ge_select_firmware(mgp);
3482 status = myri10ge_load_firmware(mgp);
3484 dev_err(&pdev->dev, "failed to load firmware\n");
3485 goto abort_with_rx_done;
3488 status = myri10ge_reset(mgp);
3490 dev_err(&pdev->dev, "failed reset\n");
3491 goto abort_with_firmware;
3494 pci_set_drvdata(pdev, mgp);
3495 if ((myri10ge_initial_mtu + ETH_HLEN) > MYRI10GE_MAX_ETHER_MTU)
3496 myri10ge_initial_mtu = MYRI10GE_MAX_ETHER_MTU - ETH_HLEN;
3497 if ((myri10ge_initial_mtu + ETH_HLEN) < 68)
3498 myri10ge_initial_mtu = 68;
3499 netdev->mtu = myri10ge_initial_mtu;
3500 netdev->open = myri10ge_open;
3501 netdev->stop = myri10ge_close;
3502 netdev->hard_start_xmit = myri10ge_xmit;
3503 netdev->get_stats = myri10ge_get_stats;
3504 netdev->base_addr = mgp->iomem_base;
3505 netdev->change_mtu = myri10ge_change_mtu;
3506 netdev->set_multicast_list = myri10ge_set_multicast_list;
3507 netdev->set_mac_address = myri10ge_set_mac_address;
3508 netdev->features = mgp->features;
3510 netdev->features |= NETIF_F_HIGHDMA;
3512 /* make sure we can get an irq, and that MSI can be
3513 * setup (if available). Also ensure netdev->irq
3514 * is set to correct value if MSI is enabled */
3515 status = myri10ge_request_irq(mgp);
3517 goto abort_with_firmware;
3518 netdev->irq = pdev->irq;
3519 myri10ge_free_irq(mgp);
3521 /* Save configuration space to be restored if the
3522 * nic resets due to a parity error */
3523 pci_save_state(pdev);
3525 /* Setup the watchdog timer */
3526 setup_timer(&mgp->watchdog_timer, myri10ge_watchdog_timer,
3527 (unsigned long)mgp);
3529 SET_ETHTOOL_OPS(netdev, &myri10ge_ethtool_ops);
3530 INIT_WORK(&mgp->watchdog_work, myri10ge_watchdog);
3531 status = register_netdev(netdev);
3533 dev_err(&pdev->dev, "register_netdev failed: %d\n", status);
3534 goto abort_with_state;
3536 dev_info(dev, "%s IRQ %d, tx bndry %d, fw %s, WC %s\n",
3537 (mgp->msi_enabled ? "MSI" : "xPIC"),
3538 netdev->irq, mgp->tx_boundary, mgp->fw_name,
3539 (mgp->wc_enabled ? "Enabled" : "Disabled"));
3544 pci_restore_state(pdev);
3546 abort_with_firmware:
3547 myri10ge_dummy_rdma(mgp, 0);
3550 bytes = mgp->max_intr_slots * sizeof(*mgp->ss.rx_done.entry);
3551 dma_free_coherent(&pdev->dev, bytes,
3552 mgp->ss.rx_done.entry, mgp->ss.rx_done.bus);
3560 mtrr_del(mgp->mtrr, mgp->iomem_base, mgp->board_span);
3562 dma_free_coherent(&pdev->dev, sizeof(*mgp->ss.fw_stats),
3563 mgp->ss.fw_stats, mgp->ss.fw_stats_bus);
3566 dma_free_coherent(&pdev->dev, sizeof(*mgp->cmd),
3567 mgp->cmd, mgp->cmd_bus);
3571 free_netdev(netdev);
3578 * Does what is necessary to shutdown one Myrinet device. Called
3579 * once for each Myrinet card by the kernel when a module is
3582 static void myri10ge_remove(struct pci_dev *pdev)
3584 struct myri10ge_priv *mgp;
3585 struct net_device *netdev;
3588 mgp = pci_get_drvdata(pdev);
3592 flush_scheduled_work();
3594 unregister_netdev(netdev);
3596 myri10ge_dummy_rdma(mgp, 0);
3598 /* avoid a memory leak */
3599 pci_restore_state(pdev);
3601 bytes = mgp->max_intr_slots * sizeof(*mgp->ss.rx_done.entry);
3602 dma_free_coherent(&pdev->dev, bytes,
3603 mgp->ss.rx_done.entry, mgp->ss.rx_done.bus);
3609 mtrr_del(mgp->mtrr, mgp->iomem_base, mgp->board_span);
3611 dma_free_coherent(&pdev->dev, sizeof(*mgp->ss.fw_stats),
3612 mgp->ss.fw_stats, mgp->ss.fw_stats_bus);
3614 dma_free_coherent(&pdev->dev, sizeof(*mgp->cmd),
3615 mgp->cmd, mgp->cmd_bus);
3617 free_netdev(netdev);
3618 pci_set_drvdata(pdev, NULL);
3621 #define PCI_DEVICE_ID_MYRICOM_MYRI10GE_Z8E 0x0008
3622 #define PCI_DEVICE_ID_MYRICOM_MYRI10GE_Z8E_9 0x0009
3624 static struct pci_device_id myri10ge_pci_tbl[] = {
3625 {PCI_DEVICE(PCI_VENDOR_ID_MYRICOM, PCI_DEVICE_ID_MYRICOM_MYRI10GE_Z8E)},
3627 (PCI_VENDOR_ID_MYRICOM, PCI_DEVICE_ID_MYRICOM_MYRI10GE_Z8E_9)},
3631 static struct pci_driver myri10ge_driver = {
3633 .probe = myri10ge_probe,
3634 .remove = myri10ge_remove,
3635 .id_table = myri10ge_pci_tbl,
3637 .suspend = myri10ge_suspend,
3638 .resume = myri10ge_resume,
3642 static __init int myri10ge_init_module(void)
3644 printk(KERN_INFO "%s: Version %s\n", myri10ge_driver.name,
3645 MYRI10GE_VERSION_STR);
3646 return pci_register_driver(&myri10ge_driver);
3649 module_init(myri10ge_init_module);
3651 static __exit void myri10ge_cleanup_module(void)
3653 pci_unregister_driver(&myri10ge_driver);
3656 module_exit(myri10ge_cleanup_module);