1 /*************************************************************************
2 * myri10ge.c: Myricom Myri-10G Ethernet driver.
4 * Copyright (C) 2005 - 2007 Myricom, Inc.
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 * 3. Neither the name of Myricom, Inc. nor the names of its contributors
16 * may be used to endorse or promote products derived from this software
17 * without specific prior written permission.
19 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
20 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
22 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
23 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
29 * POSSIBILITY OF SUCH DAMAGE.
32 * If the eeprom on your board is not recent enough, you will need to get a
33 * newer firmware image at:
34 * http://www.myri.com/scs/download-Myri10GE.html
36 * Contact Information:
38 * Myricom, Inc., 325N Santa Anita Avenue, Arcadia, CA 91006
39 *************************************************************************/
41 #include <linux/tcp.h>
42 #include <linux/netdevice.h>
43 #include <linux/skbuff.h>
44 #include <linux/string.h>
45 #include <linux/module.h>
46 #include <linux/pci.h>
47 #include <linux/dma-mapping.h>
48 #include <linux/etherdevice.h>
49 #include <linux/if_ether.h>
50 #include <linux/if_vlan.h>
51 #include <linux/inet_lro.h>
52 #include <linux/dca.h>
54 #include <linux/inet.h>
56 #include <linux/ethtool.h>
57 #include <linux/firmware.h>
58 #include <linux/delay.h>
59 #include <linux/version.h>
60 #include <linux/timer.h>
61 #include <linux/vmalloc.h>
62 #include <linux/crc32.h>
63 #include <linux/moduleparam.h>
65 #include <linux/log2.h>
66 #include <net/checksum.h>
69 #include <asm/byteorder.h>
71 #include <asm/processor.h>
76 #include "myri10ge_mcp.h"
77 #include "myri10ge_mcp_gen_header.h"
79 #define MYRI10GE_VERSION_STR "1.3.2-1.287"
81 MODULE_DESCRIPTION("Myricom 10G driver (10GbE)");
82 MODULE_AUTHOR("Maintainer: help@myri.com");
83 MODULE_VERSION(MYRI10GE_VERSION_STR);
84 MODULE_LICENSE("Dual BSD/GPL");
86 #define MYRI10GE_MAX_ETHER_MTU 9014
88 #define MYRI10GE_ETH_STOPPED 0
89 #define MYRI10GE_ETH_STOPPING 1
90 #define MYRI10GE_ETH_STARTING 2
91 #define MYRI10GE_ETH_RUNNING 3
92 #define MYRI10GE_ETH_OPEN_FAILED 4
94 #define MYRI10GE_EEPROM_STRINGS_SIZE 256
95 #define MYRI10GE_MAX_SEND_DESC_TSO ((65536 / 2048) * 2)
96 #define MYRI10GE_MAX_LRO_DESCRIPTORS 8
97 #define MYRI10GE_LRO_MAX_PKTS 64
99 #define MYRI10GE_NO_CONFIRM_DATA htonl(0xffffffff)
100 #define MYRI10GE_NO_RESPONSE_RESULT 0xffffffff
102 #define MYRI10GE_ALLOC_ORDER 0
103 #define MYRI10GE_ALLOC_SIZE ((1 << MYRI10GE_ALLOC_ORDER) * PAGE_SIZE)
104 #define MYRI10GE_MAX_FRAGS_PER_FRAME (MYRI10GE_MAX_ETHER_MTU/MYRI10GE_ALLOC_SIZE + 1)
106 struct myri10ge_rx_buffer_state {
109 DECLARE_PCI_UNMAP_ADDR(bus)
110 DECLARE_PCI_UNMAP_LEN(len)
113 struct myri10ge_tx_buffer_state {
116 DECLARE_PCI_UNMAP_ADDR(bus)
117 DECLARE_PCI_UNMAP_LEN(len)
120 struct myri10ge_cmd {
126 struct myri10ge_rx_buf {
127 struct mcp_kreq_ether_recv __iomem *lanai; /* lanai ptr for recv ring */
128 u8 __iomem *wc_fifo; /* w/c rx dma addr fifo address */
129 struct mcp_kreq_ether_recv *shadow; /* host shadow of recv ring */
130 struct myri10ge_rx_buffer_state *info;
137 int mask; /* number of rx slots -1 */
141 struct myri10ge_tx_buf {
142 struct mcp_kreq_ether_send __iomem *lanai; /* lanai ptr for sendq */
143 u8 __iomem *wc_fifo; /* w/c send fifo address */
144 struct mcp_kreq_ether_send *req_list; /* host shadow of sendq */
146 struct myri10ge_tx_buffer_state *info;
147 int mask; /* number of transmit slots -1 */
148 int req ____cacheline_aligned; /* transmit slots submitted */
149 int pkt_start; /* packets started */
152 int done ____cacheline_aligned; /* transmit slots completed */
153 int pkt_done; /* packets completed */
157 struct myri10ge_rx_done {
158 struct mcp_slot *entry;
162 struct net_lro_mgr lro_mgr;
163 struct net_lro_desc lro_desc[MYRI10GE_MAX_LRO_DESCRIPTORS];
166 struct myri10ge_slice_netstats {
167 unsigned long rx_packets;
168 unsigned long tx_packets;
169 unsigned long rx_bytes;
170 unsigned long tx_bytes;
171 unsigned long rx_dropped;
172 unsigned long tx_dropped;
175 struct myri10ge_slice_state {
176 struct myri10ge_tx_buf tx; /* transmit ring */
177 struct myri10ge_rx_buf rx_small;
178 struct myri10ge_rx_buf rx_big;
179 struct myri10ge_rx_done rx_done;
180 struct net_device *dev;
181 struct napi_struct napi;
182 struct myri10ge_priv *mgp;
183 struct myri10ge_slice_netstats stats;
184 __be32 __iomem *irq_claim;
185 struct mcp_irq_data *fw_stats;
186 dma_addr_t fw_stats_bus;
187 int watchdog_tx_done;
192 __be32 __iomem *dca_tag;
197 struct myri10ge_priv {
198 struct myri10ge_slice_state *ss;
199 int tx_boundary; /* boundary transmits cannot cross */
201 int running; /* running? */
202 int csum_flag; /* rx_csums? */
206 struct net_device *dev;
207 struct net_device_stats stats;
208 spinlock_t stats_lock;
211 unsigned long board_span;
212 unsigned long iomem_base;
213 __be32 __iomem *irq_deassert;
214 char *mac_addr_string;
215 struct mcp_cmd_response *cmd;
217 struct pci_dev *pdev;
220 struct msix_entry *msix_vectors;
225 unsigned int rdma_tags_available;
227 __be32 __iomem *intr_coal_delay_ptr;
231 wait_queue_head_t down_wq;
232 struct work_struct watchdog_work;
233 struct timer_list watchdog_timer;
238 char eeprom_strings[MYRI10GE_EEPROM_STRINGS_SIZE];
239 char *product_code_string;
240 char fw_version[128];
244 int adopted_rx_filter_bug;
245 u8 mac_addr[6]; /* eeprom mac address */
246 unsigned long serial_number;
247 int vendor_specific_offset;
248 int fw_multicast_support;
249 unsigned long features;
258 static char *myri10ge_fw_unaligned = "myri10ge_ethp_z8e.dat";
259 static char *myri10ge_fw_aligned = "myri10ge_eth_z8e.dat";
260 static char *myri10ge_fw_rss_unaligned = "myri10ge_rss_ethp_z8e.dat";
261 static char *myri10ge_fw_rss_aligned = "myri10ge_rss_eth_z8e.dat";
263 static char *myri10ge_fw_name = NULL;
264 module_param(myri10ge_fw_name, charp, S_IRUGO | S_IWUSR);
265 MODULE_PARM_DESC(myri10ge_fw_name, "Firmware image name");
267 static int myri10ge_ecrc_enable = 1;
268 module_param(myri10ge_ecrc_enable, int, S_IRUGO);
269 MODULE_PARM_DESC(myri10ge_ecrc_enable, "Enable Extended CRC on PCI-E");
271 static int myri10ge_small_bytes = -1; /* -1 == auto */
272 module_param(myri10ge_small_bytes, int, S_IRUGO | S_IWUSR);
273 MODULE_PARM_DESC(myri10ge_small_bytes, "Threshold of small packets");
275 static int myri10ge_msi = 1; /* enable msi by default */
276 module_param(myri10ge_msi, int, S_IRUGO | S_IWUSR);
277 MODULE_PARM_DESC(myri10ge_msi, "Enable Message Signalled Interrupts");
279 static int myri10ge_intr_coal_delay = 75;
280 module_param(myri10ge_intr_coal_delay, int, S_IRUGO);
281 MODULE_PARM_DESC(myri10ge_intr_coal_delay, "Interrupt coalescing delay");
283 static int myri10ge_flow_control = 1;
284 module_param(myri10ge_flow_control, int, S_IRUGO);
285 MODULE_PARM_DESC(myri10ge_flow_control, "Pause parameter");
287 static int myri10ge_deassert_wait = 1;
288 module_param(myri10ge_deassert_wait, int, S_IRUGO | S_IWUSR);
289 MODULE_PARM_DESC(myri10ge_deassert_wait,
290 "Wait when deasserting legacy interrupts");
292 static int myri10ge_force_firmware = 0;
293 module_param(myri10ge_force_firmware, int, S_IRUGO);
294 MODULE_PARM_DESC(myri10ge_force_firmware,
295 "Force firmware to assume aligned completions");
297 static int myri10ge_initial_mtu = MYRI10GE_MAX_ETHER_MTU - ETH_HLEN;
298 module_param(myri10ge_initial_mtu, int, S_IRUGO);
299 MODULE_PARM_DESC(myri10ge_initial_mtu, "Initial MTU");
301 static int myri10ge_napi_weight = 64;
302 module_param(myri10ge_napi_weight, int, S_IRUGO);
303 MODULE_PARM_DESC(myri10ge_napi_weight, "Set NAPI weight");
305 static int myri10ge_watchdog_timeout = 1;
306 module_param(myri10ge_watchdog_timeout, int, S_IRUGO);
307 MODULE_PARM_DESC(myri10ge_watchdog_timeout, "Set watchdog timeout");
309 static int myri10ge_max_irq_loops = 1048576;
310 module_param(myri10ge_max_irq_loops, int, S_IRUGO);
311 MODULE_PARM_DESC(myri10ge_max_irq_loops,
312 "Set stuck legacy IRQ detection threshold");
314 #define MYRI10GE_MSG_DEFAULT NETIF_MSG_LINK
316 static int myri10ge_debug = -1; /* defaults above */
317 module_param(myri10ge_debug, int, 0);
318 MODULE_PARM_DESC(myri10ge_debug, "Debug level (0=none,...,16=all)");
320 static int myri10ge_lro = 1;
321 module_param(myri10ge_lro, int, S_IRUGO);
322 MODULE_PARM_DESC(myri10ge_lro, "Enable large receive offload");
324 static int myri10ge_lro_max_pkts = MYRI10GE_LRO_MAX_PKTS;
325 module_param(myri10ge_lro_max_pkts, int, S_IRUGO);
326 MODULE_PARM_DESC(myri10ge_lro_max_pkts,
327 "Number of LRO packets to be aggregated");
329 static int myri10ge_fill_thresh = 256;
330 module_param(myri10ge_fill_thresh, int, S_IRUGO | S_IWUSR);
331 MODULE_PARM_DESC(myri10ge_fill_thresh, "Number of empty rx slots allowed");
333 static int myri10ge_reset_recover = 1;
335 static int myri10ge_wcfifo = 0;
336 module_param(myri10ge_wcfifo, int, S_IRUGO);
337 MODULE_PARM_DESC(myri10ge_wcfifo, "Enable WC Fifo when WC is enabled");
339 static int myri10ge_max_slices = 1;
340 module_param(myri10ge_max_slices, int, S_IRUGO);
341 MODULE_PARM_DESC(myri10ge_max_slices, "Max tx/rx queues");
343 static int myri10ge_rss_hash = MXGEFW_RSS_HASH_TYPE_SRC_PORT;
344 module_param(myri10ge_rss_hash, int, S_IRUGO);
345 MODULE_PARM_DESC(myri10ge_rss_hash, "Type of RSS hashing to do");
347 static int myri10ge_dca = 1;
348 module_param(myri10ge_dca, int, S_IRUGO);
349 MODULE_PARM_DESC(myri10ge_dca, "Enable DCA if possible");
351 #define MYRI10GE_FW_OFFSET 1024*1024
352 #define MYRI10GE_HIGHPART_TO_U32(X) \
353 (sizeof (X) == 8) ? ((u32)((u64)(X) >> 32)) : (0)
354 #define MYRI10GE_LOWPART_TO_U32(X) ((u32)(X))
356 #define myri10ge_pio_copy(to,from,size) __iowrite64_copy(to,from,size/8)
358 static void myri10ge_set_multicast_list(struct net_device *dev);
359 static int myri10ge_sw_tso(struct sk_buff *skb, struct net_device *dev);
361 static inline void put_be32(__be32 val, __be32 __iomem * p)
363 __raw_writel((__force __u32) val, (__force void __iomem *)p);
367 myri10ge_send_cmd(struct myri10ge_priv *mgp, u32 cmd,
368 struct myri10ge_cmd *data, int atomic)
371 char buf_bytes[sizeof(*buf) + 8];
372 struct mcp_cmd_response *response = mgp->cmd;
373 char __iomem *cmd_addr = mgp->sram + MXGEFW_ETH_CMD;
374 u32 dma_low, dma_high, result, value;
377 /* ensure buf is aligned to 8 bytes */
378 buf = (struct mcp_cmd *)ALIGN((unsigned long)buf_bytes, 8);
380 buf->data0 = htonl(data->data0);
381 buf->data1 = htonl(data->data1);
382 buf->data2 = htonl(data->data2);
383 buf->cmd = htonl(cmd);
384 dma_low = MYRI10GE_LOWPART_TO_U32(mgp->cmd_bus);
385 dma_high = MYRI10GE_HIGHPART_TO_U32(mgp->cmd_bus);
387 buf->response_addr.low = htonl(dma_low);
388 buf->response_addr.high = htonl(dma_high);
389 response->result = htonl(MYRI10GE_NO_RESPONSE_RESULT);
391 myri10ge_pio_copy(cmd_addr, buf, sizeof(*buf));
393 /* wait up to 15ms. Longest command is the DMA benchmark,
394 * which is capped at 5ms, but runs from a timeout handler
395 * that runs every 7.8ms. So a 15ms timeout leaves us with
399 /* if atomic is set, do not sleep,
400 * and try to get the completion quickly
401 * (1ms will be enough for those commands) */
402 for (sleep_total = 0;
404 && response->result == htonl(MYRI10GE_NO_RESPONSE_RESULT);
410 /* use msleep for most command */
411 for (sleep_total = 0;
413 && response->result == htonl(MYRI10GE_NO_RESPONSE_RESULT);
418 result = ntohl(response->result);
419 value = ntohl(response->data);
420 if (result != MYRI10GE_NO_RESPONSE_RESULT) {
424 } else if (result == MXGEFW_CMD_UNKNOWN) {
426 } else if (result == MXGEFW_CMD_ERROR_UNALIGNED) {
429 dev_err(&mgp->pdev->dev,
430 "command %d failed, result = %d\n",
436 dev_err(&mgp->pdev->dev, "command %d timed out, result = %d\n",
442 * The eeprom strings on the lanaiX have the format
445 * PT:ddd mmm xx xx:xx:xx xx\0
446 * PV:ddd mmm xx xx:xx:xx xx\0
448 static int myri10ge_read_mac_addr(struct myri10ge_priv *mgp)
453 ptr = mgp->eeprom_strings;
454 limit = mgp->eeprom_strings + MYRI10GE_EEPROM_STRINGS_SIZE;
456 while (*ptr != '\0' && ptr < limit) {
457 if (memcmp(ptr, "MAC=", 4) == 0) {
459 mgp->mac_addr_string = ptr;
460 for (i = 0; i < 6; i++) {
461 if ((ptr + 2) > limit)
464 simple_strtoul(ptr, &ptr, 16);
468 if (memcmp(ptr, "PC=", 3) == 0) {
470 mgp->product_code_string = ptr;
472 if (memcmp((const void *)ptr, "SN=", 3) == 0) {
474 mgp->serial_number = simple_strtoul(ptr, &ptr, 10);
476 while (ptr < limit && *ptr++) ;
482 dev_err(&mgp->pdev->dev, "failed to parse eeprom_strings\n");
487 * Enable or disable periodic RDMAs from the host to make certain
488 * chipsets resend dropped PCIe messages
491 static void myri10ge_dummy_rdma(struct myri10ge_priv *mgp, int enable)
493 char __iomem *submit;
494 __be32 buf[16] __attribute__ ((__aligned__(8)));
495 u32 dma_low, dma_high;
498 /* clear confirmation addr */
502 /* send a rdma command to the PCIe engine, and wait for the
503 * response in the confirmation address. The firmware should
504 * write a -1 there to indicate it is alive and well
506 dma_low = MYRI10GE_LOWPART_TO_U32(mgp->cmd_bus);
507 dma_high = MYRI10GE_HIGHPART_TO_U32(mgp->cmd_bus);
509 buf[0] = htonl(dma_high); /* confirm addr MSW */
510 buf[1] = htonl(dma_low); /* confirm addr LSW */
511 buf[2] = MYRI10GE_NO_CONFIRM_DATA; /* confirm data */
512 buf[3] = htonl(dma_high); /* dummy addr MSW */
513 buf[4] = htonl(dma_low); /* dummy addr LSW */
514 buf[5] = htonl(enable); /* enable? */
516 submit = mgp->sram + MXGEFW_BOOT_DUMMY_RDMA;
518 myri10ge_pio_copy(submit, &buf, sizeof(buf));
519 for (i = 0; mgp->cmd->data != MYRI10GE_NO_CONFIRM_DATA && i < 20; i++)
521 if (mgp->cmd->data != MYRI10GE_NO_CONFIRM_DATA)
522 dev_err(&mgp->pdev->dev, "dummy rdma %s failed\n",
523 (enable ? "enable" : "disable"));
527 myri10ge_validate_firmware(struct myri10ge_priv *mgp,
528 struct mcp_gen_header *hdr)
530 struct device *dev = &mgp->pdev->dev;
532 /* check firmware type */
533 if (ntohl(hdr->mcp_type) != MCP_TYPE_ETH) {
534 dev_err(dev, "Bad firmware type: 0x%x\n", ntohl(hdr->mcp_type));
538 /* save firmware version for ethtool */
539 strncpy(mgp->fw_version, hdr->version, sizeof(mgp->fw_version));
541 sscanf(mgp->fw_version, "%d.%d.%d", &mgp->fw_ver_major,
542 &mgp->fw_ver_minor, &mgp->fw_ver_tiny);
544 if (!(mgp->fw_ver_major == MXGEFW_VERSION_MAJOR
545 && mgp->fw_ver_minor == MXGEFW_VERSION_MINOR)) {
546 dev_err(dev, "Found firmware version %s\n", mgp->fw_version);
547 dev_err(dev, "Driver needs %d.%d\n", MXGEFW_VERSION_MAJOR,
548 MXGEFW_VERSION_MINOR);
554 static int myri10ge_load_hotplug_firmware(struct myri10ge_priv *mgp, u32 * size)
556 unsigned crc, reread_crc;
557 const struct firmware *fw;
558 struct device *dev = &mgp->pdev->dev;
559 struct mcp_gen_header *hdr;
564 if ((status = request_firmware(&fw, mgp->fw_name, dev)) < 0) {
565 dev_err(dev, "Unable to load %s firmware image via hotplug\n",
568 goto abort_with_nothing;
573 if (fw->size >= mgp->sram_size - MYRI10GE_FW_OFFSET ||
574 fw->size < MCP_HEADER_PTR_OFFSET + 4) {
575 dev_err(dev, "Firmware size invalid:%d\n", (int)fw->size);
581 hdr_offset = ntohl(*(__be32 *) (fw->data + MCP_HEADER_PTR_OFFSET));
582 if ((hdr_offset & 3) || hdr_offset + sizeof(*hdr) > fw->size) {
583 dev_err(dev, "Bad firmware file\n");
587 hdr = (void *)(fw->data + hdr_offset);
589 status = myri10ge_validate_firmware(mgp, hdr);
593 crc = crc32(~0, fw->data, fw->size);
594 for (i = 0; i < fw->size; i += 256) {
595 myri10ge_pio_copy(mgp->sram + MYRI10GE_FW_OFFSET + i,
597 min(256U, (unsigned)(fw->size - i)));
601 /* corruption checking is good for parity recovery and buggy chipset */
602 memcpy_fromio(fw->data, mgp->sram + MYRI10GE_FW_OFFSET, fw->size);
603 reread_crc = crc32(~0, fw->data, fw->size);
604 if (crc != reread_crc) {
605 dev_err(dev, "CRC failed(fw-len=%u), got 0x%x (expect 0x%x)\n",
606 (unsigned)fw->size, reread_crc, crc);
610 *size = (u32) fw->size;
613 release_firmware(fw);
619 static int myri10ge_adopt_running_firmware(struct myri10ge_priv *mgp)
621 struct mcp_gen_header *hdr;
622 struct device *dev = &mgp->pdev->dev;
623 const size_t bytes = sizeof(struct mcp_gen_header);
627 /* find running firmware header */
628 hdr_offset = swab32(readl(mgp->sram + MCP_HEADER_PTR_OFFSET));
630 if ((hdr_offset & 3) || hdr_offset + sizeof(*hdr) > mgp->sram_size) {
631 dev_err(dev, "Running firmware has bad header offset (%d)\n",
636 /* copy header of running firmware from SRAM to host memory to
637 * validate firmware */
638 hdr = kmalloc(bytes, GFP_KERNEL);
640 dev_err(dev, "could not malloc firmware hdr\n");
643 memcpy_fromio(hdr, mgp->sram + hdr_offset, bytes);
644 status = myri10ge_validate_firmware(mgp, hdr);
647 /* check to see if adopted firmware has bug where adopting
648 * it will cause broadcasts to be filtered unless the NIC
649 * is kept in ALLMULTI mode */
650 if (mgp->fw_ver_major == 1 && mgp->fw_ver_minor == 4 &&
651 mgp->fw_ver_tiny >= 4 && mgp->fw_ver_tiny <= 11) {
652 mgp->adopted_rx_filter_bug = 1;
653 dev_warn(dev, "Adopting fw %d.%d.%d: "
654 "working around rx filter bug\n",
655 mgp->fw_ver_major, mgp->fw_ver_minor,
661 static int myri10ge_get_firmware_capabilities(struct myri10ge_priv *mgp)
663 struct myri10ge_cmd cmd;
666 /* probe for IPv6 TSO support */
667 mgp->features = NETIF_F_SG | NETIF_F_HW_CSUM | NETIF_F_TSO;
668 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_GET_MAX_TSO6_HDR_SIZE,
671 mgp->max_tso6 = cmd.data0;
672 mgp->features |= NETIF_F_TSO6;
675 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_GET_RX_RING_SIZE, &cmd, 0);
677 dev_err(&mgp->pdev->dev,
678 "failed MXGEFW_CMD_GET_RX_RING_SIZE\n");
682 mgp->max_intr_slots = 2 * (cmd.data0 / sizeof(struct mcp_dma_addr));
687 static int myri10ge_load_firmware(struct myri10ge_priv *mgp, int adopt)
689 char __iomem *submit;
690 __be32 buf[16] __attribute__ ((__aligned__(8)));
691 u32 dma_low, dma_high, size;
695 status = myri10ge_load_hotplug_firmware(mgp, &size);
699 dev_warn(&mgp->pdev->dev, "hotplug firmware loading failed\n");
701 /* Do not attempt to adopt firmware if there
706 status = myri10ge_adopt_running_firmware(mgp);
708 dev_err(&mgp->pdev->dev,
709 "failed to adopt running firmware\n");
712 dev_info(&mgp->pdev->dev,
713 "Successfully adopted running firmware\n");
714 if (mgp->tx_boundary == 4096) {
715 dev_warn(&mgp->pdev->dev,
716 "Using firmware currently running on NIC"
718 dev_warn(&mgp->pdev->dev,
719 "performance consider loading optimized "
721 dev_warn(&mgp->pdev->dev, "via hotplug\n");
724 mgp->fw_name = "adopted";
725 mgp->tx_boundary = 2048;
726 myri10ge_dummy_rdma(mgp, 1);
727 status = myri10ge_get_firmware_capabilities(mgp);
731 /* clear confirmation addr */
735 /* send a reload command to the bootstrap MCP, and wait for the
736 * response in the confirmation address. The firmware should
737 * write a -1 there to indicate it is alive and well
739 dma_low = MYRI10GE_LOWPART_TO_U32(mgp->cmd_bus);
740 dma_high = MYRI10GE_HIGHPART_TO_U32(mgp->cmd_bus);
742 buf[0] = htonl(dma_high); /* confirm addr MSW */
743 buf[1] = htonl(dma_low); /* confirm addr LSW */
744 buf[2] = MYRI10GE_NO_CONFIRM_DATA; /* confirm data */
746 /* FIX: All newest firmware should un-protect the bottom of
747 * the sram before handoff. However, the very first interfaces
748 * do not. Therefore the handoff copy must skip the first 8 bytes
750 buf[3] = htonl(MYRI10GE_FW_OFFSET + 8); /* where the code starts */
751 buf[4] = htonl(size - 8); /* length of code */
752 buf[5] = htonl(8); /* where to copy to */
753 buf[6] = htonl(0); /* where to jump to */
755 submit = mgp->sram + MXGEFW_BOOT_HANDOFF;
757 myri10ge_pio_copy(submit, &buf, sizeof(buf));
762 while (mgp->cmd->data != MYRI10GE_NO_CONFIRM_DATA && i < 9) {
766 if (mgp->cmd->data != MYRI10GE_NO_CONFIRM_DATA) {
767 dev_err(&mgp->pdev->dev, "handoff failed\n");
770 myri10ge_dummy_rdma(mgp, 1);
771 status = myri10ge_get_firmware_capabilities(mgp);
776 static int myri10ge_update_mac_address(struct myri10ge_priv *mgp, u8 * addr)
778 struct myri10ge_cmd cmd;
781 cmd.data0 = ((addr[0] << 24) | (addr[1] << 16)
782 | (addr[2] << 8) | addr[3]);
784 cmd.data1 = ((addr[4] << 8) | (addr[5]));
786 status = myri10ge_send_cmd(mgp, MXGEFW_SET_MAC_ADDRESS, &cmd, 0);
790 static int myri10ge_change_pause(struct myri10ge_priv *mgp, int pause)
792 struct myri10ge_cmd cmd;
795 ctl = pause ? MXGEFW_ENABLE_FLOW_CONTROL : MXGEFW_DISABLE_FLOW_CONTROL;
796 status = myri10ge_send_cmd(mgp, ctl, &cmd, 0);
800 "myri10ge: %s: Failed to set flow control mode\n",
809 myri10ge_change_promisc(struct myri10ge_priv *mgp, int promisc, int atomic)
811 struct myri10ge_cmd cmd;
814 ctl = promisc ? MXGEFW_ENABLE_PROMISC : MXGEFW_DISABLE_PROMISC;
815 status = myri10ge_send_cmd(mgp, ctl, &cmd, atomic);
817 printk(KERN_ERR "myri10ge: %s: Failed to set promisc mode\n",
821 static int myri10ge_dma_test(struct myri10ge_priv *mgp, int test_type)
823 struct myri10ge_cmd cmd;
826 struct page *dmatest_page;
827 dma_addr_t dmatest_bus;
830 dmatest_page = alloc_page(GFP_KERNEL);
833 dmatest_bus = pci_map_page(mgp->pdev, dmatest_page, 0, PAGE_SIZE,
836 /* Run a small DMA test.
837 * The magic multipliers to the length tell the firmware
838 * to do DMA read, write, or read+write tests. The
839 * results are returned in cmd.data0. The upper 16
840 * bits or the return is the number of transfers completed.
841 * The lower 16 bits is the time in 0.5us ticks that the
842 * transfers took to complete.
845 len = mgp->tx_boundary;
847 cmd.data0 = MYRI10GE_LOWPART_TO_U32(dmatest_bus);
848 cmd.data1 = MYRI10GE_HIGHPART_TO_U32(dmatest_bus);
849 cmd.data2 = len * 0x10000;
850 status = myri10ge_send_cmd(mgp, test_type, &cmd, 0);
855 mgp->read_dma = ((cmd.data0 >> 16) * len * 2) / (cmd.data0 & 0xffff);
856 cmd.data0 = MYRI10GE_LOWPART_TO_U32(dmatest_bus);
857 cmd.data1 = MYRI10GE_HIGHPART_TO_U32(dmatest_bus);
858 cmd.data2 = len * 0x1;
859 status = myri10ge_send_cmd(mgp, test_type, &cmd, 0);
864 mgp->write_dma = ((cmd.data0 >> 16) * len * 2) / (cmd.data0 & 0xffff);
866 cmd.data0 = MYRI10GE_LOWPART_TO_U32(dmatest_bus);
867 cmd.data1 = MYRI10GE_HIGHPART_TO_U32(dmatest_bus);
868 cmd.data2 = len * 0x10001;
869 status = myri10ge_send_cmd(mgp, test_type, &cmd, 0);
874 mgp->read_write_dma = ((cmd.data0 >> 16) * len * 2 * 2) /
875 (cmd.data0 & 0xffff);
878 pci_unmap_page(mgp->pdev, dmatest_bus, PAGE_SIZE, DMA_BIDIRECTIONAL);
879 put_page(dmatest_page);
881 if (status != 0 && test_type != MXGEFW_CMD_UNALIGNED_TEST)
882 dev_warn(&mgp->pdev->dev, "DMA %s benchmark failed: %d\n",
888 static int myri10ge_reset(struct myri10ge_priv *mgp)
890 struct myri10ge_cmd cmd;
891 struct myri10ge_slice_state *ss;
895 unsigned long dca_tag_off;
898 /* try to send a reset command to the card to see if it
900 memset(&cmd, 0, sizeof(cmd));
901 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_RESET, &cmd, 0);
903 dev_err(&mgp->pdev->dev, "failed reset\n");
907 (void)myri10ge_dma_test(mgp, MXGEFW_DMA_TEST);
909 * Use non-ndis mcp_slot (eg, 4 bytes total,
910 * no toeplitz hash value returned. Older firmware will
911 * not understand this command, but will use the correct
912 * sized mcp_slot, so we ignore error returns
914 cmd.data0 = MXGEFW_RSS_MCP_SLOT_TYPE_MIN;
915 (void)myri10ge_send_cmd(mgp, MXGEFW_CMD_SET_RSS_MCP_SLOT_TYPE, &cmd, 0);
917 /* Now exchange information about interrupts */
919 bytes = mgp->max_intr_slots * sizeof(*mgp->ss[0].rx_done.entry);
920 cmd.data0 = (u32) bytes;
921 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_SET_INTRQ_SIZE, &cmd, 0);
924 * Even though we already know how many slices are supported
925 * via myri10ge_probe_slices() MXGEFW_CMD_GET_MAX_RSS_QUEUES
926 * has magic side effects, and must be called after a reset.
927 * It must be called prior to calling any RSS related cmds,
928 * including assigning an interrupt queue for anything but
929 * slice 0. It must also be called *after*
930 * MXGEFW_CMD_SET_INTRQ_SIZE, since the intrq size is used by
931 * the firmware to compute offsets.
934 if (mgp->num_slices > 1) {
936 /* ask the maximum number of slices it supports */
937 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_GET_MAX_RSS_QUEUES,
940 dev_err(&mgp->pdev->dev,
941 "failed to get number of slices\n");
945 * MXGEFW_CMD_ENABLE_RSS_QUEUES must be called prior
946 * to setting up the interrupt queue DMA
949 cmd.data0 = mgp->num_slices;
950 cmd.data1 = 1; /* use MSI-X */
951 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_ENABLE_RSS_QUEUES,
954 dev_err(&mgp->pdev->dev,
955 "failed to set number of slices\n");
960 for (i = 0; i < mgp->num_slices; i++) {
962 cmd.data0 = MYRI10GE_LOWPART_TO_U32(ss->rx_done.bus);
963 cmd.data1 = MYRI10GE_HIGHPART_TO_U32(ss->rx_done.bus);
965 status |= myri10ge_send_cmd(mgp, MXGEFW_CMD_SET_INTRQ_DMA,
970 myri10ge_send_cmd(mgp, MXGEFW_CMD_GET_IRQ_ACK_OFFSET, &cmd, 0);
971 for (i = 0; i < mgp->num_slices; i++) {
974 (__iomem __be32 *) (mgp->sram + cmd.data0 + 8 * i);
976 status |= myri10ge_send_cmd(mgp, MXGEFW_CMD_GET_IRQ_DEASSERT_OFFSET,
978 mgp->irq_deassert = (__iomem __be32 *) (mgp->sram + cmd.data0);
980 status |= myri10ge_send_cmd
981 (mgp, MXGEFW_CMD_GET_INTR_COAL_DELAY_OFFSET, &cmd, 0);
982 mgp->intr_coal_delay_ptr = (__iomem __be32 *) (mgp->sram + cmd.data0);
984 dev_err(&mgp->pdev->dev, "failed set interrupt parameters\n");
987 put_be32(htonl(mgp->intr_coal_delay), mgp->intr_coal_delay_ptr);
990 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_GET_DCA_OFFSET, &cmd, 0);
991 dca_tag_off = cmd.data0;
992 for (i = 0; i < mgp->num_slices; i++) {
995 ss->dca_tag = (__iomem __be32 *)
996 (mgp->sram + dca_tag_off + 4 * i);
1001 #endif /* CONFIG_DCA */
1003 /* reset mcp/driver shared state back to 0 */
1005 mgp->link_changes = 0;
1006 for (i = 0; i < mgp->num_slices; i++) {
1009 memset(ss->rx_done.entry, 0, bytes);
1012 ss->tx.pkt_start = 0;
1013 ss->tx.pkt_done = 0;
1015 ss->rx_small.cnt = 0;
1016 ss->rx_done.idx = 0;
1017 ss->rx_done.cnt = 0;
1018 ss->tx.wake_queue = 0;
1019 ss->tx.stop_queue = 0;
1022 status = myri10ge_update_mac_address(mgp, mgp->dev->dev_addr);
1023 myri10ge_change_pause(mgp, mgp->pause);
1024 myri10ge_set_multicast_list(mgp->dev);
1030 myri10ge_write_dca(struct myri10ge_slice_state *ss, int cpu, int tag)
1033 ss->cached_dca_tag = tag;
1034 put_be32(htonl(tag), ss->dca_tag);
1037 static inline void myri10ge_update_dca(struct myri10ge_slice_state *ss)
1039 int cpu = get_cpu();
1042 if (cpu != ss->cpu) {
1043 tag = dca_get_tag(cpu);
1044 if (ss->cached_dca_tag != tag)
1045 myri10ge_write_dca(ss, cpu, tag);
1050 static void myri10ge_setup_dca(struct myri10ge_priv *mgp)
1053 struct pci_dev *pdev = mgp->pdev;
1055 if (mgp->ss[0].dca_tag == NULL || mgp->dca_enabled)
1057 if (!myri10ge_dca) {
1058 dev_err(&pdev->dev, "dca disabled by administrator\n");
1061 err = dca_add_requester(&pdev->dev);
1064 "dca_add_requester() failed, err=%d\n", err);
1067 mgp->dca_enabled = 1;
1068 for (i = 0; i < mgp->num_slices; i++)
1069 myri10ge_write_dca(&mgp->ss[i], -1, 0);
1072 static void myri10ge_teardown_dca(struct myri10ge_priv *mgp)
1074 struct pci_dev *pdev = mgp->pdev;
1077 if (!mgp->dca_enabled)
1079 mgp->dca_enabled = 0;
1080 err = dca_remove_requester(&pdev->dev);
1083 static int myri10ge_notify_dca_device(struct device *dev, void *data)
1085 struct myri10ge_priv *mgp;
1086 unsigned long event;
1088 mgp = dev_get_drvdata(dev);
1089 event = *(unsigned long *)data;
1091 if (event == DCA_PROVIDER_ADD)
1092 myri10ge_setup_dca(mgp);
1093 else if (event == DCA_PROVIDER_REMOVE)
1094 myri10ge_teardown_dca(mgp);
1097 #endif /* CONFIG_DCA */
1100 myri10ge_submit_8rx(struct mcp_kreq_ether_recv __iomem * dst,
1101 struct mcp_kreq_ether_recv *src)
1105 low = src->addr_low;
1106 src->addr_low = htonl(DMA_32BIT_MASK);
1107 myri10ge_pio_copy(dst, src, 4 * sizeof(*src));
1109 myri10ge_pio_copy(dst + 4, src + 4, 4 * sizeof(*src));
1111 src->addr_low = low;
1112 put_be32(low, &dst->addr_low);
1116 static inline void myri10ge_vlan_ip_csum(struct sk_buff *skb, __wsum hw_csum)
1118 struct vlan_hdr *vh = (struct vlan_hdr *)(skb->data);
1120 if ((skb->protocol == htons(ETH_P_8021Q)) &&
1121 (vh->h_vlan_encapsulated_proto == htons(ETH_P_IP) ||
1122 vh->h_vlan_encapsulated_proto == htons(ETH_P_IPV6))) {
1123 skb->csum = hw_csum;
1124 skb->ip_summed = CHECKSUM_COMPLETE;
1129 myri10ge_rx_skb_build(struct sk_buff *skb, u8 * va,
1130 struct skb_frag_struct *rx_frags, int len, int hlen)
1132 struct skb_frag_struct *skb_frags;
1134 skb->len = skb->data_len = len;
1135 skb->truesize = len + sizeof(struct sk_buff);
1136 /* attach the page(s) */
1138 skb_frags = skb_shinfo(skb)->frags;
1140 memcpy(skb_frags, rx_frags, sizeof(*skb_frags));
1141 len -= rx_frags->size;
1144 skb_shinfo(skb)->nr_frags++;
1147 /* pskb_may_pull is not available in irq context, but
1148 * skb_pull() (for ether_pad and eth_type_trans()) requires
1149 * the beginning of the packet in skb_headlen(), move it
1151 skb_copy_to_linear_data(skb, va, hlen);
1152 skb_shinfo(skb)->frags[0].page_offset += hlen;
1153 skb_shinfo(skb)->frags[0].size -= hlen;
1154 skb->data_len -= hlen;
1156 skb_pull(skb, MXGEFW_PAD);
1160 myri10ge_alloc_rx_pages(struct myri10ge_priv *mgp, struct myri10ge_rx_buf *rx,
1161 int bytes, int watchdog)
1166 if (unlikely(rx->watchdog_needed && !watchdog))
1169 /* try to refill entire ring */
1170 while (rx->fill_cnt != (rx->cnt + rx->mask + 1)) {
1171 idx = rx->fill_cnt & rx->mask;
1172 if (rx->page_offset + bytes <= MYRI10GE_ALLOC_SIZE) {
1173 /* we can use part of previous page */
1176 /* we need a new page */
1178 alloc_pages(GFP_ATOMIC | __GFP_COMP,
1179 MYRI10GE_ALLOC_ORDER);
1180 if (unlikely(page == NULL)) {
1181 if (rx->fill_cnt - rx->cnt < 16)
1182 rx->watchdog_needed = 1;
1186 rx->page_offset = 0;
1187 rx->bus = pci_map_page(mgp->pdev, page, 0,
1188 MYRI10GE_ALLOC_SIZE,
1189 PCI_DMA_FROMDEVICE);
1191 rx->info[idx].page = rx->page;
1192 rx->info[idx].page_offset = rx->page_offset;
1193 /* note that this is the address of the start of the
1195 pci_unmap_addr_set(&rx->info[idx], bus, rx->bus);
1196 rx->shadow[idx].addr_low =
1197 htonl(MYRI10GE_LOWPART_TO_U32(rx->bus) + rx->page_offset);
1198 rx->shadow[idx].addr_high =
1199 htonl(MYRI10GE_HIGHPART_TO_U32(rx->bus));
1201 /* start next packet on a cacheline boundary */
1202 rx->page_offset += SKB_DATA_ALIGN(bytes);
1204 #if MYRI10GE_ALLOC_SIZE > 4096
1205 /* don't cross a 4KB boundary */
1206 if ((rx->page_offset >> 12) !=
1207 ((rx->page_offset + bytes - 1) >> 12))
1208 rx->page_offset = (rx->page_offset + 4096) & ~4095;
1212 /* copy 8 descriptors to the firmware at a time */
1213 if ((idx & 7) == 7) {
1214 if (rx->wc_fifo == NULL)
1215 myri10ge_submit_8rx(&rx->lanai[idx - 7],
1216 &rx->shadow[idx - 7]);
1219 myri10ge_pio_copy(rx->wc_fifo,
1220 &rx->shadow[idx - 7], 64);
1227 myri10ge_unmap_rx_page(struct pci_dev *pdev,
1228 struct myri10ge_rx_buffer_state *info, int bytes)
1230 /* unmap the recvd page if we're the only or last user of it */
1231 if (bytes >= MYRI10GE_ALLOC_SIZE / 2 ||
1232 (info->page_offset + 2 * bytes) > MYRI10GE_ALLOC_SIZE) {
1233 pci_unmap_page(pdev, (pci_unmap_addr(info, bus)
1234 & ~(MYRI10GE_ALLOC_SIZE - 1)),
1235 MYRI10GE_ALLOC_SIZE, PCI_DMA_FROMDEVICE);
1239 #define MYRI10GE_HLEN 64 /* The number of bytes to copy from a
1240 * page into an skb */
1243 myri10ge_rx_done(struct myri10ge_slice_state *ss, struct myri10ge_rx_buf *rx,
1244 int bytes, int len, __wsum csum)
1246 struct myri10ge_priv *mgp = ss->mgp;
1247 struct sk_buff *skb;
1248 struct skb_frag_struct rx_frags[MYRI10GE_MAX_FRAGS_PER_FRAME];
1249 int i, idx, hlen, remainder;
1250 struct pci_dev *pdev = mgp->pdev;
1251 struct net_device *dev = mgp->dev;
1255 idx = rx->cnt & rx->mask;
1256 va = page_address(rx->info[idx].page) + rx->info[idx].page_offset;
1258 /* Fill skb_frag_struct(s) with data from our receive */
1259 for (i = 0, remainder = len; remainder > 0; i++) {
1260 myri10ge_unmap_rx_page(pdev, &rx->info[idx], bytes);
1261 rx_frags[i].page = rx->info[idx].page;
1262 rx_frags[i].page_offset = rx->info[idx].page_offset;
1263 if (remainder < MYRI10GE_ALLOC_SIZE)
1264 rx_frags[i].size = remainder;
1266 rx_frags[i].size = MYRI10GE_ALLOC_SIZE;
1268 idx = rx->cnt & rx->mask;
1269 remainder -= MYRI10GE_ALLOC_SIZE;
1272 if (mgp->csum_flag && myri10ge_lro) {
1273 rx_frags[0].page_offset += MXGEFW_PAD;
1274 rx_frags[0].size -= MXGEFW_PAD;
1276 lro_receive_frags(&ss->rx_done.lro_mgr, rx_frags,
1277 /* opaque, will come back in get_frag_header */
1279 (void *)(__force unsigned long)csum, csum);
1284 hlen = MYRI10GE_HLEN > len ? len : MYRI10GE_HLEN;
1286 /* allocate an skb to attach the page(s) to. This is done
1287 * after trying LRO, so as to avoid skb allocation overheads */
1289 skb = netdev_alloc_skb(dev, MYRI10GE_HLEN + 16);
1290 if (unlikely(skb == NULL)) {
1291 mgp->stats.rx_dropped++;
1294 put_page(rx_frags[i].page);
1299 /* Attach the pages to the skb, and trim off any padding */
1300 myri10ge_rx_skb_build(skb, va, rx_frags, len, hlen);
1301 if (skb_shinfo(skb)->frags[0].size <= 0) {
1302 put_page(skb_shinfo(skb)->frags[0].page);
1303 skb_shinfo(skb)->nr_frags = 0;
1305 skb->protocol = eth_type_trans(skb, dev);
1307 if (mgp->csum_flag) {
1308 if ((skb->protocol == htons(ETH_P_IP)) ||
1309 (skb->protocol == htons(ETH_P_IPV6))) {
1311 skb->ip_summed = CHECKSUM_COMPLETE;
1313 myri10ge_vlan_ip_csum(skb, csum);
1315 netif_receive_skb(skb);
1316 dev->last_rx = jiffies;
1321 myri10ge_tx_done(struct myri10ge_slice_state *ss, int mcp_index)
1323 struct pci_dev *pdev = ss->mgp->pdev;
1324 struct myri10ge_tx_buf *tx = &ss->tx;
1325 struct sk_buff *skb;
1328 while (tx->pkt_done != mcp_index) {
1329 idx = tx->done & tx->mask;
1330 skb = tx->info[idx].skb;
1333 tx->info[idx].skb = NULL;
1334 if (tx->info[idx].last) {
1336 tx->info[idx].last = 0;
1339 len = pci_unmap_len(&tx->info[idx], len);
1340 pci_unmap_len_set(&tx->info[idx], len, 0);
1342 ss->stats.tx_bytes += skb->len;
1343 ss->stats.tx_packets++;
1344 dev_kfree_skb_irq(skb);
1346 pci_unmap_single(pdev,
1347 pci_unmap_addr(&tx->info[idx],
1352 pci_unmap_page(pdev,
1353 pci_unmap_addr(&tx->info[idx],
1358 /* start the queue if we've stopped it */
1359 if (netif_queue_stopped(ss->dev)
1360 && tx->req - tx->done < (tx->mask >> 1)) {
1362 netif_wake_queue(ss->dev);
1367 myri10ge_clean_rx_done(struct myri10ge_slice_state *ss, int budget)
1369 struct myri10ge_rx_done *rx_done = &ss->rx_done;
1370 struct myri10ge_priv *mgp = ss->mgp;
1371 unsigned long rx_bytes = 0;
1372 unsigned long rx_packets = 0;
1373 unsigned long rx_ok;
1375 int idx = rx_done->idx;
1376 int cnt = rx_done->cnt;
1381 while (rx_done->entry[idx].length != 0 && work_done < budget) {
1382 length = ntohs(rx_done->entry[idx].length);
1383 rx_done->entry[idx].length = 0;
1384 checksum = csum_unfold(rx_done->entry[idx].checksum);
1385 if (length <= mgp->small_bytes)
1386 rx_ok = myri10ge_rx_done(ss, &ss->rx_small,
1390 rx_ok = myri10ge_rx_done(ss, &ss->rx_big,
1393 rx_packets += rx_ok;
1394 rx_bytes += rx_ok * (unsigned long)length;
1396 idx = cnt & (mgp->max_intr_slots - 1);
1401 ss->stats.rx_packets += rx_packets;
1402 ss->stats.rx_bytes += rx_bytes;
1405 lro_flush_all(&rx_done->lro_mgr);
1407 /* restock receive rings if needed */
1408 if (ss->rx_small.fill_cnt - ss->rx_small.cnt < myri10ge_fill_thresh)
1409 myri10ge_alloc_rx_pages(mgp, &ss->rx_small,
1410 mgp->small_bytes + MXGEFW_PAD, 0);
1411 if (ss->rx_big.fill_cnt - ss->rx_big.cnt < myri10ge_fill_thresh)
1412 myri10ge_alloc_rx_pages(mgp, &ss->rx_big, mgp->big_bytes, 0);
1417 static inline void myri10ge_check_statblock(struct myri10ge_priv *mgp)
1419 struct mcp_irq_data *stats = mgp->ss[0].fw_stats;
1421 if (unlikely(stats->stats_updated)) {
1422 unsigned link_up = ntohl(stats->link_up);
1423 if (mgp->link_state != link_up) {
1424 mgp->link_state = link_up;
1426 if (mgp->link_state == MXGEFW_LINK_UP) {
1427 if (netif_msg_link(mgp))
1429 "myri10ge: %s: link up\n",
1431 netif_carrier_on(mgp->dev);
1432 mgp->link_changes++;
1434 if (netif_msg_link(mgp))
1436 "myri10ge: %s: link %s\n",
1438 (link_up == MXGEFW_LINK_MYRINET ?
1439 "mismatch (Myrinet detected)" :
1441 netif_carrier_off(mgp->dev);
1442 mgp->link_changes++;
1445 if (mgp->rdma_tags_available !=
1446 ntohl(stats->rdma_tags_available)) {
1447 mgp->rdma_tags_available =
1448 ntohl(stats->rdma_tags_available);
1449 printk(KERN_WARNING "myri10ge: %s: RDMA timed out! "
1450 "%d tags left\n", mgp->dev->name,
1451 mgp->rdma_tags_available);
1453 mgp->down_cnt += stats->link_down;
1454 if (stats->link_down)
1455 wake_up(&mgp->down_wq);
1459 static int myri10ge_poll(struct napi_struct *napi, int budget)
1461 struct myri10ge_slice_state *ss =
1462 container_of(napi, struct myri10ge_slice_state, napi);
1463 struct net_device *netdev = ss->mgp->dev;
1467 if (ss->mgp->dca_enabled)
1468 myri10ge_update_dca(ss);
1471 /* process as many rx events as NAPI will allow */
1472 work_done = myri10ge_clean_rx_done(ss, budget);
1474 if (work_done < budget) {
1475 netif_rx_complete(netdev, napi);
1476 put_be32(htonl(3), ss->irq_claim);
1481 static irqreturn_t myri10ge_intr(int irq, void *arg)
1483 struct myri10ge_slice_state *ss = arg;
1484 struct myri10ge_priv *mgp = ss->mgp;
1485 struct mcp_irq_data *stats = ss->fw_stats;
1486 struct myri10ge_tx_buf *tx = &ss->tx;
1487 u32 send_done_count;
1490 /* an interrupt on a non-zero slice is implicitly valid
1491 * since MSI-X irqs are not shared */
1492 if (ss != mgp->ss) {
1493 netif_rx_schedule(ss->dev, &ss->napi);
1494 return (IRQ_HANDLED);
1497 /* make sure it is our IRQ, and that the DMA has finished */
1498 if (unlikely(!stats->valid))
1501 /* low bit indicates receives are present, so schedule
1502 * napi poll handler */
1503 if (stats->valid & 1)
1504 netif_rx_schedule(ss->dev, &ss->napi);
1506 if (!mgp->msi_enabled && !mgp->msix_enabled) {
1507 put_be32(0, mgp->irq_deassert);
1508 if (!myri10ge_deassert_wait)
1514 /* Wait for IRQ line to go low, if using INTx */
1518 /* check for transmit completes and receives */
1519 send_done_count = ntohl(stats->send_done_count);
1520 if (send_done_count != tx->pkt_done)
1521 myri10ge_tx_done(ss, (int)send_done_count);
1522 if (unlikely(i > myri10ge_max_irq_loops)) {
1523 printk(KERN_WARNING "myri10ge: %s: irq stuck?\n",
1526 schedule_work(&mgp->watchdog_work);
1528 if (likely(stats->valid == 0))
1534 myri10ge_check_statblock(mgp);
1536 put_be32(htonl(3), ss->irq_claim + 1);
1537 return (IRQ_HANDLED);
1541 myri10ge_get_settings(struct net_device *netdev, struct ethtool_cmd *cmd)
1543 struct myri10ge_priv *mgp = netdev_priv(netdev);
1547 cmd->autoneg = AUTONEG_DISABLE;
1548 cmd->speed = SPEED_10000;
1549 cmd->duplex = DUPLEX_FULL;
1552 * parse the product code to deterimine the interface type
1553 * (CX4, XFP, Quad Ribbon Fiber) by looking at the character
1554 * after the 3rd dash in the driver's cached copy of the
1555 * EEPROM's product code string.
1557 ptr = mgp->product_code_string;
1559 printk(KERN_ERR "myri10ge: %s: Missing product code\n",
1563 for (i = 0; i < 3; i++, ptr++) {
1564 ptr = strchr(ptr, '-');
1566 printk(KERN_ERR "myri10ge: %s: Invalid product "
1567 "code %s\n", netdev->name,
1568 mgp->product_code_string);
1572 if (*ptr == 'R' || *ptr == 'Q') {
1573 /* We've found either an XFP or quad ribbon fiber */
1574 cmd->port = PORT_FIBRE;
1580 myri10ge_get_drvinfo(struct net_device *netdev, struct ethtool_drvinfo *info)
1582 struct myri10ge_priv *mgp = netdev_priv(netdev);
1584 strlcpy(info->driver, "myri10ge", sizeof(info->driver));
1585 strlcpy(info->version, MYRI10GE_VERSION_STR, sizeof(info->version));
1586 strlcpy(info->fw_version, mgp->fw_version, sizeof(info->fw_version));
1587 strlcpy(info->bus_info, pci_name(mgp->pdev), sizeof(info->bus_info));
1591 myri10ge_get_coalesce(struct net_device *netdev, struct ethtool_coalesce *coal)
1593 struct myri10ge_priv *mgp = netdev_priv(netdev);
1595 coal->rx_coalesce_usecs = mgp->intr_coal_delay;
1600 myri10ge_set_coalesce(struct net_device *netdev, struct ethtool_coalesce *coal)
1602 struct myri10ge_priv *mgp = netdev_priv(netdev);
1604 mgp->intr_coal_delay = coal->rx_coalesce_usecs;
1605 put_be32(htonl(mgp->intr_coal_delay), mgp->intr_coal_delay_ptr);
1610 myri10ge_get_pauseparam(struct net_device *netdev,
1611 struct ethtool_pauseparam *pause)
1613 struct myri10ge_priv *mgp = netdev_priv(netdev);
1616 pause->rx_pause = mgp->pause;
1617 pause->tx_pause = mgp->pause;
1621 myri10ge_set_pauseparam(struct net_device *netdev,
1622 struct ethtool_pauseparam *pause)
1624 struct myri10ge_priv *mgp = netdev_priv(netdev);
1626 if (pause->tx_pause != mgp->pause)
1627 return myri10ge_change_pause(mgp, pause->tx_pause);
1628 if (pause->rx_pause != mgp->pause)
1629 return myri10ge_change_pause(mgp, pause->tx_pause);
1630 if (pause->autoneg != 0)
1636 myri10ge_get_ringparam(struct net_device *netdev,
1637 struct ethtool_ringparam *ring)
1639 struct myri10ge_priv *mgp = netdev_priv(netdev);
1641 ring->rx_mini_max_pending = mgp->ss[0].rx_small.mask + 1;
1642 ring->rx_max_pending = mgp->ss[0].rx_big.mask + 1;
1643 ring->rx_jumbo_max_pending = 0;
1644 ring->tx_max_pending = mgp->ss[0].rx_small.mask + 1;
1645 ring->rx_mini_pending = ring->rx_mini_max_pending;
1646 ring->rx_pending = ring->rx_max_pending;
1647 ring->rx_jumbo_pending = ring->rx_jumbo_max_pending;
1648 ring->tx_pending = ring->tx_max_pending;
1651 static u32 myri10ge_get_rx_csum(struct net_device *netdev)
1653 struct myri10ge_priv *mgp = netdev_priv(netdev);
1661 static int myri10ge_set_rx_csum(struct net_device *netdev, u32 csum_enabled)
1663 struct myri10ge_priv *mgp = netdev_priv(netdev);
1666 mgp->csum_flag = MXGEFW_FLAGS_CKSUM;
1672 static int myri10ge_set_tso(struct net_device *netdev, u32 tso_enabled)
1674 struct myri10ge_priv *mgp = netdev_priv(netdev);
1675 unsigned long flags = mgp->features & (NETIF_F_TSO6 | NETIF_F_TSO);
1678 netdev->features |= flags;
1680 netdev->features &= ~flags;
1684 static const char myri10ge_gstrings_main_stats[][ETH_GSTRING_LEN] = {
1685 "rx_packets", "tx_packets", "rx_bytes", "tx_bytes", "rx_errors",
1686 "tx_errors", "rx_dropped", "tx_dropped", "multicast", "collisions",
1687 "rx_length_errors", "rx_over_errors", "rx_crc_errors",
1688 "rx_frame_errors", "rx_fifo_errors", "rx_missed_errors",
1689 "tx_aborted_errors", "tx_carrier_errors", "tx_fifo_errors",
1690 "tx_heartbeat_errors", "tx_window_errors",
1691 /* device-specific stats */
1692 "tx_boundary", "WC", "irq", "MSI", "MSIX",
1693 "read_dma_bw_MBs", "write_dma_bw_MBs", "read_write_dma_bw_MBs",
1694 "serial_number", "watchdog_resets",
1696 "dca_capable", "dca_enabled",
1698 "link_changes", "link_up", "dropped_link_overflow",
1699 "dropped_link_error_or_filtered",
1700 "dropped_pause", "dropped_bad_phy", "dropped_bad_crc32",
1701 "dropped_unicast_filtered", "dropped_multicast_filtered",
1702 "dropped_runt", "dropped_overrun", "dropped_no_small_buffer",
1703 "dropped_no_big_buffer"
1706 static const char myri10ge_gstrings_slice_stats[][ETH_GSTRING_LEN] = {
1707 "----------- slice ---------",
1708 "tx_pkt_start", "tx_pkt_done", "tx_req", "tx_done",
1709 "rx_small_cnt", "rx_big_cnt",
1710 "wake_queue", "stop_queue", "tx_linearized", "LRO aggregated",
1712 "LRO avg aggr", "LRO no_desc"
1715 #define MYRI10GE_NET_STATS_LEN 21
1716 #define MYRI10GE_MAIN_STATS_LEN ARRAY_SIZE(myri10ge_gstrings_main_stats)
1717 #define MYRI10GE_SLICE_STATS_LEN ARRAY_SIZE(myri10ge_gstrings_slice_stats)
1720 myri10ge_get_strings(struct net_device *netdev, u32 stringset, u8 * data)
1722 struct myri10ge_priv *mgp = netdev_priv(netdev);
1725 switch (stringset) {
1727 memcpy(data, *myri10ge_gstrings_main_stats,
1728 sizeof(myri10ge_gstrings_main_stats));
1729 data += sizeof(myri10ge_gstrings_main_stats);
1730 for (i = 0; i < mgp->num_slices; i++) {
1731 memcpy(data, *myri10ge_gstrings_slice_stats,
1732 sizeof(myri10ge_gstrings_slice_stats));
1733 data += sizeof(myri10ge_gstrings_slice_stats);
1739 static int myri10ge_get_sset_count(struct net_device *netdev, int sset)
1741 struct myri10ge_priv *mgp = netdev_priv(netdev);
1745 return MYRI10GE_MAIN_STATS_LEN +
1746 mgp->num_slices * MYRI10GE_SLICE_STATS_LEN;
1753 myri10ge_get_ethtool_stats(struct net_device *netdev,
1754 struct ethtool_stats *stats, u64 * data)
1756 struct myri10ge_priv *mgp = netdev_priv(netdev);
1757 struct myri10ge_slice_state *ss;
1761 for (i = 0; i < MYRI10GE_NET_STATS_LEN; i++)
1762 data[i] = ((unsigned long *)&mgp->stats)[i];
1764 data[i++] = (unsigned int)mgp->tx_boundary;
1765 data[i++] = (unsigned int)mgp->wc_enabled;
1766 data[i++] = (unsigned int)mgp->pdev->irq;
1767 data[i++] = (unsigned int)mgp->msi_enabled;
1768 data[i++] = (unsigned int)mgp->msix_enabled;
1769 data[i++] = (unsigned int)mgp->read_dma;
1770 data[i++] = (unsigned int)mgp->write_dma;
1771 data[i++] = (unsigned int)mgp->read_write_dma;
1772 data[i++] = (unsigned int)mgp->serial_number;
1773 data[i++] = (unsigned int)mgp->watchdog_resets;
1775 data[i++] = (unsigned int)(mgp->ss[0].dca_tag != NULL);
1776 data[i++] = (unsigned int)(mgp->dca_enabled);
1778 data[i++] = (unsigned int)mgp->link_changes;
1780 /* firmware stats are useful only in the first slice */
1782 data[i++] = (unsigned int)ntohl(ss->fw_stats->link_up);
1783 data[i++] = (unsigned int)ntohl(ss->fw_stats->dropped_link_overflow);
1785 (unsigned int)ntohl(ss->fw_stats->dropped_link_error_or_filtered);
1786 data[i++] = (unsigned int)ntohl(ss->fw_stats->dropped_pause);
1787 data[i++] = (unsigned int)ntohl(ss->fw_stats->dropped_bad_phy);
1788 data[i++] = (unsigned int)ntohl(ss->fw_stats->dropped_bad_crc32);
1789 data[i++] = (unsigned int)ntohl(ss->fw_stats->dropped_unicast_filtered);
1791 (unsigned int)ntohl(ss->fw_stats->dropped_multicast_filtered);
1792 data[i++] = (unsigned int)ntohl(ss->fw_stats->dropped_runt);
1793 data[i++] = (unsigned int)ntohl(ss->fw_stats->dropped_overrun);
1794 data[i++] = (unsigned int)ntohl(ss->fw_stats->dropped_no_small_buffer);
1795 data[i++] = (unsigned int)ntohl(ss->fw_stats->dropped_no_big_buffer);
1797 for (slice = 0; slice < mgp->num_slices; slice++) {
1798 ss = &mgp->ss[slice];
1800 data[i++] = (unsigned int)ss->tx.pkt_start;
1801 data[i++] = (unsigned int)ss->tx.pkt_done;
1802 data[i++] = (unsigned int)ss->tx.req;
1803 data[i++] = (unsigned int)ss->tx.done;
1804 data[i++] = (unsigned int)ss->rx_small.cnt;
1805 data[i++] = (unsigned int)ss->rx_big.cnt;
1806 data[i++] = (unsigned int)ss->tx.wake_queue;
1807 data[i++] = (unsigned int)ss->tx.stop_queue;
1808 data[i++] = (unsigned int)ss->tx.linearized;
1809 data[i++] = ss->rx_done.lro_mgr.stats.aggregated;
1810 data[i++] = ss->rx_done.lro_mgr.stats.flushed;
1811 if (ss->rx_done.lro_mgr.stats.flushed)
1812 data[i++] = ss->rx_done.lro_mgr.stats.aggregated /
1813 ss->rx_done.lro_mgr.stats.flushed;
1816 data[i++] = ss->rx_done.lro_mgr.stats.no_desc;
1820 static void myri10ge_set_msglevel(struct net_device *netdev, u32 value)
1822 struct myri10ge_priv *mgp = netdev_priv(netdev);
1823 mgp->msg_enable = value;
1826 static u32 myri10ge_get_msglevel(struct net_device *netdev)
1828 struct myri10ge_priv *mgp = netdev_priv(netdev);
1829 return mgp->msg_enable;
1832 static const struct ethtool_ops myri10ge_ethtool_ops = {
1833 .get_settings = myri10ge_get_settings,
1834 .get_drvinfo = myri10ge_get_drvinfo,
1835 .get_coalesce = myri10ge_get_coalesce,
1836 .set_coalesce = myri10ge_set_coalesce,
1837 .get_pauseparam = myri10ge_get_pauseparam,
1838 .set_pauseparam = myri10ge_set_pauseparam,
1839 .get_ringparam = myri10ge_get_ringparam,
1840 .get_rx_csum = myri10ge_get_rx_csum,
1841 .set_rx_csum = myri10ge_set_rx_csum,
1842 .set_tx_csum = ethtool_op_set_tx_hw_csum,
1843 .set_sg = ethtool_op_set_sg,
1844 .set_tso = myri10ge_set_tso,
1845 .get_link = ethtool_op_get_link,
1846 .get_strings = myri10ge_get_strings,
1847 .get_sset_count = myri10ge_get_sset_count,
1848 .get_ethtool_stats = myri10ge_get_ethtool_stats,
1849 .set_msglevel = myri10ge_set_msglevel,
1850 .get_msglevel = myri10ge_get_msglevel
1853 static int myri10ge_allocate_rings(struct myri10ge_slice_state *ss)
1855 struct myri10ge_priv *mgp = ss->mgp;
1856 struct myri10ge_cmd cmd;
1857 struct net_device *dev = mgp->dev;
1858 int tx_ring_size, rx_ring_size;
1859 int tx_ring_entries, rx_ring_entries;
1860 int i, slice, status;
1863 /* get ring sizes */
1864 slice = ss - mgp->ss;
1866 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_GET_SEND_RING_SIZE, &cmd, 0);
1867 tx_ring_size = cmd.data0;
1869 status |= myri10ge_send_cmd(mgp, MXGEFW_CMD_GET_RX_RING_SIZE, &cmd, 0);
1872 rx_ring_size = cmd.data0;
1874 tx_ring_entries = tx_ring_size / sizeof(struct mcp_kreq_ether_send);
1875 rx_ring_entries = rx_ring_size / sizeof(struct mcp_dma_addr);
1876 ss->tx.mask = tx_ring_entries - 1;
1877 ss->rx_small.mask = ss->rx_big.mask = rx_ring_entries - 1;
1881 /* allocate the host shadow rings */
1883 bytes = 8 + (MYRI10GE_MAX_SEND_DESC_TSO + 4)
1884 * sizeof(*ss->tx.req_list);
1885 ss->tx.req_bytes = kzalloc(bytes, GFP_KERNEL);
1886 if (ss->tx.req_bytes == NULL)
1887 goto abort_with_nothing;
1889 /* ensure req_list entries are aligned to 8 bytes */
1890 ss->tx.req_list = (struct mcp_kreq_ether_send *)
1891 ALIGN((unsigned long)ss->tx.req_bytes, 8);
1893 bytes = rx_ring_entries * sizeof(*ss->rx_small.shadow);
1894 ss->rx_small.shadow = kzalloc(bytes, GFP_KERNEL);
1895 if (ss->rx_small.shadow == NULL)
1896 goto abort_with_tx_req_bytes;
1898 bytes = rx_ring_entries * sizeof(*ss->rx_big.shadow);
1899 ss->rx_big.shadow = kzalloc(bytes, GFP_KERNEL);
1900 if (ss->rx_big.shadow == NULL)
1901 goto abort_with_rx_small_shadow;
1903 /* allocate the host info rings */
1905 bytes = tx_ring_entries * sizeof(*ss->tx.info);
1906 ss->tx.info = kzalloc(bytes, GFP_KERNEL);
1907 if (ss->tx.info == NULL)
1908 goto abort_with_rx_big_shadow;
1910 bytes = rx_ring_entries * sizeof(*ss->rx_small.info);
1911 ss->rx_small.info = kzalloc(bytes, GFP_KERNEL);
1912 if (ss->rx_small.info == NULL)
1913 goto abort_with_tx_info;
1915 bytes = rx_ring_entries * sizeof(*ss->rx_big.info);
1916 ss->rx_big.info = kzalloc(bytes, GFP_KERNEL);
1917 if (ss->rx_big.info == NULL)
1918 goto abort_with_rx_small_info;
1920 /* Fill the receive rings */
1922 ss->rx_small.cnt = 0;
1923 ss->rx_big.fill_cnt = 0;
1924 ss->rx_small.fill_cnt = 0;
1925 ss->rx_small.page_offset = MYRI10GE_ALLOC_SIZE;
1926 ss->rx_big.page_offset = MYRI10GE_ALLOC_SIZE;
1927 ss->rx_small.watchdog_needed = 0;
1928 ss->rx_big.watchdog_needed = 0;
1929 myri10ge_alloc_rx_pages(mgp, &ss->rx_small,
1930 mgp->small_bytes + MXGEFW_PAD, 0);
1932 if (ss->rx_small.fill_cnt < ss->rx_small.mask + 1) {
1934 "myri10ge: %s:slice-%d: alloced only %d small bufs\n",
1935 dev->name, slice, ss->rx_small.fill_cnt);
1936 goto abort_with_rx_small_ring;
1939 myri10ge_alloc_rx_pages(mgp, &ss->rx_big, mgp->big_bytes, 0);
1940 if (ss->rx_big.fill_cnt < ss->rx_big.mask + 1) {
1942 "myri10ge: %s:slice-%d: alloced only %d big bufs\n",
1943 dev->name, slice, ss->rx_big.fill_cnt);
1944 goto abort_with_rx_big_ring;
1949 abort_with_rx_big_ring:
1950 for (i = ss->rx_big.cnt; i < ss->rx_big.fill_cnt; i++) {
1951 int idx = i & ss->rx_big.mask;
1952 myri10ge_unmap_rx_page(mgp->pdev, &ss->rx_big.info[idx],
1954 put_page(ss->rx_big.info[idx].page);
1957 abort_with_rx_small_ring:
1958 for (i = ss->rx_small.cnt; i < ss->rx_small.fill_cnt; i++) {
1959 int idx = i & ss->rx_small.mask;
1960 myri10ge_unmap_rx_page(mgp->pdev, &ss->rx_small.info[idx],
1961 mgp->small_bytes + MXGEFW_PAD);
1962 put_page(ss->rx_small.info[idx].page);
1965 kfree(ss->rx_big.info);
1967 abort_with_rx_small_info:
1968 kfree(ss->rx_small.info);
1973 abort_with_rx_big_shadow:
1974 kfree(ss->rx_big.shadow);
1976 abort_with_rx_small_shadow:
1977 kfree(ss->rx_small.shadow);
1979 abort_with_tx_req_bytes:
1980 kfree(ss->tx.req_bytes);
1981 ss->tx.req_bytes = NULL;
1982 ss->tx.req_list = NULL;
1988 static void myri10ge_free_rings(struct myri10ge_slice_state *ss)
1990 struct myri10ge_priv *mgp = ss->mgp;
1991 struct sk_buff *skb;
1992 struct myri10ge_tx_buf *tx;
1995 /* If not allocated, skip it */
1996 if (ss->tx.req_list == NULL)
1999 for (i = ss->rx_big.cnt; i < ss->rx_big.fill_cnt; i++) {
2000 idx = i & ss->rx_big.mask;
2001 if (i == ss->rx_big.fill_cnt - 1)
2002 ss->rx_big.info[idx].page_offset = MYRI10GE_ALLOC_SIZE;
2003 myri10ge_unmap_rx_page(mgp->pdev, &ss->rx_big.info[idx],
2005 put_page(ss->rx_big.info[idx].page);
2008 for (i = ss->rx_small.cnt; i < ss->rx_small.fill_cnt; i++) {
2009 idx = i & ss->rx_small.mask;
2010 if (i == ss->rx_small.fill_cnt - 1)
2011 ss->rx_small.info[idx].page_offset =
2012 MYRI10GE_ALLOC_SIZE;
2013 myri10ge_unmap_rx_page(mgp->pdev, &ss->rx_small.info[idx],
2014 mgp->small_bytes + MXGEFW_PAD);
2015 put_page(ss->rx_small.info[idx].page);
2018 while (tx->done != tx->req) {
2019 idx = tx->done & tx->mask;
2020 skb = tx->info[idx].skb;
2023 tx->info[idx].skb = NULL;
2025 len = pci_unmap_len(&tx->info[idx], len);
2026 pci_unmap_len_set(&tx->info[idx], len, 0);
2028 ss->stats.tx_dropped++;
2029 dev_kfree_skb_any(skb);
2031 pci_unmap_single(mgp->pdev,
2032 pci_unmap_addr(&tx->info[idx],
2037 pci_unmap_page(mgp->pdev,
2038 pci_unmap_addr(&tx->info[idx],
2043 kfree(ss->rx_big.info);
2045 kfree(ss->rx_small.info);
2049 kfree(ss->rx_big.shadow);
2051 kfree(ss->rx_small.shadow);
2053 kfree(ss->tx.req_bytes);
2054 ss->tx.req_bytes = NULL;
2055 ss->tx.req_list = NULL;
2058 static int myri10ge_request_irq(struct myri10ge_priv *mgp)
2060 struct pci_dev *pdev = mgp->pdev;
2061 struct myri10ge_slice_state *ss;
2062 struct net_device *netdev = mgp->dev;
2066 mgp->msi_enabled = 0;
2067 mgp->msix_enabled = 0;
2070 if (mgp->num_slices > 1) {
2072 pci_enable_msix(pdev, mgp->msix_vectors,
2075 mgp->msix_enabled = 1;
2078 "Error %d setting up MSI-X\n", status);
2082 if (mgp->msix_enabled == 0) {
2083 status = pci_enable_msi(pdev);
2086 "Error %d setting up MSI; falling back to xPIC\n",
2089 mgp->msi_enabled = 1;
2093 if (mgp->msix_enabled) {
2094 for (i = 0; i < mgp->num_slices; i++) {
2096 snprintf(ss->irq_desc, sizeof(ss->irq_desc),
2097 "%s:slice-%d", netdev->name, i);
2098 status = request_irq(mgp->msix_vectors[i].vector,
2099 myri10ge_intr, 0, ss->irq_desc,
2103 "slice %d failed to allocate IRQ\n", i);
2106 free_irq(mgp->msix_vectors[i].vector,
2110 pci_disable_msix(pdev);
2115 status = request_irq(pdev->irq, myri10ge_intr, IRQF_SHARED,
2116 mgp->dev->name, &mgp->ss[0]);
2118 dev_err(&pdev->dev, "failed to allocate IRQ\n");
2119 if (mgp->msi_enabled)
2120 pci_disable_msi(pdev);
2126 static void myri10ge_free_irq(struct myri10ge_priv *mgp)
2128 struct pci_dev *pdev = mgp->pdev;
2131 if (mgp->msix_enabled) {
2132 for (i = 0; i < mgp->num_slices; i++)
2133 free_irq(mgp->msix_vectors[i].vector, &mgp->ss[i]);
2135 free_irq(pdev->irq, &mgp->ss[0]);
2137 if (mgp->msi_enabled)
2138 pci_disable_msi(pdev);
2139 if (mgp->msix_enabled)
2140 pci_disable_msix(pdev);
2144 myri10ge_get_frag_header(struct skb_frag_struct *frag, void **mac_hdr,
2145 void **ip_hdr, void **tcpudp_hdr,
2146 u64 * hdr_flags, void *priv)
2149 struct vlan_ethhdr *veh;
2151 u8 *va = page_address(frag->page) + frag->page_offset;
2152 unsigned long ll_hlen;
2153 /* passed opaque through lro_receive_frags() */
2154 __wsum csum = (__force __wsum) (unsigned long)priv;
2156 /* find the mac header, aborting if not IPv4 */
2158 eh = (struct ethhdr *)va;
2161 if (eh->h_proto != htons(ETH_P_IP)) {
2162 if (eh->h_proto == htons(ETH_P_8021Q)) {
2163 veh = (struct vlan_ethhdr *)va;
2164 if (veh->h_vlan_encapsulated_proto != htons(ETH_P_IP))
2167 ll_hlen += VLAN_HLEN;
2170 * HW checksum starts ETH_HLEN bytes into
2171 * frame, so we must subtract off the VLAN
2172 * header's checksum before csum can be used
2174 csum = csum_sub(csum, csum_partial(va + ETH_HLEN,
2180 *hdr_flags = LRO_IPV4;
2182 iph = (struct iphdr *)(va + ll_hlen);
2184 if (iph->protocol != IPPROTO_TCP)
2186 *hdr_flags |= LRO_TCP;
2187 *tcpudp_hdr = (u8 *) (*ip_hdr) + (iph->ihl << 2);
2189 /* verify the IP checksum */
2190 if (unlikely(ip_fast_csum((u8 *) iph, iph->ihl)))
2193 /* verify the checksum */
2194 if (unlikely(csum_tcpudp_magic(iph->saddr, iph->daddr,
2195 ntohs(iph->tot_len) - (iph->ihl << 2),
2196 IPPROTO_TCP, csum)))
2202 static int myri10ge_get_txrx(struct myri10ge_priv *mgp, int slice)
2204 struct myri10ge_cmd cmd;
2205 struct myri10ge_slice_state *ss;
2208 ss = &mgp->ss[slice];
2209 cmd.data0 = 0; /* single slice for now */
2210 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_GET_SEND_OFFSET, &cmd, 0);
2211 ss->tx.lanai = (struct mcp_kreq_ether_send __iomem *)
2212 (mgp->sram + cmd.data0);
2215 status |= myri10ge_send_cmd(mgp, MXGEFW_CMD_GET_SMALL_RX_OFFSET,
2217 ss->rx_small.lanai = (struct mcp_kreq_ether_recv __iomem *)
2218 (mgp->sram + cmd.data0);
2221 status |= myri10ge_send_cmd(mgp, MXGEFW_CMD_GET_BIG_RX_OFFSET, &cmd, 0);
2222 ss->rx_big.lanai = (struct mcp_kreq_ether_recv __iomem *)
2223 (mgp->sram + cmd.data0);
2225 if (myri10ge_wcfifo && mgp->wc_enabled) {
2226 ss->tx.wc_fifo = (u8 __iomem *)
2227 mgp->sram + MXGEFW_ETH_SEND_4 + 64 * slice;
2228 ss->rx_small.wc_fifo = (u8 __iomem *)
2229 mgp->sram + MXGEFW_ETH_RECV_SMALL + 64 * slice;
2230 ss->rx_big.wc_fifo = (u8 __iomem *)
2231 mgp->sram + MXGEFW_ETH_RECV_BIG + 64 * slice;
2233 ss->tx.wc_fifo = NULL;
2234 ss->rx_small.wc_fifo = NULL;
2235 ss->rx_big.wc_fifo = NULL;
2241 static int myri10ge_set_stats(struct myri10ge_priv *mgp, int slice)
2243 struct myri10ge_cmd cmd;
2244 struct myri10ge_slice_state *ss;
2247 ss = &mgp->ss[slice];
2248 cmd.data0 = MYRI10GE_LOWPART_TO_U32(ss->fw_stats_bus);
2249 cmd.data1 = MYRI10GE_HIGHPART_TO_U32(ss->fw_stats_bus);
2250 cmd.data2 = sizeof(struct mcp_irq_data);
2251 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_SET_STATS_DMA_V2, &cmd, 0);
2252 if (status == -ENOSYS) {
2253 dma_addr_t bus = ss->fw_stats_bus;
2256 bus += offsetof(struct mcp_irq_data, send_done_count);
2257 cmd.data0 = MYRI10GE_LOWPART_TO_U32(bus);
2258 cmd.data1 = MYRI10GE_HIGHPART_TO_U32(bus);
2259 status = myri10ge_send_cmd(mgp,
2260 MXGEFW_CMD_SET_STATS_DMA_OBSOLETE,
2262 /* Firmware cannot support multicast without STATS_DMA_V2 */
2263 mgp->fw_multicast_support = 0;
2265 mgp->fw_multicast_support = 1;
2270 static int myri10ge_open(struct net_device *dev)
2272 struct myri10ge_slice_state *ss;
2273 struct myri10ge_priv *mgp = netdev_priv(dev);
2274 struct myri10ge_cmd cmd;
2275 int i, status, big_pow2, slice;
2277 struct net_lro_mgr *lro_mgr;
2279 if (mgp->running != MYRI10GE_ETH_STOPPED)
2282 mgp->running = MYRI10GE_ETH_STARTING;
2283 status = myri10ge_reset(mgp);
2285 printk(KERN_ERR "myri10ge: %s: failed reset\n", dev->name);
2286 goto abort_with_nothing;
2289 if (mgp->num_slices > 1) {
2290 cmd.data0 = mgp->num_slices;
2291 cmd.data1 = 1; /* use MSI-X */
2292 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_ENABLE_RSS_QUEUES,
2296 "myri10ge: %s: failed to set number of slices\n",
2298 goto abort_with_nothing;
2300 /* setup the indirection table */
2301 cmd.data0 = mgp->num_slices;
2302 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_SET_RSS_TABLE_SIZE,
2305 status |= myri10ge_send_cmd(mgp,
2306 MXGEFW_CMD_GET_RSS_TABLE_OFFSET,
2310 "myri10ge: %s: failed to setup rss tables\n",
2314 /* just enable an identity mapping */
2315 itable = mgp->sram + cmd.data0;
2316 for (i = 0; i < mgp->num_slices; i++)
2317 __raw_writeb(i, &itable[i]);
2320 cmd.data1 = myri10ge_rss_hash;
2321 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_SET_RSS_ENABLE,
2325 "myri10ge: %s: failed to enable slices\n",
2327 goto abort_with_nothing;
2331 status = myri10ge_request_irq(mgp);
2333 goto abort_with_nothing;
2335 /* decide what small buffer size to use. For good TCP rx
2336 * performance, it is important to not receive 1514 byte
2337 * frames into jumbo buffers, as it confuses the socket buffer
2338 * accounting code, leading to drops and erratic performance.
2341 if (dev->mtu <= ETH_DATA_LEN)
2342 /* enough for a TCP header */
2343 mgp->small_bytes = (128 > SMP_CACHE_BYTES)
2344 ? (128 - MXGEFW_PAD)
2345 : (SMP_CACHE_BYTES - MXGEFW_PAD);
2347 /* enough for a vlan encapsulated ETH_DATA_LEN frame */
2348 mgp->small_bytes = VLAN_ETH_FRAME_LEN;
2350 /* Override the small buffer size? */
2351 if (myri10ge_small_bytes > 0)
2352 mgp->small_bytes = myri10ge_small_bytes;
2354 /* Firmware needs the big buff size as a power of 2. Lie and
2355 * tell him the buffer is larger, because we only use 1
2356 * buffer/pkt, and the mtu will prevent overruns.
2358 big_pow2 = dev->mtu + ETH_HLEN + VLAN_HLEN + MXGEFW_PAD;
2359 if (big_pow2 < MYRI10GE_ALLOC_SIZE / 2) {
2360 while (!is_power_of_2(big_pow2))
2362 mgp->big_bytes = dev->mtu + ETH_HLEN + VLAN_HLEN + MXGEFW_PAD;
2364 big_pow2 = MYRI10GE_ALLOC_SIZE;
2365 mgp->big_bytes = big_pow2;
2368 /* setup the per-slice data structures */
2369 for (slice = 0; slice < mgp->num_slices; slice++) {
2370 ss = &mgp->ss[slice];
2372 status = myri10ge_get_txrx(mgp, slice);
2375 "myri10ge: %s: failed to get ring sizes or locations\n",
2377 goto abort_with_rings;
2379 status = myri10ge_allocate_rings(ss);
2381 goto abort_with_rings;
2383 status = myri10ge_set_stats(mgp, slice);
2386 "myri10ge: %s: Couldn't set stats DMA\n",
2388 goto abort_with_rings;
2391 lro_mgr = &ss->rx_done.lro_mgr;
2393 lro_mgr->features = LRO_F_NAPI;
2394 lro_mgr->ip_summed = CHECKSUM_COMPLETE;
2395 lro_mgr->ip_summed_aggr = CHECKSUM_UNNECESSARY;
2396 lro_mgr->max_desc = MYRI10GE_MAX_LRO_DESCRIPTORS;
2397 lro_mgr->lro_arr = ss->rx_done.lro_desc;
2398 lro_mgr->get_frag_header = myri10ge_get_frag_header;
2399 lro_mgr->max_aggr = myri10ge_lro_max_pkts;
2400 if (lro_mgr->max_aggr > MAX_SKB_FRAGS)
2401 lro_mgr->max_aggr = MAX_SKB_FRAGS;
2403 /* must happen prior to any irq */
2404 napi_enable(&(ss)->napi);
2407 /* now give firmware buffers sizes, and MTU */
2408 cmd.data0 = dev->mtu + ETH_HLEN + VLAN_HLEN;
2409 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_SET_MTU, &cmd, 0);
2410 cmd.data0 = mgp->small_bytes;
2412 myri10ge_send_cmd(mgp, MXGEFW_CMD_SET_SMALL_BUFFER_SIZE, &cmd, 0);
2413 cmd.data0 = big_pow2;
2415 myri10ge_send_cmd(mgp, MXGEFW_CMD_SET_BIG_BUFFER_SIZE, &cmd, 0);
2417 printk(KERN_ERR "myri10ge: %s: Couldn't set buffer sizes\n",
2419 goto abort_with_rings;
2423 * Set Linux style TSO mode; this is needed only on newer
2424 * firmware versions. Older versions default to Linux
2428 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_SET_TSO_MODE, &cmd, 0);
2429 if (status && status != -ENOSYS) {
2430 printk(KERN_ERR "myri10ge: %s: Couldn't set TSO mode\n",
2432 goto abort_with_rings;
2435 mgp->link_state = ~0U;
2436 mgp->rdma_tags_available = 15;
2438 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_ETHERNET_UP, &cmd, 0);
2440 printk(KERN_ERR "myri10ge: %s: Couldn't bring up link\n",
2442 goto abort_with_rings;
2445 mgp->running = MYRI10GE_ETH_RUNNING;
2446 mgp->watchdog_timer.expires = jiffies + myri10ge_watchdog_timeout * HZ;
2447 add_timer(&mgp->watchdog_timer);
2448 netif_wake_queue(dev);
2452 for (i = 0; i < mgp->num_slices; i++)
2453 myri10ge_free_rings(&mgp->ss[i]);
2455 myri10ge_free_irq(mgp);
2458 mgp->running = MYRI10GE_ETH_STOPPED;
2462 static int myri10ge_close(struct net_device *dev)
2464 struct myri10ge_priv *mgp = netdev_priv(dev);
2465 struct myri10ge_cmd cmd;
2466 int status, old_down_cnt;
2469 if (mgp->running != MYRI10GE_ETH_RUNNING)
2472 if (mgp->ss[0].tx.req_bytes == NULL)
2475 del_timer_sync(&mgp->watchdog_timer);
2476 mgp->running = MYRI10GE_ETH_STOPPING;
2477 for (i = 0; i < mgp->num_slices; i++) {
2478 napi_disable(&mgp->ss[i].napi);
2480 netif_carrier_off(dev);
2481 netif_stop_queue(dev);
2482 old_down_cnt = mgp->down_cnt;
2484 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_ETHERNET_DOWN, &cmd, 0);
2486 printk(KERN_ERR "myri10ge: %s: Couldn't bring down link\n",
2489 wait_event_timeout(mgp->down_wq, old_down_cnt != mgp->down_cnt, HZ);
2490 if (old_down_cnt == mgp->down_cnt)
2491 printk(KERN_ERR "myri10ge: %s never got down irq\n", dev->name);
2493 netif_tx_disable(dev);
2494 myri10ge_free_irq(mgp);
2495 for (i = 0; i < mgp->num_slices; i++)
2496 myri10ge_free_rings(&mgp->ss[i]);
2498 mgp->running = MYRI10GE_ETH_STOPPED;
2502 /* copy an array of struct mcp_kreq_ether_send's to the mcp. Copy
2503 * backwards one at a time and handle ring wraps */
2506 myri10ge_submit_req_backwards(struct myri10ge_tx_buf *tx,
2507 struct mcp_kreq_ether_send *src, int cnt)
2509 int idx, starting_slot;
2510 starting_slot = tx->req;
2513 idx = (starting_slot + cnt) & tx->mask;
2514 myri10ge_pio_copy(&tx->lanai[idx], &src[cnt], sizeof(*src));
2520 * copy an array of struct mcp_kreq_ether_send's to the mcp. Copy
2521 * at most 32 bytes at a time, so as to avoid involving the software
2522 * pio handler in the nic. We re-write the first segment's flags
2523 * to mark them valid only after writing the entire chain.
2527 myri10ge_submit_req(struct myri10ge_tx_buf *tx, struct mcp_kreq_ether_send *src,
2531 struct mcp_kreq_ether_send __iomem *dstp, *dst;
2532 struct mcp_kreq_ether_send *srcp;
2535 idx = tx->req & tx->mask;
2537 last_flags = src->flags;
2540 dst = dstp = &tx->lanai[idx];
2543 if ((idx + cnt) < tx->mask) {
2544 for (i = 0; i < (cnt - 1); i += 2) {
2545 myri10ge_pio_copy(dstp, srcp, 2 * sizeof(*src));
2546 mb(); /* force write every 32 bytes */
2551 /* submit all but the first request, and ensure
2552 * that it is submitted below */
2553 myri10ge_submit_req_backwards(tx, src, cnt);
2557 /* submit the first request */
2558 myri10ge_pio_copy(dstp, srcp, sizeof(*src));
2559 mb(); /* barrier before setting valid flag */
2562 /* re-write the last 32-bits with the valid flags */
2563 src->flags = last_flags;
2564 put_be32(*((__be32 *) src + 3), (__be32 __iomem *) dst + 3);
2570 myri10ge_submit_req_wc(struct myri10ge_tx_buf *tx,
2571 struct mcp_kreq_ether_send *src, int cnt)
2576 myri10ge_pio_copy(tx->wc_fifo, src, 64);
2582 /* pad it to 64 bytes. The src is 64 bytes bigger than it
2583 * needs to be so that we don't overrun it */
2584 myri10ge_pio_copy(tx->wc_fifo + MXGEFW_ETH_SEND_OFFSET(cnt),
2591 * Transmit a packet. We need to split the packet so that a single
2592 * segment does not cross myri10ge->tx_boundary, so this makes segment
2593 * counting tricky. So rather than try to count segments up front, we
2594 * just give up if there are too few segments to hold a reasonably
2595 * fragmented packet currently available. If we run
2596 * out of segments while preparing a packet for DMA, we just linearize
2600 static int myri10ge_xmit(struct sk_buff *skb, struct net_device *dev)
2602 struct myri10ge_priv *mgp = netdev_priv(dev);
2603 struct myri10ge_slice_state *ss;
2604 struct mcp_kreq_ether_send *req;
2605 struct myri10ge_tx_buf *tx;
2606 struct skb_frag_struct *frag;
2609 __be32 high_swapped;
2611 int idx, last_idx, avail, frag_cnt, frag_idx, count, mss, max_segments;
2612 u16 pseudo_hdr_offset, cksum_offset;
2613 int cum_len, seglen, boundary, rdma_count;
2616 /* always transmit through slot 0 */
2621 avail = tx->mask - 1 - (tx->req - tx->done);
2624 max_segments = MXGEFW_MAX_SEND_DESC;
2626 if (skb_is_gso(skb)) {
2627 mss = skb_shinfo(skb)->gso_size;
2628 max_segments = MYRI10GE_MAX_SEND_DESC_TSO;
2631 if ((unlikely(avail < max_segments))) {
2632 /* we are out of transmit resources */
2634 netif_stop_queue(dev);
2638 /* Setup checksum offloading, if needed */
2640 pseudo_hdr_offset = 0;
2642 flags = (MXGEFW_FLAGS_NO_TSO | MXGEFW_FLAGS_FIRST);
2643 if (likely(skb->ip_summed == CHECKSUM_PARTIAL)) {
2644 cksum_offset = skb_transport_offset(skb);
2645 pseudo_hdr_offset = cksum_offset + skb->csum_offset;
2646 /* If the headers are excessively large, then we must
2647 * fall back to a software checksum */
2648 if (unlikely(!mss && (cksum_offset > 255 ||
2649 pseudo_hdr_offset > 127))) {
2650 if (skb_checksum_help(skb))
2653 pseudo_hdr_offset = 0;
2655 odd_flag = MXGEFW_FLAGS_ALIGN_ODD;
2656 flags |= MXGEFW_FLAGS_CKSUM;
2662 if (mss) { /* TSO */
2663 /* this removes any CKSUM flag from before */
2664 flags = (MXGEFW_FLAGS_TSO_HDR | MXGEFW_FLAGS_FIRST);
2666 /* negative cum_len signifies to the
2667 * send loop that we are still in the
2668 * header portion of the TSO packet.
2669 * TSO header can be at most 1KB long */
2670 cum_len = -(skb_transport_offset(skb) + tcp_hdrlen(skb));
2672 /* for IPv6 TSO, the checksum offset stores the
2673 * TCP header length, to save the firmware from
2674 * the need to parse the headers */
2675 if (skb_is_gso_v6(skb)) {
2676 cksum_offset = tcp_hdrlen(skb);
2677 /* Can only handle headers <= max_tso6 long */
2678 if (unlikely(-cum_len > mgp->max_tso6))
2679 return myri10ge_sw_tso(skb, dev);
2681 /* for TSO, pseudo_hdr_offset holds mss.
2682 * The firmware figures out where to put
2683 * the checksum by parsing the header. */
2684 pseudo_hdr_offset = mss;
2686 /* Mark small packets, and pad out tiny packets */
2687 if (skb->len <= MXGEFW_SEND_SMALL_SIZE) {
2688 flags |= MXGEFW_FLAGS_SMALL;
2690 /* pad frames to at least ETH_ZLEN bytes */
2691 if (unlikely(skb->len < ETH_ZLEN)) {
2692 if (skb_padto(skb, ETH_ZLEN)) {
2693 /* The packet is gone, so we must
2695 ss->stats.tx_dropped += 1;
2698 /* adjust the len to account for the zero pad
2699 * so that the nic can know how long it is */
2700 skb->len = ETH_ZLEN;
2704 /* map the skb for DMA */
2705 len = skb->len - skb->data_len;
2706 idx = tx->req & tx->mask;
2707 tx->info[idx].skb = skb;
2708 bus = pci_map_single(mgp->pdev, skb->data, len, PCI_DMA_TODEVICE);
2709 pci_unmap_addr_set(&tx->info[idx], bus, bus);
2710 pci_unmap_len_set(&tx->info[idx], len, len);
2712 frag_cnt = skb_shinfo(skb)->nr_frags;
2717 /* "rdma_count" is the number of RDMAs belonging to the
2718 * current packet BEFORE the current send request. For
2719 * non-TSO packets, this is equal to "count".
2720 * For TSO packets, rdma_count needs to be reset
2721 * to 0 after a segment cut.
2723 * The rdma_count field of the send request is
2724 * the number of RDMAs of the packet starting at
2725 * that request. For TSO send requests with one ore more cuts
2726 * in the middle, this is the number of RDMAs starting
2727 * after the last cut in the request. All previous
2728 * segments before the last cut implicitly have 1 RDMA.
2730 * Since the number of RDMAs is not known beforehand,
2731 * it must be filled-in retroactively - after each
2732 * segmentation cut or at the end of the entire packet.
2736 /* Break the SKB or Fragment up into pieces which
2737 * do not cross mgp->tx_boundary */
2738 low = MYRI10GE_LOWPART_TO_U32(bus);
2739 high_swapped = htonl(MYRI10GE_HIGHPART_TO_U32(bus));
2744 if (unlikely(count == max_segments))
2745 goto abort_linearize;
2748 (low + mgp->tx_boundary) & ~(mgp->tx_boundary - 1);
2749 seglen = boundary - low;
2752 flags_next = flags & ~MXGEFW_FLAGS_FIRST;
2753 cum_len_next = cum_len + seglen;
2754 if (mss) { /* TSO */
2755 (req - rdma_count)->rdma_count = rdma_count + 1;
2757 if (likely(cum_len >= 0)) { /* payload */
2758 int next_is_first, chop;
2760 chop = (cum_len_next > mss);
2761 cum_len_next = cum_len_next % mss;
2762 next_is_first = (cum_len_next == 0);
2763 flags |= chop * MXGEFW_FLAGS_TSO_CHOP;
2764 flags_next |= next_is_first *
2766 rdma_count |= -(chop | next_is_first);
2767 rdma_count += chop & !next_is_first;
2768 } else if (likely(cum_len_next >= 0)) { /* header ends */
2774 small = (mss <= MXGEFW_SEND_SMALL_SIZE);
2775 flags_next = MXGEFW_FLAGS_TSO_PLD |
2776 MXGEFW_FLAGS_FIRST |
2777 (small * MXGEFW_FLAGS_SMALL);
2780 req->addr_high = high_swapped;
2781 req->addr_low = htonl(low);
2782 req->pseudo_hdr_offset = htons(pseudo_hdr_offset);
2783 req->pad = 0; /* complete solid 16-byte block; does this matter? */
2784 req->rdma_count = 1;
2785 req->length = htons(seglen);
2786 req->cksum_offset = cksum_offset;
2787 req->flags = flags | ((cum_len & 1) * odd_flag);
2791 cum_len = cum_len_next;
2796 if (cksum_offset != 0 && !(mss && skb_is_gso_v6(skb))) {
2797 if (unlikely(cksum_offset > seglen))
2798 cksum_offset -= seglen;
2803 if (frag_idx == frag_cnt)
2806 /* map next fragment for DMA */
2807 idx = (count + tx->req) & tx->mask;
2808 frag = &skb_shinfo(skb)->frags[frag_idx];
2811 bus = pci_map_page(mgp->pdev, frag->page, frag->page_offset,
2812 len, PCI_DMA_TODEVICE);
2813 pci_unmap_addr_set(&tx->info[idx], bus, bus);
2814 pci_unmap_len_set(&tx->info[idx], len, len);
2817 (req - rdma_count)->rdma_count = rdma_count;
2821 req->flags |= MXGEFW_FLAGS_TSO_LAST;
2822 } while (!(req->flags & (MXGEFW_FLAGS_TSO_CHOP |
2823 MXGEFW_FLAGS_FIRST)));
2824 idx = ((count - 1) + tx->req) & tx->mask;
2825 tx->info[idx].last = 1;
2826 if (tx->wc_fifo == NULL)
2827 myri10ge_submit_req(tx, tx->req_list, count);
2829 myri10ge_submit_req_wc(tx, tx->req_list, count);
2831 if ((avail - count) < MXGEFW_MAX_SEND_DESC) {
2833 netif_stop_queue(dev);
2835 dev->trans_start = jiffies;
2839 /* Free any DMA resources we've alloced and clear out the skb
2840 * slot so as to not trip up assertions, and to avoid a
2841 * double-free if linearizing fails */
2843 last_idx = (idx + 1) & tx->mask;
2844 idx = tx->req & tx->mask;
2845 tx->info[idx].skb = NULL;
2847 len = pci_unmap_len(&tx->info[idx], len);
2849 if (tx->info[idx].skb != NULL)
2850 pci_unmap_single(mgp->pdev,
2851 pci_unmap_addr(&tx->info[idx],
2855 pci_unmap_page(mgp->pdev,
2856 pci_unmap_addr(&tx->info[idx],
2859 pci_unmap_len_set(&tx->info[idx], len, 0);
2860 tx->info[idx].skb = NULL;
2862 idx = (idx + 1) & tx->mask;
2863 } while (idx != last_idx);
2864 if (skb_is_gso(skb)) {
2866 "myri10ge: %s: TSO but wanted to linearize?!?!?\n",
2871 if (skb_linearize(skb))
2878 dev_kfree_skb_any(skb);
2879 ss->stats.tx_dropped += 1;
2884 static int myri10ge_sw_tso(struct sk_buff *skb, struct net_device *dev)
2886 struct sk_buff *segs, *curr;
2887 struct myri10ge_priv *mgp = netdev_priv(dev);
2890 segs = skb_gso_segment(skb, dev->features & ~NETIF_F_TSO6);
2898 status = myri10ge_xmit(curr, dev);
2900 dev_kfree_skb_any(curr);
2905 dev_kfree_skb_any(segs);
2910 dev_kfree_skb_any(skb);
2914 dev_kfree_skb_any(skb);
2915 mgp->stats.tx_dropped += 1;
2919 static struct net_device_stats *myri10ge_get_stats(struct net_device *dev)
2921 struct myri10ge_priv *mgp = netdev_priv(dev);
2922 struct myri10ge_slice_netstats *slice_stats;
2923 struct net_device_stats *stats = &mgp->stats;
2926 memset(stats, 0, sizeof(*stats));
2927 for (i = 0; i < mgp->num_slices; i++) {
2928 slice_stats = &mgp->ss[i].stats;
2929 stats->rx_packets += slice_stats->rx_packets;
2930 stats->tx_packets += slice_stats->tx_packets;
2931 stats->rx_bytes += slice_stats->rx_bytes;
2932 stats->tx_bytes += slice_stats->tx_bytes;
2933 stats->rx_dropped += slice_stats->rx_dropped;
2934 stats->tx_dropped += slice_stats->tx_dropped;
2939 static void myri10ge_set_multicast_list(struct net_device *dev)
2941 struct myri10ge_priv *mgp = netdev_priv(dev);
2942 struct myri10ge_cmd cmd;
2943 struct dev_mc_list *mc_list;
2944 __be32 data[2] = { 0, 0 };
2946 DECLARE_MAC_BUF(mac);
2948 /* can be called from atomic contexts,
2949 * pass 1 to force atomicity in myri10ge_send_cmd() */
2950 myri10ge_change_promisc(mgp, dev->flags & IFF_PROMISC, 1);
2952 /* This firmware is known to not support multicast */
2953 if (!mgp->fw_multicast_support)
2956 /* Disable multicast filtering */
2958 err = myri10ge_send_cmd(mgp, MXGEFW_ENABLE_ALLMULTI, &cmd, 1);
2960 printk(KERN_ERR "myri10ge: %s: Failed MXGEFW_ENABLE_ALLMULTI,"
2961 " error status: %d\n", dev->name, err);
2965 if ((dev->flags & IFF_ALLMULTI) || mgp->adopted_rx_filter_bug) {
2966 /* request to disable multicast filtering, so quit here */
2970 /* Flush the filters */
2972 err = myri10ge_send_cmd(mgp, MXGEFW_LEAVE_ALL_MULTICAST_GROUPS,
2976 "myri10ge: %s: Failed MXGEFW_LEAVE_ALL_MULTICAST_GROUPS"
2977 ", error status: %d\n", dev->name, err);
2981 /* Walk the multicast list, and add each address */
2982 for (mc_list = dev->mc_list; mc_list != NULL; mc_list = mc_list->next) {
2983 memcpy(data, &mc_list->dmi_addr, 6);
2984 cmd.data0 = ntohl(data[0]);
2985 cmd.data1 = ntohl(data[1]);
2986 err = myri10ge_send_cmd(mgp, MXGEFW_JOIN_MULTICAST_GROUP,
2990 printk(KERN_ERR "myri10ge: %s: Failed "
2991 "MXGEFW_JOIN_MULTICAST_GROUP, error status:"
2992 "%d\t", dev->name, err);
2993 printk(KERN_ERR "MAC %s\n",
2994 print_mac(mac, mc_list->dmi_addr));
2998 /* Enable multicast filtering */
2999 err = myri10ge_send_cmd(mgp, MXGEFW_DISABLE_ALLMULTI, &cmd, 1);
3001 printk(KERN_ERR "myri10ge: %s: Failed MXGEFW_DISABLE_ALLMULTI,"
3002 "error status: %d\n", dev->name, err);
3012 static int myri10ge_set_mac_address(struct net_device *dev, void *addr)
3014 struct sockaddr *sa = addr;
3015 struct myri10ge_priv *mgp = netdev_priv(dev);
3018 if (!is_valid_ether_addr(sa->sa_data))
3019 return -EADDRNOTAVAIL;
3021 status = myri10ge_update_mac_address(mgp, sa->sa_data);
3024 "myri10ge: %s: changing mac address failed with %d\n",
3029 /* change the dev structure */
3030 memcpy(dev->dev_addr, sa->sa_data, 6);
3034 static int myri10ge_change_mtu(struct net_device *dev, int new_mtu)
3036 struct myri10ge_priv *mgp = netdev_priv(dev);
3039 if ((new_mtu < 68) || (ETH_HLEN + new_mtu > MYRI10GE_MAX_ETHER_MTU)) {
3040 printk(KERN_ERR "myri10ge: %s: new mtu (%d) is not valid\n",
3041 dev->name, new_mtu);
3044 printk(KERN_INFO "%s: changing mtu from %d to %d\n",
3045 dev->name, dev->mtu, new_mtu);
3047 /* if we change the mtu on an active device, we must
3048 * reset the device so the firmware sees the change */
3049 myri10ge_close(dev);
3059 * Enable ECRC to align PCI-E Completion packets on an 8-byte boundary.
3060 * Only do it if the bridge is a root port since we don't want to disturb
3061 * any other device, except if forced with myri10ge_ecrc_enable > 1.
3064 static void myri10ge_enable_ecrc(struct myri10ge_priv *mgp)
3066 struct pci_dev *bridge = mgp->pdev->bus->self;
3067 struct device *dev = &mgp->pdev->dev;
3074 if (!myri10ge_ecrc_enable || !bridge)
3077 /* check that the bridge is a root port */
3078 cap = pci_find_capability(bridge, PCI_CAP_ID_EXP);
3079 pci_read_config_word(bridge, cap + PCI_CAP_FLAGS, &val);
3080 ext_type = (val & PCI_EXP_FLAGS_TYPE) >> 4;
3081 if (ext_type != PCI_EXP_TYPE_ROOT_PORT) {
3082 if (myri10ge_ecrc_enable > 1) {
3083 struct pci_dev *prev_bridge, *old_bridge = bridge;
3085 /* Walk the hierarchy up to the root port
3086 * where ECRC has to be enabled */
3088 prev_bridge = bridge;
3089 bridge = bridge->bus->self;
3090 if (!bridge || prev_bridge == bridge) {
3092 "Failed to find root port"
3093 " to force ECRC\n");
3097 pci_find_capability(bridge, PCI_CAP_ID_EXP);
3098 pci_read_config_word(bridge,
3099 cap + PCI_CAP_FLAGS, &val);
3100 ext_type = (val & PCI_EXP_FLAGS_TYPE) >> 4;
3101 } while (ext_type != PCI_EXP_TYPE_ROOT_PORT);
3104 "Forcing ECRC on non-root port %s"
3105 " (enabling on root port %s)\n",
3106 pci_name(old_bridge), pci_name(bridge));
3109 "Not enabling ECRC on non-root port %s\n",
3115 cap = pci_find_ext_capability(bridge, PCI_EXT_CAP_ID_ERR);
3119 ret = pci_read_config_dword(bridge, cap + PCI_ERR_CAP, &err_cap);
3121 dev_err(dev, "failed reading ext-conf-space of %s\n",
3123 dev_err(dev, "\t pci=nommconf in use? "
3124 "or buggy/incomplete/absent ACPI MCFG attr?\n");
3127 if (!(err_cap & PCI_ERR_CAP_ECRC_GENC))
3130 err_cap |= PCI_ERR_CAP_ECRC_GENE;
3131 pci_write_config_dword(bridge, cap + PCI_ERR_CAP, err_cap);
3132 dev_info(dev, "Enabled ECRC on upstream bridge %s\n", pci_name(bridge));
3136 * The Lanai Z8E PCI-E interface achieves higher Read-DMA throughput
3137 * when the PCI-E Completion packets are aligned on an 8-byte
3138 * boundary. Some PCI-E chip sets always align Completion packets; on
3139 * the ones that do not, the alignment can be enforced by enabling
3140 * ECRC generation (if supported).
3142 * When PCI-E Completion packets are not aligned, it is actually more
3143 * efficient to limit Read-DMA transactions to 2KB, rather than 4KB.
3145 * If the driver can neither enable ECRC nor verify that it has
3146 * already been enabled, then it must use a firmware image which works
3147 * around unaligned completion packets (myri10ge_rss_ethp_z8e.dat), and it
3148 * should also ensure that it never gives the device a Read-DMA which is
3149 * larger than 2KB by setting the tx_boundary to 2KB. If ECRC is
3150 * enabled, then the driver should use the aligned (myri10ge_rss_eth_z8e.dat)
3151 * firmware image, and set tx_boundary to 4KB.
3154 static void myri10ge_firmware_probe(struct myri10ge_priv *mgp)
3156 struct pci_dev *pdev = mgp->pdev;
3157 struct device *dev = &pdev->dev;
3160 mgp->tx_boundary = 4096;
3162 * Verify the max read request size was set to 4KB
3163 * before trying the test with 4KB.
3165 status = pcie_get_readrq(pdev);
3167 dev_err(dev, "Couldn't read max read req size: %d\n", status);
3170 if (status != 4096) {
3171 dev_warn(dev, "Max Read Request size != 4096 (%d)\n", status);
3172 mgp->tx_boundary = 2048;
3175 * load the optimized firmware (which assumes aligned PCIe
3176 * completions) in order to see if it works on this host.
3178 mgp->fw_name = myri10ge_fw_aligned;
3179 status = myri10ge_load_firmware(mgp, 1);
3185 * Enable ECRC if possible
3187 myri10ge_enable_ecrc(mgp);
3190 * Run a DMA test which watches for unaligned completions and
3191 * aborts on the first one seen.
3194 status = myri10ge_dma_test(mgp, MXGEFW_CMD_UNALIGNED_TEST);
3196 return; /* keep the aligned firmware */
3198 if (status != -E2BIG)
3199 dev_warn(dev, "DMA test failed: %d\n", status);
3200 if (status == -ENOSYS)
3201 dev_warn(dev, "Falling back to ethp! "
3202 "Please install up to date fw\n");
3204 /* fall back to using the unaligned firmware */
3205 mgp->tx_boundary = 2048;
3206 mgp->fw_name = myri10ge_fw_unaligned;
3210 static void myri10ge_select_firmware(struct myri10ge_priv *mgp)
3212 if (myri10ge_force_firmware == 0) {
3213 int link_width, exp_cap;
3216 exp_cap = pci_find_capability(mgp->pdev, PCI_CAP_ID_EXP);
3217 pci_read_config_word(mgp->pdev, exp_cap + PCI_EXP_LNKSTA, &lnk);
3218 link_width = (lnk >> 4) & 0x3f;
3220 /* Check to see if Link is less than 8 or if the
3221 * upstream bridge is known to provide aligned
3223 if (link_width < 8) {
3224 dev_info(&mgp->pdev->dev, "PCIE x%d Link\n",
3226 mgp->tx_boundary = 4096;
3227 mgp->fw_name = myri10ge_fw_aligned;
3229 myri10ge_firmware_probe(mgp);
3232 if (myri10ge_force_firmware == 1) {
3233 dev_info(&mgp->pdev->dev,
3234 "Assuming aligned completions (forced)\n");
3235 mgp->tx_boundary = 4096;
3236 mgp->fw_name = myri10ge_fw_aligned;
3238 dev_info(&mgp->pdev->dev,
3239 "Assuming unaligned completions (forced)\n");
3240 mgp->tx_boundary = 2048;
3241 mgp->fw_name = myri10ge_fw_unaligned;
3244 if (myri10ge_fw_name != NULL) {
3245 dev_info(&mgp->pdev->dev, "overriding firmware to %s\n",
3247 mgp->fw_name = myri10ge_fw_name;
3252 static int myri10ge_suspend(struct pci_dev *pdev, pm_message_t state)
3254 struct myri10ge_priv *mgp;
3255 struct net_device *netdev;
3257 mgp = pci_get_drvdata(pdev);
3262 netif_device_detach(netdev);
3263 if (netif_running(netdev)) {
3264 printk(KERN_INFO "myri10ge: closing %s\n", netdev->name);
3266 myri10ge_close(netdev);
3269 myri10ge_dummy_rdma(mgp, 0);
3270 pci_save_state(pdev);
3271 pci_disable_device(pdev);
3273 return pci_set_power_state(pdev, pci_choose_state(pdev, state));
3276 static int myri10ge_resume(struct pci_dev *pdev)
3278 struct myri10ge_priv *mgp;
3279 struct net_device *netdev;
3283 mgp = pci_get_drvdata(pdev);
3287 pci_set_power_state(pdev, 0); /* zeros conf space as a side effect */
3288 msleep(5); /* give card time to respond */
3289 pci_read_config_word(mgp->pdev, PCI_VENDOR_ID, &vendor);
3290 if (vendor == 0xffff) {
3291 printk(KERN_ERR "myri10ge: %s: device disappeared!\n",
3296 status = pci_restore_state(pdev);
3300 status = pci_enable_device(pdev);
3302 dev_err(&pdev->dev, "failed to enable device\n");
3306 pci_set_master(pdev);
3308 myri10ge_reset(mgp);
3309 myri10ge_dummy_rdma(mgp, 1);
3311 /* Save configuration space to be restored if the
3312 * nic resets due to a parity error */
3313 pci_save_state(pdev);
3315 if (netif_running(netdev)) {
3317 status = myri10ge_open(netdev);
3320 goto abort_with_enabled;
3323 netif_device_attach(netdev);
3328 pci_disable_device(pdev);
3332 #endif /* CONFIG_PM */
3334 static u32 myri10ge_read_reboot(struct myri10ge_priv *mgp)
3336 struct pci_dev *pdev = mgp->pdev;
3337 int vs = mgp->vendor_specific_offset;
3340 /*enter read32 mode */
3341 pci_write_config_byte(pdev, vs + 0x10, 0x3);
3343 /*read REBOOT_STATUS (0xfffffff0) */
3344 pci_write_config_dword(pdev, vs + 0x18, 0xfffffff0);
3345 pci_read_config_dword(pdev, vs + 0x14, &reboot);
3350 * This watchdog is used to check whether the board has suffered
3351 * from a parity error and needs to be recovered.
3353 static void myri10ge_watchdog(struct work_struct *work)
3355 struct myri10ge_priv *mgp =
3356 container_of(work, struct myri10ge_priv, watchdog_work);
3357 struct myri10ge_tx_buf *tx;
3363 mgp->watchdog_resets++;
3364 pci_read_config_word(mgp->pdev, PCI_COMMAND, &cmd);
3365 if ((cmd & PCI_COMMAND_MASTER) == 0) {
3366 /* Bus master DMA disabled? Check to see
3367 * if the card rebooted due to a parity error
3368 * For now, just report it */
3369 reboot = myri10ge_read_reboot(mgp);
3371 "myri10ge: %s: NIC rebooted (0x%x),%s resetting\n",
3372 mgp->dev->name, reboot,
3373 myri10ge_reset_recover ? " " : " not");
3374 if (myri10ge_reset_recover == 0)
3377 myri10ge_reset_recover--;
3380 * A rebooted nic will come back with config space as
3381 * it was after power was applied to PCIe bus.
3382 * Attempt to restore config space which was saved
3383 * when the driver was loaded, or the last time the
3384 * nic was resumed from power saving mode.
3386 pci_restore_state(mgp->pdev);
3388 /* save state again for accounting reasons */
3389 pci_save_state(mgp->pdev);
3392 /* if we get back -1's from our slot, perhaps somebody
3393 * powered off our card. Don't try to reset it in
3395 if (cmd == 0xffff) {
3396 pci_read_config_word(mgp->pdev, PCI_VENDOR_ID, &vendor);
3397 if (vendor == 0xffff) {
3399 "myri10ge: %s: device disappeared!\n",
3404 /* Perhaps it is a software error. Try to reset */
3406 printk(KERN_ERR "myri10ge: %s: device timeout, resetting\n",
3408 for (i = 0; i < mgp->num_slices; i++) {
3409 tx = &mgp->ss[i].tx;
3411 "myri10ge: %s: (%d): %d %d %d %d %d\n",
3412 mgp->dev->name, i, tx->req, tx->done,
3413 tx->pkt_start, tx->pkt_done,
3414 (int)ntohl(mgp->ss[i].fw_stats->
3418 "myri10ge: %s: (%d): %d %d %d %d %d\n",
3419 mgp->dev->name, i, tx->req, tx->done,
3420 tx->pkt_start, tx->pkt_done,
3421 (int)ntohl(mgp->ss[i].fw_stats->
3426 myri10ge_close(mgp->dev);
3427 status = myri10ge_load_firmware(mgp, 1);
3429 printk(KERN_ERR "myri10ge: %s: failed to load firmware\n",
3432 myri10ge_open(mgp->dev);
3437 * We use our own timer routine rather than relying upon
3438 * netdev->tx_timeout because we have a very large hardware transmit
3439 * queue. Due to the large queue, the netdev->tx_timeout function
3440 * cannot detect a NIC with a parity error in a timely fashion if the
3441 * NIC is lightly loaded.
3443 static void myri10ge_watchdog_timer(unsigned long arg)
3445 struct myri10ge_priv *mgp;
3446 struct myri10ge_slice_state *ss;
3447 int i, reset_needed;
3450 mgp = (struct myri10ge_priv *)arg;
3452 rx_pause_cnt = ntohl(mgp->ss[0].fw_stats->dropped_pause);
3453 for (i = 0, reset_needed = 0;
3454 i < mgp->num_slices && reset_needed == 0; ++i) {
3457 if (ss->rx_small.watchdog_needed) {
3458 myri10ge_alloc_rx_pages(mgp, &ss->rx_small,
3459 mgp->small_bytes + MXGEFW_PAD,
3461 if (ss->rx_small.fill_cnt - ss->rx_small.cnt >=
3462 myri10ge_fill_thresh)
3463 ss->rx_small.watchdog_needed = 0;
3465 if (ss->rx_big.watchdog_needed) {
3466 myri10ge_alloc_rx_pages(mgp, &ss->rx_big,
3468 if (ss->rx_big.fill_cnt - ss->rx_big.cnt >=
3469 myri10ge_fill_thresh)
3470 ss->rx_big.watchdog_needed = 0;
3473 if (ss->tx.req != ss->tx.done &&
3474 ss->tx.done == ss->watchdog_tx_done &&
3475 ss->watchdog_tx_req != ss->watchdog_tx_done) {
3476 /* nic seems like it might be stuck.. */
3477 if (rx_pause_cnt != mgp->watchdog_pause) {
3478 if (net_ratelimit())
3479 printk(KERN_WARNING "myri10ge %s:"
3480 "TX paused, check link partner\n",
3486 ss->watchdog_tx_done = ss->tx.done;
3487 ss->watchdog_tx_req = ss->tx.req;
3489 mgp->watchdog_pause = rx_pause_cnt;
3492 schedule_work(&mgp->watchdog_work);
3495 mod_timer(&mgp->watchdog_timer,
3496 jiffies + myri10ge_watchdog_timeout * HZ);
3500 static void myri10ge_free_slices(struct myri10ge_priv *mgp)
3502 struct myri10ge_slice_state *ss;
3503 struct pci_dev *pdev = mgp->pdev;
3507 if (mgp->ss == NULL)
3510 for (i = 0; i < mgp->num_slices; i++) {
3512 if (ss->rx_done.entry != NULL) {
3513 bytes = mgp->max_intr_slots *
3514 sizeof(*ss->rx_done.entry);
3515 dma_free_coherent(&pdev->dev, bytes,
3516 ss->rx_done.entry, ss->rx_done.bus);
3517 ss->rx_done.entry = NULL;
3519 if (ss->fw_stats != NULL) {
3520 bytes = sizeof(*ss->fw_stats);
3521 dma_free_coherent(&pdev->dev, bytes,
3522 ss->fw_stats, ss->fw_stats_bus);
3523 ss->fw_stats = NULL;
3530 static int myri10ge_alloc_slices(struct myri10ge_priv *mgp)
3532 struct myri10ge_slice_state *ss;
3533 struct pci_dev *pdev = mgp->pdev;
3537 bytes = sizeof(*mgp->ss) * mgp->num_slices;
3538 mgp->ss = kzalloc(bytes, GFP_KERNEL);
3539 if (mgp->ss == NULL) {
3543 for (i = 0; i < mgp->num_slices; i++) {
3545 bytes = mgp->max_intr_slots * sizeof(*ss->rx_done.entry);
3546 ss->rx_done.entry = dma_alloc_coherent(&pdev->dev, bytes,
3549 if (ss->rx_done.entry == NULL)
3551 memset(ss->rx_done.entry, 0, bytes);
3552 bytes = sizeof(*ss->fw_stats);
3553 ss->fw_stats = dma_alloc_coherent(&pdev->dev, bytes,
3556 if (ss->fw_stats == NULL)
3560 netif_napi_add(ss->dev, &ss->napi, myri10ge_poll,
3561 myri10ge_napi_weight);
3565 myri10ge_free_slices(mgp);
3570 * This function determines the number of slices supported.
3571 * The number slices is the minumum of the number of CPUS,
3572 * the number of MSI-X irqs supported, the number of slices
3573 * supported by the firmware
3575 static void myri10ge_probe_slices(struct myri10ge_priv *mgp)
3577 struct myri10ge_cmd cmd;
3578 struct pci_dev *pdev = mgp->pdev;
3580 int i, status, ncpus, msix_cap;
3582 mgp->num_slices = 1;
3583 msix_cap = pci_find_capability(pdev, PCI_CAP_ID_MSIX);
3584 ncpus = num_online_cpus();
3586 if (myri10ge_max_slices == 1 || msix_cap == 0 ||
3587 (myri10ge_max_slices == -1 && ncpus < 2))
3590 /* try to load the slice aware rss firmware */
3591 old_fw = mgp->fw_name;
3592 if (old_fw == myri10ge_fw_aligned)
3593 mgp->fw_name = myri10ge_fw_rss_aligned;
3595 mgp->fw_name = myri10ge_fw_rss_unaligned;
3596 status = myri10ge_load_firmware(mgp, 0);
3598 dev_info(&pdev->dev, "Rss firmware not found\n");
3602 /* hit the board with a reset to ensure it is alive */
3603 memset(&cmd, 0, sizeof(cmd));
3604 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_RESET, &cmd, 0);
3606 dev_err(&mgp->pdev->dev, "failed reset\n");
3611 mgp->max_intr_slots = cmd.data0 / sizeof(struct mcp_slot);
3613 /* tell it the size of the interrupt queues */
3614 cmd.data0 = mgp->max_intr_slots * sizeof(struct mcp_slot);
3615 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_SET_INTRQ_SIZE, &cmd, 0);
3617 dev_err(&mgp->pdev->dev, "failed MXGEFW_CMD_SET_INTRQ_SIZE\n");
3621 /* ask the maximum number of slices it supports */
3622 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_GET_MAX_RSS_QUEUES, &cmd, 0);
3626 mgp->num_slices = cmd.data0;
3628 /* Only allow multiple slices if MSI-X is usable */
3629 if (!myri10ge_msi) {
3633 /* if the admin did not specify a limit to how many
3634 * slices we should use, cap it automatically to the
3635 * number of CPUs currently online */
3636 if (myri10ge_max_slices == -1)
3637 myri10ge_max_slices = ncpus;
3639 if (mgp->num_slices > myri10ge_max_slices)
3640 mgp->num_slices = myri10ge_max_slices;
3642 /* Now try to allocate as many MSI-X vectors as we have
3643 * slices. We give up on MSI-X if we can only get a single
3646 mgp->msix_vectors = kzalloc(mgp->num_slices *
3647 sizeof(*mgp->msix_vectors), GFP_KERNEL);
3648 if (mgp->msix_vectors == NULL)
3650 for (i = 0; i < mgp->num_slices; i++) {
3651 mgp->msix_vectors[i].entry = i;
3654 while (mgp->num_slices > 1) {
3655 /* make sure it is a power of two */
3656 while (!is_power_of_2(mgp->num_slices))
3658 if (mgp->num_slices == 1)
3660 status = pci_enable_msix(pdev, mgp->msix_vectors,
3663 pci_disable_msix(pdev);
3667 mgp->num_slices = status;
3673 if (mgp->msix_vectors != NULL) {
3674 kfree(mgp->msix_vectors);
3675 mgp->msix_vectors = NULL;
3679 mgp->num_slices = 1;
3680 mgp->fw_name = old_fw;
3681 myri10ge_load_firmware(mgp, 0);
3684 static int myri10ge_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
3686 struct net_device *netdev;
3687 struct myri10ge_priv *mgp;
3688 struct device *dev = &pdev->dev;
3690 int status = -ENXIO;
3693 netdev = alloc_etherdev(sizeof(*mgp));
3694 if (netdev == NULL) {
3695 dev_err(dev, "Could not allocate ethernet device\n");
3699 SET_NETDEV_DEV(netdev, &pdev->dev);
3701 mgp = netdev_priv(netdev);
3704 mgp->csum_flag = MXGEFW_FLAGS_CKSUM;
3705 mgp->pause = myri10ge_flow_control;
3706 mgp->intr_coal_delay = myri10ge_intr_coal_delay;
3707 mgp->msg_enable = netif_msg_init(myri10ge_debug, MYRI10GE_MSG_DEFAULT);
3708 init_waitqueue_head(&mgp->down_wq);
3710 if (pci_enable_device(pdev)) {
3711 dev_err(&pdev->dev, "pci_enable_device call failed\n");
3713 goto abort_with_netdev;
3716 /* Find the vendor-specific cap so we can check
3717 * the reboot register later on */
3718 mgp->vendor_specific_offset
3719 = pci_find_capability(pdev, PCI_CAP_ID_VNDR);
3721 /* Set our max read request to 4KB */
3722 status = pcie_set_readrq(pdev, 4096);
3724 dev_err(&pdev->dev, "Error %d writing PCI_EXP_DEVCTL\n",
3726 goto abort_with_netdev;
3729 pci_set_master(pdev);
3731 status = pci_set_dma_mask(pdev, DMA_64BIT_MASK);
3735 "64-bit pci address mask was refused, "
3737 status = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
3740 dev_err(&pdev->dev, "Error %d setting DMA mask\n", status);
3741 goto abort_with_netdev;
3743 mgp->cmd = dma_alloc_coherent(&pdev->dev, sizeof(*mgp->cmd),
3744 &mgp->cmd_bus, GFP_KERNEL);
3745 if (mgp->cmd == NULL)
3746 goto abort_with_netdev;
3748 mgp->board_span = pci_resource_len(pdev, 0);
3749 mgp->iomem_base = pci_resource_start(pdev, 0);
3751 mgp->wc_enabled = 0;
3753 mgp->mtrr = mtrr_add(mgp->iomem_base, mgp->board_span,
3754 MTRR_TYPE_WRCOMB, 1);
3756 mgp->wc_enabled = 1;
3758 /* Hack. need to get rid of these magic numbers */
3760 2 * 1024 * 1024 - (2 * (48 * 1024) + (32 * 1024)) - 0x100;
3761 if (mgp->sram_size > mgp->board_span) {
3762 dev_err(&pdev->dev, "board span %ld bytes too small\n",
3766 mgp->sram = ioremap(mgp->iomem_base, mgp->board_span);
3767 if (mgp->sram == NULL) {
3768 dev_err(&pdev->dev, "ioremap failed for %ld bytes at 0x%lx\n",
3769 mgp->board_span, mgp->iomem_base);
3773 memcpy_fromio(mgp->eeprom_strings,
3774 mgp->sram + mgp->sram_size - MYRI10GE_EEPROM_STRINGS_SIZE,
3775 MYRI10GE_EEPROM_STRINGS_SIZE);
3776 memset(mgp->eeprom_strings + MYRI10GE_EEPROM_STRINGS_SIZE - 2, 0, 2);
3777 status = myri10ge_read_mac_addr(mgp);
3779 goto abort_with_ioremap;
3781 for (i = 0; i < ETH_ALEN; i++)
3782 netdev->dev_addr[i] = mgp->mac_addr[i];
3784 myri10ge_select_firmware(mgp);
3786 status = myri10ge_load_firmware(mgp, 1);
3788 dev_err(&pdev->dev, "failed to load firmware\n");
3789 goto abort_with_ioremap;
3791 myri10ge_probe_slices(mgp);
3792 status = myri10ge_alloc_slices(mgp);
3794 dev_err(&pdev->dev, "failed to alloc slice state\n");
3795 goto abort_with_firmware;
3798 status = myri10ge_reset(mgp);
3800 dev_err(&pdev->dev, "failed reset\n");
3801 goto abort_with_slices;
3804 myri10ge_setup_dca(mgp);
3806 pci_set_drvdata(pdev, mgp);
3807 if ((myri10ge_initial_mtu + ETH_HLEN) > MYRI10GE_MAX_ETHER_MTU)
3808 myri10ge_initial_mtu = MYRI10GE_MAX_ETHER_MTU - ETH_HLEN;
3809 if ((myri10ge_initial_mtu + ETH_HLEN) < 68)
3810 myri10ge_initial_mtu = 68;
3811 netdev->mtu = myri10ge_initial_mtu;
3812 netdev->open = myri10ge_open;
3813 netdev->stop = myri10ge_close;
3814 netdev->hard_start_xmit = myri10ge_xmit;
3815 netdev->get_stats = myri10ge_get_stats;
3816 netdev->base_addr = mgp->iomem_base;
3817 netdev->change_mtu = myri10ge_change_mtu;
3818 netdev->set_multicast_list = myri10ge_set_multicast_list;
3819 netdev->set_mac_address = myri10ge_set_mac_address;
3820 netdev->features = mgp->features;
3822 netdev->features |= NETIF_F_HIGHDMA;
3824 /* make sure we can get an irq, and that MSI can be
3825 * setup (if available). Also ensure netdev->irq
3826 * is set to correct value if MSI is enabled */
3827 status = myri10ge_request_irq(mgp);
3829 goto abort_with_firmware;
3830 netdev->irq = pdev->irq;
3831 myri10ge_free_irq(mgp);
3833 /* Save configuration space to be restored if the
3834 * nic resets due to a parity error */
3835 pci_save_state(pdev);
3837 /* Setup the watchdog timer */
3838 setup_timer(&mgp->watchdog_timer, myri10ge_watchdog_timer,
3839 (unsigned long)mgp);
3841 SET_ETHTOOL_OPS(netdev, &myri10ge_ethtool_ops);
3842 INIT_WORK(&mgp->watchdog_work, myri10ge_watchdog);
3843 status = register_netdev(netdev);
3845 dev_err(&pdev->dev, "register_netdev failed: %d\n", status);
3846 goto abort_with_state;
3848 if (mgp->msix_enabled)
3849 dev_info(dev, "%d MSI-X IRQs, tx bndry %d, fw %s, WC %s\n",
3850 mgp->num_slices, mgp->tx_boundary, mgp->fw_name,
3851 (mgp->wc_enabled ? "Enabled" : "Disabled"));
3853 dev_info(dev, "%s IRQ %d, tx bndry %d, fw %s, WC %s\n",
3854 mgp->msi_enabled ? "MSI" : "xPIC",
3855 netdev->irq, mgp->tx_boundary, mgp->fw_name,
3856 (mgp->wc_enabled ? "Enabled" : "Disabled"));
3861 pci_restore_state(pdev);
3864 myri10ge_free_slices(mgp);
3866 abort_with_firmware:
3867 myri10ge_dummy_rdma(mgp, 0);
3875 mtrr_del(mgp->mtrr, mgp->iomem_base, mgp->board_span);
3877 dma_free_coherent(&pdev->dev, sizeof(*mgp->cmd),
3878 mgp->cmd, mgp->cmd_bus);
3882 free_netdev(netdev);
3889 * Does what is necessary to shutdown one Myrinet device. Called
3890 * once for each Myrinet card by the kernel when a module is
3893 static void myri10ge_remove(struct pci_dev *pdev)
3895 struct myri10ge_priv *mgp;
3896 struct net_device *netdev;
3898 mgp = pci_get_drvdata(pdev);
3902 flush_scheduled_work();
3904 unregister_netdev(netdev);
3907 myri10ge_teardown_dca(mgp);
3909 myri10ge_dummy_rdma(mgp, 0);
3911 /* avoid a memory leak */
3912 pci_restore_state(pdev);
3918 mtrr_del(mgp->mtrr, mgp->iomem_base, mgp->board_span);
3920 myri10ge_free_slices(mgp);
3921 if (mgp->msix_vectors != NULL)
3922 kfree(mgp->msix_vectors);
3923 dma_free_coherent(&pdev->dev, sizeof(*mgp->cmd),
3924 mgp->cmd, mgp->cmd_bus);
3926 free_netdev(netdev);
3927 pci_set_drvdata(pdev, NULL);
3930 #define PCI_DEVICE_ID_MYRICOM_MYRI10GE_Z8E 0x0008
3931 #define PCI_DEVICE_ID_MYRICOM_MYRI10GE_Z8E_9 0x0009
3933 static struct pci_device_id myri10ge_pci_tbl[] = {
3934 {PCI_DEVICE(PCI_VENDOR_ID_MYRICOM, PCI_DEVICE_ID_MYRICOM_MYRI10GE_Z8E)},
3936 (PCI_VENDOR_ID_MYRICOM, PCI_DEVICE_ID_MYRICOM_MYRI10GE_Z8E_9)},
3940 static struct pci_driver myri10ge_driver = {
3942 .probe = myri10ge_probe,
3943 .remove = myri10ge_remove,
3944 .id_table = myri10ge_pci_tbl,
3946 .suspend = myri10ge_suspend,
3947 .resume = myri10ge_resume,
3953 myri10ge_notify_dca(struct notifier_block *nb, unsigned long event, void *p)
3955 int err = driver_for_each_device(&myri10ge_driver.driver,
3957 myri10ge_notify_dca_device);
3964 static struct notifier_block myri10ge_dca_notifier = {
3965 .notifier_call = myri10ge_notify_dca,
3969 #endif /* CONFIG_DCA */
3971 static __init int myri10ge_init_module(void)
3973 printk(KERN_INFO "%s: Version %s\n", myri10ge_driver.name,
3974 MYRI10GE_VERSION_STR);
3976 if (myri10ge_rss_hash > MXGEFW_RSS_HASH_TYPE_SRC_PORT ||
3977 myri10ge_rss_hash < MXGEFW_RSS_HASH_TYPE_IPV4) {
3979 "%s: Illegal rssh hash type %d, defaulting to source port\n",
3980 myri10ge_driver.name, myri10ge_rss_hash);
3981 myri10ge_rss_hash = MXGEFW_RSS_HASH_TYPE_SRC_PORT;
3984 dca_register_notify(&myri10ge_dca_notifier);
3987 return pci_register_driver(&myri10ge_driver);
3990 module_init(myri10ge_init_module);
3992 static __exit void myri10ge_cleanup_module(void)
3995 dca_unregister_notify(&myri10ge_dca_notifier);
3997 pci_unregister_driver(&myri10ge_driver);
4000 module_exit(myri10ge_cleanup_module);