2 * Driver for Marvell Discovery (MV643XX) and Marvell Orion ethernet ports
3 * Copyright (C) 2002 Matthew Dharm <mdharm@momenco.com>
5 * Based on the 64360 driver from:
6 * Copyright (C) 2002 Rabeeh Khoury <rabeeh@galileo.co.il>
7 * Rabeeh Khoury <rabeeh@marvell.com>
9 * Copyright (C) 2003 PMC-Sierra, Inc.,
10 * written by Manish Lachwani
12 * Copyright (C) 2003 Ralf Baechle <ralf@linux-mips.org>
14 * Copyright (C) 2004-2006 MontaVista Software, Inc.
15 * Dale Farnsworth <dale@farnsworth.org>
17 * Copyright (C) 2004 Steven J. Hill <sjhill1@rockwellcollins.com>
18 * <sjhill@realitydiluted.com>
20 * Copyright (C) 2007-2008 Marvell Semiconductor
21 * Lennert Buytenhek <buytenh@marvell.com>
23 * This program is free software; you can redistribute it and/or
24 * modify it under the terms of the GNU General Public License
25 * as published by the Free Software Foundation; either version 2
26 * of the License, or (at your option) any later version.
28 * This program is distributed in the hope that it will be useful,
29 * but WITHOUT ANY WARRANTY; without even the implied warranty of
30 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
31 * GNU General Public License for more details.
33 * You should have received a copy of the GNU General Public License
34 * along with this program; if not, write to the Free Software
35 * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
38 #include <linux/init.h>
39 #include <linux/dma-mapping.h>
41 #include <linux/tcp.h>
42 #include <linux/udp.h>
43 #include <linux/etherdevice.h>
44 #include <linux/delay.h>
45 #include <linux/ethtool.h>
46 #include <linux/platform_device.h>
47 #include <linux/module.h>
48 #include <linux/kernel.h>
49 #include <linux/spinlock.h>
50 #include <linux/workqueue.h>
51 #include <linux/mii.h>
52 #include <linux/mv643xx_eth.h>
54 #include <asm/types.h>
55 #include <asm/system.h>
57 static char mv643xx_driver_name[] = "mv643xx_eth";
58 static char mv643xx_driver_version[] = "1.0";
60 #define MV643XX_CHECKSUM_OFFLOAD_TX
62 #define MV643XX_TX_FAST_REFILL
65 #define MV643XX_TX_COAL 100
67 #define MV643XX_RX_COAL 100
70 #ifdef MV643XX_CHECKSUM_OFFLOAD_TX
71 #define MAX_DESCS_PER_SKB (MAX_SKB_FRAGS + 1)
73 #define MAX_DESCS_PER_SKB 1
76 #define ETH_VLAN_HLEN 4
78 #define ETH_HW_IP_ALIGN 2 /* hw aligns IP header */
79 #define ETH_WRAPPER_LEN (ETH_HW_IP_ALIGN + ETH_HLEN + \
80 ETH_VLAN_HLEN + ETH_FCS_LEN)
81 #define ETH_RX_SKB_SIZE (dev->mtu + ETH_WRAPPER_LEN + \
82 dma_get_cache_alignment())
85 * Registers shared between all ports.
87 #define PHY_ADDR 0x0000
88 #define SMI_REG 0x0004
89 #define WINDOW_BASE(w) (0x0200 + ((w) << 3))
90 #define WINDOW_SIZE(w) (0x0204 + ((w) << 3))
91 #define WINDOW_REMAP_HIGH(w) (0x0280 + ((w) << 2))
92 #define WINDOW_BAR_ENABLE 0x0290
93 #define WINDOW_PROTECT(w) (0x0294 + ((w) << 4))
98 #define PORT_CONFIG(p) (0x0400 + ((p) << 10))
99 #define UNICAST_PROMISCUOUS_MODE 0x00000001
100 #define PORT_CONFIG_EXT(p) (0x0404 + ((p) << 10))
101 #define MAC_ADDR_LOW(p) (0x0414 + ((p) << 10))
102 #define MAC_ADDR_HIGH(p) (0x0418 + ((p) << 10))
103 #define SDMA_CONFIG(p) (0x041c + ((p) << 10))
104 #define PORT_SERIAL_CONTROL(p) (0x043c + ((p) << 10))
105 #define PORT_STATUS(p) (0x0444 + ((p) << 10))
106 #define TXQ_COMMAND(p) (0x0448 + ((p) << 10))
107 #define TX_BW_MTU(p) (0x0458 + ((p) << 10))
108 #define INT_CAUSE(p) (0x0460 + ((p) << 10))
109 #define INT_CAUSE_EXT(p) (0x0464 + ((p) << 10))
110 #define INT_MASK(p) (0x0468 + ((p) << 10))
111 #define INT_MASK_EXT(p) (0x046c + ((p) << 10))
112 #define TX_FIFO_URGENT_THRESHOLD(p) (0x0474 + ((p) << 10))
113 #define RXQ_CURRENT_DESC_PTR(p) (0x060c + ((p) << 10))
114 #define RXQ_COMMAND(p) (0x0680 + ((p) << 10))
115 #define TXQ_CURRENT_DESC_PTR(p) (0x06c0 + ((p) << 10))
116 #define MIB_COUNTERS(p) (0x1000 + ((p) << 7))
117 #define SPECIAL_MCAST_TABLE(p) (0x1400 + ((p) << 10))
118 #define OTHER_MCAST_TABLE(p) (0x1500 + ((p) << 10))
119 #define UNICAST_TABLE(p) (0x1600 + ((p) << 10))
123 * SDMA configuration register.
125 #define RX_BURST_SIZE_4_64BIT (2 << 1)
126 #define BLM_RX_NO_SWAP (1 << 4)
127 #define BLM_TX_NO_SWAP (1 << 5)
128 #define TX_BURST_SIZE_4_64BIT (2 << 22)
130 #if defined(__BIG_ENDIAN)
131 #define PORT_SDMA_CONFIG_DEFAULT_VALUE \
132 RX_BURST_SIZE_4_64BIT | \
133 TX_BURST_SIZE_4_64BIT
134 #elif defined(__LITTLE_ENDIAN)
135 #define PORT_SDMA_CONFIG_DEFAULT_VALUE \
136 RX_BURST_SIZE_4_64BIT | \
139 TX_BURST_SIZE_4_64BIT
141 #error One of __BIG_ENDIAN or __LITTLE_ENDIAN must be defined
146 * Port serial control register.
148 #define SET_MII_SPEED_TO_100 (1 << 24)
149 #define SET_GMII_SPEED_TO_1000 (1 << 23)
150 #define SET_FULL_DUPLEX_MODE (1 << 21)
151 #define MAX_RX_PACKET_1522BYTE (1 << 17)
152 #define MAX_RX_PACKET_9700BYTE (5 << 17)
153 #define MAX_RX_PACKET_MASK (7 << 17)
154 #define DISABLE_AUTO_NEG_SPEED_GMII (1 << 13)
155 #define DO_NOT_FORCE_LINK_FAIL (1 << 10)
156 #define SERIAL_PORT_CONTROL_RESERVED (1 << 9)
157 #define DISABLE_AUTO_NEG_FOR_FLOW_CTRL (1 << 3)
158 #define DISABLE_AUTO_NEG_FOR_DUPLEX (1 << 2)
159 #define FORCE_LINK_PASS (1 << 1)
160 #define SERIAL_PORT_ENABLE (1 << 0)
162 #define PORT_DEFAULT_TRANSMIT_QUEUE_SIZE 800
163 #define PORT_DEFAULT_RECEIVE_QUEUE_SIZE 400
165 #define ETH_RX_QUEUES_ENABLED (1 << 0) /* use only Q0 for receive */
166 #define ETH_TX_QUEUES_ENABLED (1 << 0) /* use only Q0 for transmit */
168 #define ETH_INT_CAUSE_RX_DONE (ETH_RX_QUEUES_ENABLED << 2)
169 #define ETH_INT_CAUSE_RX_ERROR (ETH_RX_QUEUES_ENABLED << 9)
170 #define ETH_INT_CAUSE_RX (ETH_INT_CAUSE_RX_DONE | ETH_INT_CAUSE_RX_ERROR)
171 #define ETH_INT_CAUSE_EXT 0x00000002
172 #define ETH_INT_UNMASK_ALL (ETH_INT_CAUSE_RX | ETH_INT_CAUSE_EXT)
174 #define ETH_INT_CAUSE_TX_DONE (ETH_TX_QUEUES_ENABLED << 0)
175 #define ETH_INT_CAUSE_TX_ERROR (ETH_TX_QUEUES_ENABLED << 8)
176 #define ETH_INT_CAUSE_TX (ETH_INT_CAUSE_TX_DONE | ETH_INT_CAUSE_TX_ERROR)
177 #define ETH_INT_CAUSE_PHY 0x00010000
178 #define ETH_INT_CAUSE_STATE 0x00100000
179 #define ETH_INT_UNMASK_ALL_EXT (ETH_INT_CAUSE_TX | ETH_INT_CAUSE_PHY | \
182 #define ETH_INT_MASK_ALL 0x00000000
183 #define ETH_INT_MASK_ALL_EXT 0x00000000
185 #define PHY_WAIT_ITERATIONS 1000 /* 1000 iterations * 10uS = 10mS max */
186 #define PHY_WAIT_MICRO_SECONDS 10
188 /* Buffer offset from buffer pointer */
189 #define RX_BUF_OFFSET 0x2
191 /* Gigabit Ethernet Unit Global Registers */
193 /* MIB Counters register definitions */
194 #define ETH_MIB_GOOD_OCTETS_RECEIVED_LOW 0x0
195 #define ETH_MIB_GOOD_OCTETS_RECEIVED_HIGH 0x4
196 #define ETH_MIB_BAD_OCTETS_RECEIVED 0x8
197 #define ETH_MIB_INTERNAL_MAC_TRANSMIT_ERR 0xc
198 #define ETH_MIB_GOOD_FRAMES_RECEIVED 0x10
199 #define ETH_MIB_BAD_FRAMES_RECEIVED 0x14
200 #define ETH_MIB_BROADCAST_FRAMES_RECEIVED 0x18
201 #define ETH_MIB_MULTICAST_FRAMES_RECEIVED 0x1c
202 #define ETH_MIB_FRAMES_64_OCTETS 0x20
203 #define ETH_MIB_FRAMES_65_TO_127_OCTETS 0x24
204 #define ETH_MIB_FRAMES_128_TO_255_OCTETS 0x28
205 #define ETH_MIB_FRAMES_256_TO_511_OCTETS 0x2c
206 #define ETH_MIB_FRAMES_512_TO_1023_OCTETS 0x30
207 #define ETH_MIB_FRAMES_1024_TO_MAX_OCTETS 0x34
208 #define ETH_MIB_GOOD_OCTETS_SENT_LOW 0x38
209 #define ETH_MIB_GOOD_OCTETS_SENT_HIGH 0x3c
210 #define ETH_MIB_GOOD_FRAMES_SENT 0x40
211 #define ETH_MIB_EXCESSIVE_COLLISION 0x44
212 #define ETH_MIB_MULTICAST_FRAMES_SENT 0x48
213 #define ETH_MIB_BROADCAST_FRAMES_SENT 0x4c
214 #define ETH_MIB_UNREC_MAC_CONTROL_RECEIVED 0x50
215 #define ETH_MIB_FC_SENT 0x54
216 #define ETH_MIB_GOOD_FC_RECEIVED 0x58
217 #define ETH_MIB_BAD_FC_RECEIVED 0x5c
218 #define ETH_MIB_UNDERSIZE_RECEIVED 0x60
219 #define ETH_MIB_FRAGMENTS_RECEIVED 0x64
220 #define ETH_MIB_OVERSIZE_RECEIVED 0x68
221 #define ETH_MIB_JABBER_RECEIVED 0x6c
222 #define ETH_MIB_MAC_RECEIVE_ERROR 0x70
223 #define ETH_MIB_BAD_CRC_EVENT 0x74
224 #define ETH_MIB_COLLISION 0x78
225 #define ETH_MIB_LATE_COLLISION 0x7c
227 /* Port serial status reg (PSR) */
228 #define ETH_INTERFACE_PCM 0x00000001
229 #define ETH_LINK_IS_UP 0x00000002
230 #define ETH_PORT_AT_FULL_DUPLEX 0x00000004
231 #define ETH_RX_FLOW_CTRL_ENABLED 0x00000008
232 #define ETH_GMII_SPEED_1000 0x00000010
233 #define ETH_MII_SPEED_100 0x00000020
234 #define ETH_TX_IN_PROGRESS 0x00000080
235 #define ETH_BYPASS_ACTIVE 0x00000100
236 #define ETH_PORT_AT_PARTITION_STATE 0x00000200
237 #define ETH_PORT_TX_FIFO_EMPTY 0x00000400
240 #define ETH_SMI_BUSY 0x10000000 /* 0 - Write, 1 - Read */
241 #define ETH_SMI_READ_VALID 0x08000000 /* 0 - Write, 1 - Read */
242 #define ETH_SMI_OPCODE_WRITE 0 /* Completion of Read */
243 #define ETH_SMI_OPCODE_READ 0x04000000 /* Operation is in progress */
245 /* Interrupt Cause Register Bit Definitions */
247 /* SDMA command status fields macros */
249 /* Tx & Rx descriptors status */
250 #define ETH_ERROR_SUMMARY 0x00000001
252 /* Tx & Rx descriptors command */
253 #define ETH_BUFFER_OWNED_BY_DMA 0x80000000
255 /* Tx descriptors status */
256 #define ETH_LC_ERROR 0
257 #define ETH_UR_ERROR 0x00000002
258 #define ETH_RL_ERROR 0x00000004
259 #define ETH_LLC_SNAP_FORMAT 0x00000200
261 /* Rx descriptors status */
262 #define ETH_OVERRUN_ERROR 0x00000002
263 #define ETH_MAX_FRAME_LENGTH_ERROR 0x00000004
264 #define ETH_RESOURCE_ERROR 0x00000006
265 #define ETH_VLAN_TAGGED 0x00080000
266 #define ETH_BPDU_FRAME 0x00100000
267 #define ETH_UDP_FRAME_OVER_IP_V_4 0x00200000
268 #define ETH_OTHER_FRAME_TYPE 0x00400000
269 #define ETH_LAYER_2_IS_ETH_V_2 0x00800000
270 #define ETH_FRAME_TYPE_IP_V_4 0x01000000
271 #define ETH_FRAME_HEADER_OK 0x02000000
272 #define ETH_RX_LAST_DESC 0x04000000
273 #define ETH_RX_FIRST_DESC 0x08000000
274 #define ETH_UNKNOWN_DESTINATION_ADDR 0x10000000
275 #define ETH_RX_ENABLE_INTERRUPT 0x20000000
276 #define ETH_LAYER_4_CHECKSUM_OK 0x40000000
278 /* Rx descriptors byte count */
279 #define ETH_FRAME_FRAGMENTED 0x00000004
281 /* Tx descriptors command */
282 #define ETH_LAYER_4_CHECKSUM_FIRST_DESC 0x00000400
283 #define ETH_FRAME_SET_TO_VLAN 0x00008000
284 #define ETH_UDP_FRAME 0x00010000
285 #define ETH_GEN_TCP_UDP_CHECKSUM 0x00020000
286 #define ETH_GEN_IP_V_4_CHECKSUM 0x00040000
287 #define ETH_ZERO_PADDING 0x00080000
288 #define ETH_TX_LAST_DESC 0x00100000
289 #define ETH_TX_FIRST_DESC 0x00200000
290 #define ETH_GEN_CRC 0x00400000
291 #define ETH_TX_ENABLE_INTERRUPT 0x00800000
292 #define ETH_AUTO_MODE 0x40000000
294 #define ETH_TX_IHL_SHIFT 11
298 typedef enum _eth_func_ret_status {
299 ETH_OK, /* Returned as expected. */
300 ETH_ERROR, /* Fundamental error. */
301 ETH_RETRY, /* Could not process request. Try later.*/
302 ETH_END_OF_JOB, /* Ring has nothing to process. */
303 ETH_QUEUE_FULL, /* Ring resource error. */
304 ETH_QUEUE_LAST_RESOURCE /* Ring resources about to exhaust. */
305 } ETH_FUNC_RET_STATUS;
307 /* These are for big-endian machines. Little endian needs different
310 #if defined(__BIG_ENDIAN)
312 u16 byte_cnt; /* Descriptor buffer byte count */
313 u16 buf_size; /* Buffer size */
314 u32 cmd_sts; /* Descriptor command status */
315 u32 next_desc_ptr; /* Next descriptor pointer */
316 u32 buf_ptr; /* Descriptor buffer pointer */
320 u16 byte_cnt; /* buffer byte count */
321 u16 l4i_chk; /* CPU provided TCP checksum */
322 u32 cmd_sts; /* Command/status field */
323 u32 next_desc_ptr; /* Pointer to next descriptor */
324 u32 buf_ptr; /* pointer to buffer for this descriptor*/
326 #elif defined(__LITTLE_ENDIAN)
328 u32 cmd_sts; /* Descriptor command status */
329 u16 buf_size; /* Buffer size */
330 u16 byte_cnt; /* Descriptor buffer byte count */
331 u32 buf_ptr; /* Descriptor buffer pointer */
332 u32 next_desc_ptr; /* Next descriptor pointer */
336 u32 cmd_sts; /* Command/status field */
337 u16 l4i_chk; /* CPU provided TCP checksum */
338 u16 byte_cnt; /* buffer byte count */
339 u32 buf_ptr; /* pointer to buffer for this descriptor*/
340 u32 next_desc_ptr; /* Pointer to next descriptor */
343 #error One of __BIG_ENDIAN or __LITTLE_ENDIAN must be defined
346 /* Unified struct for Rx and Tx operations. The user is not required to */
347 /* be familier with neither Tx nor Rx descriptors. */
349 unsigned short byte_cnt; /* Descriptor buffer byte count */
350 unsigned short l4i_chk; /* Tx CPU provided TCP Checksum */
351 unsigned int cmd_sts; /* Descriptor command status */
352 dma_addr_t buf_ptr; /* Descriptor buffer pointer */
353 struct sk_buff *return_info; /* User resource return information */
357 /* global *******************************************************************/
358 struct mv643xx_shared_private {
359 void __iomem *eth_base;
361 /* used to protect SMI_REG, which is shared across ports */
370 /* per-port *****************************************************************/
371 struct mv643xx_mib_counters {
372 u64 good_octets_received;
373 u32 bad_octets_received;
374 u32 internal_mac_transmit_err;
375 u32 good_frames_received;
376 u32 bad_frames_received;
377 u32 broadcast_frames_received;
378 u32 multicast_frames_received;
379 u32 frames_64_octets;
380 u32 frames_65_to_127_octets;
381 u32 frames_128_to_255_octets;
382 u32 frames_256_to_511_octets;
383 u32 frames_512_to_1023_octets;
384 u32 frames_1024_to_max_octets;
385 u64 good_octets_sent;
386 u32 good_frames_sent;
387 u32 excessive_collision;
388 u32 multicast_frames_sent;
389 u32 broadcast_frames_sent;
390 u32 unrec_mac_control_received;
392 u32 good_fc_received;
394 u32 undersize_received;
395 u32 fragments_received;
396 u32 oversize_received;
398 u32 mac_receive_error;
404 struct mv643xx_private {
405 struct mv643xx_shared_private *shared;
406 int port_num; /* User Ethernet port number */
408 struct mv643xx_shared_private *shared_smi;
410 u32 rx_sram_addr; /* Base address of rx sram area */
411 u32 rx_sram_size; /* Size of rx sram area */
412 u32 tx_sram_addr; /* Base address of tx sram area */
413 u32 tx_sram_size; /* Size of tx sram area */
415 int rx_resource_err; /* Rx ring resource error flag */
417 /* Tx/Rx rings managment indexes fields. For driver use */
419 /* Next available and first returning Rx resource */
420 int rx_curr_desc_q, rx_used_desc_q;
422 /* Next available and first returning Tx resource */
423 int tx_curr_desc_q, tx_used_desc_q;
425 #ifdef MV643XX_TX_FAST_REFILL
426 u32 tx_clean_threshold;
429 struct eth_rx_desc *p_rx_desc_area;
430 dma_addr_t rx_desc_dma;
431 int rx_desc_area_size;
432 struct sk_buff **rx_skb;
434 struct eth_tx_desc *p_tx_desc_area;
435 dma_addr_t tx_desc_dma;
436 int tx_desc_area_size;
437 struct sk_buff **tx_skb;
439 struct work_struct tx_timeout_task;
441 struct net_device *dev;
442 struct napi_struct napi;
443 struct net_device_stats stats;
444 struct mv643xx_mib_counters mib_counters;
446 /* Size of Tx Ring per queue */
448 /* Number of tx descriptors in use */
450 /* Size of Rx Ring per queue */
452 /* Number of rx descriptors in use */
456 * Used in case RX Ring is empty, which can be caused when
457 * system does not have resources (skb's)
459 struct timer_list timeout;
463 struct mii_if_info mii;
467 /* port register accessors **************************************************/
468 static inline u32 rdl(struct mv643xx_private *mp, int offset)
470 return readl(mp->shared->eth_base + offset);
473 static inline void wrl(struct mv643xx_private *mp, int offset, u32 data)
475 writel(data, mp->shared->eth_base + offset);
479 /* rxq/txq helper functions *************************************************/
480 static void mv643xx_eth_port_enable_rx(struct mv643xx_private *mp,
483 wrl(mp, RXQ_COMMAND(mp->port_num), queues);
486 static unsigned int mv643xx_eth_port_disable_rx(struct mv643xx_private *mp)
488 unsigned int port_num = mp->port_num;
491 /* Stop Rx port activity. Check port Rx activity. */
492 queues = rdl(mp, RXQ_COMMAND(port_num)) & 0xFF;
494 /* Issue stop command for active queues only */
495 wrl(mp, RXQ_COMMAND(port_num), (queues << 8));
497 /* Wait for all Rx activity to terminate. */
498 /* Check port cause register that all Rx queues are stopped */
499 while (rdl(mp, RXQ_COMMAND(port_num)) & 0xFF)
500 udelay(PHY_WAIT_MICRO_SECONDS);
506 static void mv643xx_eth_port_enable_tx(struct mv643xx_private *mp,
509 wrl(mp, TXQ_COMMAND(mp->port_num), queues);
512 static unsigned int mv643xx_eth_port_disable_tx(struct mv643xx_private *mp)
514 unsigned int port_num = mp->port_num;
517 /* Stop Tx port activity. Check port Tx activity. */
518 queues = rdl(mp, TXQ_COMMAND(port_num)) & 0xFF;
520 /* Issue stop command for active queues only */
521 wrl(mp, TXQ_COMMAND(port_num), (queues << 8));
523 /* Wait for all Tx activity to terminate. */
524 /* Check port cause register that all Tx queues are stopped */
525 while (rdl(mp, TXQ_COMMAND(port_num)) & 0xFF)
526 udelay(PHY_WAIT_MICRO_SECONDS);
528 /* Wait for Tx FIFO to empty */
529 while (rdl(mp, PORT_STATUS(port_num)) & ETH_PORT_TX_FIFO_EMPTY)
530 udelay(PHY_WAIT_MICRO_SECONDS);
537 /* rx ***********************************************************************/
538 static void mv643xx_eth_free_completed_tx_descs(struct net_device *dev);
541 * eth_rx_return_buff - Returns a Rx buffer back to the Rx ring.
544 * This routine returns a Rx buffer back to the Rx ring. It retrieves the
545 * next 'used' descriptor and attached the returned buffer to it.
546 * In case the Rx ring was in "resource error" condition, where there are
547 * no available Rx resources, the function resets the resource error flag.
550 * struct mv643xx_private *mp Ethernet Port Control srtuct.
551 * struct pkt_info *p_pkt_info Information on returned buffer.
554 * New available Rx resource in Rx descriptor ring.
557 * ETH_ERROR in case the routine can not access Rx desc ring.
560 static ETH_FUNC_RET_STATUS eth_rx_return_buff(struct mv643xx_private *mp,
561 struct pkt_info *p_pkt_info)
563 int used_rx_desc; /* Where to return Rx resource */
564 volatile struct eth_rx_desc *p_used_rx_desc;
567 spin_lock_irqsave(&mp->lock, flags);
569 /* Get 'used' Rx descriptor */
570 used_rx_desc = mp->rx_used_desc_q;
571 p_used_rx_desc = &mp->p_rx_desc_area[used_rx_desc];
573 p_used_rx_desc->buf_ptr = p_pkt_info->buf_ptr;
574 p_used_rx_desc->buf_size = p_pkt_info->byte_cnt;
575 mp->rx_skb[used_rx_desc] = p_pkt_info->return_info;
577 /* Flush the write pipe */
579 /* Return the descriptor to DMA ownership */
581 p_used_rx_desc->cmd_sts =
582 ETH_BUFFER_OWNED_BY_DMA | ETH_RX_ENABLE_INTERRUPT;
585 /* Move the used descriptor pointer to the next descriptor */
586 mp->rx_used_desc_q = (used_rx_desc + 1) % mp->rx_ring_size;
588 /* Any Rx return cancels the Rx resource error status */
589 mp->rx_resource_err = 0;
591 spin_unlock_irqrestore(&mp->lock, flags);
597 * mv643xx_eth_rx_refill_descs
599 * Fills / refills RX queue on a certain gigabit ethernet port
601 * Input : pointer to ethernet interface network device structure
604 static void mv643xx_eth_rx_refill_descs(struct net_device *dev)
606 struct mv643xx_private *mp = netdev_priv(dev);
607 struct pkt_info pkt_info;
611 while (mp->rx_desc_count < mp->rx_ring_size) {
612 skb = dev_alloc_skb(ETH_RX_SKB_SIZE + dma_get_cache_alignment());
616 unaligned = (u32)skb->data & (dma_get_cache_alignment() - 1);
618 skb_reserve(skb, dma_get_cache_alignment() - unaligned);
619 pkt_info.cmd_sts = ETH_RX_ENABLE_INTERRUPT;
620 pkt_info.byte_cnt = ETH_RX_SKB_SIZE;
621 pkt_info.buf_ptr = dma_map_single(NULL, skb->data,
622 ETH_RX_SKB_SIZE, DMA_FROM_DEVICE);
623 pkt_info.return_info = skb;
624 if (eth_rx_return_buff(mp, &pkt_info) != ETH_OK) {
626 "%s: Error allocating RX Ring\n", dev->name);
629 skb_reserve(skb, ETH_HW_IP_ALIGN);
632 * If RX ring is empty of SKB, set a timer to try allocating
633 * again at a later time.
635 if (mp->rx_desc_count == 0) {
636 printk(KERN_INFO "%s: Rx ring is empty\n", dev->name);
637 mp->timeout.expires = jiffies + (HZ / 10); /* 100 mSec */
638 add_timer(&mp->timeout);
643 * mv643xx_eth_rx_refill_descs_timer_wrapper
645 * Timer routine to wake up RX queue filling task. This function is
646 * used only in case the RX queue is empty, and all alloc_skb has
647 * failed (due to out of memory event).
649 * Input : pointer to ethernet interface network device structure
652 static inline void mv643xx_eth_rx_refill_descs_timer_wrapper(unsigned long data)
654 mv643xx_eth_rx_refill_descs((struct net_device *)data);
658 * eth_port_receive - Get received information from Rx ring.
661 * This routine returns the received data to the caller. There is no
662 * data copying during routine operation. All information is returned
663 * using pointer to packet information struct passed from the caller.
664 * If the routine exhausts Rx ring resources then the resource error flag
668 * struct mv643xx_private *mp Ethernet Port Control srtuct.
669 * struct pkt_info *p_pkt_info User packet buffer.
672 * Rx ring current and used indexes are updated.
675 * ETH_ERROR in case the routine can not access Rx desc ring.
676 * ETH_QUEUE_FULL if Rx ring resources are exhausted.
677 * ETH_END_OF_JOB if there is no received data.
680 static ETH_FUNC_RET_STATUS eth_port_receive(struct mv643xx_private *mp,
681 struct pkt_info *p_pkt_info)
683 int rx_next_curr_desc, rx_curr_desc, rx_used_desc;
684 volatile struct eth_rx_desc *p_rx_desc;
685 unsigned int command_status;
688 /* Do not process Rx ring in case of Rx ring resource error */
689 if (mp->rx_resource_err)
690 return ETH_QUEUE_FULL;
692 spin_lock_irqsave(&mp->lock, flags);
694 /* Get the Rx Desc ring 'curr and 'used' indexes */
695 rx_curr_desc = mp->rx_curr_desc_q;
696 rx_used_desc = mp->rx_used_desc_q;
698 p_rx_desc = &mp->p_rx_desc_area[rx_curr_desc];
700 /* The following parameters are used to save readings from memory */
701 command_status = p_rx_desc->cmd_sts;
704 /* Nothing to receive... */
705 if (command_status & (ETH_BUFFER_OWNED_BY_DMA)) {
706 spin_unlock_irqrestore(&mp->lock, flags);
707 return ETH_END_OF_JOB;
710 p_pkt_info->byte_cnt = (p_rx_desc->byte_cnt) - RX_BUF_OFFSET;
711 p_pkt_info->cmd_sts = command_status;
712 p_pkt_info->buf_ptr = (p_rx_desc->buf_ptr) + RX_BUF_OFFSET;
713 p_pkt_info->return_info = mp->rx_skb[rx_curr_desc];
714 p_pkt_info->l4i_chk = p_rx_desc->buf_size;
717 * Clean the return info field to indicate that the
718 * packet has been moved to the upper layers
720 mp->rx_skb[rx_curr_desc] = NULL;
722 /* Update current index in data structure */
723 rx_next_curr_desc = (rx_curr_desc + 1) % mp->rx_ring_size;
724 mp->rx_curr_desc_q = rx_next_curr_desc;
726 /* Rx descriptors exhausted. Set the Rx ring resource error flag */
727 if (rx_next_curr_desc == rx_used_desc)
728 mp->rx_resource_err = 1;
730 spin_unlock_irqrestore(&mp->lock, flags);
736 * mv643xx_eth_receive
738 * This function is forward packets that are received from the port's
739 * queues toward kernel core or FastRoute them to another interface.
741 * Input : dev - a pointer to the required interface
742 * max - maximum number to receive (0 means unlimted)
744 * Output : number of served packets
746 static int mv643xx_eth_receive_queue(struct net_device *dev, int budget)
748 struct mv643xx_private *mp = netdev_priv(dev);
749 struct net_device_stats *stats = &dev->stats;
750 unsigned int received_packets = 0;
752 struct pkt_info pkt_info;
754 while (budget-- > 0 && eth_port_receive(mp, &pkt_info) == ETH_OK) {
755 dma_unmap_single(NULL, pkt_info.buf_ptr, ETH_RX_SKB_SIZE,
762 * Note byte count includes 4 byte CRC count
765 stats->rx_bytes += pkt_info.byte_cnt;
766 skb = pkt_info.return_info;
768 * In case received a packet without first / last bits on OR
769 * the error summary bit is on, the packets needs to be dropeed.
771 if (((pkt_info.cmd_sts
772 & (ETH_RX_FIRST_DESC | ETH_RX_LAST_DESC)) !=
773 (ETH_RX_FIRST_DESC | ETH_RX_LAST_DESC))
774 || (pkt_info.cmd_sts & ETH_ERROR_SUMMARY)) {
776 if ((pkt_info.cmd_sts & (ETH_RX_FIRST_DESC |
777 ETH_RX_LAST_DESC)) !=
778 (ETH_RX_FIRST_DESC | ETH_RX_LAST_DESC)) {
781 "%s: Received packet spread "
782 "on multiple descriptors\n",
785 if (pkt_info.cmd_sts & ETH_ERROR_SUMMARY)
788 dev_kfree_skb_irq(skb);
791 * The -4 is for the CRC in the trailer of the
794 skb_put(skb, pkt_info.byte_cnt - 4);
796 if (pkt_info.cmd_sts & ETH_LAYER_4_CHECKSUM_OK) {
797 skb->ip_summed = CHECKSUM_UNNECESSARY;
799 (pkt_info.cmd_sts & 0x0007fff8) >> 3);
801 skb->protocol = eth_type_trans(skb, dev);
803 netif_receive_skb(skb);
808 dev->last_rx = jiffies;
810 mv643xx_eth_rx_refill_descs(dev); /* Fill RX ring with skb's */
812 return received_packets;
819 * This function is used in case of NAPI
821 static int mv643xx_poll(struct napi_struct *napi, int budget)
823 struct mv643xx_private *mp = container_of(napi, struct mv643xx_private, napi);
824 struct net_device *dev = mp->dev;
825 unsigned int port_num = mp->port_num;
828 #ifdef MV643XX_TX_FAST_REFILL
829 if (++mp->tx_clean_threshold > 5) {
830 mv643xx_eth_free_completed_tx_descs(dev);
831 mp->tx_clean_threshold = 0;
836 if ((rdl(mp, RXQ_CURRENT_DESC_PTR(port_num)))
837 != (u32) mp->rx_used_desc_q)
838 work_done = mv643xx_eth_receive_queue(dev, budget);
840 if (work_done < budget) {
841 netif_rx_complete(dev, napi);
842 wrl(mp, INT_CAUSE(port_num), 0);
843 wrl(mp, INT_CAUSE_EXT(port_num), 0);
844 wrl(mp, INT_MASK(port_num), ETH_INT_UNMASK_ALL);
852 /* tx ***********************************************************************/
854 * has_tiny_unaligned_frags - check if skb has any small, unaligned fragments
856 * Hardware can't handle unaligned fragments smaller than 9 bytes.
857 * This helper function detects that case.
860 static inline unsigned int has_tiny_unaligned_frags(struct sk_buff *skb)
865 for (frag = 0; frag < skb_shinfo(skb)->nr_frags; frag++) {
866 fragp = &skb_shinfo(skb)->frags[frag];
867 if (fragp->size <= 8 && fragp->page_offset & 0x7)
874 * eth_alloc_tx_desc_index - return the index of the next available tx desc
876 static int eth_alloc_tx_desc_index(struct mv643xx_private *mp)
880 BUG_ON(mp->tx_desc_count >= mp->tx_ring_size);
882 tx_desc_curr = mp->tx_curr_desc_q;
883 mp->tx_curr_desc_q = (tx_desc_curr + 1) % mp->tx_ring_size;
885 BUG_ON(mp->tx_curr_desc_q == mp->tx_used_desc_q);
891 * eth_tx_fill_frag_descs - fill tx hw descriptors for an skb's fragments.
893 * Ensure the data for each fragment to be transmitted is mapped properly,
894 * then fill in descriptors in the tx hw queue.
896 static void eth_tx_fill_frag_descs(struct mv643xx_private *mp,
901 struct eth_tx_desc *desc;
903 for (frag = 0; frag < skb_shinfo(skb)->nr_frags; frag++) {
904 skb_frag_t *this_frag = &skb_shinfo(skb)->frags[frag];
906 tx_index = eth_alloc_tx_desc_index(mp);
907 desc = &mp->p_tx_desc_area[tx_index];
909 desc->cmd_sts = ETH_BUFFER_OWNED_BY_DMA;
910 /* Last Frag enables interrupt and frees the skb */
911 if (frag == (skb_shinfo(skb)->nr_frags - 1)) {
912 desc->cmd_sts |= ETH_ZERO_PADDING |
914 ETH_TX_ENABLE_INTERRUPT;
915 mp->tx_skb[tx_index] = skb;
917 mp->tx_skb[tx_index] = NULL;
919 desc = &mp->p_tx_desc_area[tx_index];
921 desc->byte_cnt = this_frag->size;
922 desc->buf_ptr = dma_map_page(NULL, this_frag->page,
923 this_frag->page_offset,
929 static inline __be16 sum16_as_be(__sum16 sum)
931 return (__force __be16)sum;
935 * eth_tx_submit_descs_for_skb - submit data from an skb to the tx hw
937 * Ensure the data for an skb to be transmitted is mapped properly,
938 * then fill in descriptors in the tx hw queue and start the hardware.
940 static void eth_tx_submit_descs_for_skb(struct mv643xx_private *mp,
944 struct eth_tx_desc *desc;
947 int nr_frags = skb_shinfo(skb)->nr_frags;
949 cmd_sts = ETH_TX_FIRST_DESC | ETH_GEN_CRC | ETH_BUFFER_OWNED_BY_DMA;
951 tx_index = eth_alloc_tx_desc_index(mp);
952 desc = &mp->p_tx_desc_area[tx_index];
955 eth_tx_fill_frag_descs(mp, skb);
957 length = skb_headlen(skb);
958 mp->tx_skb[tx_index] = NULL;
960 cmd_sts |= ETH_ZERO_PADDING |
962 ETH_TX_ENABLE_INTERRUPT;
964 mp->tx_skb[tx_index] = skb;
967 desc->byte_cnt = length;
968 desc->buf_ptr = dma_map_single(NULL, skb->data, length, DMA_TO_DEVICE);
970 if (skb->ip_summed == CHECKSUM_PARTIAL) {
971 BUG_ON(skb->protocol != htons(ETH_P_IP));
973 cmd_sts |= ETH_GEN_TCP_UDP_CHECKSUM |
974 ETH_GEN_IP_V_4_CHECKSUM |
975 ip_hdr(skb)->ihl << ETH_TX_IHL_SHIFT;
977 switch (ip_hdr(skb)->protocol) {
979 cmd_sts |= ETH_UDP_FRAME;
980 desc->l4i_chk = ntohs(sum16_as_be(udp_hdr(skb)->check));
983 desc->l4i_chk = ntohs(sum16_as_be(tcp_hdr(skb)->check));
989 /* Errata BTS #50, IHL must be 5 if no HW checksum */
990 cmd_sts |= 5 << ETH_TX_IHL_SHIFT;
994 /* ensure all other descriptors are written before first cmd_sts */
996 desc->cmd_sts = cmd_sts;
998 /* ensure all descriptors are written before poking hardware */
1000 mv643xx_eth_port_enable_tx(mp, ETH_TX_QUEUES_ENABLED);
1002 mp->tx_desc_count += nr_frags + 1;
1006 * mv643xx_eth_start_xmit - queue an skb to the hardware for transmission
1009 static int mv643xx_eth_start_xmit(struct sk_buff *skb, struct net_device *dev)
1011 struct mv643xx_private *mp = netdev_priv(dev);
1012 struct net_device_stats *stats = &dev->stats;
1013 unsigned long flags;
1015 BUG_ON(netif_queue_stopped(dev));
1017 if (has_tiny_unaligned_frags(skb) && __skb_linearize(skb)) {
1018 stats->tx_dropped++;
1019 printk(KERN_DEBUG "%s: failed to linearize tiny "
1020 "unaligned fragment\n", dev->name);
1021 return NETDEV_TX_BUSY;
1024 spin_lock_irqsave(&mp->lock, flags);
1026 if (mp->tx_ring_size - mp->tx_desc_count < MAX_DESCS_PER_SKB) {
1027 printk(KERN_ERR "%s: transmit with queue full\n", dev->name);
1028 netif_stop_queue(dev);
1029 spin_unlock_irqrestore(&mp->lock, flags);
1030 return NETDEV_TX_BUSY;
1033 eth_tx_submit_descs_for_skb(mp, skb);
1034 stats->tx_bytes += skb->len;
1035 stats->tx_packets++;
1036 dev->trans_start = jiffies;
1038 if (mp->tx_ring_size - mp->tx_desc_count < MAX_DESCS_PER_SKB)
1039 netif_stop_queue(dev);
1041 spin_unlock_irqrestore(&mp->lock, flags);
1043 return NETDEV_TX_OK;
1047 /* mii management interface *************************************************/
1048 static int ethernet_phy_get(struct mv643xx_private *mp);
1051 * eth_port_read_smi_reg - Read PHY registers
1054 * This routine utilize the SMI interface to interact with the PHY in
1055 * order to perform PHY register read.
1058 * struct mv643xx_private *mp Ethernet Port.
1059 * unsigned int phy_reg PHY register address offset.
1060 * unsigned int *value Register value buffer.
1063 * Write the value of a specified PHY register into given buffer.
1066 * false if the PHY is busy or read data is not in valid state.
1070 static void eth_port_read_smi_reg(struct mv643xx_private *mp,
1071 unsigned int phy_reg, unsigned int *value)
1073 void __iomem *smi_reg = mp->shared_smi->eth_base + SMI_REG;
1074 int phy_addr = ethernet_phy_get(mp);
1075 unsigned long flags;
1078 /* the SMI register is a shared resource */
1079 spin_lock_irqsave(&mp->shared_smi->phy_lock, flags);
1081 /* wait for the SMI register to become available */
1082 for (i = 0; readl(smi_reg) & ETH_SMI_BUSY; i++) {
1083 if (i == PHY_WAIT_ITERATIONS) {
1084 printk("%s: PHY busy timeout\n", mp->dev->name);
1087 udelay(PHY_WAIT_MICRO_SECONDS);
1090 writel((phy_addr << 16) | (phy_reg << 21) | ETH_SMI_OPCODE_READ,
1093 /* now wait for the data to be valid */
1094 for (i = 0; !(readl(smi_reg) & ETH_SMI_READ_VALID); i++) {
1095 if (i == PHY_WAIT_ITERATIONS) {
1096 printk("%s: PHY read timeout\n", mp->dev->name);
1099 udelay(PHY_WAIT_MICRO_SECONDS);
1102 *value = readl(smi_reg) & 0xffff;
1104 spin_unlock_irqrestore(&mp->shared_smi->phy_lock, flags);
1108 * eth_port_write_smi_reg - Write to PHY registers
1111 * This routine utilize the SMI interface to interact with the PHY in
1112 * order to perform writes to PHY registers.
1115 * struct mv643xx_private *mp Ethernet Port.
1116 * unsigned int phy_reg PHY register address offset.
1117 * unsigned int value Register value.
1120 * Write the given value to the specified PHY register.
1123 * false if the PHY is busy.
1127 static void eth_port_write_smi_reg(struct mv643xx_private *mp,
1128 unsigned int phy_reg, unsigned int value)
1130 void __iomem *smi_reg = mp->shared_smi->eth_base + SMI_REG;
1131 int phy_addr = ethernet_phy_get(mp);
1132 unsigned long flags;
1135 /* the SMI register is a shared resource */
1136 spin_lock_irqsave(&mp->shared_smi->phy_lock, flags);
1138 /* wait for the SMI register to become available */
1139 for (i = 0; readl(smi_reg) & ETH_SMI_BUSY; i++) {
1140 if (i == PHY_WAIT_ITERATIONS) {
1141 printk("%s: PHY busy timeout\n", mp->dev->name);
1144 udelay(PHY_WAIT_MICRO_SECONDS);
1147 writel((phy_addr << 16) | (phy_reg << 21) |
1148 ETH_SMI_OPCODE_WRITE | (value & 0xffff), smi_reg);
1150 spin_unlock_irqrestore(&mp->shared_smi->phy_lock, flags);
1154 /* mib counters *************************************************************/
1156 * eth_clear_mib_counters - Clear all MIB counters
1159 * This function clears all MIB counters of a specific ethernet port.
1160 * A read from the MIB counter will reset the counter.
1163 * struct mv643xx_private *mp Ethernet Port.
1166 * After reading all MIB counters, the counters resets.
1169 * MIB counter value.
1172 static void eth_clear_mib_counters(struct mv643xx_private *mp)
1174 unsigned int port_num = mp->port_num;
1177 /* Perform dummy reads from MIB counters */
1178 for (i = ETH_MIB_GOOD_OCTETS_RECEIVED_LOW; i < ETH_MIB_LATE_COLLISION;
1180 rdl(mp, MIB_COUNTERS(port_num) + i);
1183 static inline u32 read_mib(struct mv643xx_private *mp, int offset)
1185 return rdl(mp, MIB_COUNTERS(mp->port_num) + offset);
1188 static void eth_update_mib_counters(struct mv643xx_private *mp)
1190 struct mv643xx_mib_counters *p = &mp->mib_counters;
1193 p->good_octets_received +=
1194 read_mib(mp, ETH_MIB_GOOD_OCTETS_RECEIVED_LOW);
1195 p->good_octets_received +=
1196 (u64)read_mib(mp, ETH_MIB_GOOD_OCTETS_RECEIVED_HIGH) << 32;
1198 for (offset = ETH_MIB_BAD_OCTETS_RECEIVED;
1199 offset <= ETH_MIB_FRAMES_1024_TO_MAX_OCTETS;
1201 *(u32 *)((char *)p + offset) += read_mib(mp, offset);
1203 p->good_octets_sent += read_mib(mp, ETH_MIB_GOOD_OCTETS_SENT_LOW);
1204 p->good_octets_sent +=
1205 (u64)read_mib(mp, ETH_MIB_GOOD_OCTETS_SENT_HIGH) << 32;
1207 for (offset = ETH_MIB_GOOD_FRAMES_SENT;
1208 offset <= ETH_MIB_LATE_COLLISION;
1210 *(u32 *)((char *)p + offset) += read_mib(mp, offset);
1214 /* ethtool ******************************************************************/
1215 struct mv643xx_stats {
1216 char stat_string[ETH_GSTRING_LEN];
1221 #define MV643XX_STAT(m) FIELD_SIZEOF(struct mv643xx_private, m), \
1222 offsetof(struct mv643xx_private, m)
1224 static const struct mv643xx_stats mv643xx_gstrings_stats[] = {
1225 { "rx_packets", MV643XX_STAT(stats.rx_packets) },
1226 { "tx_packets", MV643XX_STAT(stats.tx_packets) },
1227 { "rx_bytes", MV643XX_STAT(stats.rx_bytes) },
1228 { "tx_bytes", MV643XX_STAT(stats.tx_bytes) },
1229 { "rx_errors", MV643XX_STAT(stats.rx_errors) },
1230 { "tx_errors", MV643XX_STAT(stats.tx_errors) },
1231 { "rx_dropped", MV643XX_STAT(stats.rx_dropped) },
1232 { "tx_dropped", MV643XX_STAT(stats.tx_dropped) },
1233 { "good_octets_received", MV643XX_STAT(mib_counters.good_octets_received) },
1234 { "bad_octets_received", MV643XX_STAT(mib_counters.bad_octets_received) },
1235 { "internal_mac_transmit_err", MV643XX_STAT(mib_counters.internal_mac_transmit_err) },
1236 { "good_frames_received", MV643XX_STAT(mib_counters.good_frames_received) },
1237 { "bad_frames_received", MV643XX_STAT(mib_counters.bad_frames_received) },
1238 { "broadcast_frames_received", MV643XX_STAT(mib_counters.broadcast_frames_received) },
1239 { "multicast_frames_received", MV643XX_STAT(mib_counters.multicast_frames_received) },
1240 { "frames_64_octets", MV643XX_STAT(mib_counters.frames_64_octets) },
1241 { "frames_65_to_127_octets", MV643XX_STAT(mib_counters.frames_65_to_127_octets) },
1242 { "frames_128_to_255_octets", MV643XX_STAT(mib_counters.frames_128_to_255_octets) },
1243 { "frames_256_to_511_octets", MV643XX_STAT(mib_counters.frames_256_to_511_octets) },
1244 { "frames_512_to_1023_octets", MV643XX_STAT(mib_counters.frames_512_to_1023_octets) },
1245 { "frames_1024_to_max_octets", MV643XX_STAT(mib_counters.frames_1024_to_max_octets) },
1246 { "good_octets_sent", MV643XX_STAT(mib_counters.good_octets_sent) },
1247 { "good_frames_sent", MV643XX_STAT(mib_counters.good_frames_sent) },
1248 { "excessive_collision", MV643XX_STAT(mib_counters.excessive_collision) },
1249 { "multicast_frames_sent", MV643XX_STAT(mib_counters.multicast_frames_sent) },
1250 { "broadcast_frames_sent", MV643XX_STAT(mib_counters.broadcast_frames_sent) },
1251 { "unrec_mac_control_received", MV643XX_STAT(mib_counters.unrec_mac_control_received) },
1252 { "fc_sent", MV643XX_STAT(mib_counters.fc_sent) },
1253 { "good_fc_received", MV643XX_STAT(mib_counters.good_fc_received) },
1254 { "bad_fc_received", MV643XX_STAT(mib_counters.bad_fc_received) },
1255 { "undersize_received", MV643XX_STAT(mib_counters.undersize_received) },
1256 { "fragments_received", MV643XX_STAT(mib_counters.fragments_received) },
1257 { "oversize_received", MV643XX_STAT(mib_counters.oversize_received) },
1258 { "jabber_received", MV643XX_STAT(mib_counters.jabber_received) },
1259 { "mac_receive_error", MV643XX_STAT(mib_counters.mac_receive_error) },
1260 { "bad_crc_event", MV643XX_STAT(mib_counters.bad_crc_event) },
1261 { "collision", MV643XX_STAT(mib_counters.collision) },
1262 { "late_collision", MV643XX_STAT(mib_counters.late_collision) },
1265 #define MV643XX_STATS_LEN ARRAY_SIZE(mv643xx_gstrings_stats)
1267 static int mv643xx_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1269 struct mv643xx_private *mp = netdev_priv(dev);
1272 spin_lock_irq(&mp->lock);
1273 err = mii_ethtool_gset(&mp->mii, cmd);
1274 spin_unlock_irq(&mp->lock);
1276 /* The PHY may support 1000baseT_Half, but the mv643xx does not */
1277 cmd->supported &= ~SUPPORTED_1000baseT_Half;
1278 cmd->advertising &= ~ADVERTISED_1000baseT_Half;
1283 static int mv643xx_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1285 struct mv643xx_private *mp = netdev_priv(dev);
1288 spin_lock_irq(&mp->lock);
1289 err = mii_ethtool_sset(&mp->mii, cmd);
1290 spin_unlock_irq(&mp->lock);
1295 static void mv643xx_get_drvinfo(struct net_device *netdev,
1296 struct ethtool_drvinfo *drvinfo)
1298 strncpy(drvinfo->driver, mv643xx_driver_name, 32);
1299 strncpy(drvinfo->version, mv643xx_driver_version, 32);
1300 strncpy(drvinfo->fw_version, "N/A", 32);
1301 strncpy(drvinfo->bus_info, "mv643xx", 32);
1302 drvinfo->n_stats = MV643XX_STATS_LEN;
1305 static int mv643xx_eth_nway_restart(struct net_device *dev)
1307 struct mv643xx_private *mp = netdev_priv(dev);
1309 return mii_nway_restart(&mp->mii);
1312 static u32 mv643xx_eth_get_link(struct net_device *dev)
1314 struct mv643xx_private *mp = netdev_priv(dev);
1316 return mii_link_ok(&mp->mii);
1319 static void mv643xx_get_strings(struct net_device *netdev, uint32_t stringset,
1326 for (i=0; i < MV643XX_STATS_LEN; i++) {
1327 memcpy(data + i * ETH_GSTRING_LEN,
1328 mv643xx_gstrings_stats[i].stat_string,
1335 static void mv643xx_get_ethtool_stats(struct net_device *netdev,
1336 struct ethtool_stats *stats, uint64_t *data)
1338 struct mv643xx_private *mp = netdev->priv;
1341 eth_update_mib_counters(mp);
1343 for (i = 0; i < MV643XX_STATS_LEN; i++) {
1344 char *p = (char *)mp+mv643xx_gstrings_stats[i].stat_offset;
1345 data[i] = (mv643xx_gstrings_stats[i].sizeof_stat ==
1346 sizeof(uint64_t)) ? *(uint64_t *)p : *(uint32_t *)p;
1350 static int mv643xx_get_sset_count(struct net_device *netdev, int sset)
1354 return MV643XX_STATS_LEN;
1360 static const struct ethtool_ops mv643xx_ethtool_ops = {
1361 .get_settings = mv643xx_get_settings,
1362 .set_settings = mv643xx_set_settings,
1363 .get_drvinfo = mv643xx_get_drvinfo,
1364 .get_link = mv643xx_eth_get_link,
1365 .set_sg = ethtool_op_set_sg,
1366 .get_sset_count = mv643xx_get_sset_count,
1367 .get_ethtool_stats = mv643xx_get_ethtool_stats,
1368 .get_strings = mv643xx_get_strings,
1369 .nway_reset = mv643xx_eth_nway_restart,
1373 /* address handling *********************************************************/
1375 * eth_port_uc_addr_get - Read the MAC address from the port's hw registers
1377 static void eth_port_uc_addr_get(struct mv643xx_private *mp,
1378 unsigned char *p_addr)
1380 unsigned int port_num = mp->port_num;
1384 mac_h = rdl(mp, MAC_ADDR_HIGH(port_num));
1385 mac_l = rdl(mp, MAC_ADDR_LOW(port_num));
1387 p_addr[0] = (mac_h >> 24) & 0xff;
1388 p_addr[1] = (mac_h >> 16) & 0xff;
1389 p_addr[2] = (mac_h >> 8) & 0xff;
1390 p_addr[3] = mac_h & 0xff;
1391 p_addr[4] = (mac_l >> 8) & 0xff;
1392 p_addr[5] = mac_l & 0xff;
1396 * eth_port_init_mac_tables - Clear all entrance in the UC, SMC and OMC tables
1399 * Go through all the DA filter tables (Unicast, Special Multicast &
1400 * Other Multicast) and set each entry to 0.
1403 * struct mv643xx_private *mp Ethernet Port.
1406 * Multicast and Unicast packets are rejected.
1411 static void eth_port_init_mac_tables(struct mv643xx_private *mp)
1413 unsigned int port_num = mp->port_num;
1416 /* Clear DA filter unicast table (Ex_dFUT) */
1417 for (table_index = 0; table_index <= 0xC; table_index += 4)
1418 wrl(mp, UNICAST_TABLE(port_num) + table_index, 0);
1420 for (table_index = 0; table_index <= 0xFC; table_index += 4) {
1421 /* Clear DA filter special multicast table (Ex_dFSMT) */
1422 wrl(mp, SPECIAL_MCAST_TABLE(port_num) + table_index, 0);
1423 /* Clear DA filter other multicast table (Ex_dFOMT) */
1424 wrl(mp, OTHER_MCAST_TABLE(port_num) + table_index, 0);
1429 * The entries in each table are indexed by a hash of a packet's MAC
1430 * address. One bit in each entry determines whether the packet is
1431 * accepted. There are 4 entries (each 8 bits wide) in each register
1432 * of the table. The bits in each entry are defined as follows:
1433 * 0 Accept=1, Drop=0
1434 * 3-1 Queue (ETH_Q0=0)
1437 static void eth_port_set_filter_table_entry(struct mv643xx_private *mp,
1438 int table, unsigned char entry)
1440 unsigned int table_reg;
1441 unsigned int tbl_offset;
1442 unsigned int reg_offset;
1444 tbl_offset = (entry / 4) * 4; /* Register offset of DA table entry */
1445 reg_offset = entry % 4; /* Entry offset within the register */
1447 /* Set "accepts frame bit" at specified table entry */
1448 table_reg = rdl(mp, table + tbl_offset);
1449 table_reg |= 0x01 << (8 * reg_offset);
1450 wrl(mp, table + tbl_offset, table_reg);
1454 * eth_port_uc_addr_set - Write a MAC address into the port's hw registers
1456 static void eth_port_uc_addr_set(struct mv643xx_private *mp,
1457 unsigned char *p_addr)
1459 unsigned int port_num = mp->port_num;
1464 mac_l = (p_addr[4] << 8) | (p_addr[5]);
1465 mac_h = (p_addr[0] << 24) | (p_addr[1] << 16) | (p_addr[2] << 8) |
1468 wrl(mp, MAC_ADDR_LOW(port_num), mac_l);
1469 wrl(mp, MAC_ADDR_HIGH(port_num), mac_h);
1471 /* Accept frames with this address */
1472 table = UNICAST_TABLE(port_num);
1473 eth_port_set_filter_table_entry(mp, table, p_addr[5] & 0x0f);
1477 * mv643xx_eth_update_mac_address
1479 * Update the MAC address of the port in the address table
1481 * Input : pointer to ethernet interface network device structure
1484 static void mv643xx_eth_update_mac_address(struct net_device *dev)
1486 struct mv643xx_private *mp = netdev_priv(dev);
1488 eth_port_init_mac_tables(mp);
1489 eth_port_uc_addr_set(mp, dev->dev_addr);
1493 * mv643xx_eth_set_mac_address
1495 * Change the interface's mac address.
1496 * No special hardware thing should be done because interface is always
1497 * put in promiscuous mode.
1499 * Input : pointer to ethernet interface network device structure and
1500 * a pointer to the designated entry to be added to the cache.
1501 * Output : zero upon success, negative upon failure
1503 static int mv643xx_eth_set_mac_address(struct net_device *dev, void *addr)
1507 for (i = 0; i < 6; i++)
1508 /* +2 is for the offset of the HW addr type */
1509 dev->dev_addr[i] = ((unsigned char *)addr)[i + 2];
1510 mv643xx_eth_update_mac_address(dev);
1515 * eth_port_mc_addr - Multicast address settings.
1517 * The MV device supports multicast using two tables:
1518 * 1) Special Multicast Table for MAC addresses of the form
1519 * 0x01-00-5E-00-00-XX (where XX is between 0x00 and 0x_FF).
1520 * The MAC DA[7:0] bits are used as a pointer to the Special Multicast
1521 * Table entries in the DA-Filter table.
1522 * 2) Other Multicast Table for multicast of another type. A CRC-8bit
1523 * is used as an index to the Other Multicast Table entries in the
1524 * DA-Filter table. This function calculates the CRC-8bit value.
1525 * In either case, eth_port_set_filter_table_entry() is then called
1526 * to set to set the actual table entry.
1528 static void eth_port_mc_addr(struct mv643xx_private *mp, unsigned char *p_addr)
1530 unsigned int port_num = mp->port_num;
1533 unsigned char crc_result = 0;
1539 if ((p_addr[0] == 0x01) && (p_addr[1] == 0x00) &&
1540 (p_addr[2] == 0x5E) && (p_addr[3] == 0x00) && (p_addr[4] == 0x00)) {
1541 table = SPECIAL_MCAST_TABLE(port_num);
1542 eth_port_set_filter_table_entry(mp, table, p_addr[5]);
1546 /* Calculate CRC-8 out of the given address */
1547 mac_h = (p_addr[0] << 8) | (p_addr[1]);
1548 mac_l = (p_addr[2] << 24) | (p_addr[3] << 16) |
1549 (p_addr[4] << 8) | (p_addr[5] << 0);
1551 for (i = 0; i < 32; i++)
1552 mac_array[i] = (mac_l >> i) & 0x1;
1553 for (i = 32; i < 48; i++)
1554 mac_array[i] = (mac_h >> (i - 32)) & 0x1;
1556 crc[0] = mac_array[45] ^ mac_array[43] ^ mac_array[40] ^ mac_array[39] ^
1557 mac_array[35] ^ mac_array[34] ^ mac_array[31] ^ mac_array[30] ^
1558 mac_array[28] ^ mac_array[23] ^ mac_array[21] ^ mac_array[19] ^
1559 mac_array[18] ^ mac_array[16] ^ mac_array[14] ^ mac_array[12] ^
1560 mac_array[8] ^ mac_array[7] ^ mac_array[6] ^ mac_array[0];
1562 crc[1] = mac_array[46] ^ mac_array[45] ^ mac_array[44] ^ mac_array[43] ^
1563 mac_array[41] ^ mac_array[39] ^ mac_array[36] ^ mac_array[34] ^
1564 mac_array[32] ^ mac_array[30] ^ mac_array[29] ^ mac_array[28] ^
1565 mac_array[24] ^ mac_array[23] ^ mac_array[22] ^ mac_array[21] ^
1566 mac_array[20] ^ mac_array[18] ^ mac_array[17] ^ mac_array[16] ^
1567 mac_array[15] ^ mac_array[14] ^ mac_array[13] ^ mac_array[12] ^
1568 mac_array[9] ^ mac_array[6] ^ mac_array[1] ^ mac_array[0];
1570 crc[2] = mac_array[47] ^ mac_array[46] ^ mac_array[44] ^ mac_array[43] ^
1571 mac_array[42] ^ mac_array[39] ^ mac_array[37] ^ mac_array[34] ^
1572 mac_array[33] ^ mac_array[29] ^ mac_array[28] ^ mac_array[25] ^
1573 mac_array[24] ^ mac_array[22] ^ mac_array[17] ^ mac_array[15] ^
1574 mac_array[13] ^ mac_array[12] ^ mac_array[10] ^ mac_array[8] ^
1575 mac_array[6] ^ mac_array[2] ^ mac_array[1] ^ mac_array[0];
1577 crc[3] = mac_array[47] ^ mac_array[45] ^ mac_array[44] ^ mac_array[43] ^
1578 mac_array[40] ^ mac_array[38] ^ mac_array[35] ^ mac_array[34] ^
1579 mac_array[30] ^ mac_array[29] ^ mac_array[26] ^ mac_array[25] ^
1580 mac_array[23] ^ mac_array[18] ^ mac_array[16] ^ mac_array[14] ^
1581 mac_array[13] ^ mac_array[11] ^ mac_array[9] ^ mac_array[7] ^
1582 mac_array[3] ^ mac_array[2] ^ mac_array[1];
1584 crc[4] = mac_array[46] ^ mac_array[45] ^ mac_array[44] ^ mac_array[41] ^
1585 mac_array[39] ^ mac_array[36] ^ mac_array[35] ^ mac_array[31] ^
1586 mac_array[30] ^ mac_array[27] ^ mac_array[26] ^ mac_array[24] ^
1587 mac_array[19] ^ mac_array[17] ^ mac_array[15] ^ mac_array[14] ^
1588 mac_array[12] ^ mac_array[10] ^ mac_array[8] ^ mac_array[4] ^
1589 mac_array[3] ^ mac_array[2];
1591 crc[5] = mac_array[47] ^ mac_array[46] ^ mac_array[45] ^ mac_array[42] ^
1592 mac_array[40] ^ mac_array[37] ^ mac_array[36] ^ mac_array[32] ^
1593 mac_array[31] ^ mac_array[28] ^ mac_array[27] ^ mac_array[25] ^
1594 mac_array[20] ^ mac_array[18] ^ mac_array[16] ^ mac_array[15] ^
1595 mac_array[13] ^ mac_array[11] ^ mac_array[9] ^ mac_array[5] ^
1596 mac_array[4] ^ mac_array[3];
1598 crc[6] = mac_array[47] ^ mac_array[46] ^ mac_array[43] ^ mac_array[41] ^
1599 mac_array[38] ^ mac_array[37] ^ mac_array[33] ^ mac_array[32] ^
1600 mac_array[29] ^ mac_array[28] ^ mac_array[26] ^ mac_array[21] ^
1601 mac_array[19] ^ mac_array[17] ^ mac_array[16] ^ mac_array[14] ^
1602 mac_array[12] ^ mac_array[10] ^ mac_array[6] ^ mac_array[5] ^
1605 crc[7] = mac_array[47] ^ mac_array[44] ^ mac_array[42] ^ mac_array[39] ^
1606 mac_array[38] ^ mac_array[34] ^ mac_array[33] ^ mac_array[30] ^
1607 mac_array[29] ^ mac_array[27] ^ mac_array[22] ^ mac_array[20] ^
1608 mac_array[18] ^ mac_array[17] ^ mac_array[15] ^ mac_array[13] ^
1609 mac_array[11] ^ mac_array[7] ^ mac_array[6] ^ mac_array[5];
1611 for (i = 0; i < 8; i++)
1612 crc_result = crc_result | (crc[i] << i);
1614 table = OTHER_MCAST_TABLE(port_num);
1615 eth_port_set_filter_table_entry(mp, table, crc_result);
1619 * Set the entire multicast list based on dev->mc_list.
1621 static void eth_port_set_multicast_list(struct net_device *dev)
1624 struct dev_mc_list *mc_list;
1627 struct mv643xx_private *mp = netdev_priv(dev);
1628 unsigned int eth_port_num = mp->port_num;
1630 /* If the device is in promiscuous mode or in all multicast mode,
1631 * we will fully populate both multicast tables with accept.
1632 * This is guaranteed to yield a match on all multicast addresses...
1634 if ((dev->flags & IFF_PROMISC) || (dev->flags & IFF_ALLMULTI)) {
1635 for (table_index = 0; table_index <= 0xFC; table_index += 4) {
1636 /* Set all entries in DA filter special multicast
1638 * Set for ETH_Q0 for now
1640 * 0 Accept=1, Drop=0
1641 * 3-1 Queue ETH_Q0=0
1644 wrl(mp, SPECIAL_MCAST_TABLE(eth_port_num) + table_index, 0x01010101);
1646 /* Set all entries in DA filter other multicast
1648 * Set for ETH_Q0 for now
1650 * 0 Accept=1, Drop=0
1651 * 3-1 Queue ETH_Q0=0
1654 wrl(mp, OTHER_MCAST_TABLE(eth_port_num) + table_index, 0x01010101);
1659 /* We will clear out multicast tables every time we get the list.
1660 * Then add the entire new list...
1662 for (table_index = 0; table_index <= 0xFC; table_index += 4) {
1663 /* Clear DA filter special multicast table (Ex_dFSMT) */
1664 wrl(mp, SPECIAL_MCAST_TABLE(eth_port_num) + table_index, 0);
1666 /* Clear DA filter other multicast table (Ex_dFOMT) */
1667 wrl(mp, OTHER_MCAST_TABLE(eth_port_num) + table_index, 0);
1670 /* Get pointer to net_device multicast list and add each one... */
1671 for (i = 0, mc_list = dev->mc_list;
1672 (i < 256) && (mc_list != NULL) && (i < dev->mc_count);
1673 i++, mc_list = mc_list->next)
1674 if (mc_list->dmi_addrlen == 6)
1675 eth_port_mc_addr(mp, mc_list->dmi_addr);
1679 * mv643xx_eth_set_rx_mode
1681 * Change from promiscuos to regular rx mode
1683 * Input : pointer to ethernet interface network device structure
1686 static void mv643xx_eth_set_rx_mode(struct net_device *dev)
1688 struct mv643xx_private *mp = netdev_priv(dev);
1691 config_reg = rdl(mp, PORT_CONFIG(mp->port_num));
1692 if (dev->flags & IFF_PROMISC)
1693 config_reg |= UNICAST_PROMISCUOUS_MODE;
1695 config_reg &= ~UNICAST_PROMISCUOUS_MODE;
1696 wrl(mp, PORT_CONFIG(mp->port_num), config_reg);
1698 eth_port_set_multicast_list(dev);
1702 /* rx/tx queue initialisation ***********************************************/
1704 * ether_init_rx_desc_ring - Curve a Rx chain desc list and buffer in memory.
1707 * This function prepares a Rx chained list of descriptors and packet
1708 * buffers in a form of a ring. The routine must be called after port
1709 * initialization routine and before port start routine.
1710 * The Ethernet SDMA engine uses CPU bus addresses to access the various
1711 * devices in the system (i.e. DRAM). This function uses the ethernet
1712 * struct 'virtual to physical' routine (set by the user) to set the ring
1713 * with physical addresses.
1716 * struct mv643xx_private *mp Ethernet Port Control srtuct.
1719 * The routine updates the Ethernet port control struct with information
1720 * regarding the Rx descriptors and buffers.
1725 static void ether_init_rx_desc_ring(struct mv643xx_private *mp)
1727 volatile struct eth_rx_desc *p_rx_desc;
1728 int rx_desc_num = mp->rx_ring_size;
1731 /* initialize the next_desc_ptr links in the Rx descriptors ring */
1732 p_rx_desc = (struct eth_rx_desc *)mp->p_rx_desc_area;
1733 for (i = 0; i < rx_desc_num; i++) {
1734 p_rx_desc[i].next_desc_ptr = mp->rx_desc_dma +
1735 ((i + 1) % rx_desc_num) * sizeof(struct eth_rx_desc);
1738 /* Save Rx desc pointer to driver struct. */
1739 mp->rx_curr_desc_q = 0;
1740 mp->rx_used_desc_q = 0;
1742 mp->rx_desc_area_size = rx_desc_num * sizeof(struct eth_rx_desc);
1745 static void mv643xx_eth_free_rx_rings(struct net_device *dev)
1747 struct mv643xx_private *mp = netdev_priv(dev);
1750 /* Stop RX Queues */
1751 mv643xx_eth_port_disable_rx(mp);
1753 /* Free preallocated skb's on RX rings */
1754 for (curr = 0; mp->rx_desc_count && curr < mp->rx_ring_size; curr++) {
1755 if (mp->rx_skb[curr]) {
1756 dev_kfree_skb(mp->rx_skb[curr]);
1757 mp->rx_desc_count--;
1761 if (mp->rx_desc_count)
1763 "%s: Error in freeing Rx Ring. %d skb's still"
1764 " stuck in RX Ring - ignoring them\n", dev->name,
1767 if (mp->rx_sram_size)
1768 iounmap(mp->p_rx_desc_area);
1770 dma_free_coherent(NULL, mp->rx_desc_area_size,
1771 mp->p_rx_desc_area, mp->rx_desc_dma);
1775 * ether_init_tx_desc_ring - Curve a Tx chain desc list and buffer in memory.
1778 * This function prepares a Tx chained list of descriptors and packet
1779 * buffers in a form of a ring. The routine must be called after port
1780 * initialization routine and before port start routine.
1781 * The Ethernet SDMA engine uses CPU bus addresses to access the various
1782 * devices in the system (i.e. DRAM). This function uses the ethernet
1783 * struct 'virtual to physical' routine (set by the user) to set the ring
1784 * with physical addresses.
1787 * struct mv643xx_private *mp Ethernet Port Control srtuct.
1790 * The routine updates the Ethernet port control struct with information
1791 * regarding the Tx descriptors and buffers.
1796 static void ether_init_tx_desc_ring(struct mv643xx_private *mp)
1798 int tx_desc_num = mp->tx_ring_size;
1799 struct eth_tx_desc *p_tx_desc;
1802 /* Initialize the next_desc_ptr links in the Tx descriptors ring */
1803 p_tx_desc = (struct eth_tx_desc *)mp->p_tx_desc_area;
1804 for (i = 0; i < tx_desc_num; i++) {
1805 p_tx_desc[i].next_desc_ptr = mp->tx_desc_dma +
1806 ((i + 1) % tx_desc_num) * sizeof(struct eth_tx_desc);
1809 mp->tx_curr_desc_q = 0;
1810 mp->tx_used_desc_q = 0;
1812 mp->tx_desc_area_size = tx_desc_num * sizeof(struct eth_tx_desc);
1816 * mv643xx_eth_free_tx_descs - Free the tx desc data for completed descriptors
1818 * If force is non-zero, frees uncompleted descriptors as well
1820 static int mv643xx_eth_free_tx_descs(struct net_device *dev, int force)
1822 struct mv643xx_private *mp = netdev_priv(dev);
1823 struct eth_tx_desc *desc;
1825 struct sk_buff *skb;
1826 unsigned long flags;
1832 while (mp->tx_desc_count > 0) {
1833 spin_lock_irqsave(&mp->lock, flags);
1835 /* tx_desc_count might have changed before acquiring the lock */
1836 if (mp->tx_desc_count <= 0) {
1837 spin_unlock_irqrestore(&mp->lock, flags);
1841 tx_index = mp->tx_used_desc_q;
1842 desc = &mp->p_tx_desc_area[tx_index];
1843 cmd_sts = desc->cmd_sts;
1845 if (!force && (cmd_sts & ETH_BUFFER_OWNED_BY_DMA)) {
1846 spin_unlock_irqrestore(&mp->lock, flags);
1850 mp->tx_used_desc_q = (tx_index + 1) % mp->tx_ring_size;
1851 mp->tx_desc_count--;
1853 addr = desc->buf_ptr;
1854 count = desc->byte_cnt;
1855 skb = mp->tx_skb[tx_index];
1857 mp->tx_skb[tx_index] = NULL;
1859 if (cmd_sts & ETH_ERROR_SUMMARY) {
1860 printk("%s: Error in TX\n", dev->name);
1861 dev->stats.tx_errors++;
1864 spin_unlock_irqrestore(&mp->lock, flags);
1866 if (cmd_sts & ETH_TX_FIRST_DESC)
1867 dma_unmap_single(NULL, addr, count, DMA_TO_DEVICE);
1869 dma_unmap_page(NULL, addr, count, DMA_TO_DEVICE);
1872 dev_kfree_skb_irq(skb);
1880 static void mv643xx_eth_free_completed_tx_descs(struct net_device *dev)
1882 struct mv643xx_private *mp = netdev_priv(dev);
1884 if (mv643xx_eth_free_tx_descs(dev, 0) &&
1885 mp->tx_ring_size - mp->tx_desc_count >= MAX_DESCS_PER_SKB)
1886 netif_wake_queue(dev);
1889 static void mv643xx_eth_free_all_tx_descs(struct net_device *dev)
1891 mv643xx_eth_free_tx_descs(dev, 1);
1894 static void mv643xx_eth_free_tx_rings(struct net_device *dev)
1896 struct mv643xx_private *mp = netdev_priv(dev);
1898 /* Stop Tx Queues */
1899 mv643xx_eth_port_disable_tx(mp);
1901 /* Free outstanding skb's on TX ring */
1902 mv643xx_eth_free_all_tx_descs(dev);
1904 BUG_ON(mp->tx_used_desc_q != mp->tx_curr_desc_q);
1907 if (mp->tx_sram_size)
1908 iounmap(mp->p_tx_desc_area);
1910 dma_free_coherent(NULL, mp->tx_desc_area_size,
1911 mp->p_tx_desc_area, mp->tx_desc_dma);
1915 /* netdev ops and related ***************************************************/
1916 static void eth_port_reset(struct mv643xx_private *mp);
1918 /* Set the mv643xx port configuration register for the speed/duplex mode. */
1919 static void mv643xx_eth_update_pscr(struct net_device *dev,
1920 struct ethtool_cmd *ecmd)
1922 struct mv643xx_private *mp = netdev_priv(dev);
1923 int port_num = mp->port_num;
1925 unsigned int queues;
1927 o_pscr = rdl(mp, PORT_SERIAL_CONTROL(port_num));
1930 /* clear speed, duplex and rx buffer size fields */
1931 n_pscr &= ~(SET_MII_SPEED_TO_100 |
1932 SET_GMII_SPEED_TO_1000 |
1933 SET_FULL_DUPLEX_MODE |
1934 MAX_RX_PACKET_MASK);
1936 if (ecmd->duplex == DUPLEX_FULL)
1937 n_pscr |= SET_FULL_DUPLEX_MODE;
1939 if (ecmd->speed == SPEED_1000)
1940 n_pscr |= SET_GMII_SPEED_TO_1000 |
1941 MAX_RX_PACKET_9700BYTE;
1943 if (ecmd->speed == SPEED_100)
1944 n_pscr |= SET_MII_SPEED_TO_100;
1945 n_pscr |= MAX_RX_PACKET_1522BYTE;
1948 if (n_pscr != o_pscr) {
1949 if ((o_pscr & SERIAL_PORT_ENABLE) == 0)
1950 wrl(mp, PORT_SERIAL_CONTROL(port_num), n_pscr);
1952 queues = mv643xx_eth_port_disable_tx(mp);
1954 o_pscr &= ~SERIAL_PORT_ENABLE;
1955 wrl(mp, PORT_SERIAL_CONTROL(port_num), o_pscr);
1956 wrl(mp, PORT_SERIAL_CONTROL(port_num), n_pscr);
1957 wrl(mp, PORT_SERIAL_CONTROL(port_num), n_pscr);
1959 mv643xx_eth_port_enable_tx(mp, queues);
1965 * mv643xx_eth_int_handler
1967 * Main interrupt handler for the gigbit ethernet ports
1969 * Input : irq - irq number (not used)
1970 * dev_id - a pointer to the required interface's data structure
1975 static irqreturn_t mv643xx_eth_int_handler(int irq, void *dev_id)
1977 struct net_device *dev = (struct net_device *)dev_id;
1978 struct mv643xx_private *mp = netdev_priv(dev);
1979 u32 eth_int_cause, eth_int_cause_ext = 0;
1980 unsigned int port_num = mp->port_num;
1982 /* Read interrupt cause registers */
1983 eth_int_cause = rdl(mp, INT_CAUSE(port_num)) & ETH_INT_UNMASK_ALL;
1984 if (eth_int_cause & ETH_INT_CAUSE_EXT) {
1985 eth_int_cause_ext = rdl(mp, INT_CAUSE_EXT(port_num))
1986 & ETH_INT_UNMASK_ALL_EXT;
1987 wrl(mp, INT_CAUSE_EXT(port_num), ~eth_int_cause_ext);
1990 /* PHY status changed */
1991 if (eth_int_cause_ext & (ETH_INT_CAUSE_PHY | ETH_INT_CAUSE_STATE)) {
1992 struct ethtool_cmd cmd;
1994 if (mii_link_ok(&mp->mii)) {
1995 mii_ethtool_gset(&mp->mii, &cmd);
1996 mv643xx_eth_update_pscr(dev, &cmd);
1997 mv643xx_eth_port_enable_tx(mp, ETH_TX_QUEUES_ENABLED);
1998 if (!netif_carrier_ok(dev)) {
1999 netif_carrier_on(dev);
2000 if (mp->tx_ring_size - mp->tx_desc_count >=
2002 netif_wake_queue(dev);
2004 } else if (netif_carrier_ok(dev)) {
2005 netif_stop_queue(dev);
2006 netif_carrier_off(dev);
2011 if (eth_int_cause & ETH_INT_CAUSE_RX) {
2012 /* schedule the NAPI poll routine to maintain port */
2013 wrl(mp, INT_MASK(port_num), ETH_INT_MASK_ALL);
2015 /* wait for previous write to complete */
2016 rdl(mp, INT_MASK(port_num));
2018 netif_rx_schedule(dev, &mp->napi);
2021 if (eth_int_cause & ETH_INT_CAUSE_RX)
2022 mv643xx_eth_receive_queue(dev, INT_MAX);
2024 if (eth_int_cause_ext & ETH_INT_CAUSE_TX)
2025 mv643xx_eth_free_completed_tx_descs(dev);
2028 * If no real interrupt occured, exit.
2029 * This can happen when using gigE interrupt coalescing mechanism.
2031 if ((eth_int_cause == 0x0) && (eth_int_cause_ext == 0x0))
2038 * ethernet_phy_reset - Reset Ethernet port PHY.
2041 * This routine utilizes the SMI interface to reset the ethernet port PHY.
2044 * struct mv643xx_private *mp Ethernet Port.
2053 static void ethernet_phy_reset(struct mv643xx_private *mp)
2055 unsigned int phy_reg_data;
2058 eth_port_read_smi_reg(mp, 0, &phy_reg_data);
2059 phy_reg_data |= 0x8000; /* Set bit 15 to reset the PHY */
2060 eth_port_write_smi_reg(mp, 0, phy_reg_data);
2062 /* wait for PHY to come out of reset */
2065 eth_port_read_smi_reg(mp, 0, &phy_reg_data);
2066 } while (phy_reg_data & 0x8000);
2070 * eth_port_start - Start the Ethernet port activity.
2073 * This routine prepares the Ethernet port for Rx and Tx activity:
2074 * 1. Initialize Tx and Rx Current Descriptor Pointer for each queue that
2075 * has been initialized a descriptor's ring (using
2076 * ether_init_tx_desc_ring for Tx and ether_init_rx_desc_ring for Rx)
2077 * 2. Initialize and enable the Ethernet configuration port by writing to
2078 * the port's configuration and command registers.
2079 * 3. Initialize and enable the SDMA by writing to the SDMA's
2080 * configuration and command registers. After completing these steps,
2081 * the ethernet port SDMA can starts to perform Rx and Tx activities.
2083 * Note: Each Rx and Tx queue descriptor's list must be initialized prior
2084 * to calling this function (use ether_init_tx_desc_ring for Tx queues
2085 * and ether_init_rx_desc_ring for Rx queues).
2088 * dev - a pointer to the required interface
2091 * Ethernet port is ready to receive and transmit.
2096 static void eth_port_start(struct net_device *dev)
2098 struct mv643xx_private *mp = netdev_priv(dev);
2099 unsigned int port_num = mp->port_num;
2100 int tx_curr_desc, rx_curr_desc;
2102 struct ethtool_cmd ethtool_cmd;
2104 /* Assignment of Tx CTRP of given queue */
2105 tx_curr_desc = mp->tx_curr_desc_q;
2106 wrl(mp, TXQ_CURRENT_DESC_PTR(port_num),
2107 (u32)((struct eth_tx_desc *)mp->tx_desc_dma + tx_curr_desc));
2109 /* Assignment of Rx CRDP of given queue */
2110 rx_curr_desc = mp->rx_curr_desc_q;
2111 wrl(mp, RXQ_CURRENT_DESC_PTR(port_num),
2112 (u32)((struct eth_rx_desc *)mp->rx_desc_dma + rx_curr_desc));
2114 /* Add the assigned Ethernet address to the port's address table */
2115 eth_port_uc_addr_set(mp, dev->dev_addr);
2118 * Receive all unmatched unicast, TCP, UDP, BPDU and broadcast
2119 * frames to RX queue #0.
2121 wrl(mp, PORT_CONFIG(port_num), 0x00000000);
2124 * Treat BPDUs as normal multicasts, and disable partition mode.
2126 wrl(mp, PORT_CONFIG_EXT(port_num), 0x00000000);
2128 pscr = rdl(mp, PORT_SERIAL_CONTROL(port_num));
2130 pscr &= ~(SERIAL_PORT_ENABLE | FORCE_LINK_PASS);
2131 wrl(mp, PORT_SERIAL_CONTROL(port_num), pscr);
2133 pscr |= DISABLE_AUTO_NEG_FOR_FLOW_CTRL |
2134 DISABLE_AUTO_NEG_SPEED_GMII |
2135 DISABLE_AUTO_NEG_FOR_DUPLEX |
2136 DO_NOT_FORCE_LINK_FAIL |
2137 SERIAL_PORT_CONTROL_RESERVED;
2139 wrl(mp, PORT_SERIAL_CONTROL(port_num), pscr);
2141 pscr |= SERIAL_PORT_ENABLE;
2142 wrl(mp, PORT_SERIAL_CONTROL(port_num), pscr);
2144 /* Assign port SDMA configuration */
2145 wrl(mp, SDMA_CONFIG(port_num), PORT_SDMA_CONFIG_DEFAULT_VALUE);
2147 /* Enable port Rx. */
2148 mv643xx_eth_port_enable_rx(mp, ETH_RX_QUEUES_ENABLED);
2150 /* Disable port bandwidth limits by clearing MTU register */
2151 wrl(mp, TX_BW_MTU(port_num), 0);
2153 /* save phy settings across reset */
2154 mv643xx_get_settings(dev, ðtool_cmd);
2155 ethernet_phy_reset(mp);
2156 mv643xx_set_settings(dev, ðtool_cmd);
2162 * eth_port_set_rx_coal - Sets coalescing interrupt mechanism on RX path
2165 * This routine sets the RX coalescing interrupt mechanism parameter.
2166 * This parameter is a timeout counter, that counts in 64 t_clk
2167 * chunks ; that when timeout event occurs a maskable interrupt
2169 * The parameter is calculated using the tClk of the MV-643xx chip
2170 * , and the required delay of the interrupt in usec.
2173 * struct mv643xx_private *mp Ethernet port
2174 * unsigned int delay Delay in usec
2177 * Interrupt coalescing mechanism value is set in MV-643xx chip.
2180 * The interrupt coalescing value set in the gigE port.
2183 static unsigned int eth_port_set_rx_coal(struct mv643xx_private *mp,
2186 unsigned int port_num = mp->port_num;
2187 unsigned int coal = ((mp->shared->t_clk / 1000000) * delay) / 64;
2189 /* Set RX Coalescing mechanism */
2190 wrl(mp, SDMA_CONFIG(port_num),
2191 ((coal & 0x3fff) << 8) |
2192 (rdl(mp, SDMA_CONFIG(port_num))
2200 * eth_port_set_tx_coal - Sets coalescing interrupt mechanism on TX path
2203 * This routine sets the TX coalescing interrupt mechanism parameter.
2204 * This parameter is a timeout counter, that counts in 64 t_clk
2205 * chunks ; that when timeout event occurs a maskable interrupt
2207 * The parameter is calculated using the t_cLK frequency of the
2208 * MV-643xx chip and the required delay in the interrupt in uSec
2211 * struct mv643xx_private *mp Ethernet port
2212 * unsigned int delay Delay in uSeconds
2215 * Interrupt coalescing mechanism value is set in MV-643xx chip.
2218 * The interrupt coalescing value set in the gigE port.
2221 static unsigned int eth_port_set_tx_coal(struct mv643xx_private *mp,
2224 unsigned int coal = ((mp->shared->t_clk / 1000000) * delay) / 64;
2226 /* Set TX Coalescing mechanism */
2227 wrl(mp, TX_FIFO_URGENT_THRESHOLD(mp->port_num), coal << 4);
2233 * eth_port_init - Initialize the Ethernet port driver
2236 * This function prepares the ethernet port to start its activity:
2237 * 1) Completes the ethernet port driver struct initialization toward port
2239 * 2) Resets the device to a quiescent state in case of warm reboot.
2240 * 3) Enable SDMA access to all four DRAM banks as well as internal SRAM.
2241 * 4) Clean MAC tables. The reset status of those tables is unknown.
2242 * 5) Set PHY address.
2243 * Note: Call this routine prior to eth_port_start routine and after
2244 * setting user values in the user fields of Ethernet port control
2248 * struct mv643xx_private *mp Ethernet port control struct
2256 static void eth_port_init(struct mv643xx_private *mp)
2258 mp->rx_resource_err = 0;
2262 eth_port_init_mac_tables(mp);
2268 * This function is called when openning the network device. The function
2269 * should initialize all the hardware, initialize cyclic Rx/Tx
2270 * descriptors chain and buffers and allocate an IRQ to the network
2273 * Input : a pointer to the network device structure
2275 * Output : zero of success , nonzero if fails.
2278 static int mv643xx_eth_open(struct net_device *dev)
2280 struct mv643xx_private *mp = netdev_priv(dev);
2281 unsigned int port_num = mp->port_num;
2285 /* Clear any pending ethernet port interrupts */
2286 wrl(mp, INT_CAUSE(port_num), 0);
2287 wrl(mp, INT_CAUSE_EXT(port_num), 0);
2288 /* wait for previous write to complete */
2289 rdl(mp, INT_CAUSE_EXT(port_num));
2291 err = request_irq(dev->irq, mv643xx_eth_int_handler,
2292 IRQF_SHARED | IRQF_SAMPLE_RANDOM, dev->name, dev);
2294 printk(KERN_ERR "%s: Can not assign IRQ\n", dev->name);
2300 memset(&mp->timeout, 0, sizeof(struct timer_list));
2301 mp->timeout.function = mv643xx_eth_rx_refill_descs_timer_wrapper;
2302 mp->timeout.data = (unsigned long)dev;
2304 /* Allocate RX and TX skb rings */
2305 mp->rx_skb = kmalloc(sizeof(*mp->rx_skb) * mp->rx_ring_size,
2308 printk(KERN_ERR "%s: Cannot allocate Rx skb ring\n", dev->name);
2312 mp->tx_skb = kmalloc(sizeof(*mp->tx_skb) * mp->tx_ring_size,
2315 printk(KERN_ERR "%s: Cannot allocate Tx skb ring\n", dev->name);
2317 goto out_free_rx_skb;
2320 /* Allocate TX ring */
2321 mp->tx_desc_count = 0;
2322 size = mp->tx_ring_size * sizeof(struct eth_tx_desc);
2323 mp->tx_desc_area_size = size;
2325 if (mp->tx_sram_size) {
2326 mp->p_tx_desc_area = ioremap(mp->tx_sram_addr,
2328 mp->tx_desc_dma = mp->tx_sram_addr;
2330 mp->p_tx_desc_area = dma_alloc_coherent(NULL, size,
2334 if (!mp->p_tx_desc_area) {
2335 printk(KERN_ERR "%s: Cannot allocate Tx Ring (size %d bytes)\n",
2338 goto out_free_tx_skb;
2340 BUG_ON((u32) mp->p_tx_desc_area & 0xf); /* check 16-byte alignment */
2341 memset((void *)mp->p_tx_desc_area, 0, mp->tx_desc_area_size);
2343 ether_init_tx_desc_ring(mp);
2345 /* Allocate RX ring */
2346 mp->rx_desc_count = 0;
2347 size = mp->rx_ring_size * sizeof(struct eth_rx_desc);
2348 mp->rx_desc_area_size = size;
2350 if (mp->rx_sram_size) {
2351 mp->p_rx_desc_area = ioremap(mp->rx_sram_addr,
2353 mp->rx_desc_dma = mp->rx_sram_addr;
2355 mp->p_rx_desc_area = dma_alloc_coherent(NULL, size,
2359 if (!mp->p_rx_desc_area) {
2360 printk(KERN_ERR "%s: Cannot allocate Rx ring (size %d bytes)\n",
2362 printk(KERN_ERR "%s: Freeing previously allocated TX queues...",
2364 if (mp->rx_sram_size)
2365 iounmap(mp->p_tx_desc_area);
2367 dma_free_coherent(NULL, mp->tx_desc_area_size,
2368 mp->p_tx_desc_area, mp->tx_desc_dma);
2370 goto out_free_tx_skb;
2372 memset((void *)mp->p_rx_desc_area, 0, size);
2374 ether_init_rx_desc_ring(mp);
2376 mv643xx_eth_rx_refill_descs(dev); /* Fill RX ring with skb's */
2379 napi_enable(&mp->napi);
2382 eth_port_start(dev);
2384 /* Interrupt Coalescing */
2388 eth_port_set_rx_coal(mp, MV643XX_RX_COAL);
2392 eth_port_set_tx_coal(mp, MV643XX_TX_COAL);
2394 /* Unmask phy and link status changes interrupts */
2395 wrl(mp, INT_MASK_EXT(port_num), ETH_INT_UNMASK_ALL_EXT);
2397 /* Unmask RX buffer and TX end interrupt */
2398 wrl(mp, INT_MASK(port_num), ETH_INT_UNMASK_ALL);
2407 free_irq(dev->irq, dev);
2413 * eth_port_reset - Reset Ethernet port
2416 * This routine resets the chip by aborting any SDMA engine activity and
2417 * clearing the MIB counters. The Receiver and the Transmit unit are in
2418 * idle state after this command is performed and the port is disabled.
2421 * struct mv643xx_private *mp Ethernet Port.
2424 * Channel activity is halted.
2430 static void eth_port_reset(struct mv643xx_private *mp)
2432 unsigned int port_num = mp->port_num;
2433 unsigned int reg_data;
2435 mv643xx_eth_port_disable_tx(mp);
2436 mv643xx_eth_port_disable_rx(mp);
2438 /* Clear all MIB counters */
2439 eth_clear_mib_counters(mp);
2441 /* Reset the Enable bit in the Configuration Register */
2442 reg_data = rdl(mp, PORT_SERIAL_CONTROL(port_num));
2443 reg_data &= ~(SERIAL_PORT_ENABLE |
2444 DO_NOT_FORCE_LINK_FAIL |
2446 wrl(mp, PORT_SERIAL_CONTROL(port_num), reg_data);
2452 * This function is used when closing the network device.
2453 * It updates the hardware,
2454 * release all memory that holds buffers and descriptors and release the IRQ.
2455 * Input : a pointer to the device structure
2456 * Output : zero if success , nonzero if fails
2459 static int mv643xx_eth_stop(struct net_device *dev)
2461 struct mv643xx_private *mp = netdev_priv(dev);
2462 unsigned int port_num = mp->port_num;
2464 /* Mask all interrupts on ethernet port */
2465 wrl(mp, INT_MASK(port_num), ETH_INT_MASK_ALL);
2466 /* wait for previous write to complete */
2467 rdl(mp, INT_MASK(port_num));
2470 napi_disable(&mp->napi);
2472 netif_carrier_off(dev);
2473 netif_stop_queue(dev);
2477 mv643xx_eth_free_tx_rings(dev);
2478 mv643xx_eth_free_rx_rings(dev);
2480 free_irq(dev->irq, dev);
2485 static int mv643xx_eth_do_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
2487 struct mv643xx_private *mp = netdev_priv(dev);
2489 return generic_mii_ioctl(&mp->mii, if_mii(ifr), cmd, NULL);
2493 * Changes MTU (maximum transfer unit) of the gigabit ethenret port
2495 * Input : pointer to ethernet interface network device structure
2497 * Output : 0 upon success, -EINVAL upon failure
2499 static int mv643xx_eth_change_mtu(struct net_device *dev, int new_mtu)
2501 if ((new_mtu > 9500) || (new_mtu < 64))
2505 if (!netif_running(dev))
2509 * Stop and then re-open the interface. This will allocate RX
2510 * skbs of the new MTU.
2511 * There is a possible danger that the open will not succeed,
2512 * due to memory being full, which might fail the open function.
2514 mv643xx_eth_stop(dev);
2515 if (mv643xx_eth_open(dev)) {
2516 printk(KERN_ERR "%s: Fatal error on opening device\n",
2524 * mv643xx_eth_tx_timeout_task
2526 * Actual routine to reset the adapter when a timeout on Tx has occurred
2528 static void mv643xx_eth_tx_timeout_task(struct work_struct *ugly)
2530 struct mv643xx_private *mp = container_of(ugly, struct mv643xx_private,
2532 struct net_device *dev = mp->dev;
2534 if (!netif_running(dev))
2537 netif_stop_queue(dev);
2540 eth_port_start(dev);
2542 if (mp->tx_ring_size - mp->tx_desc_count >= MAX_DESCS_PER_SKB)
2543 netif_wake_queue(dev);
2547 * mv643xx_eth_tx_timeout
2549 * Called upon a timeout on transmitting a packet
2551 * Input : pointer to ethernet interface network device structure.
2554 static void mv643xx_eth_tx_timeout(struct net_device *dev)
2556 struct mv643xx_private *mp = netdev_priv(dev);
2558 printk(KERN_INFO "%s: TX timeout ", dev->name);
2560 /* Do the reset outside of interrupt context */
2561 schedule_work(&mp->tx_timeout_task);
2564 #ifdef CONFIG_NET_POLL_CONTROLLER
2565 static void mv643xx_netpoll(struct net_device *netdev)
2567 struct mv643xx_private *mp = netdev_priv(netdev);
2568 int port_num = mp->port_num;
2570 wrl(mp, INT_MASK(port_num), ETH_INT_MASK_ALL);
2571 /* wait for previous write to complete */
2572 rdl(mp, INT_MASK(port_num));
2574 mv643xx_eth_int_handler(netdev->irq, netdev);
2576 wrl(mp, INT_MASK(port_num), ETH_INT_UNMASK_ALL);
2581 * Wrappers for MII support library.
2583 static int mv643xx_mdio_read(struct net_device *dev, int phy_id, int location)
2585 struct mv643xx_private *mp = netdev_priv(dev);
2588 eth_port_read_smi_reg(mp, location, &val);
2592 static void mv643xx_mdio_write(struct net_device *dev, int phy_id, int location, int val)
2594 struct mv643xx_private *mp = netdev_priv(dev);
2595 eth_port_write_smi_reg(mp, location, val);
2599 /* platform glue ************************************************************/
2600 static void mv643xx_eth_conf_mbus_windows(struct mv643xx_shared_private *msp,
2601 struct mbus_dram_target_info *dram)
2603 void __iomem *base = msp->eth_base;
2608 for (i = 0; i < 6; i++) {
2609 writel(0, base + WINDOW_BASE(i));
2610 writel(0, base + WINDOW_SIZE(i));
2612 writel(0, base + WINDOW_REMAP_HIGH(i));
2618 for (i = 0; i < dram->num_cs; i++) {
2619 struct mbus_dram_window *cs = dram->cs + i;
2621 writel((cs->base & 0xffff0000) |
2622 (cs->mbus_attr << 8) |
2623 dram->mbus_dram_target_id, base + WINDOW_BASE(i));
2624 writel((cs->size - 1) & 0xffff0000, base + WINDOW_SIZE(i));
2626 win_enable &= ~(1 << i);
2627 win_protect |= 3 << (2 * i);
2630 writel(win_enable, base + WINDOW_BAR_ENABLE);
2631 msp->win_protect = win_protect;
2634 static int mv643xx_eth_shared_probe(struct platform_device *pdev)
2636 static int mv643xx_version_printed = 0;
2637 struct mv643xx_eth_shared_platform_data *pd = pdev->dev.platform_data;
2638 struct mv643xx_shared_private *msp;
2639 struct resource *res;
2642 if (!mv643xx_version_printed++)
2643 printk(KERN_NOTICE "MV-643xx 10/100/1000 Ethernet Driver\n");
2646 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2651 msp = kmalloc(sizeof(*msp), GFP_KERNEL);
2654 memset(msp, 0, sizeof(*msp));
2656 msp->eth_base = ioremap(res->start, res->end - res->start + 1);
2657 if (msp->eth_base == NULL)
2660 spin_lock_init(&msp->phy_lock);
2661 msp->t_clk = (pd != NULL && pd->t_clk != 0) ? pd->t_clk : 133000000;
2663 platform_set_drvdata(pdev, msp);
2666 * (Re-)program MBUS remapping windows if we are asked to.
2668 if (pd != NULL && pd->dram != NULL)
2669 mv643xx_eth_conf_mbus_windows(msp, pd->dram);
2679 static int mv643xx_eth_shared_remove(struct platform_device *pdev)
2681 struct mv643xx_shared_private *msp = platform_get_drvdata(pdev);
2683 iounmap(msp->eth_base);
2689 static struct platform_driver mv643xx_eth_shared_driver = {
2690 .probe = mv643xx_eth_shared_probe,
2691 .remove = mv643xx_eth_shared_remove,
2693 .name = MV643XX_ETH_SHARED_NAME,
2694 .owner = THIS_MODULE,
2699 * ethernet_phy_set - Set the ethernet port PHY address.
2702 * This routine sets the given ethernet port PHY address.
2705 * struct mv643xx_private *mp Ethernet Port.
2706 * int phy_addr PHY address.
2715 static void ethernet_phy_set(struct mv643xx_private *mp, int phy_addr)
2718 int addr_shift = 5 * mp->port_num;
2720 reg_data = rdl(mp, PHY_ADDR);
2721 reg_data &= ~(0x1f << addr_shift);
2722 reg_data |= (phy_addr & 0x1f) << addr_shift;
2723 wrl(mp, PHY_ADDR, reg_data);
2727 * ethernet_phy_get - Get the ethernet port PHY address.
2730 * This routine returns the given ethernet port PHY address.
2733 * struct mv643xx_private *mp Ethernet Port.
2742 static int ethernet_phy_get(struct mv643xx_private *mp)
2744 unsigned int reg_data;
2746 reg_data = rdl(mp, PHY_ADDR);
2748 return ((reg_data >> (5 * mp->port_num)) & 0x1f);
2752 * ethernet_phy_detect - Detect whether a phy is present
2755 * This function tests whether there is a PHY present on
2756 * the specified port.
2759 * struct mv643xx_private *mp Ethernet Port.
2766 * -ENODEV on failure
2769 static int ethernet_phy_detect(struct mv643xx_private *mp)
2771 unsigned int phy_reg_data0;
2774 eth_port_read_smi_reg(mp, 0, &phy_reg_data0);
2775 auto_neg = phy_reg_data0 & 0x1000;
2776 phy_reg_data0 ^= 0x1000; /* invert auto_neg */
2777 eth_port_write_smi_reg(mp, 0, phy_reg_data0);
2779 eth_port_read_smi_reg(mp, 0, &phy_reg_data0);
2780 if ((phy_reg_data0 & 0x1000) == auto_neg)
2781 return -ENODEV; /* change didn't take */
2783 phy_reg_data0 ^= 0x1000;
2784 eth_port_write_smi_reg(mp, 0, phy_reg_data0);
2788 static void mv643xx_init_ethtool_cmd(struct net_device *dev, int phy_address,
2789 int speed, int duplex,
2790 struct ethtool_cmd *cmd)
2792 struct mv643xx_private *mp = netdev_priv(dev);
2794 memset(cmd, 0, sizeof(*cmd));
2796 cmd->port = PORT_MII;
2797 cmd->transceiver = XCVR_INTERNAL;
2798 cmd->phy_address = phy_address;
2801 cmd->autoneg = AUTONEG_ENABLE;
2802 /* mii lib checks, but doesn't use speed on AUTONEG_ENABLE */
2803 cmd->speed = SPEED_100;
2804 cmd->advertising = ADVERTISED_10baseT_Half |
2805 ADVERTISED_10baseT_Full |
2806 ADVERTISED_100baseT_Half |
2807 ADVERTISED_100baseT_Full;
2808 if (mp->mii.supports_gmii)
2809 cmd->advertising |= ADVERTISED_1000baseT_Full;
2811 cmd->autoneg = AUTONEG_DISABLE;
2813 cmd->duplex = duplex;
2820 * First function called after registering the network device.
2821 * It's purpose is to initialize the device as an ethernet device,
2822 * fill the ethernet device structure with pointers * to functions,
2823 * and set the MAC address of the interface
2825 * Input : struct device *
2826 * Output : -ENOMEM if failed , 0 if success
2828 static int mv643xx_eth_probe(struct platform_device *pdev)
2830 struct mv643xx_eth_platform_data *pd;
2832 struct mv643xx_private *mp;
2833 struct net_device *dev;
2835 struct resource *res;
2837 struct ethtool_cmd cmd;
2838 int duplex = DUPLEX_HALF;
2839 int speed = 0; /* default to auto-negotiation */
2840 DECLARE_MAC_BUF(mac);
2842 pd = pdev->dev.platform_data;
2844 printk(KERN_ERR "No mv643xx_eth_platform_data\n");
2848 if (pd->shared == NULL) {
2849 printk(KERN_ERR "No mv643xx_eth_platform_data->shared\n");
2853 dev = alloc_etherdev(sizeof(struct mv643xx_private));
2857 platform_set_drvdata(pdev, dev);
2859 mp = netdev_priv(dev);
2862 netif_napi_add(dev, &mp->napi, mv643xx_poll, 64);
2865 res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
2867 dev->irq = res->start;
2869 dev->open = mv643xx_eth_open;
2870 dev->stop = mv643xx_eth_stop;
2871 dev->hard_start_xmit = mv643xx_eth_start_xmit;
2872 dev->set_mac_address = mv643xx_eth_set_mac_address;
2873 dev->set_multicast_list = mv643xx_eth_set_rx_mode;
2875 /* No need to Tx Timeout */
2876 dev->tx_timeout = mv643xx_eth_tx_timeout;
2878 #ifdef CONFIG_NET_POLL_CONTROLLER
2879 dev->poll_controller = mv643xx_netpoll;
2882 dev->watchdog_timeo = 2 * HZ;
2884 dev->change_mtu = mv643xx_eth_change_mtu;
2885 dev->do_ioctl = mv643xx_eth_do_ioctl;
2886 SET_ETHTOOL_OPS(dev, &mv643xx_ethtool_ops);
2888 #ifdef MV643XX_CHECKSUM_OFFLOAD_TX
2889 #ifdef MAX_SKB_FRAGS
2891 * Zero copy can only work if we use Discovery II memory. Else, we will
2892 * have to map the buffers to ISA memory which is only 16 MB
2894 dev->features = NETIF_F_SG | NETIF_F_IP_CSUM;
2898 /* Configure the timeout task */
2899 INIT_WORK(&mp->tx_timeout_task, mv643xx_eth_tx_timeout_task);
2901 spin_lock_init(&mp->lock);
2903 mp->shared = platform_get_drvdata(pd->shared);
2904 port_num = mp->port_num = pd->port_number;
2906 if (mp->shared->win_protect)
2907 wrl(mp, WINDOW_PROTECT(port_num), mp->shared->win_protect);
2909 mp->shared_smi = mp->shared;
2910 if (pd->shared_smi != NULL)
2911 mp->shared_smi = platform_get_drvdata(pd->shared_smi);
2913 /* set default config values */
2914 eth_port_uc_addr_get(mp, dev->dev_addr);
2915 mp->rx_ring_size = PORT_DEFAULT_RECEIVE_QUEUE_SIZE;
2916 mp->tx_ring_size = PORT_DEFAULT_TRANSMIT_QUEUE_SIZE;
2918 if (is_valid_ether_addr(pd->mac_addr))
2919 memcpy(dev->dev_addr, pd->mac_addr, 6);
2921 if (pd->phy_addr || pd->force_phy_addr)
2922 ethernet_phy_set(mp, pd->phy_addr);
2924 if (pd->rx_queue_size)
2925 mp->rx_ring_size = pd->rx_queue_size;
2927 if (pd->tx_queue_size)
2928 mp->tx_ring_size = pd->tx_queue_size;
2930 if (pd->tx_sram_size) {
2931 mp->tx_sram_size = pd->tx_sram_size;
2932 mp->tx_sram_addr = pd->tx_sram_addr;
2935 if (pd->rx_sram_size) {
2936 mp->rx_sram_size = pd->rx_sram_size;
2937 mp->rx_sram_addr = pd->rx_sram_addr;
2940 duplex = pd->duplex;
2943 /* Hook up MII support for ethtool */
2945 mp->mii.mdio_read = mv643xx_mdio_read;
2946 mp->mii.mdio_write = mv643xx_mdio_write;
2947 mp->mii.phy_id = ethernet_phy_get(mp);
2948 mp->mii.phy_id_mask = 0x3f;
2949 mp->mii.reg_num_mask = 0x1f;
2951 err = ethernet_phy_detect(mp);
2953 pr_debug("%s: No PHY detected at addr %d\n",
2954 dev->name, ethernet_phy_get(mp));
2958 ethernet_phy_reset(mp);
2959 mp->mii.supports_gmii = mii_check_gmii_support(&mp->mii);
2960 mv643xx_init_ethtool_cmd(dev, mp->mii.phy_id, speed, duplex, &cmd);
2961 mv643xx_eth_update_pscr(dev, &cmd);
2962 mv643xx_set_settings(dev, &cmd);
2964 SET_NETDEV_DEV(dev, &pdev->dev);
2965 err = register_netdev(dev);
2971 "%s: port %d with MAC address %s\n",
2972 dev->name, port_num, print_mac(mac, p));
2974 if (dev->features & NETIF_F_SG)
2975 printk(KERN_NOTICE "%s: Scatter Gather Enabled\n", dev->name);
2977 if (dev->features & NETIF_F_IP_CSUM)
2978 printk(KERN_NOTICE "%s: TX TCP/IP Checksumming Supported\n",
2981 #ifdef MV643XX_CHECKSUM_OFFLOAD_TX
2982 printk(KERN_NOTICE "%s: RX TCP/UDP Checksum Offload ON \n", dev->name);
2986 printk(KERN_NOTICE "%s: TX and RX Interrupt Coalescing ON \n",
2991 printk(KERN_NOTICE "%s: RX NAPI Enabled \n", dev->name);
2994 if (mp->tx_sram_size > 0)
2995 printk(KERN_NOTICE "%s: Using SRAM\n", dev->name);
3005 static int mv643xx_eth_remove(struct platform_device *pdev)
3007 struct net_device *dev = platform_get_drvdata(pdev);
3009 unregister_netdev(dev);
3010 flush_scheduled_work();
3013 platform_set_drvdata(pdev, NULL);
3017 static void mv643xx_eth_shutdown(struct platform_device *pdev)
3019 struct net_device *dev = platform_get_drvdata(pdev);
3020 struct mv643xx_private *mp = netdev_priv(dev);
3021 unsigned int port_num = mp->port_num;
3023 /* Mask all interrupts on ethernet port */
3024 wrl(mp, INT_MASK(port_num), 0);
3025 rdl(mp, INT_MASK(port_num));
3030 static struct platform_driver mv643xx_eth_driver = {
3031 .probe = mv643xx_eth_probe,
3032 .remove = mv643xx_eth_remove,
3033 .shutdown = mv643xx_eth_shutdown,
3035 .name = MV643XX_ETH_NAME,
3036 .owner = THIS_MODULE,
3041 * mv643xx_init_module
3043 * Registers the network drivers into the Linux kernel
3049 static int __init mv643xx_init_module(void)
3053 rc = platform_driver_register(&mv643xx_eth_shared_driver);
3055 rc = platform_driver_register(&mv643xx_eth_driver);
3057 platform_driver_unregister(&mv643xx_eth_shared_driver);
3063 * mv643xx_cleanup_module
3065 * Registers the network drivers into the Linux kernel
3071 static void __exit mv643xx_cleanup_module(void)
3073 platform_driver_unregister(&mv643xx_eth_driver);
3074 platform_driver_unregister(&mv643xx_eth_shared_driver);
3077 module_init(mv643xx_init_module);
3078 module_exit(mv643xx_cleanup_module);
3080 MODULE_LICENSE("GPL");
3081 MODULE_AUTHOR( "Rabeeh Khoury, Assaf Hoffman, Matthew Dharm, Manish Lachwani"
3082 " and Dale Farnsworth");
3083 MODULE_DESCRIPTION("Ethernet driver for Marvell MV643XX");
3084 MODULE_ALIAS("platform:" MV643XX_ETH_NAME);
3085 MODULE_ALIAS("platform:" MV643XX_ETH_SHARED_NAME);