2 * Driver for Marvell Discovery (MV643XX) and Marvell Orion ethernet ports
3 * Copyright (C) 2002 Matthew Dharm <mdharm@momenco.com>
5 * Based on the 64360 driver from:
6 * Copyright (C) 2002 Rabeeh Khoury <rabeeh@galileo.co.il>
7 * Rabeeh Khoury <rabeeh@marvell.com>
9 * Copyright (C) 2003 PMC-Sierra, Inc.,
10 * written by Manish Lachwani
12 * Copyright (C) 2003 Ralf Baechle <ralf@linux-mips.org>
14 * Copyright (C) 2004-2006 MontaVista Software, Inc.
15 * Dale Farnsworth <dale@farnsworth.org>
17 * Copyright (C) 2004 Steven J. Hill <sjhill1@rockwellcollins.com>
18 * <sjhill@realitydiluted.com>
20 * Copyright (C) 2007-2008 Marvell Semiconductor
21 * Lennert Buytenhek <buytenh@marvell.com>
23 * This program is free software; you can redistribute it and/or
24 * modify it under the terms of the GNU General Public License
25 * as published by the Free Software Foundation; either version 2
26 * of the License, or (at your option) any later version.
28 * This program is distributed in the hope that it will be useful,
29 * but WITHOUT ANY WARRANTY; without even the implied warranty of
30 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
31 * GNU General Public License for more details.
33 * You should have received a copy of the GNU General Public License
34 * along with this program; if not, write to the Free Software
35 * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
38 #include <linux/init.h>
39 #include <linux/dma-mapping.h>
41 #include <linux/tcp.h>
42 #include <linux/udp.h>
43 #include <linux/etherdevice.h>
44 #include <linux/delay.h>
45 #include <linux/ethtool.h>
46 #include <linux/platform_device.h>
47 #include <linux/module.h>
48 #include <linux/kernel.h>
49 #include <linux/spinlock.h>
50 #include <linux/workqueue.h>
51 #include <linux/mii.h>
52 #include <linux/mv643xx_eth.h>
54 #include <asm/types.h>
55 #include <asm/system.h>
57 static char mv643xx_eth_driver_name[] = "mv643xx_eth";
58 static char mv643xx_eth_driver_version[] = "1.1";
60 #define MV643XX_ETH_CHECKSUM_OFFLOAD_TX
61 #define MV643XX_ETH_NAPI
62 #define MV643XX_ETH_TX_FAST_REFILL
64 #ifdef MV643XX_ETH_CHECKSUM_OFFLOAD_TX
65 #define MAX_DESCS_PER_SKB (MAX_SKB_FRAGS + 1)
67 #define MAX_DESCS_PER_SKB 1
71 * Registers shared between all ports.
73 #define PHY_ADDR 0x0000
74 #define SMI_REG 0x0004
75 #define WINDOW_BASE(w) (0x0200 + ((w) << 3))
76 #define WINDOW_SIZE(w) (0x0204 + ((w) << 3))
77 #define WINDOW_REMAP_HIGH(w) (0x0280 + ((w) << 2))
78 #define WINDOW_BAR_ENABLE 0x0290
79 #define WINDOW_PROTECT(w) (0x0294 + ((w) << 4))
84 #define PORT_CONFIG(p) (0x0400 + ((p) << 10))
85 #define UNICAST_PROMISCUOUS_MODE 0x00000001
86 #define PORT_CONFIG_EXT(p) (0x0404 + ((p) << 10))
87 #define MAC_ADDR_LOW(p) (0x0414 + ((p) << 10))
88 #define MAC_ADDR_HIGH(p) (0x0418 + ((p) << 10))
89 #define SDMA_CONFIG(p) (0x041c + ((p) << 10))
90 #define PORT_SERIAL_CONTROL(p) (0x043c + ((p) << 10))
91 #define PORT_STATUS(p) (0x0444 + ((p) << 10))
92 #define TX_FIFO_EMPTY 0x00000400
93 #define TX_IN_PROGRESS 0x00000080
94 #define TXQ_COMMAND(p) (0x0448 + ((p) << 10))
95 #define TXQ_FIX_PRIO_CONF(p) (0x044c + ((p) << 10))
96 #define TX_BW_RATE(p) (0x0450 + ((p) << 10))
97 #define TX_BW_MTU(p) (0x0458 + ((p) << 10))
98 #define TX_BW_BURST(p) (0x045c + ((p) << 10))
99 #define INT_CAUSE(p) (0x0460 + ((p) << 10))
100 #define INT_TX_END_0 0x00080000
101 #define INT_TX_END 0x07f80000
102 #define INT_RX 0x0007fbfc
103 #define INT_EXT 0x00000002
104 #define INT_CAUSE_EXT(p) (0x0464 + ((p) << 10))
105 #define INT_EXT_LINK 0x00100000
106 #define INT_EXT_PHY 0x00010000
107 #define INT_EXT_TX_ERROR_0 0x00000100
108 #define INT_EXT_TX_0 0x00000001
109 #define INT_EXT_TX 0x0000ffff
110 #define INT_MASK(p) (0x0468 + ((p) << 10))
111 #define INT_MASK_EXT(p) (0x046c + ((p) << 10))
112 #define TX_FIFO_URGENT_THRESHOLD(p) (0x0474 + ((p) << 10))
113 #define TXQ_FIX_PRIO_CONF_MOVED(p) (0x04dc + ((p) << 10))
114 #define TX_BW_RATE_MOVED(p) (0x04e0 + ((p) << 10))
115 #define TX_BW_MTU_MOVED(p) (0x04e8 + ((p) << 10))
116 #define TX_BW_BURST_MOVED(p) (0x04ec + ((p) << 10))
117 #define RXQ_CURRENT_DESC_PTR(p, q) (0x060c + ((p) << 10) + ((q) << 4))
118 #define RXQ_COMMAND(p) (0x0680 + ((p) << 10))
119 #define TXQ_CURRENT_DESC_PTR(p, q) (0x06c0 + ((p) << 10) + ((q) << 2))
120 #define TXQ_BW_TOKENS(p, q) (0x0700 + ((p) << 10) + ((q) << 4))
121 #define TXQ_BW_CONF(p, q) (0x0704 + ((p) << 10) + ((q) << 4))
122 #define TXQ_BW_WRR_CONF(p, q) (0x0708 + ((p) << 10) + ((q) << 4))
123 #define MIB_COUNTERS(p) (0x1000 + ((p) << 7))
124 #define SPECIAL_MCAST_TABLE(p) (0x1400 + ((p) << 10))
125 #define OTHER_MCAST_TABLE(p) (0x1500 + ((p) << 10))
126 #define UNICAST_TABLE(p) (0x1600 + ((p) << 10))
130 * SDMA configuration register.
132 #define RX_BURST_SIZE_16_64BIT (4 << 1)
133 #define BLM_RX_NO_SWAP (1 << 4)
134 #define BLM_TX_NO_SWAP (1 << 5)
135 #define TX_BURST_SIZE_16_64BIT (4 << 22)
137 #if defined(__BIG_ENDIAN)
138 #define PORT_SDMA_CONFIG_DEFAULT_VALUE \
139 RX_BURST_SIZE_16_64BIT | \
140 TX_BURST_SIZE_16_64BIT
141 #elif defined(__LITTLE_ENDIAN)
142 #define PORT_SDMA_CONFIG_DEFAULT_VALUE \
143 RX_BURST_SIZE_16_64BIT | \
146 TX_BURST_SIZE_16_64BIT
148 #error One of __BIG_ENDIAN or __LITTLE_ENDIAN must be defined
153 * Port serial control register.
155 #define SET_MII_SPEED_TO_100 (1 << 24)
156 #define SET_GMII_SPEED_TO_1000 (1 << 23)
157 #define SET_FULL_DUPLEX_MODE (1 << 21)
158 #define MAX_RX_PACKET_9700BYTE (5 << 17)
159 #define MAX_RX_PACKET_MASK (7 << 17)
160 #define DISABLE_AUTO_NEG_SPEED_GMII (1 << 13)
161 #define DO_NOT_FORCE_LINK_FAIL (1 << 10)
162 #define SERIAL_PORT_CONTROL_RESERVED (1 << 9)
163 #define DISABLE_AUTO_NEG_FOR_FLOW_CTRL (1 << 3)
164 #define DISABLE_AUTO_NEG_FOR_DUPLEX (1 << 2)
165 #define FORCE_LINK_PASS (1 << 1)
166 #define SERIAL_PORT_ENABLE (1 << 0)
168 #define DEFAULT_RX_QUEUE_SIZE 400
169 #define DEFAULT_TX_QUEUE_SIZE 800
175 #if defined(__BIG_ENDIAN)
177 u16 byte_cnt; /* Descriptor buffer byte count */
178 u16 buf_size; /* Buffer size */
179 u32 cmd_sts; /* Descriptor command status */
180 u32 next_desc_ptr; /* Next descriptor pointer */
181 u32 buf_ptr; /* Descriptor buffer pointer */
185 u16 byte_cnt; /* buffer byte count */
186 u16 l4i_chk; /* CPU provided TCP checksum */
187 u32 cmd_sts; /* Command/status field */
188 u32 next_desc_ptr; /* Pointer to next descriptor */
189 u32 buf_ptr; /* pointer to buffer for this descriptor*/
191 #elif defined(__LITTLE_ENDIAN)
193 u32 cmd_sts; /* Descriptor command status */
194 u16 buf_size; /* Buffer size */
195 u16 byte_cnt; /* Descriptor buffer byte count */
196 u32 buf_ptr; /* Descriptor buffer pointer */
197 u32 next_desc_ptr; /* Next descriptor pointer */
201 u32 cmd_sts; /* Command/status field */
202 u16 l4i_chk; /* CPU provided TCP checksum */
203 u16 byte_cnt; /* buffer byte count */
204 u32 buf_ptr; /* pointer to buffer for this descriptor*/
205 u32 next_desc_ptr; /* Pointer to next descriptor */
208 #error One of __BIG_ENDIAN or __LITTLE_ENDIAN must be defined
211 /* RX & TX descriptor command */
212 #define BUFFER_OWNED_BY_DMA 0x80000000
214 /* RX & TX descriptor status */
215 #define ERROR_SUMMARY 0x00000001
217 /* RX descriptor status */
218 #define LAYER_4_CHECKSUM_OK 0x40000000
219 #define RX_ENABLE_INTERRUPT 0x20000000
220 #define RX_FIRST_DESC 0x08000000
221 #define RX_LAST_DESC 0x04000000
223 /* TX descriptor command */
224 #define TX_ENABLE_INTERRUPT 0x00800000
225 #define GEN_CRC 0x00400000
226 #define TX_FIRST_DESC 0x00200000
227 #define TX_LAST_DESC 0x00100000
228 #define ZERO_PADDING 0x00080000
229 #define GEN_IP_V4_CHECKSUM 0x00040000
230 #define GEN_TCP_UDP_CHECKSUM 0x00020000
231 #define UDP_FRAME 0x00010000
233 #define TX_IHL_SHIFT 11
236 /* global *******************************************************************/
237 struct mv643xx_eth_shared_private {
239 * Ethernet controller base address.
244 * Protects access to SMI_REG, which is shared between ports.
249 * Per-port MBUS window access register value.
254 * Hardware-specific parameters.
257 int extended_rx_coal_limit;
258 int tx_bw_control_moved;
262 /* per-port *****************************************************************/
263 struct mib_counters {
264 u64 good_octets_received;
265 u32 bad_octets_received;
266 u32 internal_mac_transmit_err;
267 u32 good_frames_received;
268 u32 bad_frames_received;
269 u32 broadcast_frames_received;
270 u32 multicast_frames_received;
271 u32 frames_64_octets;
272 u32 frames_65_to_127_octets;
273 u32 frames_128_to_255_octets;
274 u32 frames_256_to_511_octets;
275 u32 frames_512_to_1023_octets;
276 u32 frames_1024_to_max_octets;
277 u64 good_octets_sent;
278 u32 good_frames_sent;
279 u32 excessive_collision;
280 u32 multicast_frames_sent;
281 u32 broadcast_frames_sent;
282 u32 unrec_mac_control_received;
284 u32 good_fc_received;
286 u32 undersize_received;
287 u32 fragments_received;
288 u32 oversize_received;
290 u32 mac_receive_error;
305 struct rx_desc *rx_desc_area;
306 dma_addr_t rx_desc_dma;
307 int rx_desc_area_size;
308 struct sk_buff **rx_skb;
310 struct timer_list rx_oom;
322 struct tx_desc *tx_desc_area;
323 dma_addr_t tx_desc_dma;
324 int tx_desc_area_size;
325 struct sk_buff **tx_skb;
328 struct mv643xx_eth_private {
329 struct mv643xx_eth_shared_private *shared;
332 struct net_device *dev;
334 struct mv643xx_eth_shared_private *shared_smi;
339 struct mib_counters mib_counters;
340 struct work_struct tx_timeout_task;
341 struct mii_if_info mii;
346 int default_rx_ring_size;
347 unsigned long rx_desc_sram_addr;
348 int rx_desc_sram_size;
351 struct napi_struct napi;
352 struct rx_queue rxq[8];
357 int default_tx_ring_size;
358 unsigned long tx_desc_sram_addr;
359 int tx_desc_sram_size;
362 struct tx_queue txq[8];
363 #ifdef MV643XX_ETH_TX_FAST_REFILL
364 int tx_clean_threshold;
369 /* port register accessors **************************************************/
370 static inline u32 rdl(struct mv643xx_eth_private *mp, int offset)
372 return readl(mp->shared->base + offset);
375 static inline void wrl(struct mv643xx_eth_private *mp, int offset, u32 data)
377 writel(data, mp->shared->base + offset);
381 /* rxq/txq helper functions *************************************************/
382 static struct mv643xx_eth_private *rxq_to_mp(struct rx_queue *rxq)
384 return container_of(rxq, struct mv643xx_eth_private, rxq[rxq->index]);
387 static struct mv643xx_eth_private *txq_to_mp(struct tx_queue *txq)
389 return container_of(txq, struct mv643xx_eth_private, txq[txq->index]);
392 static void rxq_enable(struct rx_queue *rxq)
394 struct mv643xx_eth_private *mp = rxq_to_mp(rxq);
395 wrl(mp, RXQ_COMMAND(mp->port_num), 1 << rxq->index);
398 static void rxq_disable(struct rx_queue *rxq)
400 struct mv643xx_eth_private *mp = rxq_to_mp(rxq);
401 u8 mask = 1 << rxq->index;
403 wrl(mp, RXQ_COMMAND(mp->port_num), mask << 8);
404 while (rdl(mp, RXQ_COMMAND(mp->port_num)) & mask)
408 static void txq_reset_hw_ptr(struct tx_queue *txq)
410 struct mv643xx_eth_private *mp = txq_to_mp(txq);
411 int off = TXQ_CURRENT_DESC_PTR(mp->port_num, txq->index);
414 addr = (u32)txq->tx_desc_dma;
415 addr += txq->tx_curr_desc * sizeof(struct tx_desc);
419 static void txq_enable(struct tx_queue *txq)
421 struct mv643xx_eth_private *mp = txq_to_mp(txq);
422 wrl(mp, TXQ_COMMAND(mp->port_num), 1 << txq->index);
425 static void txq_disable(struct tx_queue *txq)
427 struct mv643xx_eth_private *mp = txq_to_mp(txq);
428 u8 mask = 1 << txq->index;
430 wrl(mp, TXQ_COMMAND(mp->port_num), mask << 8);
431 while (rdl(mp, TXQ_COMMAND(mp->port_num)) & mask)
435 static void __txq_maybe_wake(struct tx_queue *txq)
437 struct mv643xx_eth_private *mp = txq_to_mp(txq);
440 * netif_{stop,wake}_queue() flow control only applies to
443 BUG_ON(txq->index != mp->txq_primary);
445 if (txq->tx_ring_size - txq->tx_desc_count >= MAX_DESCS_PER_SKB)
446 netif_wake_queue(mp->dev);
450 /* rx ***********************************************************************/
451 static void txq_reclaim(struct tx_queue *txq, int force);
453 static void rxq_refill(struct rx_queue *rxq)
455 struct mv643xx_eth_private *mp = rxq_to_mp(rxq);
458 spin_lock_irqsave(&mp->lock, flags);
460 while (rxq->rx_desc_count < rxq->rx_ring_size) {
467 * Reserve 2+14 bytes for an ethernet header (the
468 * hardware automatically prepends 2 bytes of dummy
469 * data to each received packet), 4 bytes for a VLAN
470 * header, and 4 bytes for the trailing FCS -- 24
473 skb_size = mp->dev->mtu + 24;
475 skb = dev_alloc_skb(skb_size + dma_get_cache_alignment() - 1);
479 unaligned = (u32)skb->data & (dma_get_cache_alignment() - 1);
481 skb_reserve(skb, dma_get_cache_alignment() - unaligned);
483 rxq->rx_desc_count++;
484 rx = rxq->rx_used_desc;
485 rxq->rx_used_desc = (rx + 1) % rxq->rx_ring_size;
487 rxq->rx_desc_area[rx].buf_ptr = dma_map_single(NULL, skb->data,
488 skb_size, DMA_FROM_DEVICE);
489 rxq->rx_desc_area[rx].buf_size = skb_size;
490 rxq->rx_skb[rx] = skb;
492 rxq->rx_desc_area[rx].cmd_sts = BUFFER_OWNED_BY_DMA |
497 * The hardware automatically prepends 2 bytes of
498 * dummy data to each received packet, so that the
499 * IP header ends up 16-byte aligned.
504 if (rxq->rx_desc_count != rxq->rx_ring_size) {
505 rxq->rx_oom.expires = jiffies + (HZ / 10);
506 add_timer(&rxq->rx_oom);
509 spin_unlock_irqrestore(&mp->lock, flags);
512 static inline void rxq_refill_timer_wrapper(unsigned long data)
514 rxq_refill((struct rx_queue *)data);
517 static int rxq_process(struct rx_queue *rxq, int budget)
519 struct mv643xx_eth_private *mp = rxq_to_mp(rxq);
520 struct net_device_stats *stats = &mp->dev->stats;
524 while (rx < budget) {
525 struct rx_desc *rx_desc;
526 unsigned int cmd_sts;
530 spin_lock_irqsave(&mp->lock, flags);
532 rx_desc = &rxq->rx_desc_area[rxq->rx_curr_desc];
534 cmd_sts = rx_desc->cmd_sts;
535 if (cmd_sts & BUFFER_OWNED_BY_DMA) {
536 spin_unlock_irqrestore(&mp->lock, flags);
541 skb = rxq->rx_skb[rxq->rx_curr_desc];
542 rxq->rx_skb[rxq->rx_curr_desc] = NULL;
544 rxq->rx_curr_desc = (rxq->rx_curr_desc + 1) % rxq->rx_ring_size;
546 spin_unlock_irqrestore(&mp->lock, flags);
548 dma_unmap_single(NULL, rx_desc->buf_ptr + 2,
549 mp->dev->mtu + 24, DMA_FROM_DEVICE);
550 rxq->rx_desc_count--;
556 * Note that the descriptor byte count includes 2 dummy
557 * bytes automatically inserted by the hardware at the
558 * start of the packet (which we don't count), and a 4
559 * byte CRC at the end of the packet (which we do count).
562 stats->rx_bytes += rx_desc->byte_cnt - 2;
565 * In case we received a packet without first / last bits
566 * on, or the error summary bit is set, the packet needs
569 if (((cmd_sts & (RX_FIRST_DESC | RX_LAST_DESC)) !=
570 (RX_FIRST_DESC | RX_LAST_DESC))
571 || (cmd_sts & ERROR_SUMMARY)) {
574 if ((cmd_sts & (RX_FIRST_DESC | RX_LAST_DESC)) !=
575 (RX_FIRST_DESC | RX_LAST_DESC)) {
577 dev_printk(KERN_ERR, &mp->dev->dev,
578 "received packet spanning "
579 "multiple descriptors\n");
582 if (cmd_sts & ERROR_SUMMARY)
585 dev_kfree_skb_irq(skb);
588 * The -4 is for the CRC in the trailer of the
591 skb_put(skb, rx_desc->byte_cnt - 2 - 4);
593 if (cmd_sts & LAYER_4_CHECKSUM_OK) {
594 skb->ip_summed = CHECKSUM_UNNECESSARY;
596 (cmd_sts & 0x0007fff8) >> 3);
598 skb->protocol = eth_type_trans(skb, mp->dev);
599 #ifdef MV643XX_ETH_NAPI
600 netif_receive_skb(skb);
606 mp->dev->last_rx = jiffies;
614 #ifdef MV643XX_ETH_NAPI
615 static int mv643xx_eth_poll(struct napi_struct *napi, int budget)
617 struct mv643xx_eth_private *mp;
621 mp = container_of(napi, struct mv643xx_eth_private, napi);
623 #ifdef MV643XX_ETH_TX_FAST_REFILL
624 if (++mp->tx_clean_threshold > 5) {
625 mp->tx_clean_threshold = 0;
626 for (i = 0; i < 8; i++)
627 if (mp->txq_mask & (1 << i))
628 txq_reclaim(mp->txq + i, 0);
630 if (netif_carrier_ok(mp->dev)) {
631 spin_lock(&mp->lock);
632 __txq_maybe_wake(mp->txq + mp->txq_primary);
633 spin_unlock(&mp->lock);
639 for (i = 7; rx < budget && i >= 0; i--)
640 if (mp->rxq_mask & (1 << i))
641 rx += rxq_process(mp->rxq + i, budget - rx);
644 netif_rx_complete(mp->dev, napi);
645 wrl(mp, INT_CAUSE(mp->port_num), 0);
646 wrl(mp, INT_CAUSE_EXT(mp->port_num), 0);
647 wrl(mp, INT_MASK(mp->port_num), INT_TX_END | INT_RX | INT_EXT);
655 /* tx ***********************************************************************/
656 static inline unsigned int has_tiny_unaligned_frags(struct sk_buff *skb)
660 for (frag = 0; frag < skb_shinfo(skb)->nr_frags; frag++) {
661 skb_frag_t *fragp = &skb_shinfo(skb)->frags[frag];
662 if (fragp->size <= 8 && fragp->page_offset & 7)
669 static int txq_alloc_desc_index(struct tx_queue *txq)
673 BUG_ON(txq->tx_desc_count >= txq->tx_ring_size);
675 tx_desc_curr = txq->tx_curr_desc;
676 txq->tx_curr_desc = (tx_desc_curr + 1) % txq->tx_ring_size;
678 BUG_ON(txq->tx_curr_desc == txq->tx_used_desc);
683 static void txq_submit_frag_skb(struct tx_queue *txq, struct sk_buff *skb)
685 int nr_frags = skb_shinfo(skb)->nr_frags;
688 for (frag = 0; frag < nr_frags; frag++) {
689 skb_frag_t *this_frag;
691 struct tx_desc *desc;
693 this_frag = &skb_shinfo(skb)->frags[frag];
694 tx_index = txq_alloc_desc_index(txq);
695 desc = &txq->tx_desc_area[tx_index];
698 * The last fragment will generate an interrupt
699 * which will free the skb on TX completion.
701 if (frag == nr_frags - 1) {
702 desc->cmd_sts = BUFFER_OWNED_BY_DMA |
703 ZERO_PADDING | TX_LAST_DESC |
705 txq->tx_skb[tx_index] = skb;
707 desc->cmd_sts = BUFFER_OWNED_BY_DMA;
708 txq->tx_skb[tx_index] = NULL;
712 desc->byte_cnt = this_frag->size;
713 desc->buf_ptr = dma_map_page(NULL, this_frag->page,
714 this_frag->page_offset,
720 static inline __be16 sum16_as_be(__sum16 sum)
722 return (__force __be16)sum;
725 static void txq_submit_skb(struct tx_queue *txq, struct sk_buff *skb)
727 struct mv643xx_eth_private *mp = txq_to_mp(txq);
728 int nr_frags = skb_shinfo(skb)->nr_frags;
730 struct tx_desc *desc;
734 cmd_sts = TX_FIRST_DESC | GEN_CRC | BUFFER_OWNED_BY_DMA;
736 tx_index = txq_alloc_desc_index(txq);
737 desc = &txq->tx_desc_area[tx_index];
740 txq_submit_frag_skb(txq, skb);
742 length = skb_headlen(skb);
743 txq->tx_skb[tx_index] = NULL;
745 cmd_sts |= ZERO_PADDING | TX_LAST_DESC | TX_ENABLE_INTERRUPT;
747 txq->tx_skb[tx_index] = skb;
750 desc->byte_cnt = length;
751 desc->buf_ptr = dma_map_single(NULL, skb->data, length, DMA_TO_DEVICE);
753 if (skb->ip_summed == CHECKSUM_PARTIAL) {
754 BUG_ON(skb->protocol != htons(ETH_P_IP));
756 cmd_sts |= GEN_TCP_UDP_CHECKSUM |
758 ip_hdr(skb)->ihl << TX_IHL_SHIFT;
760 switch (ip_hdr(skb)->protocol) {
762 cmd_sts |= UDP_FRAME;
763 desc->l4i_chk = ntohs(sum16_as_be(udp_hdr(skb)->check));
766 desc->l4i_chk = ntohs(sum16_as_be(tcp_hdr(skb)->check));
772 /* Errata BTS #50, IHL must be 5 if no HW checksum */
773 cmd_sts |= 5 << TX_IHL_SHIFT;
777 /* ensure all other descriptors are written before first cmd_sts */
779 desc->cmd_sts = cmd_sts;
781 /* clear TX_END interrupt status */
782 wrl(mp, INT_CAUSE(mp->port_num), ~(INT_TX_END_0 << txq->index));
783 rdl(mp, INT_CAUSE(mp->port_num));
785 /* ensure all descriptors are written before poking hardware */
789 txq->tx_desc_count += nr_frags + 1;
792 static int mv643xx_eth_xmit(struct sk_buff *skb, struct net_device *dev)
794 struct mv643xx_eth_private *mp = netdev_priv(dev);
795 struct net_device_stats *stats = &dev->stats;
796 struct tx_queue *txq;
799 if (has_tiny_unaligned_frags(skb) && __skb_linearize(skb)) {
801 dev_printk(KERN_DEBUG, &dev->dev,
802 "failed to linearize skb with tiny "
803 "unaligned fragment\n");
804 return NETDEV_TX_BUSY;
807 spin_lock_irqsave(&mp->lock, flags);
809 txq = mp->txq + mp->txq_primary;
811 if (txq->tx_ring_size - txq->tx_desc_count < MAX_DESCS_PER_SKB) {
812 spin_unlock_irqrestore(&mp->lock, flags);
813 if (txq->index == mp->txq_primary && net_ratelimit())
814 dev_printk(KERN_ERR, &dev->dev,
815 "primary tx queue full?!\n");
820 txq_submit_skb(txq, skb);
821 stats->tx_bytes += skb->len;
823 dev->trans_start = jiffies;
825 if (txq->index == mp->txq_primary) {
828 entries_left = txq->tx_ring_size - txq->tx_desc_count;
829 if (entries_left < MAX_DESCS_PER_SKB)
830 netif_stop_queue(dev);
833 spin_unlock_irqrestore(&mp->lock, flags);
839 /* tx rate control **********************************************************/
841 * Set total maximum TX rate (shared by all TX queues for this port)
842 * to 'rate' bits per second, with a maximum burst of 'burst' bytes.
844 static void tx_set_rate(struct mv643xx_eth_private *mp, int rate, int burst)
850 token_rate = ((rate / 1000) * 64) / (mp->shared->t_clk / 1000);
851 if (token_rate > 1023)
854 mtu = (mp->dev->mtu + 255) >> 8;
858 bucket_size = (burst + 255) >> 8;
859 if (bucket_size > 65535)
862 if (mp->shared->tx_bw_control_moved) {
863 wrl(mp, TX_BW_RATE_MOVED(mp->port_num), token_rate);
864 wrl(mp, TX_BW_MTU_MOVED(mp->port_num), mtu);
865 wrl(mp, TX_BW_BURST_MOVED(mp->port_num), bucket_size);
867 wrl(mp, TX_BW_RATE(mp->port_num), token_rate);
868 wrl(mp, TX_BW_MTU(mp->port_num), mtu);
869 wrl(mp, TX_BW_BURST(mp->port_num), bucket_size);
873 static void txq_set_rate(struct tx_queue *txq, int rate, int burst)
875 struct mv643xx_eth_private *mp = txq_to_mp(txq);
879 token_rate = ((rate / 1000) * 64) / (mp->shared->t_clk / 1000);
880 if (token_rate > 1023)
883 bucket_size = (burst + 255) >> 8;
884 if (bucket_size > 65535)
887 wrl(mp, TXQ_BW_TOKENS(mp->port_num, txq->index), token_rate << 14);
888 wrl(mp, TXQ_BW_CONF(mp->port_num, txq->index),
889 (bucket_size << 10) | token_rate);
892 static void txq_set_fixed_prio_mode(struct tx_queue *txq)
894 struct mv643xx_eth_private *mp = txq_to_mp(txq);
899 * Turn on fixed priority mode.
901 if (mp->shared->tx_bw_control_moved)
902 off = TXQ_FIX_PRIO_CONF_MOVED(mp->port_num);
904 off = TXQ_FIX_PRIO_CONF(mp->port_num);
907 val |= 1 << txq->index;
911 static void txq_set_wrr(struct tx_queue *txq, int weight)
913 struct mv643xx_eth_private *mp = txq_to_mp(txq);
918 * Turn off fixed priority mode.
920 if (mp->shared->tx_bw_control_moved)
921 off = TXQ_FIX_PRIO_CONF_MOVED(mp->port_num);
923 off = TXQ_FIX_PRIO_CONF(mp->port_num);
926 val &= ~(1 << txq->index);
930 * Configure WRR weight for this queue.
932 off = TXQ_BW_WRR_CONF(mp->port_num, txq->index);
935 val = (val & ~0xff) | (weight & 0xff);
940 /* mii management interface *************************************************/
941 #define SMI_BUSY 0x10000000
942 #define SMI_READ_VALID 0x08000000
943 #define SMI_OPCODE_READ 0x04000000
944 #define SMI_OPCODE_WRITE 0x00000000
946 static void smi_reg_read(struct mv643xx_eth_private *mp, unsigned int addr,
947 unsigned int reg, unsigned int *value)
949 void __iomem *smi_reg = mp->shared_smi->base + SMI_REG;
953 /* the SMI register is a shared resource */
954 spin_lock_irqsave(&mp->shared_smi->phy_lock, flags);
956 /* wait for the SMI register to become available */
957 for (i = 0; readl(smi_reg) & SMI_BUSY; i++) {
959 printk("%s: PHY busy timeout\n", mp->dev->name);
965 writel(SMI_OPCODE_READ | (reg << 21) | (addr << 16), smi_reg);
967 /* now wait for the data to be valid */
968 for (i = 0; !(readl(smi_reg) & SMI_READ_VALID); i++) {
970 printk("%s: PHY read timeout\n", mp->dev->name);
976 *value = readl(smi_reg) & 0xffff;
978 spin_unlock_irqrestore(&mp->shared_smi->phy_lock, flags);
981 static void smi_reg_write(struct mv643xx_eth_private *mp,
983 unsigned int reg, unsigned int value)
985 void __iomem *smi_reg = mp->shared_smi->base + SMI_REG;
989 /* the SMI register is a shared resource */
990 spin_lock_irqsave(&mp->shared_smi->phy_lock, flags);
992 /* wait for the SMI register to become available */
993 for (i = 0; readl(smi_reg) & SMI_BUSY; i++) {
995 printk("%s: PHY busy timeout\n", mp->dev->name);
1001 writel(SMI_OPCODE_WRITE | (reg << 21) |
1002 (addr << 16) | (value & 0xffff), smi_reg);
1004 spin_unlock_irqrestore(&mp->shared_smi->phy_lock, flags);
1008 /* mib counters *************************************************************/
1009 static inline u32 mib_read(struct mv643xx_eth_private *mp, int offset)
1011 return rdl(mp, MIB_COUNTERS(mp->port_num) + offset);
1014 static void mib_counters_clear(struct mv643xx_eth_private *mp)
1018 for (i = 0; i < 0x80; i += 4)
1022 static void mib_counters_update(struct mv643xx_eth_private *mp)
1024 struct mib_counters *p = &mp->mib_counters;
1026 p->good_octets_received += mib_read(mp, 0x00);
1027 p->good_octets_received += (u64)mib_read(mp, 0x04) << 32;
1028 p->bad_octets_received += mib_read(mp, 0x08);
1029 p->internal_mac_transmit_err += mib_read(mp, 0x0c);
1030 p->good_frames_received += mib_read(mp, 0x10);
1031 p->bad_frames_received += mib_read(mp, 0x14);
1032 p->broadcast_frames_received += mib_read(mp, 0x18);
1033 p->multicast_frames_received += mib_read(mp, 0x1c);
1034 p->frames_64_octets += mib_read(mp, 0x20);
1035 p->frames_65_to_127_octets += mib_read(mp, 0x24);
1036 p->frames_128_to_255_octets += mib_read(mp, 0x28);
1037 p->frames_256_to_511_octets += mib_read(mp, 0x2c);
1038 p->frames_512_to_1023_octets += mib_read(mp, 0x30);
1039 p->frames_1024_to_max_octets += mib_read(mp, 0x34);
1040 p->good_octets_sent += mib_read(mp, 0x38);
1041 p->good_octets_sent += (u64)mib_read(mp, 0x3c) << 32;
1042 p->good_frames_sent += mib_read(mp, 0x40);
1043 p->excessive_collision += mib_read(mp, 0x44);
1044 p->multicast_frames_sent += mib_read(mp, 0x48);
1045 p->broadcast_frames_sent += mib_read(mp, 0x4c);
1046 p->unrec_mac_control_received += mib_read(mp, 0x50);
1047 p->fc_sent += mib_read(mp, 0x54);
1048 p->good_fc_received += mib_read(mp, 0x58);
1049 p->bad_fc_received += mib_read(mp, 0x5c);
1050 p->undersize_received += mib_read(mp, 0x60);
1051 p->fragments_received += mib_read(mp, 0x64);
1052 p->oversize_received += mib_read(mp, 0x68);
1053 p->jabber_received += mib_read(mp, 0x6c);
1054 p->mac_receive_error += mib_read(mp, 0x70);
1055 p->bad_crc_event += mib_read(mp, 0x74);
1056 p->collision += mib_read(mp, 0x78);
1057 p->late_collision += mib_read(mp, 0x7c);
1061 /* ethtool ******************************************************************/
1062 struct mv643xx_eth_stats {
1063 char stat_string[ETH_GSTRING_LEN];
1070 { #m, FIELD_SIZEOF(struct net_device_stats, m), \
1071 offsetof(struct net_device, stats.m), -1 }
1073 #define MIBSTAT(m) \
1074 { #m, FIELD_SIZEOF(struct mib_counters, m), \
1075 -1, offsetof(struct mv643xx_eth_private, mib_counters.m) }
1077 static const struct mv643xx_eth_stats mv643xx_eth_stats[] = {
1086 MIBSTAT(good_octets_received),
1087 MIBSTAT(bad_octets_received),
1088 MIBSTAT(internal_mac_transmit_err),
1089 MIBSTAT(good_frames_received),
1090 MIBSTAT(bad_frames_received),
1091 MIBSTAT(broadcast_frames_received),
1092 MIBSTAT(multicast_frames_received),
1093 MIBSTAT(frames_64_octets),
1094 MIBSTAT(frames_65_to_127_octets),
1095 MIBSTAT(frames_128_to_255_octets),
1096 MIBSTAT(frames_256_to_511_octets),
1097 MIBSTAT(frames_512_to_1023_octets),
1098 MIBSTAT(frames_1024_to_max_octets),
1099 MIBSTAT(good_octets_sent),
1100 MIBSTAT(good_frames_sent),
1101 MIBSTAT(excessive_collision),
1102 MIBSTAT(multicast_frames_sent),
1103 MIBSTAT(broadcast_frames_sent),
1104 MIBSTAT(unrec_mac_control_received),
1106 MIBSTAT(good_fc_received),
1107 MIBSTAT(bad_fc_received),
1108 MIBSTAT(undersize_received),
1109 MIBSTAT(fragments_received),
1110 MIBSTAT(oversize_received),
1111 MIBSTAT(jabber_received),
1112 MIBSTAT(mac_receive_error),
1113 MIBSTAT(bad_crc_event),
1115 MIBSTAT(late_collision),
1118 static int mv643xx_eth_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1120 struct mv643xx_eth_private *mp = netdev_priv(dev);
1123 spin_lock_irq(&mp->lock);
1124 err = mii_ethtool_gset(&mp->mii, cmd);
1125 spin_unlock_irq(&mp->lock);
1128 * The MAC does not support 1000baseT_Half.
1130 cmd->supported &= ~SUPPORTED_1000baseT_Half;
1131 cmd->advertising &= ~ADVERTISED_1000baseT_Half;
1136 static int mv643xx_eth_get_settings_phyless(struct net_device *dev, struct ethtool_cmd *cmd)
1138 cmd->supported = SUPPORTED_MII;
1139 cmd->advertising = ADVERTISED_MII;
1140 cmd->speed = SPEED_1000;
1141 cmd->duplex = DUPLEX_FULL;
1142 cmd->port = PORT_MII;
1143 cmd->phy_address = 0;
1144 cmd->transceiver = XCVR_INTERNAL;
1145 cmd->autoneg = AUTONEG_DISABLE;
1152 static int mv643xx_eth_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1154 struct mv643xx_eth_private *mp = netdev_priv(dev);
1158 * The MAC does not support 1000baseT_Half.
1160 cmd->advertising &= ~ADVERTISED_1000baseT_Half;
1162 spin_lock_irq(&mp->lock);
1163 err = mii_ethtool_sset(&mp->mii, cmd);
1164 spin_unlock_irq(&mp->lock);
1169 static int mv643xx_eth_set_settings_phyless(struct net_device *dev, struct ethtool_cmd *cmd)
1174 static void mv643xx_eth_get_drvinfo(struct net_device *dev,
1175 struct ethtool_drvinfo *drvinfo)
1177 strncpy(drvinfo->driver, mv643xx_eth_driver_name, 32);
1178 strncpy(drvinfo->version, mv643xx_eth_driver_version, 32);
1179 strncpy(drvinfo->fw_version, "N/A", 32);
1180 strncpy(drvinfo->bus_info, "platform", 32);
1181 drvinfo->n_stats = ARRAY_SIZE(mv643xx_eth_stats);
1184 static int mv643xx_eth_nway_reset(struct net_device *dev)
1186 struct mv643xx_eth_private *mp = netdev_priv(dev);
1188 return mii_nway_restart(&mp->mii);
1191 static int mv643xx_eth_nway_reset_phyless(struct net_device *dev)
1196 static u32 mv643xx_eth_get_link(struct net_device *dev)
1198 struct mv643xx_eth_private *mp = netdev_priv(dev);
1200 return mii_link_ok(&mp->mii);
1203 static u32 mv643xx_eth_get_link_phyless(struct net_device *dev)
1208 static void mv643xx_eth_get_strings(struct net_device *dev,
1209 uint32_t stringset, uint8_t *data)
1213 if (stringset == ETH_SS_STATS) {
1214 for (i = 0; i < ARRAY_SIZE(mv643xx_eth_stats); i++) {
1215 memcpy(data + i * ETH_GSTRING_LEN,
1216 mv643xx_eth_stats[i].stat_string,
1222 static void mv643xx_eth_get_ethtool_stats(struct net_device *dev,
1223 struct ethtool_stats *stats,
1226 struct mv643xx_eth_private *mp = dev->priv;
1229 mib_counters_update(mp);
1231 for (i = 0; i < ARRAY_SIZE(mv643xx_eth_stats); i++) {
1232 const struct mv643xx_eth_stats *stat;
1235 stat = mv643xx_eth_stats + i;
1237 if (stat->netdev_off >= 0)
1238 p = ((void *)mp->dev) + stat->netdev_off;
1240 p = ((void *)mp) + stat->mp_off;
1242 data[i] = (stat->sizeof_stat == 8) ?
1243 *(uint64_t *)p : *(uint32_t *)p;
1247 static int mv643xx_eth_get_sset_count(struct net_device *dev, int sset)
1249 if (sset == ETH_SS_STATS)
1250 return ARRAY_SIZE(mv643xx_eth_stats);
1255 static const struct ethtool_ops mv643xx_eth_ethtool_ops = {
1256 .get_settings = mv643xx_eth_get_settings,
1257 .set_settings = mv643xx_eth_set_settings,
1258 .get_drvinfo = mv643xx_eth_get_drvinfo,
1259 .nway_reset = mv643xx_eth_nway_reset,
1260 .get_link = mv643xx_eth_get_link,
1261 .set_sg = ethtool_op_set_sg,
1262 .get_strings = mv643xx_eth_get_strings,
1263 .get_ethtool_stats = mv643xx_eth_get_ethtool_stats,
1264 .get_sset_count = mv643xx_eth_get_sset_count,
1267 static const struct ethtool_ops mv643xx_eth_ethtool_ops_phyless = {
1268 .get_settings = mv643xx_eth_get_settings_phyless,
1269 .set_settings = mv643xx_eth_set_settings_phyless,
1270 .get_drvinfo = mv643xx_eth_get_drvinfo,
1271 .nway_reset = mv643xx_eth_nway_reset_phyless,
1272 .get_link = mv643xx_eth_get_link_phyless,
1273 .set_sg = ethtool_op_set_sg,
1274 .get_strings = mv643xx_eth_get_strings,
1275 .get_ethtool_stats = mv643xx_eth_get_ethtool_stats,
1276 .get_sset_count = mv643xx_eth_get_sset_count,
1280 /* address handling *********************************************************/
1281 static void uc_addr_get(struct mv643xx_eth_private *mp, unsigned char *addr)
1286 mac_h = rdl(mp, MAC_ADDR_HIGH(mp->port_num));
1287 mac_l = rdl(mp, MAC_ADDR_LOW(mp->port_num));
1289 addr[0] = (mac_h >> 24) & 0xff;
1290 addr[1] = (mac_h >> 16) & 0xff;
1291 addr[2] = (mac_h >> 8) & 0xff;
1292 addr[3] = mac_h & 0xff;
1293 addr[4] = (mac_l >> 8) & 0xff;
1294 addr[5] = mac_l & 0xff;
1297 static void init_mac_tables(struct mv643xx_eth_private *mp)
1301 for (i = 0; i < 0x100; i += 4) {
1302 wrl(mp, SPECIAL_MCAST_TABLE(mp->port_num) + i, 0);
1303 wrl(mp, OTHER_MCAST_TABLE(mp->port_num) + i, 0);
1306 for (i = 0; i < 0x10; i += 4)
1307 wrl(mp, UNICAST_TABLE(mp->port_num) + i, 0);
1310 static void set_filter_table_entry(struct mv643xx_eth_private *mp,
1311 int table, unsigned char entry)
1313 unsigned int table_reg;
1315 /* Set "accepts frame bit" at specified table entry */
1316 table_reg = rdl(mp, table + (entry & 0xfc));
1317 table_reg |= 0x01 << (8 * (entry & 3));
1318 wrl(mp, table + (entry & 0xfc), table_reg);
1321 static void uc_addr_set(struct mv643xx_eth_private *mp, unsigned char *addr)
1327 mac_l = (addr[4] << 8) | addr[5];
1328 mac_h = (addr[0] << 24) | (addr[1] << 16) | (addr[2] << 8) | addr[3];
1330 wrl(mp, MAC_ADDR_LOW(mp->port_num), mac_l);
1331 wrl(mp, MAC_ADDR_HIGH(mp->port_num), mac_h);
1333 table = UNICAST_TABLE(mp->port_num);
1334 set_filter_table_entry(mp, table, addr[5] & 0x0f);
1337 static int mv643xx_eth_set_mac_address(struct net_device *dev, void *addr)
1339 struct mv643xx_eth_private *mp = netdev_priv(dev);
1341 /* +2 is for the offset of the HW addr type */
1342 memcpy(dev->dev_addr, addr + 2, 6);
1344 init_mac_tables(mp);
1345 uc_addr_set(mp, dev->dev_addr);
1350 static int addr_crc(unsigned char *addr)
1355 for (i = 0; i < 6; i++) {
1358 crc = (crc ^ addr[i]) << 8;
1359 for (j = 7; j >= 0; j--) {
1360 if (crc & (0x100 << j))
1368 static void mv643xx_eth_set_rx_mode(struct net_device *dev)
1370 struct mv643xx_eth_private *mp = netdev_priv(dev);
1372 struct dev_addr_list *addr;
1375 port_config = rdl(mp, PORT_CONFIG(mp->port_num));
1376 if (dev->flags & IFF_PROMISC)
1377 port_config |= UNICAST_PROMISCUOUS_MODE;
1379 port_config &= ~UNICAST_PROMISCUOUS_MODE;
1380 wrl(mp, PORT_CONFIG(mp->port_num), port_config);
1382 if (dev->flags & (IFF_PROMISC | IFF_ALLMULTI)) {
1383 int port_num = mp->port_num;
1384 u32 accept = 0x01010101;
1386 for (i = 0; i < 0x100; i += 4) {
1387 wrl(mp, SPECIAL_MCAST_TABLE(port_num) + i, accept);
1388 wrl(mp, OTHER_MCAST_TABLE(port_num) + i, accept);
1393 for (i = 0; i < 0x100; i += 4) {
1394 wrl(mp, SPECIAL_MCAST_TABLE(mp->port_num) + i, 0);
1395 wrl(mp, OTHER_MCAST_TABLE(mp->port_num) + i, 0);
1398 for (addr = dev->mc_list; addr != NULL; addr = addr->next) {
1399 u8 *a = addr->da_addr;
1402 if (addr->da_addrlen != 6)
1405 if (memcmp(a, "\x01\x00\x5e\x00\x00", 5) == 0) {
1406 table = SPECIAL_MCAST_TABLE(mp->port_num);
1407 set_filter_table_entry(mp, table, a[5]);
1409 int crc = addr_crc(a);
1411 table = OTHER_MCAST_TABLE(mp->port_num);
1412 set_filter_table_entry(mp, table, crc);
1418 /* rx/tx queue initialisation ***********************************************/
1419 static int rxq_init(struct mv643xx_eth_private *mp, int index)
1421 struct rx_queue *rxq = mp->rxq + index;
1422 struct rx_desc *rx_desc;
1428 rxq->rx_ring_size = mp->default_rx_ring_size;
1430 rxq->rx_desc_count = 0;
1431 rxq->rx_curr_desc = 0;
1432 rxq->rx_used_desc = 0;
1434 size = rxq->rx_ring_size * sizeof(struct rx_desc);
1436 if (index == mp->rxq_primary && size <= mp->rx_desc_sram_size) {
1437 rxq->rx_desc_area = ioremap(mp->rx_desc_sram_addr,
1438 mp->rx_desc_sram_size);
1439 rxq->rx_desc_dma = mp->rx_desc_sram_addr;
1441 rxq->rx_desc_area = dma_alloc_coherent(NULL, size,
1446 if (rxq->rx_desc_area == NULL) {
1447 dev_printk(KERN_ERR, &mp->dev->dev,
1448 "can't allocate rx ring (%d bytes)\n", size);
1451 memset(rxq->rx_desc_area, 0, size);
1453 rxq->rx_desc_area_size = size;
1454 rxq->rx_skb = kmalloc(rxq->rx_ring_size * sizeof(*rxq->rx_skb),
1456 if (rxq->rx_skb == NULL) {
1457 dev_printk(KERN_ERR, &mp->dev->dev,
1458 "can't allocate rx skb ring\n");
1462 rx_desc = (struct rx_desc *)rxq->rx_desc_area;
1463 for (i = 0; i < rxq->rx_ring_size; i++) {
1464 int nexti = (i + 1) % rxq->rx_ring_size;
1465 rx_desc[i].next_desc_ptr = rxq->rx_desc_dma +
1466 nexti * sizeof(struct rx_desc);
1469 init_timer(&rxq->rx_oom);
1470 rxq->rx_oom.data = (unsigned long)rxq;
1471 rxq->rx_oom.function = rxq_refill_timer_wrapper;
1477 if (index == mp->rxq_primary && size <= mp->rx_desc_sram_size)
1478 iounmap(rxq->rx_desc_area);
1480 dma_free_coherent(NULL, size,
1488 static void rxq_deinit(struct rx_queue *rxq)
1490 struct mv643xx_eth_private *mp = rxq_to_mp(rxq);
1495 del_timer_sync(&rxq->rx_oom);
1497 for (i = 0; i < rxq->rx_ring_size; i++) {
1498 if (rxq->rx_skb[i]) {
1499 dev_kfree_skb(rxq->rx_skb[i]);
1500 rxq->rx_desc_count--;
1504 if (rxq->rx_desc_count) {
1505 dev_printk(KERN_ERR, &mp->dev->dev,
1506 "error freeing rx ring -- %d skbs stuck\n",
1507 rxq->rx_desc_count);
1510 if (rxq->index == mp->rxq_primary &&
1511 rxq->rx_desc_area_size <= mp->rx_desc_sram_size)
1512 iounmap(rxq->rx_desc_area);
1514 dma_free_coherent(NULL, rxq->rx_desc_area_size,
1515 rxq->rx_desc_area, rxq->rx_desc_dma);
1520 static int txq_init(struct mv643xx_eth_private *mp, int index)
1522 struct tx_queue *txq = mp->txq + index;
1523 struct tx_desc *tx_desc;
1529 txq->tx_ring_size = mp->default_tx_ring_size;
1531 txq->tx_desc_count = 0;
1532 txq->tx_curr_desc = 0;
1533 txq->tx_used_desc = 0;
1535 size = txq->tx_ring_size * sizeof(struct tx_desc);
1537 if (index == mp->txq_primary && size <= mp->tx_desc_sram_size) {
1538 txq->tx_desc_area = ioremap(mp->tx_desc_sram_addr,
1539 mp->tx_desc_sram_size);
1540 txq->tx_desc_dma = mp->tx_desc_sram_addr;
1542 txq->tx_desc_area = dma_alloc_coherent(NULL, size,
1547 if (txq->tx_desc_area == NULL) {
1548 dev_printk(KERN_ERR, &mp->dev->dev,
1549 "can't allocate tx ring (%d bytes)\n", size);
1552 memset(txq->tx_desc_area, 0, size);
1554 txq->tx_desc_area_size = size;
1555 txq->tx_skb = kmalloc(txq->tx_ring_size * sizeof(*txq->tx_skb),
1557 if (txq->tx_skb == NULL) {
1558 dev_printk(KERN_ERR, &mp->dev->dev,
1559 "can't allocate tx skb ring\n");
1563 tx_desc = (struct tx_desc *)txq->tx_desc_area;
1564 for (i = 0; i < txq->tx_ring_size; i++) {
1565 struct tx_desc *txd = tx_desc + i;
1566 int nexti = (i + 1) % txq->tx_ring_size;
1569 txd->next_desc_ptr = txq->tx_desc_dma +
1570 nexti * sizeof(struct tx_desc);
1577 if (index == mp->txq_primary && size <= mp->tx_desc_sram_size)
1578 iounmap(txq->tx_desc_area);
1580 dma_free_coherent(NULL, size,
1588 static void txq_reclaim(struct tx_queue *txq, int force)
1590 struct mv643xx_eth_private *mp = txq_to_mp(txq);
1591 unsigned long flags;
1593 spin_lock_irqsave(&mp->lock, flags);
1594 while (txq->tx_desc_count > 0) {
1596 struct tx_desc *desc;
1598 struct sk_buff *skb;
1602 tx_index = txq->tx_used_desc;
1603 desc = &txq->tx_desc_area[tx_index];
1604 cmd_sts = desc->cmd_sts;
1606 if (cmd_sts & BUFFER_OWNED_BY_DMA) {
1609 desc->cmd_sts = cmd_sts & ~BUFFER_OWNED_BY_DMA;
1612 txq->tx_used_desc = (tx_index + 1) % txq->tx_ring_size;
1613 txq->tx_desc_count--;
1615 addr = desc->buf_ptr;
1616 count = desc->byte_cnt;
1617 skb = txq->tx_skb[tx_index];
1618 txq->tx_skb[tx_index] = NULL;
1620 if (cmd_sts & ERROR_SUMMARY) {
1621 dev_printk(KERN_INFO, &mp->dev->dev, "tx error\n");
1622 mp->dev->stats.tx_errors++;
1626 * Drop mp->lock while we free the skb.
1628 spin_unlock_irqrestore(&mp->lock, flags);
1630 if (cmd_sts & TX_FIRST_DESC)
1631 dma_unmap_single(NULL, addr, count, DMA_TO_DEVICE);
1633 dma_unmap_page(NULL, addr, count, DMA_TO_DEVICE);
1636 dev_kfree_skb_irq(skb);
1638 spin_lock_irqsave(&mp->lock, flags);
1640 spin_unlock_irqrestore(&mp->lock, flags);
1643 static void txq_deinit(struct tx_queue *txq)
1645 struct mv643xx_eth_private *mp = txq_to_mp(txq);
1648 txq_reclaim(txq, 1);
1650 BUG_ON(txq->tx_used_desc != txq->tx_curr_desc);
1652 if (txq->index == mp->txq_primary &&
1653 txq->tx_desc_area_size <= mp->tx_desc_sram_size)
1654 iounmap(txq->tx_desc_area);
1656 dma_free_coherent(NULL, txq->tx_desc_area_size,
1657 txq->tx_desc_area, txq->tx_desc_dma);
1663 /* netdev ops and related ***************************************************/
1664 static void update_pscr(struct mv643xx_eth_private *mp, int speed, int duplex)
1669 pscr_o = rdl(mp, PORT_SERIAL_CONTROL(mp->port_num));
1671 /* clear speed, duplex and rx buffer size fields */
1672 pscr_n = pscr_o & ~(SET_MII_SPEED_TO_100 |
1673 SET_GMII_SPEED_TO_1000 |
1674 SET_FULL_DUPLEX_MODE |
1675 MAX_RX_PACKET_MASK);
1677 pscr_n |= MAX_RX_PACKET_9700BYTE;
1679 if (speed == SPEED_1000)
1680 pscr_n |= SET_GMII_SPEED_TO_1000;
1681 else if (speed == SPEED_100)
1682 pscr_n |= SET_MII_SPEED_TO_100;
1684 if (duplex == DUPLEX_FULL)
1685 pscr_n |= SET_FULL_DUPLEX_MODE;
1687 if (pscr_n != pscr_o) {
1688 if ((pscr_o & SERIAL_PORT_ENABLE) == 0)
1689 wrl(mp, PORT_SERIAL_CONTROL(mp->port_num), pscr_n);
1693 for (i = 0; i < 8; i++)
1694 if (mp->txq_mask & (1 << i))
1695 txq_disable(mp->txq + i);
1697 pscr_o &= ~SERIAL_PORT_ENABLE;
1698 wrl(mp, PORT_SERIAL_CONTROL(mp->port_num), pscr_o);
1699 wrl(mp, PORT_SERIAL_CONTROL(mp->port_num), pscr_n);
1700 wrl(mp, PORT_SERIAL_CONTROL(mp->port_num), pscr_n);
1702 for (i = 0; i < 8; i++)
1703 if (mp->txq_mask & (1 << i))
1704 txq_enable(mp->txq + i);
1709 static irqreturn_t mv643xx_eth_irq(int irq, void *dev_id)
1711 struct net_device *dev = (struct net_device *)dev_id;
1712 struct mv643xx_eth_private *mp = netdev_priv(dev);
1716 int_cause = rdl(mp, INT_CAUSE(mp->port_num)) &
1717 (INT_TX_END | INT_RX | INT_EXT);
1722 if (int_cause & INT_EXT) {
1723 int_cause_ext = rdl(mp, INT_CAUSE_EXT(mp->port_num))
1724 & (INT_EXT_LINK | INT_EXT_PHY | INT_EXT_TX);
1725 wrl(mp, INT_CAUSE_EXT(mp->port_num), ~int_cause_ext);
1728 if (int_cause_ext & (INT_EXT_PHY | INT_EXT_LINK)) {
1729 if (mp->phy_addr == -1 || mii_link_ok(&mp->mii)) {
1730 if (mp->phy_addr != -1) {
1731 struct ethtool_cmd cmd;
1733 mii_ethtool_gset(&mp->mii, &cmd);
1734 update_pscr(mp, cmd.speed, cmd.duplex);
1737 if (!netif_carrier_ok(dev)) {
1738 netif_carrier_on(dev);
1739 netif_wake_queue(dev);
1741 } else if (netif_carrier_ok(dev)) {
1744 netif_stop_queue(dev);
1745 netif_carrier_off(dev);
1747 for (i = 0; i < 8; i++) {
1748 struct tx_queue *txq = mp->txq + i;
1750 if (mp->txq_mask & (1 << i)) {
1751 txq_reclaim(txq, 1);
1752 txq_reset_hw_ptr(txq);
1759 * RxBuffer or RxError set for any of the 8 queues?
1761 #ifdef MV643XX_ETH_NAPI
1762 if (int_cause & INT_RX) {
1763 wrl(mp, INT_MASK(mp->port_num), 0x00000000);
1764 rdl(mp, INT_MASK(mp->port_num));
1766 netif_rx_schedule(dev, &mp->napi);
1769 if (int_cause & INT_RX) {
1772 for (i = 7; i >= 0; i--)
1773 if (mp->rxq_mask & (1 << i))
1774 rxq_process(mp->rxq + i, INT_MAX);
1779 * TxBuffer or TxError set for any of the 8 queues?
1781 if (int_cause_ext & INT_EXT_TX) {
1784 for (i = 0; i < 8; i++)
1785 if (mp->txq_mask & (1 << i))
1786 txq_reclaim(mp->txq + i, 0);
1789 * Enough space again in the primary TX queue for a
1792 if (netif_carrier_ok(dev)) {
1793 spin_lock(&mp->lock);
1794 __txq_maybe_wake(mp->txq + mp->txq_primary);
1795 spin_unlock(&mp->lock);
1800 * Any TxEnd interrupts?
1802 if (int_cause & INT_TX_END) {
1805 wrl(mp, INT_CAUSE(mp->port_num), ~(int_cause & INT_TX_END));
1807 spin_lock(&mp->lock);
1808 for (i = 0; i < 8; i++) {
1809 struct tx_queue *txq = mp->txq + i;
1813 if ((int_cause & (INT_TX_END_0 << i)) == 0)
1817 rdl(mp, TXQ_CURRENT_DESC_PTR(mp->port_num, i));
1818 expected_ptr = (u32)txq->tx_desc_dma +
1819 txq->tx_curr_desc * sizeof(struct tx_desc);
1821 if (hw_desc_ptr != expected_ptr)
1824 spin_unlock(&mp->lock);
1830 static void phy_reset(struct mv643xx_eth_private *mp)
1834 smi_reg_read(mp, mp->phy_addr, 0, &data);
1836 smi_reg_write(mp, mp->phy_addr, 0, data);
1840 smi_reg_read(mp, mp->phy_addr, 0, &data);
1841 } while (data & 0x8000);
1844 static void port_start(struct mv643xx_eth_private *mp)
1850 * Configure basic link parameters.
1852 pscr = rdl(mp, PORT_SERIAL_CONTROL(mp->port_num));
1853 pscr &= ~(SERIAL_PORT_ENABLE | FORCE_LINK_PASS);
1854 wrl(mp, PORT_SERIAL_CONTROL(mp->port_num), pscr);
1855 pscr |= DISABLE_AUTO_NEG_FOR_FLOW_CTRL |
1856 DISABLE_AUTO_NEG_SPEED_GMII |
1857 DISABLE_AUTO_NEG_FOR_DUPLEX |
1858 DO_NOT_FORCE_LINK_FAIL |
1859 SERIAL_PORT_CONTROL_RESERVED;
1860 wrl(mp, PORT_SERIAL_CONTROL(mp->port_num), pscr);
1861 pscr |= SERIAL_PORT_ENABLE;
1862 wrl(mp, PORT_SERIAL_CONTROL(mp->port_num), pscr);
1864 wrl(mp, SDMA_CONFIG(mp->port_num), PORT_SDMA_CONFIG_DEFAULT_VALUE);
1867 * Perform PHY reset, if there is a PHY.
1869 if (mp->phy_addr != -1) {
1870 struct ethtool_cmd cmd;
1872 mv643xx_eth_get_settings(mp->dev, &cmd);
1874 mv643xx_eth_set_settings(mp->dev, &cmd);
1878 * Configure TX path and queues.
1880 tx_set_rate(mp, 1000000000, 16777216);
1881 for (i = 0; i < 8; i++) {
1882 struct tx_queue *txq = mp->txq + i;
1884 if ((mp->txq_mask & (1 << i)) == 0)
1887 txq_reset_hw_ptr(txq);
1888 txq_set_rate(txq, 1000000000, 16777216);
1889 txq_set_fixed_prio_mode(txq);
1893 * Add configured unicast address to address filter table.
1895 uc_addr_set(mp, mp->dev->dev_addr);
1898 * Receive all unmatched unicast, TCP, UDP, BPDU and broadcast
1899 * frames to RX queue #0.
1901 wrl(mp, PORT_CONFIG(mp->port_num), 0x00000000);
1904 * Treat BPDUs as normal multicasts, and disable partition mode.
1906 wrl(mp, PORT_CONFIG_EXT(mp->port_num), 0x00000000);
1909 * Enable the receive queues.
1911 for (i = 0; i < 8; i++) {
1912 struct rx_queue *rxq = mp->rxq + i;
1913 int off = RXQ_CURRENT_DESC_PTR(mp->port_num, i);
1916 if ((mp->rxq_mask & (1 << i)) == 0)
1919 addr = (u32)rxq->rx_desc_dma;
1920 addr += rxq->rx_curr_desc * sizeof(struct rx_desc);
1927 static void set_rx_coal(struct mv643xx_eth_private *mp, unsigned int delay)
1929 unsigned int coal = ((mp->shared->t_clk / 1000000) * delay) / 64;
1932 val = rdl(mp, SDMA_CONFIG(mp->port_num));
1933 if (mp->shared->extended_rx_coal_limit) {
1937 val |= (coal & 0x8000) << 10;
1938 val |= (coal & 0x7fff) << 7;
1943 val |= (coal & 0x3fff) << 8;
1945 wrl(mp, SDMA_CONFIG(mp->port_num), val);
1948 static void set_tx_coal(struct mv643xx_eth_private *mp, unsigned int delay)
1950 unsigned int coal = ((mp->shared->t_clk / 1000000) * delay) / 64;
1954 wrl(mp, TX_FIFO_URGENT_THRESHOLD(mp->port_num), (coal & 0x3fff) << 4);
1957 static int mv643xx_eth_open(struct net_device *dev)
1959 struct mv643xx_eth_private *mp = netdev_priv(dev);
1963 wrl(mp, INT_CAUSE(mp->port_num), 0);
1964 wrl(mp, INT_CAUSE_EXT(mp->port_num), 0);
1965 rdl(mp, INT_CAUSE_EXT(mp->port_num));
1967 err = request_irq(dev->irq, mv643xx_eth_irq,
1968 IRQF_SHARED | IRQF_SAMPLE_RANDOM,
1971 dev_printk(KERN_ERR, &dev->dev, "can't assign irq\n");
1975 init_mac_tables(mp);
1977 for (i = 0; i < 8; i++) {
1978 if ((mp->rxq_mask & (1 << i)) == 0)
1981 err = rxq_init(mp, i);
1984 if (mp->rxq_mask & (1 << i))
1985 rxq_deinit(mp->rxq + i);
1989 rxq_refill(mp->rxq + i);
1992 for (i = 0; i < 8; i++) {
1993 if ((mp->txq_mask & (1 << i)) == 0)
1996 err = txq_init(mp, i);
1999 if (mp->txq_mask & (1 << i))
2000 txq_deinit(mp->txq + i);
2005 #ifdef MV643XX_ETH_NAPI
2006 napi_enable(&mp->napi);
2014 wrl(mp, INT_MASK_EXT(mp->port_num),
2015 INT_EXT_LINK | INT_EXT_PHY | INT_EXT_TX);
2017 wrl(mp, INT_MASK(mp->port_num), INT_TX_END | INT_RX | INT_EXT);
2023 for (i = 0; i < 8; i++)
2024 if (mp->rxq_mask & (1 << i))
2025 rxq_deinit(mp->rxq + i);
2027 free_irq(dev->irq, dev);
2032 static void port_reset(struct mv643xx_eth_private *mp)
2037 for (i = 0; i < 8; i++) {
2038 if (mp->rxq_mask & (1 << i))
2039 rxq_disable(mp->rxq + i);
2040 if (mp->txq_mask & (1 << i))
2041 txq_disable(mp->txq + i);
2045 u32 ps = rdl(mp, PORT_STATUS(mp->port_num));
2047 if ((ps & (TX_IN_PROGRESS | TX_FIFO_EMPTY)) == TX_FIFO_EMPTY)
2052 /* Reset the Enable bit in the Configuration Register */
2053 data = rdl(mp, PORT_SERIAL_CONTROL(mp->port_num));
2054 data &= ~(SERIAL_PORT_ENABLE |
2055 DO_NOT_FORCE_LINK_FAIL |
2057 wrl(mp, PORT_SERIAL_CONTROL(mp->port_num), data);
2060 static int mv643xx_eth_stop(struct net_device *dev)
2062 struct mv643xx_eth_private *mp = netdev_priv(dev);
2065 wrl(mp, INT_MASK(mp->port_num), 0x00000000);
2066 rdl(mp, INT_MASK(mp->port_num));
2068 #ifdef MV643XX_ETH_NAPI
2069 napi_disable(&mp->napi);
2071 netif_carrier_off(dev);
2072 netif_stop_queue(dev);
2074 free_irq(dev->irq, dev);
2077 mib_counters_update(mp);
2079 for (i = 0; i < 8; i++) {
2080 if (mp->rxq_mask & (1 << i))
2081 rxq_deinit(mp->rxq + i);
2082 if (mp->txq_mask & (1 << i))
2083 txq_deinit(mp->txq + i);
2089 static int mv643xx_eth_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
2091 struct mv643xx_eth_private *mp = netdev_priv(dev);
2093 if (mp->phy_addr != -1)
2094 return generic_mii_ioctl(&mp->mii, if_mii(ifr), cmd, NULL);
2099 static int mv643xx_eth_change_mtu(struct net_device *dev, int new_mtu)
2101 struct mv643xx_eth_private *mp = netdev_priv(dev);
2103 if (new_mtu < 64 || new_mtu > 9500)
2107 tx_set_rate(mp, 1000000000, 16777216);
2109 if (!netif_running(dev))
2113 * Stop and then re-open the interface. This will allocate RX
2114 * skbs of the new MTU.
2115 * There is a possible danger that the open will not succeed,
2116 * due to memory being full.
2118 mv643xx_eth_stop(dev);
2119 if (mv643xx_eth_open(dev)) {
2120 dev_printk(KERN_ERR, &dev->dev,
2121 "fatal error on re-opening device after "
2128 static void tx_timeout_task(struct work_struct *ugly)
2130 struct mv643xx_eth_private *mp;
2132 mp = container_of(ugly, struct mv643xx_eth_private, tx_timeout_task);
2133 if (netif_running(mp->dev)) {
2134 netif_stop_queue(mp->dev);
2139 __txq_maybe_wake(mp->txq + mp->txq_primary);
2143 static void mv643xx_eth_tx_timeout(struct net_device *dev)
2145 struct mv643xx_eth_private *mp = netdev_priv(dev);
2147 dev_printk(KERN_INFO, &dev->dev, "tx timeout\n");
2149 schedule_work(&mp->tx_timeout_task);
2152 #ifdef CONFIG_NET_POLL_CONTROLLER
2153 static void mv643xx_eth_netpoll(struct net_device *dev)
2155 struct mv643xx_eth_private *mp = netdev_priv(dev);
2157 wrl(mp, INT_MASK(mp->port_num), 0x00000000);
2158 rdl(mp, INT_MASK(mp->port_num));
2160 mv643xx_eth_irq(dev->irq, dev);
2162 wrl(mp, INT_MASK(mp->port_num), INT_TX_END | INT_RX | INT_EXT);
2166 static int mv643xx_eth_mdio_read(struct net_device *dev, int addr, int reg)
2168 struct mv643xx_eth_private *mp = netdev_priv(dev);
2171 smi_reg_read(mp, addr, reg, &val);
2176 static void mv643xx_eth_mdio_write(struct net_device *dev, int addr, int reg, int val)
2178 struct mv643xx_eth_private *mp = netdev_priv(dev);
2179 smi_reg_write(mp, addr, reg, val);
2183 /* platform glue ************************************************************/
2185 mv643xx_eth_conf_mbus_windows(struct mv643xx_eth_shared_private *msp,
2186 struct mbus_dram_target_info *dram)
2188 void __iomem *base = msp->base;
2193 for (i = 0; i < 6; i++) {
2194 writel(0, base + WINDOW_BASE(i));
2195 writel(0, base + WINDOW_SIZE(i));
2197 writel(0, base + WINDOW_REMAP_HIGH(i));
2203 for (i = 0; i < dram->num_cs; i++) {
2204 struct mbus_dram_window *cs = dram->cs + i;
2206 writel((cs->base & 0xffff0000) |
2207 (cs->mbus_attr << 8) |
2208 dram->mbus_dram_target_id, base + WINDOW_BASE(i));
2209 writel((cs->size - 1) & 0xffff0000, base + WINDOW_SIZE(i));
2211 win_enable &= ~(1 << i);
2212 win_protect |= 3 << (2 * i);
2215 writel(win_enable, base + WINDOW_BAR_ENABLE);
2216 msp->win_protect = win_protect;
2219 static void infer_hw_params(struct mv643xx_eth_shared_private *msp)
2222 * Check whether we have a 14-bit coal limit field in bits
2223 * [21:8], or a 16-bit coal limit in bits [25,21:7] of the
2224 * SDMA config register.
2226 writel(0x02000000, msp->base + SDMA_CONFIG(0));
2227 if (readl(msp->base + SDMA_CONFIG(0)) & 0x02000000)
2228 msp->extended_rx_coal_limit = 1;
2230 msp->extended_rx_coal_limit = 0;
2233 * Check whether the TX rate control registers are in the
2234 * old or the new place.
2236 writel(1, msp->base + TX_BW_MTU_MOVED(0));
2237 if (readl(msp->base + TX_BW_MTU_MOVED(0)) & 1)
2238 msp->tx_bw_control_moved = 1;
2240 msp->tx_bw_control_moved = 0;
2243 static int mv643xx_eth_shared_probe(struct platform_device *pdev)
2245 static int mv643xx_eth_version_printed = 0;
2246 struct mv643xx_eth_shared_platform_data *pd = pdev->dev.platform_data;
2247 struct mv643xx_eth_shared_private *msp;
2248 struct resource *res;
2251 if (!mv643xx_eth_version_printed++)
2252 printk(KERN_NOTICE "MV-643xx 10/100/1000 Ethernet Driver\n");
2255 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2260 msp = kmalloc(sizeof(*msp), GFP_KERNEL);
2263 memset(msp, 0, sizeof(*msp));
2265 msp->base = ioremap(res->start, res->end - res->start + 1);
2266 if (msp->base == NULL)
2269 spin_lock_init(&msp->phy_lock);
2272 * (Re-)program MBUS remapping windows if we are asked to.
2274 if (pd != NULL && pd->dram != NULL)
2275 mv643xx_eth_conf_mbus_windows(msp, pd->dram);
2278 * Detect hardware parameters.
2280 msp->t_clk = (pd != NULL && pd->t_clk != 0) ? pd->t_clk : 133000000;
2281 infer_hw_params(msp);
2283 platform_set_drvdata(pdev, msp);
2293 static int mv643xx_eth_shared_remove(struct platform_device *pdev)
2295 struct mv643xx_eth_shared_private *msp = platform_get_drvdata(pdev);
2303 static struct platform_driver mv643xx_eth_shared_driver = {
2304 .probe = mv643xx_eth_shared_probe,
2305 .remove = mv643xx_eth_shared_remove,
2307 .name = MV643XX_ETH_SHARED_NAME,
2308 .owner = THIS_MODULE,
2312 static void phy_addr_set(struct mv643xx_eth_private *mp, int phy_addr)
2314 int addr_shift = 5 * mp->port_num;
2317 data = rdl(mp, PHY_ADDR);
2318 data &= ~(0x1f << addr_shift);
2319 data |= (phy_addr & 0x1f) << addr_shift;
2320 wrl(mp, PHY_ADDR, data);
2323 static int phy_addr_get(struct mv643xx_eth_private *mp)
2327 data = rdl(mp, PHY_ADDR);
2329 return (data >> (5 * mp->port_num)) & 0x1f;
2332 static void set_params(struct mv643xx_eth_private *mp,
2333 struct mv643xx_eth_platform_data *pd)
2335 struct net_device *dev = mp->dev;
2337 if (is_valid_ether_addr(pd->mac_addr))
2338 memcpy(dev->dev_addr, pd->mac_addr, 6);
2340 uc_addr_get(mp, dev->dev_addr);
2342 if (pd->phy_addr == -1) {
2343 mp->shared_smi = NULL;
2346 mp->shared_smi = mp->shared;
2347 if (pd->shared_smi != NULL)
2348 mp->shared_smi = platform_get_drvdata(pd->shared_smi);
2350 if (pd->force_phy_addr || pd->phy_addr) {
2351 mp->phy_addr = pd->phy_addr & 0x3f;
2352 phy_addr_set(mp, mp->phy_addr);
2354 mp->phy_addr = phy_addr_get(mp);
2358 mp->default_rx_ring_size = DEFAULT_RX_QUEUE_SIZE;
2359 if (pd->rx_queue_size)
2360 mp->default_rx_ring_size = pd->rx_queue_size;
2361 mp->rx_desc_sram_addr = pd->rx_sram_addr;
2362 mp->rx_desc_sram_size = pd->rx_sram_size;
2364 if (pd->rx_queue_mask)
2365 mp->rxq_mask = pd->rx_queue_mask;
2367 mp->rxq_mask = 0x01;
2368 mp->rxq_primary = fls(mp->rxq_mask) - 1;
2370 mp->default_tx_ring_size = DEFAULT_TX_QUEUE_SIZE;
2371 if (pd->tx_queue_size)
2372 mp->default_tx_ring_size = pd->tx_queue_size;
2373 mp->tx_desc_sram_addr = pd->tx_sram_addr;
2374 mp->tx_desc_sram_size = pd->tx_sram_size;
2376 if (pd->tx_queue_mask)
2377 mp->txq_mask = pd->tx_queue_mask;
2379 mp->txq_mask = 0x01;
2380 mp->txq_primary = fls(mp->txq_mask) - 1;
2383 static int phy_detect(struct mv643xx_eth_private *mp)
2388 smi_reg_read(mp, mp->phy_addr, 0, &data);
2389 smi_reg_write(mp, mp->phy_addr, 0, data ^ 0x1000);
2391 smi_reg_read(mp, mp->phy_addr, 0, &data2);
2392 if (((data ^ data2) & 0x1000) == 0)
2395 smi_reg_write(mp, mp->phy_addr, 0, data);
2400 static int phy_init(struct mv643xx_eth_private *mp,
2401 struct mv643xx_eth_platform_data *pd)
2403 struct ethtool_cmd cmd;
2406 err = phy_detect(mp);
2408 dev_printk(KERN_INFO, &mp->dev->dev,
2409 "no PHY detected at addr %d\n", mp->phy_addr);
2414 mp->mii.phy_id = mp->phy_addr;
2415 mp->mii.phy_id_mask = 0x3f;
2416 mp->mii.reg_num_mask = 0x1f;
2417 mp->mii.dev = mp->dev;
2418 mp->mii.mdio_read = mv643xx_eth_mdio_read;
2419 mp->mii.mdio_write = mv643xx_eth_mdio_write;
2421 mp->mii.supports_gmii = mii_check_gmii_support(&mp->mii);
2423 memset(&cmd, 0, sizeof(cmd));
2425 cmd.port = PORT_MII;
2426 cmd.transceiver = XCVR_INTERNAL;
2427 cmd.phy_address = mp->phy_addr;
2428 if (pd->speed == 0) {
2429 cmd.autoneg = AUTONEG_ENABLE;
2430 cmd.speed = SPEED_100;
2431 cmd.advertising = ADVERTISED_10baseT_Half |
2432 ADVERTISED_10baseT_Full |
2433 ADVERTISED_100baseT_Half |
2434 ADVERTISED_100baseT_Full;
2435 if (mp->mii.supports_gmii)
2436 cmd.advertising |= ADVERTISED_1000baseT_Full;
2438 cmd.autoneg = AUTONEG_DISABLE;
2439 cmd.speed = pd->speed;
2440 cmd.duplex = pd->duplex;
2443 update_pscr(mp, cmd.speed, cmd.duplex);
2444 mv643xx_eth_set_settings(mp->dev, &cmd);
2449 static int mv643xx_eth_probe(struct platform_device *pdev)
2451 struct mv643xx_eth_platform_data *pd;
2452 struct mv643xx_eth_private *mp;
2453 struct net_device *dev;
2454 struct resource *res;
2455 DECLARE_MAC_BUF(mac);
2458 pd = pdev->dev.platform_data;
2460 dev_printk(KERN_ERR, &pdev->dev,
2461 "no mv643xx_eth_platform_data\n");
2465 if (pd->shared == NULL) {
2466 dev_printk(KERN_ERR, &pdev->dev,
2467 "no mv643xx_eth_platform_data->shared\n");
2471 dev = alloc_etherdev(sizeof(struct mv643xx_eth_private));
2475 mp = netdev_priv(dev);
2476 platform_set_drvdata(pdev, mp);
2478 mp->shared = platform_get_drvdata(pd->shared);
2479 mp->port_num = pd->port_number;
2482 #ifdef MV643XX_ETH_NAPI
2483 netif_napi_add(dev, &mp->napi, mv643xx_eth_poll, 64);
2488 spin_lock_init(&mp->lock);
2490 mib_counters_clear(mp);
2491 INIT_WORK(&mp->tx_timeout_task, tx_timeout_task);
2493 if (mp->phy_addr != -1) {
2494 err = phy_init(mp, pd);
2498 SET_ETHTOOL_OPS(dev, &mv643xx_eth_ethtool_ops);
2500 SET_ETHTOOL_OPS(dev, &mv643xx_eth_ethtool_ops_phyless);
2504 res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
2506 dev->irq = res->start;
2508 dev->hard_start_xmit = mv643xx_eth_xmit;
2509 dev->open = mv643xx_eth_open;
2510 dev->stop = mv643xx_eth_stop;
2511 dev->set_multicast_list = mv643xx_eth_set_rx_mode;
2512 dev->set_mac_address = mv643xx_eth_set_mac_address;
2513 dev->do_ioctl = mv643xx_eth_ioctl;
2514 dev->change_mtu = mv643xx_eth_change_mtu;
2515 dev->tx_timeout = mv643xx_eth_tx_timeout;
2516 #ifdef CONFIG_NET_POLL_CONTROLLER
2517 dev->poll_controller = mv643xx_eth_netpoll;
2519 dev->watchdog_timeo = 2 * HZ;
2522 #ifdef MV643XX_ETH_CHECKSUM_OFFLOAD_TX
2524 * Zero copy can only work if we use Discovery II memory. Else, we will
2525 * have to map the buffers to ISA memory which is only 16 MB
2527 dev->features = NETIF_F_SG | NETIF_F_IP_CSUM;
2530 SET_NETDEV_DEV(dev, &pdev->dev);
2532 if (mp->shared->win_protect)
2533 wrl(mp, WINDOW_PROTECT(mp->port_num), mp->shared->win_protect);
2535 err = register_netdev(dev);
2539 dev_printk(KERN_NOTICE, &dev->dev, "port %d with MAC address %s\n",
2540 mp->port_num, print_mac(mac, dev->dev_addr));
2542 if (dev->features & NETIF_F_SG)
2543 dev_printk(KERN_NOTICE, &dev->dev, "scatter/gather enabled\n");
2545 if (dev->features & NETIF_F_IP_CSUM)
2546 dev_printk(KERN_NOTICE, &dev->dev, "tx checksum offload\n");
2548 #ifdef MV643XX_ETH_NAPI
2549 dev_printk(KERN_NOTICE, &dev->dev, "napi enabled\n");
2552 if (mp->tx_desc_sram_size > 0)
2553 dev_printk(KERN_NOTICE, &dev->dev, "configured with sram\n");
2563 static int mv643xx_eth_remove(struct platform_device *pdev)
2565 struct mv643xx_eth_private *mp = platform_get_drvdata(pdev);
2567 unregister_netdev(mp->dev);
2568 flush_scheduled_work();
2569 free_netdev(mp->dev);
2571 platform_set_drvdata(pdev, NULL);
2576 static void mv643xx_eth_shutdown(struct platform_device *pdev)
2578 struct mv643xx_eth_private *mp = platform_get_drvdata(pdev);
2580 /* Mask all interrupts on ethernet port */
2581 wrl(mp, INT_MASK(mp->port_num), 0);
2582 rdl(mp, INT_MASK(mp->port_num));
2584 if (netif_running(mp->dev))
2588 static struct platform_driver mv643xx_eth_driver = {
2589 .probe = mv643xx_eth_probe,
2590 .remove = mv643xx_eth_remove,
2591 .shutdown = mv643xx_eth_shutdown,
2593 .name = MV643XX_ETH_NAME,
2594 .owner = THIS_MODULE,
2598 static int __init mv643xx_eth_init_module(void)
2602 rc = platform_driver_register(&mv643xx_eth_shared_driver);
2604 rc = platform_driver_register(&mv643xx_eth_driver);
2606 platform_driver_unregister(&mv643xx_eth_shared_driver);
2611 module_init(mv643xx_eth_init_module);
2613 static void __exit mv643xx_eth_cleanup_module(void)
2615 platform_driver_unregister(&mv643xx_eth_driver);
2616 platform_driver_unregister(&mv643xx_eth_shared_driver);
2618 module_exit(mv643xx_eth_cleanup_module);
2620 MODULE_AUTHOR("Rabeeh Khoury, Assaf Hoffman, Matthew Dharm, "
2621 "Manish Lachwani, Dale Farnsworth and Lennert Buytenhek");
2622 MODULE_DESCRIPTION("Ethernet driver for Marvell MV643XX");
2623 MODULE_LICENSE("GPL");
2624 MODULE_ALIAS("platform:" MV643XX_ETH_SHARED_NAME);
2625 MODULE_ALIAS("platform:" MV643XX_ETH_NAME);