2 * Driver for Marvell Discovery (MV643XX) and Marvell Orion ethernet ports
3 * Copyright (C) 2002 Matthew Dharm <mdharm@momenco.com>
5 * Based on the 64360 driver from:
6 * Copyright (C) 2002 Rabeeh Khoury <rabeeh@galileo.co.il>
7 * Rabeeh Khoury <rabeeh@marvell.com>
9 * Copyright (C) 2003 PMC-Sierra, Inc.,
10 * written by Manish Lachwani
12 * Copyright (C) 2003 Ralf Baechle <ralf@linux-mips.org>
14 * Copyright (C) 2004-2006 MontaVista Software, Inc.
15 * Dale Farnsworth <dale@farnsworth.org>
17 * Copyright (C) 2004 Steven J. Hill <sjhill1@rockwellcollins.com>
18 * <sjhill@realitydiluted.com>
20 * Copyright (C) 2007-2008 Marvell Semiconductor
21 * Lennert Buytenhek <buytenh@marvell.com>
23 * This program is free software; you can redistribute it and/or
24 * modify it under the terms of the GNU General Public License
25 * as published by the Free Software Foundation; either version 2
26 * of the License, or (at your option) any later version.
28 * This program is distributed in the hope that it will be useful,
29 * but WITHOUT ANY WARRANTY; without even the implied warranty of
30 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
31 * GNU General Public License for more details.
33 * You should have received a copy of the GNU General Public License
34 * along with this program; if not, write to the Free Software
35 * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
38 #include <linux/init.h>
39 #include <linux/dma-mapping.h>
41 #include <linux/tcp.h>
42 #include <linux/udp.h>
43 #include <linux/etherdevice.h>
44 #include <linux/delay.h>
45 #include <linux/ethtool.h>
46 #include <linux/platform_device.h>
47 #include <linux/module.h>
48 #include <linux/kernel.h>
49 #include <linux/spinlock.h>
50 #include <linux/workqueue.h>
51 #include <linux/mii.h>
52 #include <linux/mv643xx_eth.h>
54 #include <asm/types.h>
55 #include <asm/system.h>
57 static char mv643xx_eth_driver_name[] = "mv643xx_eth";
58 static char mv643xx_eth_driver_version[] = "1.0";
60 #define MV643XX_ETH_CHECKSUM_OFFLOAD_TX
61 #define MV643XX_ETH_NAPI
62 #define MV643XX_ETH_TX_FAST_REFILL
63 #undef MV643XX_ETH_COAL
65 #define MV643XX_ETH_TX_COAL 100
66 #ifdef MV643XX_ETH_COAL
67 #define MV643XX_ETH_RX_COAL 100
70 #ifdef MV643XX_ETH_CHECKSUM_OFFLOAD_TX
71 #define MAX_DESCS_PER_SKB (MAX_SKB_FRAGS + 1)
73 #define MAX_DESCS_PER_SKB 1
76 #define ETH_VLAN_HLEN 4
78 #define ETH_HW_IP_ALIGN 2 /* hw aligns IP header */
79 #define ETH_WRAPPER_LEN (ETH_HW_IP_ALIGN + ETH_HLEN + \
80 ETH_VLAN_HLEN + ETH_FCS_LEN)
81 #define ETH_RX_SKB_SIZE (dev->mtu + ETH_WRAPPER_LEN + \
82 dma_get_cache_alignment())
85 * Registers shared between all ports.
87 #define PHY_ADDR 0x0000
88 #define SMI_REG 0x0004
89 #define WINDOW_BASE(w) (0x0200 + ((w) << 3))
90 #define WINDOW_SIZE(w) (0x0204 + ((w) << 3))
91 #define WINDOW_REMAP_HIGH(w) (0x0280 + ((w) << 2))
92 #define WINDOW_BAR_ENABLE 0x0290
93 #define WINDOW_PROTECT(w) (0x0294 + ((w) << 4))
98 #define PORT_CONFIG(p) (0x0400 + ((p) << 10))
99 #define UNICAST_PROMISCUOUS_MODE 0x00000001
100 #define PORT_CONFIG_EXT(p) (0x0404 + ((p) << 10))
101 #define MAC_ADDR_LOW(p) (0x0414 + ((p) << 10))
102 #define MAC_ADDR_HIGH(p) (0x0418 + ((p) << 10))
103 #define SDMA_CONFIG(p) (0x041c + ((p) << 10))
104 #define PORT_SERIAL_CONTROL(p) (0x043c + ((p) << 10))
105 #define PORT_STATUS(p) (0x0444 + ((p) << 10))
106 #define TX_FIFO_EMPTY 0x00000400
107 #define TXQ_COMMAND(p) (0x0448 + ((p) << 10))
108 #define TX_BW_MTU(p) (0x0458 + ((p) << 10))
109 #define INT_CAUSE(p) (0x0460 + ((p) << 10))
110 #define INT_RX 0x00000804
111 #define INT_EXT 0x00000002
112 #define INT_CAUSE_EXT(p) (0x0464 + ((p) << 10))
113 #define INT_EXT_LINK 0x00100000
114 #define INT_EXT_PHY 0x00010000
115 #define INT_EXT_TX_ERROR_0 0x00000100
116 #define INT_EXT_TX_0 0x00000001
117 #define INT_EXT_TX 0x00000101
118 #define INT_MASK(p) (0x0468 + ((p) << 10))
119 #define INT_MASK_EXT(p) (0x046c + ((p) << 10))
120 #define TX_FIFO_URGENT_THRESHOLD(p) (0x0474 + ((p) << 10))
121 #define RXQ_CURRENT_DESC_PTR(p) (0x060c + ((p) << 10))
122 #define RXQ_COMMAND(p) (0x0680 + ((p) << 10))
123 #define TXQ_CURRENT_DESC_PTR(p) (0x06c0 + ((p) << 10))
124 #define MIB_COUNTERS(p) (0x1000 + ((p) << 7))
125 #define SPECIAL_MCAST_TABLE(p) (0x1400 + ((p) << 10))
126 #define OTHER_MCAST_TABLE(p) (0x1500 + ((p) << 10))
127 #define UNICAST_TABLE(p) (0x1600 + ((p) << 10))
131 * SDMA configuration register.
133 #define RX_BURST_SIZE_4_64BIT (2 << 1)
134 #define BLM_RX_NO_SWAP (1 << 4)
135 #define BLM_TX_NO_SWAP (1 << 5)
136 #define TX_BURST_SIZE_4_64BIT (2 << 22)
138 #if defined(__BIG_ENDIAN)
139 #define PORT_SDMA_CONFIG_DEFAULT_VALUE \
140 RX_BURST_SIZE_4_64BIT | \
141 TX_BURST_SIZE_4_64BIT
142 #elif defined(__LITTLE_ENDIAN)
143 #define PORT_SDMA_CONFIG_DEFAULT_VALUE \
144 RX_BURST_SIZE_4_64BIT | \
147 TX_BURST_SIZE_4_64BIT
149 #error One of __BIG_ENDIAN or __LITTLE_ENDIAN must be defined
154 * Port serial control register.
156 #define SET_MII_SPEED_TO_100 (1 << 24)
157 #define SET_GMII_SPEED_TO_1000 (1 << 23)
158 #define SET_FULL_DUPLEX_MODE (1 << 21)
159 #define MAX_RX_PACKET_1522BYTE (1 << 17)
160 #define MAX_RX_PACKET_9700BYTE (5 << 17)
161 #define MAX_RX_PACKET_MASK (7 << 17)
162 #define DISABLE_AUTO_NEG_SPEED_GMII (1 << 13)
163 #define DO_NOT_FORCE_LINK_FAIL (1 << 10)
164 #define SERIAL_PORT_CONTROL_RESERVED (1 << 9)
165 #define DISABLE_AUTO_NEG_FOR_FLOW_CTRL (1 << 3)
166 #define DISABLE_AUTO_NEG_FOR_DUPLEX (1 << 2)
167 #define FORCE_LINK_PASS (1 << 1)
168 #define SERIAL_PORT_ENABLE (1 << 0)
170 #define DEFAULT_RX_QUEUE_SIZE 400
171 #define DEFAULT_TX_QUEUE_SIZE 800
174 #define SMI_BUSY 0x10000000 /* 0 - Write, 1 - Read */
175 #define SMI_READ_VALID 0x08000000 /* 0 - Write, 1 - Read */
176 #define SMI_OPCODE_WRITE 0 /* Completion of Read */
177 #define SMI_OPCODE_READ 0x04000000 /* Operation is in progress */
181 typedef enum _func_ret_status {
182 ETH_OK, /* Returned as expected. */
183 ETH_ERROR, /* Fundamental error. */
184 ETH_RETRY, /* Could not process request. Try later.*/
185 ETH_END_OF_JOB, /* Ring has nothing to process. */
186 ETH_QUEUE_FULL, /* Ring resource error. */
187 ETH_QUEUE_LAST_RESOURCE /* Ring resources about to exhaust. */
193 #if defined(__BIG_ENDIAN)
195 u16 byte_cnt; /* Descriptor buffer byte count */
196 u16 buf_size; /* Buffer size */
197 u32 cmd_sts; /* Descriptor command status */
198 u32 next_desc_ptr; /* Next descriptor pointer */
199 u32 buf_ptr; /* Descriptor buffer pointer */
203 u16 byte_cnt; /* buffer byte count */
204 u16 l4i_chk; /* CPU provided TCP checksum */
205 u32 cmd_sts; /* Command/status field */
206 u32 next_desc_ptr; /* Pointer to next descriptor */
207 u32 buf_ptr; /* pointer to buffer for this descriptor*/
209 #elif defined(__LITTLE_ENDIAN)
211 u32 cmd_sts; /* Descriptor command status */
212 u16 buf_size; /* Buffer size */
213 u16 byte_cnt; /* Descriptor buffer byte count */
214 u32 buf_ptr; /* Descriptor buffer pointer */
215 u32 next_desc_ptr; /* Next descriptor pointer */
219 u32 cmd_sts; /* Command/status field */
220 u16 l4i_chk; /* CPU provided TCP checksum */
221 u16 byte_cnt; /* buffer byte count */
222 u32 buf_ptr; /* pointer to buffer for this descriptor*/
223 u32 next_desc_ptr; /* Pointer to next descriptor */
226 #error One of __BIG_ENDIAN or __LITTLE_ENDIAN must be defined
229 /* RX & TX descriptor command */
230 #define BUFFER_OWNED_BY_DMA 0x80000000
232 /* RX & TX descriptor status */
233 #define ERROR_SUMMARY 0x00000001
235 /* RX descriptor status */
236 #define LAYER_4_CHECKSUM_OK 0x40000000
237 #define RX_ENABLE_INTERRUPT 0x20000000
238 #define RX_FIRST_DESC 0x08000000
239 #define RX_LAST_DESC 0x04000000
241 /* TX descriptor command */
242 #define TX_ENABLE_INTERRUPT 0x00800000
243 #define GEN_CRC 0x00400000
244 #define TX_FIRST_DESC 0x00200000
245 #define TX_LAST_DESC 0x00100000
246 #define ZERO_PADDING 0x00080000
247 #define GEN_IP_V4_CHECKSUM 0x00040000
248 #define GEN_TCP_UDP_CHECKSUM 0x00020000
249 #define UDP_FRAME 0x00010000
251 #define TX_IHL_SHIFT 11
254 /* Unified struct for Rx and Tx operations. The user is not required to */
255 /* be familier with neither Tx nor Rx descriptors. */
257 unsigned short byte_cnt; /* Descriptor buffer byte count */
258 unsigned short l4i_chk; /* Tx CPU provided TCP Checksum */
259 unsigned int cmd_sts; /* Descriptor command status */
260 dma_addr_t buf_ptr; /* Descriptor buffer pointer */
261 struct sk_buff *return_info; /* User resource return information */
265 /* global *******************************************************************/
266 struct mv643xx_eth_shared_private {
269 /* used to protect SMI_REG, which is shared across ports */
278 /* per-port *****************************************************************/
279 struct mib_counters {
280 u64 good_octets_received;
281 u32 bad_octets_received;
282 u32 internal_mac_transmit_err;
283 u32 good_frames_received;
284 u32 bad_frames_received;
285 u32 broadcast_frames_received;
286 u32 multicast_frames_received;
287 u32 frames_64_octets;
288 u32 frames_65_to_127_octets;
289 u32 frames_128_to_255_octets;
290 u32 frames_256_to_511_octets;
291 u32 frames_512_to_1023_octets;
292 u32 frames_1024_to_max_octets;
293 u64 good_octets_sent;
294 u32 good_frames_sent;
295 u32 excessive_collision;
296 u32 multicast_frames_sent;
297 u32 broadcast_frames_sent;
298 u32 unrec_mac_control_received;
300 u32 good_fc_received;
302 u32 undersize_received;
303 u32 fragments_received;
304 u32 oversize_received;
306 u32 mac_receive_error;
312 struct mv643xx_eth_private {
313 struct mv643xx_eth_shared_private *shared;
314 int port_num; /* User Ethernet port number */
316 struct mv643xx_eth_shared_private *shared_smi;
318 u32 rx_sram_addr; /* Base address of rx sram area */
319 u32 rx_sram_size; /* Size of rx sram area */
320 u32 tx_sram_addr; /* Base address of tx sram area */
321 u32 tx_sram_size; /* Size of tx sram area */
323 /* Tx/Rx rings managment indexes fields. For driver use */
325 /* Next available and first returning Rx resource */
326 int rx_curr_desc, rx_used_desc;
328 /* Next available and first returning Tx resource */
329 int tx_curr_desc, tx_used_desc;
331 #ifdef MV643XX_ETH_TX_FAST_REFILL
332 u32 tx_clean_threshold;
335 struct rx_desc *rx_desc_area;
336 dma_addr_t rx_desc_dma;
337 int rx_desc_area_size;
338 struct sk_buff **rx_skb;
340 struct tx_desc *tx_desc_area;
341 dma_addr_t tx_desc_dma;
342 int tx_desc_area_size;
343 struct sk_buff **tx_skb;
345 struct work_struct tx_timeout_task;
347 struct net_device *dev;
348 struct napi_struct napi;
349 struct net_device_stats stats;
350 struct mib_counters mib_counters;
352 /* Size of Tx Ring per queue */
354 /* Number of tx descriptors in use */
356 /* Size of Rx Ring per queue */
358 /* Number of rx descriptors in use */
362 * Used in case RX Ring is empty, which can be caused when
363 * system does not have resources (skb's)
365 struct timer_list timeout;
369 struct mii_if_info mii;
373 /* port register accessors **************************************************/
374 static inline u32 rdl(struct mv643xx_eth_private *mp, int offset)
376 return readl(mp->shared->base + offset);
379 static inline void wrl(struct mv643xx_eth_private *mp, int offset, u32 data)
381 writel(data, mp->shared->base + offset);
385 /* rxq/txq helper functions *************************************************/
386 static void mv643xx_eth_port_enable_rx(struct mv643xx_eth_private *mp,
389 wrl(mp, RXQ_COMMAND(mp->port_num), queues);
392 static unsigned int mv643xx_eth_port_disable_rx(struct mv643xx_eth_private *mp)
394 unsigned int port_num = mp->port_num;
397 /* Stop Rx port activity. Check port Rx activity. */
398 queues = rdl(mp, RXQ_COMMAND(port_num)) & 0xFF;
400 /* Issue stop command for active queues only */
401 wrl(mp, RXQ_COMMAND(port_num), (queues << 8));
403 /* Wait for all Rx activity to terminate. */
404 /* Check port cause register that all Rx queues are stopped */
405 while (rdl(mp, RXQ_COMMAND(port_num)) & 0xFF)
412 static void mv643xx_eth_port_enable_tx(struct mv643xx_eth_private *mp,
415 wrl(mp, TXQ_COMMAND(mp->port_num), queues);
418 static unsigned int mv643xx_eth_port_disable_tx(struct mv643xx_eth_private *mp)
420 unsigned int port_num = mp->port_num;
423 /* Stop Tx port activity. Check port Tx activity. */
424 queues = rdl(mp, TXQ_COMMAND(port_num)) & 0xFF;
426 /* Issue stop command for active queues only */
427 wrl(mp, TXQ_COMMAND(port_num), (queues << 8));
429 /* Wait for all Tx activity to terminate. */
430 /* Check port cause register that all Tx queues are stopped */
431 while (rdl(mp, TXQ_COMMAND(port_num)) & 0xFF)
434 /* Wait for Tx FIFO to empty */
435 while (rdl(mp, PORT_STATUS(port_num)) & TX_FIFO_EMPTY)
443 /* rx ***********************************************************************/
444 static void mv643xx_eth_free_completed_tx_descs(struct net_device *dev);
446 static FUNC_RET_STATUS rx_return_buff(struct mv643xx_eth_private *mp,
447 struct pkt_info *pkt_info)
449 int used_rx_desc; /* Where to return Rx resource */
450 volatile struct rx_desc *rx_desc;
453 spin_lock_irqsave(&mp->lock, flags);
455 /* Get 'used' Rx descriptor */
456 used_rx_desc = mp->rx_used_desc;
457 rx_desc = &mp->rx_desc_area[used_rx_desc];
459 rx_desc->buf_ptr = pkt_info->buf_ptr;
460 rx_desc->buf_size = pkt_info->byte_cnt;
461 mp->rx_skb[used_rx_desc] = pkt_info->return_info;
463 /* Flush the write pipe */
465 /* Return the descriptor to DMA ownership */
467 rx_desc->cmd_sts = BUFFER_OWNED_BY_DMA | RX_ENABLE_INTERRUPT;
470 /* Move the used descriptor pointer to the next descriptor */
471 mp->rx_used_desc = (used_rx_desc + 1) % mp->rx_ring_size;
473 spin_unlock_irqrestore(&mp->lock, flags);
478 static void mv643xx_eth_rx_refill_descs(struct net_device *dev)
480 struct mv643xx_eth_private *mp = netdev_priv(dev);
481 struct pkt_info pkt_info;
485 while (mp->rx_desc_count < mp->rx_ring_size) {
486 skb = dev_alloc_skb(ETH_RX_SKB_SIZE + dma_get_cache_alignment());
490 unaligned = (u32)skb->data & (dma_get_cache_alignment() - 1);
492 skb_reserve(skb, dma_get_cache_alignment() - unaligned);
493 pkt_info.cmd_sts = RX_ENABLE_INTERRUPT;
494 pkt_info.byte_cnt = ETH_RX_SKB_SIZE;
495 pkt_info.buf_ptr = dma_map_single(NULL, skb->data,
496 ETH_RX_SKB_SIZE, DMA_FROM_DEVICE);
497 pkt_info.return_info = skb;
498 if (rx_return_buff(mp, &pkt_info) != ETH_OK) {
500 "%s: Error allocating RX Ring\n", dev->name);
503 skb_reserve(skb, ETH_HW_IP_ALIGN);
506 * If RX ring is empty of SKB, set a timer to try allocating
507 * again at a later time.
509 if (mp->rx_desc_count == 0) {
510 printk(KERN_INFO "%s: Rx ring is empty\n", dev->name);
511 mp->timeout.expires = jiffies + (HZ / 10); /* 100 mSec */
512 add_timer(&mp->timeout);
516 static inline void mv643xx_eth_rx_refill_descs_timer_wrapper(unsigned long data)
518 mv643xx_eth_rx_refill_descs((struct net_device *)data);
521 static int mv643xx_eth_receive_queue(struct net_device *dev, int budget)
523 struct mv643xx_eth_private *mp = netdev_priv(dev);
524 struct net_device_stats *stats = &dev->stats;
525 unsigned int received_packets = 0;
527 while (budget-- > 0) {
529 volatile struct rx_desc *rx_desc;
530 unsigned int cmd_sts;
533 spin_lock_irqsave(&mp->lock, flags);
535 rx_desc = &mp->rx_desc_area[mp->rx_curr_desc];
537 cmd_sts = rx_desc->cmd_sts;
538 if (cmd_sts & BUFFER_OWNED_BY_DMA) {
539 spin_unlock_irqrestore(&mp->lock, flags);
544 skb = mp->rx_skb[mp->rx_curr_desc];
545 mp->rx_skb[mp->rx_curr_desc] = NULL;
547 mp->rx_curr_desc = (mp->rx_curr_desc + 1) % mp->rx_ring_size;
549 spin_unlock_irqrestore(&mp->lock, flags);
551 dma_unmap_single(NULL, rx_desc->buf_ptr + ETH_HW_IP_ALIGN,
552 ETH_RX_SKB_SIZE, DMA_FROM_DEVICE);
558 * Note byte count includes 4 byte CRC count
561 stats->rx_bytes += rx_desc->byte_cnt - ETH_HW_IP_ALIGN;
564 * In case received a packet without first / last bits on OR
565 * the error summary bit is on, the packets needs to be dropeed.
567 if (((cmd_sts & (RX_FIRST_DESC | RX_LAST_DESC)) !=
568 (RX_FIRST_DESC | RX_LAST_DESC))
569 || (cmd_sts & ERROR_SUMMARY)) {
571 if ((cmd_sts & (RX_FIRST_DESC | RX_LAST_DESC)) !=
572 (RX_FIRST_DESC | RX_LAST_DESC)) {
575 "%s: Received packet spread "
576 "on multiple descriptors\n",
579 if (cmd_sts & ERROR_SUMMARY)
582 dev_kfree_skb_irq(skb);
585 * The -4 is for the CRC in the trailer of the
588 skb_put(skb, rx_desc->byte_cnt - ETH_HW_IP_ALIGN - 4);
590 if (cmd_sts & LAYER_4_CHECKSUM_OK) {
591 skb->ip_summed = CHECKSUM_UNNECESSARY;
593 (cmd_sts & 0x0007fff8) >> 3);
595 skb->protocol = eth_type_trans(skb, dev);
596 #ifdef MV643XX_ETH_NAPI
597 netif_receive_skb(skb);
602 dev->last_rx = jiffies;
604 mv643xx_eth_rx_refill_descs(dev); /* Fill RX ring with skb's */
606 return received_packets;
609 #ifdef MV643XX_ETH_NAPI
610 static int mv643xx_eth_poll(struct napi_struct *napi, int budget)
612 struct mv643xx_eth_private *mp = container_of(napi, struct mv643xx_eth_private, napi);
613 struct net_device *dev = mp->dev;
614 unsigned int port_num = mp->port_num;
617 #ifdef MV643XX_ETH_TX_FAST_REFILL
618 if (++mp->tx_clean_threshold > 5) {
619 mv643xx_eth_free_completed_tx_descs(dev);
620 mp->tx_clean_threshold = 0;
625 if ((rdl(mp, RXQ_CURRENT_DESC_PTR(port_num)))
626 != (u32) mp->rx_used_desc)
627 work_done = mv643xx_eth_receive_queue(dev, budget);
629 if (work_done < budget) {
630 netif_rx_complete(dev, napi);
631 wrl(mp, INT_CAUSE(port_num), 0);
632 wrl(mp, INT_CAUSE_EXT(port_num), 0);
633 wrl(mp, INT_MASK(port_num), INT_RX | INT_EXT);
641 /* tx ***********************************************************************/
642 static inline unsigned int has_tiny_unaligned_frags(struct sk_buff *skb)
647 for (frag = 0; frag < skb_shinfo(skb)->nr_frags; frag++) {
648 fragp = &skb_shinfo(skb)->frags[frag];
649 if (fragp->size <= 8 && fragp->page_offset & 0x7)
655 static int alloc_tx_desc_index(struct mv643xx_eth_private *mp)
659 BUG_ON(mp->tx_desc_count >= mp->tx_ring_size);
661 tx_desc_curr = mp->tx_curr_desc;
662 mp->tx_curr_desc = (tx_desc_curr + 1) % mp->tx_ring_size;
664 BUG_ON(mp->tx_curr_desc == mp->tx_used_desc);
669 static void tx_fill_frag_descs(struct mv643xx_eth_private *mp,
674 struct tx_desc *desc;
676 for (frag = 0; frag < skb_shinfo(skb)->nr_frags; frag++) {
677 skb_frag_t *this_frag = &skb_shinfo(skb)->frags[frag];
679 tx_index = alloc_tx_desc_index(mp);
680 desc = &mp->tx_desc_area[tx_index];
682 desc->cmd_sts = BUFFER_OWNED_BY_DMA;
683 /* Last Frag enables interrupt and frees the skb */
684 if (frag == (skb_shinfo(skb)->nr_frags - 1)) {
685 desc->cmd_sts |= ZERO_PADDING |
688 mp->tx_skb[tx_index] = skb;
690 mp->tx_skb[tx_index] = NULL;
692 desc = &mp->tx_desc_area[tx_index];
694 desc->byte_cnt = this_frag->size;
695 desc->buf_ptr = dma_map_page(NULL, this_frag->page,
696 this_frag->page_offset,
702 static inline __be16 sum16_as_be(__sum16 sum)
704 return (__force __be16)sum;
707 static void tx_submit_descs_for_skb(struct mv643xx_eth_private *mp,
711 struct tx_desc *desc;
714 int nr_frags = skb_shinfo(skb)->nr_frags;
716 cmd_sts = TX_FIRST_DESC | GEN_CRC | BUFFER_OWNED_BY_DMA;
718 tx_index = alloc_tx_desc_index(mp);
719 desc = &mp->tx_desc_area[tx_index];
722 tx_fill_frag_descs(mp, skb);
724 length = skb_headlen(skb);
725 mp->tx_skb[tx_index] = NULL;
727 cmd_sts |= ZERO_PADDING | TX_LAST_DESC | TX_ENABLE_INTERRUPT;
729 mp->tx_skb[tx_index] = skb;
732 desc->byte_cnt = length;
733 desc->buf_ptr = dma_map_single(NULL, skb->data, length, DMA_TO_DEVICE);
735 if (skb->ip_summed == CHECKSUM_PARTIAL) {
736 BUG_ON(skb->protocol != htons(ETH_P_IP));
738 cmd_sts |= GEN_TCP_UDP_CHECKSUM |
740 ip_hdr(skb)->ihl << TX_IHL_SHIFT;
742 switch (ip_hdr(skb)->protocol) {
744 cmd_sts |= UDP_FRAME;
745 desc->l4i_chk = ntohs(sum16_as_be(udp_hdr(skb)->check));
748 desc->l4i_chk = ntohs(sum16_as_be(tcp_hdr(skb)->check));
754 /* Errata BTS #50, IHL must be 5 if no HW checksum */
755 cmd_sts |= 5 << TX_IHL_SHIFT;
759 /* ensure all other descriptors are written before first cmd_sts */
761 desc->cmd_sts = cmd_sts;
763 /* ensure all descriptors are written before poking hardware */
765 mv643xx_eth_port_enable_tx(mp, 1);
767 mp->tx_desc_count += nr_frags + 1;
770 static int mv643xx_eth_start_xmit(struct sk_buff *skb, struct net_device *dev)
772 struct mv643xx_eth_private *mp = netdev_priv(dev);
773 struct net_device_stats *stats = &dev->stats;
776 BUG_ON(netif_queue_stopped(dev));
778 if (has_tiny_unaligned_frags(skb) && __skb_linearize(skb)) {
780 printk(KERN_DEBUG "%s: failed to linearize tiny "
781 "unaligned fragment\n", dev->name);
782 return NETDEV_TX_BUSY;
785 spin_lock_irqsave(&mp->lock, flags);
787 if (mp->tx_ring_size - mp->tx_desc_count < MAX_DESCS_PER_SKB) {
788 printk(KERN_ERR "%s: transmit with queue full\n", dev->name);
789 netif_stop_queue(dev);
790 spin_unlock_irqrestore(&mp->lock, flags);
791 return NETDEV_TX_BUSY;
794 tx_submit_descs_for_skb(mp, skb);
795 stats->tx_bytes += skb->len;
797 dev->trans_start = jiffies;
799 if (mp->tx_ring_size - mp->tx_desc_count < MAX_DESCS_PER_SKB)
800 netif_stop_queue(dev);
802 spin_unlock_irqrestore(&mp->lock, flags);
808 /* mii management interface *************************************************/
809 static int phy_addr_get(struct mv643xx_eth_private *mp);
811 static void read_smi_reg(struct mv643xx_eth_private *mp,
812 unsigned int phy_reg, unsigned int *value)
814 void __iomem *smi_reg = mp->shared_smi->base + SMI_REG;
815 int phy_addr = phy_addr_get(mp);
819 /* the SMI register is a shared resource */
820 spin_lock_irqsave(&mp->shared_smi->phy_lock, flags);
822 /* wait for the SMI register to become available */
823 for (i = 0; readl(smi_reg) & SMI_BUSY; i++) {
825 printk("%s: PHY busy timeout\n", mp->dev->name);
831 writel((phy_addr << 16) | (phy_reg << 21) | SMI_OPCODE_READ, smi_reg);
833 /* now wait for the data to be valid */
834 for (i = 0; !(readl(smi_reg) & SMI_READ_VALID); i++) {
836 printk("%s: PHY read timeout\n", mp->dev->name);
842 *value = readl(smi_reg) & 0xffff;
844 spin_unlock_irqrestore(&mp->shared_smi->phy_lock, flags);
847 static void write_smi_reg(struct mv643xx_eth_private *mp,
848 unsigned int phy_reg, unsigned int value)
850 void __iomem *smi_reg = mp->shared_smi->base + SMI_REG;
851 int phy_addr = phy_addr_get(mp);
855 /* the SMI register is a shared resource */
856 spin_lock_irqsave(&mp->shared_smi->phy_lock, flags);
858 /* wait for the SMI register to become available */
859 for (i = 0; readl(smi_reg) & SMI_BUSY; i++) {
861 printk("%s: PHY busy timeout\n", mp->dev->name);
867 writel((phy_addr << 16) | (phy_reg << 21) |
868 SMI_OPCODE_WRITE | (value & 0xffff), smi_reg);
870 spin_unlock_irqrestore(&mp->shared_smi->phy_lock, flags);
874 /* mib counters *************************************************************/
875 static void clear_mib_counters(struct mv643xx_eth_private *mp)
877 unsigned int port_num = mp->port_num;
880 /* Perform dummy reads from MIB counters */
881 for (i = 0; i < 0x80; i += 4)
882 rdl(mp, MIB_COUNTERS(port_num) + i);
885 static inline u32 read_mib(struct mv643xx_eth_private *mp, int offset)
887 return rdl(mp, MIB_COUNTERS(mp->port_num) + offset);
890 static void update_mib_counters(struct mv643xx_eth_private *mp)
892 struct mib_counters *p = &mp->mib_counters;
894 p->good_octets_received += read_mib(mp, 0x00);
895 p->good_octets_received += (u64)read_mib(mp, 0x04) << 32;
896 p->bad_octets_received += read_mib(mp, 0x08);
897 p->internal_mac_transmit_err += read_mib(mp, 0x0c);
898 p->good_frames_received += read_mib(mp, 0x10);
899 p->bad_frames_received += read_mib(mp, 0x14);
900 p->broadcast_frames_received += read_mib(mp, 0x18);
901 p->multicast_frames_received += read_mib(mp, 0x1c);
902 p->frames_64_octets += read_mib(mp, 0x20);
903 p->frames_65_to_127_octets += read_mib(mp, 0x24);
904 p->frames_128_to_255_octets += read_mib(mp, 0x28);
905 p->frames_256_to_511_octets += read_mib(mp, 0x2c);
906 p->frames_512_to_1023_octets += read_mib(mp, 0x30);
907 p->frames_1024_to_max_octets += read_mib(mp, 0x34);
908 p->good_octets_sent += read_mib(mp, 0x38);
909 p->good_octets_sent += (u64)read_mib(mp, 0x3c) << 32;
910 p->good_frames_sent += read_mib(mp, 0x40);
911 p->excessive_collision += read_mib(mp, 0x44);
912 p->multicast_frames_sent += read_mib(mp, 0x48);
913 p->broadcast_frames_sent += read_mib(mp, 0x4c);
914 p->unrec_mac_control_received += read_mib(mp, 0x50);
915 p->fc_sent += read_mib(mp, 0x54);
916 p->good_fc_received += read_mib(mp, 0x58);
917 p->bad_fc_received += read_mib(mp, 0x5c);
918 p->undersize_received += read_mib(mp, 0x60);
919 p->fragments_received += read_mib(mp, 0x64);
920 p->oversize_received += read_mib(mp, 0x68);
921 p->jabber_received += read_mib(mp, 0x6c);
922 p->mac_receive_error += read_mib(mp, 0x70);
923 p->bad_crc_event += read_mib(mp, 0x74);
924 p->collision += read_mib(mp, 0x78);
925 p->late_collision += read_mib(mp, 0x7c);
929 /* ethtool ******************************************************************/
930 struct mv643xx_eth_stats {
931 char stat_string[ETH_GSTRING_LEN];
936 #define MV643XX_ETH_STAT(m) FIELD_SIZEOF(struct mv643xx_eth_private, m), \
937 offsetof(struct mv643xx_eth_private, m)
939 static const struct mv643xx_eth_stats mv643xx_eth_gstrings_stats[] = {
940 { "rx_packets", MV643XX_ETH_STAT(stats.rx_packets) },
941 { "tx_packets", MV643XX_ETH_STAT(stats.tx_packets) },
942 { "rx_bytes", MV643XX_ETH_STAT(stats.rx_bytes) },
943 { "tx_bytes", MV643XX_ETH_STAT(stats.tx_bytes) },
944 { "rx_errors", MV643XX_ETH_STAT(stats.rx_errors) },
945 { "tx_errors", MV643XX_ETH_STAT(stats.tx_errors) },
946 { "rx_dropped", MV643XX_ETH_STAT(stats.rx_dropped) },
947 { "tx_dropped", MV643XX_ETH_STAT(stats.tx_dropped) },
948 { "good_octets_received", MV643XX_ETH_STAT(mib_counters.good_octets_received) },
949 { "bad_octets_received", MV643XX_ETH_STAT(mib_counters.bad_octets_received) },
950 { "internal_mac_transmit_err", MV643XX_ETH_STAT(mib_counters.internal_mac_transmit_err) },
951 { "good_frames_received", MV643XX_ETH_STAT(mib_counters.good_frames_received) },
952 { "bad_frames_received", MV643XX_ETH_STAT(mib_counters.bad_frames_received) },
953 { "broadcast_frames_received", MV643XX_ETH_STAT(mib_counters.broadcast_frames_received) },
954 { "multicast_frames_received", MV643XX_ETH_STAT(mib_counters.multicast_frames_received) },
955 { "frames_64_octets", MV643XX_ETH_STAT(mib_counters.frames_64_octets) },
956 { "frames_65_to_127_octets", MV643XX_ETH_STAT(mib_counters.frames_65_to_127_octets) },
957 { "frames_128_to_255_octets", MV643XX_ETH_STAT(mib_counters.frames_128_to_255_octets) },
958 { "frames_256_to_511_octets", MV643XX_ETH_STAT(mib_counters.frames_256_to_511_octets) },
959 { "frames_512_to_1023_octets", MV643XX_ETH_STAT(mib_counters.frames_512_to_1023_octets) },
960 { "frames_1024_to_max_octets", MV643XX_ETH_STAT(mib_counters.frames_1024_to_max_octets) },
961 { "good_octets_sent", MV643XX_ETH_STAT(mib_counters.good_octets_sent) },
962 { "good_frames_sent", MV643XX_ETH_STAT(mib_counters.good_frames_sent) },
963 { "excessive_collision", MV643XX_ETH_STAT(mib_counters.excessive_collision) },
964 { "multicast_frames_sent", MV643XX_ETH_STAT(mib_counters.multicast_frames_sent) },
965 { "broadcast_frames_sent", MV643XX_ETH_STAT(mib_counters.broadcast_frames_sent) },
966 { "unrec_mac_control_received", MV643XX_ETH_STAT(mib_counters.unrec_mac_control_received) },
967 { "fc_sent", MV643XX_ETH_STAT(mib_counters.fc_sent) },
968 { "good_fc_received", MV643XX_ETH_STAT(mib_counters.good_fc_received) },
969 { "bad_fc_received", MV643XX_ETH_STAT(mib_counters.bad_fc_received) },
970 { "undersize_received", MV643XX_ETH_STAT(mib_counters.undersize_received) },
971 { "fragments_received", MV643XX_ETH_STAT(mib_counters.fragments_received) },
972 { "oversize_received", MV643XX_ETH_STAT(mib_counters.oversize_received) },
973 { "jabber_received", MV643XX_ETH_STAT(mib_counters.jabber_received) },
974 { "mac_receive_error", MV643XX_ETH_STAT(mib_counters.mac_receive_error) },
975 { "bad_crc_event", MV643XX_ETH_STAT(mib_counters.bad_crc_event) },
976 { "collision", MV643XX_ETH_STAT(mib_counters.collision) },
977 { "late_collision", MV643XX_ETH_STAT(mib_counters.late_collision) },
980 #define MV643XX_ETH_STATS_LEN ARRAY_SIZE(mv643xx_eth_gstrings_stats)
982 static int mv643xx_eth_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
984 struct mv643xx_eth_private *mp = netdev_priv(dev);
987 spin_lock_irq(&mp->lock);
988 err = mii_ethtool_gset(&mp->mii, cmd);
989 spin_unlock_irq(&mp->lock);
991 /* The PHY may support 1000baseT_Half, but the mv643xx does not */
992 cmd->supported &= ~SUPPORTED_1000baseT_Half;
993 cmd->advertising &= ~ADVERTISED_1000baseT_Half;
998 static int mv643xx_eth_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1000 struct mv643xx_eth_private *mp = netdev_priv(dev);
1003 spin_lock_irq(&mp->lock);
1004 err = mii_ethtool_sset(&mp->mii, cmd);
1005 spin_unlock_irq(&mp->lock);
1010 static void mv643xx_eth_get_drvinfo(struct net_device *netdev,
1011 struct ethtool_drvinfo *drvinfo)
1013 strncpy(drvinfo->driver, mv643xx_eth_driver_name, 32);
1014 strncpy(drvinfo->version, mv643xx_eth_driver_version, 32);
1015 strncpy(drvinfo->fw_version, "N/A", 32);
1016 strncpy(drvinfo->bus_info, "mv643xx", 32);
1017 drvinfo->n_stats = MV643XX_ETH_STATS_LEN;
1020 static int mv643xx_eth_nway_restart(struct net_device *dev)
1022 struct mv643xx_eth_private *mp = netdev_priv(dev);
1024 return mii_nway_restart(&mp->mii);
1027 static u32 mv643xx_eth_get_link(struct net_device *dev)
1029 struct mv643xx_eth_private *mp = netdev_priv(dev);
1031 return mii_link_ok(&mp->mii);
1034 static void mv643xx_eth_get_strings(struct net_device *netdev, uint32_t stringset,
1041 for (i=0; i < MV643XX_ETH_STATS_LEN; i++) {
1042 memcpy(data + i * ETH_GSTRING_LEN,
1043 mv643xx_eth_gstrings_stats[i].stat_string,
1050 static void mv643xx_eth_get_ethtool_stats(struct net_device *netdev,
1051 struct ethtool_stats *stats, uint64_t *data)
1053 struct mv643xx_eth_private *mp = netdev->priv;
1056 update_mib_counters(mp);
1058 for (i = 0; i < MV643XX_ETH_STATS_LEN; i++) {
1059 char *p = (char *)mp+mv643xx_eth_gstrings_stats[i].stat_offset;
1060 data[i] = (mv643xx_eth_gstrings_stats[i].sizeof_stat ==
1061 sizeof(uint64_t)) ? *(uint64_t *)p : *(uint32_t *)p;
1065 static int mv643xx_eth_get_sset_count(struct net_device *netdev, int sset)
1069 return MV643XX_ETH_STATS_LEN;
1075 static const struct ethtool_ops mv643xx_eth_ethtool_ops = {
1076 .get_settings = mv643xx_eth_get_settings,
1077 .set_settings = mv643xx_eth_set_settings,
1078 .get_drvinfo = mv643xx_eth_get_drvinfo,
1079 .get_link = mv643xx_eth_get_link,
1080 .set_sg = ethtool_op_set_sg,
1081 .get_sset_count = mv643xx_eth_get_sset_count,
1082 .get_ethtool_stats = mv643xx_eth_get_ethtool_stats,
1083 .get_strings = mv643xx_eth_get_strings,
1084 .nway_reset = mv643xx_eth_nway_restart,
1088 /* address handling *********************************************************/
1089 static void uc_addr_get(struct mv643xx_eth_private *mp, unsigned char *addr)
1091 unsigned int port_num = mp->port_num;
1095 mac_h = rdl(mp, MAC_ADDR_HIGH(port_num));
1096 mac_l = rdl(mp, MAC_ADDR_LOW(port_num));
1098 addr[0] = (mac_h >> 24) & 0xff;
1099 addr[1] = (mac_h >> 16) & 0xff;
1100 addr[2] = (mac_h >> 8) & 0xff;
1101 addr[3] = mac_h & 0xff;
1102 addr[4] = (mac_l >> 8) & 0xff;
1103 addr[5] = mac_l & 0xff;
1106 static void init_mac_tables(struct mv643xx_eth_private *mp)
1108 unsigned int port_num = mp->port_num;
1111 /* Clear DA filter unicast table (Ex_dFUT) */
1112 for (table_index = 0; table_index <= 0xC; table_index += 4)
1113 wrl(mp, UNICAST_TABLE(port_num) + table_index, 0);
1115 for (table_index = 0; table_index <= 0xFC; table_index += 4) {
1116 /* Clear DA filter special multicast table (Ex_dFSMT) */
1117 wrl(mp, SPECIAL_MCAST_TABLE(port_num) + table_index, 0);
1118 /* Clear DA filter other multicast table (Ex_dFOMT) */
1119 wrl(mp, OTHER_MCAST_TABLE(port_num) + table_index, 0);
1123 static void set_filter_table_entry(struct mv643xx_eth_private *mp,
1124 int table, unsigned char entry)
1126 unsigned int table_reg;
1127 unsigned int tbl_offset;
1128 unsigned int reg_offset;
1130 tbl_offset = (entry / 4) * 4; /* Register offset of DA table entry */
1131 reg_offset = entry % 4; /* Entry offset within the register */
1133 /* Set "accepts frame bit" at specified table entry */
1134 table_reg = rdl(mp, table + tbl_offset);
1135 table_reg |= 0x01 << (8 * reg_offset);
1136 wrl(mp, table + tbl_offset, table_reg);
1139 static void uc_addr_set(struct mv643xx_eth_private *mp, unsigned char *addr)
1141 unsigned int port_num = mp->port_num;
1146 mac_l = (addr[4] << 8) | (addr[5]);
1147 mac_h = (addr[0] << 24) | (addr[1] << 16) | (addr[2] << 8) |
1150 wrl(mp, MAC_ADDR_LOW(port_num), mac_l);
1151 wrl(mp, MAC_ADDR_HIGH(port_num), mac_h);
1153 /* Accept frames with this address */
1154 table = UNICAST_TABLE(port_num);
1155 set_filter_table_entry(mp, table, addr[5] & 0x0f);
1158 static void mv643xx_eth_update_mac_address(struct net_device *dev)
1160 struct mv643xx_eth_private *mp = netdev_priv(dev);
1162 init_mac_tables(mp);
1163 uc_addr_set(mp, dev->dev_addr);
1166 static int mv643xx_eth_set_mac_address(struct net_device *dev, void *addr)
1170 for (i = 0; i < 6; i++)
1171 /* +2 is for the offset of the HW addr type */
1172 dev->dev_addr[i] = ((unsigned char *)addr)[i + 2];
1173 mv643xx_eth_update_mac_address(dev);
1177 static void mc_addr(struct mv643xx_eth_private *mp, unsigned char *addr)
1179 unsigned int port_num = mp->port_num;
1182 unsigned char crc_result = 0;
1188 if ((addr[0] == 0x01) && (addr[1] == 0x00) &&
1189 (addr[2] == 0x5E) && (addr[3] == 0x00) && (addr[4] == 0x00)) {
1190 table = SPECIAL_MCAST_TABLE(port_num);
1191 set_filter_table_entry(mp, table, addr[5]);
1195 /* Calculate CRC-8 out of the given address */
1196 mac_h = (addr[0] << 8) | (addr[1]);
1197 mac_l = (addr[2] << 24) | (addr[3] << 16) |
1198 (addr[4] << 8) | (addr[5] << 0);
1200 for (i = 0; i < 32; i++)
1201 mac_array[i] = (mac_l >> i) & 0x1;
1202 for (i = 32; i < 48; i++)
1203 mac_array[i] = (mac_h >> (i - 32)) & 0x1;
1205 crc[0] = mac_array[45] ^ mac_array[43] ^ mac_array[40] ^ mac_array[39] ^
1206 mac_array[35] ^ mac_array[34] ^ mac_array[31] ^ mac_array[30] ^
1207 mac_array[28] ^ mac_array[23] ^ mac_array[21] ^ mac_array[19] ^
1208 mac_array[18] ^ mac_array[16] ^ mac_array[14] ^ mac_array[12] ^
1209 mac_array[8] ^ mac_array[7] ^ mac_array[6] ^ mac_array[0];
1211 crc[1] = mac_array[46] ^ mac_array[45] ^ mac_array[44] ^ mac_array[43] ^
1212 mac_array[41] ^ mac_array[39] ^ mac_array[36] ^ mac_array[34] ^
1213 mac_array[32] ^ mac_array[30] ^ mac_array[29] ^ mac_array[28] ^
1214 mac_array[24] ^ mac_array[23] ^ mac_array[22] ^ mac_array[21] ^
1215 mac_array[20] ^ mac_array[18] ^ mac_array[17] ^ mac_array[16] ^
1216 mac_array[15] ^ mac_array[14] ^ mac_array[13] ^ mac_array[12] ^
1217 mac_array[9] ^ mac_array[6] ^ mac_array[1] ^ mac_array[0];
1219 crc[2] = mac_array[47] ^ mac_array[46] ^ mac_array[44] ^ mac_array[43] ^
1220 mac_array[42] ^ mac_array[39] ^ mac_array[37] ^ mac_array[34] ^
1221 mac_array[33] ^ mac_array[29] ^ mac_array[28] ^ mac_array[25] ^
1222 mac_array[24] ^ mac_array[22] ^ mac_array[17] ^ mac_array[15] ^
1223 mac_array[13] ^ mac_array[12] ^ mac_array[10] ^ mac_array[8] ^
1224 mac_array[6] ^ mac_array[2] ^ mac_array[1] ^ mac_array[0];
1226 crc[3] = mac_array[47] ^ mac_array[45] ^ mac_array[44] ^ mac_array[43] ^
1227 mac_array[40] ^ mac_array[38] ^ mac_array[35] ^ mac_array[34] ^
1228 mac_array[30] ^ mac_array[29] ^ mac_array[26] ^ mac_array[25] ^
1229 mac_array[23] ^ mac_array[18] ^ mac_array[16] ^ mac_array[14] ^
1230 mac_array[13] ^ mac_array[11] ^ mac_array[9] ^ mac_array[7] ^
1231 mac_array[3] ^ mac_array[2] ^ mac_array[1];
1233 crc[4] = mac_array[46] ^ mac_array[45] ^ mac_array[44] ^ mac_array[41] ^
1234 mac_array[39] ^ mac_array[36] ^ mac_array[35] ^ mac_array[31] ^
1235 mac_array[30] ^ mac_array[27] ^ mac_array[26] ^ mac_array[24] ^
1236 mac_array[19] ^ mac_array[17] ^ mac_array[15] ^ mac_array[14] ^
1237 mac_array[12] ^ mac_array[10] ^ mac_array[8] ^ mac_array[4] ^
1238 mac_array[3] ^ mac_array[2];
1240 crc[5] = mac_array[47] ^ mac_array[46] ^ mac_array[45] ^ mac_array[42] ^
1241 mac_array[40] ^ mac_array[37] ^ mac_array[36] ^ mac_array[32] ^
1242 mac_array[31] ^ mac_array[28] ^ mac_array[27] ^ mac_array[25] ^
1243 mac_array[20] ^ mac_array[18] ^ mac_array[16] ^ mac_array[15] ^
1244 mac_array[13] ^ mac_array[11] ^ mac_array[9] ^ mac_array[5] ^
1245 mac_array[4] ^ mac_array[3];
1247 crc[6] = mac_array[47] ^ mac_array[46] ^ mac_array[43] ^ mac_array[41] ^
1248 mac_array[38] ^ mac_array[37] ^ mac_array[33] ^ mac_array[32] ^
1249 mac_array[29] ^ mac_array[28] ^ mac_array[26] ^ mac_array[21] ^
1250 mac_array[19] ^ mac_array[17] ^ mac_array[16] ^ mac_array[14] ^
1251 mac_array[12] ^ mac_array[10] ^ mac_array[6] ^ mac_array[5] ^
1254 crc[7] = mac_array[47] ^ mac_array[44] ^ mac_array[42] ^ mac_array[39] ^
1255 mac_array[38] ^ mac_array[34] ^ mac_array[33] ^ mac_array[30] ^
1256 mac_array[29] ^ mac_array[27] ^ mac_array[22] ^ mac_array[20] ^
1257 mac_array[18] ^ mac_array[17] ^ mac_array[15] ^ mac_array[13] ^
1258 mac_array[11] ^ mac_array[7] ^ mac_array[6] ^ mac_array[5];
1260 for (i = 0; i < 8; i++)
1261 crc_result = crc_result | (crc[i] << i);
1263 table = OTHER_MCAST_TABLE(port_num);
1264 set_filter_table_entry(mp, table, crc_result);
1267 static void set_multicast_list(struct net_device *dev)
1270 struct dev_mc_list *mc_list;
1273 struct mv643xx_eth_private *mp = netdev_priv(dev);
1274 unsigned int port_num = mp->port_num;
1276 /* If the device is in promiscuous mode or in all multicast mode,
1277 * we will fully populate both multicast tables with accept.
1278 * This is guaranteed to yield a match on all multicast addresses...
1280 if ((dev->flags & IFF_PROMISC) || (dev->flags & IFF_ALLMULTI)) {
1281 for (table_index = 0; table_index <= 0xFC; table_index += 4) {
1282 /* Set all entries in DA filter special multicast
1284 * Set for ETH_Q0 for now
1286 * 0 Accept=1, Drop=0
1287 * 3-1 Queue ETH_Q0=0
1290 wrl(mp, SPECIAL_MCAST_TABLE(port_num) + table_index, 0x01010101);
1292 /* Set all entries in DA filter other multicast
1294 * Set for ETH_Q0 for now
1296 * 0 Accept=1, Drop=0
1297 * 3-1 Queue ETH_Q0=0
1300 wrl(mp, OTHER_MCAST_TABLE(port_num) + table_index, 0x01010101);
1305 /* We will clear out multicast tables every time we get the list.
1306 * Then add the entire new list...
1308 for (table_index = 0; table_index <= 0xFC; table_index += 4) {
1309 /* Clear DA filter special multicast table (Ex_dFSMT) */
1310 wrl(mp, SPECIAL_MCAST_TABLE(port_num) + table_index, 0);
1312 /* Clear DA filter other multicast table (Ex_dFOMT) */
1313 wrl(mp, OTHER_MCAST_TABLE(port_num) + table_index, 0);
1316 /* Get pointer to net_device multicast list and add each one... */
1317 for (i = 0, mc_list = dev->mc_list;
1318 (i < 256) && (mc_list != NULL) && (i < dev->mc_count);
1319 i++, mc_list = mc_list->next)
1320 if (mc_list->dmi_addrlen == 6)
1321 mc_addr(mp, mc_list->dmi_addr);
1324 static void mv643xx_eth_set_rx_mode(struct net_device *dev)
1326 struct mv643xx_eth_private *mp = netdev_priv(dev);
1329 config_reg = rdl(mp, PORT_CONFIG(mp->port_num));
1330 if (dev->flags & IFF_PROMISC)
1331 config_reg |= UNICAST_PROMISCUOUS_MODE;
1333 config_reg &= ~UNICAST_PROMISCUOUS_MODE;
1334 wrl(mp, PORT_CONFIG(mp->port_num), config_reg);
1336 set_multicast_list(dev);
1340 /* rx/tx queue initialisation ***********************************************/
1341 static void ether_init_rx_desc_ring(struct mv643xx_eth_private *mp)
1343 volatile struct rx_desc *p_rx_desc;
1344 int rx_desc_num = mp->rx_ring_size;
1347 /* initialize the next_desc_ptr links in the Rx descriptors ring */
1348 p_rx_desc = (struct rx_desc *)mp->rx_desc_area;
1349 for (i = 0; i < rx_desc_num; i++) {
1350 p_rx_desc[i].next_desc_ptr = mp->rx_desc_dma +
1351 ((i + 1) % rx_desc_num) * sizeof(struct rx_desc);
1354 /* Save Rx desc pointer to driver struct. */
1355 mp->rx_curr_desc = 0;
1356 mp->rx_used_desc = 0;
1358 mp->rx_desc_area_size = rx_desc_num * sizeof(struct rx_desc);
1361 static void mv643xx_eth_free_rx_rings(struct net_device *dev)
1363 struct mv643xx_eth_private *mp = netdev_priv(dev);
1366 /* Stop RX Queues */
1367 mv643xx_eth_port_disable_rx(mp);
1369 /* Free preallocated skb's on RX rings */
1370 for (curr = 0; mp->rx_desc_count && curr < mp->rx_ring_size; curr++) {
1371 if (mp->rx_skb[curr]) {
1372 dev_kfree_skb(mp->rx_skb[curr]);
1373 mp->rx_desc_count--;
1377 if (mp->rx_desc_count)
1379 "%s: Error in freeing Rx Ring. %d skb's still"
1380 " stuck in RX Ring - ignoring them\n", dev->name,
1383 if (mp->rx_sram_size)
1384 iounmap(mp->rx_desc_area);
1386 dma_free_coherent(NULL, mp->rx_desc_area_size,
1387 mp->rx_desc_area, mp->rx_desc_dma);
1390 static void ether_init_tx_desc_ring(struct mv643xx_eth_private *mp)
1392 int tx_desc_num = mp->tx_ring_size;
1393 struct tx_desc *p_tx_desc;
1396 /* Initialize the next_desc_ptr links in the Tx descriptors ring */
1397 p_tx_desc = (struct tx_desc *)mp->tx_desc_area;
1398 for (i = 0; i < tx_desc_num; i++) {
1399 p_tx_desc[i].next_desc_ptr = mp->tx_desc_dma +
1400 ((i + 1) % tx_desc_num) * sizeof(struct tx_desc);
1403 mp->tx_curr_desc = 0;
1404 mp->tx_used_desc = 0;
1406 mp->tx_desc_area_size = tx_desc_num * sizeof(struct tx_desc);
1409 static int mv643xx_eth_free_tx_descs(struct net_device *dev, int force)
1411 struct mv643xx_eth_private *mp = netdev_priv(dev);
1412 struct tx_desc *desc;
1414 struct sk_buff *skb;
1415 unsigned long flags;
1421 while (mp->tx_desc_count > 0) {
1422 spin_lock_irqsave(&mp->lock, flags);
1424 /* tx_desc_count might have changed before acquiring the lock */
1425 if (mp->tx_desc_count <= 0) {
1426 spin_unlock_irqrestore(&mp->lock, flags);
1430 tx_index = mp->tx_used_desc;
1431 desc = &mp->tx_desc_area[tx_index];
1432 cmd_sts = desc->cmd_sts;
1434 if (!force && (cmd_sts & BUFFER_OWNED_BY_DMA)) {
1435 spin_unlock_irqrestore(&mp->lock, flags);
1439 mp->tx_used_desc = (tx_index + 1) % mp->tx_ring_size;
1440 mp->tx_desc_count--;
1442 addr = desc->buf_ptr;
1443 count = desc->byte_cnt;
1444 skb = mp->tx_skb[tx_index];
1446 mp->tx_skb[tx_index] = NULL;
1448 if (cmd_sts & ERROR_SUMMARY) {
1449 printk("%s: Error in TX\n", dev->name);
1450 dev->stats.tx_errors++;
1453 spin_unlock_irqrestore(&mp->lock, flags);
1455 if (cmd_sts & TX_FIRST_DESC)
1456 dma_unmap_single(NULL, addr, count, DMA_TO_DEVICE);
1458 dma_unmap_page(NULL, addr, count, DMA_TO_DEVICE);
1461 dev_kfree_skb_irq(skb);
1469 static void mv643xx_eth_free_completed_tx_descs(struct net_device *dev)
1471 struct mv643xx_eth_private *mp = netdev_priv(dev);
1473 if (mv643xx_eth_free_tx_descs(dev, 0) &&
1474 mp->tx_ring_size - mp->tx_desc_count >= MAX_DESCS_PER_SKB)
1475 netif_wake_queue(dev);
1478 static void mv643xx_eth_free_all_tx_descs(struct net_device *dev)
1480 mv643xx_eth_free_tx_descs(dev, 1);
1483 static void mv643xx_eth_free_tx_rings(struct net_device *dev)
1485 struct mv643xx_eth_private *mp = netdev_priv(dev);
1487 /* Stop Tx Queues */
1488 mv643xx_eth_port_disable_tx(mp);
1490 /* Free outstanding skb's on TX ring */
1491 mv643xx_eth_free_all_tx_descs(dev);
1493 BUG_ON(mp->tx_used_desc != mp->tx_curr_desc);
1496 if (mp->tx_sram_size)
1497 iounmap(mp->tx_desc_area);
1499 dma_free_coherent(NULL, mp->tx_desc_area_size,
1500 mp->tx_desc_area, mp->tx_desc_dma);
1504 /* netdev ops and related ***************************************************/
1505 static void port_reset(struct mv643xx_eth_private *mp);
1507 static void mv643xx_eth_update_pscr(struct net_device *dev,
1508 struct ethtool_cmd *ecmd)
1510 struct mv643xx_eth_private *mp = netdev_priv(dev);
1511 int port_num = mp->port_num;
1513 unsigned int queues;
1515 o_pscr = rdl(mp, PORT_SERIAL_CONTROL(port_num));
1518 /* clear speed, duplex and rx buffer size fields */
1519 n_pscr &= ~(SET_MII_SPEED_TO_100 |
1520 SET_GMII_SPEED_TO_1000 |
1521 SET_FULL_DUPLEX_MODE |
1522 MAX_RX_PACKET_MASK);
1524 if (ecmd->duplex == DUPLEX_FULL)
1525 n_pscr |= SET_FULL_DUPLEX_MODE;
1527 if (ecmd->speed == SPEED_1000)
1528 n_pscr |= SET_GMII_SPEED_TO_1000 |
1529 MAX_RX_PACKET_9700BYTE;
1531 if (ecmd->speed == SPEED_100)
1532 n_pscr |= SET_MII_SPEED_TO_100;
1533 n_pscr |= MAX_RX_PACKET_1522BYTE;
1536 if (n_pscr != o_pscr) {
1537 if ((o_pscr & SERIAL_PORT_ENABLE) == 0)
1538 wrl(mp, PORT_SERIAL_CONTROL(port_num), n_pscr);
1540 queues = mv643xx_eth_port_disable_tx(mp);
1542 o_pscr &= ~SERIAL_PORT_ENABLE;
1543 wrl(mp, PORT_SERIAL_CONTROL(port_num), o_pscr);
1544 wrl(mp, PORT_SERIAL_CONTROL(port_num), n_pscr);
1545 wrl(mp, PORT_SERIAL_CONTROL(port_num), n_pscr);
1547 mv643xx_eth_port_enable_tx(mp, queues);
1552 static irqreturn_t mv643xx_eth_int_handler(int irq, void *dev_id)
1554 struct net_device *dev = (struct net_device *)dev_id;
1555 struct mv643xx_eth_private *mp = netdev_priv(dev);
1556 u32 int_cause, int_cause_ext = 0;
1557 unsigned int port_num = mp->port_num;
1559 /* Read interrupt cause registers */
1560 int_cause = rdl(mp, INT_CAUSE(port_num)) & (INT_RX | INT_EXT);
1561 if (int_cause & INT_EXT) {
1562 int_cause_ext = rdl(mp, INT_CAUSE_EXT(port_num))
1563 & (INT_EXT_LINK | INT_EXT_PHY | INT_EXT_TX);
1564 wrl(mp, INT_CAUSE_EXT(port_num), ~int_cause_ext);
1567 /* PHY status changed */
1568 if (int_cause_ext & (INT_EXT_LINK | INT_EXT_PHY)) {
1569 struct ethtool_cmd cmd;
1571 if (mii_link_ok(&mp->mii)) {
1572 mii_ethtool_gset(&mp->mii, &cmd);
1573 mv643xx_eth_update_pscr(dev, &cmd);
1574 mv643xx_eth_port_enable_tx(mp, 1);
1575 if (!netif_carrier_ok(dev)) {
1576 netif_carrier_on(dev);
1577 if (mp->tx_ring_size - mp->tx_desc_count >=
1579 netif_wake_queue(dev);
1581 } else if (netif_carrier_ok(dev)) {
1582 netif_stop_queue(dev);
1583 netif_carrier_off(dev);
1587 #ifdef MV643XX_ETH_NAPI
1588 if (int_cause & INT_RX) {
1589 /* schedule the NAPI poll routine to maintain port */
1590 wrl(mp, INT_MASK(port_num), 0x00000000);
1592 /* wait for previous write to complete */
1593 rdl(mp, INT_MASK(port_num));
1595 netif_rx_schedule(dev, &mp->napi);
1598 if (int_cause & INT_RX)
1599 mv643xx_eth_receive_queue(dev, INT_MAX);
1601 if (int_cause_ext & INT_EXT_TX)
1602 mv643xx_eth_free_completed_tx_descs(dev);
1605 * If no real interrupt occured, exit.
1606 * This can happen when using gigE interrupt coalescing mechanism.
1608 if ((int_cause == 0x0) && (int_cause_ext == 0x0))
1614 static void phy_reset(struct mv643xx_eth_private *mp)
1616 unsigned int phy_reg_data;
1619 read_smi_reg(mp, 0, &phy_reg_data);
1620 phy_reg_data |= 0x8000; /* Set bit 15 to reset the PHY */
1621 write_smi_reg(mp, 0, phy_reg_data);
1623 /* wait for PHY to come out of reset */
1626 read_smi_reg(mp, 0, &phy_reg_data);
1627 } while (phy_reg_data & 0x8000);
1630 static void port_start(struct net_device *dev)
1632 struct mv643xx_eth_private *mp = netdev_priv(dev);
1633 unsigned int port_num = mp->port_num;
1634 int tx_curr_desc, rx_curr_desc;
1636 struct ethtool_cmd ethtool_cmd;
1638 /* Assignment of Tx CTRP of given queue */
1639 tx_curr_desc = mp->tx_curr_desc;
1640 wrl(mp, TXQ_CURRENT_DESC_PTR(port_num),
1641 (u32)((struct tx_desc *)mp->tx_desc_dma + tx_curr_desc));
1643 /* Assignment of Rx CRDP of given queue */
1644 rx_curr_desc = mp->rx_curr_desc;
1645 wrl(mp, RXQ_CURRENT_DESC_PTR(port_num),
1646 (u32)((struct rx_desc *)mp->rx_desc_dma + rx_curr_desc));
1648 /* Add the assigned Ethernet address to the port's address table */
1649 uc_addr_set(mp, dev->dev_addr);
1652 * Receive all unmatched unicast, TCP, UDP, BPDU and broadcast
1653 * frames to RX queue #0.
1655 wrl(mp, PORT_CONFIG(port_num), 0x00000000);
1658 * Treat BPDUs as normal multicasts, and disable partition mode.
1660 wrl(mp, PORT_CONFIG_EXT(port_num), 0x00000000);
1662 pscr = rdl(mp, PORT_SERIAL_CONTROL(port_num));
1664 pscr &= ~(SERIAL_PORT_ENABLE | FORCE_LINK_PASS);
1665 wrl(mp, PORT_SERIAL_CONTROL(port_num), pscr);
1667 pscr |= DISABLE_AUTO_NEG_FOR_FLOW_CTRL |
1668 DISABLE_AUTO_NEG_SPEED_GMII |
1669 DISABLE_AUTO_NEG_FOR_DUPLEX |
1670 DO_NOT_FORCE_LINK_FAIL |
1671 SERIAL_PORT_CONTROL_RESERVED;
1673 wrl(mp, PORT_SERIAL_CONTROL(port_num), pscr);
1675 pscr |= SERIAL_PORT_ENABLE;
1676 wrl(mp, PORT_SERIAL_CONTROL(port_num), pscr);
1678 /* Assign port SDMA configuration */
1679 wrl(mp, SDMA_CONFIG(port_num), PORT_SDMA_CONFIG_DEFAULT_VALUE);
1681 /* Enable port Rx. */
1682 mv643xx_eth_port_enable_rx(mp, 1);
1684 /* Disable port bandwidth limits by clearing MTU register */
1685 wrl(mp, TX_BW_MTU(port_num), 0);
1687 /* save phy settings across reset */
1688 mv643xx_eth_get_settings(dev, ðtool_cmd);
1690 mv643xx_eth_set_settings(dev, ðtool_cmd);
1693 #ifdef MV643XX_ETH_COAL
1694 static unsigned int set_rx_coal(struct mv643xx_eth_private *mp,
1697 unsigned int port_num = mp->port_num;
1698 unsigned int coal = ((mp->shared->t_clk / 1000000) * delay) / 64;
1700 /* Set RX Coalescing mechanism */
1701 wrl(mp, SDMA_CONFIG(port_num),
1702 ((coal & 0x3fff) << 8) |
1703 (rdl(mp, SDMA_CONFIG(port_num))
1710 static unsigned int set_tx_coal(struct mv643xx_eth_private *mp,
1713 unsigned int coal = ((mp->shared->t_clk / 1000000) * delay) / 64;
1715 /* Set TX Coalescing mechanism */
1716 wrl(mp, TX_FIFO_URGENT_THRESHOLD(mp->port_num), coal << 4);
1721 static void port_init(struct mv643xx_eth_private *mp)
1725 init_mac_tables(mp);
1728 static int mv643xx_eth_open(struct net_device *dev)
1730 struct mv643xx_eth_private *mp = netdev_priv(dev);
1731 unsigned int port_num = mp->port_num;
1735 /* Clear any pending ethernet port interrupts */
1736 wrl(mp, INT_CAUSE(port_num), 0);
1737 wrl(mp, INT_CAUSE_EXT(port_num), 0);
1738 /* wait for previous write to complete */
1739 rdl(mp, INT_CAUSE_EXT(port_num));
1741 err = request_irq(dev->irq, mv643xx_eth_int_handler,
1742 IRQF_SHARED | IRQF_SAMPLE_RANDOM, dev->name, dev);
1744 printk(KERN_ERR "%s: Can not assign IRQ\n", dev->name);
1750 memset(&mp->timeout, 0, sizeof(struct timer_list));
1751 mp->timeout.function = mv643xx_eth_rx_refill_descs_timer_wrapper;
1752 mp->timeout.data = (unsigned long)dev;
1754 /* Allocate RX and TX skb rings */
1755 mp->rx_skb = kmalloc(sizeof(*mp->rx_skb) * mp->rx_ring_size,
1758 printk(KERN_ERR "%s: Cannot allocate Rx skb ring\n", dev->name);
1762 mp->tx_skb = kmalloc(sizeof(*mp->tx_skb) * mp->tx_ring_size,
1765 printk(KERN_ERR "%s: Cannot allocate Tx skb ring\n", dev->name);
1767 goto out_free_rx_skb;
1770 /* Allocate TX ring */
1771 mp->tx_desc_count = 0;
1772 size = mp->tx_ring_size * sizeof(struct tx_desc);
1773 mp->tx_desc_area_size = size;
1775 if (mp->tx_sram_size) {
1776 mp->tx_desc_area = ioremap(mp->tx_sram_addr,
1778 mp->tx_desc_dma = mp->tx_sram_addr;
1780 mp->tx_desc_area = dma_alloc_coherent(NULL, size,
1784 if (!mp->tx_desc_area) {
1785 printk(KERN_ERR "%s: Cannot allocate Tx Ring (size %d bytes)\n",
1788 goto out_free_tx_skb;
1790 BUG_ON((u32) mp->tx_desc_area & 0xf); /* check 16-byte alignment */
1791 memset((void *)mp->tx_desc_area, 0, mp->tx_desc_area_size);
1793 ether_init_tx_desc_ring(mp);
1795 /* Allocate RX ring */
1796 mp->rx_desc_count = 0;
1797 size = mp->rx_ring_size * sizeof(struct rx_desc);
1798 mp->rx_desc_area_size = size;
1800 if (mp->rx_sram_size) {
1801 mp->rx_desc_area = ioremap(mp->rx_sram_addr,
1803 mp->rx_desc_dma = mp->rx_sram_addr;
1805 mp->rx_desc_area = dma_alloc_coherent(NULL, size,
1809 if (!mp->rx_desc_area) {
1810 printk(KERN_ERR "%s: Cannot allocate Rx ring (size %d bytes)\n",
1812 printk(KERN_ERR "%s: Freeing previously allocated TX queues...",
1814 if (mp->rx_sram_size)
1815 iounmap(mp->tx_desc_area);
1817 dma_free_coherent(NULL, mp->tx_desc_area_size,
1818 mp->tx_desc_area, mp->tx_desc_dma);
1820 goto out_free_tx_skb;
1822 memset((void *)mp->rx_desc_area, 0, size);
1824 ether_init_rx_desc_ring(mp);
1826 mv643xx_eth_rx_refill_descs(dev); /* Fill RX ring with skb's */
1828 #ifdef MV643XX_ETH_NAPI
1829 napi_enable(&mp->napi);
1834 /* Interrupt Coalescing */
1836 #ifdef MV643XX_ETH_COAL
1837 mp->rx_int_coal = set_rx_coal(mp, MV643XX_ETH_RX_COAL);
1840 mp->tx_int_coal = set_tx_coal(mp, MV643XX_ETH_TX_COAL);
1842 /* Unmask phy and link status changes interrupts */
1843 wrl(mp, INT_MASK_EXT(port_num), INT_EXT_LINK | INT_EXT_PHY | INT_EXT_TX);
1845 /* Unmask RX buffer and TX end interrupt */
1846 wrl(mp, INT_MASK(port_num), INT_RX | INT_EXT);
1855 free_irq(dev->irq, dev);
1860 static void port_reset(struct mv643xx_eth_private *mp)
1862 unsigned int port_num = mp->port_num;
1863 unsigned int reg_data;
1865 mv643xx_eth_port_disable_tx(mp);
1866 mv643xx_eth_port_disable_rx(mp);
1868 /* Clear all MIB counters */
1869 clear_mib_counters(mp);
1871 /* Reset the Enable bit in the Configuration Register */
1872 reg_data = rdl(mp, PORT_SERIAL_CONTROL(port_num));
1873 reg_data &= ~(SERIAL_PORT_ENABLE |
1874 DO_NOT_FORCE_LINK_FAIL |
1876 wrl(mp, PORT_SERIAL_CONTROL(port_num), reg_data);
1879 static int mv643xx_eth_stop(struct net_device *dev)
1881 struct mv643xx_eth_private *mp = netdev_priv(dev);
1882 unsigned int port_num = mp->port_num;
1884 /* Mask all interrupts on ethernet port */
1885 wrl(mp, INT_MASK(port_num), 0x00000000);
1886 /* wait for previous write to complete */
1887 rdl(mp, INT_MASK(port_num));
1889 #ifdef MV643XX_ETH_NAPI
1890 napi_disable(&mp->napi);
1892 netif_carrier_off(dev);
1893 netif_stop_queue(dev);
1897 mv643xx_eth_free_tx_rings(dev);
1898 mv643xx_eth_free_rx_rings(dev);
1900 free_irq(dev->irq, dev);
1905 static int mv643xx_eth_do_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
1907 struct mv643xx_eth_private *mp = netdev_priv(dev);
1909 return generic_mii_ioctl(&mp->mii, if_mii(ifr), cmd, NULL);
1912 static int mv643xx_eth_change_mtu(struct net_device *dev, int new_mtu)
1914 if ((new_mtu > 9500) || (new_mtu < 64))
1918 if (!netif_running(dev))
1922 * Stop and then re-open the interface. This will allocate RX
1923 * skbs of the new MTU.
1924 * There is a possible danger that the open will not succeed,
1925 * due to memory being full, which might fail the open function.
1927 mv643xx_eth_stop(dev);
1928 if (mv643xx_eth_open(dev)) {
1929 printk(KERN_ERR "%s: Fatal error on opening device\n",
1936 static void mv643xx_eth_tx_timeout_task(struct work_struct *ugly)
1938 struct mv643xx_eth_private *mp = container_of(ugly, struct mv643xx_eth_private,
1940 struct net_device *dev = mp->dev;
1942 if (!netif_running(dev))
1945 netif_stop_queue(dev);
1950 if (mp->tx_ring_size - mp->tx_desc_count >= MAX_DESCS_PER_SKB)
1951 netif_wake_queue(dev);
1954 static void mv643xx_eth_tx_timeout(struct net_device *dev)
1956 struct mv643xx_eth_private *mp = netdev_priv(dev);
1958 printk(KERN_INFO "%s: TX timeout ", dev->name);
1960 /* Do the reset outside of interrupt context */
1961 schedule_work(&mp->tx_timeout_task);
1964 #ifdef CONFIG_NET_POLL_CONTROLLER
1965 static void mv643xx_eth_netpoll(struct net_device *netdev)
1967 struct mv643xx_eth_private *mp = netdev_priv(netdev);
1968 int port_num = mp->port_num;
1970 wrl(mp, INT_MASK(port_num), 0x00000000);
1971 /* wait for previous write to complete */
1972 rdl(mp, INT_MASK(port_num));
1974 mv643xx_eth_int_handler(netdev->irq, netdev);
1976 wrl(mp, INT_MASK(port_num), INT_RX | INT_CAUSE_EXT);
1980 static int mv643xx_eth_mdio_read(struct net_device *dev, int phy_id, int location)
1982 struct mv643xx_eth_private *mp = netdev_priv(dev);
1985 read_smi_reg(mp, location, &val);
1989 static void mv643xx_eth_mdio_write(struct net_device *dev, int phy_id, int location, int val)
1991 struct mv643xx_eth_private *mp = netdev_priv(dev);
1992 write_smi_reg(mp, location, val);
1996 /* platform glue ************************************************************/
1998 mv643xx_eth_conf_mbus_windows(struct mv643xx_eth_shared_private *msp,
1999 struct mbus_dram_target_info *dram)
2001 void __iomem *base = msp->base;
2006 for (i = 0; i < 6; i++) {
2007 writel(0, base + WINDOW_BASE(i));
2008 writel(0, base + WINDOW_SIZE(i));
2010 writel(0, base + WINDOW_REMAP_HIGH(i));
2016 for (i = 0; i < dram->num_cs; i++) {
2017 struct mbus_dram_window *cs = dram->cs + i;
2019 writel((cs->base & 0xffff0000) |
2020 (cs->mbus_attr << 8) |
2021 dram->mbus_dram_target_id, base + WINDOW_BASE(i));
2022 writel((cs->size - 1) & 0xffff0000, base + WINDOW_SIZE(i));
2024 win_enable &= ~(1 << i);
2025 win_protect |= 3 << (2 * i);
2028 writel(win_enable, base + WINDOW_BAR_ENABLE);
2029 msp->win_protect = win_protect;
2032 static int mv643xx_eth_shared_probe(struct platform_device *pdev)
2034 static int mv643xx_eth_version_printed = 0;
2035 struct mv643xx_eth_shared_platform_data *pd = pdev->dev.platform_data;
2036 struct mv643xx_eth_shared_private *msp;
2037 struct resource *res;
2040 if (!mv643xx_eth_version_printed++)
2041 printk(KERN_NOTICE "MV-643xx 10/100/1000 Ethernet Driver\n");
2044 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2049 msp = kmalloc(sizeof(*msp), GFP_KERNEL);
2052 memset(msp, 0, sizeof(*msp));
2054 msp->base = ioremap(res->start, res->end - res->start + 1);
2055 if (msp->base == NULL)
2058 spin_lock_init(&msp->phy_lock);
2059 msp->t_clk = (pd != NULL && pd->t_clk != 0) ? pd->t_clk : 133000000;
2061 platform_set_drvdata(pdev, msp);
2064 * (Re-)program MBUS remapping windows if we are asked to.
2066 if (pd != NULL && pd->dram != NULL)
2067 mv643xx_eth_conf_mbus_windows(msp, pd->dram);
2077 static int mv643xx_eth_shared_remove(struct platform_device *pdev)
2079 struct mv643xx_eth_shared_private *msp = platform_get_drvdata(pdev);
2087 static struct platform_driver mv643xx_eth_shared_driver = {
2088 .probe = mv643xx_eth_shared_probe,
2089 .remove = mv643xx_eth_shared_remove,
2091 .name = MV643XX_ETH_SHARED_NAME,
2092 .owner = THIS_MODULE,
2096 static void phy_addr_set(struct mv643xx_eth_private *mp, int phy_addr)
2099 int addr_shift = 5 * mp->port_num;
2101 reg_data = rdl(mp, PHY_ADDR);
2102 reg_data &= ~(0x1f << addr_shift);
2103 reg_data |= (phy_addr & 0x1f) << addr_shift;
2104 wrl(mp, PHY_ADDR, reg_data);
2107 static int phy_addr_get(struct mv643xx_eth_private *mp)
2109 unsigned int reg_data;
2111 reg_data = rdl(mp, PHY_ADDR);
2113 return ((reg_data >> (5 * mp->port_num)) & 0x1f);
2116 static int phy_detect(struct mv643xx_eth_private *mp)
2118 unsigned int phy_reg_data0;
2121 read_smi_reg(mp, 0, &phy_reg_data0);
2122 auto_neg = phy_reg_data0 & 0x1000;
2123 phy_reg_data0 ^= 0x1000; /* invert auto_neg */
2124 write_smi_reg(mp, 0, phy_reg_data0);
2126 read_smi_reg(mp, 0, &phy_reg_data0);
2127 if ((phy_reg_data0 & 0x1000) == auto_neg)
2128 return -ENODEV; /* change didn't take */
2130 phy_reg_data0 ^= 0x1000;
2131 write_smi_reg(mp, 0, phy_reg_data0);
2135 static void mv643xx_init_ethtool_cmd(struct net_device *dev, int phy_address,
2136 int speed, int duplex,
2137 struct ethtool_cmd *cmd)
2139 struct mv643xx_eth_private *mp = netdev_priv(dev);
2141 memset(cmd, 0, sizeof(*cmd));
2143 cmd->port = PORT_MII;
2144 cmd->transceiver = XCVR_INTERNAL;
2145 cmd->phy_address = phy_address;
2148 cmd->autoneg = AUTONEG_ENABLE;
2149 /* mii lib checks, but doesn't use speed on AUTONEG_ENABLE */
2150 cmd->speed = SPEED_100;
2151 cmd->advertising = ADVERTISED_10baseT_Half |
2152 ADVERTISED_10baseT_Full |
2153 ADVERTISED_100baseT_Half |
2154 ADVERTISED_100baseT_Full;
2155 if (mp->mii.supports_gmii)
2156 cmd->advertising |= ADVERTISED_1000baseT_Full;
2158 cmd->autoneg = AUTONEG_DISABLE;
2160 cmd->duplex = duplex;
2164 static int mv643xx_eth_probe(struct platform_device *pdev)
2166 struct mv643xx_eth_platform_data *pd;
2168 struct mv643xx_eth_private *mp;
2169 struct net_device *dev;
2171 struct resource *res;
2173 struct ethtool_cmd cmd;
2174 int duplex = DUPLEX_HALF;
2175 int speed = 0; /* default to auto-negotiation */
2176 DECLARE_MAC_BUF(mac);
2178 pd = pdev->dev.platform_data;
2180 printk(KERN_ERR "No mv643xx_eth_platform_data\n");
2184 if (pd->shared == NULL) {
2185 printk(KERN_ERR "No mv643xx_eth_platform_data->shared\n");
2189 dev = alloc_etherdev(sizeof(struct mv643xx_eth_private));
2193 platform_set_drvdata(pdev, dev);
2195 mp = netdev_priv(dev);
2197 #ifdef MV643XX_ETH_NAPI
2198 netif_napi_add(dev, &mp->napi, mv643xx_eth_poll, 64);
2201 res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
2203 dev->irq = res->start;
2205 dev->open = mv643xx_eth_open;
2206 dev->stop = mv643xx_eth_stop;
2207 dev->hard_start_xmit = mv643xx_eth_start_xmit;
2208 dev->set_mac_address = mv643xx_eth_set_mac_address;
2209 dev->set_multicast_list = mv643xx_eth_set_rx_mode;
2211 /* No need to Tx Timeout */
2212 dev->tx_timeout = mv643xx_eth_tx_timeout;
2214 #ifdef CONFIG_NET_POLL_CONTROLLER
2215 dev->poll_controller = mv643xx_eth_netpoll;
2218 dev->watchdog_timeo = 2 * HZ;
2220 dev->change_mtu = mv643xx_eth_change_mtu;
2221 dev->do_ioctl = mv643xx_eth_do_ioctl;
2222 SET_ETHTOOL_OPS(dev, &mv643xx_eth_ethtool_ops);
2224 #ifdef MV643XX_ETH_CHECKSUM_OFFLOAD_TX
2225 #ifdef MAX_SKB_FRAGS
2227 * Zero copy can only work if we use Discovery II memory. Else, we will
2228 * have to map the buffers to ISA memory which is only 16 MB
2230 dev->features = NETIF_F_SG | NETIF_F_IP_CSUM;
2234 /* Configure the timeout task */
2235 INIT_WORK(&mp->tx_timeout_task, mv643xx_eth_tx_timeout_task);
2237 spin_lock_init(&mp->lock);
2239 mp->shared = platform_get_drvdata(pd->shared);
2240 port_num = mp->port_num = pd->port_number;
2242 if (mp->shared->win_protect)
2243 wrl(mp, WINDOW_PROTECT(port_num), mp->shared->win_protect);
2245 mp->shared_smi = mp->shared;
2246 if (pd->shared_smi != NULL)
2247 mp->shared_smi = platform_get_drvdata(pd->shared_smi);
2249 /* set default config values */
2250 uc_addr_get(mp, dev->dev_addr);
2251 mp->rx_ring_size = DEFAULT_RX_QUEUE_SIZE;
2252 mp->tx_ring_size = DEFAULT_TX_QUEUE_SIZE;
2254 if (is_valid_ether_addr(pd->mac_addr))
2255 memcpy(dev->dev_addr, pd->mac_addr, 6);
2257 if (pd->phy_addr || pd->force_phy_addr)
2258 phy_addr_set(mp, pd->phy_addr);
2260 if (pd->rx_queue_size)
2261 mp->rx_ring_size = pd->rx_queue_size;
2263 if (pd->tx_queue_size)
2264 mp->tx_ring_size = pd->tx_queue_size;
2266 if (pd->tx_sram_size) {
2267 mp->tx_sram_size = pd->tx_sram_size;
2268 mp->tx_sram_addr = pd->tx_sram_addr;
2271 if (pd->rx_sram_size) {
2272 mp->rx_sram_size = pd->rx_sram_size;
2273 mp->rx_sram_addr = pd->rx_sram_addr;
2276 duplex = pd->duplex;
2279 /* Hook up MII support for ethtool */
2281 mp->mii.mdio_read = mv643xx_eth_mdio_read;
2282 mp->mii.mdio_write = mv643xx_eth_mdio_write;
2283 mp->mii.phy_id = phy_addr_get(mp);
2284 mp->mii.phy_id_mask = 0x3f;
2285 mp->mii.reg_num_mask = 0x1f;
2287 err = phy_detect(mp);
2289 pr_debug("%s: No PHY detected at addr %d\n",
2290 dev->name, phy_addr_get(mp));
2295 mp->mii.supports_gmii = mii_check_gmii_support(&mp->mii);
2296 mv643xx_init_ethtool_cmd(dev, mp->mii.phy_id, speed, duplex, &cmd);
2297 mv643xx_eth_update_pscr(dev, &cmd);
2298 mv643xx_eth_set_settings(dev, &cmd);
2300 SET_NETDEV_DEV(dev, &pdev->dev);
2301 err = register_netdev(dev);
2307 "%s: port %d with MAC address %s\n",
2308 dev->name, port_num, print_mac(mac, p));
2310 if (dev->features & NETIF_F_SG)
2311 printk(KERN_NOTICE "%s: Scatter Gather Enabled\n", dev->name);
2313 if (dev->features & NETIF_F_IP_CSUM)
2314 printk(KERN_NOTICE "%s: TX TCP/IP Checksumming Supported\n",
2317 #ifdef MV643XX_ETH_CHECKSUM_OFFLOAD_TX
2318 printk(KERN_NOTICE "%s: RX TCP/UDP Checksum Offload ON \n", dev->name);
2321 #ifdef MV643XX_ETH_COAL
2322 printk(KERN_NOTICE "%s: TX and RX Interrupt Coalescing ON \n",
2326 #ifdef MV643XX_ETH_NAPI
2327 printk(KERN_NOTICE "%s: RX NAPI Enabled \n", dev->name);
2330 if (mp->tx_sram_size > 0)
2331 printk(KERN_NOTICE "%s: Using SRAM\n", dev->name);
2341 static int mv643xx_eth_remove(struct platform_device *pdev)
2343 struct net_device *dev = platform_get_drvdata(pdev);
2345 unregister_netdev(dev);
2346 flush_scheduled_work();
2349 platform_set_drvdata(pdev, NULL);
2353 static void mv643xx_eth_shutdown(struct platform_device *pdev)
2355 struct net_device *dev = platform_get_drvdata(pdev);
2356 struct mv643xx_eth_private *mp = netdev_priv(dev);
2357 unsigned int port_num = mp->port_num;
2359 /* Mask all interrupts on ethernet port */
2360 wrl(mp, INT_MASK(port_num), 0);
2361 rdl(mp, INT_MASK(port_num));
2366 static struct platform_driver mv643xx_eth_driver = {
2367 .probe = mv643xx_eth_probe,
2368 .remove = mv643xx_eth_remove,
2369 .shutdown = mv643xx_eth_shutdown,
2371 .name = MV643XX_ETH_NAME,
2372 .owner = THIS_MODULE,
2376 static int __init mv643xx_eth_init_module(void)
2380 rc = platform_driver_register(&mv643xx_eth_shared_driver);
2382 rc = platform_driver_register(&mv643xx_eth_driver);
2384 platform_driver_unregister(&mv643xx_eth_shared_driver);
2389 static void __exit mv643xx_eth_cleanup_module(void)
2391 platform_driver_unregister(&mv643xx_eth_driver);
2392 platform_driver_unregister(&mv643xx_eth_shared_driver);
2395 module_init(mv643xx_eth_init_module);
2396 module_exit(mv643xx_eth_cleanup_module);
2398 MODULE_LICENSE("GPL");
2399 MODULE_AUTHOR( "Rabeeh Khoury, Assaf Hoffman, Matthew Dharm, Manish Lachwani"
2400 " and Dale Farnsworth");
2401 MODULE_DESCRIPTION("Ethernet driver for Marvell MV643XX");
2402 MODULE_ALIAS("platform:" MV643XX_ETH_NAME);
2403 MODULE_ALIAS("platform:" MV643XX_ETH_SHARED_NAME);