2 * Driver for Marvell Discovery (MV643XX) and Marvell Orion ethernet ports
3 * Copyright (C) 2002 Matthew Dharm <mdharm@momenco.com>
5 * Based on the 64360 driver from:
6 * Copyright (C) 2002 Rabeeh Khoury <rabeeh@galileo.co.il>
7 * Rabeeh Khoury <rabeeh@marvell.com>
9 * Copyright (C) 2003 PMC-Sierra, Inc.,
10 * written by Manish Lachwani
12 * Copyright (C) 2003 Ralf Baechle <ralf@linux-mips.org>
14 * Copyright (C) 2004-2006 MontaVista Software, Inc.
15 * Dale Farnsworth <dale@farnsworth.org>
17 * Copyright (C) 2004 Steven J. Hill <sjhill1@rockwellcollins.com>
18 * <sjhill@realitydiluted.com>
20 * Copyright (C) 2007-2008 Marvell Semiconductor
21 * Lennert Buytenhek <buytenh@marvell.com>
23 * This program is free software; you can redistribute it and/or
24 * modify it under the terms of the GNU General Public License
25 * as published by the Free Software Foundation; either version 2
26 * of the License, or (at your option) any later version.
28 * This program is distributed in the hope that it will be useful,
29 * but WITHOUT ANY WARRANTY; without even the implied warranty of
30 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
31 * GNU General Public License for more details.
33 * You should have received a copy of the GNU General Public License
34 * along with this program; if not, write to the Free Software
35 * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
38 #include <linux/init.h>
39 #include <linux/dma-mapping.h>
41 #include <linux/tcp.h>
42 #include <linux/udp.h>
43 #include <linux/etherdevice.h>
44 #include <linux/delay.h>
45 #include <linux/ethtool.h>
46 #include <linux/platform_device.h>
47 #include <linux/module.h>
48 #include <linux/kernel.h>
49 #include <linux/spinlock.h>
50 #include <linux/workqueue.h>
51 #include <linux/mii.h>
52 #include <linux/mv643xx_eth.h>
54 #include <asm/types.h>
55 #include <asm/system.h>
57 static char mv643xx_eth_driver_name[] = "mv643xx_eth";
58 static char mv643xx_eth_driver_version[] = "1.0";
60 #define MV643XX_ETH_CHECKSUM_OFFLOAD_TX
61 #define MV643XX_ETH_NAPI
62 #define MV643XX_ETH_TX_FAST_REFILL
64 #ifdef MV643XX_ETH_CHECKSUM_OFFLOAD_TX
65 #define MAX_DESCS_PER_SKB (MAX_SKB_FRAGS + 1)
67 #define MAX_DESCS_PER_SKB 1
71 * Registers shared between all ports.
73 #define PHY_ADDR 0x0000
74 #define SMI_REG 0x0004
75 #define WINDOW_BASE(w) (0x0200 + ((w) << 3))
76 #define WINDOW_SIZE(w) (0x0204 + ((w) << 3))
77 #define WINDOW_REMAP_HIGH(w) (0x0280 + ((w) << 2))
78 #define WINDOW_BAR_ENABLE 0x0290
79 #define WINDOW_PROTECT(w) (0x0294 + ((w) << 4))
84 #define PORT_CONFIG(p) (0x0400 + ((p) << 10))
85 #define UNICAST_PROMISCUOUS_MODE 0x00000001
86 #define PORT_CONFIG_EXT(p) (0x0404 + ((p) << 10))
87 #define MAC_ADDR_LOW(p) (0x0414 + ((p) << 10))
88 #define MAC_ADDR_HIGH(p) (0x0418 + ((p) << 10))
89 #define SDMA_CONFIG(p) (0x041c + ((p) << 10))
90 #define PORT_SERIAL_CONTROL(p) (0x043c + ((p) << 10))
91 #define PORT_STATUS(p) (0x0444 + ((p) << 10))
92 #define TX_FIFO_EMPTY 0x00000400
93 #define TXQ_COMMAND(p) (0x0448 + ((p) << 10))
94 #define TXQ_FIX_PRIO_CONF(p) (0x044c + ((p) << 10))
95 #define TX_BW_RATE(p) (0x0450 + ((p) << 10))
96 #define TX_BW_MTU(p) (0x0458 + ((p) << 10))
97 #define TX_BW_BURST(p) (0x045c + ((p) << 10))
98 #define INT_CAUSE(p) (0x0460 + ((p) << 10))
99 #define INT_TX_END 0x07f80000
100 #define INT_RX 0x0007fbfc
101 #define INT_EXT 0x00000002
102 #define INT_CAUSE_EXT(p) (0x0464 + ((p) << 10))
103 #define INT_EXT_LINK 0x00100000
104 #define INT_EXT_PHY 0x00010000
105 #define INT_EXT_TX_ERROR_0 0x00000100
106 #define INT_EXT_TX_0 0x00000001
107 #define INT_EXT_TX 0x0000ffff
108 #define INT_MASK(p) (0x0468 + ((p) << 10))
109 #define INT_MASK_EXT(p) (0x046c + ((p) << 10))
110 #define TX_FIFO_URGENT_THRESHOLD(p) (0x0474 + ((p) << 10))
111 #define RXQ_CURRENT_DESC_PTR(p, q) (0x060c + ((p) << 10) + ((q) << 4))
112 #define RXQ_COMMAND(p) (0x0680 + ((p) << 10))
113 #define TXQ_CURRENT_DESC_PTR(p, q) (0x06c0 + ((p) << 10) + ((q) << 2))
114 #define TXQ_BW_TOKENS(p, q) (0x0700 + ((p) << 10) + ((q) << 4))
115 #define TXQ_BW_CONF(p, q) (0x0704 + ((p) << 10) + ((q) << 4))
116 #define TXQ_BW_WRR_CONF(p, q) (0x0708 + ((p) << 10) + ((q) << 4))
117 #define MIB_COUNTERS(p) (0x1000 + ((p) << 7))
118 #define SPECIAL_MCAST_TABLE(p) (0x1400 + ((p) << 10))
119 #define OTHER_MCAST_TABLE(p) (0x1500 + ((p) << 10))
120 #define UNICAST_TABLE(p) (0x1600 + ((p) << 10))
124 * SDMA configuration register.
126 #define RX_BURST_SIZE_4_64BIT (2 << 1)
127 #define BLM_RX_NO_SWAP (1 << 4)
128 #define BLM_TX_NO_SWAP (1 << 5)
129 #define TX_BURST_SIZE_4_64BIT (2 << 22)
131 #if defined(__BIG_ENDIAN)
132 #define PORT_SDMA_CONFIG_DEFAULT_VALUE \
133 RX_BURST_SIZE_4_64BIT | \
134 TX_BURST_SIZE_4_64BIT
135 #elif defined(__LITTLE_ENDIAN)
136 #define PORT_SDMA_CONFIG_DEFAULT_VALUE \
137 RX_BURST_SIZE_4_64BIT | \
140 TX_BURST_SIZE_4_64BIT
142 #error One of __BIG_ENDIAN or __LITTLE_ENDIAN must be defined
147 * Port serial control register.
149 #define SET_MII_SPEED_TO_100 (1 << 24)
150 #define SET_GMII_SPEED_TO_1000 (1 << 23)
151 #define SET_FULL_DUPLEX_MODE (1 << 21)
152 #define MAX_RX_PACKET_1522BYTE (1 << 17)
153 #define MAX_RX_PACKET_9700BYTE (5 << 17)
154 #define MAX_RX_PACKET_MASK (7 << 17)
155 #define DISABLE_AUTO_NEG_SPEED_GMII (1 << 13)
156 #define DO_NOT_FORCE_LINK_FAIL (1 << 10)
157 #define SERIAL_PORT_CONTROL_RESERVED (1 << 9)
158 #define DISABLE_AUTO_NEG_FOR_FLOW_CTRL (1 << 3)
159 #define DISABLE_AUTO_NEG_FOR_DUPLEX (1 << 2)
160 #define FORCE_LINK_PASS (1 << 1)
161 #define SERIAL_PORT_ENABLE (1 << 0)
163 #define DEFAULT_RX_QUEUE_SIZE 400
164 #define DEFAULT_TX_QUEUE_SIZE 800
170 #if defined(__BIG_ENDIAN)
172 u16 byte_cnt; /* Descriptor buffer byte count */
173 u16 buf_size; /* Buffer size */
174 u32 cmd_sts; /* Descriptor command status */
175 u32 next_desc_ptr; /* Next descriptor pointer */
176 u32 buf_ptr; /* Descriptor buffer pointer */
180 u16 byte_cnt; /* buffer byte count */
181 u16 l4i_chk; /* CPU provided TCP checksum */
182 u32 cmd_sts; /* Command/status field */
183 u32 next_desc_ptr; /* Pointer to next descriptor */
184 u32 buf_ptr; /* pointer to buffer for this descriptor*/
186 #elif defined(__LITTLE_ENDIAN)
188 u32 cmd_sts; /* Descriptor command status */
189 u16 buf_size; /* Buffer size */
190 u16 byte_cnt; /* Descriptor buffer byte count */
191 u32 buf_ptr; /* Descriptor buffer pointer */
192 u32 next_desc_ptr; /* Next descriptor pointer */
196 u32 cmd_sts; /* Command/status field */
197 u16 l4i_chk; /* CPU provided TCP checksum */
198 u16 byte_cnt; /* buffer byte count */
199 u32 buf_ptr; /* pointer to buffer for this descriptor*/
200 u32 next_desc_ptr; /* Pointer to next descriptor */
203 #error One of __BIG_ENDIAN or __LITTLE_ENDIAN must be defined
206 /* RX & TX descriptor command */
207 #define BUFFER_OWNED_BY_DMA 0x80000000
209 /* RX & TX descriptor status */
210 #define ERROR_SUMMARY 0x00000001
212 /* RX descriptor status */
213 #define LAYER_4_CHECKSUM_OK 0x40000000
214 #define RX_ENABLE_INTERRUPT 0x20000000
215 #define RX_FIRST_DESC 0x08000000
216 #define RX_LAST_DESC 0x04000000
218 /* TX descriptor command */
219 #define TX_ENABLE_INTERRUPT 0x00800000
220 #define GEN_CRC 0x00400000
221 #define TX_FIRST_DESC 0x00200000
222 #define TX_LAST_DESC 0x00100000
223 #define ZERO_PADDING 0x00080000
224 #define GEN_IP_V4_CHECKSUM 0x00040000
225 #define GEN_TCP_UDP_CHECKSUM 0x00020000
226 #define UDP_FRAME 0x00010000
228 #define TX_IHL_SHIFT 11
231 /* global *******************************************************************/
232 struct mv643xx_eth_shared_private {
234 * Ethernet controller base address.
239 * Protects access to SMI_REG, which is shared between ports.
244 * Per-port MBUS window access register value.
249 * Hardware-specific parameters.
252 int extended_rx_coal_limit;
256 /* per-port *****************************************************************/
257 struct mib_counters {
258 u64 good_octets_received;
259 u32 bad_octets_received;
260 u32 internal_mac_transmit_err;
261 u32 good_frames_received;
262 u32 bad_frames_received;
263 u32 broadcast_frames_received;
264 u32 multicast_frames_received;
265 u32 frames_64_octets;
266 u32 frames_65_to_127_octets;
267 u32 frames_128_to_255_octets;
268 u32 frames_256_to_511_octets;
269 u32 frames_512_to_1023_octets;
270 u32 frames_1024_to_max_octets;
271 u64 good_octets_sent;
272 u32 good_frames_sent;
273 u32 excessive_collision;
274 u32 multicast_frames_sent;
275 u32 broadcast_frames_sent;
276 u32 unrec_mac_control_received;
278 u32 good_fc_received;
280 u32 undersize_received;
281 u32 fragments_received;
282 u32 oversize_received;
284 u32 mac_receive_error;
299 struct rx_desc *rx_desc_area;
300 dma_addr_t rx_desc_dma;
301 int rx_desc_area_size;
302 struct sk_buff **rx_skb;
304 struct timer_list rx_oom;
316 struct tx_desc *tx_desc_area;
317 dma_addr_t tx_desc_dma;
318 int tx_desc_area_size;
319 struct sk_buff **tx_skb;
322 struct mv643xx_eth_private {
323 struct mv643xx_eth_shared_private *shared;
326 struct net_device *dev;
328 struct mv643xx_eth_shared_private *shared_smi;
333 struct mib_counters mib_counters;
334 struct work_struct tx_timeout_task;
335 struct mii_if_info mii;
340 int default_rx_ring_size;
341 unsigned long rx_desc_sram_addr;
342 int rx_desc_sram_size;
345 struct napi_struct napi;
346 struct rx_queue rxq[8];
351 int default_tx_ring_size;
352 unsigned long tx_desc_sram_addr;
353 int tx_desc_sram_size;
356 struct tx_queue txq[8];
357 #ifdef MV643XX_ETH_TX_FAST_REFILL
358 int tx_clean_threshold;
363 /* port register accessors **************************************************/
364 static inline u32 rdl(struct mv643xx_eth_private *mp, int offset)
366 return readl(mp->shared->base + offset);
369 static inline void wrl(struct mv643xx_eth_private *mp, int offset, u32 data)
371 writel(data, mp->shared->base + offset);
375 /* rxq/txq helper functions *************************************************/
376 static struct mv643xx_eth_private *rxq_to_mp(struct rx_queue *rxq)
378 return container_of(rxq, struct mv643xx_eth_private, rxq[rxq->index]);
381 static struct mv643xx_eth_private *txq_to_mp(struct tx_queue *txq)
383 return container_of(txq, struct mv643xx_eth_private, txq[txq->index]);
386 static void rxq_enable(struct rx_queue *rxq)
388 struct mv643xx_eth_private *mp = rxq_to_mp(rxq);
389 wrl(mp, RXQ_COMMAND(mp->port_num), 1 << rxq->index);
392 static void rxq_disable(struct rx_queue *rxq)
394 struct mv643xx_eth_private *mp = rxq_to_mp(rxq);
395 u8 mask = 1 << rxq->index;
397 wrl(mp, RXQ_COMMAND(mp->port_num), mask << 8);
398 while (rdl(mp, RXQ_COMMAND(mp->port_num)) & mask)
402 static void txq_enable(struct tx_queue *txq)
404 struct mv643xx_eth_private *mp = txq_to_mp(txq);
405 wrl(mp, TXQ_COMMAND(mp->port_num), 1 << txq->index);
408 static void txq_disable(struct tx_queue *txq)
410 struct mv643xx_eth_private *mp = txq_to_mp(txq);
411 u8 mask = 1 << txq->index;
413 wrl(mp, TXQ_COMMAND(mp->port_num), mask << 8);
414 while (rdl(mp, TXQ_COMMAND(mp->port_num)) & mask)
418 static void __txq_maybe_wake(struct tx_queue *txq)
420 struct mv643xx_eth_private *mp = txq_to_mp(txq);
423 * netif_{stop,wake}_queue() flow control only applies to
426 BUG_ON(txq->index != mp->txq_primary);
428 if (txq->tx_ring_size - txq->tx_desc_count >= MAX_DESCS_PER_SKB)
429 netif_wake_queue(mp->dev);
433 /* rx ***********************************************************************/
434 static void txq_reclaim(struct tx_queue *txq, int force);
436 static void rxq_refill(struct rx_queue *rxq)
438 struct mv643xx_eth_private *mp = rxq_to_mp(rxq);
441 spin_lock_irqsave(&mp->lock, flags);
443 while (rxq->rx_desc_count < rxq->rx_ring_size) {
450 * Reserve 2+14 bytes for an ethernet header (the
451 * hardware automatically prepends 2 bytes of dummy
452 * data to each received packet), 4 bytes for a VLAN
453 * header, and 4 bytes for the trailing FCS -- 24
456 skb_size = mp->dev->mtu + 24;
458 skb = dev_alloc_skb(skb_size + dma_get_cache_alignment() - 1);
462 unaligned = (u32)skb->data & (dma_get_cache_alignment() - 1);
464 skb_reserve(skb, dma_get_cache_alignment() - unaligned);
466 rxq->rx_desc_count++;
467 rx = rxq->rx_used_desc;
468 rxq->rx_used_desc = (rx + 1) % rxq->rx_ring_size;
470 rxq->rx_desc_area[rx].buf_ptr = dma_map_single(NULL, skb->data,
471 skb_size, DMA_FROM_DEVICE);
472 rxq->rx_desc_area[rx].buf_size = skb_size;
473 rxq->rx_skb[rx] = skb;
475 rxq->rx_desc_area[rx].cmd_sts = BUFFER_OWNED_BY_DMA |
480 * The hardware automatically prepends 2 bytes of
481 * dummy data to each received packet, so that the
482 * IP header ends up 16-byte aligned.
487 if (rxq->rx_desc_count == 0) {
488 rxq->rx_oom.expires = jiffies + (HZ / 10);
489 add_timer(&rxq->rx_oom);
492 spin_unlock_irqrestore(&mp->lock, flags);
495 static inline void rxq_refill_timer_wrapper(unsigned long data)
497 rxq_refill((struct rx_queue *)data);
500 static int rxq_process(struct rx_queue *rxq, int budget)
502 struct mv643xx_eth_private *mp = rxq_to_mp(rxq);
503 struct net_device_stats *stats = &mp->dev->stats;
507 while (rx < budget) {
508 struct rx_desc *rx_desc;
509 unsigned int cmd_sts;
513 spin_lock_irqsave(&mp->lock, flags);
515 rx_desc = &rxq->rx_desc_area[rxq->rx_curr_desc];
517 cmd_sts = rx_desc->cmd_sts;
518 if (cmd_sts & BUFFER_OWNED_BY_DMA) {
519 spin_unlock_irqrestore(&mp->lock, flags);
524 skb = rxq->rx_skb[rxq->rx_curr_desc];
525 rxq->rx_skb[rxq->rx_curr_desc] = NULL;
527 rxq->rx_curr_desc = (rxq->rx_curr_desc + 1) % rxq->rx_ring_size;
529 spin_unlock_irqrestore(&mp->lock, flags);
531 dma_unmap_single(NULL, rx_desc->buf_ptr + 2,
532 mp->dev->mtu + 24, DMA_FROM_DEVICE);
533 rxq->rx_desc_count--;
539 * Note that the descriptor byte count includes 2 dummy
540 * bytes automatically inserted by the hardware at the
541 * start of the packet (which we don't count), and a 4
542 * byte CRC at the end of the packet (which we do count).
545 stats->rx_bytes += rx_desc->byte_cnt - 2;
548 * In case we received a packet without first / last bits
549 * on, or the error summary bit is set, the packet needs
552 if (((cmd_sts & (RX_FIRST_DESC | RX_LAST_DESC)) !=
553 (RX_FIRST_DESC | RX_LAST_DESC))
554 || (cmd_sts & ERROR_SUMMARY)) {
557 if ((cmd_sts & (RX_FIRST_DESC | RX_LAST_DESC)) !=
558 (RX_FIRST_DESC | RX_LAST_DESC)) {
560 dev_printk(KERN_ERR, &mp->dev->dev,
561 "received packet spanning "
562 "multiple descriptors\n");
565 if (cmd_sts & ERROR_SUMMARY)
568 dev_kfree_skb_irq(skb);
571 * The -4 is for the CRC in the trailer of the
574 skb_put(skb, rx_desc->byte_cnt - 2 - 4);
576 if (cmd_sts & LAYER_4_CHECKSUM_OK) {
577 skb->ip_summed = CHECKSUM_UNNECESSARY;
579 (cmd_sts & 0x0007fff8) >> 3);
581 skb->protocol = eth_type_trans(skb, mp->dev);
582 #ifdef MV643XX_ETH_NAPI
583 netif_receive_skb(skb);
589 mp->dev->last_rx = jiffies;
597 #ifdef MV643XX_ETH_NAPI
598 static int mv643xx_eth_poll(struct napi_struct *napi, int budget)
600 struct mv643xx_eth_private *mp;
604 mp = container_of(napi, struct mv643xx_eth_private, napi);
606 #ifdef MV643XX_ETH_TX_FAST_REFILL
607 if (++mp->tx_clean_threshold > 5) {
608 mp->tx_clean_threshold = 0;
609 for (i = 0; i < 8; i++)
610 if (mp->txq_mask & (1 << i))
611 txq_reclaim(mp->txq + i, 0);
616 for (i = 7; rx < budget && i >= 0; i--)
617 if (mp->rxq_mask & (1 << i))
618 rx += rxq_process(mp->rxq + i, budget - rx);
621 netif_rx_complete(mp->dev, napi);
622 wrl(mp, INT_CAUSE(mp->port_num), 0);
623 wrl(mp, INT_CAUSE_EXT(mp->port_num), 0);
624 wrl(mp, INT_MASK(mp->port_num), INT_TX_END | INT_RX | INT_EXT);
632 /* tx ***********************************************************************/
633 static inline unsigned int has_tiny_unaligned_frags(struct sk_buff *skb)
637 for (frag = 0; frag < skb_shinfo(skb)->nr_frags; frag++) {
638 skb_frag_t *fragp = &skb_shinfo(skb)->frags[frag];
639 if (fragp->size <= 8 && fragp->page_offset & 7)
646 static int txq_alloc_desc_index(struct tx_queue *txq)
650 BUG_ON(txq->tx_desc_count >= txq->tx_ring_size);
652 tx_desc_curr = txq->tx_curr_desc;
653 txq->tx_curr_desc = (tx_desc_curr + 1) % txq->tx_ring_size;
655 BUG_ON(txq->tx_curr_desc == txq->tx_used_desc);
660 static void txq_submit_frag_skb(struct tx_queue *txq, struct sk_buff *skb)
662 int nr_frags = skb_shinfo(skb)->nr_frags;
665 for (frag = 0; frag < nr_frags; frag++) {
666 skb_frag_t *this_frag;
668 struct tx_desc *desc;
670 this_frag = &skb_shinfo(skb)->frags[frag];
671 tx_index = txq_alloc_desc_index(txq);
672 desc = &txq->tx_desc_area[tx_index];
675 * The last fragment will generate an interrupt
676 * which will free the skb on TX completion.
678 if (frag == nr_frags - 1) {
679 desc->cmd_sts = BUFFER_OWNED_BY_DMA |
680 ZERO_PADDING | TX_LAST_DESC |
682 txq->tx_skb[tx_index] = skb;
684 desc->cmd_sts = BUFFER_OWNED_BY_DMA;
685 txq->tx_skb[tx_index] = NULL;
689 desc->byte_cnt = this_frag->size;
690 desc->buf_ptr = dma_map_page(NULL, this_frag->page,
691 this_frag->page_offset,
697 static inline __be16 sum16_as_be(__sum16 sum)
699 return (__force __be16)sum;
702 static void txq_submit_skb(struct tx_queue *txq, struct sk_buff *skb)
704 int nr_frags = skb_shinfo(skb)->nr_frags;
706 struct tx_desc *desc;
710 cmd_sts = TX_FIRST_DESC | GEN_CRC | BUFFER_OWNED_BY_DMA;
712 tx_index = txq_alloc_desc_index(txq);
713 desc = &txq->tx_desc_area[tx_index];
716 txq_submit_frag_skb(txq, skb);
718 length = skb_headlen(skb);
719 txq->tx_skb[tx_index] = NULL;
721 cmd_sts |= ZERO_PADDING | TX_LAST_DESC | TX_ENABLE_INTERRUPT;
723 txq->tx_skb[tx_index] = skb;
726 desc->byte_cnt = length;
727 desc->buf_ptr = dma_map_single(NULL, skb->data, length, DMA_TO_DEVICE);
729 if (skb->ip_summed == CHECKSUM_PARTIAL) {
730 BUG_ON(skb->protocol != htons(ETH_P_IP));
732 cmd_sts |= GEN_TCP_UDP_CHECKSUM |
734 ip_hdr(skb)->ihl << TX_IHL_SHIFT;
736 switch (ip_hdr(skb)->protocol) {
738 cmd_sts |= UDP_FRAME;
739 desc->l4i_chk = ntohs(sum16_as_be(udp_hdr(skb)->check));
742 desc->l4i_chk = ntohs(sum16_as_be(tcp_hdr(skb)->check));
748 /* Errata BTS #50, IHL must be 5 if no HW checksum */
749 cmd_sts |= 5 << TX_IHL_SHIFT;
753 /* ensure all other descriptors are written before first cmd_sts */
755 desc->cmd_sts = cmd_sts;
757 /* ensure all descriptors are written before poking hardware */
761 txq->tx_desc_count += nr_frags + 1;
764 static int mv643xx_eth_xmit(struct sk_buff *skb, struct net_device *dev)
766 struct mv643xx_eth_private *mp = netdev_priv(dev);
767 struct net_device_stats *stats = &dev->stats;
768 struct tx_queue *txq;
771 if (has_tiny_unaligned_frags(skb) && __skb_linearize(skb)) {
773 dev_printk(KERN_DEBUG, &dev->dev,
774 "failed to linearize skb with tiny "
775 "unaligned fragment\n");
776 return NETDEV_TX_BUSY;
779 spin_lock_irqsave(&mp->lock, flags);
781 txq = mp->txq + mp->txq_primary;
783 if (txq->tx_ring_size - txq->tx_desc_count < MAX_DESCS_PER_SKB) {
784 spin_unlock_irqrestore(&mp->lock, flags);
785 if (txq->index == mp->txq_primary && net_ratelimit())
786 dev_printk(KERN_ERR, &dev->dev,
787 "primary tx queue full?!\n");
792 txq_submit_skb(txq, skb);
793 stats->tx_bytes += skb->len;
795 dev->trans_start = jiffies;
797 if (txq->index == mp->txq_primary) {
800 entries_left = txq->tx_ring_size - txq->tx_desc_count;
801 if (entries_left < MAX_DESCS_PER_SKB)
802 netif_stop_queue(dev);
805 spin_unlock_irqrestore(&mp->lock, flags);
811 /* tx rate control **********************************************************/
813 * Set total maximum TX rate (shared by all TX queues for this port)
814 * to 'rate' bits per second, with a maximum burst of 'burst' bytes.
816 static void tx_set_rate(struct mv643xx_eth_private *mp, int rate, int burst)
822 token_rate = ((rate / 1000) * 64) / (mp->shared->t_clk / 1000);
823 if (token_rate > 1023)
826 mtu = (mp->dev->mtu + 255) >> 8;
830 bucket_size = (burst + 255) >> 8;
831 if (bucket_size > 65535)
834 wrl(mp, TX_BW_RATE(mp->port_num), token_rate);
835 wrl(mp, TX_BW_MTU(mp->port_num), mtu);
836 wrl(mp, TX_BW_BURST(mp->port_num), bucket_size);
839 static void txq_set_rate(struct tx_queue *txq, int rate, int burst)
841 struct mv643xx_eth_private *mp = txq_to_mp(txq);
845 token_rate = ((rate / 1000) * 64) / (mp->shared->t_clk / 1000);
846 if (token_rate > 1023)
849 bucket_size = (burst + 255) >> 8;
850 if (bucket_size > 65535)
853 wrl(mp, TXQ_BW_TOKENS(mp->port_num, txq->index), token_rate << 14);
854 wrl(mp, TXQ_BW_CONF(mp->port_num, txq->index),
855 (bucket_size << 10) | token_rate);
858 static void txq_set_fixed_prio_mode(struct tx_queue *txq)
860 struct mv643xx_eth_private *mp = txq_to_mp(txq);
865 * Turn on fixed priority mode.
867 off = TXQ_FIX_PRIO_CONF(mp->port_num);
870 val |= 1 << txq->index;
874 static void txq_set_wrr(struct tx_queue *txq, int weight)
876 struct mv643xx_eth_private *mp = txq_to_mp(txq);
881 * Turn off fixed priority mode.
883 off = TXQ_FIX_PRIO_CONF(mp->port_num);
886 val &= ~(1 << txq->index);
890 * Configure WRR weight for this queue.
892 off = TXQ_BW_WRR_CONF(mp->port_num, txq->index);
895 val = (val & ~0xff) | (weight & 0xff);
900 /* mii management interface *************************************************/
901 #define SMI_BUSY 0x10000000
902 #define SMI_READ_VALID 0x08000000
903 #define SMI_OPCODE_READ 0x04000000
904 #define SMI_OPCODE_WRITE 0x00000000
906 static void smi_reg_read(struct mv643xx_eth_private *mp, unsigned int addr,
907 unsigned int reg, unsigned int *value)
909 void __iomem *smi_reg = mp->shared_smi->base + SMI_REG;
913 /* the SMI register is a shared resource */
914 spin_lock_irqsave(&mp->shared_smi->phy_lock, flags);
916 /* wait for the SMI register to become available */
917 for (i = 0; readl(smi_reg) & SMI_BUSY; i++) {
919 printk("%s: PHY busy timeout\n", mp->dev->name);
925 writel(SMI_OPCODE_READ | (reg << 21) | (addr << 16), smi_reg);
927 /* now wait for the data to be valid */
928 for (i = 0; !(readl(smi_reg) & SMI_READ_VALID); i++) {
930 printk("%s: PHY read timeout\n", mp->dev->name);
936 *value = readl(smi_reg) & 0xffff;
938 spin_unlock_irqrestore(&mp->shared_smi->phy_lock, flags);
941 static void smi_reg_write(struct mv643xx_eth_private *mp,
943 unsigned int reg, unsigned int value)
945 void __iomem *smi_reg = mp->shared_smi->base + SMI_REG;
949 /* the SMI register is a shared resource */
950 spin_lock_irqsave(&mp->shared_smi->phy_lock, flags);
952 /* wait for the SMI register to become available */
953 for (i = 0; readl(smi_reg) & SMI_BUSY; i++) {
955 printk("%s: PHY busy timeout\n", mp->dev->name);
961 writel(SMI_OPCODE_WRITE | (reg << 21) |
962 (addr << 16) | (value & 0xffff), smi_reg);
964 spin_unlock_irqrestore(&mp->shared_smi->phy_lock, flags);
968 /* mib counters *************************************************************/
969 static inline u32 mib_read(struct mv643xx_eth_private *mp, int offset)
971 return rdl(mp, MIB_COUNTERS(mp->port_num) + offset);
974 static void mib_counters_clear(struct mv643xx_eth_private *mp)
978 for (i = 0; i < 0x80; i += 4)
982 static void mib_counters_update(struct mv643xx_eth_private *mp)
984 struct mib_counters *p = &mp->mib_counters;
986 p->good_octets_received += mib_read(mp, 0x00);
987 p->good_octets_received += (u64)mib_read(mp, 0x04) << 32;
988 p->bad_octets_received += mib_read(mp, 0x08);
989 p->internal_mac_transmit_err += mib_read(mp, 0x0c);
990 p->good_frames_received += mib_read(mp, 0x10);
991 p->bad_frames_received += mib_read(mp, 0x14);
992 p->broadcast_frames_received += mib_read(mp, 0x18);
993 p->multicast_frames_received += mib_read(mp, 0x1c);
994 p->frames_64_octets += mib_read(mp, 0x20);
995 p->frames_65_to_127_octets += mib_read(mp, 0x24);
996 p->frames_128_to_255_octets += mib_read(mp, 0x28);
997 p->frames_256_to_511_octets += mib_read(mp, 0x2c);
998 p->frames_512_to_1023_octets += mib_read(mp, 0x30);
999 p->frames_1024_to_max_octets += mib_read(mp, 0x34);
1000 p->good_octets_sent += mib_read(mp, 0x38);
1001 p->good_octets_sent += (u64)mib_read(mp, 0x3c) << 32;
1002 p->good_frames_sent += mib_read(mp, 0x40);
1003 p->excessive_collision += mib_read(mp, 0x44);
1004 p->multicast_frames_sent += mib_read(mp, 0x48);
1005 p->broadcast_frames_sent += mib_read(mp, 0x4c);
1006 p->unrec_mac_control_received += mib_read(mp, 0x50);
1007 p->fc_sent += mib_read(mp, 0x54);
1008 p->good_fc_received += mib_read(mp, 0x58);
1009 p->bad_fc_received += mib_read(mp, 0x5c);
1010 p->undersize_received += mib_read(mp, 0x60);
1011 p->fragments_received += mib_read(mp, 0x64);
1012 p->oversize_received += mib_read(mp, 0x68);
1013 p->jabber_received += mib_read(mp, 0x6c);
1014 p->mac_receive_error += mib_read(mp, 0x70);
1015 p->bad_crc_event += mib_read(mp, 0x74);
1016 p->collision += mib_read(mp, 0x78);
1017 p->late_collision += mib_read(mp, 0x7c);
1021 /* ethtool ******************************************************************/
1022 struct mv643xx_eth_stats {
1023 char stat_string[ETH_GSTRING_LEN];
1030 { #m, FIELD_SIZEOF(struct net_device_stats, m), \
1031 offsetof(struct net_device, stats.m), -1 }
1033 #define MIBSTAT(m) \
1034 { #m, FIELD_SIZEOF(struct mib_counters, m), \
1035 -1, offsetof(struct mv643xx_eth_private, mib_counters.m) }
1037 static const struct mv643xx_eth_stats mv643xx_eth_stats[] = {
1046 MIBSTAT(good_octets_received),
1047 MIBSTAT(bad_octets_received),
1048 MIBSTAT(internal_mac_transmit_err),
1049 MIBSTAT(good_frames_received),
1050 MIBSTAT(bad_frames_received),
1051 MIBSTAT(broadcast_frames_received),
1052 MIBSTAT(multicast_frames_received),
1053 MIBSTAT(frames_64_octets),
1054 MIBSTAT(frames_65_to_127_octets),
1055 MIBSTAT(frames_128_to_255_octets),
1056 MIBSTAT(frames_256_to_511_octets),
1057 MIBSTAT(frames_512_to_1023_octets),
1058 MIBSTAT(frames_1024_to_max_octets),
1059 MIBSTAT(good_octets_sent),
1060 MIBSTAT(good_frames_sent),
1061 MIBSTAT(excessive_collision),
1062 MIBSTAT(multicast_frames_sent),
1063 MIBSTAT(broadcast_frames_sent),
1064 MIBSTAT(unrec_mac_control_received),
1066 MIBSTAT(good_fc_received),
1067 MIBSTAT(bad_fc_received),
1068 MIBSTAT(undersize_received),
1069 MIBSTAT(fragments_received),
1070 MIBSTAT(oversize_received),
1071 MIBSTAT(jabber_received),
1072 MIBSTAT(mac_receive_error),
1073 MIBSTAT(bad_crc_event),
1075 MIBSTAT(late_collision),
1078 static int mv643xx_eth_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1080 struct mv643xx_eth_private *mp = netdev_priv(dev);
1083 spin_lock_irq(&mp->lock);
1084 err = mii_ethtool_gset(&mp->mii, cmd);
1085 spin_unlock_irq(&mp->lock);
1088 * The MAC does not support 1000baseT_Half.
1090 cmd->supported &= ~SUPPORTED_1000baseT_Half;
1091 cmd->advertising &= ~ADVERTISED_1000baseT_Half;
1096 static int mv643xx_eth_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1098 struct mv643xx_eth_private *mp = netdev_priv(dev);
1102 * The MAC does not support 1000baseT_Half.
1104 cmd->advertising &= ~ADVERTISED_1000baseT_Half;
1106 spin_lock_irq(&mp->lock);
1107 err = mii_ethtool_sset(&mp->mii, cmd);
1108 spin_unlock_irq(&mp->lock);
1113 static void mv643xx_eth_get_drvinfo(struct net_device *dev,
1114 struct ethtool_drvinfo *drvinfo)
1116 strncpy(drvinfo->driver, mv643xx_eth_driver_name, 32);
1117 strncpy(drvinfo->version, mv643xx_eth_driver_version, 32);
1118 strncpy(drvinfo->fw_version, "N/A", 32);
1119 strncpy(drvinfo->bus_info, "platform", 32);
1120 drvinfo->n_stats = ARRAY_SIZE(mv643xx_eth_stats);
1123 static int mv643xx_eth_nway_reset(struct net_device *dev)
1125 struct mv643xx_eth_private *mp = netdev_priv(dev);
1127 return mii_nway_restart(&mp->mii);
1130 static u32 mv643xx_eth_get_link(struct net_device *dev)
1132 struct mv643xx_eth_private *mp = netdev_priv(dev);
1134 return mii_link_ok(&mp->mii);
1137 static void mv643xx_eth_get_strings(struct net_device *dev,
1138 uint32_t stringset, uint8_t *data)
1142 if (stringset == ETH_SS_STATS) {
1143 for (i = 0; i < ARRAY_SIZE(mv643xx_eth_stats); i++) {
1144 memcpy(data + i * ETH_GSTRING_LEN,
1145 mv643xx_eth_stats[i].stat_string,
1151 static void mv643xx_eth_get_ethtool_stats(struct net_device *dev,
1152 struct ethtool_stats *stats,
1155 struct mv643xx_eth_private *mp = dev->priv;
1158 mib_counters_update(mp);
1160 for (i = 0; i < ARRAY_SIZE(mv643xx_eth_stats); i++) {
1161 const struct mv643xx_eth_stats *stat;
1164 stat = mv643xx_eth_stats + i;
1166 if (stat->netdev_off >= 0)
1167 p = ((void *)mp->dev) + stat->netdev_off;
1169 p = ((void *)mp) + stat->mp_off;
1171 data[i] = (stat->sizeof_stat == 8) ?
1172 *(uint64_t *)p : *(uint32_t *)p;
1176 static int mv643xx_eth_get_sset_count(struct net_device *dev, int sset)
1178 if (sset == ETH_SS_STATS)
1179 return ARRAY_SIZE(mv643xx_eth_stats);
1184 static const struct ethtool_ops mv643xx_eth_ethtool_ops = {
1185 .get_settings = mv643xx_eth_get_settings,
1186 .set_settings = mv643xx_eth_set_settings,
1187 .get_drvinfo = mv643xx_eth_get_drvinfo,
1188 .nway_reset = mv643xx_eth_nway_reset,
1189 .get_link = mv643xx_eth_get_link,
1190 .set_sg = ethtool_op_set_sg,
1191 .get_strings = mv643xx_eth_get_strings,
1192 .get_ethtool_stats = mv643xx_eth_get_ethtool_stats,
1193 .get_sset_count = mv643xx_eth_get_sset_count,
1197 /* address handling *********************************************************/
1198 static void uc_addr_get(struct mv643xx_eth_private *mp, unsigned char *addr)
1203 mac_h = rdl(mp, MAC_ADDR_HIGH(mp->port_num));
1204 mac_l = rdl(mp, MAC_ADDR_LOW(mp->port_num));
1206 addr[0] = (mac_h >> 24) & 0xff;
1207 addr[1] = (mac_h >> 16) & 0xff;
1208 addr[2] = (mac_h >> 8) & 0xff;
1209 addr[3] = mac_h & 0xff;
1210 addr[4] = (mac_l >> 8) & 0xff;
1211 addr[5] = mac_l & 0xff;
1214 static void init_mac_tables(struct mv643xx_eth_private *mp)
1218 for (i = 0; i < 0x100; i += 4) {
1219 wrl(mp, SPECIAL_MCAST_TABLE(mp->port_num) + i, 0);
1220 wrl(mp, OTHER_MCAST_TABLE(mp->port_num) + i, 0);
1223 for (i = 0; i < 0x10; i += 4)
1224 wrl(mp, UNICAST_TABLE(mp->port_num) + i, 0);
1227 static void set_filter_table_entry(struct mv643xx_eth_private *mp,
1228 int table, unsigned char entry)
1230 unsigned int table_reg;
1232 /* Set "accepts frame bit" at specified table entry */
1233 table_reg = rdl(mp, table + (entry & 0xfc));
1234 table_reg |= 0x01 << (8 * (entry & 3));
1235 wrl(mp, table + (entry & 0xfc), table_reg);
1238 static void uc_addr_set(struct mv643xx_eth_private *mp, unsigned char *addr)
1244 mac_l = (addr[4] << 8) | addr[5];
1245 mac_h = (addr[0] << 24) | (addr[1] << 16) | (addr[2] << 8) | addr[3];
1247 wrl(mp, MAC_ADDR_LOW(mp->port_num), mac_l);
1248 wrl(mp, MAC_ADDR_HIGH(mp->port_num), mac_h);
1250 table = UNICAST_TABLE(mp->port_num);
1251 set_filter_table_entry(mp, table, addr[5] & 0x0f);
1254 static int mv643xx_eth_set_mac_address(struct net_device *dev, void *addr)
1256 struct mv643xx_eth_private *mp = netdev_priv(dev);
1258 /* +2 is for the offset of the HW addr type */
1259 memcpy(dev->dev_addr, addr + 2, 6);
1261 init_mac_tables(mp);
1262 uc_addr_set(mp, dev->dev_addr);
1267 static int addr_crc(unsigned char *addr)
1272 for (i = 0; i < 6; i++) {
1275 crc = (crc ^ addr[i]) << 8;
1276 for (j = 7; j >= 0; j--) {
1277 if (crc & (0x100 << j))
1285 static void mv643xx_eth_set_rx_mode(struct net_device *dev)
1287 struct mv643xx_eth_private *mp = netdev_priv(dev);
1289 struct dev_addr_list *addr;
1292 port_config = rdl(mp, PORT_CONFIG(mp->port_num));
1293 if (dev->flags & IFF_PROMISC)
1294 port_config |= UNICAST_PROMISCUOUS_MODE;
1296 port_config &= ~UNICAST_PROMISCUOUS_MODE;
1297 wrl(mp, PORT_CONFIG(mp->port_num), port_config);
1299 if (dev->flags & (IFF_PROMISC | IFF_ALLMULTI)) {
1300 int port_num = mp->port_num;
1301 u32 accept = 0x01010101;
1303 for (i = 0; i < 0x100; i += 4) {
1304 wrl(mp, SPECIAL_MCAST_TABLE(port_num) + i, accept);
1305 wrl(mp, OTHER_MCAST_TABLE(port_num) + i, accept);
1310 for (i = 0; i < 0x100; i += 4) {
1311 wrl(mp, SPECIAL_MCAST_TABLE(mp->port_num) + i, 0);
1312 wrl(mp, OTHER_MCAST_TABLE(mp->port_num) + i, 0);
1315 for (addr = dev->mc_list; addr != NULL; addr = addr->next) {
1316 u8 *a = addr->da_addr;
1319 if (addr->da_addrlen != 6)
1322 if (memcmp(a, "\x01\x00\x5e\x00\x00", 5) == 0) {
1323 table = SPECIAL_MCAST_TABLE(mp->port_num);
1324 set_filter_table_entry(mp, table, a[5]);
1326 int crc = addr_crc(a);
1328 table = OTHER_MCAST_TABLE(mp->port_num);
1329 set_filter_table_entry(mp, table, crc);
1335 /* rx/tx queue initialisation ***********************************************/
1336 static int rxq_init(struct mv643xx_eth_private *mp, int index)
1338 struct rx_queue *rxq = mp->rxq + index;
1339 struct rx_desc *rx_desc;
1345 rxq->rx_ring_size = mp->default_rx_ring_size;
1347 rxq->rx_desc_count = 0;
1348 rxq->rx_curr_desc = 0;
1349 rxq->rx_used_desc = 0;
1351 size = rxq->rx_ring_size * sizeof(struct rx_desc);
1353 if (index == mp->rxq_primary && size <= mp->rx_desc_sram_size) {
1354 rxq->rx_desc_area = ioremap(mp->rx_desc_sram_addr,
1355 mp->rx_desc_sram_size);
1356 rxq->rx_desc_dma = mp->rx_desc_sram_addr;
1358 rxq->rx_desc_area = dma_alloc_coherent(NULL, size,
1363 if (rxq->rx_desc_area == NULL) {
1364 dev_printk(KERN_ERR, &mp->dev->dev,
1365 "can't allocate rx ring (%d bytes)\n", size);
1368 memset(rxq->rx_desc_area, 0, size);
1370 rxq->rx_desc_area_size = size;
1371 rxq->rx_skb = kmalloc(rxq->rx_ring_size * sizeof(*rxq->rx_skb),
1373 if (rxq->rx_skb == NULL) {
1374 dev_printk(KERN_ERR, &mp->dev->dev,
1375 "can't allocate rx skb ring\n");
1379 rx_desc = (struct rx_desc *)rxq->rx_desc_area;
1380 for (i = 0; i < rxq->rx_ring_size; i++) {
1381 int nexti = (i + 1) % rxq->rx_ring_size;
1382 rx_desc[i].next_desc_ptr = rxq->rx_desc_dma +
1383 nexti * sizeof(struct rx_desc);
1386 init_timer(&rxq->rx_oom);
1387 rxq->rx_oom.data = (unsigned long)rxq;
1388 rxq->rx_oom.function = rxq_refill_timer_wrapper;
1394 if (index == mp->rxq_primary && size <= mp->rx_desc_sram_size)
1395 iounmap(rxq->rx_desc_area);
1397 dma_free_coherent(NULL, size,
1405 static void rxq_deinit(struct rx_queue *rxq)
1407 struct mv643xx_eth_private *mp = rxq_to_mp(rxq);
1412 del_timer_sync(&rxq->rx_oom);
1414 for (i = 0; i < rxq->rx_ring_size; i++) {
1415 if (rxq->rx_skb[i]) {
1416 dev_kfree_skb(rxq->rx_skb[i]);
1417 rxq->rx_desc_count--;
1421 if (rxq->rx_desc_count) {
1422 dev_printk(KERN_ERR, &mp->dev->dev,
1423 "error freeing rx ring -- %d skbs stuck\n",
1424 rxq->rx_desc_count);
1427 if (rxq->index == mp->rxq_primary &&
1428 rxq->rx_desc_area_size <= mp->rx_desc_sram_size)
1429 iounmap(rxq->rx_desc_area);
1431 dma_free_coherent(NULL, rxq->rx_desc_area_size,
1432 rxq->rx_desc_area, rxq->rx_desc_dma);
1437 static int txq_init(struct mv643xx_eth_private *mp, int index)
1439 struct tx_queue *txq = mp->txq + index;
1440 struct tx_desc *tx_desc;
1446 txq->tx_ring_size = mp->default_tx_ring_size;
1448 txq->tx_desc_count = 0;
1449 txq->tx_curr_desc = 0;
1450 txq->tx_used_desc = 0;
1452 size = txq->tx_ring_size * sizeof(struct tx_desc);
1454 if (index == mp->txq_primary && size <= mp->tx_desc_sram_size) {
1455 txq->tx_desc_area = ioremap(mp->tx_desc_sram_addr,
1456 mp->tx_desc_sram_size);
1457 txq->tx_desc_dma = mp->tx_desc_sram_addr;
1459 txq->tx_desc_area = dma_alloc_coherent(NULL, size,
1464 if (txq->tx_desc_area == NULL) {
1465 dev_printk(KERN_ERR, &mp->dev->dev,
1466 "can't allocate tx ring (%d bytes)\n", size);
1469 memset(txq->tx_desc_area, 0, size);
1471 txq->tx_desc_area_size = size;
1472 txq->tx_skb = kmalloc(txq->tx_ring_size * sizeof(*txq->tx_skb),
1474 if (txq->tx_skb == NULL) {
1475 dev_printk(KERN_ERR, &mp->dev->dev,
1476 "can't allocate tx skb ring\n");
1480 tx_desc = (struct tx_desc *)txq->tx_desc_area;
1481 for (i = 0; i < txq->tx_ring_size; i++) {
1482 int nexti = (i + 1) % txq->tx_ring_size;
1483 tx_desc[i].next_desc_ptr = txq->tx_desc_dma +
1484 nexti * sizeof(struct tx_desc);
1491 if (index == mp->txq_primary && size <= mp->tx_desc_sram_size)
1492 iounmap(txq->tx_desc_area);
1494 dma_free_coherent(NULL, size,
1502 static void txq_reclaim(struct tx_queue *txq, int force)
1504 struct mv643xx_eth_private *mp = txq_to_mp(txq);
1505 unsigned long flags;
1507 spin_lock_irqsave(&mp->lock, flags);
1508 while (txq->tx_desc_count > 0) {
1510 struct tx_desc *desc;
1512 struct sk_buff *skb;
1516 tx_index = txq->tx_used_desc;
1517 desc = &txq->tx_desc_area[tx_index];
1518 cmd_sts = desc->cmd_sts;
1520 if (!force && (cmd_sts & BUFFER_OWNED_BY_DMA))
1523 txq->tx_used_desc = (tx_index + 1) % txq->tx_ring_size;
1524 txq->tx_desc_count--;
1526 addr = desc->buf_ptr;
1527 count = desc->byte_cnt;
1528 skb = txq->tx_skb[tx_index];
1529 txq->tx_skb[tx_index] = NULL;
1531 if (cmd_sts & ERROR_SUMMARY) {
1532 dev_printk(KERN_INFO, &mp->dev->dev, "tx error\n");
1533 mp->dev->stats.tx_errors++;
1537 * Drop mp->lock while we free the skb.
1539 spin_unlock_irqrestore(&mp->lock, flags);
1541 if (cmd_sts & TX_FIRST_DESC)
1542 dma_unmap_single(NULL, addr, count, DMA_TO_DEVICE);
1544 dma_unmap_page(NULL, addr, count, DMA_TO_DEVICE);
1547 dev_kfree_skb_irq(skb);
1549 spin_lock_irqsave(&mp->lock, flags);
1551 spin_unlock_irqrestore(&mp->lock, flags);
1554 static void txq_deinit(struct tx_queue *txq)
1556 struct mv643xx_eth_private *mp = txq_to_mp(txq);
1559 txq_reclaim(txq, 1);
1561 BUG_ON(txq->tx_used_desc != txq->tx_curr_desc);
1563 if (txq->index == mp->txq_primary &&
1564 txq->tx_desc_area_size <= mp->tx_desc_sram_size)
1565 iounmap(txq->tx_desc_area);
1567 dma_free_coherent(NULL, txq->tx_desc_area_size,
1568 txq->tx_desc_area, txq->tx_desc_dma);
1574 /* netdev ops and related ***************************************************/
1575 static void update_pscr(struct mv643xx_eth_private *mp, int speed, int duplex)
1580 pscr_o = rdl(mp, PORT_SERIAL_CONTROL(mp->port_num));
1582 /* clear speed, duplex and rx buffer size fields */
1583 pscr_n = pscr_o & ~(SET_MII_SPEED_TO_100 |
1584 SET_GMII_SPEED_TO_1000 |
1585 SET_FULL_DUPLEX_MODE |
1586 MAX_RX_PACKET_MASK);
1588 if (speed == SPEED_1000) {
1589 pscr_n |= SET_GMII_SPEED_TO_1000 | MAX_RX_PACKET_9700BYTE;
1591 if (speed == SPEED_100)
1592 pscr_n |= SET_MII_SPEED_TO_100;
1593 pscr_n |= MAX_RX_PACKET_1522BYTE;
1596 if (duplex == DUPLEX_FULL)
1597 pscr_n |= SET_FULL_DUPLEX_MODE;
1599 if (pscr_n != pscr_o) {
1600 if ((pscr_o & SERIAL_PORT_ENABLE) == 0)
1601 wrl(mp, PORT_SERIAL_CONTROL(mp->port_num), pscr_n);
1605 for (i = 0; i < 8; i++)
1606 if (mp->txq_mask & (1 << i))
1607 txq_disable(mp->txq + i);
1609 pscr_o &= ~SERIAL_PORT_ENABLE;
1610 wrl(mp, PORT_SERIAL_CONTROL(mp->port_num), pscr_o);
1611 wrl(mp, PORT_SERIAL_CONTROL(mp->port_num), pscr_n);
1612 wrl(mp, PORT_SERIAL_CONTROL(mp->port_num), pscr_n);
1614 for (i = 0; i < 8; i++)
1615 if (mp->txq_mask & (1 << i))
1616 txq_enable(mp->txq + i);
1621 static irqreturn_t mv643xx_eth_irq(int irq, void *dev_id)
1623 struct net_device *dev = (struct net_device *)dev_id;
1624 struct mv643xx_eth_private *mp = netdev_priv(dev);
1629 int_cause = rdl(mp, INT_CAUSE(mp->port_num)) &
1630 (INT_TX_END | INT_RX | INT_EXT);
1635 if (int_cause & INT_EXT) {
1636 int_cause_ext = rdl(mp, INT_CAUSE_EXT(mp->port_num))
1637 & (INT_EXT_LINK | INT_EXT_PHY | INT_EXT_TX);
1638 wrl(mp, INT_CAUSE_EXT(mp->port_num), ~int_cause_ext);
1641 if (int_cause_ext & (INT_EXT_PHY | INT_EXT_LINK)) {
1642 if (mii_link_ok(&mp->mii)) {
1643 struct ethtool_cmd cmd;
1646 mii_ethtool_gset(&mp->mii, &cmd);
1647 update_pscr(mp, cmd.speed, cmd.duplex);
1648 for (i = 0; i < 8; i++)
1649 if (mp->txq_mask & (1 << i))
1650 txq_enable(mp->txq + i);
1652 if (!netif_carrier_ok(dev)) {
1653 netif_carrier_on(dev);
1654 __txq_maybe_wake(mp->txq + mp->txq_primary);
1656 } else if (netif_carrier_ok(dev)) {
1657 netif_stop_queue(dev);
1658 netif_carrier_off(dev);
1663 * RxBuffer or RxError set for any of the 8 queues?
1665 #ifdef MV643XX_ETH_NAPI
1666 if (int_cause & INT_RX) {
1667 wrl(mp, INT_MASK(mp->port_num), 0x00000000);
1668 rdl(mp, INT_MASK(mp->port_num));
1670 netif_rx_schedule(dev, &mp->napi);
1673 if (int_cause & INT_RX) {
1676 for (i = 7; i >= 0; i--)
1677 if (mp->rxq_mask & (1 << i))
1678 rxq_process(mp->rxq + i, INT_MAX);
1682 txq_active = rdl(mp, TXQ_COMMAND(mp->port_num));
1685 * TxBuffer or TxError set for any of the 8 queues?
1687 if (int_cause_ext & INT_EXT_TX) {
1690 for (i = 0; i < 8; i++)
1691 if (mp->txq_mask & (1 << i))
1692 txq_reclaim(mp->txq + i, 0);
1696 * Any TxEnd interrupts?
1698 if (int_cause & INT_TX_END) {
1701 wrl(mp, INT_CAUSE(mp->port_num), ~(int_cause & INT_TX_END));
1702 for (i = 0; i < 8; i++) {
1703 struct tx_queue *txq = mp->txq + i;
1704 if (txq->tx_desc_count && !((txq_active >> i) & 1))
1710 * Enough space again in the primary TX queue for a full packet?
1712 if (int_cause_ext & INT_EXT_TX) {
1713 struct tx_queue *txq = mp->txq + mp->txq_primary;
1714 __txq_maybe_wake(txq);
1720 static void phy_reset(struct mv643xx_eth_private *mp)
1724 smi_reg_read(mp, mp->phy_addr, 0, &data);
1726 smi_reg_write(mp, mp->phy_addr, 0, data);
1730 smi_reg_read(mp, mp->phy_addr, 0, &data);
1731 } while (data & 0x8000);
1734 static void port_start(struct mv643xx_eth_private *mp)
1737 struct ethtool_cmd ethtool_cmd;
1741 * Configure basic link parameters.
1743 pscr = rdl(mp, PORT_SERIAL_CONTROL(mp->port_num));
1744 pscr &= ~(SERIAL_PORT_ENABLE | FORCE_LINK_PASS);
1745 wrl(mp, PORT_SERIAL_CONTROL(mp->port_num), pscr);
1746 pscr |= DISABLE_AUTO_NEG_FOR_FLOW_CTRL |
1747 DISABLE_AUTO_NEG_SPEED_GMII |
1748 DISABLE_AUTO_NEG_FOR_DUPLEX |
1749 DO_NOT_FORCE_LINK_FAIL |
1750 SERIAL_PORT_CONTROL_RESERVED;
1751 wrl(mp, PORT_SERIAL_CONTROL(mp->port_num), pscr);
1752 pscr |= SERIAL_PORT_ENABLE;
1753 wrl(mp, PORT_SERIAL_CONTROL(mp->port_num), pscr);
1755 wrl(mp, SDMA_CONFIG(mp->port_num), PORT_SDMA_CONFIG_DEFAULT_VALUE);
1757 mv643xx_eth_get_settings(mp->dev, ðtool_cmd);
1759 mv643xx_eth_set_settings(mp->dev, ðtool_cmd);
1762 * Configure TX path and queues.
1764 tx_set_rate(mp, 1000000000, 16777216);
1765 for (i = 0; i < 8; i++) {
1766 struct tx_queue *txq = mp->txq + i;
1767 int off = TXQ_CURRENT_DESC_PTR(mp->port_num, i);
1770 if ((mp->txq_mask & (1 << i)) == 0)
1773 addr = (u32)txq->tx_desc_dma;
1774 addr += txq->tx_curr_desc * sizeof(struct tx_desc);
1777 txq_set_rate(txq, 1000000000, 16777216);
1778 txq_set_fixed_prio_mode(txq);
1782 * Add configured unicast address to address filter table.
1784 uc_addr_set(mp, mp->dev->dev_addr);
1787 * Receive all unmatched unicast, TCP, UDP, BPDU and broadcast
1788 * frames to RX queue #0.
1790 wrl(mp, PORT_CONFIG(mp->port_num), 0x00000000);
1793 * Treat BPDUs as normal multicasts, and disable partition mode.
1795 wrl(mp, PORT_CONFIG_EXT(mp->port_num), 0x00000000);
1798 * Enable the receive queues.
1800 for (i = 0; i < 8; i++) {
1801 struct rx_queue *rxq = mp->rxq + i;
1802 int off = RXQ_CURRENT_DESC_PTR(mp->port_num, i);
1805 if ((mp->rxq_mask & (1 << i)) == 0)
1808 addr = (u32)rxq->rx_desc_dma;
1809 addr += rxq->rx_curr_desc * sizeof(struct rx_desc);
1816 static void set_rx_coal(struct mv643xx_eth_private *mp, unsigned int delay)
1818 unsigned int coal = ((mp->shared->t_clk / 1000000) * delay) / 64;
1821 val = rdl(mp, SDMA_CONFIG(mp->port_num));
1822 if (mp->shared->extended_rx_coal_limit) {
1826 val |= (coal & 0x8000) << 10;
1827 val |= (coal & 0x7fff) << 7;
1832 val |= (coal & 0x3fff) << 8;
1834 wrl(mp, SDMA_CONFIG(mp->port_num), val);
1837 static void set_tx_coal(struct mv643xx_eth_private *mp, unsigned int delay)
1839 unsigned int coal = ((mp->shared->t_clk / 1000000) * delay) / 64;
1843 wrl(mp, TX_FIFO_URGENT_THRESHOLD(mp->port_num), (coal & 0x3fff) << 4);
1846 static int mv643xx_eth_open(struct net_device *dev)
1848 struct mv643xx_eth_private *mp = netdev_priv(dev);
1852 wrl(mp, INT_CAUSE(mp->port_num), 0);
1853 wrl(mp, INT_CAUSE_EXT(mp->port_num), 0);
1854 rdl(mp, INT_CAUSE_EXT(mp->port_num));
1856 err = request_irq(dev->irq, mv643xx_eth_irq,
1857 IRQF_SHARED | IRQF_SAMPLE_RANDOM,
1860 dev_printk(KERN_ERR, &dev->dev, "can't assign irq\n");
1864 init_mac_tables(mp);
1866 for (i = 0; i < 8; i++) {
1867 if ((mp->rxq_mask & (1 << i)) == 0)
1870 err = rxq_init(mp, i);
1873 if (mp->rxq_mask & (1 << i))
1874 rxq_deinit(mp->rxq + i);
1878 rxq_refill(mp->rxq + i);
1881 for (i = 0; i < 8; i++) {
1882 if ((mp->txq_mask & (1 << i)) == 0)
1885 err = txq_init(mp, i);
1888 if (mp->txq_mask & (1 << i))
1889 txq_deinit(mp->txq + i);
1894 #ifdef MV643XX_ETH_NAPI
1895 napi_enable(&mp->napi);
1903 wrl(mp, INT_MASK_EXT(mp->port_num),
1904 INT_EXT_LINK | INT_EXT_PHY | INT_EXT_TX);
1906 wrl(mp, INT_MASK(mp->port_num), INT_TX_END | INT_RX | INT_EXT);
1912 for (i = 0; i < 8; i++)
1913 if (mp->rxq_mask & (1 << i))
1914 rxq_deinit(mp->rxq + i);
1916 free_irq(dev->irq, dev);
1921 static void port_reset(struct mv643xx_eth_private *mp)
1926 for (i = 0; i < 8; i++) {
1927 if (mp->rxq_mask & (1 << i))
1928 rxq_disable(mp->rxq + i);
1929 if (mp->txq_mask & (1 << i))
1930 txq_disable(mp->txq + i);
1932 while (!(rdl(mp, PORT_STATUS(mp->port_num)) & TX_FIFO_EMPTY))
1935 /* Reset the Enable bit in the Configuration Register */
1936 data = rdl(mp, PORT_SERIAL_CONTROL(mp->port_num));
1937 data &= ~(SERIAL_PORT_ENABLE |
1938 DO_NOT_FORCE_LINK_FAIL |
1940 wrl(mp, PORT_SERIAL_CONTROL(mp->port_num), data);
1943 static int mv643xx_eth_stop(struct net_device *dev)
1945 struct mv643xx_eth_private *mp = netdev_priv(dev);
1948 wrl(mp, INT_MASK(mp->port_num), 0x00000000);
1949 rdl(mp, INT_MASK(mp->port_num));
1951 #ifdef MV643XX_ETH_NAPI
1952 napi_disable(&mp->napi);
1954 netif_carrier_off(dev);
1955 netif_stop_queue(dev);
1957 free_irq(dev->irq, dev);
1960 mib_counters_update(mp);
1962 for (i = 0; i < 8; i++) {
1963 if (mp->rxq_mask & (1 << i))
1964 rxq_deinit(mp->rxq + i);
1965 if (mp->txq_mask & (1 << i))
1966 txq_deinit(mp->txq + i);
1972 static int mv643xx_eth_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
1974 struct mv643xx_eth_private *mp = netdev_priv(dev);
1976 return generic_mii_ioctl(&mp->mii, if_mii(ifr), cmd, NULL);
1979 static int mv643xx_eth_change_mtu(struct net_device *dev, int new_mtu)
1981 struct mv643xx_eth_private *mp = netdev_priv(dev);
1983 if (new_mtu < 64 || new_mtu > 9500)
1987 tx_set_rate(mp, 1000000000, 16777216);
1989 if (!netif_running(dev))
1993 * Stop and then re-open the interface. This will allocate RX
1994 * skbs of the new MTU.
1995 * There is a possible danger that the open will not succeed,
1996 * due to memory being full.
1998 mv643xx_eth_stop(dev);
1999 if (mv643xx_eth_open(dev)) {
2000 dev_printk(KERN_ERR, &dev->dev,
2001 "fatal error on re-opening device after "
2008 static void tx_timeout_task(struct work_struct *ugly)
2010 struct mv643xx_eth_private *mp;
2012 mp = container_of(ugly, struct mv643xx_eth_private, tx_timeout_task);
2013 if (netif_running(mp->dev)) {
2014 netif_stop_queue(mp->dev);
2019 __txq_maybe_wake(mp->txq + mp->txq_primary);
2023 static void mv643xx_eth_tx_timeout(struct net_device *dev)
2025 struct mv643xx_eth_private *mp = netdev_priv(dev);
2027 dev_printk(KERN_INFO, &dev->dev, "tx timeout\n");
2029 schedule_work(&mp->tx_timeout_task);
2032 #ifdef CONFIG_NET_POLL_CONTROLLER
2033 static void mv643xx_eth_netpoll(struct net_device *dev)
2035 struct mv643xx_eth_private *mp = netdev_priv(dev);
2037 wrl(mp, INT_MASK(mp->port_num), 0x00000000);
2038 rdl(mp, INT_MASK(mp->port_num));
2040 mv643xx_eth_irq(dev->irq, dev);
2042 wrl(mp, INT_MASK(mp->port_num), INT_TX_END | INT_RX | INT_CAUSE_EXT);
2046 static int mv643xx_eth_mdio_read(struct net_device *dev, int addr, int reg)
2048 struct mv643xx_eth_private *mp = netdev_priv(dev);
2051 smi_reg_read(mp, addr, reg, &val);
2056 static void mv643xx_eth_mdio_write(struct net_device *dev, int addr, int reg, int val)
2058 struct mv643xx_eth_private *mp = netdev_priv(dev);
2059 smi_reg_write(mp, addr, reg, val);
2063 /* platform glue ************************************************************/
2065 mv643xx_eth_conf_mbus_windows(struct mv643xx_eth_shared_private *msp,
2066 struct mbus_dram_target_info *dram)
2068 void __iomem *base = msp->base;
2073 for (i = 0; i < 6; i++) {
2074 writel(0, base + WINDOW_BASE(i));
2075 writel(0, base + WINDOW_SIZE(i));
2077 writel(0, base + WINDOW_REMAP_HIGH(i));
2083 for (i = 0; i < dram->num_cs; i++) {
2084 struct mbus_dram_window *cs = dram->cs + i;
2086 writel((cs->base & 0xffff0000) |
2087 (cs->mbus_attr << 8) |
2088 dram->mbus_dram_target_id, base + WINDOW_BASE(i));
2089 writel((cs->size - 1) & 0xffff0000, base + WINDOW_SIZE(i));
2091 win_enable &= ~(1 << i);
2092 win_protect |= 3 << (2 * i);
2095 writel(win_enable, base + WINDOW_BAR_ENABLE);
2096 msp->win_protect = win_protect;
2099 static void infer_hw_params(struct mv643xx_eth_shared_private *msp)
2102 * Check whether we have a 14-bit coal limit field in bits
2103 * [21:8], or a 16-bit coal limit in bits [25,21:7] of the
2104 * SDMA config register.
2106 writel(0x02000000, msp->base + SDMA_CONFIG(0));
2107 if (readl(msp->base + SDMA_CONFIG(0)) & 0x02000000)
2108 msp->extended_rx_coal_limit = 1;
2110 msp->extended_rx_coal_limit = 0;
2113 static int mv643xx_eth_shared_probe(struct platform_device *pdev)
2115 static int mv643xx_eth_version_printed = 0;
2116 struct mv643xx_eth_shared_platform_data *pd = pdev->dev.platform_data;
2117 struct mv643xx_eth_shared_private *msp;
2118 struct resource *res;
2121 if (!mv643xx_eth_version_printed++)
2122 printk(KERN_NOTICE "MV-643xx 10/100/1000 Ethernet Driver\n");
2125 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2130 msp = kmalloc(sizeof(*msp), GFP_KERNEL);
2133 memset(msp, 0, sizeof(*msp));
2135 msp->base = ioremap(res->start, res->end - res->start + 1);
2136 if (msp->base == NULL)
2139 spin_lock_init(&msp->phy_lock);
2142 * (Re-)program MBUS remapping windows if we are asked to.
2144 if (pd != NULL && pd->dram != NULL)
2145 mv643xx_eth_conf_mbus_windows(msp, pd->dram);
2148 * Detect hardware parameters.
2150 msp->t_clk = (pd != NULL && pd->t_clk != 0) ? pd->t_clk : 133000000;
2151 infer_hw_params(msp);
2153 platform_set_drvdata(pdev, msp);
2163 static int mv643xx_eth_shared_remove(struct platform_device *pdev)
2165 struct mv643xx_eth_shared_private *msp = platform_get_drvdata(pdev);
2173 static struct platform_driver mv643xx_eth_shared_driver = {
2174 .probe = mv643xx_eth_shared_probe,
2175 .remove = mv643xx_eth_shared_remove,
2177 .name = MV643XX_ETH_SHARED_NAME,
2178 .owner = THIS_MODULE,
2182 static void phy_addr_set(struct mv643xx_eth_private *mp, int phy_addr)
2184 int addr_shift = 5 * mp->port_num;
2187 data = rdl(mp, PHY_ADDR);
2188 data &= ~(0x1f << addr_shift);
2189 data |= (phy_addr & 0x1f) << addr_shift;
2190 wrl(mp, PHY_ADDR, data);
2193 static int phy_addr_get(struct mv643xx_eth_private *mp)
2197 data = rdl(mp, PHY_ADDR);
2199 return (data >> (5 * mp->port_num)) & 0x1f;
2202 static void set_params(struct mv643xx_eth_private *mp,
2203 struct mv643xx_eth_platform_data *pd)
2205 struct net_device *dev = mp->dev;
2207 if (is_valid_ether_addr(pd->mac_addr))
2208 memcpy(dev->dev_addr, pd->mac_addr, 6);
2210 uc_addr_get(mp, dev->dev_addr);
2212 if (pd->phy_addr == -1) {
2213 mp->shared_smi = NULL;
2216 mp->shared_smi = mp->shared;
2217 if (pd->shared_smi != NULL)
2218 mp->shared_smi = platform_get_drvdata(pd->shared_smi);
2220 if (pd->force_phy_addr || pd->phy_addr) {
2221 mp->phy_addr = pd->phy_addr & 0x3f;
2222 phy_addr_set(mp, mp->phy_addr);
2224 mp->phy_addr = phy_addr_get(mp);
2228 mp->default_rx_ring_size = DEFAULT_RX_QUEUE_SIZE;
2229 if (pd->rx_queue_size)
2230 mp->default_rx_ring_size = pd->rx_queue_size;
2231 mp->rx_desc_sram_addr = pd->rx_sram_addr;
2232 mp->rx_desc_sram_size = pd->rx_sram_size;
2234 if (pd->rx_queue_mask)
2235 mp->rxq_mask = pd->rx_queue_mask;
2237 mp->rxq_mask = 0x01;
2238 mp->rxq_primary = fls(mp->rxq_mask) - 1;
2240 mp->default_tx_ring_size = DEFAULT_TX_QUEUE_SIZE;
2241 if (pd->tx_queue_size)
2242 mp->default_tx_ring_size = pd->tx_queue_size;
2243 mp->tx_desc_sram_addr = pd->tx_sram_addr;
2244 mp->tx_desc_sram_size = pd->tx_sram_size;
2246 if (pd->tx_queue_mask)
2247 mp->txq_mask = pd->tx_queue_mask;
2249 mp->txq_mask = 0x01;
2250 mp->txq_primary = fls(mp->txq_mask) - 1;
2253 static int phy_detect(struct mv643xx_eth_private *mp)
2258 smi_reg_read(mp, mp->phy_addr, 0, &data);
2259 smi_reg_write(mp, mp->phy_addr, 0, data ^ 0x1000);
2261 smi_reg_read(mp, mp->phy_addr, 0, &data2);
2262 if (((data ^ data2) & 0x1000) == 0)
2265 smi_reg_write(mp, mp->phy_addr, 0, data);
2270 static int phy_init(struct mv643xx_eth_private *mp,
2271 struct mv643xx_eth_platform_data *pd)
2273 struct ethtool_cmd cmd;
2276 err = phy_detect(mp);
2278 dev_printk(KERN_INFO, &mp->dev->dev,
2279 "no PHY detected at addr %d\n", mp->phy_addr);
2284 mp->mii.phy_id = mp->phy_addr;
2285 mp->mii.phy_id_mask = 0x3f;
2286 mp->mii.reg_num_mask = 0x1f;
2287 mp->mii.dev = mp->dev;
2288 mp->mii.mdio_read = mv643xx_eth_mdio_read;
2289 mp->mii.mdio_write = mv643xx_eth_mdio_write;
2291 mp->mii.supports_gmii = mii_check_gmii_support(&mp->mii);
2293 memset(&cmd, 0, sizeof(cmd));
2295 cmd.port = PORT_MII;
2296 cmd.transceiver = XCVR_INTERNAL;
2297 cmd.phy_address = mp->phy_addr;
2298 if (pd->speed == 0) {
2299 cmd.autoneg = AUTONEG_ENABLE;
2300 cmd.speed = SPEED_100;
2301 cmd.advertising = ADVERTISED_10baseT_Half |
2302 ADVERTISED_10baseT_Full |
2303 ADVERTISED_100baseT_Half |
2304 ADVERTISED_100baseT_Full;
2305 if (mp->mii.supports_gmii)
2306 cmd.advertising |= ADVERTISED_1000baseT_Full;
2308 cmd.autoneg = AUTONEG_DISABLE;
2309 cmd.speed = pd->speed;
2310 cmd.duplex = pd->duplex;
2313 update_pscr(mp, cmd.speed, cmd.duplex);
2314 mv643xx_eth_set_settings(mp->dev, &cmd);
2319 static int mv643xx_eth_probe(struct platform_device *pdev)
2321 struct mv643xx_eth_platform_data *pd;
2322 struct mv643xx_eth_private *mp;
2323 struct net_device *dev;
2324 struct resource *res;
2325 DECLARE_MAC_BUF(mac);
2328 pd = pdev->dev.platform_data;
2330 dev_printk(KERN_ERR, &pdev->dev,
2331 "no mv643xx_eth_platform_data\n");
2335 if (pd->shared == NULL) {
2336 dev_printk(KERN_ERR, &pdev->dev,
2337 "no mv643xx_eth_platform_data->shared\n");
2341 dev = alloc_etherdev(sizeof(struct mv643xx_eth_private));
2345 mp = netdev_priv(dev);
2346 platform_set_drvdata(pdev, mp);
2348 mp->shared = platform_get_drvdata(pd->shared);
2349 mp->port_num = pd->port_number;
2352 #ifdef MV643XX_ETH_NAPI
2353 netif_napi_add(dev, &mp->napi, mv643xx_eth_poll, 64);
2358 spin_lock_init(&mp->lock);
2360 mib_counters_clear(mp);
2361 INIT_WORK(&mp->tx_timeout_task, tx_timeout_task);
2363 err = phy_init(mp, pd);
2366 SET_ETHTOOL_OPS(dev, &mv643xx_eth_ethtool_ops);
2369 res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
2371 dev->irq = res->start;
2373 dev->hard_start_xmit = mv643xx_eth_xmit;
2374 dev->open = mv643xx_eth_open;
2375 dev->stop = mv643xx_eth_stop;
2376 dev->set_multicast_list = mv643xx_eth_set_rx_mode;
2377 dev->set_mac_address = mv643xx_eth_set_mac_address;
2378 dev->do_ioctl = mv643xx_eth_ioctl;
2379 dev->change_mtu = mv643xx_eth_change_mtu;
2380 dev->tx_timeout = mv643xx_eth_tx_timeout;
2381 #ifdef CONFIG_NET_POLL_CONTROLLER
2382 dev->poll_controller = mv643xx_eth_netpoll;
2384 dev->watchdog_timeo = 2 * HZ;
2387 #ifdef MV643XX_ETH_CHECKSUM_OFFLOAD_TX
2389 * Zero copy can only work if we use Discovery II memory. Else, we will
2390 * have to map the buffers to ISA memory which is only 16 MB
2392 dev->features = NETIF_F_SG | NETIF_F_IP_CSUM;
2395 SET_NETDEV_DEV(dev, &pdev->dev);
2397 if (mp->shared->win_protect)
2398 wrl(mp, WINDOW_PROTECT(mp->port_num), mp->shared->win_protect);
2400 err = register_netdev(dev);
2404 dev_printk(KERN_NOTICE, &dev->dev, "port %d with MAC address %s\n",
2405 mp->port_num, print_mac(mac, dev->dev_addr));
2407 if (dev->features & NETIF_F_SG)
2408 dev_printk(KERN_NOTICE, &dev->dev, "scatter/gather enabled\n");
2410 if (dev->features & NETIF_F_IP_CSUM)
2411 dev_printk(KERN_NOTICE, &dev->dev, "tx checksum offload\n");
2413 #ifdef MV643XX_ETH_NAPI
2414 dev_printk(KERN_NOTICE, &dev->dev, "napi enabled\n");
2417 if (mp->tx_desc_sram_size > 0)
2418 dev_printk(KERN_NOTICE, &dev->dev, "configured with sram\n");
2428 static int mv643xx_eth_remove(struct platform_device *pdev)
2430 struct mv643xx_eth_private *mp = platform_get_drvdata(pdev);
2432 unregister_netdev(mp->dev);
2433 flush_scheduled_work();
2434 free_netdev(mp->dev);
2436 platform_set_drvdata(pdev, NULL);
2441 static void mv643xx_eth_shutdown(struct platform_device *pdev)
2443 struct mv643xx_eth_private *mp = platform_get_drvdata(pdev);
2445 /* Mask all interrupts on ethernet port */
2446 wrl(mp, INT_MASK(mp->port_num), 0);
2447 rdl(mp, INT_MASK(mp->port_num));
2449 if (netif_running(mp->dev))
2453 static struct platform_driver mv643xx_eth_driver = {
2454 .probe = mv643xx_eth_probe,
2455 .remove = mv643xx_eth_remove,
2456 .shutdown = mv643xx_eth_shutdown,
2458 .name = MV643XX_ETH_NAME,
2459 .owner = THIS_MODULE,
2463 static int __init mv643xx_eth_init_module(void)
2467 rc = platform_driver_register(&mv643xx_eth_shared_driver);
2469 rc = platform_driver_register(&mv643xx_eth_driver);
2471 platform_driver_unregister(&mv643xx_eth_shared_driver);
2476 module_init(mv643xx_eth_init_module);
2478 static void __exit mv643xx_eth_cleanup_module(void)
2480 platform_driver_unregister(&mv643xx_eth_driver);
2481 platform_driver_unregister(&mv643xx_eth_shared_driver);
2483 module_exit(mv643xx_eth_cleanup_module);
2485 MODULE_AUTHOR("Rabeeh Khoury, Assaf Hoffman, Matthew Dharm, Manish Lachwani "
2486 "and Dale Farnsworth");
2487 MODULE_DESCRIPTION("Ethernet driver for Marvell MV643XX");
2488 MODULE_LICENSE("GPL");
2489 MODULE_ALIAS("platform:" MV643XX_ETH_SHARED_NAME);
2490 MODULE_ALIAS("platform:" MV643XX_ETH_NAME);