2 * Driver for Marvell Discovery (MV643XX) and Marvell Orion ethernet ports
3 * Copyright (C) 2002 Matthew Dharm <mdharm@momenco.com>
5 * Based on the 64360 driver from:
6 * Copyright (C) 2002 Rabeeh Khoury <rabeeh@galileo.co.il>
7 * Rabeeh Khoury <rabeeh@marvell.com>
9 * Copyright (C) 2003 PMC-Sierra, Inc.,
10 * written by Manish Lachwani
12 * Copyright (C) 2003 Ralf Baechle <ralf@linux-mips.org>
14 * Copyright (C) 2004-2006 MontaVista Software, Inc.
15 * Dale Farnsworth <dale@farnsworth.org>
17 * Copyright (C) 2004 Steven J. Hill <sjhill1@rockwellcollins.com>
18 * <sjhill@realitydiluted.com>
20 * Copyright (C) 2007-2008 Marvell Semiconductor
21 * Lennert Buytenhek <buytenh@marvell.com>
23 * This program is free software; you can redistribute it and/or
24 * modify it under the terms of the GNU General Public License
25 * as published by the Free Software Foundation; either version 2
26 * of the License, or (at your option) any later version.
28 * This program is distributed in the hope that it will be useful,
29 * but WITHOUT ANY WARRANTY; without even the implied warranty of
30 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
31 * GNU General Public License for more details.
33 * You should have received a copy of the GNU General Public License
34 * along with this program; if not, write to the Free Software
35 * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
38 #include <linux/init.h>
39 #include <linux/dma-mapping.h>
41 #include <linux/tcp.h>
42 #include <linux/udp.h>
43 #include <linux/etherdevice.h>
44 #include <linux/delay.h>
45 #include <linux/ethtool.h>
46 #include <linux/platform_device.h>
47 #include <linux/module.h>
48 #include <linux/kernel.h>
49 #include <linux/spinlock.h>
50 #include <linux/workqueue.h>
51 #include <linux/mii.h>
52 #include <linux/mv643xx_eth.h>
54 #include <asm/types.h>
55 #include <asm/system.h>
57 static char mv643xx_eth_driver_name[] = "mv643xx_eth";
58 static char mv643xx_eth_driver_version[] = "1.1";
60 #define MV643XX_ETH_CHECKSUM_OFFLOAD_TX
61 #define MV643XX_ETH_NAPI
62 #define MV643XX_ETH_TX_FAST_REFILL
64 #ifdef MV643XX_ETH_CHECKSUM_OFFLOAD_TX
65 #define MAX_DESCS_PER_SKB (MAX_SKB_FRAGS + 1)
67 #define MAX_DESCS_PER_SKB 1
71 * Registers shared between all ports.
73 #define PHY_ADDR 0x0000
74 #define SMI_REG 0x0004
75 #define WINDOW_BASE(w) (0x0200 + ((w) << 3))
76 #define WINDOW_SIZE(w) (0x0204 + ((w) << 3))
77 #define WINDOW_REMAP_HIGH(w) (0x0280 + ((w) << 2))
78 #define WINDOW_BAR_ENABLE 0x0290
79 #define WINDOW_PROTECT(w) (0x0294 + ((w) << 4))
84 #define PORT_CONFIG(p) (0x0400 + ((p) << 10))
85 #define UNICAST_PROMISCUOUS_MODE 0x00000001
86 #define PORT_CONFIG_EXT(p) (0x0404 + ((p) << 10))
87 #define MAC_ADDR_LOW(p) (0x0414 + ((p) << 10))
88 #define MAC_ADDR_HIGH(p) (0x0418 + ((p) << 10))
89 #define SDMA_CONFIG(p) (0x041c + ((p) << 10))
90 #define PORT_SERIAL_CONTROL(p) (0x043c + ((p) << 10))
91 #define PORT_STATUS(p) (0x0444 + ((p) << 10))
92 #define TX_FIFO_EMPTY 0x00000400
93 #define TX_IN_PROGRESS 0x00000080
94 #define PORT_SPEED_MASK 0x00000030
95 #define PORT_SPEED_1000 0x00000010
96 #define PORT_SPEED_100 0x00000020
97 #define PORT_SPEED_10 0x00000000
98 #define FLOW_CONTROL_ENABLED 0x00000008
99 #define FULL_DUPLEX 0x00000004
100 #define LINK_UP 0x00000002
101 #define TXQ_COMMAND(p) (0x0448 + ((p) << 10))
102 #define TXQ_FIX_PRIO_CONF(p) (0x044c + ((p) << 10))
103 #define TX_BW_RATE(p) (0x0450 + ((p) << 10))
104 #define TX_BW_MTU(p) (0x0458 + ((p) << 10))
105 #define TX_BW_BURST(p) (0x045c + ((p) << 10))
106 #define INT_CAUSE(p) (0x0460 + ((p) << 10))
107 #define INT_TX_END_0 0x00080000
108 #define INT_TX_END 0x07f80000
109 #define INT_RX 0x0007fbfc
110 #define INT_EXT 0x00000002
111 #define INT_CAUSE_EXT(p) (0x0464 + ((p) << 10))
112 #define INT_EXT_LINK 0x00100000
113 #define INT_EXT_PHY 0x00010000
114 #define INT_EXT_TX_ERROR_0 0x00000100
115 #define INT_EXT_TX_0 0x00000001
116 #define INT_EXT_TX 0x0000ffff
117 #define INT_MASK(p) (0x0468 + ((p) << 10))
118 #define INT_MASK_EXT(p) (0x046c + ((p) << 10))
119 #define TX_FIFO_URGENT_THRESHOLD(p) (0x0474 + ((p) << 10))
120 #define TXQ_FIX_PRIO_CONF_MOVED(p) (0x04dc + ((p) << 10))
121 #define TX_BW_RATE_MOVED(p) (0x04e0 + ((p) << 10))
122 #define TX_BW_MTU_MOVED(p) (0x04e8 + ((p) << 10))
123 #define TX_BW_BURST_MOVED(p) (0x04ec + ((p) << 10))
124 #define RXQ_CURRENT_DESC_PTR(p, q) (0x060c + ((p) << 10) + ((q) << 4))
125 #define RXQ_COMMAND(p) (0x0680 + ((p) << 10))
126 #define TXQ_CURRENT_DESC_PTR(p, q) (0x06c0 + ((p) << 10) + ((q) << 2))
127 #define TXQ_BW_TOKENS(p, q) (0x0700 + ((p) << 10) + ((q) << 4))
128 #define TXQ_BW_CONF(p, q) (0x0704 + ((p) << 10) + ((q) << 4))
129 #define TXQ_BW_WRR_CONF(p, q) (0x0708 + ((p) << 10) + ((q) << 4))
130 #define MIB_COUNTERS(p) (0x1000 + ((p) << 7))
131 #define SPECIAL_MCAST_TABLE(p) (0x1400 + ((p) << 10))
132 #define OTHER_MCAST_TABLE(p) (0x1500 + ((p) << 10))
133 #define UNICAST_TABLE(p) (0x1600 + ((p) << 10))
137 * SDMA configuration register.
139 #define RX_BURST_SIZE_16_64BIT (4 << 1)
140 #define BLM_RX_NO_SWAP (1 << 4)
141 #define BLM_TX_NO_SWAP (1 << 5)
142 #define TX_BURST_SIZE_16_64BIT (4 << 22)
144 #if defined(__BIG_ENDIAN)
145 #define PORT_SDMA_CONFIG_DEFAULT_VALUE \
146 RX_BURST_SIZE_16_64BIT | \
147 TX_BURST_SIZE_16_64BIT
148 #elif defined(__LITTLE_ENDIAN)
149 #define PORT_SDMA_CONFIG_DEFAULT_VALUE \
150 RX_BURST_SIZE_16_64BIT | \
153 TX_BURST_SIZE_16_64BIT
155 #error One of __BIG_ENDIAN or __LITTLE_ENDIAN must be defined
160 * Port serial control register.
162 #define SET_MII_SPEED_TO_100 (1 << 24)
163 #define SET_GMII_SPEED_TO_1000 (1 << 23)
164 #define SET_FULL_DUPLEX_MODE (1 << 21)
165 #define MAX_RX_PACKET_9700BYTE (5 << 17)
166 #define DISABLE_AUTO_NEG_SPEED_GMII (1 << 13)
167 #define DO_NOT_FORCE_LINK_FAIL (1 << 10)
168 #define SERIAL_PORT_CONTROL_RESERVED (1 << 9)
169 #define DISABLE_AUTO_NEG_FOR_FLOW_CTRL (1 << 3)
170 #define DISABLE_AUTO_NEG_FOR_DUPLEX (1 << 2)
171 #define FORCE_LINK_PASS (1 << 1)
172 #define SERIAL_PORT_ENABLE (1 << 0)
174 #define DEFAULT_RX_QUEUE_SIZE 400
175 #define DEFAULT_TX_QUEUE_SIZE 800
181 #if defined(__BIG_ENDIAN)
183 u16 byte_cnt; /* Descriptor buffer byte count */
184 u16 buf_size; /* Buffer size */
185 u32 cmd_sts; /* Descriptor command status */
186 u32 next_desc_ptr; /* Next descriptor pointer */
187 u32 buf_ptr; /* Descriptor buffer pointer */
191 u16 byte_cnt; /* buffer byte count */
192 u16 l4i_chk; /* CPU provided TCP checksum */
193 u32 cmd_sts; /* Command/status field */
194 u32 next_desc_ptr; /* Pointer to next descriptor */
195 u32 buf_ptr; /* pointer to buffer for this descriptor*/
197 #elif defined(__LITTLE_ENDIAN)
199 u32 cmd_sts; /* Descriptor command status */
200 u16 buf_size; /* Buffer size */
201 u16 byte_cnt; /* Descriptor buffer byte count */
202 u32 buf_ptr; /* Descriptor buffer pointer */
203 u32 next_desc_ptr; /* Next descriptor pointer */
207 u32 cmd_sts; /* Command/status field */
208 u16 l4i_chk; /* CPU provided TCP checksum */
209 u16 byte_cnt; /* buffer byte count */
210 u32 buf_ptr; /* pointer to buffer for this descriptor*/
211 u32 next_desc_ptr; /* Pointer to next descriptor */
214 #error One of __BIG_ENDIAN or __LITTLE_ENDIAN must be defined
217 /* RX & TX descriptor command */
218 #define BUFFER_OWNED_BY_DMA 0x80000000
220 /* RX & TX descriptor status */
221 #define ERROR_SUMMARY 0x00000001
223 /* RX descriptor status */
224 #define LAYER_4_CHECKSUM_OK 0x40000000
225 #define RX_ENABLE_INTERRUPT 0x20000000
226 #define RX_FIRST_DESC 0x08000000
227 #define RX_LAST_DESC 0x04000000
229 /* TX descriptor command */
230 #define TX_ENABLE_INTERRUPT 0x00800000
231 #define GEN_CRC 0x00400000
232 #define TX_FIRST_DESC 0x00200000
233 #define TX_LAST_DESC 0x00100000
234 #define ZERO_PADDING 0x00080000
235 #define GEN_IP_V4_CHECKSUM 0x00040000
236 #define GEN_TCP_UDP_CHECKSUM 0x00020000
237 #define UDP_FRAME 0x00010000
239 #define TX_IHL_SHIFT 11
242 /* global *******************************************************************/
243 struct mv643xx_eth_shared_private {
245 * Ethernet controller base address.
250 * Protects access to SMI_REG, which is shared between ports.
255 * Per-port MBUS window access register value.
260 * Hardware-specific parameters.
263 int extended_rx_coal_limit;
264 int tx_bw_control_moved;
268 /* per-port *****************************************************************/
269 struct mib_counters {
270 u64 good_octets_received;
271 u32 bad_octets_received;
272 u32 internal_mac_transmit_err;
273 u32 good_frames_received;
274 u32 bad_frames_received;
275 u32 broadcast_frames_received;
276 u32 multicast_frames_received;
277 u32 frames_64_octets;
278 u32 frames_65_to_127_octets;
279 u32 frames_128_to_255_octets;
280 u32 frames_256_to_511_octets;
281 u32 frames_512_to_1023_octets;
282 u32 frames_1024_to_max_octets;
283 u64 good_octets_sent;
284 u32 good_frames_sent;
285 u32 excessive_collision;
286 u32 multicast_frames_sent;
287 u32 broadcast_frames_sent;
288 u32 unrec_mac_control_received;
290 u32 good_fc_received;
292 u32 undersize_received;
293 u32 fragments_received;
294 u32 oversize_received;
296 u32 mac_receive_error;
311 struct rx_desc *rx_desc_area;
312 dma_addr_t rx_desc_dma;
313 int rx_desc_area_size;
314 struct sk_buff **rx_skb;
316 struct timer_list rx_oom;
328 struct tx_desc *tx_desc_area;
329 dma_addr_t tx_desc_dma;
330 int tx_desc_area_size;
331 struct sk_buff **tx_skb;
334 struct mv643xx_eth_private {
335 struct mv643xx_eth_shared_private *shared;
338 struct net_device *dev;
340 struct mv643xx_eth_shared_private *shared_smi;
345 struct mib_counters mib_counters;
346 struct work_struct tx_timeout_task;
347 struct mii_if_info mii;
352 int default_rx_ring_size;
353 unsigned long rx_desc_sram_addr;
354 int rx_desc_sram_size;
357 struct napi_struct napi;
358 struct rx_queue rxq[8];
363 int default_tx_ring_size;
364 unsigned long tx_desc_sram_addr;
365 int tx_desc_sram_size;
368 struct tx_queue txq[8];
369 #ifdef MV643XX_ETH_TX_FAST_REFILL
370 int tx_clean_threshold;
375 /* port register accessors **************************************************/
376 static inline u32 rdl(struct mv643xx_eth_private *mp, int offset)
378 return readl(mp->shared->base + offset);
381 static inline void wrl(struct mv643xx_eth_private *mp, int offset, u32 data)
383 writel(data, mp->shared->base + offset);
387 /* rxq/txq helper functions *************************************************/
388 static struct mv643xx_eth_private *rxq_to_mp(struct rx_queue *rxq)
390 return container_of(rxq, struct mv643xx_eth_private, rxq[rxq->index]);
393 static struct mv643xx_eth_private *txq_to_mp(struct tx_queue *txq)
395 return container_of(txq, struct mv643xx_eth_private, txq[txq->index]);
398 static void rxq_enable(struct rx_queue *rxq)
400 struct mv643xx_eth_private *mp = rxq_to_mp(rxq);
401 wrl(mp, RXQ_COMMAND(mp->port_num), 1 << rxq->index);
404 static void rxq_disable(struct rx_queue *rxq)
406 struct mv643xx_eth_private *mp = rxq_to_mp(rxq);
407 u8 mask = 1 << rxq->index;
409 wrl(mp, RXQ_COMMAND(mp->port_num), mask << 8);
410 while (rdl(mp, RXQ_COMMAND(mp->port_num)) & mask)
414 static void txq_reset_hw_ptr(struct tx_queue *txq)
416 struct mv643xx_eth_private *mp = txq_to_mp(txq);
417 int off = TXQ_CURRENT_DESC_PTR(mp->port_num, txq->index);
420 addr = (u32)txq->tx_desc_dma;
421 addr += txq->tx_curr_desc * sizeof(struct tx_desc);
425 static void txq_enable(struct tx_queue *txq)
427 struct mv643xx_eth_private *mp = txq_to_mp(txq);
428 wrl(mp, TXQ_COMMAND(mp->port_num), 1 << txq->index);
431 static void txq_disable(struct tx_queue *txq)
433 struct mv643xx_eth_private *mp = txq_to_mp(txq);
434 u8 mask = 1 << txq->index;
436 wrl(mp, TXQ_COMMAND(mp->port_num), mask << 8);
437 while (rdl(mp, TXQ_COMMAND(mp->port_num)) & mask)
441 static void __txq_maybe_wake(struct tx_queue *txq)
443 struct mv643xx_eth_private *mp = txq_to_mp(txq);
446 * netif_{stop,wake}_queue() flow control only applies to
449 BUG_ON(txq->index != mp->txq_primary);
451 if (txq->tx_ring_size - txq->tx_desc_count >= MAX_DESCS_PER_SKB)
452 netif_wake_queue(mp->dev);
456 /* rx ***********************************************************************/
457 static void txq_reclaim(struct tx_queue *txq, int force);
459 static void rxq_refill(struct rx_queue *rxq)
461 struct mv643xx_eth_private *mp = rxq_to_mp(rxq);
464 spin_lock_irqsave(&mp->lock, flags);
466 while (rxq->rx_desc_count < rxq->rx_ring_size) {
473 * Reserve 2+14 bytes for an ethernet header (the
474 * hardware automatically prepends 2 bytes of dummy
475 * data to each received packet), 4 bytes for a VLAN
476 * header, and 4 bytes for the trailing FCS -- 24
479 skb_size = mp->dev->mtu + 24;
481 skb = dev_alloc_skb(skb_size + dma_get_cache_alignment() - 1);
485 unaligned = (u32)skb->data & (dma_get_cache_alignment() - 1);
487 skb_reserve(skb, dma_get_cache_alignment() - unaligned);
489 rxq->rx_desc_count++;
490 rx = rxq->rx_used_desc;
491 rxq->rx_used_desc = (rx + 1) % rxq->rx_ring_size;
493 rxq->rx_desc_area[rx].buf_ptr = dma_map_single(NULL, skb->data,
494 skb_size, DMA_FROM_DEVICE);
495 rxq->rx_desc_area[rx].buf_size = skb_size;
496 rxq->rx_skb[rx] = skb;
498 rxq->rx_desc_area[rx].cmd_sts = BUFFER_OWNED_BY_DMA |
503 * The hardware automatically prepends 2 bytes of
504 * dummy data to each received packet, so that the
505 * IP header ends up 16-byte aligned.
510 if (rxq->rx_desc_count != rxq->rx_ring_size) {
511 rxq->rx_oom.expires = jiffies + (HZ / 10);
512 add_timer(&rxq->rx_oom);
515 spin_unlock_irqrestore(&mp->lock, flags);
518 static inline void rxq_refill_timer_wrapper(unsigned long data)
520 rxq_refill((struct rx_queue *)data);
523 static int rxq_process(struct rx_queue *rxq, int budget)
525 struct mv643xx_eth_private *mp = rxq_to_mp(rxq);
526 struct net_device_stats *stats = &mp->dev->stats;
530 while (rx < budget) {
531 struct rx_desc *rx_desc;
532 unsigned int cmd_sts;
536 spin_lock_irqsave(&mp->lock, flags);
538 rx_desc = &rxq->rx_desc_area[rxq->rx_curr_desc];
540 cmd_sts = rx_desc->cmd_sts;
541 if (cmd_sts & BUFFER_OWNED_BY_DMA) {
542 spin_unlock_irqrestore(&mp->lock, flags);
547 skb = rxq->rx_skb[rxq->rx_curr_desc];
548 rxq->rx_skb[rxq->rx_curr_desc] = NULL;
550 rxq->rx_curr_desc = (rxq->rx_curr_desc + 1) % rxq->rx_ring_size;
552 spin_unlock_irqrestore(&mp->lock, flags);
554 dma_unmap_single(NULL, rx_desc->buf_ptr + 2,
555 mp->dev->mtu + 24, DMA_FROM_DEVICE);
556 rxq->rx_desc_count--;
562 * Note that the descriptor byte count includes 2 dummy
563 * bytes automatically inserted by the hardware at the
564 * start of the packet (which we don't count), and a 4
565 * byte CRC at the end of the packet (which we do count).
568 stats->rx_bytes += rx_desc->byte_cnt - 2;
571 * In case we received a packet without first / last bits
572 * on, or the error summary bit is set, the packet needs
575 if (((cmd_sts & (RX_FIRST_DESC | RX_LAST_DESC)) !=
576 (RX_FIRST_DESC | RX_LAST_DESC))
577 || (cmd_sts & ERROR_SUMMARY)) {
580 if ((cmd_sts & (RX_FIRST_DESC | RX_LAST_DESC)) !=
581 (RX_FIRST_DESC | RX_LAST_DESC)) {
583 dev_printk(KERN_ERR, &mp->dev->dev,
584 "received packet spanning "
585 "multiple descriptors\n");
588 if (cmd_sts & ERROR_SUMMARY)
591 dev_kfree_skb_irq(skb);
594 * The -4 is for the CRC in the trailer of the
597 skb_put(skb, rx_desc->byte_cnt - 2 - 4);
599 if (cmd_sts & LAYER_4_CHECKSUM_OK) {
600 skb->ip_summed = CHECKSUM_UNNECESSARY;
602 (cmd_sts & 0x0007fff8) >> 3);
604 skb->protocol = eth_type_trans(skb, mp->dev);
605 #ifdef MV643XX_ETH_NAPI
606 netif_receive_skb(skb);
612 mp->dev->last_rx = jiffies;
620 #ifdef MV643XX_ETH_NAPI
621 static int mv643xx_eth_poll(struct napi_struct *napi, int budget)
623 struct mv643xx_eth_private *mp;
627 mp = container_of(napi, struct mv643xx_eth_private, napi);
629 #ifdef MV643XX_ETH_TX_FAST_REFILL
630 if (++mp->tx_clean_threshold > 5) {
631 mp->tx_clean_threshold = 0;
632 for (i = 0; i < 8; i++)
633 if (mp->txq_mask & (1 << i))
634 txq_reclaim(mp->txq + i, 0);
636 if (netif_carrier_ok(mp->dev)) {
637 spin_lock(&mp->lock);
638 __txq_maybe_wake(mp->txq + mp->txq_primary);
639 spin_unlock(&mp->lock);
645 for (i = 7; rx < budget && i >= 0; i--)
646 if (mp->rxq_mask & (1 << i))
647 rx += rxq_process(mp->rxq + i, budget - rx);
650 netif_rx_complete(mp->dev, napi);
651 wrl(mp, INT_CAUSE(mp->port_num), 0);
652 wrl(mp, INT_CAUSE_EXT(mp->port_num), 0);
653 wrl(mp, INT_MASK(mp->port_num), INT_TX_END | INT_RX | INT_EXT);
661 /* tx ***********************************************************************/
662 static inline unsigned int has_tiny_unaligned_frags(struct sk_buff *skb)
666 for (frag = 0; frag < skb_shinfo(skb)->nr_frags; frag++) {
667 skb_frag_t *fragp = &skb_shinfo(skb)->frags[frag];
668 if (fragp->size <= 8 && fragp->page_offset & 7)
675 static int txq_alloc_desc_index(struct tx_queue *txq)
679 BUG_ON(txq->tx_desc_count >= txq->tx_ring_size);
681 tx_desc_curr = txq->tx_curr_desc;
682 txq->tx_curr_desc = (tx_desc_curr + 1) % txq->tx_ring_size;
684 BUG_ON(txq->tx_curr_desc == txq->tx_used_desc);
689 static void txq_submit_frag_skb(struct tx_queue *txq, struct sk_buff *skb)
691 int nr_frags = skb_shinfo(skb)->nr_frags;
694 for (frag = 0; frag < nr_frags; frag++) {
695 skb_frag_t *this_frag;
697 struct tx_desc *desc;
699 this_frag = &skb_shinfo(skb)->frags[frag];
700 tx_index = txq_alloc_desc_index(txq);
701 desc = &txq->tx_desc_area[tx_index];
704 * The last fragment will generate an interrupt
705 * which will free the skb on TX completion.
707 if (frag == nr_frags - 1) {
708 desc->cmd_sts = BUFFER_OWNED_BY_DMA |
709 ZERO_PADDING | TX_LAST_DESC |
711 txq->tx_skb[tx_index] = skb;
713 desc->cmd_sts = BUFFER_OWNED_BY_DMA;
714 txq->tx_skb[tx_index] = NULL;
718 desc->byte_cnt = this_frag->size;
719 desc->buf_ptr = dma_map_page(NULL, this_frag->page,
720 this_frag->page_offset,
726 static inline __be16 sum16_as_be(__sum16 sum)
728 return (__force __be16)sum;
731 static void txq_submit_skb(struct tx_queue *txq, struct sk_buff *skb)
733 struct mv643xx_eth_private *mp = txq_to_mp(txq);
734 int nr_frags = skb_shinfo(skb)->nr_frags;
736 struct tx_desc *desc;
740 cmd_sts = TX_FIRST_DESC | GEN_CRC | BUFFER_OWNED_BY_DMA;
742 tx_index = txq_alloc_desc_index(txq);
743 desc = &txq->tx_desc_area[tx_index];
746 txq_submit_frag_skb(txq, skb);
748 length = skb_headlen(skb);
749 txq->tx_skb[tx_index] = NULL;
751 cmd_sts |= ZERO_PADDING | TX_LAST_DESC | TX_ENABLE_INTERRUPT;
753 txq->tx_skb[tx_index] = skb;
756 desc->byte_cnt = length;
757 desc->buf_ptr = dma_map_single(NULL, skb->data, length, DMA_TO_DEVICE);
759 if (skb->ip_summed == CHECKSUM_PARTIAL) {
760 BUG_ON(skb->protocol != htons(ETH_P_IP));
762 cmd_sts |= GEN_TCP_UDP_CHECKSUM |
764 ip_hdr(skb)->ihl << TX_IHL_SHIFT;
766 switch (ip_hdr(skb)->protocol) {
768 cmd_sts |= UDP_FRAME;
769 desc->l4i_chk = ntohs(sum16_as_be(udp_hdr(skb)->check));
772 desc->l4i_chk = ntohs(sum16_as_be(tcp_hdr(skb)->check));
778 /* Errata BTS #50, IHL must be 5 if no HW checksum */
779 cmd_sts |= 5 << TX_IHL_SHIFT;
783 /* ensure all other descriptors are written before first cmd_sts */
785 desc->cmd_sts = cmd_sts;
787 /* clear TX_END interrupt status */
788 wrl(mp, INT_CAUSE(mp->port_num), ~(INT_TX_END_0 << txq->index));
789 rdl(mp, INT_CAUSE(mp->port_num));
791 /* ensure all descriptors are written before poking hardware */
795 txq->tx_desc_count += nr_frags + 1;
798 static int mv643xx_eth_xmit(struct sk_buff *skb, struct net_device *dev)
800 struct mv643xx_eth_private *mp = netdev_priv(dev);
801 struct net_device_stats *stats = &dev->stats;
802 struct tx_queue *txq;
805 if (has_tiny_unaligned_frags(skb) && __skb_linearize(skb)) {
807 dev_printk(KERN_DEBUG, &dev->dev,
808 "failed to linearize skb with tiny "
809 "unaligned fragment\n");
810 return NETDEV_TX_BUSY;
813 spin_lock_irqsave(&mp->lock, flags);
815 txq = mp->txq + mp->txq_primary;
817 if (txq->tx_ring_size - txq->tx_desc_count < MAX_DESCS_PER_SKB) {
818 spin_unlock_irqrestore(&mp->lock, flags);
819 if (txq->index == mp->txq_primary && net_ratelimit())
820 dev_printk(KERN_ERR, &dev->dev,
821 "primary tx queue full?!\n");
826 txq_submit_skb(txq, skb);
827 stats->tx_bytes += skb->len;
829 dev->trans_start = jiffies;
831 if (txq->index == mp->txq_primary) {
834 entries_left = txq->tx_ring_size - txq->tx_desc_count;
835 if (entries_left < MAX_DESCS_PER_SKB)
836 netif_stop_queue(dev);
839 spin_unlock_irqrestore(&mp->lock, flags);
845 /* tx rate control **********************************************************/
847 * Set total maximum TX rate (shared by all TX queues for this port)
848 * to 'rate' bits per second, with a maximum burst of 'burst' bytes.
850 static void tx_set_rate(struct mv643xx_eth_private *mp, int rate, int burst)
856 token_rate = ((rate / 1000) * 64) / (mp->shared->t_clk / 1000);
857 if (token_rate > 1023)
860 mtu = (mp->dev->mtu + 255) >> 8;
864 bucket_size = (burst + 255) >> 8;
865 if (bucket_size > 65535)
868 if (mp->shared->tx_bw_control_moved) {
869 wrl(mp, TX_BW_RATE_MOVED(mp->port_num), token_rate);
870 wrl(mp, TX_BW_MTU_MOVED(mp->port_num), mtu);
871 wrl(mp, TX_BW_BURST_MOVED(mp->port_num), bucket_size);
873 wrl(mp, TX_BW_RATE(mp->port_num), token_rate);
874 wrl(mp, TX_BW_MTU(mp->port_num), mtu);
875 wrl(mp, TX_BW_BURST(mp->port_num), bucket_size);
879 static void txq_set_rate(struct tx_queue *txq, int rate, int burst)
881 struct mv643xx_eth_private *mp = txq_to_mp(txq);
885 token_rate = ((rate / 1000) * 64) / (mp->shared->t_clk / 1000);
886 if (token_rate > 1023)
889 bucket_size = (burst + 255) >> 8;
890 if (bucket_size > 65535)
893 wrl(mp, TXQ_BW_TOKENS(mp->port_num, txq->index), token_rate << 14);
894 wrl(mp, TXQ_BW_CONF(mp->port_num, txq->index),
895 (bucket_size << 10) | token_rate);
898 static void txq_set_fixed_prio_mode(struct tx_queue *txq)
900 struct mv643xx_eth_private *mp = txq_to_mp(txq);
905 * Turn on fixed priority mode.
907 if (mp->shared->tx_bw_control_moved)
908 off = TXQ_FIX_PRIO_CONF_MOVED(mp->port_num);
910 off = TXQ_FIX_PRIO_CONF(mp->port_num);
913 val |= 1 << txq->index;
917 static void txq_set_wrr(struct tx_queue *txq, int weight)
919 struct mv643xx_eth_private *mp = txq_to_mp(txq);
924 * Turn off fixed priority mode.
926 if (mp->shared->tx_bw_control_moved)
927 off = TXQ_FIX_PRIO_CONF_MOVED(mp->port_num);
929 off = TXQ_FIX_PRIO_CONF(mp->port_num);
932 val &= ~(1 << txq->index);
936 * Configure WRR weight for this queue.
938 off = TXQ_BW_WRR_CONF(mp->port_num, txq->index);
941 val = (val & ~0xff) | (weight & 0xff);
946 /* mii management interface *************************************************/
947 #define SMI_BUSY 0x10000000
948 #define SMI_READ_VALID 0x08000000
949 #define SMI_OPCODE_READ 0x04000000
950 #define SMI_OPCODE_WRITE 0x00000000
952 static void smi_reg_read(struct mv643xx_eth_private *mp, unsigned int addr,
953 unsigned int reg, unsigned int *value)
955 void __iomem *smi_reg = mp->shared_smi->base + SMI_REG;
959 /* the SMI register is a shared resource */
960 spin_lock_irqsave(&mp->shared_smi->phy_lock, flags);
962 /* wait for the SMI register to become available */
963 for (i = 0; readl(smi_reg) & SMI_BUSY; i++) {
965 printk("%s: PHY busy timeout\n", mp->dev->name);
971 writel(SMI_OPCODE_READ | (reg << 21) | (addr << 16), smi_reg);
973 /* now wait for the data to be valid */
974 for (i = 0; !(readl(smi_reg) & SMI_READ_VALID); i++) {
976 printk("%s: PHY read timeout\n", mp->dev->name);
982 *value = readl(smi_reg) & 0xffff;
984 spin_unlock_irqrestore(&mp->shared_smi->phy_lock, flags);
987 static void smi_reg_write(struct mv643xx_eth_private *mp,
989 unsigned int reg, unsigned int value)
991 void __iomem *smi_reg = mp->shared_smi->base + SMI_REG;
995 /* the SMI register is a shared resource */
996 spin_lock_irqsave(&mp->shared_smi->phy_lock, flags);
998 /* wait for the SMI register to become available */
999 for (i = 0; readl(smi_reg) & SMI_BUSY; i++) {
1001 printk("%s: PHY busy timeout\n", mp->dev->name);
1007 writel(SMI_OPCODE_WRITE | (reg << 21) |
1008 (addr << 16) | (value & 0xffff), smi_reg);
1010 spin_unlock_irqrestore(&mp->shared_smi->phy_lock, flags);
1014 /* mib counters *************************************************************/
1015 static inline u32 mib_read(struct mv643xx_eth_private *mp, int offset)
1017 return rdl(mp, MIB_COUNTERS(mp->port_num) + offset);
1020 static void mib_counters_clear(struct mv643xx_eth_private *mp)
1024 for (i = 0; i < 0x80; i += 4)
1028 static void mib_counters_update(struct mv643xx_eth_private *mp)
1030 struct mib_counters *p = &mp->mib_counters;
1032 p->good_octets_received += mib_read(mp, 0x00);
1033 p->good_octets_received += (u64)mib_read(mp, 0x04) << 32;
1034 p->bad_octets_received += mib_read(mp, 0x08);
1035 p->internal_mac_transmit_err += mib_read(mp, 0x0c);
1036 p->good_frames_received += mib_read(mp, 0x10);
1037 p->bad_frames_received += mib_read(mp, 0x14);
1038 p->broadcast_frames_received += mib_read(mp, 0x18);
1039 p->multicast_frames_received += mib_read(mp, 0x1c);
1040 p->frames_64_octets += mib_read(mp, 0x20);
1041 p->frames_65_to_127_octets += mib_read(mp, 0x24);
1042 p->frames_128_to_255_octets += mib_read(mp, 0x28);
1043 p->frames_256_to_511_octets += mib_read(mp, 0x2c);
1044 p->frames_512_to_1023_octets += mib_read(mp, 0x30);
1045 p->frames_1024_to_max_octets += mib_read(mp, 0x34);
1046 p->good_octets_sent += mib_read(mp, 0x38);
1047 p->good_octets_sent += (u64)mib_read(mp, 0x3c) << 32;
1048 p->good_frames_sent += mib_read(mp, 0x40);
1049 p->excessive_collision += mib_read(mp, 0x44);
1050 p->multicast_frames_sent += mib_read(mp, 0x48);
1051 p->broadcast_frames_sent += mib_read(mp, 0x4c);
1052 p->unrec_mac_control_received += mib_read(mp, 0x50);
1053 p->fc_sent += mib_read(mp, 0x54);
1054 p->good_fc_received += mib_read(mp, 0x58);
1055 p->bad_fc_received += mib_read(mp, 0x5c);
1056 p->undersize_received += mib_read(mp, 0x60);
1057 p->fragments_received += mib_read(mp, 0x64);
1058 p->oversize_received += mib_read(mp, 0x68);
1059 p->jabber_received += mib_read(mp, 0x6c);
1060 p->mac_receive_error += mib_read(mp, 0x70);
1061 p->bad_crc_event += mib_read(mp, 0x74);
1062 p->collision += mib_read(mp, 0x78);
1063 p->late_collision += mib_read(mp, 0x7c);
1067 /* ethtool ******************************************************************/
1068 struct mv643xx_eth_stats {
1069 char stat_string[ETH_GSTRING_LEN];
1076 { #m, FIELD_SIZEOF(struct net_device_stats, m), \
1077 offsetof(struct net_device, stats.m), -1 }
1079 #define MIBSTAT(m) \
1080 { #m, FIELD_SIZEOF(struct mib_counters, m), \
1081 -1, offsetof(struct mv643xx_eth_private, mib_counters.m) }
1083 static const struct mv643xx_eth_stats mv643xx_eth_stats[] = {
1092 MIBSTAT(good_octets_received),
1093 MIBSTAT(bad_octets_received),
1094 MIBSTAT(internal_mac_transmit_err),
1095 MIBSTAT(good_frames_received),
1096 MIBSTAT(bad_frames_received),
1097 MIBSTAT(broadcast_frames_received),
1098 MIBSTAT(multicast_frames_received),
1099 MIBSTAT(frames_64_octets),
1100 MIBSTAT(frames_65_to_127_octets),
1101 MIBSTAT(frames_128_to_255_octets),
1102 MIBSTAT(frames_256_to_511_octets),
1103 MIBSTAT(frames_512_to_1023_octets),
1104 MIBSTAT(frames_1024_to_max_octets),
1105 MIBSTAT(good_octets_sent),
1106 MIBSTAT(good_frames_sent),
1107 MIBSTAT(excessive_collision),
1108 MIBSTAT(multicast_frames_sent),
1109 MIBSTAT(broadcast_frames_sent),
1110 MIBSTAT(unrec_mac_control_received),
1112 MIBSTAT(good_fc_received),
1113 MIBSTAT(bad_fc_received),
1114 MIBSTAT(undersize_received),
1115 MIBSTAT(fragments_received),
1116 MIBSTAT(oversize_received),
1117 MIBSTAT(jabber_received),
1118 MIBSTAT(mac_receive_error),
1119 MIBSTAT(bad_crc_event),
1121 MIBSTAT(late_collision),
1124 static int mv643xx_eth_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1126 struct mv643xx_eth_private *mp = netdev_priv(dev);
1129 spin_lock_irq(&mp->lock);
1130 err = mii_ethtool_gset(&mp->mii, cmd);
1131 spin_unlock_irq(&mp->lock);
1134 * The MAC does not support 1000baseT_Half.
1136 cmd->supported &= ~SUPPORTED_1000baseT_Half;
1137 cmd->advertising &= ~ADVERTISED_1000baseT_Half;
1142 static int mv643xx_eth_get_settings_phyless(struct net_device *dev, struct ethtool_cmd *cmd)
1144 struct mv643xx_eth_private *mp = netdev_priv(dev);
1147 port_status = rdl(mp, PORT_STATUS(mp->port_num));
1149 cmd->supported = SUPPORTED_MII;
1150 cmd->advertising = ADVERTISED_MII;
1151 switch (port_status & PORT_SPEED_MASK) {
1153 cmd->speed = SPEED_10;
1155 case PORT_SPEED_100:
1156 cmd->speed = SPEED_100;
1158 case PORT_SPEED_1000:
1159 cmd->speed = SPEED_1000;
1165 cmd->duplex = (port_status & FULL_DUPLEX) ? DUPLEX_FULL : DUPLEX_HALF;
1166 cmd->port = PORT_MII;
1167 cmd->phy_address = 0;
1168 cmd->transceiver = XCVR_INTERNAL;
1169 cmd->autoneg = AUTONEG_DISABLE;
1176 static int mv643xx_eth_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1178 struct mv643xx_eth_private *mp = netdev_priv(dev);
1182 * The MAC does not support 1000baseT_Half.
1184 cmd->advertising &= ~ADVERTISED_1000baseT_Half;
1186 spin_lock_irq(&mp->lock);
1187 err = mii_ethtool_sset(&mp->mii, cmd);
1188 spin_unlock_irq(&mp->lock);
1193 static int mv643xx_eth_set_settings_phyless(struct net_device *dev, struct ethtool_cmd *cmd)
1198 static void mv643xx_eth_get_drvinfo(struct net_device *dev,
1199 struct ethtool_drvinfo *drvinfo)
1201 strncpy(drvinfo->driver, mv643xx_eth_driver_name, 32);
1202 strncpy(drvinfo->version, mv643xx_eth_driver_version, 32);
1203 strncpy(drvinfo->fw_version, "N/A", 32);
1204 strncpy(drvinfo->bus_info, "platform", 32);
1205 drvinfo->n_stats = ARRAY_SIZE(mv643xx_eth_stats);
1208 static int mv643xx_eth_nway_reset(struct net_device *dev)
1210 struct mv643xx_eth_private *mp = netdev_priv(dev);
1212 return mii_nway_restart(&mp->mii);
1215 static int mv643xx_eth_nway_reset_phyless(struct net_device *dev)
1220 static u32 mv643xx_eth_get_link(struct net_device *dev)
1222 struct mv643xx_eth_private *mp = netdev_priv(dev);
1224 return mii_link_ok(&mp->mii);
1227 static u32 mv643xx_eth_get_link_phyless(struct net_device *dev)
1232 static void mv643xx_eth_get_strings(struct net_device *dev,
1233 uint32_t stringset, uint8_t *data)
1237 if (stringset == ETH_SS_STATS) {
1238 for (i = 0; i < ARRAY_SIZE(mv643xx_eth_stats); i++) {
1239 memcpy(data + i * ETH_GSTRING_LEN,
1240 mv643xx_eth_stats[i].stat_string,
1246 static void mv643xx_eth_get_ethtool_stats(struct net_device *dev,
1247 struct ethtool_stats *stats,
1250 struct mv643xx_eth_private *mp = dev->priv;
1253 mib_counters_update(mp);
1255 for (i = 0; i < ARRAY_SIZE(mv643xx_eth_stats); i++) {
1256 const struct mv643xx_eth_stats *stat;
1259 stat = mv643xx_eth_stats + i;
1261 if (stat->netdev_off >= 0)
1262 p = ((void *)mp->dev) + stat->netdev_off;
1264 p = ((void *)mp) + stat->mp_off;
1266 data[i] = (stat->sizeof_stat == 8) ?
1267 *(uint64_t *)p : *(uint32_t *)p;
1271 static int mv643xx_eth_get_sset_count(struct net_device *dev, int sset)
1273 if (sset == ETH_SS_STATS)
1274 return ARRAY_SIZE(mv643xx_eth_stats);
1279 static const struct ethtool_ops mv643xx_eth_ethtool_ops = {
1280 .get_settings = mv643xx_eth_get_settings,
1281 .set_settings = mv643xx_eth_set_settings,
1282 .get_drvinfo = mv643xx_eth_get_drvinfo,
1283 .nway_reset = mv643xx_eth_nway_reset,
1284 .get_link = mv643xx_eth_get_link,
1285 .set_sg = ethtool_op_set_sg,
1286 .get_strings = mv643xx_eth_get_strings,
1287 .get_ethtool_stats = mv643xx_eth_get_ethtool_stats,
1288 .get_sset_count = mv643xx_eth_get_sset_count,
1291 static const struct ethtool_ops mv643xx_eth_ethtool_ops_phyless = {
1292 .get_settings = mv643xx_eth_get_settings_phyless,
1293 .set_settings = mv643xx_eth_set_settings_phyless,
1294 .get_drvinfo = mv643xx_eth_get_drvinfo,
1295 .nway_reset = mv643xx_eth_nway_reset_phyless,
1296 .get_link = mv643xx_eth_get_link_phyless,
1297 .set_sg = ethtool_op_set_sg,
1298 .get_strings = mv643xx_eth_get_strings,
1299 .get_ethtool_stats = mv643xx_eth_get_ethtool_stats,
1300 .get_sset_count = mv643xx_eth_get_sset_count,
1304 /* address handling *********************************************************/
1305 static void uc_addr_get(struct mv643xx_eth_private *mp, unsigned char *addr)
1310 mac_h = rdl(mp, MAC_ADDR_HIGH(mp->port_num));
1311 mac_l = rdl(mp, MAC_ADDR_LOW(mp->port_num));
1313 addr[0] = (mac_h >> 24) & 0xff;
1314 addr[1] = (mac_h >> 16) & 0xff;
1315 addr[2] = (mac_h >> 8) & 0xff;
1316 addr[3] = mac_h & 0xff;
1317 addr[4] = (mac_l >> 8) & 0xff;
1318 addr[5] = mac_l & 0xff;
1321 static void init_mac_tables(struct mv643xx_eth_private *mp)
1325 for (i = 0; i < 0x100; i += 4) {
1326 wrl(mp, SPECIAL_MCAST_TABLE(mp->port_num) + i, 0);
1327 wrl(mp, OTHER_MCAST_TABLE(mp->port_num) + i, 0);
1330 for (i = 0; i < 0x10; i += 4)
1331 wrl(mp, UNICAST_TABLE(mp->port_num) + i, 0);
1334 static void set_filter_table_entry(struct mv643xx_eth_private *mp,
1335 int table, unsigned char entry)
1337 unsigned int table_reg;
1339 /* Set "accepts frame bit" at specified table entry */
1340 table_reg = rdl(mp, table + (entry & 0xfc));
1341 table_reg |= 0x01 << (8 * (entry & 3));
1342 wrl(mp, table + (entry & 0xfc), table_reg);
1345 static void uc_addr_set(struct mv643xx_eth_private *mp, unsigned char *addr)
1351 mac_l = (addr[4] << 8) | addr[5];
1352 mac_h = (addr[0] << 24) | (addr[1] << 16) | (addr[2] << 8) | addr[3];
1354 wrl(mp, MAC_ADDR_LOW(mp->port_num), mac_l);
1355 wrl(mp, MAC_ADDR_HIGH(mp->port_num), mac_h);
1357 table = UNICAST_TABLE(mp->port_num);
1358 set_filter_table_entry(mp, table, addr[5] & 0x0f);
1361 static int mv643xx_eth_set_mac_address(struct net_device *dev, void *addr)
1363 struct mv643xx_eth_private *mp = netdev_priv(dev);
1365 /* +2 is for the offset of the HW addr type */
1366 memcpy(dev->dev_addr, addr + 2, 6);
1368 init_mac_tables(mp);
1369 uc_addr_set(mp, dev->dev_addr);
1374 static int addr_crc(unsigned char *addr)
1379 for (i = 0; i < 6; i++) {
1382 crc = (crc ^ addr[i]) << 8;
1383 for (j = 7; j >= 0; j--) {
1384 if (crc & (0x100 << j))
1392 static void mv643xx_eth_set_rx_mode(struct net_device *dev)
1394 struct mv643xx_eth_private *mp = netdev_priv(dev);
1396 struct dev_addr_list *addr;
1399 port_config = rdl(mp, PORT_CONFIG(mp->port_num));
1400 if (dev->flags & IFF_PROMISC)
1401 port_config |= UNICAST_PROMISCUOUS_MODE;
1403 port_config &= ~UNICAST_PROMISCUOUS_MODE;
1404 wrl(mp, PORT_CONFIG(mp->port_num), port_config);
1406 if (dev->flags & (IFF_PROMISC | IFF_ALLMULTI)) {
1407 int port_num = mp->port_num;
1408 u32 accept = 0x01010101;
1410 for (i = 0; i < 0x100; i += 4) {
1411 wrl(mp, SPECIAL_MCAST_TABLE(port_num) + i, accept);
1412 wrl(mp, OTHER_MCAST_TABLE(port_num) + i, accept);
1417 for (i = 0; i < 0x100; i += 4) {
1418 wrl(mp, SPECIAL_MCAST_TABLE(mp->port_num) + i, 0);
1419 wrl(mp, OTHER_MCAST_TABLE(mp->port_num) + i, 0);
1422 for (addr = dev->mc_list; addr != NULL; addr = addr->next) {
1423 u8 *a = addr->da_addr;
1426 if (addr->da_addrlen != 6)
1429 if (memcmp(a, "\x01\x00\x5e\x00\x00", 5) == 0) {
1430 table = SPECIAL_MCAST_TABLE(mp->port_num);
1431 set_filter_table_entry(mp, table, a[5]);
1433 int crc = addr_crc(a);
1435 table = OTHER_MCAST_TABLE(mp->port_num);
1436 set_filter_table_entry(mp, table, crc);
1442 /* rx/tx queue initialisation ***********************************************/
1443 static int rxq_init(struct mv643xx_eth_private *mp, int index)
1445 struct rx_queue *rxq = mp->rxq + index;
1446 struct rx_desc *rx_desc;
1452 rxq->rx_ring_size = mp->default_rx_ring_size;
1454 rxq->rx_desc_count = 0;
1455 rxq->rx_curr_desc = 0;
1456 rxq->rx_used_desc = 0;
1458 size = rxq->rx_ring_size * sizeof(struct rx_desc);
1460 if (index == mp->rxq_primary && size <= mp->rx_desc_sram_size) {
1461 rxq->rx_desc_area = ioremap(mp->rx_desc_sram_addr,
1462 mp->rx_desc_sram_size);
1463 rxq->rx_desc_dma = mp->rx_desc_sram_addr;
1465 rxq->rx_desc_area = dma_alloc_coherent(NULL, size,
1470 if (rxq->rx_desc_area == NULL) {
1471 dev_printk(KERN_ERR, &mp->dev->dev,
1472 "can't allocate rx ring (%d bytes)\n", size);
1475 memset(rxq->rx_desc_area, 0, size);
1477 rxq->rx_desc_area_size = size;
1478 rxq->rx_skb = kmalloc(rxq->rx_ring_size * sizeof(*rxq->rx_skb),
1480 if (rxq->rx_skb == NULL) {
1481 dev_printk(KERN_ERR, &mp->dev->dev,
1482 "can't allocate rx skb ring\n");
1486 rx_desc = (struct rx_desc *)rxq->rx_desc_area;
1487 for (i = 0; i < rxq->rx_ring_size; i++) {
1488 int nexti = (i + 1) % rxq->rx_ring_size;
1489 rx_desc[i].next_desc_ptr = rxq->rx_desc_dma +
1490 nexti * sizeof(struct rx_desc);
1493 init_timer(&rxq->rx_oom);
1494 rxq->rx_oom.data = (unsigned long)rxq;
1495 rxq->rx_oom.function = rxq_refill_timer_wrapper;
1501 if (index == mp->rxq_primary && size <= mp->rx_desc_sram_size)
1502 iounmap(rxq->rx_desc_area);
1504 dma_free_coherent(NULL, size,
1512 static void rxq_deinit(struct rx_queue *rxq)
1514 struct mv643xx_eth_private *mp = rxq_to_mp(rxq);
1519 del_timer_sync(&rxq->rx_oom);
1521 for (i = 0; i < rxq->rx_ring_size; i++) {
1522 if (rxq->rx_skb[i]) {
1523 dev_kfree_skb(rxq->rx_skb[i]);
1524 rxq->rx_desc_count--;
1528 if (rxq->rx_desc_count) {
1529 dev_printk(KERN_ERR, &mp->dev->dev,
1530 "error freeing rx ring -- %d skbs stuck\n",
1531 rxq->rx_desc_count);
1534 if (rxq->index == mp->rxq_primary &&
1535 rxq->rx_desc_area_size <= mp->rx_desc_sram_size)
1536 iounmap(rxq->rx_desc_area);
1538 dma_free_coherent(NULL, rxq->rx_desc_area_size,
1539 rxq->rx_desc_area, rxq->rx_desc_dma);
1544 static int txq_init(struct mv643xx_eth_private *mp, int index)
1546 struct tx_queue *txq = mp->txq + index;
1547 struct tx_desc *tx_desc;
1553 txq->tx_ring_size = mp->default_tx_ring_size;
1555 txq->tx_desc_count = 0;
1556 txq->tx_curr_desc = 0;
1557 txq->tx_used_desc = 0;
1559 size = txq->tx_ring_size * sizeof(struct tx_desc);
1561 if (index == mp->txq_primary && size <= mp->tx_desc_sram_size) {
1562 txq->tx_desc_area = ioremap(mp->tx_desc_sram_addr,
1563 mp->tx_desc_sram_size);
1564 txq->tx_desc_dma = mp->tx_desc_sram_addr;
1566 txq->tx_desc_area = dma_alloc_coherent(NULL, size,
1571 if (txq->tx_desc_area == NULL) {
1572 dev_printk(KERN_ERR, &mp->dev->dev,
1573 "can't allocate tx ring (%d bytes)\n", size);
1576 memset(txq->tx_desc_area, 0, size);
1578 txq->tx_desc_area_size = size;
1579 txq->tx_skb = kmalloc(txq->tx_ring_size * sizeof(*txq->tx_skb),
1581 if (txq->tx_skb == NULL) {
1582 dev_printk(KERN_ERR, &mp->dev->dev,
1583 "can't allocate tx skb ring\n");
1587 tx_desc = (struct tx_desc *)txq->tx_desc_area;
1588 for (i = 0; i < txq->tx_ring_size; i++) {
1589 struct tx_desc *txd = tx_desc + i;
1590 int nexti = (i + 1) % txq->tx_ring_size;
1593 txd->next_desc_ptr = txq->tx_desc_dma +
1594 nexti * sizeof(struct tx_desc);
1601 if (index == mp->txq_primary && size <= mp->tx_desc_sram_size)
1602 iounmap(txq->tx_desc_area);
1604 dma_free_coherent(NULL, size,
1612 static void txq_reclaim(struct tx_queue *txq, int force)
1614 struct mv643xx_eth_private *mp = txq_to_mp(txq);
1615 unsigned long flags;
1617 spin_lock_irqsave(&mp->lock, flags);
1618 while (txq->tx_desc_count > 0) {
1620 struct tx_desc *desc;
1622 struct sk_buff *skb;
1626 tx_index = txq->tx_used_desc;
1627 desc = &txq->tx_desc_area[tx_index];
1628 cmd_sts = desc->cmd_sts;
1630 if (cmd_sts & BUFFER_OWNED_BY_DMA) {
1633 desc->cmd_sts = cmd_sts & ~BUFFER_OWNED_BY_DMA;
1636 txq->tx_used_desc = (tx_index + 1) % txq->tx_ring_size;
1637 txq->tx_desc_count--;
1639 addr = desc->buf_ptr;
1640 count = desc->byte_cnt;
1641 skb = txq->tx_skb[tx_index];
1642 txq->tx_skb[tx_index] = NULL;
1644 if (cmd_sts & ERROR_SUMMARY) {
1645 dev_printk(KERN_INFO, &mp->dev->dev, "tx error\n");
1646 mp->dev->stats.tx_errors++;
1650 * Drop mp->lock while we free the skb.
1652 spin_unlock_irqrestore(&mp->lock, flags);
1654 if (cmd_sts & TX_FIRST_DESC)
1655 dma_unmap_single(NULL, addr, count, DMA_TO_DEVICE);
1657 dma_unmap_page(NULL, addr, count, DMA_TO_DEVICE);
1660 dev_kfree_skb_irq(skb);
1662 spin_lock_irqsave(&mp->lock, flags);
1664 spin_unlock_irqrestore(&mp->lock, flags);
1667 static void txq_deinit(struct tx_queue *txq)
1669 struct mv643xx_eth_private *mp = txq_to_mp(txq);
1672 txq_reclaim(txq, 1);
1674 BUG_ON(txq->tx_used_desc != txq->tx_curr_desc);
1676 if (txq->index == mp->txq_primary &&
1677 txq->tx_desc_area_size <= mp->tx_desc_sram_size)
1678 iounmap(txq->tx_desc_area);
1680 dma_free_coherent(NULL, txq->tx_desc_area_size,
1681 txq->tx_desc_area, txq->tx_desc_dma);
1687 /* netdev ops and related ***************************************************/
1688 static void handle_link_event(struct mv643xx_eth_private *mp)
1690 struct net_device *dev = mp->dev;
1696 port_status = rdl(mp, PORT_STATUS(mp->port_num));
1697 if (!(port_status & LINK_UP)) {
1698 if (netif_carrier_ok(dev)) {
1701 printk(KERN_INFO "%s: link down\n", dev->name);
1703 netif_carrier_off(dev);
1704 netif_stop_queue(dev);
1706 for (i = 0; i < 8; i++) {
1707 struct tx_queue *txq = mp->txq + i;
1709 if (mp->txq_mask & (1 << i)) {
1710 txq_reclaim(txq, 1);
1711 txq_reset_hw_ptr(txq);
1718 switch (port_status & PORT_SPEED_MASK) {
1722 case PORT_SPEED_100:
1725 case PORT_SPEED_1000:
1732 duplex = (port_status & FULL_DUPLEX) ? 1 : 0;
1733 fc = (port_status & FLOW_CONTROL_ENABLED) ? 1 : 0;
1735 printk(KERN_INFO "%s: link up, %d Mb/s, %s duplex, "
1736 "flow control %sabled\n", dev->name,
1737 speed, duplex ? "full" : "half",
1740 if (!netif_carrier_ok(dev)) {
1741 netif_carrier_on(dev);
1742 netif_wake_queue(dev);
1746 static irqreturn_t mv643xx_eth_irq(int irq, void *dev_id)
1748 struct net_device *dev = (struct net_device *)dev_id;
1749 struct mv643xx_eth_private *mp = netdev_priv(dev);
1753 int_cause = rdl(mp, INT_CAUSE(mp->port_num)) &
1754 (INT_TX_END | INT_RX | INT_EXT);
1759 if (int_cause & INT_EXT) {
1760 int_cause_ext = rdl(mp, INT_CAUSE_EXT(mp->port_num))
1761 & (INT_EXT_LINK | INT_EXT_PHY | INT_EXT_TX);
1762 wrl(mp, INT_CAUSE_EXT(mp->port_num), ~int_cause_ext);
1765 if (int_cause_ext & (INT_EXT_PHY | INT_EXT_LINK))
1766 handle_link_event(mp);
1769 * RxBuffer or RxError set for any of the 8 queues?
1771 #ifdef MV643XX_ETH_NAPI
1772 if (int_cause & INT_RX) {
1773 wrl(mp, INT_MASK(mp->port_num), 0x00000000);
1774 rdl(mp, INT_MASK(mp->port_num));
1776 netif_rx_schedule(dev, &mp->napi);
1779 if (int_cause & INT_RX) {
1782 for (i = 7; i >= 0; i--)
1783 if (mp->rxq_mask & (1 << i))
1784 rxq_process(mp->rxq + i, INT_MAX);
1789 * TxBuffer or TxError set for any of the 8 queues?
1791 if (int_cause_ext & INT_EXT_TX) {
1794 for (i = 0; i < 8; i++)
1795 if (mp->txq_mask & (1 << i))
1796 txq_reclaim(mp->txq + i, 0);
1799 * Enough space again in the primary TX queue for a
1802 if (netif_carrier_ok(dev)) {
1803 spin_lock(&mp->lock);
1804 __txq_maybe_wake(mp->txq + mp->txq_primary);
1805 spin_unlock(&mp->lock);
1810 * Any TxEnd interrupts?
1812 if (int_cause & INT_TX_END) {
1815 wrl(mp, INT_CAUSE(mp->port_num), ~(int_cause & INT_TX_END));
1817 spin_lock(&mp->lock);
1818 for (i = 0; i < 8; i++) {
1819 struct tx_queue *txq = mp->txq + i;
1823 if ((int_cause & (INT_TX_END_0 << i)) == 0)
1827 rdl(mp, TXQ_CURRENT_DESC_PTR(mp->port_num, i));
1828 expected_ptr = (u32)txq->tx_desc_dma +
1829 txq->tx_curr_desc * sizeof(struct tx_desc);
1831 if (hw_desc_ptr != expected_ptr)
1834 spin_unlock(&mp->lock);
1840 static void phy_reset(struct mv643xx_eth_private *mp)
1844 smi_reg_read(mp, mp->phy_addr, MII_BMCR, &data);
1846 smi_reg_write(mp, mp->phy_addr, MII_BMCR, data);
1850 smi_reg_read(mp, mp->phy_addr, MII_BMCR, &data);
1851 } while (data & BMCR_RESET);
1854 static void port_start(struct mv643xx_eth_private *mp)
1860 * Perform PHY reset, if there is a PHY.
1862 if (mp->phy_addr != -1) {
1863 struct ethtool_cmd cmd;
1865 mv643xx_eth_get_settings(mp->dev, &cmd);
1867 mv643xx_eth_set_settings(mp->dev, &cmd);
1871 * Configure basic link parameters.
1873 pscr = rdl(mp, PORT_SERIAL_CONTROL(mp->port_num));
1875 pscr |= SERIAL_PORT_ENABLE;
1876 wrl(mp, PORT_SERIAL_CONTROL(mp->port_num), pscr);
1878 pscr |= DO_NOT_FORCE_LINK_FAIL;
1879 if (mp->phy_addr == -1)
1880 pscr |= FORCE_LINK_PASS;
1881 wrl(mp, PORT_SERIAL_CONTROL(mp->port_num), pscr);
1883 wrl(mp, SDMA_CONFIG(mp->port_num), PORT_SDMA_CONFIG_DEFAULT_VALUE);
1886 * Configure TX path and queues.
1888 tx_set_rate(mp, 1000000000, 16777216);
1889 for (i = 0; i < 8; i++) {
1890 struct tx_queue *txq = mp->txq + i;
1892 if ((mp->txq_mask & (1 << i)) == 0)
1895 txq_reset_hw_ptr(txq);
1896 txq_set_rate(txq, 1000000000, 16777216);
1897 txq_set_fixed_prio_mode(txq);
1901 * Add configured unicast address to address filter table.
1903 uc_addr_set(mp, mp->dev->dev_addr);
1906 * Receive all unmatched unicast, TCP, UDP, BPDU and broadcast
1907 * frames to RX queue #0.
1909 wrl(mp, PORT_CONFIG(mp->port_num), 0x00000000);
1912 * Treat BPDUs as normal multicasts, and disable partition mode.
1914 wrl(mp, PORT_CONFIG_EXT(mp->port_num), 0x00000000);
1917 * Enable the receive queues.
1919 for (i = 0; i < 8; i++) {
1920 struct rx_queue *rxq = mp->rxq + i;
1921 int off = RXQ_CURRENT_DESC_PTR(mp->port_num, i);
1924 if ((mp->rxq_mask & (1 << i)) == 0)
1927 addr = (u32)rxq->rx_desc_dma;
1928 addr += rxq->rx_curr_desc * sizeof(struct rx_desc);
1935 static void set_rx_coal(struct mv643xx_eth_private *mp, unsigned int delay)
1937 unsigned int coal = ((mp->shared->t_clk / 1000000) * delay) / 64;
1940 val = rdl(mp, SDMA_CONFIG(mp->port_num));
1941 if (mp->shared->extended_rx_coal_limit) {
1945 val |= (coal & 0x8000) << 10;
1946 val |= (coal & 0x7fff) << 7;
1951 val |= (coal & 0x3fff) << 8;
1953 wrl(mp, SDMA_CONFIG(mp->port_num), val);
1956 static void set_tx_coal(struct mv643xx_eth_private *mp, unsigned int delay)
1958 unsigned int coal = ((mp->shared->t_clk / 1000000) * delay) / 64;
1962 wrl(mp, TX_FIFO_URGENT_THRESHOLD(mp->port_num), (coal & 0x3fff) << 4);
1965 static int mv643xx_eth_open(struct net_device *dev)
1967 struct mv643xx_eth_private *mp = netdev_priv(dev);
1971 wrl(mp, INT_CAUSE(mp->port_num), 0);
1972 wrl(mp, INT_CAUSE_EXT(mp->port_num), 0);
1973 rdl(mp, INT_CAUSE_EXT(mp->port_num));
1975 err = request_irq(dev->irq, mv643xx_eth_irq,
1976 IRQF_SHARED | IRQF_SAMPLE_RANDOM,
1979 dev_printk(KERN_ERR, &dev->dev, "can't assign irq\n");
1983 init_mac_tables(mp);
1985 for (i = 0; i < 8; i++) {
1986 if ((mp->rxq_mask & (1 << i)) == 0)
1989 err = rxq_init(mp, i);
1992 if (mp->rxq_mask & (1 << i))
1993 rxq_deinit(mp->rxq + i);
1997 rxq_refill(mp->rxq + i);
2000 for (i = 0; i < 8; i++) {
2001 if ((mp->txq_mask & (1 << i)) == 0)
2004 err = txq_init(mp, i);
2007 if (mp->txq_mask & (1 << i))
2008 txq_deinit(mp->txq + i);
2013 #ifdef MV643XX_ETH_NAPI
2014 napi_enable(&mp->napi);
2017 netif_carrier_off(dev);
2018 netif_stop_queue(dev);
2025 wrl(mp, INT_MASK_EXT(mp->port_num),
2026 INT_EXT_LINK | INT_EXT_PHY | INT_EXT_TX);
2028 wrl(mp, INT_MASK(mp->port_num), INT_TX_END | INT_RX | INT_EXT);
2034 for (i = 0; i < 8; i++)
2035 if (mp->rxq_mask & (1 << i))
2036 rxq_deinit(mp->rxq + i);
2038 free_irq(dev->irq, dev);
2043 static void port_reset(struct mv643xx_eth_private *mp)
2048 for (i = 0; i < 8; i++) {
2049 if (mp->rxq_mask & (1 << i))
2050 rxq_disable(mp->rxq + i);
2051 if (mp->txq_mask & (1 << i))
2052 txq_disable(mp->txq + i);
2056 u32 ps = rdl(mp, PORT_STATUS(mp->port_num));
2058 if ((ps & (TX_IN_PROGRESS | TX_FIFO_EMPTY)) == TX_FIFO_EMPTY)
2063 /* Reset the Enable bit in the Configuration Register */
2064 data = rdl(mp, PORT_SERIAL_CONTROL(mp->port_num));
2065 data &= ~(SERIAL_PORT_ENABLE |
2066 DO_NOT_FORCE_LINK_FAIL |
2068 wrl(mp, PORT_SERIAL_CONTROL(mp->port_num), data);
2071 static int mv643xx_eth_stop(struct net_device *dev)
2073 struct mv643xx_eth_private *mp = netdev_priv(dev);
2076 wrl(mp, INT_MASK(mp->port_num), 0x00000000);
2077 rdl(mp, INT_MASK(mp->port_num));
2079 #ifdef MV643XX_ETH_NAPI
2080 napi_disable(&mp->napi);
2082 netif_carrier_off(dev);
2083 netif_stop_queue(dev);
2085 free_irq(dev->irq, dev);
2088 mib_counters_update(mp);
2090 for (i = 0; i < 8; i++) {
2091 if (mp->rxq_mask & (1 << i))
2092 rxq_deinit(mp->rxq + i);
2093 if (mp->txq_mask & (1 << i))
2094 txq_deinit(mp->txq + i);
2100 static int mv643xx_eth_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
2102 struct mv643xx_eth_private *mp = netdev_priv(dev);
2104 if (mp->phy_addr != -1)
2105 return generic_mii_ioctl(&mp->mii, if_mii(ifr), cmd, NULL);
2110 static int mv643xx_eth_change_mtu(struct net_device *dev, int new_mtu)
2112 struct mv643xx_eth_private *mp = netdev_priv(dev);
2114 if (new_mtu < 64 || new_mtu > 9500)
2118 tx_set_rate(mp, 1000000000, 16777216);
2120 if (!netif_running(dev))
2124 * Stop and then re-open the interface. This will allocate RX
2125 * skbs of the new MTU.
2126 * There is a possible danger that the open will not succeed,
2127 * due to memory being full.
2129 mv643xx_eth_stop(dev);
2130 if (mv643xx_eth_open(dev)) {
2131 dev_printk(KERN_ERR, &dev->dev,
2132 "fatal error on re-opening device after "
2139 static void tx_timeout_task(struct work_struct *ugly)
2141 struct mv643xx_eth_private *mp;
2143 mp = container_of(ugly, struct mv643xx_eth_private, tx_timeout_task);
2144 if (netif_running(mp->dev)) {
2145 netif_stop_queue(mp->dev);
2150 __txq_maybe_wake(mp->txq + mp->txq_primary);
2154 static void mv643xx_eth_tx_timeout(struct net_device *dev)
2156 struct mv643xx_eth_private *mp = netdev_priv(dev);
2158 dev_printk(KERN_INFO, &dev->dev, "tx timeout\n");
2160 schedule_work(&mp->tx_timeout_task);
2163 #ifdef CONFIG_NET_POLL_CONTROLLER
2164 static void mv643xx_eth_netpoll(struct net_device *dev)
2166 struct mv643xx_eth_private *mp = netdev_priv(dev);
2168 wrl(mp, INT_MASK(mp->port_num), 0x00000000);
2169 rdl(mp, INT_MASK(mp->port_num));
2171 mv643xx_eth_irq(dev->irq, dev);
2173 wrl(mp, INT_MASK(mp->port_num), INT_TX_END | INT_RX | INT_EXT);
2177 static int mv643xx_eth_mdio_read(struct net_device *dev, int addr, int reg)
2179 struct mv643xx_eth_private *mp = netdev_priv(dev);
2182 smi_reg_read(mp, addr, reg, &val);
2187 static void mv643xx_eth_mdio_write(struct net_device *dev, int addr, int reg, int val)
2189 struct mv643xx_eth_private *mp = netdev_priv(dev);
2190 smi_reg_write(mp, addr, reg, val);
2194 /* platform glue ************************************************************/
2196 mv643xx_eth_conf_mbus_windows(struct mv643xx_eth_shared_private *msp,
2197 struct mbus_dram_target_info *dram)
2199 void __iomem *base = msp->base;
2204 for (i = 0; i < 6; i++) {
2205 writel(0, base + WINDOW_BASE(i));
2206 writel(0, base + WINDOW_SIZE(i));
2208 writel(0, base + WINDOW_REMAP_HIGH(i));
2214 for (i = 0; i < dram->num_cs; i++) {
2215 struct mbus_dram_window *cs = dram->cs + i;
2217 writel((cs->base & 0xffff0000) |
2218 (cs->mbus_attr << 8) |
2219 dram->mbus_dram_target_id, base + WINDOW_BASE(i));
2220 writel((cs->size - 1) & 0xffff0000, base + WINDOW_SIZE(i));
2222 win_enable &= ~(1 << i);
2223 win_protect |= 3 << (2 * i);
2226 writel(win_enable, base + WINDOW_BAR_ENABLE);
2227 msp->win_protect = win_protect;
2230 static void infer_hw_params(struct mv643xx_eth_shared_private *msp)
2233 * Check whether we have a 14-bit coal limit field in bits
2234 * [21:8], or a 16-bit coal limit in bits [25,21:7] of the
2235 * SDMA config register.
2237 writel(0x02000000, msp->base + SDMA_CONFIG(0));
2238 if (readl(msp->base + SDMA_CONFIG(0)) & 0x02000000)
2239 msp->extended_rx_coal_limit = 1;
2241 msp->extended_rx_coal_limit = 0;
2244 * Check whether the TX rate control registers are in the
2245 * old or the new place.
2247 writel(1, msp->base + TX_BW_MTU_MOVED(0));
2248 if (readl(msp->base + TX_BW_MTU_MOVED(0)) & 1)
2249 msp->tx_bw_control_moved = 1;
2251 msp->tx_bw_control_moved = 0;
2254 static int mv643xx_eth_shared_probe(struct platform_device *pdev)
2256 static int mv643xx_eth_version_printed = 0;
2257 struct mv643xx_eth_shared_platform_data *pd = pdev->dev.platform_data;
2258 struct mv643xx_eth_shared_private *msp;
2259 struct resource *res;
2262 if (!mv643xx_eth_version_printed++)
2263 printk(KERN_NOTICE "MV-643xx 10/100/1000 ethernet "
2264 "driver version %s\n", mv643xx_eth_driver_version);
2267 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2272 msp = kmalloc(sizeof(*msp), GFP_KERNEL);
2275 memset(msp, 0, sizeof(*msp));
2277 msp->base = ioremap(res->start, res->end - res->start + 1);
2278 if (msp->base == NULL)
2281 spin_lock_init(&msp->phy_lock);
2284 * (Re-)program MBUS remapping windows if we are asked to.
2286 if (pd != NULL && pd->dram != NULL)
2287 mv643xx_eth_conf_mbus_windows(msp, pd->dram);
2290 * Detect hardware parameters.
2292 msp->t_clk = (pd != NULL && pd->t_clk != 0) ? pd->t_clk : 133000000;
2293 infer_hw_params(msp);
2295 platform_set_drvdata(pdev, msp);
2305 static int mv643xx_eth_shared_remove(struct platform_device *pdev)
2307 struct mv643xx_eth_shared_private *msp = platform_get_drvdata(pdev);
2315 static struct platform_driver mv643xx_eth_shared_driver = {
2316 .probe = mv643xx_eth_shared_probe,
2317 .remove = mv643xx_eth_shared_remove,
2319 .name = MV643XX_ETH_SHARED_NAME,
2320 .owner = THIS_MODULE,
2324 static void phy_addr_set(struct mv643xx_eth_private *mp, int phy_addr)
2326 int addr_shift = 5 * mp->port_num;
2329 data = rdl(mp, PHY_ADDR);
2330 data &= ~(0x1f << addr_shift);
2331 data |= (phy_addr & 0x1f) << addr_shift;
2332 wrl(mp, PHY_ADDR, data);
2335 static int phy_addr_get(struct mv643xx_eth_private *mp)
2339 data = rdl(mp, PHY_ADDR);
2341 return (data >> (5 * mp->port_num)) & 0x1f;
2344 static void set_params(struct mv643xx_eth_private *mp,
2345 struct mv643xx_eth_platform_data *pd)
2347 struct net_device *dev = mp->dev;
2349 if (is_valid_ether_addr(pd->mac_addr))
2350 memcpy(dev->dev_addr, pd->mac_addr, 6);
2352 uc_addr_get(mp, dev->dev_addr);
2354 if (pd->phy_addr == -1) {
2355 mp->shared_smi = NULL;
2358 mp->shared_smi = mp->shared;
2359 if (pd->shared_smi != NULL)
2360 mp->shared_smi = platform_get_drvdata(pd->shared_smi);
2362 if (pd->force_phy_addr || pd->phy_addr) {
2363 mp->phy_addr = pd->phy_addr & 0x3f;
2364 phy_addr_set(mp, mp->phy_addr);
2366 mp->phy_addr = phy_addr_get(mp);
2370 mp->default_rx_ring_size = DEFAULT_RX_QUEUE_SIZE;
2371 if (pd->rx_queue_size)
2372 mp->default_rx_ring_size = pd->rx_queue_size;
2373 mp->rx_desc_sram_addr = pd->rx_sram_addr;
2374 mp->rx_desc_sram_size = pd->rx_sram_size;
2376 if (pd->rx_queue_mask)
2377 mp->rxq_mask = pd->rx_queue_mask;
2379 mp->rxq_mask = 0x01;
2380 mp->rxq_primary = fls(mp->rxq_mask) - 1;
2382 mp->default_tx_ring_size = DEFAULT_TX_QUEUE_SIZE;
2383 if (pd->tx_queue_size)
2384 mp->default_tx_ring_size = pd->tx_queue_size;
2385 mp->tx_desc_sram_addr = pd->tx_sram_addr;
2386 mp->tx_desc_sram_size = pd->tx_sram_size;
2388 if (pd->tx_queue_mask)
2389 mp->txq_mask = pd->tx_queue_mask;
2391 mp->txq_mask = 0x01;
2392 mp->txq_primary = fls(mp->txq_mask) - 1;
2395 static int phy_detect(struct mv643xx_eth_private *mp)
2400 smi_reg_read(mp, mp->phy_addr, MII_BMCR, &data);
2401 smi_reg_write(mp, mp->phy_addr, MII_BMCR, data ^ BMCR_ANENABLE);
2403 smi_reg_read(mp, mp->phy_addr, MII_BMCR, &data2);
2404 if (((data ^ data2) & BMCR_ANENABLE) == 0)
2407 smi_reg_write(mp, mp->phy_addr, MII_BMCR, data);
2412 static int phy_init(struct mv643xx_eth_private *mp,
2413 struct mv643xx_eth_platform_data *pd)
2415 struct ethtool_cmd cmd;
2418 err = phy_detect(mp);
2420 dev_printk(KERN_INFO, &mp->dev->dev,
2421 "no PHY detected at addr %d\n", mp->phy_addr);
2426 mp->mii.phy_id = mp->phy_addr;
2427 mp->mii.phy_id_mask = 0x3f;
2428 mp->mii.reg_num_mask = 0x1f;
2429 mp->mii.dev = mp->dev;
2430 mp->mii.mdio_read = mv643xx_eth_mdio_read;
2431 mp->mii.mdio_write = mv643xx_eth_mdio_write;
2433 mp->mii.supports_gmii = mii_check_gmii_support(&mp->mii);
2435 memset(&cmd, 0, sizeof(cmd));
2437 cmd.port = PORT_MII;
2438 cmd.transceiver = XCVR_INTERNAL;
2439 cmd.phy_address = mp->phy_addr;
2440 if (pd->speed == 0) {
2441 cmd.autoneg = AUTONEG_ENABLE;
2442 cmd.speed = SPEED_100;
2443 cmd.advertising = ADVERTISED_10baseT_Half |
2444 ADVERTISED_10baseT_Full |
2445 ADVERTISED_100baseT_Half |
2446 ADVERTISED_100baseT_Full;
2447 if (mp->mii.supports_gmii)
2448 cmd.advertising |= ADVERTISED_1000baseT_Full;
2450 cmd.autoneg = AUTONEG_DISABLE;
2451 cmd.speed = pd->speed;
2452 cmd.duplex = pd->duplex;
2455 mv643xx_eth_set_settings(mp->dev, &cmd);
2460 static void init_pscr(struct mv643xx_eth_private *mp, int speed, int duplex)
2464 pscr = rdl(mp, PORT_SERIAL_CONTROL(mp->port_num));
2465 if (pscr & SERIAL_PORT_ENABLE) {
2466 pscr &= ~SERIAL_PORT_ENABLE;
2467 wrl(mp, PORT_SERIAL_CONTROL(mp->port_num), pscr);
2470 pscr = MAX_RX_PACKET_9700BYTE | SERIAL_PORT_CONTROL_RESERVED;
2471 if (mp->phy_addr == -1) {
2472 pscr |= DISABLE_AUTO_NEG_SPEED_GMII;
2473 if (speed == SPEED_1000)
2474 pscr |= SET_GMII_SPEED_TO_1000;
2475 else if (speed == SPEED_100)
2476 pscr |= SET_MII_SPEED_TO_100;
2478 pscr |= DISABLE_AUTO_NEG_FOR_FLOW_CTRL;
2480 pscr |= DISABLE_AUTO_NEG_FOR_DUPLEX;
2481 if (duplex == DUPLEX_FULL)
2482 pscr |= SET_FULL_DUPLEX_MODE;
2485 wrl(mp, PORT_SERIAL_CONTROL(mp->port_num), pscr);
2488 static int mv643xx_eth_probe(struct platform_device *pdev)
2490 struct mv643xx_eth_platform_data *pd;
2491 struct mv643xx_eth_private *mp;
2492 struct net_device *dev;
2493 struct resource *res;
2494 DECLARE_MAC_BUF(mac);
2497 pd = pdev->dev.platform_data;
2499 dev_printk(KERN_ERR, &pdev->dev,
2500 "no mv643xx_eth_platform_data\n");
2504 if (pd->shared == NULL) {
2505 dev_printk(KERN_ERR, &pdev->dev,
2506 "no mv643xx_eth_platform_data->shared\n");
2510 dev = alloc_etherdev(sizeof(struct mv643xx_eth_private));
2514 mp = netdev_priv(dev);
2515 platform_set_drvdata(pdev, mp);
2517 mp->shared = platform_get_drvdata(pd->shared);
2518 mp->port_num = pd->port_number;
2521 #ifdef MV643XX_ETH_NAPI
2522 netif_napi_add(dev, &mp->napi, mv643xx_eth_poll, 64);
2527 spin_lock_init(&mp->lock);
2529 mib_counters_clear(mp);
2530 INIT_WORK(&mp->tx_timeout_task, tx_timeout_task);
2532 if (mp->phy_addr != -1) {
2533 err = phy_init(mp, pd);
2537 SET_ETHTOOL_OPS(dev, &mv643xx_eth_ethtool_ops);
2539 SET_ETHTOOL_OPS(dev, &mv643xx_eth_ethtool_ops_phyless);
2541 init_pscr(mp, pd->speed, pd->duplex);
2544 res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
2546 dev->irq = res->start;
2548 dev->hard_start_xmit = mv643xx_eth_xmit;
2549 dev->open = mv643xx_eth_open;
2550 dev->stop = mv643xx_eth_stop;
2551 dev->set_multicast_list = mv643xx_eth_set_rx_mode;
2552 dev->set_mac_address = mv643xx_eth_set_mac_address;
2553 dev->do_ioctl = mv643xx_eth_ioctl;
2554 dev->change_mtu = mv643xx_eth_change_mtu;
2555 dev->tx_timeout = mv643xx_eth_tx_timeout;
2556 #ifdef CONFIG_NET_POLL_CONTROLLER
2557 dev->poll_controller = mv643xx_eth_netpoll;
2559 dev->watchdog_timeo = 2 * HZ;
2562 #ifdef MV643XX_ETH_CHECKSUM_OFFLOAD_TX
2564 * Zero copy can only work if we use Discovery II memory. Else, we will
2565 * have to map the buffers to ISA memory which is only 16 MB
2567 dev->features = NETIF_F_SG | NETIF_F_IP_CSUM;
2570 SET_NETDEV_DEV(dev, &pdev->dev);
2572 if (mp->shared->win_protect)
2573 wrl(mp, WINDOW_PROTECT(mp->port_num), mp->shared->win_protect);
2575 err = register_netdev(dev);
2579 dev_printk(KERN_NOTICE, &dev->dev, "port %d with MAC address %s\n",
2580 mp->port_num, print_mac(mac, dev->dev_addr));
2582 if (dev->features & NETIF_F_SG)
2583 dev_printk(KERN_NOTICE, &dev->dev, "scatter/gather enabled\n");
2585 if (dev->features & NETIF_F_IP_CSUM)
2586 dev_printk(KERN_NOTICE, &dev->dev, "tx checksum offload\n");
2588 #ifdef MV643XX_ETH_NAPI
2589 dev_printk(KERN_NOTICE, &dev->dev, "napi enabled\n");
2592 if (mp->tx_desc_sram_size > 0)
2593 dev_printk(KERN_NOTICE, &dev->dev, "configured with sram\n");
2603 static int mv643xx_eth_remove(struct platform_device *pdev)
2605 struct mv643xx_eth_private *mp = platform_get_drvdata(pdev);
2607 unregister_netdev(mp->dev);
2608 flush_scheduled_work();
2609 free_netdev(mp->dev);
2611 platform_set_drvdata(pdev, NULL);
2616 static void mv643xx_eth_shutdown(struct platform_device *pdev)
2618 struct mv643xx_eth_private *mp = platform_get_drvdata(pdev);
2620 /* Mask all interrupts on ethernet port */
2621 wrl(mp, INT_MASK(mp->port_num), 0);
2622 rdl(mp, INT_MASK(mp->port_num));
2624 if (netif_running(mp->dev))
2628 static struct platform_driver mv643xx_eth_driver = {
2629 .probe = mv643xx_eth_probe,
2630 .remove = mv643xx_eth_remove,
2631 .shutdown = mv643xx_eth_shutdown,
2633 .name = MV643XX_ETH_NAME,
2634 .owner = THIS_MODULE,
2638 static int __init mv643xx_eth_init_module(void)
2642 rc = platform_driver_register(&mv643xx_eth_shared_driver);
2644 rc = platform_driver_register(&mv643xx_eth_driver);
2646 platform_driver_unregister(&mv643xx_eth_shared_driver);
2651 module_init(mv643xx_eth_init_module);
2653 static void __exit mv643xx_eth_cleanup_module(void)
2655 platform_driver_unregister(&mv643xx_eth_driver);
2656 platform_driver_unregister(&mv643xx_eth_shared_driver);
2658 module_exit(mv643xx_eth_cleanup_module);
2660 MODULE_AUTHOR("Rabeeh Khoury, Assaf Hoffman, Matthew Dharm, "
2661 "Manish Lachwani, Dale Farnsworth and Lennert Buytenhek");
2662 MODULE_DESCRIPTION("Ethernet driver for Marvell MV643XX");
2663 MODULE_LICENSE("GPL");
2664 MODULE_ALIAS("platform:" MV643XX_ETH_SHARED_NAME);
2665 MODULE_ALIAS("platform:" MV643XX_ETH_NAME);