2 * Driver for Marvell Discovery (MV643XX) and Marvell Orion ethernet ports
3 * Copyright (C) 2002 Matthew Dharm <mdharm@momenco.com>
5 * Based on the 64360 driver from:
6 * Copyright (C) 2002 Rabeeh Khoury <rabeeh@galileo.co.il>
7 * Rabeeh Khoury <rabeeh@marvell.com>
9 * Copyright (C) 2003 PMC-Sierra, Inc.,
10 * written by Manish Lachwani
12 * Copyright (C) 2003 Ralf Baechle <ralf@linux-mips.org>
14 * Copyright (C) 2004-2006 MontaVista Software, Inc.
15 * Dale Farnsworth <dale@farnsworth.org>
17 * Copyright (C) 2004 Steven J. Hill <sjhill1@rockwellcollins.com>
18 * <sjhill@realitydiluted.com>
20 * Copyright (C) 2007-2008 Marvell Semiconductor
21 * Lennert Buytenhek <buytenh@marvell.com>
23 * This program is free software; you can redistribute it and/or
24 * modify it under the terms of the GNU General Public License
25 * as published by the Free Software Foundation; either version 2
26 * of the License, or (at your option) any later version.
28 * This program is distributed in the hope that it will be useful,
29 * but WITHOUT ANY WARRANTY; without even the implied warranty of
30 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
31 * GNU General Public License for more details.
33 * You should have received a copy of the GNU General Public License
34 * along with this program; if not, write to the Free Software
35 * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
38 #include <linux/init.h>
39 #include <linux/dma-mapping.h>
41 #include <linux/tcp.h>
42 #include <linux/udp.h>
43 #include <linux/etherdevice.h>
44 #include <linux/delay.h>
45 #include <linux/ethtool.h>
46 #include <linux/platform_device.h>
47 #include <linux/module.h>
48 #include <linux/kernel.h>
49 #include <linux/spinlock.h>
50 #include <linux/workqueue.h>
51 #include <linux/mii.h>
52 #include <linux/mv643xx_eth.h>
54 #include <asm/types.h>
55 #include <asm/system.h>
57 static char mv643xx_driver_name[] = "mv643xx_eth";
58 static char mv643xx_driver_version[] = "1.0";
60 #define MV643XX_CHECKSUM_OFFLOAD_TX
62 #define MV643XX_TX_FAST_REFILL
65 #define MV643XX_TX_COAL 100
67 #define MV643XX_RX_COAL 100
70 #ifdef MV643XX_CHECKSUM_OFFLOAD_TX
71 #define MAX_DESCS_PER_SKB (MAX_SKB_FRAGS + 1)
73 #define MAX_DESCS_PER_SKB 1
76 #define ETH_VLAN_HLEN 4
78 #define ETH_HW_IP_ALIGN 2 /* hw aligns IP header */
79 #define ETH_WRAPPER_LEN (ETH_HW_IP_ALIGN + ETH_HLEN + \
80 ETH_VLAN_HLEN + ETH_FCS_LEN)
81 #define ETH_RX_SKB_SIZE (dev->mtu + ETH_WRAPPER_LEN + \
82 dma_get_cache_alignment())
85 * Registers shared between all ports.
87 #define PHY_ADDR 0x0000
88 #define SMI_REG 0x0004
89 #define WINDOW_BASE(w) (0x0200 + ((w) << 3))
90 #define WINDOW_SIZE(w) (0x0204 + ((w) << 3))
91 #define WINDOW_REMAP_HIGH(w) (0x0280 + ((w) << 2))
92 #define WINDOW_BAR_ENABLE 0x0290
93 #define WINDOW_PROTECT(w) (0x0294 + ((w) << 4))
98 #define PORT_CONFIG(p) (0x0400 + ((p) << 10))
99 #define UNICAST_PROMISCUOUS_MODE 0x00000001
100 #define PORT_CONFIG_EXT(p) (0x0404 + ((p) << 10))
101 #define MAC_ADDR_LOW(p) (0x0414 + ((p) << 10))
102 #define MAC_ADDR_HIGH(p) (0x0418 + ((p) << 10))
103 #define SDMA_CONFIG(p) (0x041c + ((p) << 10))
104 #define PORT_SERIAL_CONTROL(p) (0x043c + ((p) << 10))
105 #define PORT_STATUS(p) (0x0444 + ((p) << 10))
106 #define TXQ_COMMAND(p) (0x0448 + ((p) << 10))
107 #define TX_BW_MTU(p) (0x0458 + ((p) << 10))
108 #define INT_CAUSE(p) (0x0460 + ((p) << 10))
109 #define INT_RX 0x00000804
110 #define INT_EXT 0x00000002
111 #define INT_CAUSE_EXT(p) (0x0464 + ((p) << 10))
112 #define INT_EXT_LINK 0x00100000
113 #define INT_EXT_PHY 0x00010000
114 #define INT_EXT_TX_ERROR_0 0x00000100
115 #define INT_EXT_TX_0 0x00000001
116 #define INT_EXT_TX 0x00000101
117 #define INT_MASK(p) (0x0468 + ((p) << 10))
118 #define INT_MASK_EXT(p) (0x046c + ((p) << 10))
119 #define TX_FIFO_URGENT_THRESHOLD(p) (0x0474 + ((p) << 10))
120 #define RXQ_CURRENT_DESC_PTR(p) (0x060c + ((p) << 10))
121 #define RXQ_COMMAND(p) (0x0680 + ((p) << 10))
122 #define TXQ_CURRENT_DESC_PTR(p) (0x06c0 + ((p) << 10))
123 #define MIB_COUNTERS(p) (0x1000 + ((p) << 7))
124 #define SPECIAL_MCAST_TABLE(p) (0x1400 + ((p) << 10))
125 #define OTHER_MCAST_TABLE(p) (0x1500 + ((p) << 10))
126 #define UNICAST_TABLE(p) (0x1600 + ((p) << 10))
130 * SDMA configuration register.
132 #define RX_BURST_SIZE_4_64BIT (2 << 1)
133 #define BLM_RX_NO_SWAP (1 << 4)
134 #define BLM_TX_NO_SWAP (1 << 5)
135 #define TX_BURST_SIZE_4_64BIT (2 << 22)
137 #if defined(__BIG_ENDIAN)
138 #define PORT_SDMA_CONFIG_DEFAULT_VALUE \
139 RX_BURST_SIZE_4_64BIT | \
140 TX_BURST_SIZE_4_64BIT
141 #elif defined(__LITTLE_ENDIAN)
142 #define PORT_SDMA_CONFIG_DEFAULT_VALUE \
143 RX_BURST_SIZE_4_64BIT | \
146 TX_BURST_SIZE_4_64BIT
148 #error One of __BIG_ENDIAN or __LITTLE_ENDIAN must be defined
153 * Port serial control register.
155 #define SET_MII_SPEED_TO_100 (1 << 24)
156 #define SET_GMII_SPEED_TO_1000 (1 << 23)
157 #define SET_FULL_DUPLEX_MODE (1 << 21)
158 #define MAX_RX_PACKET_1522BYTE (1 << 17)
159 #define MAX_RX_PACKET_9700BYTE (5 << 17)
160 #define MAX_RX_PACKET_MASK (7 << 17)
161 #define DISABLE_AUTO_NEG_SPEED_GMII (1 << 13)
162 #define DO_NOT_FORCE_LINK_FAIL (1 << 10)
163 #define SERIAL_PORT_CONTROL_RESERVED (1 << 9)
164 #define DISABLE_AUTO_NEG_FOR_FLOW_CTRL (1 << 3)
165 #define DISABLE_AUTO_NEG_FOR_DUPLEX (1 << 2)
166 #define FORCE_LINK_PASS (1 << 1)
167 #define SERIAL_PORT_ENABLE (1 << 0)
169 #define PORT_DEFAULT_TRANSMIT_QUEUE_SIZE 800
170 #define PORT_DEFAULT_RECEIVE_QUEUE_SIZE 400
172 /* Gigabit Ethernet Unit Global Registers */
174 /* MIB Counters register definitions */
175 #define ETH_MIB_GOOD_OCTETS_RECEIVED_LOW 0x0
176 #define ETH_MIB_GOOD_OCTETS_RECEIVED_HIGH 0x4
177 #define ETH_MIB_BAD_OCTETS_RECEIVED 0x8
178 #define ETH_MIB_INTERNAL_MAC_TRANSMIT_ERR 0xc
179 #define ETH_MIB_GOOD_FRAMES_RECEIVED 0x10
180 #define ETH_MIB_BAD_FRAMES_RECEIVED 0x14
181 #define ETH_MIB_BROADCAST_FRAMES_RECEIVED 0x18
182 #define ETH_MIB_MULTICAST_FRAMES_RECEIVED 0x1c
183 #define ETH_MIB_FRAMES_64_OCTETS 0x20
184 #define ETH_MIB_FRAMES_65_TO_127_OCTETS 0x24
185 #define ETH_MIB_FRAMES_128_TO_255_OCTETS 0x28
186 #define ETH_MIB_FRAMES_256_TO_511_OCTETS 0x2c
187 #define ETH_MIB_FRAMES_512_TO_1023_OCTETS 0x30
188 #define ETH_MIB_FRAMES_1024_TO_MAX_OCTETS 0x34
189 #define ETH_MIB_GOOD_OCTETS_SENT_LOW 0x38
190 #define ETH_MIB_GOOD_OCTETS_SENT_HIGH 0x3c
191 #define ETH_MIB_GOOD_FRAMES_SENT 0x40
192 #define ETH_MIB_EXCESSIVE_COLLISION 0x44
193 #define ETH_MIB_MULTICAST_FRAMES_SENT 0x48
194 #define ETH_MIB_BROADCAST_FRAMES_SENT 0x4c
195 #define ETH_MIB_UNREC_MAC_CONTROL_RECEIVED 0x50
196 #define ETH_MIB_FC_SENT 0x54
197 #define ETH_MIB_GOOD_FC_RECEIVED 0x58
198 #define ETH_MIB_BAD_FC_RECEIVED 0x5c
199 #define ETH_MIB_UNDERSIZE_RECEIVED 0x60
200 #define ETH_MIB_FRAGMENTS_RECEIVED 0x64
201 #define ETH_MIB_OVERSIZE_RECEIVED 0x68
202 #define ETH_MIB_JABBER_RECEIVED 0x6c
203 #define ETH_MIB_MAC_RECEIVE_ERROR 0x70
204 #define ETH_MIB_BAD_CRC_EVENT 0x74
205 #define ETH_MIB_COLLISION 0x78
206 #define ETH_MIB_LATE_COLLISION 0x7c
208 /* Port serial status reg (PSR) */
209 #define ETH_INTERFACE_PCM 0x00000001
210 #define ETH_LINK_IS_UP 0x00000002
211 #define ETH_PORT_AT_FULL_DUPLEX 0x00000004
212 #define ETH_RX_FLOW_CTRL_ENABLED 0x00000008
213 #define ETH_GMII_SPEED_1000 0x00000010
214 #define ETH_MII_SPEED_100 0x00000020
215 #define ETH_TX_IN_PROGRESS 0x00000080
216 #define ETH_BYPASS_ACTIVE 0x00000100
217 #define ETH_PORT_AT_PARTITION_STATE 0x00000200
218 #define ETH_PORT_TX_FIFO_EMPTY 0x00000400
221 #define ETH_SMI_BUSY 0x10000000 /* 0 - Write, 1 - Read */
222 #define ETH_SMI_READ_VALID 0x08000000 /* 0 - Write, 1 - Read */
223 #define ETH_SMI_OPCODE_WRITE 0 /* Completion of Read */
224 #define ETH_SMI_OPCODE_READ 0x04000000 /* Operation is in progress */
226 /* Interrupt Cause Register Bit Definitions */
228 /* SDMA command status fields macros */
230 /* Tx & Rx descriptors status */
231 #define ETH_ERROR_SUMMARY 0x00000001
233 /* Tx & Rx descriptors command */
234 #define ETH_BUFFER_OWNED_BY_DMA 0x80000000
236 /* Tx descriptors status */
237 #define ETH_LC_ERROR 0
238 #define ETH_UR_ERROR 0x00000002
239 #define ETH_RL_ERROR 0x00000004
240 #define ETH_LLC_SNAP_FORMAT 0x00000200
242 /* Rx descriptors status */
243 #define ETH_OVERRUN_ERROR 0x00000002
244 #define ETH_MAX_FRAME_LENGTH_ERROR 0x00000004
245 #define ETH_RESOURCE_ERROR 0x00000006
246 #define ETH_VLAN_TAGGED 0x00080000
247 #define ETH_BPDU_FRAME 0x00100000
248 #define ETH_UDP_FRAME_OVER_IP_V_4 0x00200000
249 #define ETH_OTHER_FRAME_TYPE 0x00400000
250 #define ETH_LAYER_2_IS_ETH_V_2 0x00800000
251 #define ETH_FRAME_TYPE_IP_V_4 0x01000000
252 #define ETH_FRAME_HEADER_OK 0x02000000
253 #define ETH_RX_LAST_DESC 0x04000000
254 #define ETH_RX_FIRST_DESC 0x08000000
255 #define ETH_UNKNOWN_DESTINATION_ADDR 0x10000000
256 #define ETH_RX_ENABLE_INTERRUPT 0x20000000
257 #define ETH_LAYER_4_CHECKSUM_OK 0x40000000
259 /* Rx descriptors byte count */
260 #define ETH_FRAME_FRAGMENTED 0x00000004
262 /* Tx descriptors command */
263 #define ETH_LAYER_4_CHECKSUM_FIRST_DESC 0x00000400
264 #define ETH_FRAME_SET_TO_VLAN 0x00008000
265 #define ETH_UDP_FRAME 0x00010000
266 #define ETH_GEN_TCP_UDP_CHECKSUM 0x00020000
267 #define ETH_GEN_IP_V_4_CHECKSUM 0x00040000
268 #define ETH_ZERO_PADDING 0x00080000
269 #define ETH_TX_LAST_DESC 0x00100000
270 #define ETH_TX_FIRST_DESC 0x00200000
271 #define ETH_GEN_CRC 0x00400000
272 #define ETH_TX_ENABLE_INTERRUPT 0x00800000
273 #define ETH_AUTO_MODE 0x40000000
275 #define ETH_TX_IHL_SHIFT 11
279 typedef enum _eth_func_ret_status {
280 ETH_OK, /* Returned as expected. */
281 ETH_ERROR, /* Fundamental error. */
282 ETH_RETRY, /* Could not process request. Try later.*/
283 ETH_END_OF_JOB, /* Ring has nothing to process. */
284 ETH_QUEUE_FULL, /* Ring resource error. */
285 ETH_QUEUE_LAST_RESOURCE /* Ring resources about to exhaust. */
286 } ETH_FUNC_RET_STATUS;
288 /* These are for big-endian machines. Little endian needs different
291 #if defined(__BIG_ENDIAN)
293 u16 byte_cnt; /* Descriptor buffer byte count */
294 u16 buf_size; /* Buffer size */
295 u32 cmd_sts; /* Descriptor command status */
296 u32 next_desc_ptr; /* Next descriptor pointer */
297 u32 buf_ptr; /* Descriptor buffer pointer */
301 u16 byte_cnt; /* buffer byte count */
302 u16 l4i_chk; /* CPU provided TCP checksum */
303 u32 cmd_sts; /* Command/status field */
304 u32 next_desc_ptr; /* Pointer to next descriptor */
305 u32 buf_ptr; /* pointer to buffer for this descriptor*/
307 #elif defined(__LITTLE_ENDIAN)
309 u32 cmd_sts; /* Descriptor command status */
310 u16 buf_size; /* Buffer size */
311 u16 byte_cnt; /* Descriptor buffer byte count */
312 u32 buf_ptr; /* Descriptor buffer pointer */
313 u32 next_desc_ptr; /* Next descriptor pointer */
317 u32 cmd_sts; /* Command/status field */
318 u16 l4i_chk; /* CPU provided TCP checksum */
319 u16 byte_cnt; /* buffer byte count */
320 u32 buf_ptr; /* pointer to buffer for this descriptor*/
321 u32 next_desc_ptr; /* Pointer to next descriptor */
324 #error One of __BIG_ENDIAN or __LITTLE_ENDIAN must be defined
327 /* Unified struct for Rx and Tx operations. The user is not required to */
328 /* be familier with neither Tx nor Rx descriptors. */
330 unsigned short byte_cnt; /* Descriptor buffer byte count */
331 unsigned short l4i_chk; /* Tx CPU provided TCP Checksum */
332 unsigned int cmd_sts; /* Descriptor command status */
333 dma_addr_t buf_ptr; /* Descriptor buffer pointer */
334 struct sk_buff *return_info; /* User resource return information */
338 /* global *******************************************************************/
339 struct mv643xx_shared_private {
340 void __iomem *eth_base;
342 /* used to protect SMI_REG, which is shared across ports */
351 /* per-port *****************************************************************/
352 struct mv643xx_mib_counters {
353 u64 good_octets_received;
354 u32 bad_octets_received;
355 u32 internal_mac_transmit_err;
356 u32 good_frames_received;
357 u32 bad_frames_received;
358 u32 broadcast_frames_received;
359 u32 multicast_frames_received;
360 u32 frames_64_octets;
361 u32 frames_65_to_127_octets;
362 u32 frames_128_to_255_octets;
363 u32 frames_256_to_511_octets;
364 u32 frames_512_to_1023_octets;
365 u32 frames_1024_to_max_octets;
366 u64 good_octets_sent;
367 u32 good_frames_sent;
368 u32 excessive_collision;
369 u32 multicast_frames_sent;
370 u32 broadcast_frames_sent;
371 u32 unrec_mac_control_received;
373 u32 good_fc_received;
375 u32 undersize_received;
376 u32 fragments_received;
377 u32 oversize_received;
379 u32 mac_receive_error;
385 struct mv643xx_private {
386 struct mv643xx_shared_private *shared;
387 int port_num; /* User Ethernet port number */
389 struct mv643xx_shared_private *shared_smi;
391 u32 rx_sram_addr; /* Base address of rx sram area */
392 u32 rx_sram_size; /* Size of rx sram area */
393 u32 tx_sram_addr; /* Base address of tx sram area */
394 u32 tx_sram_size; /* Size of tx sram area */
396 int rx_resource_err; /* Rx ring resource error flag */
398 /* Tx/Rx rings managment indexes fields. For driver use */
400 /* Next available and first returning Rx resource */
401 int rx_curr_desc_q, rx_used_desc_q;
403 /* Next available and first returning Tx resource */
404 int tx_curr_desc_q, tx_used_desc_q;
406 #ifdef MV643XX_TX_FAST_REFILL
407 u32 tx_clean_threshold;
410 struct eth_rx_desc *p_rx_desc_area;
411 dma_addr_t rx_desc_dma;
412 int rx_desc_area_size;
413 struct sk_buff **rx_skb;
415 struct eth_tx_desc *p_tx_desc_area;
416 dma_addr_t tx_desc_dma;
417 int tx_desc_area_size;
418 struct sk_buff **tx_skb;
420 struct work_struct tx_timeout_task;
422 struct net_device *dev;
423 struct napi_struct napi;
424 struct net_device_stats stats;
425 struct mv643xx_mib_counters mib_counters;
427 /* Size of Tx Ring per queue */
429 /* Number of tx descriptors in use */
431 /* Size of Rx Ring per queue */
433 /* Number of rx descriptors in use */
437 * Used in case RX Ring is empty, which can be caused when
438 * system does not have resources (skb's)
440 struct timer_list timeout;
444 struct mii_if_info mii;
448 /* port register accessors **************************************************/
449 static inline u32 rdl(struct mv643xx_private *mp, int offset)
451 return readl(mp->shared->eth_base + offset);
454 static inline void wrl(struct mv643xx_private *mp, int offset, u32 data)
456 writel(data, mp->shared->eth_base + offset);
460 /* rxq/txq helper functions *************************************************/
461 static void mv643xx_eth_port_enable_rx(struct mv643xx_private *mp,
464 wrl(mp, RXQ_COMMAND(mp->port_num), queues);
467 static unsigned int mv643xx_eth_port_disable_rx(struct mv643xx_private *mp)
469 unsigned int port_num = mp->port_num;
472 /* Stop Rx port activity. Check port Rx activity. */
473 queues = rdl(mp, RXQ_COMMAND(port_num)) & 0xFF;
475 /* Issue stop command for active queues only */
476 wrl(mp, RXQ_COMMAND(port_num), (queues << 8));
478 /* Wait for all Rx activity to terminate. */
479 /* Check port cause register that all Rx queues are stopped */
480 while (rdl(mp, RXQ_COMMAND(port_num)) & 0xFF)
487 static void mv643xx_eth_port_enable_tx(struct mv643xx_private *mp,
490 wrl(mp, TXQ_COMMAND(mp->port_num), queues);
493 static unsigned int mv643xx_eth_port_disable_tx(struct mv643xx_private *mp)
495 unsigned int port_num = mp->port_num;
498 /* Stop Tx port activity. Check port Tx activity. */
499 queues = rdl(mp, TXQ_COMMAND(port_num)) & 0xFF;
501 /* Issue stop command for active queues only */
502 wrl(mp, TXQ_COMMAND(port_num), (queues << 8));
504 /* Wait for all Tx activity to terminate. */
505 /* Check port cause register that all Tx queues are stopped */
506 while (rdl(mp, TXQ_COMMAND(port_num)) & 0xFF)
509 /* Wait for Tx FIFO to empty */
510 while (rdl(mp, PORT_STATUS(port_num)) & ETH_PORT_TX_FIFO_EMPTY)
518 /* rx ***********************************************************************/
519 static void mv643xx_eth_free_completed_tx_descs(struct net_device *dev);
522 * eth_rx_return_buff - Returns a Rx buffer back to the Rx ring.
525 * This routine returns a Rx buffer back to the Rx ring. It retrieves the
526 * next 'used' descriptor and attached the returned buffer to it.
527 * In case the Rx ring was in "resource error" condition, where there are
528 * no available Rx resources, the function resets the resource error flag.
531 * struct mv643xx_private *mp Ethernet Port Control srtuct.
532 * struct pkt_info *p_pkt_info Information on returned buffer.
535 * New available Rx resource in Rx descriptor ring.
538 * ETH_ERROR in case the routine can not access Rx desc ring.
541 static ETH_FUNC_RET_STATUS eth_rx_return_buff(struct mv643xx_private *mp,
542 struct pkt_info *p_pkt_info)
544 int used_rx_desc; /* Where to return Rx resource */
545 volatile struct eth_rx_desc *p_used_rx_desc;
548 spin_lock_irqsave(&mp->lock, flags);
550 /* Get 'used' Rx descriptor */
551 used_rx_desc = mp->rx_used_desc_q;
552 p_used_rx_desc = &mp->p_rx_desc_area[used_rx_desc];
554 p_used_rx_desc->buf_ptr = p_pkt_info->buf_ptr;
555 p_used_rx_desc->buf_size = p_pkt_info->byte_cnt;
556 mp->rx_skb[used_rx_desc] = p_pkt_info->return_info;
558 /* Flush the write pipe */
560 /* Return the descriptor to DMA ownership */
562 p_used_rx_desc->cmd_sts =
563 ETH_BUFFER_OWNED_BY_DMA | ETH_RX_ENABLE_INTERRUPT;
566 /* Move the used descriptor pointer to the next descriptor */
567 mp->rx_used_desc_q = (used_rx_desc + 1) % mp->rx_ring_size;
569 /* Any Rx return cancels the Rx resource error status */
570 mp->rx_resource_err = 0;
572 spin_unlock_irqrestore(&mp->lock, flags);
578 * mv643xx_eth_rx_refill_descs
580 * Fills / refills RX queue on a certain gigabit ethernet port
582 * Input : pointer to ethernet interface network device structure
585 static void mv643xx_eth_rx_refill_descs(struct net_device *dev)
587 struct mv643xx_private *mp = netdev_priv(dev);
588 struct pkt_info pkt_info;
592 while (mp->rx_desc_count < mp->rx_ring_size) {
593 skb = dev_alloc_skb(ETH_RX_SKB_SIZE + dma_get_cache_alignment());
597 unaligned = (u32)skb->data & (dma_get_cache_alignment() - 1);
599 skb_reserve(skb, dma_get_cache_alignment() - unaligned);
600 pkt_info.cmd_sts = ETH_RX_ENABLE_INTERRUPT;
601 pkt_info.byte_cnt = ETH_RX_SKB_SIZE;
602 pkt_info.buf_ptr = dma_map_single(NULL, skb->data,
603 ETH_RX_SKB_SIZE, DMA_FROM_DEVICE);
604 pkt_info.return_info = skb;
605 if (eth_rx_return_buff(mp, &pkt_info) != ETH_OK) {
607 "%s: Error allocating RX Ring\n", dev->name);
610 skb_reserve(skb, ETH_HW_IP_ALIGN);
613 * If RX ring is empty of SKB, set a timer to try allocating
614 * again at a later time.
616 if (mp->rx_desc_count == 0) {
617 printk(KERN_INFO "%s: Rx ring is empty\n", dev->name);
618 mp->timeout.expires = jiffies + (HZ / 10); /* 100 mSec */
619 add_timer(&mp->timeout);
624 * mv643xx_eth_rx_refill_descs_timer_wrapper
626 * Timer routine to wake up RX queue filling task. This function is
627 * used only in case the RX queue is empty, and all alloc_skb has
628 * failed (due to out of memory event).
630 * Input : pointer to ethernet interface network device structure
633 static inline void mv643xx_eth_rx_refill_descs_timer_wrapper(unsigned long data)
635 mv643xx_eth_rx_refill_descs((struct net_device *)data);
639 * eth_port_receive - Get received information from Rx ring.
642 * This routine returns the received data to the caller. There is no
643 * data copying during routine operation. All information is returned
644 * using pointer to packet information struct passed from the caller.
645 * If the routine exhausts Rx ring resources then the resource error flag
649 * struct mv643xx_private *mp Ethernet Port Control srtuct.
650 * struct pkt_info *p_pkt_info User packet buffer.
653 * Rx ring current and used indexes are updated.
656 * ETH_ERROR in case the routine can not access Rx desc ring.
657 * ETH_QUEUE_FULL if Rx ring resources are exhausted.
658 * ETH_END_OF_JOB if there is no received data.
661 static ETH_FUNC_RET_STATUS eth_port_receive(struct mv643xx_private *mp,
662 struct pkt_info *p_pkt_info)
664 int rx_next_curr_desc, rx_curr_desc, rx_used_desc;
665 volatile struct eth_rx_desc *p_rx_desc;
666 unsigned int command_status;
669 /* Do not process Rx ring in case of Rx ring resource error */
670 if (mp->rx_resource_err)
671 return ETH_QUEUE_FULL;
673 spin_lock_irqsave(&mp->lock, flags);
675 /* Get the Rx Desc ring 'curr and 'used' indexes */
676 rx_curr_desc = mp->rx_curr_desc_q;
677 rx_used_desc = mp->rx_used_desc_q;
679 p_rx_desc = &mp->p_rx_desc_area[rx_curr_desc];
681 /* The following parameters are used to save readings from memory */
682 command_status = p_rx_desc->cmd_sts;
685 /* Nothing to receive... */
686 if (command_status & (ETH_BUFFER_OWNED_BY_DMA)) {
687 spin_unlock_irqrestore(&mp->lock, flags);
688 return ETH_END_OF_JOB;
691 p_pkt_info->byte_cnt = p_rx_desc->byte_cnt - ETH_HW_IP_ALIGN;
692 p_pkt_info->cmd_sts = command_status;
693 p_pkt_info->buf_ptr = p_rx_desc->buf_ptr + ETH_HW_IP_ALIGN;
694 p_pkt_info->return_info = mp->rx_skb[rx_curr_desc];
695 p_pkt_info->l4i_chk = p_rx_desc->buf_size;
698 * Clean the return info field to indicate that the
699 * packet has been moved to the upper layers
701 mp->rx_skb[rx_curr_desc] = NULL;
703 /* Update current index in data structure */
704 rx_next_curr_desc = (rx_curr_desc + 1) % mp->rx_ring_size;
705 mp->rx_curr_desc_q = rx_next_curr_desc;
707 /* Rx descriptors exhausted. Set the Rx ring resource error flag */
708 if (rx_next_curr_desc == rx_used_desc)
709 mp->rx_resource_err = 1;
711 spin_unlock_irqrestore(&mp->lock, flags);
717 * mv643xx_eth_receive
719 * This function is forward packets that are received from the port's
720 * queues toward kernel core or FastRoute them to another interface.
722 * Input : dev - a pointer to the required interface
723 * max - maximum number to receive (0 means unlimted)
725 * Output : number of served packets
727 static int mv643xx_eth_receive_queue(struct net_device *dev, int budget)
729 struct mv643xx_private *mp = netdev_priv(dev);
730 struct net_device_stats *stats = &dev->stats;
731 unsigned int received_packets = 0;
733 struct pkt_info pkt_info;
735 while (budget-- > 0 && eth_port_receive(mp, &pkt_info) == ETH_OK) {
736 dma_unmap_single(NULL, pkt_info.buf_ptr, ETH_RX_SKB_SIZE,
743 * Note byte count includes 4 byte CRC count
746 stats->rx_bytes += pkt_info.byte_cnt;
747 skb = pkt_info.return_info;
749 * In case received a packet without first / last bits on OR
750 * the error summary bit is on, the packets needs to be dropeed.
752 if (((pkt_info.cmd_sts
753 & (ETH_RX_FIRST_DESC | ETH_RX_LAST_DESC)) !=
754 (ETH_RX_FIRST_DESC | ETH_RX_LAST_DESC))
755 || (pkt_info.cmd_sts & ETH_ERROR_SUMMARY)) {
757 if ((pkt_info.cmd_sts & (ETH_RX_FIRST_DESC |
758 ETH_RX_LAST_DESC)) !=
759 (ETH_RX_FIRST_DESC | ETH_RX_LAST_DESC)) {
762 "%s: Received packet spread "
763 "on multiple descriptors\n",
766 if (pkt_info.cmd_sts & ETH_ERROR_SUMMARY)
769 dev_kfree_skb_irq(skb);
772 * The -4 is for the CRC in the trailer of the
775 skb_put(skb, pkt_info.byte_cnt - 4);
777 if (pkt_info.cmd_sts & ETH_LAYER_4_CHECKSUM_OK) {
778 skb->ip_summed = CHECKSUM_UNNECESSARY;
780 (pkt_info.cmd_sts & 0x0007fff8) >> 3);
782 skb->protocol = eth_type_trans(skb, dev);
784 netif_receive_skb(skb);
789 dev->last_rx = jiffies;
791 mv643xx_eth_rx_refill_descs(dev); /* Fill RX ring with skb's */
793 return received_packets;
800 * This function is used in case of NAPI
802 static int mv643xx_poll(struct napi_struct *napi, int budget)
804 struct mv643xx_private *mp = container_of(napi, struct mv643xx_private, napi);
805 struct net_device *dev = mp->dev;
806 unsigned int port_num = mp->port_num;
809 #ifdef MV643XX_TX_FAST_REFILL
810 if (++mp->tx_clean_threshold > 5) {
811 mv643xx_eth_free_completed_tx_descs(dev);
812 mp->tx_clean_threshold = 0;
817 if ((rdl(mp, RXQ_CURRENT_DESC_PTR(port_num)))
818 != (u32) mp->rx_used_desc_q)
819 work_done = mv643xx_eth_receive_queue(dev, budget);
821 if (work_done < budget) {
822 netif_rx_complete(dev, napi);
823 wrl(mp, INT_CAUSE(port_num), 0);
824 wrl(mp, INT_CAUSE_EXT(port_num), 0);
825 wrl(mp, INT_MASK(port_num), INT_RX | INT_EXT);
833 /* tx ***********************************************************************/
835 * has_tiny_unaligned_frags - check if skb has any small, unaligned fragments
837 * Hardware can't handle unaligned fragments smaller than 9 bytes.
838 * This helper function detects that case.
841 static inline unsigned int has_tiny_unaligned_frags(struct sk_buff *skb)
846 for (frag = 0; frag < skb_shinfo(skb)->nr_frags; frag++) {
847 fragp = &skb_shinfo(skb)->frags[frag];
848 if (fragp->size <= 8 && fragp->page_offset & 0x7)
855 * eth_alloc_tx_desc_index - return the index of the next available tx desc
857 static int eth_alloc_tx_desc_index(struct mv643xx_private *mp)
861 BUG_ON(mp->tx_desc_count >= mp->tx_ring_size);
863 tx_desc_curr = mp->tx_curr_desc_q;
864 mp->tx_curr_desc_q = (tx_desc_curr + 1) % mp->tx_ring_size;
866 BUG_ON(mp->tx_curr_desc_q == mp->tx_used_desc_q);
872 * eth_tx_fill_frag_descs - fill tx hw descriptors for an skb's fragments.
874 * Ensure the data for each fragment to be transmitted is mapped properly,
875 * then fill in descriptors in the tx hw queue.
877 static void eth_tx_fill_frag_descs(struct mv643xx_private *mp,
882 struct eth_tx_desc *desc;
884 for (frag = 0; frag < skb_shinfo(skb)->nr_frags; frag++) {
885 skb_frag_t *this_frag = &skb_shinfo(skb)->frags[frag];
887 tx_index = eth_alloc_tx_desc_index(mp);
888 desc = &mp->p_tx_desc_area[tx_index];
890 desc->cmd_sts = ETH_BUFFER_OWNED_BY_DMA;
891 /* Last Frag enables interrupt and frees the skb */
892 if (frag == (skb_shinfo(skb)->nr_frags - 1)) {
893 desc->cmd_sts |= ETH_ZERO_PADDING |
895 ETH_TX_ENABLE_INTERRUPT;
896 mp->tx_skb[tx_index] = skb;
898 mp->tx_skb[tx_index] = NULL;
900 desc = &mp->p_tx_desc_area[tx_index];
902 desc->byte_cnt = this_frag->size;
903 desc->buf_ptr = dma_map_page(NULL, this_frag->page,
904 this_frag->page_offset,
910 static inline __be16 sum16_as_be(__sum16 sum)
912 return (__force __be16)sum;
916 * eth_tx_submit_descs_for_skb - submit data from an skb to the tx hw
918 * Ensure the data for an skb to be transmitted is mapped properly,
919 * then fill in descriptors in the tx hw queue and start the hardware.
921 static void eth_tx_submit_descs_for_skb(struct mv643xx_private *mp,
925 struct eth_tx_desc *desc;
928 int nr_frags = skb_shinfo(skb)->nr_frags;
930 cmd_sts = ETH_TX_FIRST_DESC | ETH_GEN_CRC | ETH_BUFFER_OWNED_BY_DMA;
932 tx_index = eth_alloc_tx_desc_index(mp);
933 desc = &mp->p_tx_desc_area[tx_index];
936 eth_tx_fill_frag_descs(mp, skb);
938 length = skb_headlen(skb);
939 mp->tx_skb[tx_index] = NULL;
941 cmd_sts |= ETH_ZERO_PADDING |
943 ETH_TX_ENABLE_INTERRUPT;
945 mp->tx_skb[tx_index] = skb;
948 desc->byte_cnt = length;
949 desc->buf_ptr = dma_map_single(NULL, skb->data, length, DMA_TO_DEVICE);
951 if (skb->ip_summed == CHECKSUM_PARTIAL) {
952 BUG_ON(skb->protocol != htons(ETH_P_IP));
954 cmd_sts |= ETH_GEN_TCP_UDP_CHECKSUM |
955 ETH_GEN_IP_V_4_CHECKSUM |
956 ip_hdr(skb)->ihl << ETH_TX_IHL_SHIFT;
958 switch (ip_hdr(skb)->protocol) {
960 cmd_sts |= ETH_UDP_FRAME;
961 desc->l4i_chk = ntohs(sum16_as_be(udp_hdr(skb)->check));
964 desc->l4i_chk = ntohs(sum16_as_be(tcp_hdr(skb)->check));
970 /* Errata BTS #50, IHL must be 5 if no HW checksum */
971 cmd_sts |= 5 << ETH_TX_IHL_SHIFT;
975 /* ensure all other descriptors are written before first cmd_sts */
977 desc->cmd_sts = cmd_sts;
979 /* ensure all descriptors are written before poking hardware */
981 mv643xx_eth_port_enable_tx(mp, 1);
983 mp->tx_desc_count += nr_frags + 1;
987 * mv643xx_eth_start_xmit - queue an skb to the hardware for transmission
990 static int mv643xx_eth_start_xmit(struct sk_buff *skb, struct net_device *dev)
992 struct mv643xx_private *mp = netdev_priv(dev);
993 struct net_device_stats *stats = &dev->stats;
996 BUG_ON(netif_queue_stopped(dev));
998 if (has_tiny_unaligned_frags(skb) && __skb_linearize(skb)) {
1000 printk(KERN_DEBUG "%s: failed to linearize tiny "
1001 "unaligned fragment\n", dev->name);
1002 return NETDEV_TX_BUSY;
1005 spin_lock_irqsave(&mp->lock, flags);
1007 if (mp->tx_ring_size - mp->tx_desc_count < MAX_DESCS_PER_SKB) {
1008 printk(KERN_ERR "%s: transmit with queue full\n", dev->name);
1009 netif_stop_queue(dev);
1010 spin_unlock_irqrestore(&mp->lock, flags);
1011 return NETDEV_TX_BUSY;
1014 eth_tx_submit_descs_for_skb(mp, skb);
1015 stats->tx_bytes += skb->len;
1016 stats->tx_packets++;
1017 dev->trans_start = jiffies;
1019 if (mp->tx_ring_size - mp->tx_desc_count < MAX_DESCS_PER_SKB)
1020 netif_stop_queue(dev);
1022 spin_unlock_irqrestore(&mp->lock, flags);
1024 return NETDEV_TX_OK;
1028 /* mii management interface *************************************************/
1029 static int ethernet_phy_get(struct mv643xx_private *mp);
1032 * eth_port_read_smi_reg - Read PHY registers
1035 * This routine utilize the SMI interface to interact with the PHY in
1036 * order to perform PHY register read.
1039 * struct mv643xx_private *mp Ethernet Port.
1040 * unsigned int phy_reg PHY register address offset.
1041 * unsigned int *value Register value buffer.
1044 * Write the value of a specified PHY register into given buffer.
1047 * false if the PHY is busy or read data is not in valid state.
1051 static void eth_port_read_smi_reg(struct mv643xx_private *mp,
1052 unsigned int phy_reg, unsigned int *value)
1054 void __iomem *smi_reg = mp->shared_smi->eth_base + SMI_REG;
1055 int phy_addr = ethernet_phy_get(mp);
1056 unsigned long flags;
1059 /* the SMI register is a shared resource */
1060 spin_lock_irqsave(&mp->shared_smi->phy_lock, flags);
1062 /* wait for the SMI register to become available */
1063 for (i = 0; readl(smi_reg) & ETH_SMI_BUSY; i++) {
1065 printk("%s: PHY busy timeout\n", mp->dev->name);
1071 writel((phy_addr << 16) | (phy_reg << 21) | ETH_SMI_OPCODE_READ,
1074 /* now wait for the data to be valid */
1075 for (i = 0; !(readl(smi_reg) & ETH_SMI_READ_VALID); i++) {
1077 printk("%s: PHY read timeout\n", mp->dev->name);
1083 *value = readl(smi_reg) & 0xffff;
1085 spin_unlock_irqrestore(&mp->shared_smi->phy_lock, flags);
1089 * eth_port_write_smi_reg - Write to PHY registers
1092 * This routine utilize the SMI interface to interact with the PHY in
1093 * order to perform writes to PHY registers.
1096 * struct mv643xx_private *mp Ethernet Port.
1097 * unsigned int phy_reg PHY register address offset.
1098 * unsigned int value Register value.
1101 * Write the given value to the specified PHY register.
1104 * false if the PHY is busy.
1108 static void eth_port_write_smi_reg(struct mv643xx_private *mp,
1109 unsigned int phy_reg, unsigned int value)
1111 void __iomem *smi_reg = mp->shared_smi->eth_base + SMI_REG;
1112 int phy_addr = ethernet_phy_get(mp);
1113 unsigned long flags;
1116 /* the SMI register is a shared resource */
1117 spin_lock_irqsave(&mp->shared_smi->phy_lock, flags);
1119 /* wait for the SMI register to become available */
1120 for (i = 0; readl(smi_reg) & ETH_SMI_BUSY; i++) {
1122 printk("%s: PHY busy timeout\n", mp->dev->name);
1128 writel((phy_addr << 16) | (phy_reg << 21) |
1129 ETH_SMI_OPCODE_WRITE | (value & 0xffff), smi_reg);
1131 spin_unlock_irqrestore(&mp->shared_smi->phy_lock, flags);
1135 /* mib counters *************************************************************/
1137 * eth_clear_mib_counters - Clear all MIB counters
1140 * This function clears all MIB counters of a specific ethernet port.
1141 * A read from the MIB counter will reset the counter.
1144 * struct mv643xx_private *mp Ethernet Port.
1147 * After reading all MIB counters, the counters resets.
1150 * MIB counter value.
1153 static void eth_clear_mib_counters(struct mv643xx_private *mp)
1155 unsigned int port_num = mp->port_num;
1158 /* Perform dummy reads from MIB counters */
1159 for (i = ETH_MIB_GOOD_OCTETS_RECEIVED_LOW; i < ETH_MIB_LATE_COLLISION;
1161 rdl(mp, MIB_COUNTERS(port_num) + i);
1164 static inline u32 read_mib(struct mv643xx_private *mp, int offset)
1166 return rdl(mp, MIB_COUNTERS(mp->port_num) + offset);
1169 static void eth_update_mib_counters(struct mv643xx_private *mp)
1171 struct mv643xx_mib_counters *p = &mp->mib_counters;
1174 p->good_octets_received +=
1175 read_mib(mp, ETH_MIB_GOOD_OCTETS_RECEIVED_LOW);
1176 p->good_octets_received +=
1177 (u64)read_mib(mp, ETH_MIB_GOOD_OCTETS_RECEIVED_HIGH) << 32;
1179 for (offset = ETH_MIB_BAD_OCTETS_RECEIVED;
1180 offset <= ETH_MIB_FRAMES_1024_TO_MAX_OCTETS;
1182 *(u32 *)((char *)p + offset) += read_mib(mp, offset);
1184 p->good_octets_sent += read_mib(mp, ETH_MIB_GOOD_OCTETS_SENT_LOW);
1185 p->good_octets_sent +=
1186 (u64)read_mib(mp, ETH_MIB_GOOD_OCTETS_SENT_HIGH) << 32;
1188 for (offset = ETH_MIB_GOOD_FRAMES_SENT;
1189 offset <= ETH_MIB_LATE_COLLISION;
1191 *(u32 *)((char *)p + offset) += read_mib(mp, offset);
1195 /* ethtool ******************************************************************/
1196 struct mv643xx_stats {
1197 char stat_string[ETH_GSTRING_LEN];
1202 #define MV643XX_STAT(m) FIELD_SIZEOF(struct mv643xx_private, m), \
1203 offsetof(struct mv643xx_private, m)
1205 static const struct mv643xx_stats mv643xx_gstrings_stats[] = {
1206 { "rx_packets", MV643XX_STAT(stats.rx_packets) },
1207 { "tx_packets", MV643XX_STAT(stats.tx_packets) },
1208 { "rx_bytes", MV643XX_STAT(stats.rx_bytes) },
1209 { "tx_bytes", MV643XX_STAT(stats.tx_bytes) },
1210 { "rx_errors", MV643XX_STAT(stats.rx_errors) },
1211 { "tx_errors", MV643XX_STAT(stats.tx_errors) },
1212 { "rx_dropped", MV643XX_STAT(stats.rx_dropped) },
1213 { "tx_dropped", MV643XX_STAT(stats.tx_dropped) },
1214 { "good_octets_received", MV643XX_STAT(mib_counters.good_octets_received) },
1215 { "bad_octets_received", MV643XX_STAT(mib_counters.bad_octets_received) },
1216 { "internal_mac_transmit_err", MV643XX_STAT(mib_counters.internal_mac_transmit_err) },
1217 { "good_frames_received", MV643XX_STAT(mib_counters.good_frames_received) },
1218 { "bad_frames_received", MV643XX_STAT(mib_counters.bad_frames_received) },
1219 { "broadcast_frames_received", MV643XX_STAT(mib_counters.broadcast_frames_received) },
1220 { "multicast_frames_received", MV643XX_STAT(mib_counters.multicast_frames_received) },
1221 { "frames_64_octets", MV643XX_STAT(mib_counters.frames_64_octets) },
1222 { "frames_65_to_127_octets", MV643XX_STAT(mib_counters.frames_65_to_127_octets) },
1223 { "frames_128_to_255_octets", MV643XX_STAT(mib_counters.frames_128_to_255_octets) },
1224 { "frames_256_to_511_octets", MV643XX_STAT(mib_counters.frames_256_to_511_octets) },
1225 { "frames_512_to_1023_octets", MV643XX_STAT(mib_counters.frames_512_to_1023_octets) },
1226 { "frames_1024_to_max_octets", MV643XX_STAT(mib_counters.frames_1024_to_max_octets) },
1227 { "good_octets_sent", MV643XX_STAT(mib_counters.good_octets_sent) },
1228 { "good_frames_sent", MV643XX_STAT(mib_counters.good_frames_sent) },
1229 { "excessive_collision", MV643XX_STAT(mib_counters.excessive_collision) },
1230 { "multicast_frames_sent", MV643XX_STAT(mib_counters.multicast_frames_sent) },
1231 { "broadcast_frames_sent", MV643XX_STAT(mib_counters.broadcast_frames_sent) },
1232 { "unrec_mac_control_received", MV643XX_STAT(mib_counters.unrec_mac_control_received) },
1233 { "fc_sent", MV643XX_STAT(mib_counters.fc_sent) },
1234 { "good_fc_received", MV643XX_STAT(mib_counters.good_fc_received) },
1235 { "bad_fc_received", MV643XX_STAT(mib_counters.bad_fc_received) },
1236 { "undersize_received", MV643XX_STAT(mib_counters.undersize_received) },
1237 { "fragments_received", MV643XX_STAT(mib_counters.fragments_received) },
1238 { "oversize_received", MV643XX_STAT(mib_counters.oversize_received) },
1239 { "jabber_received", MV643XX_STAT(mib_counters.jabber_received) },
1240 { "mac_receive_error", MV643XX_STAT(mib_counters.mac_receive_error) },
1241 { "bad_crc_event", MV643XX_STAT(mib_counters.bad_crc_event) },
1242 { "collision", MV643XX_STAT(mib_counters.collision) },
1243 { "late_collision", MV643XX_STAT(mib_counters.late_collision) },
1246 #define MV643XX_STATS_LEN ARRAY_SIZE(mv643xx_gstrings_stats)
1248 static int mv643xx_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1250 struct mv643xx_private *mp = netdev_priv(dev);
1253 spin_lock_irq(&mp->lock);
1254 err = mii_ethtool_gset(&mp->mii, cmd);
1255 spin_unlock_irq(&mp->lock);
1257 /* The PHY may support 1000baseT_Half, but the mv643xx does not */
1258 cmd->supported &= ~SUPPORTED_1000baseT_Half;
1259 cmd->advertising &= ~ADVERTISED_1000baseT_Half;
1264 static int mv643xx_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1266 struct mv643xx_private *mp = netdev_priv(dev);
1269 spin_lock_irq(&mp->lock);
1270 err = mii_ethtool_sset(&mp->mii, cmd);
1271 spin_unlock_irq(&mp->lock);
1276 static void mv643xx_get_drvinfo(struct net_device *netdev,
1277 struct ethtool_drvinfo *drvinfo)
1279 strncpy(drvinfo->driver, mv643xx_driver_name, 32);
1280 strncpy(drvinfo->version, mv643xx_driver_version, 32);
1281 strncpy(drvinfo->fw_version, "N/A", 32);
1282 strncpy(drvinfo->bus_info, "mv643xx", 32);
1283 drvinfo->n_stats = MV643XX_STATS_LEN;
1286 static int mv643xx_eth_nway_restart(struct net_device *dev)
1288 struct mv643xx_private *mp = netdev_priv(dev);
1290 return mii_nway_restart(&mp->mii);
1293 static u32 mv643xx_eth_get_link(struct net_device *dev)
1295 struct mv643xx_private *mp = netdev_priv(dev);
1297 return mii_link_ok(&mp->mii);
1300 static void mv643xx_get_strings(struct net_device *netdev, uint32_t stringset,
1307 for (i=0; i < MV643XX_STATS_LEN; i++) {
1308 memcpy(data + i * ETH_GSTRING_LEN,
1309 mv643xx_gstrings_stats[i].stat_string,
1316 static void mv643xx_get_ethtool_stats(struct net_device *netdev,
1317 struct ethtool_stats *stats, uint64_t *data)
1319 struct mv643xx_private *mp = netdev->priv;
1322 eth_update_mib_counters(mp);
1324 for (i = 0; i < MV643XX_STATS_LEN; i++) {
1325 char *p = (char *)mp+mv643xx_gstrings_stats[i].stat_offset;
1326 data[i] = (mv643xx_gstrings_stats[i].sizeof_stat ==
1327 sizeof(uint64_t)) ? *(uint64_t *)p : *(uint32_t *)p;
1331 static int mv643xx_get_sset_count(struct net_device *netdev, int sset)
1335 return MV643XX_STATS_LEN;
1341 static const struct ethtool_ops mv643xx_ethtool_ops = {
1342 .get_settings = mv643xx_get_settings,
1343 .set_settings = mv643xx_set_settings,
1344 .get_drvinfo = mv643xx_get_drvinfo,
1345 .get_link = mv643xx_eth_get_link,
1346 .set_sg = ethtool_op_set_sg,
1347 .get_sset_count = mv643xx_get_sset_count,
1348 .get_ethtool_stats = mv643xx_get_ethtool_stats,
1349 .get_strings = mv643xx_get_strings,
1350 .nway_reset = mv643xx_eth_nway_restart,
1354 /* address handling *********************************************************/
1356 * eth_port_uc_addr_get - Read the MAC address from the port's hw registers
1358 static void eth_port_uc_addr_get(struct mv643xx_private *mp,
1359 unsigned char *p_addr)
1361 unsigned int port_num = mp->port_num;
1365 mac_h = rdl(mp, MAC_ADDR_HIGH(port_num));
1366 mac_l = rdl(mp, MAC_ADDR_LOW(port_num));
1368 p_addr[0] = (mac_h >> 24) & 0xff;
1369 p_addr[1] = (mac_h >> 16) & 0xff;
1370 p_addr[2] = (mac_h >> 8) & 0xff;
1371 p_addr[3] = mac_h & 0xff;
1372 p_addr[4] = (mac_l >> 8) & 0xff;
1373 p_addr[5] = mac_l & 0xff;
1377 * eth_port_init_mac_tables - Clear all entrance in the UC, SMC and OMC tables
1380 * Go through all the DA filter tables (Unicast, Special Multicast &
1381 * Other Multicast) and set each entry to 0.
1384 * struct mv643xx_private *mp Ethernet Port.
1387 * Multicast and Unicast packets are rejected.
1392 static void eth_port_init_mac_tables(struct mv643xx_private *mp)
1394 unsigned int port_num = mp->port_num;
1397 /* Clear DA filter unicast table (Ex_dFUT) */
1398 for (table_index = 0; table_index <= 0xC; table_index += 4)
1399 wrl(mp, UNICAST_TABLE(port_num) + table_index, 0);
1401 for (table_index = 0; table_index <= 0xFC; table_index += 4) {
1402 /* Clear DA filter special multicast table (Ex_dFSMT) */
1403 wrl(mp, SPECIAL_MCAST_TABLE(port_num) + table_index, 0);
1404 /* Clear DA filter other multicast table (Ex_dFOMT) */
1405 wrl(mp, OTHER_MCAST_TABLE(port_num) + table_index, 0);
1410 * The entries in each table are indexed by a hash of a packet's MAC
1411 * address. One bit in each entry determines whether the packet is
1412 * accepted. There are 4 entries (each 8 bits wide) in each register
1413 * of the table. The bits in each entry are defined as follows:
1414 * 0 Accept=1, Drop=0
1415 * 3-1 Queue (ETH_Q0=0)
1418 static void eth_port_set_filter_table_entry(struct mv643xx_private *mp,
1419 int table, unsigned char entry)
1421 unsigned int table_reg;
1422 unsigned int tbl_offset;
1423 unsigned int reg_offset;
1425 tbl_offset = (entry / 4) * 4; /* Register offset of DA table entry */
1426 reg_offset = entry % 4; /* Entry offset within the register */
1428 /* Set "accepts frame bit" at specified table entry */
1429 table_reg = rdl(mp, table + tbl_offset);
1430 table_reg |= 0x01 << (8 * reg_offset);
1431 wrl(mp, table + tbl_offset, table_reg);
1435 * eth_port_uc_addr_set - Write a MAC address into the port's hw registers
1437 static void eth_port_uc_addr_set(struct mv643xx_private *mp,
1438 unsigned char *p_addr)
1440 unsigned int port_num = mp->port_num;
1445 mac_l = (p_addr[4] << 8) | (p_addr[5]);
1446 mac_h = (p_addr[0] << 24) | (p_addr[1] << 16) | (p_addr[2] << 8) |
1449 wrl(mp, MAC_ADDR_LOW(port_num), mac_l);
1450 wrl(mp, MAC_ADDR_HIGH(port_num), mac_h);
1452 /* Accept frames with this address */
1453 table = UNICAST_TABLE(port_num);
1454 eth_port_set_filter_table_entry(mp, table, p_addr[5] & 0x0f);
1458 * mv643xx_eth_update_mac_address
1460 * Update the MAC address of the port in the address table
1462 * Input : pointer to ethernet interface network device structure
1465 static void mv643xx_eth_update_mac_address(struct net_device *dev)
1467 struct mv643xx_private *mp = netdev_priv(dev);
1469 eth_port_init_mac_tables(mp);
1470 eth_port_uc_addr_set(mp, dev->dev_addr);
1474 * mv643xx_eth_set_mac_address
1476 * Change the interface's mac address.
1477 * No special hardware thing should be done because interface is always
1478 * put in promiscuous mode.
1480 * Input : pointer to ethernet interface network device structure and
1481 * a pointer to the designated entry to be added to the cache.
1482 * Output : zero upon success, negative upon failure
1484 static int mv643xx_eth_set_mac_address(struct net_device *dev, void *addr)
1488 for (i = 0; i < 6; i++)
1489 /* +2 is for the offset of the HW addr type */
1490 dev->dev_addr[i] = ((unsigned char *)addr)[i + 2];
1491 mv643xx_eth_update_mac_address(dev);
1496 * eth_port_mc_addr - Multicast address settings.
1498 * The MV device supports multicast using two tables:
1499 * 1) Special Multicast Table for MAC addresses of the form
1500 * 0x01-00-5E-00-00-XX (where XX is between 0x00 and 0x_FF).
1501 * The MAC DA[7:0] bits are used as a pointer to the Special Multicast
1502 * Table entries in the DA-Filter table.
1503 * 2) Other Multicast Table for multicast of another type. A CRC-8bit
1504 * is used as an index to the Other Multicast Table entries in the
1505 * DA-Filter table. This function calculates the CRC-8bit value.
1506 * In either case, eth_port_set_filter_table_entry() is then called
1507 * to set to set the actual table entry.
1509 static void eth_port_mc_addr(struct mv643xx_private *mp, unsigned char *p_addr)
1511 unsigned int port_num = mp->port_num;
1514 unsigned char crc_result = 0;
1520 if ((p_addr[0] == 0x01) && (p_addr[1] == 0x00) &&
1521 (p_addr[2] == 0x5E) && (p_addr[3] == 0x00) && (p_addr[4] == 0x00)) {
1522 table = SPECIAL_MCAST_TABLE(port_num);
1523 eth_port_set_filter_table_entry(mp, table, p_addr[5]);
1527 /* Calculate CRC-8 out of the given address */
1528 mac_h = (p_addr[0] << 8) | (p_addr[1]);
1529 mac_l = (p_addr[2] << 24) | (p_addr[3] << 16) |
1530 (p_addr[4] << 8) | (p_addr[5] << 0);
1532 for (i = 0; i < 32; i++)
1533 mac_array[i] = (mac_l >> i) & 0x1;
1534 for (i = 32; i < 48; i++)
1535 mac_array[i] = (mac_h >> (i - 32)) & 0x1;
1537 crc[0] = mac_array[45] ^ mac_array[43] ^ mac_array[40] ^ mac_array[39] ^
1538 mac_array[35] ^ mac_array[34] ^ mac_array[31] ^ mac_array[30] ^
1539 mac_array[28] ^ mac_array[23] ^ mac_array[21] ^ mac_array[19] ^
1540 mac_array[18] ^ mac_array[16] ^ mac_array[14] ^ mac_array[12] ^
1541 mac_array[8] ^ mac_array[7] ^ mac_array[6] ^ mac_array[0];
1543 crc[1] = mac_array[46] ^ mac_array[45] ^ mac_array[44] ^ mac_array[43] ^
1544 mac_array[41] ^ mac_array[39] ^ mac_array[36] ^ mac_array[34] ^
1545 mac_array[32] ^ mac_array[30] ^ mac_array[29] ^ mac_array[28] ^
1546 mac_array[24] ^ mac_array[23] ^ mac_array[22] ^ mac_array[21] ^
1547 mac_array[20] ^ mac_array[18] ^ mac_array[17] ^ mac_array[16] ^
1548 mac_array[15] ^ mac_array[14] ^ mac_array[13] ^ mac_array[12] ^
1549 mac_array[9] ^ mac_array[6] ^ mac_array[1] ^ mac_array[0];
1551 crc[2] = mac_array[47] ^ mac_array[46] ^ mac_array[44] ^ mac_array[43] ^
1552 mac_array[42] ^ mac_array[39] ^ mac_array[37] ^ mac_array[34] ^
1553 mac_array[33] ^ mac_array[29] ^ mac_array[28] ^ mac_array[25] ^
1554 mac_array[24] ^ mac_array[22] ^ mac_array[17] ^ mac_array[15] ^
1555 mac_array[13] ^ mac_array[12] ^ mac_array[10] ^ mac_array[8] ^
1556 mac_array[6] ^ mac_array[2] ^ mac_array[1] ^ mac_array[0];
1558 crc[3] = mac_array[47] ^ mac_array[45] ^ mac_array[44] ^ mac_array[43] ^
1559 mac_array[40] ^ mac_array[38] ^ mac_array[35] ^ mac_array[34] ^
1560 mac_array[30] ^ mac_array[29] ^ mac_array[26] ^ mac_array[25] ^
1561 mac_array[23] ^ mac_array[18] ^ mac_array[16] ^ mac_array[14] ^
1562 mac_array[13] ^ mac_array[11] ^ mac_array[9] ^ mac_array[7] ^
1563 mac_array[3] ^ mac_array[2] ^ mac_array[1];
1565 crc[4] = mac_array[46] ^ mac_array[45] ^ mac_array[44] ^ mac_array[41] ^
1566 mac_array[39] ^ mac_array[36] ^ mac_array[35] ^ mac_array[31] ^
1567 mac_array[30] ^ mac_array[27] ^ mac_array[26] ^ mac_array[24] ^
1568 mac_array[19] ^ mac_array[17] ^ mac_array[15] ^ mac_array[14] ^
1569 mac_array[12] ^ mac_array[10] ^ mac_array[8] ^ mac_array[4] ^
1570 mac_array[3] ^ mac_array[2];
1572 crc[5] = mac_array[47] ^ mac_array[46] ^ mac_array[45] ^ mac_array[42] ^
1573 mac_array[40] ^ mac_array[37] ^ mac_array[36] ^ mac_array[32] ^
1574 mac_array[31] ^ mac_array[28] ^ mac_array[27] ^ mac_array[25] ^
1575 mac_array[20] ^ mac_array[18] ^ mac_array[16] ^ mac_array[15] ^
1576 mac_array[13] ^ mac_array[11] ^ mac_array[9] ^ mac_array[5] ^
1577 mac_array[4] ^ mac_array[3];
1579 crc[6] = mac_array[47] ^ mac_array[46] ^ mac_array[43] ^ mac_array[41] ^
1580 mac_array[38] ^ mac_array[37] ^ mac_array[33] ^ mac_array[32] ^
1581 mac_array[29] ^ mac_array[28] ^ mac_array[26] ^ mac_array[21] ^
1582 mac_array[19] ^ mac_array[17] ^ mac_array[16] ^ mac_array[14] ^
1583 mac_array[12] ^ mac_array[10] ^ mac_array[6] ^ mac_array[5] ^
1586 crc[7] = mac_array[47] ^ mac_array[44] ^ mac_array[42] ^ mac_array[39] ^
1587 mac_array[38] ^ mac_array[34] ^ mac_array[33] ^ mac_array[30] ^
1588 mac_array[29] ^ mac_array[27] ^ mac_array[22] ^ mac_array[20] ^
1589 mac_array[18] ^ mac_array[17] ^ mac_array[15] ^ mac_array[13] ^
1590 mac_array[11] ^ mac_array[7] ^ mac_array[6] ^ mac_array[5];
1592 for (i = 0; i < 8; i++)
1593 crc_result = crc_result | (crc[i] << i);
1595 table = OTHER_MCAST_TABLE(port_num);
1596 eth_port_set_filter_table_entry(mp, table, crc_result);
1600 * Set the entire multicast list based on dev->mc_list.
1602 static void eth_port_set_multicast_list(struct net_device *dev)
1605 struct dev_mc_list *mc_list;
1608 struct mv643xx_private *mp = netdev_priv(dev);
1609 unsigned int eth_port_num = mp->port_num;
1611 /* If the device is in promiscuous mode or in all multicast mode,
1612 * we will fully populate both multicast tables with accept.
1613 * This is guaranteed to yield a match on all multicast addresses...
1615 if ((dev->flags & IFF_PROMISC) || (dev->flags & IFF_ALLMULTI)) {
1616 for (table_index = 0; table_index <= 0xFC; table_index += 4) {
1617 /* Set all entries in DA filter special multicast
1619 * Set for ETH_Q0 for now
1621 * 0 Accept=1, Drop=0
1622 * 3-1 Queue ETH_Q0=0
1625 wrl(mp, SPECIAL_MCAST_TABLE(eth_port_num) + table_index, 0x01010101);
1627 /* Set all entries in DA filter other multicast
1629 * Set for ETH_Q0 for now
1631 * 0 Accept=1, Drop=0
1632 * 3-1 Queue ETH_Q0=0
1635 wrl(mp, OTHER_MCAST_TABLE(eth_port_num) + table_index, 0x01010101);
1640 /* We will clear out multicast tables every time we get the list.
1641 * Then add the entire new list...
1643 for (table_index = 0; table_index <= 0xFC; table_index += 4) {
1644 /* Clear DA filter special multicast table (Ex_dFSMT) */
1645 wrl(mp, SPECIAL_MCAST_TABLE(eth_port_num) + table_index, 0);
1647 /* Clear DA filter other multicast table (Ex_dFOMT) */
1648 wrl(mp, OTHER_MCAST_TABLE(eth_port_num) + table_index, 0);
1651 /* Get pointer to net_device multicast list and add each one... */
1652 for (i = 0, mc_list = dev->mc_list;
1653 (i < 256) && (mc_list != NULL) && (i < dev->mc_count);
1654 i++, mc_list = mc_list->next)
1655 if (mc_list->dmi_addrlen == 6)
1656 eth_port_mc_addr(mp, mc_list->dmi_addr);
1660 * mv643xx_eth_set_rx_mode
1662 * Change from promiscuos to regular rx mode
1664 * Input : pointer to ethernet interface network device structure
1667 static void mv643xx_eth_set_rx_mode(struct net_device *dev)
1669 struct mv643xx_private *mp = netdev_priv(dev);
1672 config_reg = rdl(mp, PORT_CONFIG(mp->port_num));
1673 if (dev->flags & IFF_PROMISC)
1674 config_reg |= UNICAST_PROMISCUOUS_MODE;
1676 config_reg &= ~UNICAST_PROMISCUOUS_MODE;
1677 wrl(mp, PORT_CONFIG(mp->port_num), config_reg);
1679 eth_port_set_multicast_list(dev);
1683 /* rx/tx queue initialisation ***********************************************/
1685 * ether_init_rx_desc_ring - Curve a Rx chain desc list and buffer in memory.
1688 * This function prepares a Rx chained list of descriptors and packet
1689 * buffers in a form of a ring. The routine must be called after port
1690 * initialization routine and before port start routine.
1691 * The Ethernet SDMA engine uses CPU bus addresses to access the various
1692 * devices in the system (i.e. DRAM). This function uses the ethernet
1693 * struct 'virtual to physical' routine (set by the user) to set the ring
1694 * with physical addresses.
1697 * struct mv643xx_private *mp Ethernet Port Control srtuct.
1700 * The routine updates the Ethernet port control struct with information
1701 * regarding the Rx descriptors and buffers.
1706 static void ether_init_rx_desc_ring(struct mv643xx_private *mp)
1708 volatile struct eth_rx_desc *p_rx_desc;
1709 int rx_desc_num = mp->rx_ring_size;
1712 /* initialize the next_desc_ptr links in the Rx descriptors ring */
1713 p_rx_desc = (struct eth_rx_desc *)mp->p_rx_desc_area;
1714 for (i = 0; i < rx_desc_num; i++) {
1715 p_rx_desc[i].next_desc_ptr = mp->rx_desc_dma +
1716 ((i + 1) % rx_desc_num) * sizeof(struct eth_rx_desc);
1719 /* Save Rx desc pointer to driver struct. */
1720 mp->rx_curr_desc_q = 0;
1721 mp->rx_used_desc_q = 0;
1723 mp->rx_desc_area_size = rx_desc_num * sizeof(struct eth_rx_desc);
1726 static void mv643xx_eth_free_rx_rings(struct net_device *dev)
1728 struct mv643xx_private *mp = netdev_priv(dev);
1731 /* Stop RX Queues */
1732 mv643xx_eth_port_disable_rx(mp);
1734 /* Free preallocated skb's on RX rings */
1735 for (curr = 0; mp->rx_desc_count && curr < mp->rx_ring_size; curr++) {
1736 if (mp->rx_skb[curr]) {
1737 dev_kfree_skb(mp->rx_skb[curr]);
1738 mp->rx_desc_count--;
1742 if (mp->rx_desc_count)
1744 "%s: Error in freeing Rx Ring. %d skb's still"
1745 " stuck in RX Ring - ignoring them\n", dev->name,
1748 if (mp->rx_sram_size)
1749 iounmap(mp->p_rx_desc_area);
1751 dma_free_coherent(NULL, mp->rx_desc_area_size,
1752 mp->p_rx_desc_area, mp->rx_desc_dma);
1756 * ether_init_tx_desc_ring - Curve a Tx chain desc list and buffer in memory.
1759 * This function prepares a Tx chained list of descriptors and packet
1760 * buffers in a form of a ring. The routine must be called after port
1761 * initialization routine and before port start routine.
1762 * The Ethernet SDMA engine uses CPU bus addresses to access the various
1763 * devices in the system (i.e. DRAM). This function uses the ethernet
1764 * struct 'virtual to physical' routine (set by the user) to set the ring
1765 * with physical addresses.
1768 * struct mv643xx_private *mp Ethernet Port Control srtuct.
1771 * The routine updates the Ethernet port control struct with information
1772 * regarding the Tx descriptors and buffers.
1777 static void ether_init_tx_desc_ring(struct mv643xx_private *mp)
1779 int tx_desc_num = mp->tx_ring_size;
1780 struct eth_tx_desc *p_tx_desc;
1783 /* Initialize the next_desc_ptr links in the Tx descriptors ring */
1784 p_tx_desc = (struct eth_tx_desc *)mp->p_tx_desc_area;
1785 for (i = 0; i < tx_desc_num; i++) {
1786 p_tx_desc[i].next_desc_ptr = mp->tx_desc_dma +
1787 ((i + 1) % tx_desc_num) * sizeof(struct eth_tx_desc);
1790 mp->tx_curr_desc_q = 0;
1791 mp->tx_used_desc_q = 0;
1793 mp->tx_desc_area_size = tx_desc_num * sizeof(struct eth_tx_desc);
1797 * mv643xx_eth_free_tx_descs - Free the tx desc data for completed descriptors
1799 * If force is non-zero, frees uncompleted descriptors as well
1801 static int mv643xx_eth_free_tx_descs(struct net_device *dev, int force)
1803 struct mv643xx_private *mp = netdev_priv(dev);
1804 struct eth_tx_desc *desc;
1806 struct sk_buff *skb;
1807 unsigned long flags;
1813 while (mp->tx_desc_count > 0) {
1814 spin_lock_irqsave(&mp->lock, flags);
1816 /* tx_desc_count might have changed before acquiring the lock */
1817 if (mp->tx_desc_count <= 0) {
1818 spin_unlock_irqrestore(&mp->lock, flags);
1822 tx_index = mp->tx_used_desc_q;
1823 desc = &mp->p_tx_desc_area[tx_index];
1824 cmd_sts = desc->cmd_sts;
1826 if (!force && (cmd_sts & ETH_BUFFER_OWNED_BY_DMA)) {
1827 spin_unlock_irqrestore(&mp->lock, flags);
1831 mp->tx_used_desc_q = (tx_index + 1) % mp->tx_ring_size;
1832 mp->tx_desc_count--;
1834 addr = desc->buf_ptr;
1835 count = desc->byte_cnt;
1836 skb = mp->tx_skb[tx_index];
1838 mp->tx_skb[tx_index] = NULL;
1840 if (cmd_sts & ETH_ERROR_SUMMARY) {
1841 printk("%s: Error in TX\n", dev->name);
1842 dev->stats.tx_errors++;
1845 spin_unlock_irqrestore(&mp->lock, flags);
1847 if (cmd_sts & ETH_TX_FIRST_DESC)
1848 dma_unmap_single(NULL, addr, count, DMA_TO_DEVICE);
1850 dma_unmap_page(NULL, addr, count, DMA_TO_DEVICE);
1853 dev_kfree_skb_irq(skb);
1861 static void mv643xx_eth_free_completed_tx_descs(struct net_device *dev)
1863 struct mv643xx_private *mp = netdev_priv(dev);
1865 if (mv643xx_eth_free_tx_descs(dev, 0) &&
1866 mp->tx_ring_size - mp->tx_desc_count >= MAX_DESCS_PER_SKB)
1867 netif_wake_queue(dev);
1870 static void mv643xx_eth_free_all_tx_descs(struct net_device *dev)
1872 mv643xx_eth_free_tx_descs(dev, 1);
1875 static void mv643xx_eth_free_tx_rings(struct net_device *dev)
1877 struct mv643xx_private *mp = netdev_priv(dev);
1879 /* Stop Tx Queues */
1880 mv643xx_eth_port_disable_tx(mp);
1882 /* Free outstanding skb's on TX ring */
1883 mv643xx_eth_free_all_tx_descs(dev);
1885 BUG_ON(mp->tx_used_desc_q != mp->tx_curr_desc_q);
1888 if (mp->tx_sram_size)
1889 iounmap(mp->p_tx_desc_area);
1891 dma_free_coherent(NULL, mp->tx_desc_area_size,
1892 mp->p_tx_desc_area, mp->tx_desc_dma);
1896 /* netdev ops and related ***************************************************/
1897 static void eth_port_reset(struct mv643xx_private *mp);
1899 /* Set the mv643xx port configuration register for the speed/duplex mode. */
1900 static void mv643xx_eth_update_pscr(struct net_device *dev,
1901 struct ethtool_cmd *ecmd)
1903 struct mv643xx_private *mp = netdev_priv(dev);
1904 int port_num = mp->port_num;
1906 unsigned int queues;
1908 o_pscr = rdl(mp, PORT_SERIAL_CONTROL(port_num));
1911 /* clear speed, duplex and rx buffer size fields */
1912 n_pscr &= ~(SET_MII_SPEED_TO_100 |
1913 SET_GMII_SPEED_TO_1000 |
1914 SET_FULL_DUPLEX_MODE |
1915 MAX_RX_PACKET_MASK);
1917 if (ecmd->duplex == DUPLEX_FULL)
1918 n_pscr |= SET_FULL_DUPLEX_MODE;
1920 if (ecmd->speed == SPEED_1000)
1921 n_pscr |= SET_GMII_SPEED_TO_1000 |
1922 MAX_RX_PACKET_9700BYTE;
1924 if (ecmd->speed == SPEED_100)
1925 n_pscr |= SET_MII_SPEED_TO_100;
1926 n_pscr |= MAX_RX_PACKET_1522BYTE;
1929 if (n_pscr != o_pscr) {
1930 if ((o_pscr & SERIAL_PORT_ENABLE) == 0)
1931 wrl(mp, PORT_SERIAL_CONTROL(port_num), n_pscr);
1933 queues = mv643xx_eth_port_disable_tx(mp);
1935 o_pscr &= ~SERIAL_PORT_ENABLE;
1936 wrl(mp, PORT_SERIAL_CONTROL(port_num), o_pscr);
1937 wrl(mp, PORT_SERIAL_CONTROL(port_num), n_pscr);
1938 wrl(mp, PORT_SERIAL_CONTROL(port_num), n_pscr);
1940 mv643xx_eth_port_enable_tx(mp, queues);
1946 * mv643xx_eth_int_handler
1948 * Main interrupt handler for the gigbit ethernet ports
1950 * Input : irq - irq number (not used)
1951 * dev_id - a pointer to the required interface's data structure
1956 static irqreturn_t mv643xx_eth_int_handler(int irq, void *dev_id)
1958 struct net_device *dev = (struct net_device *)dev_id;
1959 struct mv643xx_private *mp = netdev_priv(dev);
1960 u32 eth_int_cause, eth_int_cause_ext = 0;
1961 unsigned int port_num = mp->port_num;
1963 /* Read interrupt cause registers */
1964 eth_int_cause = rdl(mp, INT_CAUSE(port_num)) & (INT_RX | INT_EXT);
1965 if (eth_int_cause & INT_EXT) {
1966 eth_int_cause_ext = rdl(mp, INT_CAUSE_EXT(port_num))
1967 & (INT_EXT_LINK | INT_EXT_PHY | INT_EXT_TX);
1968 wrl(mp, INT_CAUSE_EXT(port_num), ~eth_int_cause_ext);
1971 /* PHY status changed */
1972 if (eth_int_cause_ext & (INT_EXT_LINK | INT_EXT_PHY)) {
1973 struct ethtool_cmd cmd;
1975 if (mii_link_ok(&mp->mii)) {
1976 mii_ethtool_gset(&mp->mii, &cmd);
1977 mv643xx_eth_update_pscr(dev, &cmd);
1978 mv643xx_eth_port_enable_tx(mp, 1);
1979 if (!netif_carrier_ok(dev)) {
1980 netif_carrier_on(dev);
1981 if (mp->tx_ring_size - mp->tx_desc_count >=
1983 netif_wake_queue(dev);
1985 } else if (netif_carrier_ok(dev)) {
1986 netif_stop_queue(dev);
1987 netif_carrier_off(dev);
1992 if (eth_int_cause & INT_RX) {
1993 /* schedule the NAPI poll routine to maintain port */
1994 wrl(mp, INT_MASK(port_num), 0x00000000);
1996 /* wait for previous write to complete */
1997 rdl(mp, INT_MASK(port_num));
1999 netif_rx_schedule(dev, &mp->napi);
2002 if (eth_int_cause & INT_RX)
2003 mv643xx_eth_receive_queue(dev, INT_MAX);
2005 if (eth_int_cause_ext & INT_EXT_TX)
2006 mv643xx_eth_free_completed_tx_descs(dev);
2009 * If no real interrupt occured, exit.
2010 * This can happen when using gigE interrupt coalescing mechanism.
2012 if ((eth_int_cause == 0x0) && (eth_int_cause_ext == 0x0))
2019 * ethernet_phy_reset - Reset Ethernet port PHY.
2022 * This routine utilizes the SMI interface to reset the ethernet port PHY.
2025 * struct mv643xx_private *mp Ethernet Port.
2034 static void ethernet_phy_reset(struct mv643xx_private *mp)
2036 unsigned int phy_reg_data;
2039 eth_port_read_smi_reg(mp, 0, &phy_reg_data);
2040 phy_reg_data |= 0x8000; /* Set bit 15 to reset the PHY */
2041 eth_port_write_smi_reg(mp, 0, phy_reg_data);
2043 /* wait for PHY to come out of reset */
2046 eth_port_read_smi_reg(mp, 0, &phy_reg_data);
2047 } while (phy_reg_data & 0x8000);
2051 * eth_port_start - Start the Ethernet port activity.
2054 * This routine prepares the Ethernet port for Rx and Tx activity:
2055 * 1. Initialize Tx and Rx Current Descriptor Pointer for each queue that
2056 * has been initialized a descriptor's ring (using
2057 * ether_init_tx_desc_ring for Tx and ether_init_rx_desc_ring for Rx)
2058 * 2. Initialize and enable the Ethernet configuration port by writing to
2059 * the port's configuration and command registers.
2060 * 3. Initialize and enable the SDMA by writing to the SDMA's
2061 * configuration and command registers. After completing these steps,
2062 * the ethernet port SDMA can starts to perform Rx and Tx activities.
2064 * Note: Each Rx and Tx queue descriptor's list must be initialized prior
2065 * to calling this function (use ether_init_tx_desc_ring for Tx queues
2066 * and ether_init_rx_desc_ring for Rx queues).
2069 * dev - a pointer to the required interface
2072 * Ethernet port is ready to receive and transmit.
2077 static void eth_port_start(struct net_device *dev)
2079 struct mv643xx_private *mp = netdev_priv(dev);
2080 unsigned int port_num = mp->port_num;
2081 int tx_curr_desc, rx_curr_desc;
2083 struct ethtool_cmd ethtool_cmd;
2085 /* Assignment of Tx CTRP of given queue */
2086 tx_curr_desc = mp->tx_curr_desc_q;
2087 wrl(mp, TXQ_CURRENT_DESC_PTR(port_num),
2088 (u32)((struct eth_tx_desc *)mp->tx_desc_dma + tx_curr_desc));
2090 /* Assignment of Rx CRDP of given queue */
2091 rx_curr_desc = mp->rx_curr_desc_q;
2092 wrl(mp, RXQ_CURRENT_DESC_PTR(port_num),
2093 (u32)((struct eth_rx_desc *)mp->rx_desc_dma + rx_curr_desc));
2095 /* Add the assigned Ethernet address to the port's address table */
2096 eth_port_uc_addr_set(mp, dev->dev_addr);
2099 * Receive all unmatched unicast, TCP, UDP, BPDU and broadcast
2100 * frames to RX queue #0.
2102 wrl(mp, PORT_CONFIG(port_num), 0x00000000);
2105 * Treat BPDUs as normal multicasts, and disable partition mode.
2107 wrl(mp, PORT_CONFIG_EXT(port_num), 0x00000000);
2109 pscr = rdl(mp, PORT_SERIAL_CONTROL(port_num));
2111 pscr &= ~(SERIAL_PORT_ENABLE | FORCE_LINK_PASS);
2112 wrl(mp, PORT_SERIAL_CONTROL(port_num), pscr);
2114 pscr |= DISABLE_AUTO_NEG_FOR_FLOW_CTRL |
2115 DISABLE_AUTO_NEG_SPEED_GMII |
2116 DISABLE_AUTO_NEG_FOR_DUPLEX |
2117 DO_NOT_FORCE_LINK_FAIL |
2118 SERIAL_PORT_CONTROL_RESERVED;
2120 wrl(mp, PORT_SERIAL_CONTROL(port_num), pscr);
2122 pscr |= SERIAL_PORT_ENABLE;
2123 wrl(mp, PORT_SERIAL_CONTROL(port_num), pscr);
2125 /* Assign port SDMA configuration */
2126 wrl(mp, SDMA_CONFIG(port_num), PORT_SDMA_CONFIG_DEFAULT_VALUE);
2128 /* Enable port Rx. */
2129 mv643xx_eth_port_enable_rx(mp, 1);
2131 /* Disable port bandwidth limits by clearing MTU register */
2132 wrl(mp, TX_BW_MTU(port_num), 0);
2134 /* save phy settings across reset */
2135 mv643xx_get_settings(dev, ðtool_cmd);
2136 ethernet_phy_reset(mp);
2137 mv643xx_set_settings(dev, ðtool_cmd);
2143 * eth_port_set_rx_coal - Sets coalescing interrupt mechanism on RX path
2146 * This routine sets the RX coalescing interrupt mechanism parameter.
2147 * This parameter is a timeout counter, that counts in 64 t_clk
2148 * chunks ; that when timeout event occurs a maskable interrupt
2150 * The parameter is calculated using the tClk of the MV-643xx chip
2151 * , and the required delay of the interrupt in usec.
2154 * struct mv643xx_private *mp Ethernet port
2155 * unsigned int delay Delay in usec
2158 * Interrupt coalescing mechanism value is set in MV-643xx chip.
2161 * The interrupt coalescing value set in the gigE port.
2164 static unsigned int eth_port_set_rx_coal(struct mv643xx_private *mp,
2167 unsigned int port_num = mp->port_num;
2168 unsigned int coal = ((mp->shared->t_clk / 1000000) * delay) / 64;
2170 /* Set RX Coalescing mechanism */
2171 wrl(mp, SDMA_CONFIG(port_num),
2172 ((coal & 0x3fff) << 8) |
2173 (rdl(mp, SDMA_CONFIG(port_num))
2181 * eth_port_set_tx_coal - Sets coalescing interrupt mechanism on TX path
2184 * This routine sets the TX coalescing interrupt mechanism parameter.
2185 * This parameter is a timeout counter, that counts in 64 t_clk
2186 * chunks ; that when timeout event occurs a maskable interrupt
2188 * The parameter is calculated using the t_cLK frequency of the
2189 * MV-643xx chip and the required delay in the interrupt in uSec
2192 * struct mv643xx_private *mp Ethernet port
2193 * unsigned int delay Delay in uSeconds
2196 * Interrupt coalescing mechanism value is set in MV-643xx chip.
2199 * The interrupt coalescing value set in the gigE port.
2202 static unsigned int eth_port_set_tx_coal(struct mv643xx_private *mp,
2205 unsigned int coal = ((mp->shared->t_clk / 1000000) * delay) / 64;
2207 /* Set TX Coalescing mechanism */
2208 wrl(mp, TX_FIFO_URGENT_THRESHOLD(mp->port_num), coal << 4);
2214 * eth_port_init - Initialize the Ethernet port driver
2217 * This function prepares the ethernet port to start its activity:
2218 * 1) Completes the ethernet port driver struct initialization toward port
2220 * 2) Resets the device to a quiescent state in case of warm reboot.
2221 * 3) Enable SDMA access to all four DRAM banks as well as internal SRAM.
2222 * 4) Clean MAC tables. The reset status of those tables is unknown.
2223 * 5) Set PHY address.
2224 * Note: Call this routine prior to eth_port_start routine and after
2225 * setting user values in the user fields of Ethernet port control
2229 * struct mv643xx_private *mp Ethernet port control struct
2237 static void eth_port_init(struct mv643xx_private *mp)
2239 mp->rx_resource_err = 0;
2243 eth_port_init_mac_tables(mp);
2249 * This function is called when openning the network device. The function
2250 * should initialize all the hardware, initialize cyclic Rx/Tx
2251 * descriptors chain and buffers and allocate an IRQ to the network
2254 * Input : a pointer to the network device structure
2256 * Output : zero of success , nonzero if fails.
2259 static int mv643xx_eth_open(struct net_device *dev)
2261 struct mv643xx_private *mp = netdev_priv(dev);
2262 unsigned int port_num = mp->port_num;
2266 /* Clear any pending ethernet port interrupts */
2267 wrl(mp, INT_CAUSE(port_num), 0);
2268 wrl(mp, INT_CAUSE_EXT(port_num), 0);
2269 /* wait for previous write to complete */
2270 rdl(mp, INT_CAUSE_EXT(port_num));
2272 err = request_irq(dev->irq, mv643xx_eth_int_handler,
2273 IRQF_SHARED | IRQF_SAMPLE_RANDOM, dev->name, dev);
2275 printk(KERN_ERR "%s: Can not assign IRQ\n", dev->name);
2281 memset(&mp->timeout, 0, sizeof(struct timer_list));
2282 mp->timeout.function = mv643xx_eth_rx_refill_descs_timer_wrapper;
2283 mp->timeout.data = (unsigned long)dev;
2285 /* Allocate RX and TX skb rings */
2286 mp->rx_skb = kmalloc(sizeof(*mp->rx_skb) * mp->rx_ring_size,
2289 printk(KERN_ERR "%s: Cannot allocate Rx skb ring\n", dev->name);
2293 mp->tx_skb = kmalloc(sizeof(*mp->tx_skb) * mp->tx_ring_size,
2296 printk(KERN_ERR "%s: Cannot allocate Tx skb ring\n", dev->name);
2298 goto out_free_rx_skb;
2301 /* Allocate TX ring */
2302 mp->tx_desc_count = 0;
2303 size = mp->tx_ring_size * sizeof(struct eth_tx_desc);
2304 mp->tx_desc_area_size = size;
2306 if (mp->tx_sram_size) {
2307 mp->p_tx_desc_area = ioremap(mp->tx_sram_addr,
2309 mp->tx_desc_dma = mp->tx_sram_addr;
2311 mp->p_tx_desc_area = dma_alloc_coherent(NULL, size,
2315 if (!mp->p_tx_desc_area) {
2316 printk(KERN_ERR "%s: Cannot allocate Tx Ring (size %d bytes)\n",
2319 goto out_free_tx_skb;
2321 BUG_ON((u32) mp->p_tx_desc_area & 0xf); /* check 16-byte alignment */
2322 memset((void *)mp->p_tx_desc_area, 0, mp->tx_desc_area_size);
2324 ether_init_tx_desc_ring(mp);
2326 /* Allocate RX ring */
2327 mp->rx_desc_count = 0;
2328 size = mp->rx_ring_size * sizeof(struct eth_rx_desc);
2329 mp->rx_desc_area_size = size;
2331 if (mp->rx_sram_size) {
2332 mp->p_rx_desc_area = ioremap(mp->rx_sram_addr,
2334 mp->rx_desc_dma = mp->rx_sram_addr;
2336 mp->p_rx_desc_area = dma_alloc_coherent(NULL, size,
2340 if (!mp->p_rx_desc_area) {
2341 printk(KERN_ERR "%s: Cannot allocate Rx ring (size %d bytes)\n",
2343 printk(KERN_ERR "%s: Freeing previously allocated TX queues...",
2345 if (mp->rx_sram_size)
2346 iounmap(mp->p_tx_desc_area);
2348 dma_free_coherent(NULL, mp->tx_desc_area_size,
2349 mp->p_tx_desc_area, mp->tx_desc_dma);
2351 goto out_free_tx_skb;
2353 memset((void *)mp->p_rx_desc_area, 0, size);
2355 ether_init_rx_desc_ring(mp);
2357 mv643xx_eth_rx_refill_descs(dev); /* Fill RX ring with skb's */
2360 napi_enable(&mp->napi);
2363 eth_port_start(dev);
2365 /* Interrupt Coalescing */
2369 eth_port_set_rx_coal(mp, MV643XX_RX_COAL);
2373 eth_port_set_tx_coal(mp, MV643XX_TX_COAL);
2375 /* Unmask phy and link status changes interrupts */
2376 wrl(mp, INT_MASK_EXT(port_num), INT_EXT_LINK | INT_EXT_PHY | INT_EXT_TX);
2378 /* Unmask RX buffer and TX end interrupt */
2379 wrl(mp, INT_MASK(port_num), INT_RX | INT_EXT);
2388 free_irq(dev->irq, dev);
2394 * eth_port_reset - Reset Ethernet port
2397 * This routine resets the chip by aborting any SDMA engine activity and
2398 * clearing the MIB counters. The Receiver and the Transmit unit are in
2399 * idle state after this command is performed and the port is disabled.
2402 * struct mv643xx_private *mp Ethernet Port.
2405 * Channel activity is halted.
2411 static void eth_port_reset(struct mv643xx_private *mp)
2413 unsigned int port_num = mp->port_num;
2414 unsigned int reg_data;
2416 mv643xx_eth_port_disable_tx(mp);
2417 mv643xx_eth_port_disable_rx(mp);
2419 /* Clear all MIB counters */
2420 eth_clear_mib_counters(mp);
2422 /* Reset the Enable bit in the Configuration Register */
2423 reg_data = rdl(mp, PORT_SERIAL_CONTROL(port_num));
2424 reg_data &= ~(SERIAL_PORT_ENABLE |
2425 DO_NOT_FORCE_LINK_FAIL |
2427 wrl(mp, PORT_SERIAL_CONTROL(port_num), reg_data);
2433 * This function is used when closing the network device.
2434 * It updates the hardware,
2435 * release all memory that holds buffers and descriptors and release the IRQ.
2436 * Input : a pointer to the device structure
2437 * Output : zero if success , nonzero if fails
2440 static int mv643xx_eth_stop(struct net_device *dev)
2442 struct mv643xx_private *mp = netdev_priv(dev);
2443 unsigned int port_num = mp->port_num;
2445 /* Mask all interrupts on ethernet port */
2446 wrl(mp, INT_MASK(port_num), 0x00000000);
2447 /* wait for previous write to complete */
2448 rdl(mp, INT_MASK(port_num));
2451 napi_disable(&mp->napi);
2453 netif_carrier_off(dev);
2454 netif_stop_queue(dev);
2458 mv643xx_eth_free_tx_rings(dev);
2459 mv643xx_eth_free_rx_rings(dev);
2461 free_irq(dev->irq, dev);
2466 static int mv643xx_eth_do_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
2468 struct mv643xx_private *mp = netdev_priv(dev);
2470 return generic_mii_ioctl(&mp->mii, if_mii(ifr), cmd, NULL);
2474 * Changes MTU (maximum transfer unit) of the gigabit ethenret port
2476 * Input : pointer to ethernet interface network device structure
2478 * Output : 0 upon success, -EINVAL upon failure
2480 static int mv643xx_eth_change_mtu(struct net_device *dev, int new_mtu)
2482 if ((new_mtu > 9500) || (new_mtu < 64))
2486 if (!netif_running(dev))
2490 * Stop and then re-open the interface. This will allocate RX
2491 * skbs of the new MTU.
2492 * There is a possible danger that the open will not succeed,
2493 * due to memory being full, which might fail the open function.
2495 mv643xx_eth_stop(dev);
2496 if (mv643xx_eth_open(dev)) {
2497 printk(KERN_ERR "%s: Fatal error on opening device\n",
2505 * mv643xx_eth_tx_timeout_task
2507 * Actual routine to reset the adapter when a timeout on Tx has occurred
2509 static void mv643xx_eth_tx_timeout_task(struct work_struct *ugly)
2511 struct mv643xx_private *mp = container_of(ugly, struct mv643xx_private,
2513 struct net_device *dev = mp->dev;
2515 if (!netif_running(dev))
2518 netif_stop_queue(dev);
2521 eth_port_start(dev);
2523 if (mp->tx_ring_size - mp->tx_desc_count >= MAX_DESCS_PER_SKB)
2524 netif_wake_queue(dev);
2528 * mv643xx_eth_tx_timeout
2530 * Called upon a timeout on transmitting a packet
2532 * Input : pointer to ethernet interface network device structure.
2535 static void mv643xx_eth_tx_timeout(struct net_device *dev)
2537 struct mv643xx_private *mp = netdev_priv(dev);
2539 printk(KERN_INFO "%s: TX timeout ", dev->name);
2541 /* Do the reset outside of interrupt context */
2542 schedule_work(&mp->tx_timeout_task);
2545 #ifdef CONFIG_NET_POLL_CONTROLLER
2546 static void mv643xx_netpoll(struct net_device *netdev)
2548 struct mv643xx_private *mp = netdev_priv(netdev);
2549 int port_num = mp->port_num;
2551 wrl(mp, INT_MASK(port_num), 0x00000000);
2552 /* wait for previous write to complete */
2553 rdl(mp, INT_MASK(port_num));
2555 mv643xx_eth_int_handler(netdev->irq, netdev);
2557 wrl(mp, INT_MASK(port_num), INT_RX | INT_CAUSE_EXT);
2562 * Wrappers for MII support library.
2564 static int mv643xx_mdio_read(struct net_device *dev, int phy_id, int location)
2566 struct mv643xx_private *mp = netdev_priv(dev);
2569 eth_port_read_smi_reg(mp, location, &val);
2573 static void mv643xx_mdio_write(struct net_device *dev, int phy_id, int location, int val)
2575 struct mv643xx_private *mp = netdev_priv(dev);
2576 eth_port_write_smi_reg(mp, location, val);
2580 /* platform glue ************************************************************/
2581 static void mv643xx_eth_conf_mbus_windows(struct mv643xx_shared_private *msp,
2582 struct mbus_dram_target_info *dram)
2584 void __iomem *base = msp->eth_base;
2589 for (i = 0; i < 6; i++) {
2590 writel(0, base + WINDOW_BASE(i));
2591 writel(0, base + WINDOW_SIZE(i));
2593 writel(0, base + WINDOW_REMAP_HIGH(i));
2599 for (i = 0; i < dram->num_cs; i++) {
2600 struct mbus_dram_window *cs = dram->cs + i;
2602 writel((cs->base & 0xffff0000) |
2603 (cs->mbus_attr << 8) |
2604 dram->mbus_dram_target_id, base + WINDOW_BASE(i));
2605 writel((cs->size - 1) & 0xffff0000, base + WINDOW_SIZE(i));
2607 win_enable &= ~(1 << i);
2608 win_protect |= 3 << (2 * i);
2611 writel(win_enable, base + WINDOW_BAR_ENABLE);
2612 msp->win_protect = win_protect;
2615 static int mv643xx_eth_shared_probe(struct platform_device *pdev)
2617 static int mv643xx_version_printed = 0;
2618 struct mv643xx_eth_shared_platform_data *pd = pdev->dev.platform_data;
2619 struct mv643xx_shared_private *msp;
2620 struct resource *res;
2623 if (!mv643xx_version_printed++)
2624 printk(KERN_NOTICE "MV-643xx 10/100/1000 Ethernet Driver\n");
2627 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2632 msp = kmalloc(sizeof(*msp), GFP_KERNEL);
2635 memset(msp, 0, sizeof(*msp));
2637 msp->eth_base = ioremap(res->start, res->end - res->start + 1);
2638 if (msp->eth_base == NULL)
2641 spin_lock_init(&msp->phy_lock);
2642 msp->t_clk = (pd != NULL && pd->t_clk != 0) ? pd->t_clk : 133000000;
2644 platform_set_drvdata(pdev, msp);
2647 * (Re-)program MBUS remapping windows if we are asked to.
2649 if (pd != NULL && pd->dram != NULL)
2650 mv643xx_eth_conf_mbus_windows(msp, pd->dram);
2660 static int mv643xx_eth_shared_remove(struct platform_device *pdev)
2662 struct mv643xx_shared_private *msp = platform_get_drvdata(pdev);
2664 iounmap(msp->eth_base);
2670 static struct platform_driver mv643xx_eth_shared_driver = {
2671 .probe = mv643xx_eth_shared_probe,
2672 .remove = mv643xx_eth_shared_remove,
2674 .name = MV643XX_ETH_SHARED_NAME,
2675 .owner = THIS_MODULE,
2680 * ethernet_phy_set - Set the ethernet port PHY address.
2683 * This routine sets the given ethernet port PHY address.
2686 * struct mv643xx_private *mp Ethernet Port.
2687 * int phy_addr PHY address.
2696 static void ethernet_phy_set(struct mv643xx_private *mp, int phy_addr)
2699 int addr_shift = 5 * mp->port_num;
2701 reg_data = rdl(mp, PHY_ADDR);
2702 reg_data &= ~(0x1f << addr_shift);
2703 reg_data |= (phy_addr & 0x1f) << addr_shift;
2704 wrl(mp, PHY_ADDR, reg_data);
2708 * ethernet_phy_get - Get the ethernet port PHY address.
2711 * This routine returns the given ethernet port PHY address.
2714 * struct mv643xx_private *mp Ethernet Port.
2723 static int ethernet_phy_get(struct mv643xx_private *mp)
2725 unsigned int reg_data;
2727 reg_data = rdl(mp, PHY_ADDR);
2729 return ((reg_data >> (5 * mp->port_num)) & 0x1f);
2733 * ethernet_phy_detect - Detect whether a phy is present
2736 * This function tests whether there is a PHY present on
2737 * the specified port.
2740 * struct mv643xx_private *mp Ethernet Port.
2747 * -ENODEV on failure
2750 static int ethernet_phy_detect(struct mv643xx_private *mp)
2752 unsigned int phy_reg_data0;
2755 eth_port_read_smi_reg(mp, 0, &phy_reg_data0);
2756 auto_neg = phy_reg_data0 & 0x1000;
2757 phy_reg_data0 ^= 0x1000; /* invert auto_neg */
2758 eth_port_write_smi_reg(mp, 0, phy_reg_data0);
2760 eth_port_read_smi_reg(mp, 0, &phy_reg_data0);
2761 if ((phy_reg_data0 & 0x1000) == auto_neg)
2762 return -ENODEV; /* change didn't take */
2764 phy_reg_data0 ^= 0x1000;
2765 eth_port_write_smi_reg(mp, 0, phy_reg_data0);
2769 static void mv643xx_init_ethtool_cmd(struct net_device *dev, int phy_address,
2770 int speed, int duplex,
2771 struct ethtool_cmd *cmd)
2773 struct mv643xx_private *mp = netdev_priv(dev);
2775 memset(cmd, 0, sizeof(*cmd));
2777 cmd->port = PORT_MII;
2778 cmd->transceiver = XCVR_INTERNAL;
2779 cmd->phy_address = phy_address;
2782 cmd->autoneg = AUTONEG_ENABLE;
2783 /* mii lib checks, but doesn't use speed on AUTONEG_ENABLE */
2784 cmd->speed = SPEED_100;
2785 cmd->advertising = ADVERTISED_10baseT_Half |
2786 ADVERTISED_10baseT_Full |
2787 ADVERTISED_100baseT_Half |
2788 ADVERTISED_100baseT_Full;
2789 if (mp->mii.supports_gmii)
2790 cmd->advertising |= ADVERTISED_1000baseT_Full;
2792 cmd->autoneg = AUTONEG_DISABLE;
2794 cmd->duplex = duplex;
2801 * First function called after registering the network device.
2802 * It's purpose is to initialize the device as an ethernet device,
2803 * fill the ethernet device structure with pointers * to functions,
2804 * and set the MAC address of the interface
2806 * Input : struct device *
2807 * Output : -ENOMEM if failed , 0 if success
2809 static int mv643xx_eth_probe(struct platform_device *pdev)
2811 struct mv643xx_eth_platform_data *pd;
2813 struct mv643xx_private *mp;
2814 struct net_device *dev;
2816 struct resource *res;
2818 struct ethtool_cmd cmd;
2819 int duplex = DUPLEX_HALF;
2820 int speed = 0; /* default to auto-negotiation */
2821 DECLARE_MAC_BUF(mac);
2823 pd = pdev->dev.platform_data;
2825 printk(KERN_ERR "No mv643xx_eth_platform_data\n");
2829 if (pd->shared == NULL) {
2830 printk(KERN_ERR "No mv643xx_eth_platform_data->shared\n");
2834 dev = alloc_etherdev(sizeof(struct mv643xx_private));
2838 platform_set_drvdata(pdev, dev);
2840 mp = netdev_priv(dev);
2843 netif_napi_add(dev, &mp->napi, mv643xx_poll, 64);
2846 res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
2848 dev->irq = res->start;
2850 dev->open = mv643xx_eth_open;
2851 dev->stop = mv643xx_eth_stop;
2852 dev->hard_start_xmit = mv643xx_eth_start_xmit;
2853 dev->set_mac_address = mv643xx_eth_set_mac_address;
2854 dev->set_multicast_list = mv643xx_eth_set_rx_mode;
2856 /* No need to Tx Timeout */
2857 dev->tx_timeout = mv643xx_eth_tx_timeout;
2859 #ifdef CONFIG_NET_POLL_CONTROLLER
2860 dev->poll_controller = mv643xx_netpoll;
2863 dev->watchdog_timeo = 2 * HZ;
2865 dev->change_mtu = mv643xx_eth_change_mtu;
2866 dev->do_ioctl = mv643xx_eth_do_ioctl;
2867 SET_ETHTOOL_OPS(dev, &mv643xx_ethtool_ops);
2869 #ifdef MV643XX_CHECKSUM_OFFLOAD_TX
2870 #ifdef MAX_SKB_FRAGS
2872 * Zero copy can only work if we use Discovery II memory. Else, we will
2873 * have to map the buffers to ISA memory which is only 16 MB
2875 dev->features = NETIF_F_SG | NETIF_F_IP_CSUM;
2879 /* Configure the timeout task */
2880 INIT_WORK(&mp->tx_timeout_task, mv643xx_eth_tx_timeout_task);
2882 spin_lock_init(&mp->lock);
2884 mp->shared = platform_get_drvdata(pd->shared);
2885 port_num = mp->port_num = pd->port_number;
2887 if (mp->shared->win_protect)
2888 wrl(mp, WINDOW_PROTECT(port_num), mp->shared->win_protect);
2890 mp->shared_smi = mp->shared;
2891 if (pd->shared_smi != NULL)
2892 mp->shared_smi = platform_get_drvdata(pd->shared_smi);
2894 /* set default config values */
2895 eth_port_uc_addr_get(mp, dev->dev_addr);
2896 mp->rx_ring_size = PORT_DEFAULT_RECEIVE_QUEUE_SIZE;
2897 mp->tx_ring_size = PORT_DEFAULT_TRANSMIT_QUEUE_SIZE;
2899 if (is_valid_ether_addr(pd->mac_addr))
2900 memcpy(dev->dev_addr, pd->mac_addr, 6);
2902 if (pd->phy_addr || pd->force_phy_addr)
2903 ethernet_phy_set(mp, pd->phy_addr);
2905 if (pd->rx_queue_size)
2906 mp->rx_ring_size = pd->rx_queue_size;
2908 if (pd->tx_queue_size)
2909 mp->tx_ring_size = pd->tx_queue_size;
2911 if (pd->tx_sram_size) {
2912 mp->tx_sram_size = pd->tx_sram_size;
2913 mp->tx_sram_addr = pd->tx_sram_addr;
2916 if (pd->rx_sram_size) {
2917 mp->rx_sram_size = pd->rx_sram_size;
2918 mp->rx_sram_addr = pd->rx_sram_addr;
2921 duplex = pd->duplex;
2924 /* Hook up MII support for ethtool */
2926 mp->mii.mdio_read = mv643xx_mdio_read;
2927 mp->mii.mdio_write = mv643xx_mdio_write;
2928 mp->mii.phy_id = ethernet_phy_get(mp);
2929 mp->mii.phy_id_mask = 0x3f;
2930 mp->mii.reg_num_mask = 0x1f;
2932 err = ethernet_phy_detect(mp);
2934 pr_debug("%s: No PHY detected at addr %d\n",
2935 dev->name, ethernet_phy_get(mp));
2939 ethernet_phy_reset(mp);
2940 mp->mii.supports_gmii = mii_check_gmii_support(&mp->mii);
2941 mv643xx_init_ethtool_cmd(dev, mp->mii.phy_id, speed, duplex, &cmd);
2942 mv643xx_eth_update_pscr(dev, &cmd);
2943 mv643xx_set_settings(dev, &cmd);
2945 SET_NETDEV_DEV(dev, &pdev->dev);
2946 err = register_netdev(dev);
2952 "%s: port %d with MAC address %s\n",
2953 dev->name, port_num, print_mac(mac, p));
2955 if (dev->features & NETIF_F_SG)
2956 printk(KERN_NOTICE "%s: Scatter Gather Enabled\n", dev->name);
2958 if (dev->features & NETIF_F_IP_CSUM)
2959 printk(KERN_NOTICE "%s: TX TCP/IP Checksumming Supported\n",
2962 #ifdef MV643XX_CHECKSUM_OFFLOAD_TX
2963 printk(KERN_NOTICE "%s: RX TCP/UDP Checksum Offload ON \n", dev->name);
2967 printk(KERN_NOTICE "%s: TX and RX Interrupt Coalescing ON \n",
2972 printk(KERN_NOTICE "%s: RX NAPI Enabled \n", dev->name);
2975 if (mp->tx_sram_size > 0)
2976 printk(KERN_NOTICE "%s: Using SRAM\n", dev->name);
2986 static int mv643xx_eth_remove(struct platform_device *pdev)
2988 struct net_device *dev = platform_get_drvdata(pdev);
2990 unregister_netdev(dev);
2991 flush_scheduled_work();
2994 platform_set_drvdata(pdev, NULL);
2998 static void mv643xx_eth_shutdown(struct platform_device *pdev)
3000 struct net_device *dev = platform_get_drvdata(pdev);
3001 struct mv643xx_private *mp = netdev_priv(dev);
3002 unsigned int port_num = mp->port_num;
3004 /* Mask all interrupts on ethernet port */
3005 wrl(mp, INT_MASK(port_num), 0);
3006 rdl(mp, INT_MASK(port_num));
3011 static struct platform_driver mv643xx_eth_driver = {
3012 .probe = mv643xx_eth_probe,
3013 .remove = mv643xx_eth_remove,
3014 .shutdown = mv643xx_eth_shutdown,
3016 .name = MV643XX_ETH_NAME,
3017 .owner = THIS_MODULE,
3022 * mv643xx_init_module
3024 * Registers the network drivers into the Linux kernel
3030 static int __init mv643xx_init_module(void)
3034 rc = platform_driver_register(&mv643xx_eth_shared_driver);
3036 rc = platform_driver_register(&mv643xx_eth_driver);
3038 platform_driver_unregister(&mv643xx_eth_shared_driver);
3044 * mv643xx_cleanup_module
3046 * Registers the network drivers into the Linux kernel
3052 static void __exit mv643xx_cleanup_module(void)
3054 platform_driver_unregister(&mv643xx_eth_driver);
3055 platform_driver_unregister(&mv643xx_eth_shared_driver);
3058 module_init(mv643xx_init_module);
3059 module_exit(mv643xx_cleanup_module);
3061 MODULE_LICENSE("GPL");
3062 MODULE_AUTHOR( "Rabeeh Khoury, Assaf Hoffman, Matthew Dharm, Manish Lachwani"
3063 " and Dale Farnsworth");
3064 MODULE_DESCRIPTION("Ethernet driver for Marvell MV643XX");
3065 MODULE_ALIAS("platform:" MV643XX_ETH_NAME);
3066 MODULE_ALIAS("platform:" MV643XX_ETH_SHARED_NAME);