2 * drivers/net/mv643xx_eth.c - Driver for MV643XX ethernet ports
3 * Copyright (C) 2002 Matthew Dharm <mdharm@momenco.com>
5 * Based on the 64360 driver from:
6 * Copyright (C) 2002 rabeeh@galileo.co.il
8 * Copyright (C) 2003 PMC-Sierra, Inc.,
9 * written by Manish Lachwani
11 * Copyright (C) 2003 Ralf Baechle <ralf@linux-mips.org>
13 * Copyright (C) 2004-2006 MontaVista Software, Inc.
14 * Dale Farnsworth <dale@farnsworth.org>
16 * Copyright (C) 2004 Steven J. Hill <sjhill1@rockwellcollins.com>
17 * <sjhill@realitydiluted.com>
19 * This program is free software; you can redistribute it and/or
20 * modify it under the terms of the GNU General Public License
21 * as published by the Free Software Foundation; either version 2
22 * of the License, or (at your option) any later version.
24 * This program is distributed in the hope that it will be useful,
25 * but WITHOUT ANY WARRANTY; without even the implied warranty of
26 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
27 * GNU General Public License for more details.
29 * You should have received a copy of the GNU General Public License
30 * along with this program; if not, write to the Free Software
31 * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
33 #include <linux/init.h>
34 #include <linux/dma-mapping.h>
37 #include <linux/tcp.h>
38 #include <linux/udp.h>
39 #include <linux/etherdevice.h>
41 #include <linux/bitops.h>
42 #include <linux/delay.h>
43 #include <linux/ethtool.h>
44 #include <linux/platform_device.h>
47 #include <asm/types.h>
48 #include <asm/pgtable.h>
49 #include <asm/system.h>
50 #include <asm/delay.h>
51 #include "mv643xx_eth.h"
54 * The first part is the high level driver of the gigE ethernet ports.
60 #define DMA_ALIGN 8 /* hw requires 8-byte alignment */
61 #define HW_IP_ALIGN 2 /* hw aligns IP header */
62 #define WRAP HW_IP_ALIGN + ETH_HLEN + VLAN_HLEN + FCS_LEN
63 #define RX_SKB_SIZE ((dev->mtu + WRAP + 7) & ~0x7)
65 #define INT_UNMASK_ALL 0x0007ffff
66 #define INT_UNMASK_ALL_EXT 0x0011ffff
67 #define INT_MASK_ALL 0x00000000
68 #define INT_MASK_ALL_EXT 0x00000000
69 #define INT_CAUSE_CHECK_BITS INT_CAUSE_UNMASK_ALL
70 #define INT_CAUSE_CHECK_BITS_EXT INT_CAUSE_UNMASK_ALL_EXT
72 #ifdef MV643XX_CHECKSUM_OFFLOAD_TX
73 #define MAX_DESCS_PER_SKB (MAX_SKB_FRAGS + 1)
75 #define MAX_DESCS_PER_SKB 1
78 #define PHY_WAIT_ITERATIONS 1000 /* 1000 iterations * 10uS = 10mS max */
79 #define PHY_WAIT_MICRO_SECONDS 10
81 /* Static function declarations */
82 static void eth_port_uc_addr_get(struct net_device *dev,
83 unsigned char *MacAddr);
84 static void eth_port_set_multicast_list(struct net_device *);
85 static void mv643xx_eth_port_enable_tx(unsigned int port_num,
87 static void mv643xx_eth_port_enable_rx(unsigned int port_num,
89 static unsigned int mv643xx_eth_port_disable_tx(unsigned int port_num);
90 static unsigned int mv643xx_eth_port_disable_rx(unsigned int port_num);
91 static int mv643xx_eth_open(struct net_device *);
92 static int mv643xx_eth_stop(struct net_device *);
93 static int mv643xx_eth_change_mtu(struct net_device *, int);
94 static struct net_device_stats *mv643xx_eth_get_stats(struct net_device *);
95 static void eth_port_init_mac_tables(unsigned int eth_port_num);
97 static int mv643xx_poll(struct net_device *dev, int *budget);
99 static int ethernet_phy_get(unsigned int eth_port_num);
100 static void ethernet_phy_set(unsigned int eth_port_num, int phy_addr);
101 static int ethernet_phy_detect(unsigned int eth_port_num);
102 static int mv643xx_mdio_read(struct net_device *dev, int phy_id, int location);
103 static void mv643xx_mdio_write(struct net_device *dev, int phy_id, int location, int val);
104 static int mv643xx_eth_do_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd);
105 static struct ethtool_ops mv643xx_ethtool_ops;
107 static char mv643xx_driver_name[] = "mv643xx_eth";
108 static char mv643xx_driver_version[] = "1.0";
110 static void __iomem *mv643xx_eth_shared_base;
112 /* used to protect MV643XX_ETH_SMI_REG, which is shared across ports */
113 static DEFINE_SPINLOCK(mv643xx_eth_phy_lock);
115 static inline u32 mv_read(int offset)
117 void __iomem *reg_base;
119 reg_base = mv643xx_eth_shared_base - MV643XX_ETH_SHARED_REGS;
121 return readl(reg_base + offset);
124 static inline void mv_write(int offset, u32 data)
126 void __iomem *reg_base;
128 reg_base = mv643xx_eth_shared_base - MV643XX_ETH_SHARED_REGS;
129 writel(data, reg_base + offset);
133 * Changes MTU (maximum transfer unit) of the gigabit ethenret port
135 * Input : pointer to ethernet interface network device structure
137 * Output : 0 upon success, -EINVAL upon failure
139 static int mv643xx_eth_change_mtu(struct net_device *dev, int new_mtu)
141 if ((new_mtu > 9500) || (new_mtu < 64))
146 * Stop then re-open the interface. This will allocate RX skb's with
148 * There is a possible danger that the open will not successed, due
149 * to memory is full, which might fail the open function.
151 if (netif_running(dev)) {
152 mv643xx_eth_stop(dev);
153 if (mv643xx_eth_open(dev))
155 "%s: Fatal error on opening device\n",
163 * mv643xx_eth_rx_task
165 * Fills / refills RX queue on a certain gigabit ethernet port
167 * Input : pointer to ethernet interface network device structure
170 static void mv643xx_eth_rx_task(void *data)
172 struct net_device *dev = (struct net_device *)data;
173 struct mv643xx_private *mp = netdev_priv(dev);
174 struct pkt_info pkt_info;
178 if (test_and_set_bit(0, &mp->rx_task_busy))
179 panic("%s: Error in test_set_bit / clear_bit", dev->name);
181 while (mp->rx_desc_count < (mp->rx_ring_size - 5)) {
182 skb = dev_alloc_skb(RX_SKB_SIZE + DMA_ALIGN);
186 unaligned = (u32)skb->data & (DMA_ALIGN - 1);
188 skb_reserve(skb, DMA_ALIGN - unaligned);
189 pkt_info.cmd_sts = ETH_RX_ENABLE_INTERRUPT;
190 pkt_info.byte_cnt = RX_SKB_SIZE;
191 pkt_info.buf_ptr = dma_map_single(NULL, skb->data, RX_SKB_SIZE,
193 pkt_info.return_info = skb;
194 if (eth_rx_return_buff(mp, &pkt_info) != ETH_OK) {
196 "%s: Error allocating RX Ring\n", dev->name);
199 skb_reserve(skb, HW_IP_ALIGN);
201 clear_bit(0, &mp->rx_task_busy);
203 * If RX ring is empty of SKB, set a timer to try allocating
204 * again in a later time .
206 if ((mp->rx_desc_count == 0) && (mp->rx_timer_flag == 0)) {
207 printk(KERN_INFO "%s: Rx ring is empty\n", dev->name);
209 mp->timeout.expires = jiffies + (HZ / 10);
210 add_timer(&mp->timeout);
211 mp->rx_timer_flag = 1;
213 #ifdef MV643XX_RX_QUEUE_FILL_ON_TASK
215 /* Return interrupts */
216 mv_write(MV643XX_ETH_INTERRUPT_MASK_REG(mp->port_num),
223 * mv643xx_eth_rx_task_timer_wrapper
225 * Timer routine to wake up RX queue filling task. This function is
226 * used only in case the RX queue is empty, and all alloc_skb has
227 * failed (due to out of memory event).
229 * Input : pointer to ethernet interface network device structure
232 static void mv643xx_eth_rx_task_timer_wrapper(unsigned long data)
234 struct net_device *dev = (struct net_device *)data;
235 struct mv643xx_private *mp = netdev_priv(dev);
237 mp->rx_timer_flag = 0;
238 mv643xx_eth_rx_task((void *)data);
242 * mv643xx_eth_update_mac_address
244 * Update the MAC address of the port in the address table
246 * Input : pointer to ethernet interface network device structure
249 static void mv643xx_eth_update_mac_address(struct net_device *dev)
251 struct mv643xx_private *mp = netdev_priv(dev);
252 unsigned int port_num = mp->port_num;
254 eth_port_init_mac_tables(port_num);
255 eth_port_uc_addr_set(port_num, dev->dev_addr);
259 * mv643xx_eth_set_rx_mode
261 * Change from promiscuos to regular rx mode
263 * Input : pointer to ethernet interface network device structure
266 static void mv643xx_eth_set_rx_mode(struct net_device *dev)
268 struct mv643xx_private *mp = netdev_priv(dev);
271 config_reg = mv_read(MV643XX_ETH_PORT_CONFIG_REG(mp->port_num));
272 if (dev->flags & IFF_PROMISC)
273 config_reg |= (u32) MV643XX_ETH_UNICAST_PROMISCUOUS_MODE;
275 config_reg &= ~(u32) MV643XX_ETH_UNICAST_PROMISCUOUS_MODE;
276 mv_write(MV643XX_ETH_PORT_CONFIG_REG(mp->port_num), config_reg);
278 eth_port_set_multicast_list(dev);
282 * mv643xx_eth_set_mac_address
284 * Change the interface's mac address.
285 * No special hardware thing should be done because interface is always
286 * put in promiscuous mode.
288 * Input : pointer to ethernet interface network device structure and
289 * a pointer to the designated entry to be added to the cache.
290 * Output : zero upon success, negative upon failure
292 static int mv643xx_eth_set_mac_address(struct net_device *dev, void *addr)
296 for (i = 0; i < 6; i++)
297 /* +2 is for the offset of the HW addr type */
298 dev->dev_addr[i] = ((unsigned char *)addr)[i + 2];
299 mv643xx_eth_update_mac_address(dev);
304 * mv643xx_eth_tx_timeout
306 * Called upon a timeout on transmitting a packet
308 * Input : pointer to ethernet interface network device structure.
311 static void mv643xx_eth_tx_timeout(struct net_device *dev)
313 struct mv643xx_private *mp = netdev_priv(dev);
315 printk(KERN_INFO "%s: TX timeout ", dev->name);
317 /* Do the reset outside of interrupt context */
318 schedule_work(&mp->tx_timeout_task);
322 * mv643xx_eth_tx_timeout_task
324 * Actual routine to reset the adapter when a timeout on Tx has occurred
326 static void mv643xx_eth_tx_timeout_task(struct net_device *dev)
328 struct mv643xx_private *mp = netdev_priv(dev);
330 netif_device_detach(dev);
331 eth_port_reset(mp->port_num);
333 netif_device_attach(dev);
337 * mv643xx_eth_free_tx_queue
339 * Input : dev - a pointer to the required interface
341 * Output : 0 if was able to release skb , nonzero otherwise
343 static int mv643xx_eth_free_tx_queue(struct net_device *dev,
344 unsigned int eth_int_cause_ext)
346 struct mv643xx_private *mp = netdev_priv(dev);
347 struct net_device_stats *stats = &mp->stats;
348 struct pkt_info pkt_info;
351 if (!(eth_int_cause_ext & (BIT0 | BIT8)))
354 /* Check only queue 0 */
355 while (eth_tx_return_desc(mp, &pkt_info) == ETH_OK) {
356 if (pkt_info.cmd_sts & BIT0) {
357 printk("%s: Error in TX\n", dev->name);
361 if (pkt_info.cmd_sts & ETH_TX_FIRST_DESC)
362 dma_unmap_single(NULL, pkt_info.buf_ptr,
366 dma_unmap_page(NULL, pkt_info.buf_ptr,
370 if (pkt_info.return_info) {
371 dev_kfree_skb_irq(pkt_info.return_info);
380 * mv643xx_eth_receive
382 * This function is forward packets that are received from the port's
383 * queues toward kernel core or FastRoute them to another interface.
385 * Input : dev - a pointer to the required interface
386 * max - maximum number to receive (0 means unlimted)
388 * Output : number of served packets
391 static int mv643xx_eth_receive_queue(struct net_device *dev, int budget)
393 static int mv643xx_eth_receive_queue(struct net_device *dev)
396 struct mv643xx_private *mp = netdev_priv(dev);
397 struct net_device_stats *stats = &mp->stats;
398 unsigned int received_packets = 0;
400 struct pkt_info pkt_info;
403 while (budget-- > 0 && eth_port_receive(mp, &pkt_info) == ETH_OK) {
405 while (eth_port_receive(mp, &pkt_info) == ETH_OK) {
410 /* Update statistics. Note byte count includes 4 byte CRC count */
412 stats->rx_bytes += pkt_info.byte_cnt;
413 skb = pkt_info.return_info;
415 * In case received a packet without first / last bits on OR
416 * the error summary bit is on, the packets needs to be dropeed.
418 if (((pkt_info.cmd_sts
419 & (ETH_RX_FIRST_DESC | ETH_RX_LAST_DESC)) !=
420 (ETH_RX_FIRST_DESC | ETH_RX_LAST_DESC))
421 || (pkt_info.cmd_sts & ETH_ERROR_SUMMARY)) {
423 if ((pkt_info.cmd_sts & (ETH_RX_FIRST_DESC |
424 ETH_RX_LAST_DESC)) !=
425 (ETH_RX_FIRST_DESC | ETH_RX_LAST_DESC)) {
428 "%s: Received packet spread "
429 "on multiple descriptors\n",
432 if (pkt_info.cmd_sts & ETH_ERROR_SUMMARY)
435 dev_kfree_skb_irq(skb);
438 * The -4 is for the CRC in the trailer of the
441 skb_put(skb, pkt_info.byte_cnt - 4);
444 if (pkt_info.cmd_sts & ETH_LAYER_4_CHECKSUM_OK) {
445 skb->ip_summed = CHECKSUM_UNNECESSARY;
447 (pkt_info.cmd_sts & 0x0007fff8) >> 3);
449 skb->protocol = eth_type_trans(skb, dev);
451 netif_receive_skb(skb);
456 dev->last_rx = jiffies;
459 return received_packets;
462 /* Set the mv643xx port configuration register for the speed/duplex mode. */
463 static void mv643xx_eth_update_pscr(struct net_device *dev,
464 struct ethtool_cmd *ecmd)
466 struct mv643xx_private *mp = netdev_priv(dev);
467 int port_num = mp->port_num;
471 o_pscr = mv_read(MV643XX_ETH_PORT_SERIAL_CONTROL_REG(port_num));
474 /* clear speed, duplex and rx buffer size fields */
475 n_pscr &= ~(MV643XX_ETH_SET_MII_SPEED_TO_100 |
476 MV643XX_ETH_SET_GMII_SPEED_TO_1000 |
477 MV643XX_ETH_SET_FULL_DUPLEX_MODE |
478 MV643XX_ETH_MAX_RX_PACKET_MASK);
480 if (ecmd->duplex == DUPLEX_FULL)
481 n_pscr |= MV643XX_ETH_SET_FULL_DUPLEX_MODE;
483 if (ecmd->speed == SPEED_1000)
484 n_pscr |= MV643XX_ETH_SET_GMII_SPEED_TO_1000 |
485 MV643XX_ETH_MAX_RX_PACKET_9700BYTE;
487 if (ecmd->speed == SPEED_100)
488 n_pscr |= MV643XX_ETH_SET_MII_SPEED_TO_100;
489 n_pscr |= MV643XX_ETH_MAX_RX_PACKET_1522BYTE;
492 if (n_pscr != o_pscr) {
493 if ((o_pscr & MV643XX_ETH_SERIAL_PORT_ENABLE) == 0)
494 mv_write(MV643XX_ETH_PORT_SERIAL_CONTROL_REG(port_num),
497 queues = mv643xx_eth_port_disable_tx(port_num);
499 o_pscr &= ~MV643XX_ETH_SERIAL_PORT_ENABLE;
500 mv_write(MV643XX_ETH_PORT_SERIAL_CONTROL_REG(port_num),
502 mv_write(MV643XX_ETH_PORT_SERIAL_CONTROL_REG(port_num),
504 mv_write(MV643XX_ETH_PORT_SERIAL_CONTROL_REG(port_num),
507 mv643xx_eth_port_enable_tx(port_num, queues);
513 * mv643xx_eth_int_handler
515 * Main interrupt handler for the gigbit ethernet ports
517 * Input : irq - irq number (not used)
518 * dev_id - a pointer to the required interface's data structure
523 static irqreturn_t mv643xx_eth_int_handler(int irq, void *dev_id,
524 struct pt_regs *regs)
526 struct net_device *dev = (struct net_device *)dev_id;
527 struct mv643xx_private *mp = netdev_priv(dev);
528 u32 eth_int_cause, eth_int_cause_ext = 0;
529 unsigned int port_num = mp->port_num;
531 /* Read interrupt cause registers */
532 eth_int_cause = mv_read(MV643XX_ETH_INTERRUPT_CAUSE_REG(port_num)) &
535 if (eth_int_cause & BIT1)
536 eth_int_cause_ext = mv_read(
537 MV643XX_ETH_INTERRUPT_CAUSE_EXTEND_REG(port_num)) &
541 if (!(eth_int_cause & 0x0007fffd)) {
542 /* Dont ack the Rx interrupt */
545 * Clear specific ethernet port intrerrupt registers by
546 * acknowleding relevant bits.
548 mv_write(MV643XX_ETH_INTERRUPT_CAUSE_REG(port_num),
550 if (eth_int_cause_ext != 0x0)
551 mv_write(MV643XX_ETH_INTERRUPT_CAUSE_EXTEND_REG
552 (port_num), ~eth_int_cause_ext);
554 /* UDP change : We may need this */
555 if ((eth_int_cause_ext & 0x0000ffff) &&
556 (mv643xx_eth_free_tx_queue(dev, eth_int_cause_ext) == 0) &&
557 (mp->tx_ring_size - mp->tx_desc_count > MAX_DESCS_PER_SKB))
558 netif_wake_queue(dev);
561 if (netif_rx_schedule_prep(dev)) {
562 /* Mask all the interrupts */
563 mv_write(MV643XX_ETH_INTERRUPT_MASK_REG(port_num),
565 /* wait for previous write to complete */
566 mv_read(MV643XX_ETH_INTERRUPT_MASK_REG(port_num));
567 __netif_rx_schedule(dev);
570 if (eth_int_cause & (BIT2 | BIT11))
571 mv643xx_eth_receive_queue(dev, 0);
574 * After forwarded received packets to upper layer, add a task
575 * in an interrupts enabled context that refills the RX ring
578 #ifdef MV643XX_RX_QUEUE_FILL_ON_TASK
579 /* Mask all interrupts on ethernet port */
580 mv_write(MV643XX_ETH_INTERRUPT_MASK_REG(port_num),
582 /* wait for previous write to take effect */
583 mv_read(MV643XX_ETH_INTERRUPT_MASK_REG(port_num));
585 queue_task(&mp->rx_task, &tq_immediate);
586 mark_bh(IMMEDIATE_BH);
588 mp->rx_task.func(dev);
592 /* PHY status changed */
593 if (eth_int_cause_ext & (BIT16 | BIT20)) {
594 struct ethtool_cmd cmd;
596 if (mii_link_ok(&mp->mii)) {
597 mii_ethtool_gset(&mp->mii, &cmd);
598 mv643xx_eth_update_pscr(dev, &cmd);
599 if (!netif_carrier_ok(dev)) {
600 netif_carrier_on(dev);
601 if (mp->tx_ring_size - mp->tx_desc_count >
603 netif_wake_queue(dev);
605 mv643xx_eth_port_enable_tx(port_num, mp->port_tx_queue_command);
608 } else if (netif_carrier_ok(dev)) {
609 netif_stop_queue(dev);
610 netif_carrier_off(dev);
615 * If no real interrupt occured, exit.
616 * This can happen when using gigE interrupt coalescing mechanism.
618 if ((eth_int_cause == 0x0) && (eth_int_cause_ext == 0x0))
627 * eth_port_set_rx_coal - Sets coalescing interrupt mechanism on RX path
630 * This routine sets the RX coalescing interrupt mechanism parameter.
631 * This parameter is a timeout counter, that counts in 64 t_clk
632 * chunks ; that when timeout event occurs a maskable interrupt
634 * The parameter is calculated using the tClk of the MV-643xx chip
635 * , and the required delay of the interrupt in usec.
638 * unsigned int eth_port_num Ethernet port number
639 * unsigned int t_clk t_clk of the MV-643xx chip in HZ units
640 * unsigned int delay Delay in usec
643 * Interrupt coalescing mechanism value is set in MV-643xx chip.
646 * The interrupt coalescing value set in the gigE port.
649 static unsigned int eth_port_set_rx_coal(unsigned int eth_port_num,
650 unsigned int t_clk, unsigned int delay)
652 unsigned int coal = ((t_clk / 1000000) * delay) / 64;
654 /* Set RX Coalescing mechanism */
655 mv_write(MV643XX_ETH_SDMA_CONFIG_REG(eth_port_num),
656 ((coal & 0x3fff) << 8) |
657 (mv_read(MV643XX_ETH_SDMA_CONFIG_REG(eth_port_num))
665 * eth_port_set_tx_coal - Sets coalescing interrupt mechanism on TX path
668 * This routine sets the TX coalescing interrupt mechanism parameter.
669 * This parameter is a timeout counter, that counts in 64 t_clk
670 * chunks ; that when timeout event occurs a maskable interrupt
672 * The parameter is calculated using the t_cLK frequency of the
673 * MV-643xx chip and the required delay in the interrupt in uSec
676 * unsigned int eth_port_num Ethernet port number
677 * unsigned int t_clk t_clk of the MV-643xx chip in HZ units
678 * unsigned int delay Delay in uSeconds
681 * Interrupt coalescing mechanism value is set in MV-643xx chip.
684 * The interrupt coalescing value set in the gigE port.
687 static unsigned int eth_port_set_tx_coal(unsigned int eth_port_num,
688 unsigned int t_clk, unsigned int delay)
691 coal = ((t_clk / 1000000) * delay) / 64;
692 /* Set TX Coalescing mechanism */
693 mv_write(MV643XX_ETH_TX_FIFO_URGENT_THRESHOLD_REG(eth_port_num),
699 * ether_init_rx_desc_ring - Curve a Rx chain desc list and buffer in memory.
702 * This function prepares a Rx chained list of descriptors and packet
703 * buffers in a form of a ring. The routine must be called after port
704 * initialization routine and before port start routine.
705 * The Ethernet SDMA engine uses CPU bus addresses to access the various
706 * devices in the system (i.e. DRAM). This function uses the ethernet
707 * struct 'virtual to physical' routine (set by the user) to set the ring
708 * with physical addresses.
711 * struct mv643xx_private *mp Ethernet Port Control srtuct.
714 * The routine updates the Ethernet port control struct with information
715 * regarding the Rx descriptors and buffers.
720 static void ether_init_rx_desc_ring(struct mv643xx_private *mp)
722 volatile struct eth_rx_desc *p_rx_desc;
723 int rx_desc_num = mp->rx_ring_size;
726 /* initialize the next_desc_ptr links in the Rx descriptors ring */
727 p_rx_desc = (struct eth_rx_desc *)mp->p_rx_desc_area;
728 for (i = 0; i < rx_desc_num; i++) {
729 p_rx_desc[i].next_desc_ptr = mp->rx_desc_dma +
730 ((i + 1) % rx_desc_num) * sizeof(struct eth_rx_desc);
733 /* Save Rx desc pointer to driver struct. */
734 mp->rx_curr_desc_q = 0;
735 mp->rx_used_desc_q = 0;
737 mp->rx_desc_area_size = rx_desc_num * sizeof(struct eth_rx_desc);
739 /* Enable queue 0 for this port */
740 mp->port_rx_queue_command = 1;
744 * ether_init_tx_desc_ring - Curve a Tx chain desc list and buffer in memory.
747 * This function prepares a Tx chained list of descriptors and packet
748 * buffers in a form of a ring. The routine must be called after port
749 * initialization routine and before port start routine.
750 * The Ethernet SDMA engine uses CPU bus addresses to access the various
751 * devices in the system (i.e. DRAM). This function uses the ethernet
752 * struct 'virtual to physical' routine (set by the user) to set the ring
753 * with physical addresses.
756 * struct mv643xx_private *mp Ethernet Port Control srtuct.
759 * The routine updates the Ethernet port control struct with information
760 * regarding the Tx descriptors and buffers.
765 static void ether_init_tx_desc_ring(struct mv643xx_private *mp)
767 int tx_desc_num = mp->tx_ring_size;
768 struct eth_tx_desc *p_tx_desc;
771 /* Initialize the next_desc_ptr links in the Tx descriptors ring */
772 p_tx_desc = (struct eth_tx_desc *)mp->p_tx_desc_area;
773 for (i = 0; i < tx_desc_num; i++) {
774 p_tx_desc[i].next_desc_ptr = mp->tx_desc_dma +
775 ((i + 1) % tx_desc_num) * sizeof(struct eth_tx_desc);
778 mp->tx_curr_desc_q = 0;
779 mp->tx_used_desc_q = 0;
781 mp->tx_desc_area_size = tx_desc_num * sizeof(struct eth_tx_desc);
783 /* Enable queue 0 for this port */
784 mp->port_tx_queue_command = 1;
787 static int mv643xx_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
789 struct mv643xx_private *mp = netdev_priv(dev);
792 spin_lock_irq(&mp->lock);
793 err = mii_ethtool_sset(&mp->mii, cmd);
794 spin_unlock_irq(&mp->lock);
799 static int mv643xx_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
801 struct mv643xx_private *mp = netdev_priv(dev);
804 spin_lock_irq(&mp->lock);
805 err = mii_ethtool_gset(&mp->mii, cmd);
806 spin_unlock_irq(&mp->lock);
808 /* The PHY may support 1000baseT_Half, but the mv643xx does not */
809 cmd->supported &= ~SUPPORTED_1000baseT_Half;
810 cmd->advertising &= ~ADVERTISED_1000baseT_Half;
818 * This function is called when openning the network device. The function
819 * should initialize all the hardware, initialize cyclic Rx/Tx
820 * descriptors chain and buffers and allocate an IRQ to the network
823 * Input : a pointer to the network device structure
825 * Output : zero of success , nonzero if fails.
828 static int mv643xx_eth_open(struct net_device *dev)
830 struct mv643xx_private *mp = netdev_priv(dev);
831 unsigned int port_num = mp->port_num;
835 err = request_irq(dev->irq, mv643xx_eth_int_handler,
836 SA_SHIRQ | SA_SAMPLE_RANDOM, dev->name, dev);
838 printk(KERN_ERR "Can not assign IRQ number to MV643XX_eth%d\n",
845 INIT_WORK(&mp->rx_task, (void (*)(void *))mv643xx_eth_rx_task, dev);
847 memset(&mp->timeout, 0, sizeof(struct timer_list));
848 mp->timeout.function = mv643xx_eth_rx_task_timer_wrapper;
849 mp->timeout.data = (unsigned long)dev;
851 mp->rx_task_busy = 0;
852 mp->rx_timer_flag = 0;
854 /* Allocate RX and TX skb rings */
855 mp->rx_skb = kmalloc(sizeof(*mp->rx_skb) * mp->rx_ring_size,
858 printk(KERN_ERR "%s: Cannot allocate Rx skb ring\n", dev->name);
862 mp->tx_skb = kmalloc(sizeof(*mp->tx_skb) * mp->tx_ring_size,
865 printk(KERN_ERR "%s: Cannot allocate Tx skb ring\n", dev->name);
867 goto out_free_rx_skb;
870 /* Allocate TX ring */
871 mp->tx_desc_count = 0;
872 size = mp->tx_ring_size * sizeof(struct eth_tx_desc);
873 mp->tx_desc_area_size = size;
875 if (mp->tx_sram_size) {
876 mp->p_tx_desc_area = ioremap(mp->tx_sram_addr,
878 mp->tx_desc_dma = mp->tx_sram_addr;
880 mp->p_tx_desc_area = dma_alloc_coherent(NULL, size,
884 if (!mp->p_tx_desc_area) {
885 printk(KERN_ERR "%s: Cannot allocate Tx Ring (size %d bytes)\n",
888 goto out_free_tx_skb;
890 BUG_ON((u32) mp->p_tx_desc_area & 0xf); /* check 16-byte alignment */
891 memset((void *)mp->p_tx_desc_area, 0, mp->tx_desc_area_size);
893 ether_init_tx_desc_ring(mp);
895 /* Allocate RX ring */
896 mp->rx_desc_count = 0;
897 size = mp->rx_ring_size * sizeof(struct eth_rx_desc);
898 mp->rx_desc_area_size = size;
900 if (mp->rx_sram_size) {
901 mp->p_rx_desc_area = ioremap(mp->rx_sram_addr,
903 mp->rx_desc_dma = mp->rx_sram_addr;
905 mp->p_rx_desc_area = dma_alloc_coherent(NULL, size,
909 if (!mp->p_rx_desc_area) {
910 printk(KERN_ERR "%s: Cannot allocate Rx ring (size %d bytes)\n",
912 printk(KERN_ERR "%s: Freeing previously allocated TX queues...",
914 if (mp->rx_sram_size)
915 iounmap(mp->p_tx_desc_area);
917 dma_free_coherent(NULL, mp->tx_desc_area_size,
918 mp->p_tx_desc_area, mp->tx_desc_dma);
920 goto out_free_tx_skb;
922 memset((void *)mp->p_rx_desc_area, 0, size);
924 ether_init_rx_desc_ring(mp);
926 mv643xx_eth_rx_task(dev); /* Fill RX ring with skb's */
928 /* Clear any pending ethernet port interrupts */
929 mv_write(MV643XX_ETH_INTERRUPT_CAUSE_REG(port_num), 0);
930 mv_write(MV643XX_ETH_INTERRUPT_CAUSE_EXTEND_REG(port_num), 0);
934 /* Interrupt Coalescing */
938 eth_port_set_rx_coal(port_num, 133000000, MV643XX_RX_COAL);
942 eth_port_set_tx_coal(port_num, 133000000, MV643XX_TX_COAL);
944 /* Unmask phy and link status changes interrupts */
945 mv_write(MV643XX_ETH_INTERRUPT_EXTEND_MASK_REG(port_num),
948 /* Unmask RX buffer and TX end interrupt */
949 mv_write(MV643XX_ETH_INTERRUPT_MASK_REG(port_num), INT_UNMASK_ALL);
958 free_irq(dev->irq, dev);
963 static void mv643xx_eth_free_tx_rings(struct net_device *dev)
965 struct mv643xx_private *mp = netdev_priv(dev);
966 unsigned int port_num = mp->port_num;
971 mv643xx_eth_port_disable_tx(port_num);
973 /* Free outstanding skb's on TX rings */
974 for (curr = 0; mp->tx_desc_count && curr < mp->tx_ring_size; curr++) {
975 skb = mp->tx_skb[curr];
977 mp->tx_desc_count -= skb_shinfo(skb)->nr_frags;
982 if (mp->tx_desc_count)
983 printk("%s: Error on Tx descriptor free - could not free %d"
984 " descriptors\n", dev->name, mp->tx_desc_count);
987 if (mp->tx_sram_size)
988 iounmap(mp->p_tx_desc_area);
990 dma_free_coherent(NULL, mp->tx_desc_area_size,
991 mp->p_tx_desc_area, mp->tx_desc_dma);
994 static void mv643xx_eth_free_rx_rings(struct net_device *dev)
996 struct mv643xx_private *mp = netdev_priv(dev);
997 unsigned int port_num = mp->port_num;
1000 /* Stop RX Queues */
1001 mv643xx_eth_port_disable_rx(port_num);
1003 /* Free preallocated skb's on RX rings */
1004 for (curr = 0; mp->rx_desc_count && curr < mp->rx_ring_size; curr++) {
1005 if (mp->rx_skb[curr]) {
1006 dev_kfree_skb(mp->rx_skb[curr]);
1007 mp->rx_desc_count--;
1011 if (mp->rx_desc_count)
1013 "%s: Error in freeing Rx Ring. %d skb's still"
1014 " stuck in RX Ring - ignoring them\n", dev->name,
1017 if (mp->rx_sram_size)
1018 iounmap(mp->p_rx_desc_area);
1020 dma_free_coherent(NULL, mp->rx_desc_area_size,
1021 mp->p_rx_desc_area, mp->rx_desc_dma);
1027 * This function is used when closing the network device.
1028 * It updates the hardware,
1029 * release all memory that holds buffers and descriptors and release the IRQ.
1030 * Input : a pointer to the device structure
1031 * Output : zero if success , nonzero if fails
1034 static int mv643xx_eth_stop(struct net_device *dev)
1036 struct mv643xx_private *mp = netdev_priv(dev);
1037 unsigned int port_num = mp->port_num;
1039 /* Mask all interrupts on ethernet port */
1040 mv_write(MV643XX_ETH_INTERRUPT_MASK_REG(port_num), INT_MASK_ALL);
1041 /* wait for previous write to complete */
1042 mv_read(MV643XX_ETH_INTERRUPT_MASK_REG(port_num));
1045 netif_poll_disable(dev);
1047 netif_carrier_off(dev);
1048 netif_stop_queue(dev);
1050 eth_port_reset(mp->port_num);
1052 mv643xx_eth_free_tx_rings(dev);
1053 mv643xx_eth_free_rx_rings(dev);
1056 netif_poll_enable(dev);
1059 free_irq(dev->irq, dev);
1065 static void mv643xx_tx(struct net_device *dev)
1067 struct mv643xx_private *mp = netdev_priv(dev);
1068 struct pkt_info pkt_info;
1070 while (eth_tx_return_desc(mp, &pkt_info) == ETH_OK) {
1071 if (pkt_info.cmd_sts & ETH_TX_FIRST_DESC)
1072 dma_unmap_single(NULL, pkt_info.buf_ptr,
1076 dma_unmap_page(NULL, pkt_info.buf_ptr,
1080 if (pkt_info.return_info)
1081 dev_kfree_skb_irq(pkt_info.return_info);
1084 if (netif_queue_stopped(dev) &&
1085 mp->tx_ring_size - mp->tx_desc_count > MAX_DESCS_PER_SKB)
1086 netif_wake_queue(dev);
1092 * This function is used in case of NAPI
1094 static int mv643xx_poll(struct net_device *dev, int *budget)
1096 struct mv643xx_private *mp = netdev_priv(dev);
1097 int done = 1, orig_budget, work_done;
1098 unsigned int port_num = mp->port_num;
1100 #ifdef MV643XX_TX_FAST_REFILL
1101 if (++mp->tx_clean_threshold > 5) {
1103 mp->tx_clean_threshold = 0;
1107 if ((mv_read(MV643XX_ETH_RX_CURRENT_QUEUE_DESC_PTR_0(port_num)))
1108 != (u32) mp->rx_used_desc_q) {
1109 orig_budget = *budget;
1110 if (orig_budget > dev->quota)
1111 orig_budget = dev->quota;
1112 work_done = mv643xx_eth_receive_queue(dev, orig_budget);
1113 mp->rx_task.func(dev);
1114 *budget -= work_done;
1115 dev->quota -= work_done;
1116 if (work_done >= orig_budget)
1121 netif_rx_complete(dev);
1122 mv_write(MV643XX_ETH_INTERRUPT_CAUSE_REG(port_num), 0);
1123 mv_write(MV643XX_ETH_INTERRUPT_CAUSE_EXTEND_REG(port_num), 0);
1124 mv_write(MV643XX_ETH_INTERRUPT_MASK_REG(port_num),
1128 return done ? 0 : 1;
1133 * has_tiny_unaligned_frags - check if skb has any small, unaligned fragments
1135 * Hardware can't handle unaligned fragments smaller than 9 bytes.
1136 * This helper function detects that case.
1139 static inline unsigned int has_tiny_unaligned_frags(struct sk_buff *skb)
1144 for (frag = 0; frag < skb_shinfo(skb)->nr_frags; frag++) {
1145 fragp = &skb_shinfo(skb)->frags[frag];
1146 if (fragp->size <= 8 && fragp->page_offset & 0x7)
1153 * eth_alloc_tx_desc_index - return the index of the next available tx desc
1155 static int eth_alloc_tx_desc_index(struct mv643xx_private *mp)
1159 tx_desc_curr = mp->tx_curr_desc_q;
1161 BUG_ON(mp->tx_desc_count >= mp->tx_ring_size);
1162 mp->tx_desc_count++;
1164 mp->tx_curr_desc_q = (tx_desc_curr + 1) % mp->tx_ring_size;
1166 BUG_ON(mp->tx_curr_desc_q == mp->tx_used_desc_q);
1168 return tx_desc_curr;
1172 * eth_tx_fill_frag_descs - fill tx hw descriptors for an skb's fragments.
1174 * Ensure the data for each fragment to be transmitted is mapped properly,
1175 * then fill in descriptors in the tx hw queue.
1177 static void eth_tx_fill_frag_descs(struct mv643xx_private *mp,
1178 struct sk_buff *skb)
1182 struct eth_tx_desc *desc;
1183 struct net_device_stats *stats = &mp->stats;
1185 for (frag = 0; frag < skb_shinfo(skb)->nr_frags; frag++) {
1186 skb_frag_t *this_frag = &skb_shinfo(skb)->frags[frag];
1188 tx_index = eth_alloc_tx_desc_index(mp);
1189 desc = &mp->p_tx_desc_area[tx_index];
1191 desc->cmd_sts = ETH_BUFFER_OWNED_BY_DMA;
1192 /* Last Frag enables interrupt and frees the skb */
1193 if (frag == (skb_shinfo(skb)->nr_frags - 1)) {
1194 desc->cmd_sts |= ETH_ZERO_PADDING |
1196 ETH_TX_ENABLE_INTERRUPT;
1197 mp->tx_skb[tx_index] = skb;
1199 mp->tx_skb[tx_index] = 0;
1201 desc = &mp->p_tx_desc_area[tx_index];
1203 desc->byte_cnt = this_frag->size;
1204 desc->buf_ptr = dma_map_page(NULL, this_frag->page,
1205 this_frag->page_offset,
1208 stats->tx_bytes += this_frag->size;
1213 * eth_tx_submit_descs_for_skb - submit data from an skb to the tx hw
1215 * Ensure the data for an skb to be transmitted is mapped properly,
1216 * then fill in descriptors in the tx hw queue and start the hardware.
1218 static int eth_tx_submit_descs_for_skb(struct mv643xx_private *mp,
1219 struct sk_buff *skb)
1222 struct eth_tx_desc *desc;
1227 cmd_sts = ETH_TX_FIRST_DESC | ETH_GEN_CRC | ETH_BUFFER_OWNED_BY_DMA;
1229 tx_index = eth_alloc_tx_desc_index(mp);
1230 desc = &mp->p_tx_desc_area[tx_index];
1232 if (skb_shinfo(skb)->nr_frags) {
1233 eth_tx_fill_frag_descs(mp, skb);
1235 length = skb_headlen(skb);
1236 mp->tx_skb[tx_index] = 0;
1238 cmd_sts |= ETH_ZERO_PADDING |
1240 ETH_TX_ENABLE_INTERRUPT;
1242 mp->tx_skb[tx_index] = skb;
1245 desc->byte_cnt = length;
1246 desc->buf_ptr = dma_map_single(NULL, skb->data, length, DMA_TO_DEVICE);
1249 if (skb->ip_summed == CHECKSUM_HW) {
1250 BUG_ON(skb->protocol != ETH_P_IP);
1252 cmd_sts |= ETH_GEN_TCP_UDP_CHECKSUM |
1253 ETH_GEN_IP_V_4_CHECKSUM |
1254 skb->nh.iph->ihl << ETH_TX_IHL_SHIFT;
1256 switch (skb->nh.iph->protocol) {
1258 cmd_sts |= ETH_UDP_FRAME;
1259 desc->l4i_chk = skb->h.uh->check;
1262 desc->l4i_chk = skb->h.th->check;
1268 /* Errata BTS #50, IHL must be 5 if no HW checksum */
1269 cmd_sts |= 5 << ETH_TX_IHL_SHIFT;
1273 /* ensure all other descriptors are written before first cmd_sts */
1275 desc->cmd_sts = cmd_sts;
1277 /* ensure all descriptors are written before poking hardware */
1279 mv643xx_eth_port_enable_tx(mp->port_num, mp->port_tx_queue_command);
1285 * mv643xx_eth_start_xmit - queue an skb to the hardware for transmission
1288 static int mv643xx_eth_start_xmit(struct sk_buff *skb, struct net_device *dev)
1290 struct mv643xx_private *mp = netdev_priv(dev);
1291 struct net_device_stats *stats = &mp->stats;
1292 unsigned long flags;
1294 BUG_ON(netif_queue_stopped(dev));
1295 BUG_ON(skb == NULL);
1296 BUG_ON(mp->tx_ring_size - mp->tx_desc_count < MAX_DESCS_PER_SKB);
1298 if (has_tiny_unaligned_frags(skb)) {
1299 if ((skb_linearize(skb, GFP_ATOMIC) != 0)) {
1300 stats->tx_dropped++;
1301 printk(KERN_DEBUG "%s: failed to linearize tiny "
1302 "unaligned fragment\n", dev->name);
1307 spin_lock_irqsave(&mp->lock, flags);
1309 stats->tx_bytes = eth_tx_submit_descs_for_skb(mp, skb);
1310 stats->tx_packets++;
1311 dev->trans_start = jiffies;
1313 if (mp->tx_ring_size - mp->tx_desc_count < MAX_DESCS_PER_SKB)
1314 netif_stop_queue(dev);
1316 spin_unlock_irqrestore(&mp->lock, flags);
1318 return 0; /* success */
1322 * mv643xx_eth_get_stats
1324 * Returns a pointer to the interface statistics.
1326 * Input : dev - a pointer to the required interface
1328 * Output : a pointer to the interface's statistics
1331 static struct net_device_stats *mv643xx_eth_get_stats(struct net_device *dev)
1333 struct mv643xx_private *mp = netdev_priv(dev);
1338 #ifdef CONFIG_NET_POLL_CONTROLLER
1339 static void mv643xx_netpoll(struct net_device *netdev)
1341 struct mv643xx_private *mp = netdev_priv(netdev);
1342 int port_num = mp->port_num;
1344 mv_write(MV643XX_ETH_INTERRUPT_MASK_REG(port_num), INT_MASK_ALL);
1345 /* wait for previous write to complete */
1346 mv_read(MV643XX_ETH_INTERRUPT_MASK_REG(port_num));
1348 mv643xx_eth_int_handler(netdev->irq, netdev, NULL);
1350 mv_write(MV643XX_ETH_INTERRUPT_MASK_REG(port_num), INT_UNMASK_ALL);
1354 static void mv643xx_init_ethtool_cmd(struct net_device *dev, int phy_address,
1355 int speed, int duplex,
1356 struct ethtool_cmd *cmd)
1358 struct mv643xx_private *mp = netdev_priv(dev);
1360 memset(cmd, 0, sizeof(*cmd));
1362 cmd->port = PORT_MII;
1363 cmd->transceiver = XCVR_INTERNAL;
1364 cmd->phy_address = phy_address;
1367 cmd->autoneg = AUTONEG_ENABLE;
1368 /* mii lib checks, but doesn't use speed on AUTONEG_ENABLE */
1369 cmd->speed = SPEED_100;
1370 cmd->advertising = ADVERTISED_10baseT_Half |
1371 ADVERTISED_10baseT_Full |
1372 ADVERTISED_100baseT_Half |
1373 ADVERTISED_100baseT_Full;
1374 if (mp->mii.supports_gmii)
1375 cmd->advertising |= ADVERTISED_1000baseT_Full;
1377 cmd->autoneg = AUTONEG_DISABLE;
1379 cmd->duplex = duplex;
1386 * First function called after registering the network device.
1387 * It's purpose is to initialize the device as an ethernet device,
1388 * fill the ethernet device structure with pointers * to functions,
1389 * and set the MAC address of the interface
1391 * Input : struct device *
1392 * Output : -ENOMEM if failed , 0 if success
1394 static int mv643xx_eth_probe(struct platform_device *pdev)
1396 struct mv643xx_eth_platform_data *pd;
1397 int port_num = pdev->id;
1398 struct mv643xx_private *mp;
1399 struct net_device *dev;
1401 struct resource *res;
1403 struct ethtool_cmd cmd;
1404 int duplex = DUPLEX_HALF;
1405 int speed = 0; /* default to auto-negotiation */
1407 dev = alloc_etherdev(sizeof(struct mv643xx_private));
1411 platform_set_drvdata(pdev, dev);
1413 mp = netdev_priv(dev);
1415 res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
1417 dev->irq = res->start;
1419 mp->port_num = port_num;
1421 dev->open = mv643xx_eth_open;
1422 dev->stop = mv643xx_eth_stop;
1423 dev->hard_start_xmit = mv643xx_eth_start_xmit;
1424 dev->get_stats = mv643xx_eth_get_stats;
1425 dev->set_mac_address = mv643xx_eth_set_mac_address;
1426 dev->set_multicast_list = mv643xx_eth_set_rx_mode;
1428 /* No need to Tx Timeout */
1429 dev->tx_timeout = mv643xx_eth_tx_timeout;
1431 dev->poll = mv643xx_poll;
1435 #ifdef CONFIG_NET_POLL_CONTROLLER
1436 dev->poll_controller = mv643xx_netpoll;
1439 dev->watchdog_timeo = 2 * HZ;
1440 dev->tx_queue_len = mp->tx_ring_size;
1442 dev->change_mtu = mv643xx_eth_change_mtu;
1443 dev->do_ioctl = mv643xx_eth_do_ioctl;
1444 SET_ETHTOOL_OPS(dev, &mv643xx_ethtool_ops);
1446 #ifdef MV643XX_CHECKSUM_OFFLOAD_TX
1447 #ifdef MAX_SKB_FRAGS
1449 * Zero copy can only work if we use Discovery II memory. Else, we will
1450 * have to map the buffers to ISA memory which is only 16 MB
1452 dev->features = NETIF_F_SG | NETIF_F_IP_CSUM;
1456 /* Configure the timeout task */
1457 INIT_WORK(&mp->tx_timeout_task,
1458 (void (*)(void *))mv643xx_eth_tx_timeout_task, dev);
1460 spin_lock_init(&mp->lock);
1462 /* set default config values */
1463 eth_port_uc_addr_get(dev, dev->dev_addr);
1464 mp->rx_ring_size = MV643XX_ETH_PORT_DEFAULT_RECEIVE_QUEUE_SIZE;
1465 mp->tx_ring_size = MV643XX_ETH_PORT_DEFAULT_TRANSMIT_QUEUE_SIZE;
1467 pd = pdev->dev.platform_data;
1470 memcpy(dev->dev_addr, pd->mac_addr, 6);
1472 if (pd->phy_addr || pd->force_phy_addr)
1473 ethernet_phy_set(port_num, pd->phy_addr);
1475 if (pd->rx_queue_size)
1476 mp->rx_ring_size = pd->rx_queue_size;
1478 if (pd->tx_queue_size)
1479 mp->tx_ring_size = pd->tx_queue_size;
1481 if (pd->tx_sram_size) {
1482 mp->tx_sram_size = pd->tx_sram_size;
1483 mp->tx_sram_addr = pd->tx_sram_addr;
1486 if (pd->rx_sram_size) {
1487 mp->rx_sram_size = pd->rx_sram_size;
1488 mp->rx_sram_addr = pd->rx_sram_addr;
1491 duplex = pd->duplex;
1495 /* Hook up MII support for ethtool */
1497 mp->mii.mdio_read = mv643xx_mdio_read;
1498 mp->mii.mdio_write = mv643xx_mdio_write;
1499 mp->mii.phy_id = ethernet_phy_get(port_num);
1500 mp->mii.phy_id_mask = 0x3f;
1501 mp->mii.reg_num_mask = 0x1f;
1503 err = ethernet_phy_detect(port_num);
1505 pr_debug("MV643xx ethernet port %d: "
1506 "No PHY detected at addr %d\n",
1507 port_num, ethernet_phy_get(port_num));
1511 ethernet_phy_reset(port_num);
1512 mp->mii.supports_gmii = mii_check_gmii_support(&mp->mii);
1513 mv643xx_init_ethtool_cmd(dev, mp->mii.phy_id, speed, duplex, &cmd);
1514 mv643xx_eth_update_pscr(dev, &cmd);
1515 mv643xx_set_settings(dev, &cmd);
1517 err = register_netdev(dev);
1523 "%s: port %d with MAC address %02x:%02x:%02x:%02x:%02x:%02x\n",
1524 dev->name, port_num, p[0], p[1], p[2], p[3], p[4], p[5]);
1526 if (dev->features & NETIF_F_SG)
1527 printk(KERN_NOTICE "%s: Scatter Gather Enabled\n", dev->name);
1529 if (dev->features & NETIF_F_IP_CSUM)
1530 printk(KERN_NOTICE "%s: TX TCP/IP Checksumming Supported\n",
1533 #ifdef MV643XX_CHECKSUM_OFFLOAD_TX
1534 printk(KERN_NOTICE "%s: RX TCP/UDP Checksum Offload ON \n", dev->name);
1538 printk(KERN_NOTICE "%s: TX and RX Interrupt Coalescing ON \n",
1543 printk(KERN_NOTICE "%s: RX NAPI Enabled \n", dev->name);
1546 if (mp->tx_sram_size > 0)
1547 printk(KERN_NOTICE "%s: Using SRAM\n", dev->name);
1557 static int mv643xx_eth_remove(struct platform_device *pdev)
1559 struct net_device *dev = platform_get_drvdata(pdev);
1561 unregister_netdev(dev);
1562 flush_scheduled_work();
1565 platform_set_drvdata(pdev, NULL);
1569 static int mv643xx_eth_shared_probe(struct platform_device *pdev)
1571 struct resource *res;
1573 printk(KERN_NOTICE "MV-643xx 10/100/1000 Ethernet Driver\n");
1575 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1579 mv643xx_eth_shared_base = ioremap(res->start,
1580 MV643XX_ETH_SHARED_REGS_SIZE);
1581 if (mv643xx_eth_shared_base == NULL)
1588 static int mv643xx_eth_shared_remove(struct platform_device *pdev)
1590 iounmap(mv643xx_eth_shared_base);
1591 mv643xx_eth_shared_base = NULL;
1596 static struct platform_driver mv643xx_eth_driver = {
1597 .probe = mv643xx_eth_probe,
1598 .remove = mv643xx_eth_remove,
1600 .name = MV643XX_ETH_NAME,
1604 static struct platform_driver mv643xx_eth_shared_driver = {
1605 .probe = mv643xx_eth_shared_probe,
1606 .remove = mv643xx_eth_shared_remove,
1608 .name = MV643XX_ETH_SHARED_NAME,
1613 * mv643xx_init_module
1615 * Registers the network drivers into the Linux kernel
1621 static int __init mv643xx_init_module(void)
1625 rc = platform_driver_register(&mv643xx_eth_shared_driver);
1627 rc = platform_driver_register(&mv643xx_eth_driver);
1629 platform_driver_unregister(&mv643xx_eth_shared_driver);
1635 * mv643xx_cleanup_module
1637 * Registers the network drivers into the Linux kernel
1643 static void __exit mv643xx_cleanup_module(void)
1645 platform_driver_unregister(&mv643xx_eth_driver);
1646 platform_driver_unregister(&mv643xx_eth_shared_driver);
1649 module_init(mv643xx_init_module);
1650 module_exit(mv643xx_cleanup_module);
1652 MODULE_LICENSE("GPL");
1653 MODULE_AUTHOR( "Rabeeh Khoury, Assaf Hoffman, Matthew Dharm, Manish Lachwani"
1654 " and Dale Farnsworth");
1655 MODULE_DESCRIPTION("Ethernet driver for Marvell MV643XX");
1658 * The second part is the low level driver of the gigE ethernet ports.
1662 * Marvell's Gigabit Ethernet controller low level driver
1665 * This file introduce low level API to Marvell's Gigabit Ethernet
1666 * controller. This Gigabit Ethernet Controller driver API controls
1667 * 1) Operations (i.e. port init, start, reset etc').
1668 * 2) Data flow (i.e. port send, receive etc').
1669 * Each Gigabit Ethernet port is controlled via
1670 * struct mv643xx_private.
1671 * This struct includes user configuration information as well as
1672 * driver internal data needed for its operations.
1674 * Supported Features:
1675 * - This low level driver is OS independent. Allocating memory for
1676 * the descriptor rings and buffers are not within the scope of
1678 * - The user is free from Rx/Tx queue managing.
1679 * - This low level driver introduce functionality API that enable
1680 * the to operate Marvell's Gigabit Ethernet Controller in a
1682 * - Simple Gigabit Ethernet port operation API.
1683 * - Simple Gigabit Ethernet port data flow API.
1684 * - Data flow and operation API support per queue functionality.
1685 * - Support cached descriptors for better performance.
1686 * - Enable access to all four DRAM banks and internal SRAM memory
1688 * - PHY access and control API.
1689 * - Port control register configuration API.
1690 * - Full control over Unicast and Multicast MAC configurations.
1694 * Initialization phase
1695 * This phase complete the initialization of the the
1696 * mv643xx_private struct.
1697 * User information regarding port configuration has to be set
1698 * prior to calling the port initialization routine.
1700 * In this phase any port Tx/Rx activity is halted, MIB counters
1701 * are cleared, PHY address is set according to user parameter and
1702 * access to DRAM and internal SRAM memory spaces.
1704 * Driver ring initialization
1705 * Allocating memory for the descriptor rings and buffers is not
1706 * within the scope of this driver. Thus, the user is required to
1707 * allocate memory for the descriptors ring and buffers. Those
1708 * memory parameters are used by the Rx and Tx ring initialization
1709 * routines in order to curve the descriptor linked list in a form
1711 * Note: Pay special attention to alignment issues when using
1712 * cached descriptors/buffers. In this phase the driver store
1713 * information in the mv643xx_private struct regarding each queue
1717 * This phase prepares the Ethernet port for Rx and Tx activity.
1718 * It uses the information stored in the mv643xx_private struct to
1719 * initialize the various port registers.
1722 * All packet references to/from the driver are done using
1724 * This struct is a unified struct used with Rx and Tx operations.
1725 * This way the user is not required to be familiar with neither
1726 * Tx nor Rx descriptors structures.
1727 * The driver's descriptors rings are management by indexes.
1728 * Those indexes controls the ring resources and used to indicate
1729 * a SW resource error:
1731 * This index points to the current available resource for use. For
1732 * example in Rx process this index will point to the descriptor
1733 * that will be passed to the user upon calling the receive
1734 * routine. In Tx process, this index will point to the descriptor
1735 * that will be assigned with the user packet info and transmitted.
1737 * This index points to the descriptor that need to restore its
1738 * resources. For example in Rx process, using the Rx buffer return
1739 * API will attach the buffer returned in packet info to the
1740 * descriptor pointed by 'used'. In Tx process, using the Tx
1741 * descriptor return will merely return the user packet info with
1742 * the command status of the transmitted buffer pointed by the
1743 * 'used' index. Nevertheless, it is essential to use this routine
1744 * to update the 'used' index.
1746 * This index supports Tx Scatter-Gather. It points to the first
1747 * descriptor of a packet assembled of multiple buffers. For
1748 * example when in middle of Such packet we have a Tx resource
1749 * error the 'curr' index get the value of 'first' to indicate
1750 * that the ring returned to its state before trying to transmit
1753 * Receive operation:
1754 * The eth_port_receive API set the packet information struct,
1755 * passed by the caller, with received information from the
1756 * 'current' SDMA descriptor.
1757 * It is the user responsibility to return this resource back
1758 * to the Rx descriptor ring to enable the reuse of this source.
1759 * Return Rx resource is done using the eth_rx_return_buff API.
1761 * Prior to calling the initialization routine eth_port_init() the user
1762 * must set the following fields under mv643xx_private struct:
1763 * port_num User Ethernet port number.
1764 * port_config User port configuration value.
1765 * port_config_extend User port config extend value.
1766 * port_sdma_config User port SDMA config value.
1767 * port_serial_control User port serial control value.
1769 * This driver data flow is done using the struct pkt_info which
1770 * is a unified struct for Rx and Tx operations:
1772 * byte_cnt Tx/Rx descriptor buffer byte count.
1773 * l4i_chk CPU provided TCP Checksum. For Tx operation
1775 * cmd_sts Tx/Rx descriptor command status.
1776 * buf_ptr Tx/Rx descriptor buffer pointer.
1777 * return_info Tx/Rx user resource return information.
1781 static int ethernet_phy_get(unsigned int eth_port_num);
1782 static void ethernet_phy_set(unsigned int eth_port_num, int phy_addr);
1784 /* Ethernet Port routines */
1785 static void eth_port_set_filter_table_entry(int table, unsigned char entry);
1788 * eth_port_init - Initialize the Ethernet port driver
1791 * This function prepares the ethernet port to start its activity:
1792 * 1) Completes the ethernet port driver struct initialization toward port
1794 * 2) Resets the device to a quiescent state in case of warm reboot.
1795 * 3) Enable SDMA access to all four DRAM banks as well as internal SRAM.
1796 * 4) Clean MAC tables. The reset status of those tables is unknown.
1797 * 5) Set PHY address.
1798 * Note: Call this routine prior to eth_port_start routine and after
1799 * setting user values in the user fields of Ethernet port control
1803 * struct mv643xx_private *mp Ethernet port control struct
1811 static void eth_port_init(struct mv643xx_private *mp)
1813 mp->rx_resource_err = 0;
1815 eth_port_reset(mp->port_num);
1817 eth_port_init_mac_tables(mp->port_num);
1821 * eth_port_start - Start the Ethernet port activity.
1824 * This routine prepares the Ethernet port for Rx and Tx activity:
1825 * 1. Initialize Tx and Rx Current Descriptor Pointer for each queue that
1826 * has been initialized a descriptor's ring (using
1827 * ether_init_tx_desc_ring for Tx and ether_init_rx_desc_ring for Rx)
1828 * 2. Initialize and enable the Ethernet configuration port by writing to
1829 * the port's configuration and command registers.
1830 * 3. Initialize and enable the SDMA by writing to the SDMA's
1831 * configuration and command registers. After completing these steps,
1832 * the ethernet port SDMA can starts to perform Rx and Tx activities.
1834 * Note: Each Rx and Tx queue descriptor's list must be initialized prior
1835 * to calling this function (use ether_init_tx_desc_ring for Tx queues
1836 * and ether_init_rx_desc_ring for Rx queues).
1839 * dev - a pointer to the required interface
1842 * Ethernet port is ready to receive and transmit.
1847 static void eth_port_start(struct net_device *dev)
1849 struct mv643xx_private *mp = netdev_priv(dev);
1850 unsigned int port_num = mp->port_num;
1851 int tx_curr_desc, rx_curr_desc;
1853 struct ethtool_cmd ethtool_cmd;
1855 /* Assignment of Tx CTRP of given queue */
1856 tx_curr_desc = mp->tx_curr_desc_q;
1857 mv_write(MV643XX_ETH_TX_CURRENT_QUEUE_DESC_PTR_0(port_num),
1858 (u32)((struct eth_tx_desc *)mp->tx_desc_dma + tx_curr_desc));
1860 /* Assignment of Rx CRDP of given queue */
1861 rx_curr_desc = mp->rx_curr_desc_q;
1862 mv_write(MV643XX_ETH_RX_CURRENT_QUEUE_DESC_PTR_0(port_num),
1863 (u32)((struct eth_rx_desc *)mp->rx_desc_dma + rx_curr_desc));
1865 /* Add the assigned Ethernet address to the port's address table */
1866 eth_port_uc_addr_set(port_num, dev->dev_addr);
1868 /* Assign port configuration and command. */
1869 mv_write(MV643XX_ETH_PORT_CONFIG_REG(port_num),
1870 MV643XX_ETH_PORT_CONFIG_DEFAULT_VALUE);
1872 mv_write(MV643XX_ETH_PORT_CONFIG_EXTEND_REG(port_num),
1873 MV643XX_ETH_PORT_CONFIG_EXTEND_DEFAULT_VALUE);
1875 pscr = mv_read(MV643XX_ETH_PORT_SERIAL_CONTROL_REG(port_num));
1877 pscr &= ~(MV643XX_ETH_SERIAL_PORT_ENABLE | MV643XX_ETH_FORCE_LINK_PASS);
1878 mv_write(MV643XX_ETH_PORT_SERIAL_CONTROL_REG(port_num), pscr);
1880 pscr |= MV643XX_ETH_DISABLE_AUTO_NEG_FOR_FLOW_CTRL |
1881 MV643XX_ETH_DISABLE_AUTO_NEG_SPEED_GMII |
1882 MV643XX_ETH_DISABLE_AUTO_NEG_FOR_DUPLX |
1883 MV643XX_ETH_DO_NOT_FORCE_LINK_FAIL |
1884 MV643XX_ETH_SERIAL_PORT_CONTROL_RESERVED;
1886 mv_write(MV643XX_ETH_PORT_SERIAL_CONTROL_REG(port_num), pscr);
1888 pscr |= MV643XX_ETH_SERIAL_PORT_ENABLE;
1889 mv_write(MV643XX_ETH_PORT_SERIAL_CONTROL_REG(port_num), pscr);
1891 /* Assign port SDMA configuration */
1892 mv_write(MV643XX_ETH_SDMA_CONFIG_REG(port_num),
1893 MV643XX_ETH_PORT_SDMA_CONFIG_DEFAULT_VALUE);
1895 /* Enable port Rx. */
1896 mv643xx_eth_port_enable_rx(port_num, mp->port_rx_queue_command);
1898 /* Disable port bandwidth limits by clearing MTU register */
1899 mv_write(MV643XX_ETH_MAXIMUM_TRANSMIT_UNIT(port_num), 0);
1901 /* save phy settings across reset */
1902 mv643xx_get_settings(dev, ðtool_cmd);
1903 ethernet_phy_reset(mp->port_num);
1904 mv643xx_set_settings(dev, ðtool_cmd);
1908 * eth_port_uc_addr_set - This function Set the port Unicast address.
1911 * This function Set the port Ethernet MAC address.
1914 * unsigned int eth_port_num Port number.
1915 * char * p_addr Address to be set
1918 * Set MAC address low and high registers. also calls
1919 * eth_port_set_filter_table_entry() to set the unicast
1920 * table with the proper information.
1926 static void eth_port_uc_addr_set(unsigned int eth_port_num,
1927 unsigned char *p_addr)
1933 mac_l = (p_addr[4] << 8) | (p_addr[5]);
1934 mac_h = (p_addr[0] << 24) | (p_addr[1] << 16) | (p_addr[2] << 8) |
1937 mv_write(MV643XX_ETH_MAC_ADDR_LOW(eth_port_num), mac_l);
1938 mv_write(MV643XX_ETH_MAC_ADDR_HIGH(eth_port_num), mac_h);
1940 /* Accept frames of this address */
1941 table = MV643XX_ETH_DA_FILTER_UNICAST_TABLE_BASE(eth_port_num);
1942 eth_port_set_filter_table_entry(table, p_addr[5] & 0x0f);
1946 * eth_port_uc_addr_get - This function retrieves the port Unicast address
1947 * (MAC address) from the ethernet hw registers.
1950 * This function retrieves the port Ethernet MAC address.
1953 * unsigned int eth_port_num Port number.
1954 * char *MacAddr pointer where the MAC address is stored
1957 * Copy the MAC address to the location pointed to by MacAddr
1963 static void eth_port_uc_addr_get(struct net_device *dev, unsigned char *p_addr)
1965 struct mv643xx_private *mp = netdev_priv(dev);
1969 mac_h = mv_read(MV643XX_ETH_MAC_ADDR_HIGH(mp->port_num));
1970 mac_l = mv_read(MV643XX_ETH_MAC_ADDR_LOW(mp->port_num));
1972 p_addr[0] = (mac_h >> 24) & 0xff;
1973 p_addr[1] = (mac_h >> 16) & 0xff;
1974 p_addr[2] = (mac_h >> 8) & 0xff;
1975 p_addr[3] = mac_h & 0xff;
1976 p_addr[4] = (mac_l >> 8) & 0xff;
1977 p_addr[5] = mac_l & 0xff;
1981 * The entries in each table are indexed by a hash of a packet's MAC
1982 * address. One bit in each entry determines whether the packet is
1983 * accepted. There are 4 entries (each 8 bits wide) in each register
1984 * of the table. The bits in each entry are defined as follows:
1985 * 0 Accept=1, Drop=0
1986 * 3-1 Queue (ETH_Q0=0)
1989 static void eth_port_set_filter_table_entry(int table, unsigned char entry)
1991 unsigned int table_reg;
1992 unsigned int tbl_offset;
1993 unsigned int reg_offset;
1995 tbl_offset = (entry / 4) * 4; /* Register offset of DA table entry */
1996 reg_offset = entry % 4; /* Entry offset within the register */
1998 /* Set "accepts frame bit" at specified table entry */
1999 table_reg = mv_read(table + tbl_offset);
2000 table_reg |= 0x01 << (8 * reg_offset);
2001 mv_write(table + tbl_offset, table_reg);
2005 * eth_port_mc_addr - Multicast address settings.
2007 * The MV device supports multicast using two tables:
2008 * 1) Special Multicast Table for MAC addresses of the form
2009 * 0x01-00-5E-00-00-XX (where XX is between 0x00 and 0x_FF).
2010 * The MAC DA[7:0] bits are used as a pointer to the Special Multicast
2011 * Table entries in the DA-Filter table.
2012 * 2) Other Multicast Table for multicast of another type. A CRC-8bit
2013 * is used as an index to the Other Multicast Table entries in the
2014 * DA-Filter table. This function calculates the CRC-8bit value.
2015 * In either case, eth_port_set_filter_table_entry() is then called
2016 * to set to set the actual table entry.
2018 static void eth_port_mc_addr(unsigned int eth_port_num, unsigned char *p_addr)
2022 unsigned char crc_result = 0;
2028 if ((p_addr[0] == 0x01) && (p_addr[1] == 0x00) &&
2029 (p_addr[2] == 0x5E) && (p_addr[3] == 0x00) && (p_addr[4] == 0x00)) {
2030 table = MV643XX_ETH_DA_FILTER_SPECIAL_MULTICAST_TABLE_BASE
2032 eth_port_set_filter_table_entry(table, p_addr[5]);
2036 /* Calculate CRC-8 out of the given address */
2037 mac_h = (p_addr[0] << 8) | (p_addr[1]);
2038 mac_l = (p_addr[2] << 24) | (p_addr[3] << 16) |
2039 (p_addr[4] << 8) | (p_addr[5] << 0);
2041 for (i = 0; i < 32; i++)
2042 mac_array[i] = (mac_l >> i) & 0x1;
2043 for (i = 32; i < 48; i++)
2044 mac_array[i] = (mac_h >> (i - 32)) & 0x1;
2046 crc[0] = mac_array[45] ^ mac_array[43] ^ mac_array[40] ^ mac_array[39] ^
2047 mac_array[35] ^ mac_array[34] ^ mac_array[31] ^ mac_array[30] ^
2048 mac_array[28] ^ mac_array[23] ^ mac_array[21] ^ mac_array[19] ^
2049 mac_array[18] ^ mac_array[16] ^ mac_array[14] ^ mac_array[12] ^
2050 mac_array[8] ^ mac_array[7] ^ mac_array[6] ^ mac_array[0];
2052 crc[1] = mac_array[46] ^ mac_array[45] ^ mac_array[44] ^ mac_array[43] ^
2053 mac_array[41] ^ mac_array[39] ^ mac_array[36] ^ mac_array[34] ^
2054 mac_array[32] ^ mac_array[30] ^ mac_array[29] ^ mac_array[28] ^
2055 mac_array[24] ^ mac_array[23] ^ mac_array[22] ^ mac_array[21] ^
2056 mac_array[20] ^ mac_array[18] ^ mac_array[17] ^ mac_array[16] ^
2057 mac_array[15] ^ mac_array[14] ^ mac_array[13] ^ mac_array[12] ^
2058 mac_array[9] ^ mac_array[6] ^ mac_array[1] ^ mac_array[0];
2060 crc[2] = mac_array[47] ^ mac_array[46] ^ mac_array[44] ^ mac_array[43] ^
2061 mac_array[42] ^ mac_array[39] ^ mac_array[37] ^ mac_array[34] ^
2062 mac_array[33] ^ mac_array[29] ^ mac_array[28] ^ mac_array[25] ^
2063 mac_array[24] ^ mac_array[22] ^ mac_array[17] ^ mac_array[15] ^
2064 mac_array[13] ^ mac_array[12] ^ mac_array[10] ^ mac_array[8] ^
2065 mac_array[6] ^ mac_array[2] ^ mac_array[1] ^ mac_array[0];
2067 crc[3] = mac_array[47] ^ mac_array[45] ^ mac_array[44] ^ mac_array[43] ^
2068 mac_array[40] ^ mac_array[38] ^ mac_array[35] ^ mac_array[34] ^
2069 mac_array[30] ^ mac_array[29] ^ mac_array[26] ^ mac_array[25] ^
2070 mac_array[23] ^ mac_array[18] ^ mac_array[16] ^ mac_array[14] ^
2071 mac_array[13] ^ mac_array[11] ^ mac_array[9] ^ mac_array[7] ^
2072 mac_array[3] ^ mac_array[2] ^ mac_array[1];
2074 crc[4] = mac_array[46] ^ mac_array[45] ^ mac_array[44] ^ mac_array[41] ^
2075 mac_array[39] ^ mac_array[36] ^ mac_array[35] ^ mac_array[31] ^
2076 mac_array[30] ^ mac_array[27] ^ mac_array[26] ^ mac_array[24] ^
2077 mac_array[19] ^ mac_array[17] ^ mac_array[15] ^ mac_array[14] ^
2078 mac_array[12] ^ mac_array[10] ^ mac_array[8] ^ mac_array[4] ^
2079 mac_array[3] ^ mac_array[2];
2081 crc[5] = mac_array[47] ^ mac_array[46] ^ mac_array[45] ^ mac_array[42] ^
2082 mac_array[40] ^ mac_array[37] ^ mac_array[36] ^ mac_array[32] ^
2083 mac_array[31] ^ mac_array[28] ^ mac_array[27] ^ mac_array[25] ^
2084 mac_array[20] ^ mac_array[18] ^ mac_array[16] ^ mac_array[15] ^
2085 mac_array[13] ^ mac_array[11] ^ mac_array[9] ^ mac_array[5] ^
2086 mac_array[4] ^ mac_array[3];
2088 crc[6] = mac_array[47] ^ mac_array[46] ^ mac_array[43] ^ mac_array[41] ^
2089 mac_array[38] ^ mac_array[37] ^ mac_array[33] ^ mac_array[32] ^
2090 mac_array[29] ^ mac_array[28] ^ mac_array[26] ^ mac_array[21] ^
2091 mac_array[19] ^ mac_array[17] ^ mac_array[16] ^ mac_array[14] ^
2092 mac_array[12] ^ mac_array[10] ^ mac_array[6] ^ mac_array[5] ^
2095 crc[7] = mac_array[47] ^ mac_array[44] ^ mac_array[42] ^ mac_array[39] ^
2096 mac_array[38] ^ mac_array[34] ^ mac_array[33] ^ mac_array[30] ^
2097 mac_array[29] ^ mac_array[27] ^ mac_array[22] ^ mac_array[20] ^
2098 mac_array[18] ^ mac_array[17] ^ mac_array[15] ^ mac_array[13] ^
2099 mac_array[11] ^ mac_array[7] ^ mac_array[6] ^ mac_array[5];
2101 for (i = 0; i < 8; i++)
2102 crc_result = crc_result | (crc[i] << i);
2104 table = MV643XX_ETH_DA_FILTER_OTHER_MULTICAST_TABLE_BASE(eth_port_num);
2105 eth_port_set_filter_table_entry(table, crc_result);
2109 * Set the entire multicast list based on dev->mc_list.
2111 static void eth_port_set_multicast_list(struct net_device *dev)
2114 struct dev_mc_list *mc_list;
2117 struct mv643xx_private *mp = netdev_priv(dev);
2118 unsigned int eth_port_num = mp->port_num;
2120 /* If the device is in promiscuous mode or in all multicast mode,
2121 * we will fully populate both multicast tables with accept.
2122 * This is guaranteed to yield a match on all multicast addresses...
2124 if ((dev->flags & IFF_PROMISC) || (dev->flags & IFF_ALLMULTI)) {
2125 for (table_index = 0; table_index <= 0xFC; table_index += 4) {
2126 /* Set all entries in DA filter special multicast
2128 * Set for ETH_Q0 for now
2130 * 0 Accept=1, Drop=0
2131 * 3-1 Queue ETH_Q0=0
2134 mv_write(MV643XX_ETH_DA_FILTER_SPECIAL_MULTICAST_TABLE_BASE(eth_port_num) + table_index, 0x01010101);
2136 /* Set all entries in DA filter other multicast
2138 * Set for ETH_Q0 for now
2140 * 0 Accept=1, Drop=0
2141 * 3-1 Queue ETH_Q0=0
2144 mv_write(MV643XX_ETH_DA_FILTER_OTHER_MULTICAST_TABLE_BASE(eth_port_num) + table_index, 0x01010101);
2149 /* We will clear out multicast tables every time we get the list.
2150 * Then add the entire new list...
2152 for (table_index = 0; table_index <= 0xFC; table_index += 4) {
2153 /* Clear DA filter special multicast table (Ex_dFSMT) */
2154 mv_write(MV643XX_ETH_DA_FILTER_SPECIAL_MULTICAST_TABLE_BASE
2155 (eth_port_num) + table_index, 0);
2157 /* Clear DA filter other multicast table (Ex_dFOMT) */
2158 mv_write(MV643XX_ETH_DA_FILTER_OTHER_MULTICAST_TABLE_BASE
2159 (eth_port_num) + table_index, 0);
2162 /* Get pointer to net_device multicast list and add each one... */
2163 for (i = 0, mc_list = dev->mc_list;
2164 (i < 256) && (mc_list != NULL) && (i < dev->mc_count);
2165 i++, mc_list = mc_list->next)
2166 if (mc_list->dmi_addrlen == 6)
2167 eth_port_mc_addr(eth_port_num, mc_list->dmi_addr);
2171 * eth_port_init_mac_tables - Clear all entrance in the UC, SMC and OMC tables
2174 * Go through all the DA filter tables (Unicast, Special Multicast &
2175 * Other Multicast) and set each entry to 0.
2178 * unsigned int eth_port_num Ethernet Port number.
2181 * Multicast and Unicast packets are rejected.
2186 static void eth_port_init_mac_tables(unsigned int eth_port_num)
2190 /* Clear DA filter unicast table (Ex_dFUT) */
2191 for (table_index = 0; table_index <= 0xC; table_index += 4)
2192 mv_write(MV643XX_ETH_DA_FILTER_UNICAST_TABLE_BASE
2193 (eth_port_num) + table_index, 0);
2195 for (table_index = 0; table_index <= 0xFC; table_index += 4) {
2196 /* Clear DA filter special multicast table (Ex_dFSMT) */
2197 mv_write(MV643XX_ETH_DA_FILTER_SPECIAL_MULTICAST_TABLE_BASE
2198 (eth_port_num) + table_index, 0);
2199 /* Clear DA filter other multicast table (Ex_dFOMT) */
2200 mv_write(MV643XX_ETH_DA_FILTER_OTHER_MULTICAST_TABLE_BASE
2201 (eth_port_num) + table_index, 0);
2206 * eth_clear_mib_counters - Clear all MIB counters
2209 * This function clears all MIB counters of a specific ethernet port.
2210 * A read from the MIB counter will reset the counter.
2213 * unsigned int eth_port_num Ethernet Port number.
2216 * After reading all MIB counters, the counters resets.
2219 * MIB counter value.
2222 static void eth_clear_mib_counters(unsigned int eth_port_num)
2226 /* Perform dummy reads from MIB counters */
2227 for (i = ETH_MIB_GOOD_OCTETS_RECEIVED_LOW; i < ETH_MIB_LATE_COLLISION;
2229 mv_read(MV643XX_ETH_MIB_COUNTERS_BASE(eth_port_num) + i);
2232 static inline u32 read_mib(struct mv643xx_private *mp, int offset)
2234 return mv_read(MV643XX_ETH_MIB_COUNTERS_BASE(mp->port_num) + offset);
2237 static void eth_update_mib_counters(struct mv643xx_private *mp)
2239 struct mv643xx_mib_counters *p = &mp->mib_counters;
2242 p->good_octets_received +=
2243 read_mib(mp, ETH_MIB_GOOD_OCTETS_RECEIVED_LOW);
2244 p->good_octets_received +=
2245 (u64)read_mib(mp, ETH_MIB_GOOD_OCTETS_RECEIVED_HIGH) << 32;
2247 for (offset = ETH_MIB_BAD_OCTETS_RECEIVED;
2248 offset <= ETH_MIB_FRAMES_1024_TO_MAX_OCTETS;
2250 *(u32 *)((char *)p + offset) = read_mib(mp, offset);
2252 p->good_octets_sent += read_mib(mp, ETH_MIB_GOOD_OCTETS_SENT_LOW);
2253 p->good_octets_sent +=
2254 (u64)read_mib(mp, ETH_MIB_GOOD_OCTETS_SENT_HIGH) << 32;
2256 for (offset = ETH_MIB_GOOD_FRAMES_SENT;
2257 offset <= ETH_MIB_LATE_COLLISION;
2259 *(u32 *)((char *)p + offset) = read_mib(mp, offset);
2263 * ethernet_phy_detect - Detect whether a phy is present
2266 * This function tests whether there is a PHY present on
2267 * the specified port.
2270 * unsigned int eth_port_num Ethernet Port number.
2277 * -ENODEV on failure
2280 static int ethernet_phy_detect(unsigned int port_num)
2282 unsigned int phy_reg_data0;
2285 eth_port_read_smi_reg(port_num, 0, &phy_reg_data0);
2286 auto_neg = phy_reg_data0 & 0x1000;
2287 phy_reg_data0 ^= 0x1000; /* invert auto_neg */
2288 eth_port_write_smi_reg(port_num, 0, phy_reg_data0);
2290 eth_port_read_smi_reg(port_num, 0, &phy_reg_data0);
2291 if ((phy_reg_data0 & 0x1000) == auto_neg)
2292 return -ENODEV; /* change didn't take */
2294 phy_reg_data0 ^= 0x1000;
2295 eth_port_write_smi_reg(port_num, 0, phy_reg_data0);
2300 * ethernet_phy_get - Get the ethernet port PHY address.
2303 * This routine returns the given ethernet port PHY address.
2306 * unsigned int eth_port_num Ethernet Port number.
2315 static int ethernet_phy_get(unsigned int eth_port_num)
2317 unsigned int reg_data;
2319 reg_data = mv_read(MV643XX_ETH_PHY_ADDR_REG);
2321 return ((reg_data >> (5 * eth_port_num)) & 0x1f);
2325 * ethernet_phy_set - Set the ethernet port PHY address.
2328 * This routine sets the given ethernet port PHY address.
2331 * unsigned int eth_port_num Ethernet Port number.
2332 * int phy_addr PHY address.
2341 static void ethernet_phy_set(unsigned int eth_port_num, int phy_addr)
2344 int addr_shift = 5 * eth_port_num;
2346 reg_data = mv_read(MV643XX_ETH_PHY_ADDR_REG);
2347 reg_data &= ~(0x1f << addr_shift);
2348 reg_data |= (phy_addr & 0x1f) << addr_shift;
2349 mv_write(MV643XX_ETH_PHY_ADDR_REG, reg_data);
2353 * ethernet_phy_reset - Reset Ethernet port PHY.
2356 * This routine utilizes the SMI interface to reset the ethernet port PHY.
2359 * unsigned int eth_port_num Ethernet Port number.
2368 static void ethernet_phy_reset(unsigned int eth_port_num)
2370 unsigned int phy_reg_data;
2373 eth_port_read_smi_reg(eth_port_num, 0, &phy_reg_data);
2374 phy_reg_data |= 0x8000; /* Set bit 15 to reset the PHY */
2375 eth_port_write_smi_reg(eth_port_num, 0, phy_reg_data);
2377 /* wait for PHY to come out of reset */
2380 eth_port_read_smi_reg(eth_port_num, 0, &phy_reg_data);
2381 } while (phy_reg_data & 0x8000);
2384 static void mv643xx_eth_port_enable_tx(unsigned int port_num,
2385 unsigned int queues)
2387 mv_write(MV643XX_ETH_TRANSMIT_QUEUE_COMMAND_REG(port_num), queues);
2390 static void mv643xx_eth_port_enable_rx(unsigned int port_num,
2391 unsigned int queues)
2393 mv_write(MV643XX_ETH_RECEIVE_QUEUE_COMMAND_REG(port_num), queues);
2396 static unsigned int mv643xx_eth_port_disable_tx(unsigned int port_num)
2400 /* Stop Tx port activity. Check port Tx activity. */
2401 queues = mv_read(MV643XX_ETH_TRANSMIT_QUEUE_COMMAND_REG(port_num))
2404 /* Issue stop command for active queues only */
2405 mv_write(MV643XX_ETH_TRANSMIT_QUEUE_COMMAND_REG(port_num),
2408 /* Wait for all Tx activity to terminate. */
2409 /* Check port cause register that all Tx queues are stopped */
2410 while (mv_read(MV643XX_ETH_TRANSMIT_QUEUE_COMMAND_REG(port_num))
2412 udelay(PHY_WAIT_MICRO_SECONDS);
2414 /* Wait for Tx FIFO to empty */
2415 while (mv_read(MV643XX_ETH_PORT_STATUS_REG(port_num)) &
2416 ETH_PORT_TX_FIFO_EMPTY)
2417 udelay(PHY_WAIT_MICRO_SECONDS);
2423 static unsigned int mv643xx_eth_port_disable_rx(unsigned int port_num)
2427 /* Stop Rx port activity. Check port Rx activity. */
2428 queues = mv_read(MV643XX_ETH_RECEIVE_QUEUE_COMMAND_REG(port_num))
2431 /* Issue stop command for active queues only */
2432 mv_write(MV643XX_ETH_RECEIVE_QUEUE_COMMAND_REG(port_num),
2435 /* Wait for all Rx activity to terminate. */
2436 /* Check port cause register that all Rx queues are stopped */
2437 while (mv_read(MV643XX_ETH_RECEIVE_QUEUE_COMMAND_REG(port_num))
2439 udelay(PHY_WAIT_MICRO_SECONDS);
2446 * eth_port_reset - Reset Ethernet port
2449 * This routine resets the chip by aborting any SDMA engine activity and
2450 * clearing the MIB counters. The Receiver and the Transmit unit are in
2451 * idle state after this command is performed and the port is disabled.
2454 * unsigned int eth_port_num Ethernet Port number.
2457 * Channel activity is halted.
2463 static void eth_port_reset(unsigned int port_num)
2465 unsigned int reg_data;
2467 mv643xx_eth_port_disable_tx(port_num);
2468 mv643xx_eth_port_disable_rx(port_num);
2470 /* Clear all MIB counters */
2471 eth_clear_mib_counters(port_num);
2473 /* Reset the Enable bit in the Configuration Register */
2474 reg_data = mv_read(MV643XX_ETH_PORT_SERIAL_CONTROL_REG(port_num));
2475 reg_data &= ~(MV643XX_ETH_SERIAL_PORT_ENABLE |
2476 MV643XX_ETH_DO_NOT_FORCE_LINK_FAIL |
2477 MV643XX_ETH_FORCE_LINK_PASS);
2478 mv_write(MV643XX_ETH_PORT_SERIAL_CONTROL_REG(port_num), reg_data);
2483 * eth_port_read_smi_reg - Read PHY registers
2486 * This routine utilize the SMI interface to interact with the PHY in
2487 * order to perform PHY register read.
2490 * unsigned int port_num Ethernet Port number.
2491 * unsigned int phy_reg PHY register address offset.
2492 * unsigned int *value Register value buffer.
2495 * Write the value of a specified PHY register into given buffer.
2498 * false if the PHY is busy or read data is not in valid state.
2502 static void eth_port_read_smi_reg(unsigned int port_num,
2503 unsigned int phy_reg, unsigned int *value)
2505 int phy_addr = ethernet_phy_get(port_num);
2506 unsigned long flags;
2509 /* the SMI register is a shared resource */
2510 spin_lock_irqsave(&mv643xx_eth_phy_lock, flags);
2512 /* wait for the SMI register to become available */
2513 for (i = 0; mv_read(MV643XX_ETH_SMI_REG) & ETH_SMI_BUSY; i++) {
2514 if (i == PHY_WAIT_ITERATIONS) {
2515 printk("mv643xx PHY busy timeout, port %d\n", port_num);
2518 udelay(PHY_WAIT_MICRO_SECONDS);
2521 mv_write(MV643XX_ETH_SMI_REG,
2522 (phy_addr << 16) | (phy_reg << 21) | ETH_SMI_OPCODE_READ);
2524 /* now wait for the data to be valid */
2525 for (i = 0; !(mv_read(MV643XX_ETH_SMI_REG) & ETH_SMI_READ_VALID); i++) {
2526 if (i == PHY_WAIT_ITERATIONS) {
2527 printk("mv643xx PHY read timeout, port %d\n", port_num);
2530 udelay(PHY_WAIT_MICRO_SECONDS);
2533 *value = mv_read(MV643XX_ETH_SMI_REG) & 0xffff;
2535 spin_unlock_irqrestore(&mv643xx_eth_phy_lock, flags);
2539 * eth_port_write_smi_reg - Write to PHY registers
2542 * This routine utilize the SMI interface to interact with the PHY in
2543 * order to perform writes to PHY registers.
2546 * unsigned int eth_port_num Ethernet Port number.
2547 * unsigned int phy_reg PHY register address offset.
2548 * unsigned int value Register value.
2551 * Write the given value to the specified PHY register.
2554 * false if the PHY is busy.
2558 static void eth_port_write_smi_reg(unsigned int eth_port_num,
2559 unsigned int phy_reg, unsigned int value)
2563 unsigned long flags;
2565 phy_addr = ethernet_phy_get(eth_port_num);
2567 /* the SMI register is a shared resource */
2568 spin_lock_irqsave(&mv643xx_eth_phy_lock, flags);
2570 /* wait for the SMI register to become available */
2571 for (i = 0; mv_read(MV643XX_ETH_SMI_REG) & ETH_SMI_BUSY; i++) {
2572 if (i == PHY_WAIT_ITERATIONS) {
2573 printk("mv643xx PHY busy timeout, port %d\n",
2577 udelay(PHY_WAIT_MICRO_SECONDS);
2580 mv_write(MV643XX_ETH_SMI_REG, (phy_addr << 16) | (phy_reg << 21) |
2581 ETH_SMI_OPCODE_WRITE | (value & 0xffff));
2583 spin_unlock_irqrestore(&mv643xx_eth_phy_lock, flags);
2587 * Wrappers for MII support library.
2589 static int mv643xx_mdio_read(struct net_device *dev, int phy_id, int location)
2592 struct mv643xx_private *mp = netdev_priv(dev);
2594 eth_port_read_smi_reg(mp->port_num, location, &val);
2598 static void mv643xx_mdio_write(struct net_device *dev, int phy_id, int location, int val)
2600 struct mv643xx_private *mp = netdev_priv(dev);
2601 eth_port_write_smi_reg(mp->port_num, location, val);
2605 * eth_tx_return_desc - Free all used Tx descriptors
2608 * This routine returns the transmitted packet information to the caller.
2609 * It uses the 'first' index to support Tx desc return in case a transmit
2610 * of a packet spanned over multiple buffer still in process.
2611 * In case the Tx queue was in "resource error" condition, where there are
2612 * no available Tx resources, the function resets the resource error flag.
2615 * struct mv643xx_private *mp Ethernet Port Control srtuct.
2616 * struct pkt_info *p_pkt_info User packet buffer.
2619 * Tx ring 'first' and 'used' indexes are updated.
2623 * ETH_ERROR otherwise.
2626 static ETH_FUNC_RET_STATUS eth_tx_return_desc(struct mv643xx_private *mp,
2627 struct pkt_info *p_pkt_info)
2630 struct eth_tx_desc *p_tx_desc_used;
2631 unsigned int command_status;
2632 unsigned long flags;
2635 spin_lock_irqsave(&mp->lock, flags);
2637 BUG_ON(mp->tx_desc_count < 0);
2638 if (mp->tx_desc_count == 0) {
2639 /* no more tx descs in use */
2644 /* Get the Tx Desc ring indexes */
2645 tx_desc_used = mp->tx_used_desc_q;
2647 p_tx_desc_used = &mp->p_tx_desc_area[tx_desc_used];
2649 BUG_ON(p_tx_desc_used == NULL);
2651 command_status = p_tx_desc_used->cmd_sts;
2652 if (command_status & (ETH_BUFFER_OWNED_BY_DMA)) {
2653 /* Still transmitting... */
2658 /* Pass the packet information to the caller */
2659 p_pkt_info->cmd_sts = command_status;
2660 p_pkt_info->return_info = mp->tx_skb[tx_desc_used];
2661 p_pkt_info->buf_ptr = p_tx_desc_used->buf_ptr;
2662 p_pkt_info->byte_cnt = p_tx_desc_used->byte_cnt;
2663 mp->tx_skb[tx_desc_used] = NULL;
2665 /* Update the next descriptor to release. */
2666 mp->tx_used_desc_q = (tx_desc_used + 1) % mp->tx_ring_size;
2668 BUG_ON(mp->tx_desc_count == 0);
2669 mp->tx_desc_count--;
2672 spin_unlock_irqrestore(&mp->lock, flags);
2678 * eth_port_receive - Get received information from Rx ring.
2681 * This routine returns the received data to the caller. There is no
2682 * data copying during routine operation. All information is returned
2683 * using pointer to packet information struct passed from the caller.
2684 * If the routine exhausts Rx ring resources then the resource error flag
2688 * struct mv643xx_private *mp Ethernet Port Control srtuct.
2689 * struct pkt_info *p_pkt_info User packet buffer.
2692 * Rx ring current and used indexes are updated.
2695 * ETH_ERROR in case the routine can not access Rx desc ring.
2696 * ETH_QUEUE_FULL if Rx ring resources are exhausted.
2697 * ETH_END_OF_JOB if there is no received data.
2700 static ETH_FUNC_RET_STATUS eth_port_receive(struct mv643xx_private *mp,
2701 struct pkt_info *p_pkt_info)
2703 int rx_next_curr_desc, rx_curr_desc, rx_used_desc;
2704 volatile struct eth_rx_desc *p_rx_desc;
2705 unsigned int command_status;
2706 unsigned long flags;
2708 /* Do not process Rx ring in case of Rx ring resource error */
2709 if (mp->rx_resource_err)
2710 return ETH_QUEUE_FULL;
2712 spin_lock_irqsave(&mp->lock, flags);
2714 /* Get the Rx Desc ring 'curr and 'used' indexes */
2715 rx_curr_desc = mp->rx_curr_desc_q;
2716 rx_used_desc = mp->rx_used_desc_q;
2718 p_rx_desc = &mp->p_rx_desc_area[rx_curr_desc];
2720 /* The following parameters are used to save readings from memory */
2721 command_status = p_rx_desc->cmd_sts;
2724 /* Nothing to receive... */
2725 if (command_status & (ETH_BUFFER_OWNED_BY_DMA)) {
2726 spin_unlock_irqrestore(&mp->lock, flags);
2727 return ETH_END_OF_JOB;
2730 p_pkt_info->byte_cnt = (p_rx_desc->byte_cnt) - RX_BUF_OFFSET;
2731 p_pkt_info->cmd_sts = command_status;
2732 p_pkt_info->buf_ptr = (p_rx_desc->buf_ptr) + RX_BUF_OFFSET;
2733 p_pkt_info->return_info = mp->rx_skb[rx_curr_desc];
2734 p_pkt_info->l4i_chk = p_rx_desc->buf_size;
2737 * Clean the return info field to indicate that the
2738 * packet has been moved to the upper layers
2740 mp->rx_skb[rx_curr_desc] = NULL;
2742 /* Update current index in data structure */
2743 rx_next_curr_desc = (rx_curr_desc + 1) % mp->rx_ring_size;
2744 mp->rx_curr_desc_q = rx_next_curr_desc;
2746 /* Rx descriptors exhausted. Set the Rx ring resource error flag */
2747 if (rx_next_curr_desc == rx_used_desc)
2748 mp->rx_resource_err = 1;
2750 spin_unlock_irqrestore(&mp->lock, flags);
2756 * eth_rx_return_buff - Returns a Rx buffer back to the Rx ring.
2759 * This routine returns a Rx buffer back to the Rx ring. It retrieves the
2760 * next 'used' descriptor and attached the returned buffer to it.
2761 * In case the Rx ring was in "resource error" condition, where there are
2762 * no available Rx resources, the function resets the resource error flag.
2765 * struct mv643xx_private *mp Ethernet Port Control srtuct.
2766 * struct pkt_info *p_pkt_info Information on returned buffer.
2769 * New available Rx resource in Rx descriptor ring.
2772 * ETH_ERROR in case the routine can not access Rx desc ring.
2775 static ETH_FUNC_RET_STATUS eth_rx_return_buff(struct mv643xx_private *mp,
2776 struct pkt_info *p_pkt_info)
2778 int used_rx_desc; /* Where to return Rx resource */
2779 volatile struct eth_rx_desc *p_used_rx_desc;
2780 unsigned long flags;
2782 spin_lock_irqsave(&mp->lock, flags);
2784 /* Get 'used' Rx descriptor */
2785 used_rx_desc = mp->rx_used_desc_q;
2786 p_used_rx_desc = &mp->p_rx_desc_area[used_rx_desc];
2788 p_used_rx_desc->buf_ptr = p_pkt_info->buf_ptr;
2789 p_used_rx_desc->buf_size = p_pkt_info->byte_cnt;
2790 mp->rx_skb[used_rx_desc] = p_pkt_info->return_info;
2792 /* Flush the write pipe */
2794 /* Return the descriptor to DMA ownership */
2796 p_used_rx_desc->cmd_sts =
2797 ETH_BUFFER_OWNED_BY_DMA | ETH_RX_ENABLE_INTERRUPT;
2800 /* Move the used descriptor pointer to the next descriptor */
2801 mp->rx_used_desc_q = (used_rx_desc + 1) % mp->rx_ring_size;
2803 /* Any Rx return cancels the Rx resource error status */
2804 mp->rx_resource_err = 0;
2806 spin_unlock_irqrestore(&mp->lock, flags);
2811 /************* Begin ethtool support *************************/
2813 struct mv643xx_stats {
2814 char stat_string[ETH_GSTRING_LEN];
2819 #define MV643XX_STAT(m) sizeof(((struct mv643xx_private *)0)->m), \
2820 offsetof(struct mv643xx_private, m)
2822 static const struct mv643xx_stats mv643xx_gstrings_stats[] = {
2823 { "rx_packets", MV643XX_STAT(stats.rx_packets) },
2824 { "tx_packets", MV643XX_STAT(stats.tx_packets) },
2825 { "rx_bytes", MV643XX_STAT(stats.rx_bytes) },
2826 { "tx_bytes", MV643XX_STAT(stats.tx_bytes) },
2827 { "rx_errors", MV643XX_STAT(stats.rx_errors) },
2828 { "tx_errors", MV643XX_STAT(stats.tx_errors) },
2829 { "rx_dropped", MV643XX_STAT(stats.rx_dropped) },
2830 { "tx_dropped", MV643XX_STAT(stats.tx_dropped) },
2831 { "good_octets_received", MV643XX_STAT(mib_counters.good_octets_received) },
2832 { "bad_octets_received", MV643XX_STAT(mib_counters.bad_octets_received) },
2833 { "internal_mac_transmit_err", MV643XX_STAT(mib_counters.internal_mac_transmit_err) },
2834 { "good_frames_received", MV643XX_STAT(mib_counters.good_frames_received) },
2835 { "bad_frames_received", MV643XX_STAT(mib_counters.bad_frames_received) },
2836 { "broadcast_frames_received", MV643XX_STAT(mib_counters.broadcast_frames_received) },
2837 { "multicast_frames_received", MV643XX_STAT(mib_counters.multicast_frames_received) },
2838 { "frames_64_octets", MV643XX_STAT(mib_counters.frames_64_octets) },
2839 { "frames_65_to_127_octets", MV643XX_STAT(mib_counters.frames_65_to_127_octets) },
2840 { "frames_128_to_255_octets", MV643XX_STAT(mib_counters.frames_128_to_255_octets) },
2841 { "frames_256_to_511_octets", MV643XX_STAT(mib_counters.frames_256_to_511_octets) },
2842 { "frames_512_to_1023_octets", MV643XX_STAT(mib_counters.frames_512_to_1023_octets) },
2843 { "frames_1024_to_max_octets", MV643XX_STAT(mib_counters.frames_1024_to_max_octets) },
2844 { "good_octets_sent", MV643XX_STAT(mib_counters.good_octets_sent) },
2845 { "good_frames_sent", MV643XX_STAT(mib_counters.good_frames_sent) },
2846 { "excessive_collision", MV643XX_STAT(mib_counters.excessive_collision) },
2847 { "multicast_frames_sent", MV643XX_STAT(mib_counters.multicast_frames_sent) },
2848 { "broadcast_frames_sent", MV643XX_STAT(mib_counters.broadcast_frames_sent) },
2849 { "unrec_mac_control_received", MV643XX_STAT(mib_counters.unrec_mac_control_received) },
2850 { "fc_sent", MV643XX_STAT(mib_counters.fc_sent) },
2851 { "good_fc_received", MV643XX_STAT(mib_counters.good_fc_received) },
2852 { "bad_fc_received", MV643XX_STAT(mib_counters.bad_fc_received) },
2853 { "undersize_received", MV643XX_STAT(mib_counters.undersize_received) },
2854 { "fragments_received", MV643XX_STAT(mib_counters.fragments_received) },
2855 { "oversize_received", MV643XX_STAT(mib_counters.oversize_received) },
2856 { "jabber_received", MV643XX_STAT(mib_counters.jabber_received) },
2857 { "mac_receive_error", MV643XX_STAT(mib_counters.mac_receive_error) },
2858 { "bad_crc_event", MV643XX_STAT(mib_counters.bad_crc_event) },
2859 { "collision", MV643XX_STAT(mib_counters.collision) },
2860 { "late_collision", MV643XX_STAT(mib_counters.late_collision) },
2863 #define MV643XX_STATS_LEN \
2864 sizeof(mv643xx_gstrings_stats) / sizeof(struct mv643xx_stats)
2866 static void mv643xx_get_drvinfo(struct net_device *netdev,
2867 struct ethtool_drvinfo *drvinfo)
2869 strncpy(drvinfo->driver, mv643xx_driver_name, 32);
2870 strncpy(drvinfo->version, mv643xx_driver_version, 32);
2871 strncpy(drvinfo->fw_version, "N/A", 32);
2872 strncpy(drvinfo->bus_info, "mv643xx", 32);
2873 drvinfo->n_stats = MV643XX_STATS_LEN;
2876 static int mv643xx_get_stats_count(struct net_device *netdev)
2878 return MV643XX_STATS_LEN;
2881 static void mv643xx_get_ethtool_stats(struct net_device *netdev,
2882 struct ethtool_stats *stats, uint64_t *data)
2884 struct mv643xx_private *mp = netdev->priv;
2887 eth_update_mib_counters(mp);
2889 for (i = 0; i < MV643XX_STATS_LEN; i++) {
2890 char *p = (char *)mp+mv643xx_gstrings_stats[i].stat_offset;
2891 data[i] = (mv643xx_gstrings_stats[i].sizeof_stat ==
2892 sizeof(uint64_t)) ? *(uint64_t *)p : *(uint32_t *)p;
2896 static void mv643xx_get_strings(struct net_device *netdev, uint32_t stringset,
2903 for (i=0; i < MV643XX_STATS_LEN; i++) {
2904 memcpy(data + i * ETH_GSTRING_LEN,
2905 mv643xx_gstrings_stats[i].stat_string,
2912 static u32 mv643xx_eth_get_link(struct net_device *dev)
2914 struct mv643xx_private *mp = netdev_priv(dev);
2916 return mii_link_ok(&mp->mii);
2919 static int mv643xx_eth_nway_restart(struct net_device *dev)
2921 struct mv643xx_private *mp = netdev_priv(dev);
2923 return mii_nway_restart(&mp->mii);
2926 static int mv643xx_eth_do_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
2928 struct mv643xx_private *mp = netdev_priv(dev);
2930 return generic_mii_ioctl(&mp->mii, if_mii(ifr), cmd, NULL);
2933 static struct ethtool_ops mv643xx_ethtool_ops = {
2934 .get_settings = mv643xx_get_settings,
2935 .set_settings = mv643xx_set_settings,
2936 .get_drvinfo = mv643xx_get_drvinfo,
2937 .get_link = mv643xx_eth_get_link,
2938 .get_sg = ethtool_op_get_sg,
2939 .set_sg = ethtool_op_set_sg,
2940 .get_strings = mv643xx_get_strings,
2941 .get_stats_count = mv643xx_get_stats_count,
2942 .get_ethtool_stats = mv643xx_get_ethtool_stats,
2943 .get_strings = mv643xx_get_strings,
2944 .get_stats_count = mv643xx_get_stats_count,
2945 .get_ethtool_stats = mv643xx_get_ethtool_stats,
2946 .nway_reset = mv643xx_eth_nway_restart,
2949 /************* End ethtool support *************************/