2 * Copyright (c) 2004, 2005 Topspin Communications. All rights reserved.
3 * Copyright (c) 2005 Sun Microsystems, Inc. All rights reserved.
4 * Copyright (c) 2005 Mellanox Technologies. All rights reserved.
5 * Copyright (c) 2006, 2007 Cisco Systems, Inc. All rights reserved.
7 * This software is available to you under a choice of one of two
8 * licenses. You may choose to be licensed under the terms of the GNU
9 * General Public License (GPL) Version 2, available from the file
10 * COPYING in the main directory of this source tree, or the
11 * OpenIB.org BSD license below:
13 * Redistribution and use in source and binary forms, with or
14 * without modification, are permitted provided that the following
17 * - Redistributions of source code must retain the above
18 * copyright notice, this list of conditions and the following
21 * - Redistributions in binary form must reproduce the above
22 * copyright notice, this list of conditions and the following
23 * disclaimer in the documentation and/or other materials
24 * provided with the distribution.
26 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
27 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
28 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
29 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
30 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
31 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
32 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
36 #include <linux/module.h>
37 #include <linux/init.h>
38 #include <linux/errno.h>
39 #include <linux/pci.h>
40 #include <linux/dma-mapping.h>
42 #include <linux/mlx4/device.h>
43 #include <linux/mlx4/doorbell.h>
49 MODULE_AUTHOR("Roland Dreier");
50 MODULE_DESCRIPTION("Mellanox ConnectX HCA low-level driver");
51 MODULE_LICENSE("Dual BSD/GPL");
52 MODULE_VERSION(DRV_VERSION);
54 #ifdef CONFIG_MLX4_DEBUG
56 int mlx4_debug_level = 0;
57 module_param_named(debug_level, mlx4_debug_level, int, 0644);
58 MODULE_PARM_DESC(debug_level, "Enable debug tracing if > 0");
60 #endif /* CONFIG_MLX4_DEBUG */
65 module_param(msi_x, int, 0444);
66 MODULE_PARM_DESC(msi_x, "attempt to use MSI-X if nonzero");
68 #else /* CONFIG_PCI_MSI */
72 #endif /* CONFIG_PCI_MSI */
74 static char mlx4_version[] __devinitdata =
75 DRV_NAME ": Mellanox ConnectX core driver v"
76 DRV_VERSION " (" DRV_RELDATE ")\n";
78 static struct mlx4_profile default_profile = {
81 .rdmarc_per_qp = 1 << 4,
88 static int mlx4_dev_cap(struct mlx4_dev *dev, struct mlx4_dev_cap *dev_cap)
93 err = mlx4_QUERY_DEV_CAP(dev, dev_cap);
95 mlx4_err(dev, "QUERY_DEV_CAP command failed, aborting.\n");
99 if (dev_cap->min_page_sz > PAGE_SIZE) {
100 mlx4_err(dev, "HCA minimum page size of %d bigger than "
101 "kernel PAGE_SIZE of %ld, aborting.\n",
102 dev_cap->min_page_sz, PAGE_SIZE);
105 if (dev_cap->num_ports > MLX4_MAX_PORTS) {
106 mlx4_err(dev, "HCA has %d ports, but we only support %d, "
108 dev_cap->num_ports, MLX4_MAX_PORTS);
112 if (dev_cap->uar_size > pci_resource_len(dev->pdev, 2)) {
113 mlx4_err(dev, "HCA reported UAR size of 0x%x bigger than "
114 "PCI resource 2 size of 0x%llx, aborting.\n",
116 (unsigned long long) pci_resource_len(dev->pdev, 2));
120 dev->caps.num_ports = dev_cap->num_ports;
121 for (i = 1; i <= dev->caps.num_ports; ++i) {
122 dev->caps.vl_cap[i] = dev_cap->max_vl[i];
123 dev->caps.mtu_cap[i] = dev_cap->max_mtu[i];
124 dev->caps.gid_table_len[i] = dev_cap->max_gids[i];
125 dev->caps.pkey_table_len[i] = dev_cap->max_pkeys[i];
126 dev->caps.port_width_cap[i] = dev_cap->max_port_width[i];
129 dev->caps.num_uars = dev_cap->uar_size / PAGE_SIZE;
130 dev->caps.local_ca_ack_delay = dev_cap->local_ca_ack_delay;
131 dev->caps.bf_reg_size = dev_cap->bf_reg_size;
132 dev->caps.bf_regs_per_page = dev_cap->bf_regs_per_page;
133 dev->caps.max_sq_sg = dev_cap->max_sq_sg;
134 dev->caps.max_rq_sg = dev_cap->max_rq_sg;
135 dev->caps.max_wqes = dev_cap->max_qp_sz;
136 dev->caps.max_qp_init_rdma = dev_cap->max_requester_per_qp;
137 dev->caps.reserved_qps = dev_cap->reserved_qps;
138 dev->caps.max_srq_wqes = dev_cap->max_srq_sz;
139 dev->caps.max_srq_sge = dev_cap->max_rq_sg - 1;
140 dev->caps.reserved_srqs = dev_cap->reserved_srqs;
141 dev->caps.max_sq_desc_sz = dev_cap->max_sq_desc_sz;
142 dev->caps.max_rq_desc_sz = dev_cap->max_rq_desc_sz;
143 dev->caps.num_qp_per_mgm = MLX4_QP_PER_MGM;
145 * Subtract 1 from the limit because we need to allocate a
146 * spare CQE so the HCA HW can tell the difference between an
147 * empty CQ and a full CQ.
149 dev->caps.max_cqes = dev_cap->max_cq_sz - 1;
150 dev->caps.reserved_cqs = dev_cap->reserved_cqs;
151 dev->caps.reserved_eqs = dev_cap->reserved_eqs;
152 dev->caps.reserved_mtts = DIV_ROUND_UP(dev_cap->reserved_mtts,
153 MLX4_MTT_ENTRY_PER_SEG);
154 dev->caps.reserved_mrws = dev_cap->reserved_mrws;
155 dev->caps.reserved_uars = dev_cap->reserved_uars;
156 dev->caps.reserved_pds = dev_cap->reserved_pds;
157 dev->caps.mtt_entry_sz = MLX4_MTT_ENTRY_PER_SEG * dev_cap->mtt_entry_sz;
158 dev->caps.max_msg_sz = dev_cap->max_msg_sz;
159 dev->caps.page_size_cap = ~(u32) (dev_cap->min_page_sz - 1);
160 dev->caps.flags = dev_cap->flags;
161 dev->caps.stat_rate_support = dev_cap->stat_rate_support;
162 dev->caps.max_gso_sz = dev_cap->max_gso_sz;
167 static int mlx4_load_fw(struct mlx4_dev *dev)
169 struct mlx4_priv *priv = mlx4_priv(dev);
172 priv->fw.fw_icm = mlx4_alloc_icm(dev, priv->fw.fw_pages,
173 GFP_HIGHUSER | __GFP_NOWARN, 0);
174 if (!priv->fw.fw_icm) {
175 mlx4_err(dev, "Couldn't allocate FW area, aborting.\n");
179 err = mlx4_MAP_FA(dev, priv->fw.fw_icm);
181 mlx4_err(dev, "MAP_FA command failed, aborting.\n");
185 err = mlx4_RUN_FW(dev);
187 mlx4_err(dev, "RUN_FW command failed, aborting.\n");
197 mlx4_free_icm(dev, priv->fw.fw_icm, 0);
201 static int mlx4_init_cmpt_table(struct mlx4_dev *dev, u64 cmpt_base,
204 struct mlx4_priv *priv = mlx4_priv(dev);
207 err = mlx4_init_icm_table(dev, &priv->qp_table.cmpt_table,
209 ((u64) (MLX4_CMPT_TYPE_QP *
210 cmpt_entry_sz) << MLX4_CMPT_SHIFT),
211 cmpt_entry_sz, dev->caps.num_qps,
212 dev->caps.reserved_qps, 0, 0);
216 err = mlx4_init_icm_table(dev, &priv->srq_table.cmpt_table,
218 ((u64) (MLX4_CMPT_TYPE_SRQ *
219 cmpt_entry_sz) << MLX4_CMPT_SHIFT),
220 cmpt_entry_sz, dev->caps.num_srqs,
221 dev->caps.reserved_srqs, 0, 0);
225 err = mlx4_init_icm_table(dev, &priv->cq_table.cmpt_table,
227 ((u64) (MLX4_CMPT_TYPE_CQ *
228 cmpt_entry_sz) << MLX4_CMPT_SHIFT),
229 cmpt_entry_sz, dev->caps.num_cqs,
230 dev->caps.reserved_cqs, 0, 0);
234 err = mlx4_init_icm_table(dev, &priv->eq_table.cmpt_table,
236 ((u64) (MLX4_CMPT_TYPE_EQ *
237 cmpt_entry_sz) << MLX4_CMPT_SHIFT),
239 roundup_pow_of_two(MLX4_NUM_EQ +
240 dev->caps.reserved_eqs),
241 MLX4_NUM_EQ + dev->caps.reserved_eqs, 0, 0);
248 mlx4_cleanup_icm_table(dev, &priv->cq_table.cmpt_table);
251 mlx4_cleanup_icm_table(dev, &priv->srq_table.cmpt_table);
254 mlx4_cleanup_icm_table(dev, &priv->qp_table.cmpt_table);
260 static int mlx4_init_icm(struct mlx4_dev *dev, struct mlx4_dev_cap *dev_cap,
261 struct mlx4_init_hca_param *init_hca, u64 icm_size)
263 struct mlx4_priv *priv = mlx4_priv(dev);
267 err = mlx4_SET_ICM_SIZE(dev, icm_size, &aux_pages);
269 mlx4_err(dev, "SET_ICM_SIZE command failed, aborting.\n");
273 mlx4_dbg(dev, "%lld KB of HCA context requires %lld KB aux memory.\n",
274 (unsigned long long) icm_size >> 10,
275 (unsigned long long) aux_pages << 2);
277 priv->fw.aux_icm = mlx4_alloc_icm(dev, aux_pages,
278 GFP_HIGHUSER | __GFP_NOWARN, 0);
279 if (!priv->fw.aux_icm) {
280 mlx4_err(dev, "Couldn't allocate aux memory, aborting.\n");
284 err = mlx4_MAP_ICM_AUX(dev, priv->fw.aux_icm);
286 mlx4_err(dev, "MAP_ICM_AUX command failed, aborting.\n");
290 err = mlx4_init_cmpt_table(dev, init_hca->cmpt_base, dev_cap->cmpt_entry_sz);
292 mlx4_err(dev, "Failed to map cMPT context memory, aborting.\n");
296 err = mlx4_map_eq_icm(dev, init_hca->eqc_base);
298 mlx4_err(dev, "Failed to map EQ context memory, aborting.\n");
303 * Reserved MTT entries must be aligned up to a cacheline
304 * boundary, since the FW will write to them, while the driver
305 * writes to all other MTT entries. (The variable
306 * dev->caps.mtt_entry_sz below is really the MTT segment
307 * size, not the raw entry size)
309 dev->caps.reserved_mtts =
310 ALIGN(dev->caps.reserved_mtts * dev->caps.mtt_entry_sz,
311 dma_get_cache_alignment()) / dev->caps.mtt_entry_sz;
313 err = mlx4_init_icm_table(dev, &priv->mr_table.mtt_table,
315 dev->caps.mtt_entry_sz,
316 dev->caps.num_mtt_segs,
317 dev->caps.reserved_mtts, 1, 0);
319 mlx4_err(dev, "Failed to map MTT context memory, aborting.\n");
323 err = mlx4_init_icm_table(dev, &priv->mr_table.dmpt_table,
325 dev_cap->dmpt_entry_sz,
327 dev->caps.reserved_mrws, 1, 1);
329 mlx4_err(dev, "Failed to map dMPT context memory, aborting.\n");
333 err = mlx4_init_icm_table(dev, &priv->qp_table.qp_table,
335 dev_cap->qpc_entry_sz,
337 dev->caps.reserved_qps, 0, 0);
339 mlx4_err(dev, "Failed to map QP context memory, aborting.\n");
343 err = mlx4_init_icm_table(dev, &priv->qp_table.auxc_table,
345 dev_cap->aux_entry_sz,
347 dev->caps.reserved_qps, 0, 0);
349 mlx4_err(dev, "Failed to map AUXC context memory, aborting.\n");
353 err = mlx4_init_icm_table(dev, &priv->qp_table.altc_table,
355 dev_cap->altc_entry_sz,
357 dev->caps.reserved_qps, 0, 0);
359 mlx4_err(dev, "Failed to map ALTC context memory, aborting.\n");
363 err = mlx4_init_icm_table(dev, &priv->qp_table.rdmarc_table,
364 init_hca->rdmarc_base,
365 dev_cap->rdmarc_entry_sz << priv->qp_table.rdmarc_shift,
367 dev->caps.reserved_qps, 0, 0);
369 mlx4_err(dev, "Failed to map RDMARC context memory, aborting\n");
373 err = mlx4_init_icm_table(dev, &priv->cq_table.table,
375 dev_cap->cqc_entry_sz,
377 dev->caps.reserved_cqs, 0, 0);
379 mlx4_err(dev, "Failed to map CQ context memory, aborting.\n");
380 goto err_unmap_rdmarc;
383 err = mlx4_init_icm_table(dev, &priv->srq_table.table,
385 dev_cap->srq_entry_sz,
387 dev->caps.reserved_srqs, 0, 0);
389 mlx4_err(dev, "Failed to map SRQ context memory, aborting.\n");
394 * It's not strictly required, but for simplicity just map the
395 * whole multicast group table now. The table isn't very big
396 * and it's a lot easier than trying to track ref counts.
398 err = mlx4_init_icm_table(dev, &priv->mcg_table.table,
399 init_hca->mc_base, MLX4_MGM_ENTRY_SIZE,
400 dev->caps.num_mgms + dev->caps.num_amgms,
401 dev->caps.num_mgms + dev->caps.num_amgms,
404 mlx4_err(dev, "Failed to map MCG context memory, aborting.\n");
411 mlx4_cleanup_icm_table(dev, &priv->srq_table.table);
414 mlx4_cleanup_icm_table(dev, &priv->cq_table.table);
417 mlx4_cleanup_icm_table(dev, &priv->qp_table.rdmarc_table);
420 mlx4_cleanup_icm_table(dev, &priv->qp_table.altc_table);
423 mlx4_cleanup_icm_table(dev, &priv->qp_table.auxc_table);
426 mlx4_cleanup_icm_table(dev, &priv->qp_table.qp_table);
429 mlx4_cleanup_icm_table(dev, &priv->mr_table.dmpt_table);
432 mlx4_cleanup_icm_table(dev, &priv->mr_table.mtt_table);
435 mlx4_unmap_eq_icm(dev);
438 mlx4_cleanup_icm_table(dev, &priv->eq_table.cmpt_table);
439 mlx4_cleanup_icm_table(dev, &priv->cq_table.cmpt_table);
440 mlx4_cleanup_icm_table(dev, &priv->srq_table.cmpt_table);
441 mlx4_cleanup_icm_table(dev, &priv->qp_table.cmpt_table);
444 mlx4_UNMAP_ICM_AUX(dev);
447 mlx4_free_icm(dev, priv->fw.aux_icm, 0);
452 static void mlx4_free_icms(struct mlx4_dev *dev)
454 struct mlx4_priv *priv = mlx4_priv(dev);
456 mlx4_cleanup_icm_table(dev, &priv->mcg_table.table);
457 mlx4_cleanup_icm_table(dev, &priv->srq_table.table);
458 mlx4_cleanup_icm_table(dev, &priv->cq_table.table);
459 mlx4_cleanup_icm_table(dev, &priv->qp_table.rdmarc_table);
460 mlx4_cleanup_icm_table(dev, &priv->qp_table.altc_table);
461 mlx4_cleanup_icm_table(dev, &priv->qp_table.auxc_table);
462 mlx4_cleanup_icm_table(dev, &priv->qp_table.qp_table);
463 mlx4_cleanup_icm_table(dev, &priv->mr_table.dmpt_table);
464 mlx4_cleanup_icm_table(dev, &priv->mr_table.mtt_table);
465 mlx4_cleanup_icm_table(dev, &priv->eq_table.cmpt_table);
466 mlx4_cleanup_icm_table(dev, &priv->cq_table.cmpt_table);
467 mlx4_cleanup_icm_table(dev, &priv->srq_table.cmpt_table);
468 mlx4_cleanup_icm_table(dev, &priv->qp_table.cmpt_table);
469 mlx4_unmap_eq_icm(dev);
471 mlx4_UNMAP_ICM_AUX(dev);
472 mlx4_free_icm(dev, priv->fw.aux_icm, 0);
475 static void mlx4_close_hca(struct mlx4_dev *dev)
477 mlx4_CLOSE_HCA(dev, 0);
480 mlx4_free_icm(dev, mlx4_priv(dev)->fw.fw_icm, 0);
483 static int mlx4_init_hca(struct mlx4_dev *dev)
485 struct mlx4_priv *priv = mlx4_priv(dev);
486 struct mlx4_adapter adapter;
487 struct mlx4_dev_cap dev_cap;
488 struct mlx4_profile profile;
489 struct mlx4_init_hca_param init_hca;
493 err = mlx4_QUERY_FW(dev);
495 mlx4_err(dev, "QUERY_FW command failed, aborting.\n");
499 err = mlx4_load_fw(dev);
501 mlx4_err(dev, "Failed to start FW, aborting.\n");
505 err = mlx4_dev_cap(dev, &dev_cap);
507 mlx4_err(dev, "QUERY_DEV_CAP command failed, aborting.\n");
511 profile = default_profile;
513 icm_size = mlx4_make_profile(dev, &profile, &dev_cap, &init_hca);
514 if ((long long) icm_size < 0) {
519 init_hca.log_uar_sz = ilog2(dev->caps.num_uars);
521 err = mlx4_init_icm(dev, &dev_cap, &init_hca, icm_size);
525 err = mlx4_INIT_HCA(dev, &init_hca);
527 mlx4_err(dev, "INIT_HCA command failed, aborting.\n");
531 err = mlx4_QUERY_ADAPTER(dev, &adapter);
533 mlx4_err(dev, "QUERY_ADAPTER command failed, aborting.\n");
537 priv->eq_table.inta_pin = adapter.inta_pin;
538 memcpy(dev->board_id, adapter.board_id, sizeof dev->board_id);
550 mlx4_free_icm(dev, priv->fw.fw_icm, 0);
555 static int mlx4_setup_hca(struct mlx4_dev *dev)
557 struct mlx4_priv *priv = mlx4_priv(dev);
560 err = mlx4_init_uar_table(dev);
562 mlx4_err(dev, "Failed to initialize "
563 "user access region table, aborting.\n");
567 err = mlx4_uar_alloc(dev, &priv->driver_uar);
569 mlx4_err(dev, "Failed to allocate driver access region, "
571 goto err_uar_table_free;
574 priv->kar = ioremap(priv->driver_uar.pfn << PAGE_SHIFT, PAGE_SIZE);
576 mlx4_err(dev, "Couldn't map kernel access region, "
582 err = mlx4_init_pd_table(dev);
584 mlx4_err(dev, "Failed to initialize "
585 "protection domain table, aborting.\n");
589 err = mlx4_init_mr_table(dev);
591 mlx4_err(dev, "Failed to initialize "
592 "memory region table, aborting.\n");
593 goto err_pd_table_free;
596 err = mlx4_init_eq_table(dev);
598 mlx4_err(dev, "Failed to initialize "
599 "event queue table, aborting.\n");
600 goto err_mr_table_free;
603 err = mlx4_cmd_use_events(dev);
605 mlx4_err(dev, "Failed to switch to event-driven "
606 "firmware commands, aborting.\n");
607 goto err_eq_table_free;
612 if (dev->flags & MLX4_FLAG_MSI_X) {
613 mlx4_warn(dev, "NOP command failed to generate MSI-X "
614 "interrupt IRQ %d).\n",
615 priv->eq_table.eq[MLX4_EQ_ASYNC].irq);
616 mlx4_warn(dev, "Trying again without MSI-X.\n");
618 mlx4_err(dev, "NOP command failed to generate interrupt "
619 "(IRQ %d), aborting.\n",
620 priv->eq_table.eq[MLX4_EQ_ASYNC].irq);
621 mlx4_err(dev, "BIOS or ACPI interrupt routing problem?\n");
627 mlx4_dbg(dev, "NOP command IRQ test passed\n");
629 err = mlx4_init_cq_table(dev);
631 mlx4_err(dev, "Failed to initialize "
632 "completion queue table, aborting.\n");
636 err = mlx4_init_srq_table(dev);
638 mlx4_err(dev, "Failed to initialize "
639 "shared receive queue table, aborting.\n");
640 goto err_cq_table_free;
643 err = mlx4_init_qp_table(dev);
645 mlx4_err(dev, "Failed to initialize "
646 "queue pair table, aborting.\n");
647 goto err_srq_table_free;
650 err = mlx4_init_mcg_table(dev);
652 mlx4_err(dev, "Failed to initialize "
653 "multicast group table, aborting.\n");
654 goto err_qp_table_free;
660 mlx4_cleanup_qp_table(dev);
663 mlx4_cleanup_srq_table(dev);
666 mlx4_cleanup_cq_table(dev);
669 mlx4_cmd_use_polling(dev);
672 mlx4_cleanup_eq_table(dev);
675 mlx4_cleanup_mr_table(dev);
678 mlx4_cleanup_pd_table(dev);
684 mlx4_uar_free(dev, &priv->driver_uar);
687 mlx4_cleanup_uar_table(dev);
691 static void mlx4_enable_msi_x(struct mlx4_dev *dev)
693 struct mlx4_priv *priv = mlx4_priv(dev);
694 struct msix_entry entries[MLX4_NUM_EQ];
699 for (i = 0; i < MLX4_NUM_EQ; ++i)
700 entries[i].entry = i;
702 err = pci_enable_msix(dev->pdev, entries, ARRAY_SIZE(entries));
705 mlx4_info(dev, "Only %d MSI-X vectors available, "
706 "not using MSI-X\n", err);
710 for (i = 0; i < MLX4_NUM_EQ; ++i)
711 priv->eq_table.eq[i].irq = entries[i].vector;
713 dev->flags |= MLX4_FLAG_MSI_X;
718 for (i = 0; i < MLX4_NUM_EQ; ++i)
719 priv->eq_table.eq[i].irq = dev->pdev->irq;
722 static int __mlx4_init_one(struct pci_dev *pdev, const struct pci_device_id *id)
724 struct mlx4_priv *priv;
725 struct mlx4_dev *dev;
728 printk(KERN_INFO PFX "Initializing %s\n",
731 err = pci_enable_device(pdev);
733 dev_err(&pdev->dev, "Cannot enable PCI device, "
739 * Check for BARs. We expect 0: 1MB
741 if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM) ||
742 pci_resource_len(pdev, 0) != 1 << 20) {
743 dev_err(&pdev->dev, "Missing DCS, aborting.\n");
745 goto err_disable_pdev;
747 if (!(pci_resource_flags(pdev, 2) & IORESOURCE_MEM)) {
748 dev_err(&pdev->dev, "Missing UAR, aborting.\n");
750 goto err_disable_pdev;
753 err = pci_request_region(pdev, 0, DRV_NAME);
755 dev_err(&pdev->dev, "Cannot request control region, aborting.\n");
756 goto err_disable_pdev;
759 err = pci_request_region(pdev, 2, DRV_NAME);
761 dev_err(&pdev->dev, "Cannot request UAR region, aborting.\n");
762 goto err_release_bar0;
765 pci_set_master(pdev);
767 err = pci_set_dma_mask(pdev, DMA_64BIT_MASK);
769 dev_warn(&pdev->dev, "Warning: couldn't set 64-bit PCI DMA mask.\n");
770 err = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
772 dev_err(&pdev->dev, "Can't set PCI DMA mask, aborting.\n");
773 goto err_release_bar2;
776 err = pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK);
778 dev_warn(&pdev->dev, "Warning: couldn't set 64-bit "
779 "consistent PCI DMA mask.\n");
780 err = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
782 dev_err(&pdev->dev, "Can't set consistent PCI DMA mask, "
784 goto err_release_bar2;
788 priv = kzalloc(sizeof *priv, GFP_KERNEL);
790 dev_err(&pdev->dev, "Device struct alloc failed, "
793 goto err_release_bar2;
798 INIT_LIST_HEAD(&priv->ctx_list);
799 spin_lock_init(&priv->ctx_lock);
801 INIT_LIST_HEAD(&priv->pgdir_list);
802 mutex_init(&priv->pgdir_mutex);
805 * Now reset the HCA before we touch the PCI capabilities or
806 * attempt a firmware command, since a boot ROM may have left
807 * the HCA in an undefined state.
809 err = mlx4_reset(dev);
811 mlx4_err(dev, "Failed to reset HCA, aborting.\n");
815 if (mlx4_cmd_init(dev)) {
816 mlx4_err(dev, "Failed to init command interface, aborting.\n");
820 err = mlx4_init_hca(dev);
824 mlx4_enable_msi_x(dev);
826 err = mlx4_setup_hca(dev);
827 if (err == -EBUSY && (dev->flags & MLX4_FLAG_MSI_X)) {
828 dev->flags &= ~MLX4_FLAG_MSI_X;
829 pci_disable_msix(pdev);
830 err = mlx4_setup_hca(dev);
836 err = mlx4_register_device(dev);
840 pci_set_drvdata(pdev, dev);
845 mlx4_cleanup_mcg_table(dev);
846 mlx4_cleanup_qp_table(dev);
847 mlx4_cleanup_srq_table(dev);
848 mlx4_cleanup_cq_table(dev);
849 mlx4_cmd_use_polling(dev);
850 mlx4_cleanup_eq_table(dev);
851 mlx4_cleanup_mr_table(dev);
852 mlx4_cleanup_pd_table(dev);
853 mlx4_cleanup_uar_table(dev);
856 if (dev->flags & MLX4_FLAG_MSI_X)
857 pci_disable_msix(pdev);
862 mlx4_cmd_cleanup(dev);
868 pci_release_region(pdev, 2);
871 pci_release_region(pdev, 0);
874 pci_disable_device(pdev);
875 pci_set_drvdata(pdev, NULL);
879 static int __devinit mlx4_init_one(struct pci_dev *pdev,
880 const struct pci_device_id *id)
882 static int mlx4_version_printed;
884 if (!mlx4_version_printed) {
885 printk(KERN_INFO "%s", mlx4_version);
886 ++mlx4_version_printed;
889 return __mlx4_init_one(pdev, id);
892 static void mlx4_remove_one(struct pci_dev *pdev)
894 struct mlx4_dev *dev = pci_get_drvdata(pdev);
895 struct mlx4_priv *priv = mlx4_priv(dev);
899 mlx4_unregister_device(dev);
901 for (p = 1; p <= dev->caps.num_ports; ++p)
902 mlx4_CLOSE_PORT(dev, p);
904 mlx4_cleanup_mcg_table(dev);
905 mlx4_cleanup_qp_table(dev);
906 mlx4_cleanup_srq_table(dev);
907 mlx4_cleanup_cq_table(dev);
908 mlx4_cmd_use_polling(dev);
909 mlx4_cleanup_eq_table(dev);
910 mlx4_cleanup_mr_table(dev);
911 mlx4_cleanup_pd_table(dev);
914 mlx4_uar_free(dev, &priv->driver_uar);
915 mlx4_cleanup_uar_table(dev);
917 mlx4_cmd_cleanup(dev);
919 if (dev->flags & MLX4_FLAG_MSI_X)
920 pci_disable_msix(pdev);
923 pci_release_region(pdev, 2);
924 pci_release_region(pdev, 0);
925 pci_disable_device(pdev);
926 pci_set_drvdata(pdev, NULL);
930 int mlx4_restart_one(struct pci_dev *pdev)
932 mlx4_remove_one(pdev);
933 return __mlx4_init_one(pdev, NULL);
936 static struct pci_device_id mlx4_pci_table[] = {
937 { PCI_VDEVICE(MELLANOX, 0x6340) }, /* MT25408 "Hermon" SDR */
938 { PCI_VDEVICE(MELLANOX, 0x634a) }, /* MT25408 "Hermon" DDR */
939 { PCI_VDEVICE(MELLANOX, 0x6354) }, /* MT25408 "Hermon" QDR */
940 { PCI_VDEVICE(MELLANOX, 0x6732) }, /* MT25408 "Hermon" DDR PCIe gen2 */
941 { PCI_VDEVICE(MELLANOX, 0x673c) }, /* MT25408 "Hermon" QDR PCIe gen2 */
945 MODULE_DEVICE_TABLE(pci, mlx4_pci_table);
947 static struct pci_driver mlx4_driver = {
949 .id_table = mlx4_pci_table,
950 .probe = mlx4_init_one,
951 .remove = __devexit_p(mlx4_remove_one)
954 static int __init mlx4_init(void)
958 ret = mlx4_catas_init();
962 ret = pci_register_driver(&mlx4_driver);
963 return ret < 0 ? ret : 0;
966 static void __exit mlx4_cleanup(void)
968 pci_unregister_driver(&mlx4_driver);
969 mlx4_catas_cleanup();
972 module_init(mlx4_init);
973 module_exit(mlx4_cleanup);