2 * drivers/net/ibm_newemac/phy.c
4 * Driver for PowerPC 4xx on-chip ethernet controller, PHY support.
5 * Borrowed from sungem_phy.c, though I only kept the generic MII
8 * This file should be shared with other drivers or eventually
9 * merged as the "low level" part of miilib
11 * (c) 2003, Benjamin Herrenscmidt (benh@kernel.crashing.org)
12 * (c) 2004-2005, Eugene Surovegin <ebs@ebshome.net>
15 #include <linux/module.h>
16 #include <linux/kernel.h>
17 #include <linux/types.h>
18 #include <linux/netdevice.h>
19 #include <linux/mii.h>
20 #include <linux/ethtool.h>
21 #include <linux/delay.h>
26 static inline int phy_read(struct mii_phy *phy, int reg)
28 return phy->mdio_read(phy->dev, phy->address, reg);
31 static inline void phy_write(struct mii_phy *phy, int reg, int val)
33 phy->mdio_write(phy->dev, phy->address, reg, val);
36 int emac_mii_reset_phy(struct mii_phy *phy)
41 val = phy_read(phy, MII_BMCR);
42 val &= ~(BMCR_ISOLATE | BMCR_ANENABLE);
44 phy_write(phy, MII_BMCR, val);
49 val = phy_read(phy, MII_BMCR);
50 if (val >= 0 && (val & BMCR_RESET) == 0)
54 if ((val & BMCR_ISOLATE) && limit > 0)
55 phy_write(phy, MII_BMCR, val & ~BMCR_ISOLATE);
60 static int genmii_setup_aneg(struct mii_phy *phy, u32 advertise)
64 phy->autoneg = AUTONEG_ENABLE;
65 phy->speed = SPEED_10;
66 phy->duplex = DUPLEX_HALF;
67 phy->pause = phy->asym_pause = 0;
68 phy->advertising = advertise;
70 ctl = phy_read(phy, MII_BMCR);
73 ctl &= ~(BMCR_FULLDPLX | BMCR_SPEED100 | BMCR_SPEED1000 | BMCR_ANENABLE);
75 /* First clear the PHY */
76 phy_write(phy, MII_BMCR, ctl);
78 /* Setup standard advertise */
79 adv = phy_read(phy, MII_ADVERTISE);
82 adv &= ~(ADVERTISE_ALL | ADVERTISE_100BASE4 | ADVERTISE_PAUSE_CAP |
83 ADVERTISE_PAUSE_ASYM);
84 if (advertise & ADVERTISED_10baseT_Half)
85 adv |= ADVERTISE_10HALF;
86 if (advertise & ADVERTISED_10baseT_Full)
87 adv |= ADVERTISE_10FULL;
88 if (advertise & ADVERTISED_100baseT_Half)
89 adv |= ADVERTISE_100HALF;
90 if (advertise & ADVERTISED_100baseT_Full)
91 adv |= ADVERTISE_100FULL;
92 if (advertise & ADVERTISED_Pause)
93 adv |= ADVERTISE_PAUSE_CAP;
94 if (advertise & ADVERTISED_Asym_Pause)
95 adv |= ADVERTISE_PAUSE_ASYM;
96 phy_write(phy, MII_ADVERTISE, adv);
99 (SUPPORTED_1000baseT_Full | SUPPORTED_1000baseT_Half)) {
100 adv = phy_read(phy, MII_CTRL1000);
103 adv &= ~(ADVERTISE_1000FULL | ADVERTISE_1000HALF);
104 if (advertise & ADVERTISED_1000baseT_Full)
105 adv |= ADVERTISE_1000FULL;
106 if (advertise & ADVERTISED_1000baseT_Half)
107 adv |= ADVERTISE_1000HALF;
108 phy_write(phy, MII_CTRL1000, adv);
111 /* Start/Restart aneg */
112 ctl = phy_read(phy, MII_BMCR);
113 ctl |= (BMCR_ANENABLE | BMCR_ANRESTART);
114 phy_write(phy, MII_BMCR, ctl);
119 static int genmii_setup_forced(struct mii_phy *phy, int speed, int fd)
123 phy->autoneg = AUTONEG_DISABLE;
126 phy->pause = phy->asym_pause = 0;
128 ctl = phy_read(phy, MII_BMCR);
131 ctl &= ~(BMCR_FULLDPLX | BMCR_SPEED100 | BMCR_SPEED1000 | BMCR_ANENABLE);
133 /* First clear the PHY */
134 phy_write(phy, MII_BMCR, ctl | BMCR_RESET);
136 /* Select speed & duplex */
141 ctl |= BMCR_SPEED100;
144 ctl |= BMCR_SPEED1000;
149 if (fd == DUPLEX_FULL)
150 ctl |= BMCR_FULLDPLX;
151 phy_write(phy, MII_BMCR, ctl);
156 static int genmii_poll_link(struct mii_phy *phy)
160 /* Clear latched value with dummy read */
161 phy_read(phy, MII_BMSR);
162 status = phy_read(phy, MII_BMSR);
163 if (status < 0 || (status & BMSR_LSTATUS) == 0)
165 if (phy->autoneg == AUTONEG_ENABLE && !(status & BMSR_ANEGCOMPLETE))
170 static int genmii_read_link(struct mii_phy *phy)
172 if (phy->autoneg == AUTONEG_ENABLE) {
174 int lpa = phy_read(phy, MII_LPA) & phy_read(phy, MII_ADVERTISE);
179 (SUPPORTED_1000baseT_Full | SUPPORTED_1000baseT_Half)) {
180 int adv = phy_read(phy, MII_CTRL1000);
181 glpa = phy_read(phy, MII_STAT1000);
183 if (glpa < 0 || adv < 0)
189 phy->speed = SPEED_10;
190 phy->duplex = DUPLEX_HALF;
191 phy->pause = phy->asym_pause = 0;
193 if (glpa & (LPA_1000FULL | LPA_1000HALF)) {
194 phy->speed = SPEED_1000;
195 if (glpa & LPA_1000FULL)
196 phy->duplex = DUPLEX_FULL;
197 } else if (lpa & (LPA_100FULL | LPA_100HALF)) {
198 phy->speed = SPEED_100;
199 if (lpa & LPA_100FULL)
200 phy->duplex = DUPLEX_FULL;
201 } else if (lpa & LPA_10FULL)
202 phy->duplex = DUPLEX_FULL;
204 if (phy->duplex == DUPLEX_FULL) {
205 phy->pause = lpa & LPA_PAUSE_CAP ? 1 : 0;
206 phy->asym_pause = lpa & LPA_PAUSE_ASYM ? 1 : 0;
209 int bmcr = phy_read(phy, MII_BMCR);
213 if (bmcr & BMCR_FULLDPLX)
214 phy->duplex = DUPLEX_FULL;
216 phy->duplex = DUPLEX_HALF;
217 if (bmcr & BMCR_SPEED1000)
218 phy->speed = SPEED_1000;
219 else if (bmcr & BMCR_SPEED100)
220 phy->speed = SPEED_100;
222 phy->speed = SPEED_10;
224 phy->pause = phy->asym_pause = 0;
229 /* Generic implementation for most 10/100/1000 PHYs */
230 static struct mii_phy_ops generic_phy_ops = {
231 .setup_aneg = genmii_setup_aneg,
232 .setup_forced = genmii_setup_forced,
233 .poll_link = genmii_poll_link,
234 .read_link = genmii_read_link
237 static struct mii_phy_def genmii_phy_def = {
238 .phy_id = 0x00000000,
239 .phy_id_mask = 0x00000000,
240 .name = "Generic MII",
241 .ops = &generic_phy_ops
245 #define MII_CIS8201_10BTCSR 0x16
246 #define TENBTCSR_ECHO_DISABLE 0x2000
247 #define MII_CIS8201_EPCR 0x17
248 #define EPCR_MODE_MASK 0x3000
249 #define EPCR_GMII_MODE 0x0000
250 #define EPCR_RGMII_MODE 0x1000
251 #define EPCR_TBI_MODE 0x2000
252 #define EPCR_RTBI_MODE 0x3000
253 #define MII_CIS8201_ACSR 0x1c
254 #define ACSR_PIN_PRIO_SELECT 0x0004
256 static int cis8201_init(struct mii_phy *phy)
260 epcr = phy_read(phy, MII_CIS8201_EPCR);
264 epcr &= ~EPCR_MODE_MASK;
268 epcr |= EPCR_TBI_MODE;
271 epcr |= EPCR_RTBI_MODE;
274 epcr |= EPCR_GMII_MODE;
278 epcr |= EPCR_RGMII_MODE;
281 phy_write(phy, MII_CIS8201_EPCR, epcr);
283 /* MII regs override strap pins */
284 phy_write(phy, MII_CIS8201_ACSR,
285 phy_read(phy, MII_CIS8201_ACSR) | ACSR_PIN_PRIO_SELECT);
287 /* Disable TX_EN -> CRS echo mode, otherwise 10/HDX doesn't work */
288 phy_write(phy, MII_CIS8201_10BTCSR,
289 phy_read(phy, MII_CIS8201_10BTCSR) | TENBTCSR_ECHO_DISABLE);
294 static struct mii_phy_ops cis8201_phy_ops = {
295 .init = cis8201_init,
296 .setup_aneg = genmii_setup_aneg,
297 .setup_forced = genmii_setup_forced,
298 .poll_link = genmii_poll_link,
299 .read_link = genmii_read_link
302 static struct mii_phy_def cis8201_phy_def = {
303 .phy_id = 0x000fc410,
304 .phy_id_mask = 0x000ffff0,
305 .name = "CIS8201 Gigabit Ethernet",
306 .ops = &cis8201_phy_ops
309 static struct mii_phy_def bcm5248_phy_def = {
311 .phy_id = 0x0143bc00,
312 .phy_id_mask = 0x0ffffff0,
313 .name = "BCM5248 10/100 SMII Ethernet",
314 .ops = &generic_phy_ops
317 static int m88e1111_init(struct mii_phy *phy)
319 pr_debug("%s: Marvell 88E1111 Ethernet\n", __FUNCTION__);
320 phy_write(phy, 0x14, 0x0ce3);
321 phy_write(phy, 0x18, 0x4101);
322 phy_write(phy, 0x09, 0x0e00);
323 phy_write(phy, 0x04, 0x01e1);
324 phy_write(phy, 0x00, 0x9140);
325 phy_write(phy, 0x00, 0x1140);
330 static int et1011c_init(struct mii_phy *phy)
334 reg_short = (u16)(phy_read(phy, 0x16));
336 reg_short |= 0x6; /* RGMII Trace Delay*/
337 phy_write(phy, 0x16, reg_short);
339 reg_short = (u16)(phy_read(phy, 0x17));
340 reg_short &= ~(0x40);
341 phy_write(phy, 0x17, reg_short);
343 phy_write(phy, 0x1c, 0x74f0);
347 static struct mii_phy_ops et1011c_phy_ops = {
348 .init = et1011c_init,
349 .setup_aneg = genmii_setup_aneg,
350 .setup_forced = genmii_setup_forced,
351 .poll_link = genmii_poll_link,
352 .read_link = genmii_read_link
355 static struct mii_phy_def et1011c_phy_def = {
356 .phy_id = 0x0282f000,
357 .phy_id_mask = 0x0fffff00,
358 .name = "ET1011C Gigabit Ethernet",
359 .ops = &et1011c_phy_ops
366 static struct mii_phy_ops m88e1111_phy_ops = {
367 .init = m88e1111_init,
368 .setup_aneg = genmii_setup_aneg,
369 .setup_forced = genmii_setup_forced,
370 .poll_link = genmii_poll_link,
371 .read_link = genmii_read_link
374 static struct mii_phy_def m88e1111_phy_def = {
376 .phy_id = 0x01410CC0,
377 .phy_id_mask = 0x0ffffff0,
378 .name = "Marvell 88E1111 Ethernet",
379 .ops = &m88e1111_phy_ops,
382 static struct mii_phy_def *mii_phy_table[] = {
391 int emac_mii_phy_probe(struct mii_phy *phy, int address)
393 struct mii_phy_def *def;
397 phy->autoneg = AUTONEG_DISABLE;
398 phy->advertising = 0;
399 phy->address = address;
400 phy->speed = SPEED_10;
401 phy->duplex = DUPLEX_HALF;
402 phy->pause = phy->asym_pause = 0;
404 /* Take PHY out of isolate mode and reset it. */
405 if (emac_mii_reset_phy(phy))
408 /* Read ID and find matching entry */
409 id = (phy_read(phy, MII_PHYSID1) << 16) | phy_read(phy, MII_PHYSID2);
410 for (i = 0; (def = mii_phy_table[i]) != NULL; i++)
411 if ((id & def->phy_id_mask) == def->phy_id)
413 /* Should never be NULL (we have a generic entry), but... */
419 /* Determine PHY features if needed */
420 phy->features = def->features;
421 if (!phy->features) {
422 u16 bmsr = phy_read(phy, MII_BMSR);
423 if (bmsr & BMSR_ANEGCAPABLE)
424 phy->features |= SUPPORTED_Autoneg;
425 if (bmsr & BMSR_10HALF)
426 phy->features |= SUPPORTED_10baseT_Half;
427 if (bmsr & BMSR_10FULL)
428 phy->features |= SUPPORTED_10baseT_Full;
429 if (bmsr & BMSR_100HALF)
430 phy->features |= SUPPORTED_100baseT_Half;
431 if (bmsr & BMSR_100FULL)
432 phy->features |= SUPPORTED_100baseT_Full;
433 if (bmsr & BMSR_ESTATEN) {
434 u16 esr = phy_read(phy, MII_ESTATUS);
435 if (esr & ESTATUS_1000_TFULL)
436 phy->features |= SUPPORTED_1000baseT_Full;
437 if (esr & ESTATUS_1000_THALF)
438 phy->features |= SUPPORTED_1000baseT_Half;
440 phy->features |= SUPPORTED_MII;
443 /* Setup default advertising */
444 phy->advertising = phy->features;
449 MODULE_LICENSE("GPL");