2 * forcedeth: Ethernet driver for NVIDIA nForce media access controllers.
4 * Note: This driver is a cleanroom reimplementation based on reverse
5 * engineered documentation written by Carl-Daniel Hailfinger
6 * and Andrew de Quincey. It's neither supported nor endorsed
7 * by NVIDIA Corp. Use at your own risk.
9 * NVIDIA, nForce and other NVIDIA marks are trademarks or registered
10 * trademarks of NVIDIA Corporation in the United States and other
13 * Copyright (C) 2003,4 Manfred Spraul
14 * Copyright (C) 2004 Andrew de Quincey (wol support)
15 * Copyright (C) 2004 Carl-Daniel Hailfinger (invalid MAC handling, insane
16 * IRQ rate fixes, bigendian fixes, cleanups, verification)
17 * Copyright (c) 2004 NVIDIA Corporation
19 * This program is free software; you can redistribute it and/or modify
20 * it under the terms of the GNU General Public License as published by
21 * the Free Software Foundation; either version 2 of the License, or
22 * (at your option) any later version.
24 * This program is distributed in the hope that it will be useful,
25 * but WITHOUT ANY WARRANTY; without even the implied warranty of
26 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
27 * GNU General Public License for more details.
29 * You should have received a copy of the GNU General Public License
30 * along with this program; if not, write to the Free Software
31 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
34 * 0.01: 05 Oct 2003: First release that compiles without warnings.
35 * 0.02: 05 Oct 2003: Fix bug for nv_drain_tx: do not try to free NULL skbs.
36 * Check all PCI BARs for the register window.
37 * udelay added to mii_rw.
38 * 0.03: 06 Oct 2003: Initialize dev->irq.
39 * 0.04: 07 Oct 2003: Initialize np->lock, reduce handled irqs, add printks.
40 * 0.05: 09 Oct 2003: printk removed again, irq status print tx_timeout.
41 * 0.06: 10 Oct 2003: MAC Address read updated, pff flag generation updated,
43 * 0.07: 14 Oct 2003: Further irq mask updates.
44 * 0.08: 20 Oct 2003: rx_desc.Length initialization added, nv_alloc_rx refill
45 * added into irq handler, NULL check for drain_ring.
46 * 0.09: 20 Oct 2003: Basic link speed irq implementation. Only handle the
47 * requested interrupt sources.
48 * 0.10: 20 Oct 2003: First cleanup for release.
49 * 0.11: 21 Oct 2003: hexdump for tx added, rx buffer sizes increased.
50 * MAC Address init fix, set_multicast cleanup.
51 * 0.12: 23 Oct 2003: Cleanups for release.
52 * 0.13: 25 Oct 2003: Limit for concurrent tx packets increased to 10.
53 * Set link speed correctly. start rx before starting
54 * tx (nv_start_rx sets the link speed).
55 * 0.14: 25 Oct 2003: Nic dependant irq mask.
56 * 0.15: 08 Nov 2003: fix smp deadlock with set_multicast_list during
58 * 0.16: 15 Nov 2003: include file cleanup for ppc64, rx buffer size
59 * increased to 1628 bytes.
60 * 0.17: 16 Nov 2003: undo rx buffer size increase. Substract 1 from
62 * 0.18: 17 Nov 2003: fix oops due to late initialization of dev_stats
63 * 0.19: 29 Nov 2003: Handle RxNoBuf, detect & handle invalid mac
64 * addresses, really stop rx if already running
65 * in nv_start_rx, clean up a bit.
66 * 0.20: 07 Dec 2003: alloc fixes
67 * 0.21: 12 Jan 2004: additional alloc fix, nic polling fix.
68 * 0.22: 19 Jan 2004: reprogram timer to a sane rate, avoid lockup
70 * 0.23: 26 Jan 2004: various small cleanups
71 * 0.24: 27 Feb 2004: make driver even less anonymous in backtraces
72 * 0.25: 09 Mar 2004: wol support
73 * 0.26: 03 Jun 2004: netdriver specific annotation, sparse-related fixes
74 * 0.27: 19 Jun 2004: Gigabit support, new descriptor rings,
75 * added CK804/MCP04 device IDs, code fixes
76 * for registers, link status and other minor fixes.
77 * 0.28: 21 Jun 2004: Big cleanup, making driver mostly endian safe
78 * 0.29: 31 Aug 2004: Add backup timer for link change notification.
79 * 0.30: 25 Sep 2004: rx checksum support for nf 250 Gb. Add rx reset
80 * into nv_close, otherwise reenabling for wol can
81 * cause DMA to kfree'd memory.
82 * 0.31: 14 Nov 2004: ethtool support for getting/setting link
84 * 0.32: 16 Apr 2005: RX_ERROR4 handling added.
85 * 0.33: 16 May 2005: Support for MCP51 added.
86 * 0.34: 18 Jun 2005: Add DEV_NEED_LINKTIMER to all nForce nics.
87 * 0.35: 26 Jun 2005: Support for MCP55 added.
88 * 0.36: 28 Jul 2005: Add jumbo frame support.
91 * We suspect that on some hardware no TX done interrupts are generated.
92 * This means recovery from netif_stop_queue only happens if the hw timer
93 * interrupt fires (100 times/second, configurable with NVREG_POLL_DEFAULT)
94 * and the timer is active in the IRQMask, or if a rx packet arrives by chance.
95 * If your hardware reliably generates tx done interrupts, then you can remove
96 * DEV_NEED_TIMERIRQ from the driver_data flags.
97 * DEV_NEED_TIMERIRQ will not harm you on sane hardware, only generating a few
98 * superfluous timer interrupts from the nic.
100 #define FORCEDETH_VERSION "0.36"
101 #define DRV_NAME "forcedeth"
103 #include <linux/module.h>
104 #include <linux/types.h>
105 #include <linux/pci.h>
106 #include <linux/interrupt.h>
107 #include <linux/netdevice.h>
108 #include <linux/etherdevice.h>
109 #include <linux/delay.h>
110 #include <linux/spinlock.h>
111 #include <linux/ethtool.h>
112 #include <linux/timer.h>
113 #include <linux/skbuff.h>
114 #include <linux/mii.h>
115 #include <linux/random.h>
116 #include <linux/init.h>
117 #include <linux/if_vlan.h>
121 #include <asm/uaccess.h>
122 #include <asm/system.h>
125 #define dprintk printk
127 #define dprintk(x...) do { } while (0)
135 #define DEV_NEED_LASTPACKET1 0x0001 /* set LASTPACKET1 in tx flags */
136 #define DEV_IRQMASK_1 0x0002 /* use NVREG_IRQMASK_WANTED_1 for irq mask */
137 #define DEV_IRQMASK_2 0x0004 /* use NVREG_IRQMASK_WANTED_2 for irq mask */
138 #define DEV_NEED_TIMERIRQ 0x0008 /* set the timer irq flag in the irq mask */
139 #define DEV_NEED_LINKTIMER 0x0010 /* poll link settings. Relies on the timer irq */
142 NvRegIrqStatus = 0x000,
143 #define NVREG_IRQSTAT_MIIEVENT 0x040
144 #define NVREG_IRQSTAT_MASK 0x1ff
145 NvRegIrqMask = 0x004,
146 #define NVREG_IRQ_RX_ERROR 0x0001
147 #define NVREG_IRQ_RX 0x0002
148 #define NVREG_IRQ_RX_NOBUF 0x0004
149 #define NVREG_IRQ_TX_ERR 0x0008
150 #define NVREG_IRQ_TX2 0x0010
151 #define NVREG_IRQ_TIMER 0x0020
152 #define NVREG_IRQ_LINK 0x0040
153 #define NVREG_IRQ_TX1 0x0100
154 #define NVREG_IRQMASK_WANTED_1 0x005f
155 #define NVREG_IRQMASK_WANTED_2 0x0147
156 #define NVREG_IRQ_UNKNOWN (~(NVREG_IRQ_RX_ERROR|NVREG_IRQ_RX|NVREG_IRQ_RX_NOBUF|NVREG_IRQ_TX_ERR|NVREG_IRQ_TX2|NVREG_IRQ_TIMER|NVREG_IRQ_LINK|NVREG_IRQ_TX1))
158 NvRegUnknownSetupReg6 = 0x008,
159 #define NVREG_UNKSETUP6_VAL 3
162 * NVREG_POLL_DEFAULT is the interval length of the timer source on the nic
163 * NVREG_POLL_DEFAULT=97 would result in an interval length of 1 ms
165 NvRegPollingInterval = 0x00c,
166 #define NVREG_POLL_DEFAULT 970
168 #define NVREG_MISC1_HD 0x02
169 #define NVREG_MISC1_FORCE 0x3b0f3c
171 NvRegTransmitterControl = 0x084,
172 #define NVREG_XMITCTL_START 0x01
173 NvRegTransmitterStatus = 0x088,
174 #define NVREG_XMITSTAT_BUSY 0x01
176 NvRegPacketFilterFlags = 0x8c,
177 #define NVREG_PFF_ALWAYS 0x7F0008
178 #define NVREG_PFF_PROMISC 0x80
179 #define NVREG_PFF_MYADDR 0x20
181 NvRegOffloadConfig = 0x90,
182 #define NVREG_OFFLOAD_HOMEPHY 0x601
183 #define NVREG_OFFLOAD_NORMAL RX_NIC_BUFSIZE
184 NvRegReceiverControl = 0x094,
185 #define NVREG_RCVCTL_START 0x01
186 NvRegReceiverStatus = 0x98,
187 #define NVREG_RCVSTAT_BUSY 0x01
189 NvRegRandomSeed = 0x9c,
190 #define NVREG_RNDSEED_MASK 0x00ff
191 #define NVREG_RNDSEED_FORCE 0x7f00
192 #define NVREG_RNDSEED_FORCE2 0x2d00
193 #define NVREG_RNDSEED_FORCE3 0x7400
195 NvRegUnknownSetupReg1 = 0xA0,
196 #define NVREG_UNKSETUP1_VAL 0x16070f
197 NvRegUnknownSetupReg2 = 0xA4,
198 #define NVREG_UNKSETUP2_VAL 0x16
199 NvRegMacAddrA = 0xA8,
200 NvRegMacAddrB = 0xAC,
201 NvRegMulticastAddrA = 0xB0,
202 #define NVREG_MCASTADDRA_FORCE 0x01
203 NvRegMulticastAddrB = 0xB4,
204 NvRegMulticastMaskA = 0xB8,
205 NvRegMulticastMaskB = 0xBC,
207 NvRegPhyInterface = 0xC0,
208 #define PHY_RGMII 0x10000000
210 NvRegTxRingPhysAddr = 0x100,
211 NvRegRxRingPhysAddr = 0x104,
212 NvRegRingSizes = 0x108,
213 #define NVREG_RINGSZ_TXSHIFT 0
214 #define NVREG_RINGSZ_RXSHIFT 16
215 NvRegUnknownTransmitterReg = 0x10c,
216 NvRegLinkSpeed = 0x110,
217 #define NVREG_LINKSPEED_FORCE 0x10000
218 #define NVREG_LINKSPEED_10 1000
219 #define NVREG_LINKSPEED_100 100
220 #define NVREG_LINKSPEED_1000 50
221 #define NVREG_LINKSPEED_MASK (0xFFF)
222 NvRegUnknownSetupReg5 = 0x130,
223 #define NVREG_UNKSETUP5_BIT31 (1<<31)
224 NvRegUnknownSetupReg3 = 0x13c,
225 #define NVREG_UNKSETUP3_VAL1 0x200010
226 NvRegTxRxControl = 0x144,
227 #define NVREG_TXRXCTL_KICK 0x0001
228 #define NVREG_TXRXCTL_BIT1 0x0002
229 #define NVREG_TXRXCTL_BIT2 0x0004
230 #define NVREG_TXRXCTL_IDLE 0x0008
231 #define NVREG_TXRXCTL_RESET 0x0010
232 #define NVREG_TXRXCTL_RXCHECK 0x0400
233 NvRegMIIStatus = 0x180,
234 #define NVREG_MIISTAT_ERROR 0x0001
235 #define NVREG_MIISTAT_LINKCHANGE 0x0008
236 #define NVREG_MIISTAT_MASK 0x000f
237 #define NVREG_MIISTAT_MASK2 0x000f
238 NvRegUnknownSetupReg4 = 0x184,
239 #define NVREG_UNKSETUP4_VAL 8
241 NvRegAdapterControl = 0x188,
242 #define NVREG_ADAPTCTL_START 0x02
243 #define NVREG_ADAPTCTL_LINKUP 0x04
244 #define NVREG_ADAPTCTL_PHYVALID 0x40000
245 #define NVREG_ADAPTCTL_RUNNING 0x100000
246 #define NVREG_ADAPTCTL_PHYSHIFT 24
247 NvRegMIISpeed = 0x18c,
248 #define NVREG_MIISPEED_BIT8 (1<<8)
249 #define NVREG_MIIDELAY 5
250 NvRegMIIControl = 0x190,
251 #define NVREG_MIICTL_INUSE 0x08000
252 #define NVREG_MIICTL_WRITE 0x00400
253 #define NVREG_MIICTL_ADDRSHIFT 5
254 NvRegMIIData = 0x194,
255 NvRegWakeUpFlags = 0x200,
256 #define NVREG_WAKEUPFLAGS_VAL 0x7770
257 #define NVREG_WAKEUPFLAGS_BUSYSHIFT 24
258 #define NVREG_WAKEUPFLAGS_ENABLESHIFT 16
259 #define NVREG_WAKEUPFLAGS_D3SHIFT 12
260 #define NVREG_WAKEUPFLAGS_D2SHIFT 8
261 #define NVREG_WAKEUPFLAGS_D1SHIFT 4
262 #define NVREG_WAKEUPFLAGS_D0SHIFT 0
263 #define NVREG_WAKEUPFLAGS_ACCEPT_MAGPAT 0x01
264 #define NVREG_WAKEUPFLAGS_ACCEPT_WAKEUPPAT 0x02
265 #define NVREG_WAKEUPFLAGS_ACCEPT_LINKCHANGE 0x04
266 #define NVREG_WAKEUPFLAGS_ENABLE 0x1111
268 NvRegPatternCRC = 0x204,
269 NvRegPatternMask = 0x208,
270 NvRegPowerCap = 0x268,
271 #define NVREG_POWERCAP_D3SUPP (1<<30)
272 #define NVREG_POWERCAP_D2SUPP (1<<26)
273 #define NVREG_POWERCAP_D1SUPP (1<<25)
274 NvRegPowerState = 0x26c,
275 #define NVREG_POWERSTATE_POWEREDUP 0x8000
276 #define NVREG_POWERSTATE_VALID 0x0100
277 #define NVREG_POWERSTATE_MASK 0x0003
278 #define NVREG_POWERSTATE_D0 0x0000
279 #define NVREG_POWERSTATE_D1 0x0001
280 #define NVREG_POWERSTATE_D2 0x0002
281 #define NVREG_POWERSTATE_D3 0x0003
284 /* Big endian: should work, but is untested */
290 #define FLAG_MASK_V1 0xffff0000
291 #define FLAG_MASK_V2 0xffffc000
292 #define LEN_MASK_V1 (0xffffffff ^ FLAG_MASK_V1)
293 #define LEN_MASK_V2 (0xffffffff ^ FLAG_MASK_V2)
295 #define NV_TX_LASTPACKET (1<<16)
296 #define NV_TX_RETRYERROR (1<<19)
297 #define NV_TX_LASTPACKET1 (1<<24)
298 #define NV_TX_DEFERRED (1<<26)
299 #define NV_TX_CARRIERLOST (1<<27)
300 #define NV_TX_LATECOLLISION (1<<28)
301 #define NV_TX_UNDERFLOW (1<<29)
302 #define NV_TX_ERROR (1<<30)
303 #define NV_TX_VALID (1<<31)
305 #define NV_TX2_LASTPACKET (1<<29)
306 #define NV_TX2_RETRYERROR (1<<18)
307 #define NV_TX2_LASTPACKET1 (1<<23)
308 #define NV_TX2_DEFERRED (1<<25)
309 #define NV_TX2_CARRIERLOST (1<<26)
310 #define NV_TX2_LATECOLLISION (1<<27)
311 #define NV_TX2_UNDERFLOW (1<<28)
312 /* error and valid are the same for both */
313 #define NV_TX2_ERROR (1<<30)
314 #define NV_TX2_VALID (1<<31)
316 #define NV_RX_DESCRIPTORVALID (1<<16)
317 #define NV_RX_MISSEDFRAME (1<<17)
318 #define NV_RX_SUBSTRACT1 (1<<18)
319 #define NV_RX_ERROR1 (1<<23)
320 #define NV_RX_ERROR2 (1<<24)
321 #define NV_RX_ERROR3 (1<<25)
322 #define NV_RX_ERROR4 (1<<26)
323 #define NV_RX_CRCERR (1<<27)
324 #define NV_RX_OVERFLOW (1<<28)
325 #define NV_RX_FRAMINGERR (1<<29)
326 #define NV_RX_ERROR (1<<30)
327 #define NV_RX_AVAIL (1<<31)
329 #define NV_RX2_CHECKSUMMASK (0x1C000000)
330 #define NV_RX2_CHECKSUMOK1 (0x10000000)
331 #define NV_RX2_CHECKSUMOK2 (0x14000000)
332 #define NV_RX2_CHECKSUMOK3 (0x18000000)
333 #define NV_RX2_DESCRIPTORVALID (1<<29)
334 #define NV_RX2_SUBSTRACT1 (1<<25)
335 #define NV_RX2_ERROR1 (1<<18)
336 #define NV_RX2_ERROR2 (1<<19)
337 #define NV_RX2_ERROR3 (1<<20)
338 #define NV_RX2_ERROR4 (1<<21)
339 #define NV_RX2_CRCERR (1<<22)
340 #define NV_RX2_OVERFLOW (1<<23)
341 #define NV_RX2_FRAMINGERR (1<<24)
342 /* error and avail are the same for both */
343 #define NV_RX2_ERROR (1<<30)
344 #define NV_RX2_AVAIL (1<<31)
346 /* Miscelaneous hardware related defines: */
347 #define NV_PCI_REGSZ 0x270
349 /* various timeout delays: all in usec */
350 #define NV_TXRX_RESET_DELAY 4
351 #define NV_TXSTOP_DELAY1 10
352 #define NV_TXSTOP_DELAY1MAX 500000
353 #define NV_TXSTOP_DELAY2 100
354 #define NV_RXSTOP_DELAY1 10
355 #define NV_RXSTOP_DELAY1MAX 500000
356 #define NV_RXSTOP_DELAY2 100
357 #define NV_SETUP5_DELAY 5
358 #define NV_SETUP5_DELAYMAX 50000
359 #define NV_POWERUP_DELAY 5
360 #define NV_POWERUP_DELAYMAX 5000
361 #define NV_MIIBUSY_DELAY 50
362 #define NV_MIIPHY_DELAY 10
363 #define NV_MIIPHY_DELAYMAX 10000
365 #define NV_WAKEUPPATTERNS 5
366 #define NV_WAKEUPMASKENTRIES 4
368 /* General driver defaults */
369 #define NV_WATCHDOG_TIMEO (5*HZ)
374 * If your nic mysteriously hangs then try to reduce the limits
375 * to 1/0: It might be required to set NV_TX_LASTPACKET in the
376 * last valid ring entry. But this would be impossible to
377 * implement - probably a disassembly error.
379 #define TX_LIMIT_STOP 63
380 #define TX_LIMIT_START 62
382 /* rx/tx mac addr + type + vlan + align + slack*/
383 #define NV_RX_HEADERS (64)
384 /* even more slack. */
385 #define NV_RX_ALLOC_PAD (64)
387 /* maximum mtu size */
388 #define NV_PKTLIMIT_1 ETH_DATA_LEN /* hard limit not known */
389 #define NV_PKTLIMIT_2 9100 /* Actual limit according to NVidia: 9202 */
391 #define OOM_REFILL (1+HZ/20)
392 #define POLL_WAIT (1+HZ/100)
393 #define LINK_TIMEOUT (3*HZ)
397 * This field has two purposes:
398 * - Newer nics uses a different ring layout. The layout is selected by
399 * comparing np->desc_ver with DESC_VER_xy.
400 * - It contains bits that are forced on when writing to NvRegTxRxControl.
402 #define DESC_VER_1 0x0
403 #define DESC_VER_2 (0x02100|NVREG_TXRXCTL_RXCHECK)
406 #define PHY_OUI_MARVELL 0x5043
407 #define PHY_OUI_CICADA 0x03f1
408 #define PHYID1_OUI_MASK 0x03ff
409 #define PHYID1_OUI_SHFT 6
410 #define PHYID2_OUI_MASK 0xfc00
411 #define PHYID2_OUI_SHFT 10
412 #define PHY_INIT1 0x0f000
413 #define PHY_INIT2 0x0e00
414 #define PHY_INIT3 0x01000
415 #define PHY_INIT4 0x0200
416 #define PHY_INIT5 0x0004
417 #define PHY_INIT6 0x02000
418 #define PHY_GIGABIT 0x0100
420 #define PHY_TIMEOUT 0x1
421 #define PHY_ERROR 0x2
425 #define PHY_HALF 0x100
427 /* FIXME: MII defines that should be added to <linux/mii.h> */
428 #define MII_1000BT_CR 0x09
429 #define MII_1000BT_SR 0x0a
430 #define ADVERTISE_1000FULL 0x0200
431 #define ADVERTISE_1000HALF 0x0100
432 #define LPA_1000FULL 0x0800
433 #define LPA_1000HALF 0x0400
438 * All hardware access under dev->priv->lock, except the performance
440 * - rx is (pseudo-) lockless: it relies on the single-threading provided
441 * by the arch code for interrupts.
442 * - tx setup is lockless: it relies on dev->xmit_lock. Actual submission
443 * needs dev->priv->lock :-(
444 * - set_multicast_list: preparation lockless, relies on dev->xmit_lock.
447 /* in dev: base, irq */
452 * Locking: spin_lock(&np->lock); */
453 struct net_device_stats stats;
461 unsigned int phy_oui;
464 /* General data: RO fields */
465 dma_addr_t ring_addr;
466 struct pci_dev *pci_dev;
473 /* rx specific fields.
474 * Locking: Within irq hander or disable_irq+spin_lock(&np->lock);
476 struct ring_desc *rx_ring;
477 unsigned int cur_rx, refill_rx;
478 struct sk_buff *rx_skbuff[RX_RING];
479 dma_addr_t rx_dma[RX_RING];
480 unsigned int rx_buf_sz;
481 unsigned int pkt_limit;
482 struct timer_list oom_kick;
483 struct timer_list nic_poll;
485 /* media detection workaround.
486 * Locking: Within irq hander or disable_irq+spin_lock(&np->lock);
489 unsigned long link_timeout;
491 * tx specific fields.
493 struct ring_desc *tx_ring;
494 unsigned int next_tx, nic_tx;
495 struct sk_buff *tx_skbuff[TX_RING];
496 dma_addr_t tx_dma[TX_RING];
501 * Maximum number of loops until we assume that a bit in the irq mask
502 * is stuck. Overridable with module param.
504 static int max_interrupt_work = 5;
506 static inline struct fe_priv *get_nvpriv(struct net_device *dev)
508 return netdev_priv(dev);
511 static inline u8 __iomem *get_hwbase(struct net_device *dev)
513 return get_nvpriv(dev)->base;
516 static inline void pci_push(u8 __iomem *base)
518 /* force out pending posted writes */
522 static inline u32 nv_descr_getlength(struct ring_desc *prd, u32 v)
524 return le32_to_cpu(prd->FlagLen)
525 & ((v == DESC_VER_1) ? LEN_MASK_V1 : LEN_MASK_V2);
528 static int reg_delay(struct net_device *dev, int offset, u32 mask, u32 target,
529 int delay, int delaymax, const char *msg)
531 u8 __iomem *base = get_hwbase(dev);
542 } while ((readl(base + offset) & mask) != target);
546 #define MII_READ (-1)
547 /* mii_rw: read/write a register on the PHY.
549 * Caller must guarantee serialization
551 static int mii_rw(struct net_device *dev, int addr, int miireg, int value)
553 u8 __iomem *base = get_hwbase(dev);
557 writel(NVREG_MIISTAT_MASK, base + NvRegMIIStatus);
559 reg = readl(base + NvRegMIIControl);
560 if (reg & NVREG_MIICTL_INUSE) {
561 writel(NVREG_MIICTL_INUSE, base + NvRegMIIControl);
562 udelay(NV_MIIBUSY_DELAY);
565 reg = (addr << NVREG_MIICTL_ADDRSHIFT) | miireg;
566 if (value != MII_READ) {
567 writel(value, base + NvRegMIIData);
568 reg |= NVREG_MIICTL_WRITE;
570 writel(reg, base + NvRegMIIControl);
572 if (reg_delay(dev, NvRegMIIControl, NVREG_MIICTL_INUSE, 0,
573 NV_MIIPHY_DELAY, NV_MIIPHY_DELAYMAX, NULL)) {
574 dprintk(KERN_DEBUG "%s: mii_rw of reg %d at PHY %d timed out.\n",
575 dev->name, miireg, addr);
577 } else if (value != MII_READ) {
578 /* it was a write operation - fewer failures are detectable */
579 dprintk(KERN_DEBUG "%s: mii_rw wrote 0x%x to reg %d at PHY %d\n",
580 dev->name, value, miireg, addr);
582 } else if (readl(base + NvRegMIIStatus) & NVREG_MIISTAT_ERROR) {
583 dprintk(KERN_DEBUG "%s: mii_rw of reg %d at PHY %d failed.\n",
584 dev->name, miireg, addr);
587 retval = readl(base + NvRegMIIData);
588 dprintk(KERN_DEBUG "%s: mii_rw read from reg %d at PHY %d: 0x%x.\n",
589 dev->name, miireg, addr, retval);
595 static int phy_reset(struct net_device *dev)
597 struct fe_priv *np = get_nvpriv(dev);
599 unsigned int tries = 0;
601 miicontrol = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
602 miicontrol |= BMCR_RESET;
603 if (mii_rw(dev, np->phyaddr, MII_BMCR, miicontrol)) {
610 /* must wait till reset is deasserted */
611 while (miicontrol & BMCR_RESET) {
613 miicontrol = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
614 /* FIXME: 100 tries seem excessive */
621 static int phy_init(struct net_device *dev)
623 struct fe_priv *np = get_nvpriv(dev);
624 u8 __iomem *base = get_hwbase(dev);
625 u32 phyinterface, phy_reserved, mii_status, mii_control, mii_control_1000,reg;
627 /* set advertise register */
628 reg = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ);
629 reg |= (ADVERTISE_10HALF|ADVERTISE_10FULL|ADVERTISE_100HALF|ADVERTISE_100FULL|0x800|0x400);
630 if (mii_rw(dev, np->phyaddr, MII_ADVERTISE, reg)) {
631 printk(KERN_INFO "%s: phy write to advertise failed.\n", pci_name(np->pci_dev));
635 /* get phy interface type */
636 phyinterface = readl(base + NvRegPhyInterface);
638 /* see if gigabit phy */
639 mii_status = mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ);
640 if (mii_status & PHY_GIGABIT) {
641 np->gigabit = PHY_GIGABIT;
642 mii_control_1000 = mii_rw(dev, np->phyaddr, MII_1000BT_CR, MII_READ);
643 mii_control_1000 &= ~ADVERTISE_1000HALF;
644 if (phyinterface & PHY_RGMII)
645 mii_control_1000 |= ADVERTISE_1000FULL;
647 mii_control_1000 &= ~ADVERTISE_1000FULL;
649 if (mii_rw(dev, np->phyaddr, MII_1000BT_CR, mii_control_1000)) {
650 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
658 if (phy_reset(dev)) {
659 printk(KERN_INFO "%s: phy reset failed\n", pci_name(np->pci_dev));
663 /* phy vendor specific configuration */
664 if ((np->phy_oui == PHY_OUI_CICADA) && (phyinterface & PHY_RGMII) ) {
665 phy_reserved = mii_rw(dev, np->phyaddr, MII_RESV1, MII_READ);
666 phy_reserved &= ~(PHY_INIT1 | PHY_INIT2);
667 phy_reserved |= (PHY_INIT3 | PHY_INIT4);
668 if (mii_rw(dev, np->phyaddr, MII_RESV1, phy_reserved)) {
669 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
672 phy_reserved = mii_rw(dev, np->phyaddr, MII_NCONFIG, MII_READ);
673 phy_reserved |= PHY_INIT5;
674 if (mii_rw(dev, np->phyaddr, MII_NCONFIG, phy_reserved)) {
675 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
679 if (np->phy_oui == PHY_OUI_CICADA) {
680 phy_reserved = mii_rw(dev, np->phyaddr, MII_SREVISION, MII_READ);
681 phy_reserved |= PHY_INIT6;
682 if (mii_rw(dev, np->phyaddr, MII_SREVISION, phy_reserved)) {
683 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
688 /* restart auto negotiation */
689 mii_control = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
690 mii_control |= (BMCR_ANRESTART | BMCR_ANENABLE);
691 if (mii_rw(dev, np->phyaddr, MII_BMCR, mii_control)) {
698 static void nv_start_rx(struct net_device *dev)
700 struct fe_priv *np = get_nvpriv(dev);
701 u8 __iomem *base = get_hwbase(dev);
703 dprintk(KERN_DEBUG "%s: nv_start_rx\n", dev->name);
704 /* Already running? Stop it. */
705 if (readl(base + NvRegReceiverControl) & NVREG_RCVCTL_START) {
706 writel(0, base + NvRegReceiverControl);
709 writel(np->linkspeed, base + NvRegLinkSpeed);
711 writel(NVREG_RCVCTL_START, base + NvRegReceiverControl);
712 dprintk(KERN_DEBUG "%s: nv_start_rx to duplex %d, speed 0x%08x.\n",
713 dev->name, np->duplex, np->linkspeed);
717 static void nv_stop_rx(struct net_device *dev)
719 u8 __iomem *base = get_hwbase(dev);
721 dprintk(KERN_DEBUG "%s: nv_stop_rx\n", dev->name);
722 writel(0, base + NvRegReceiverControl);
723 reg_delay(dev, NvRegReceiverStatus, NVREG_RCVSTAT_BUSY, 0,
724 NV_RXSTOP_DELAY1, NV_RXSTOP_DELAY1MAX,
725 KERN_INFO "nv_stop_rx: ReceiverStatus remained busy");
727 udelay(NV_RXSTOP_DELAY2);
728 writel(0, base + NvRegLinkSpeed);
731 static void nv_start_tx(struct net_device *dev)
733 u8 __iomem *base = get_hwbase(dev);
735 dprintk(KERN_DEBUG "%s: nv_start_tx\n", dev->name);
736 writel(NVREG_XMITCTL_START, base + NvRegTransmitterControl);
740 static void nv_stop_tx(struct net_device *dev)
742 u8 __iomem *base = get_hwbase(dev);
744 dprintk(KERN_DEBUG "%s: nv_stop_tx\n", dev->name);
745 writel(0, base + NvRegTransmitterControl);
746 reg_delay(dev, NvRegTransmitterStatus, NVREG_XMITSTAT_BUSY, 0,
747 NV_TXSTOP_DELAY1, NV_TXSTOP_DELAY1MAX,
748 KERN_INFO "nv_stop_tx: TransmitterStatus remained busy");
750 udelay(NV_TXSTOP_DELAY2);
751 writel(0, base + NvRegUnknownTransmitterReg);
754 static void nv_txrx_reset(struct net_device *dev)
756 struct fe_priv *np = get_nvpriv(dev);
757 u8 __iomem *base = get_hwbase(dev);
759 dprintk(KERN_DEBUG "%s: nv_txrx_reset\n", dev->name);
760 writel(NVREG_TXRXCTL_BIT2 | NVREG_TXRXCTL_RESET | np->desc_ver, base + NvRegTxRxControl);
762 udelay(NV_TXRX_RESET_DELAY);
763 writel(NVREG_TXRXCTL_BIT2 | np->desc_ver, base + NvRegTxRxControl);
768 * nv_get_stats: dev->get_stats function
769 * Get latest stats value from the nic.
770 * Called with read_lock(&dev_base_lock) held for read -
771 * only synchronized against unregister_netdevice.
773 static struct net_device_stats *nv_get_stats(struct net_device *dev)
775 struct fe_priv *np = get_nvpriv(dev);
777 /* It seems that the nic always generates interrupts and doesn't
778 * accumulate errors internally. Thus the current values in np->stats
779 * are already up to date.
785 * nv_alloc_rx: fill rx ring entries.
786 * Return 1 if the allocations for the skbs failed and the
787 * rx engine is without Available descriptors
789 static int nv_alloc_rx(struct net_device *dev)
791 struct fe_priv *np = get_nvpriv(dev);
792 unsigned int refill_rx = np->refill_rx;
795 while (np->cur_rx != refill_rx) {
798 nr = refill_rx % RX_RING;
799 if (np->rx_skbuff[nr] == NULL) {
801 skb = dev_alloc_skb(np->rx_buf_sz + NV_RX_ALLOC_PAD);
806 np->rx_skbuff[nr] = skb;
808 skb = np->rx_skbuff[nr];
810 np->rx_dma[nr] = pci_map_single(np->pci_dev, skb->data, skb->len,
812 np->rx_ring[nr].PacketBuffer = cpu_to_le32(np->rx_dma[nr]);
814 np->rx_ring[nr].FlagLen = cpu_to_le32(np->rx_buf_sz | NV_RX_AVAIL);
815 dprintk(KERN_DEBUG "%s: nv_alloc_rx: Packet %d marked as Available\n",
816 dev->name, refill_rx);
819 np->refill_rx = refill_rx;
820 if (np->cur_rx - refill_rx == RX_RING)
825 static void nv_do_rx_refill(unsigned long data)
827 struct net_device *dev = (struct net_device *) data;
828 struct fe_priv *np = get_nvpriv(dev);
830 disable_irq(dev->irq);
831 if (nv_alloc_rx(dev)) {
832 spin_lock(&np->lock);
833 if (!np->in_shutdown)
834 mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
835 spin_unlock(&np->lock);
837 enable_irq(dev->irq);
840 static void nv_init_rx(struct net_device *dev)
842 struct fe_priv *np = get_nvpriv(dev);
845 np->cur_rx = RX_RING;
847 for (i = 0; i < RX_RING; i++)
848 np->rx_ring[i].FlagLen = 0;
851 static void nv_init_tx(struct net_device *dev)
853 struct fe_priv *np = get_nvpriv(dev);
856 np->next_tx = np->nic_tx = 0;
857 for (i = 0; i < TX_RING; i++)
858 np->tx_ring[i].FlagLen = 0;
861 static int nv_init_ring(struct net_device *dev)
865 return nv_alloc_rx(dev);
868 static void nv_drain_tx(struct net_device *dev)
870 struct fe_priv *np = get_nvpriv(dev);
872 for (i = 0; i < TX_RING; i++) {
873 np->tx_ring[i].FlagLen = 0;
874 if (np->tx_skbuff[i]) {
875 pci_unmap_single(np->pci_dev, np->tx_dma[i],
876 np->tx_skbuff[i]->len,
878 dev_kfree_skb(np->tx_skbuff[i]);
879 np->tx_skbuff[i] = NULL;
880 np->stats.tx_dropped++;
885 static void nv_drain_rx(struct net_device *dev)
887 struct fe_priv *np = get_nvpriv(dev);
889 for (i = 0; i < RX_RING; i++) {
890 np->rx_ring[i].FlagLen = 0;
892 if (np->rx_skbuff[i]) {
893 pci_unmap_single(np->pci_dev, np->rx_dma[i],
894 np->rx_skbuff[i]->len,
896 dev_kfree_skb(np->rx_skbuff[i]);
897 np->rx_skbuff[i] = NULL;
902 static void drain_ring(struct net_device *dev)
909 * nv_start_xmit: dev->hard_start_xmit function
910 * Called with dev->xmit_lock held.
912 static int nv_start_xmit(struct sk_buff *skb, struct net_device *dev)
914 struct fe_priv *np = get_nvpriv(dev);
915 int nr = np->next_tx % TX_RING;
917 np->tx_skbuff[nr] = skb;
918 np->tx_dma[nr] = pci_map_single(np->pci_dev, skb->data,skb->len,
921 np->tx_ring[nr].PacketBuffer = cpu_to_le32(np->tx_dma[nr]);
923 spin_lock_irq(&np->lock);
925 np->tx_ring[nr].FlagLen = cpu_to_le32( (skb->len-1) | np->tx_flags );
926 dprintk(KERN_DEBUG "%s: nv_start_xmit: packet packet %d queued for transmission.\n",
927 dev->name, np->next_tx);
930 for (j=0; j<64; j++) {
932 dprintk("\n%03x:", j);
933 dprintk(" %02x", ((unsigned char*)skb->data)[j]);
940 dev->trans_start = jiffies;
941 if (np->next_tx - np->nic_tx >= TX_LIMIT_STOP)
942 netif_stop_queue(dev);
943 spin_unlock_irq(&np->lock);
944 writel(NVREG_TXRXCTL_KICK|np->desc_ver, get_hwbase(dev) + NvRegTxRxControl);
945 pci_push(get_hwbase(dev));
950 * nv_tx_done: check for completed packets, release the skbs.
952 * Caller must own np->lock.
954 static void nv_tx_done(struct net_device *dev)
956 struct fe_priv *np = get_nvpriv(dev);
960 while (np->nic_tx != np->next_tx) {
961 i = np->nic_tx % TX_RING;
963 Flags = le32_to_cpu(np->tx_ring[i].FlagLen);
965 dprintk(KERN_DEBUG "%s: nv_tx_done: looking at packet %d, Flags 0x%x.\n",
966 dev->name, np->nic_tx, Flags);
967 if (Flags & NV_TX_VALID)
969 if (np->desc_ver == DESC_VER_1) {
970 if (Flags & (NV_TX_RETRYERROR|NV_TX_CARRIERLOST|NV_TX_LATECOLLISION|
971 NV_TX_UNDERFLOW|NV_TX_ERROR)) {
972 if (Flags & NV_TX_UNDERFLOW)
973 np->stats.tx_fifo_errors++;
974 if (Flags & NV_TX_CARRIERLOST)
975 np->stats.tx_carrier_errors++;
976 np->stats.tx_errors++;
978 np->stats.tx_packets++;
979 np->stats.tx_bytes += np->tx_skbuff[i]->len;
982 if (Flags & (NV_TX2_RETRYERROR|NV_TX2_CARRIERLOST|NV_TX2_LATECOLLISION|
983 NV_TX2_UNDERFLOW|NV_TX2_ERROR)) {
984 if (Flags & NV_TX2_UNDERFLOW)
985 np->stats.tx_fifo_errors++;
986 if (Flags & NV_TX2_CARRIERLOST)
987 np->stats.tx_carrier_errors++;
988 np->stats.tx_errors++;
990 np->stats.tx_packets++;
991 np->stats.tx_bytes += np->tx_skbuff[i]->len;
994 pci_unmap_single(np->pci_dev, np->tx_dma[i],
995 np->tx_skbuff[i]->len,
997 dev_kfree_skb_irq(np->tx_skbuff[i]);
998 np->tx_skbuff[i] = NULL;
1001 if (np->next_tx - np->nic_tx < TX_LIMIT_START)
1002 netif_wake_queue(dev);
1006 * nv_tx_timeout: dev->tx_timeout function
1007 * Called with dev->xmit_lock held.
1009 static void nv_tx_timeout(struct net_device *dev)
1011 struct fe_priv *np = get_nvpriv(dev);
1012 u8 __iomem *base = get_hwbase(dev);
1014 dprintk(KERN_DEBUG "%s: Got tx_timeout. irq: %08x\n", dev->name,
1015 readl(base + NvRegIrqStatus) & NVREG_IRQSTAT_MASK);
1017 spin_lock_irq(&np->lock);
1019 /* 1) stop tx engine */
1022 /* 2) check that the packets were not sent already: */
1025 /* 3) if there are dead entries: clear everything */
1026 if (np->next_tx != np->nic_tx) {
1027 printk(KERN_DEBUG "%s: tx_timeout: dead entries!\n", dev->name);
1029 np->next_tx = np->nic_tx = 0;
1030 writel((u32) (np->ring_addr + RX_RING*sizeof(struct ring_desc)), base + NvRegTxRingPhysAddr);
1031 netif_wake_queue(dev);
1034 /* 4) restart tx engine */
1036 spin_unlock_irq(&np->lock);
1040 * Called when the nic notices a mismatch between the actual data len on the
1041 * wire and the len indicated in the 802 header
1043 static int nv_getlen(struct net_device *dev, void *packet, int datalen)
1045 int hdrlen; /* length of the 802 header */
1046 int protolen; /* length as stored in the proto field */
1048 /* 1) calculate len according to header */
1049 if ( ((struct vlan_ethhdr *)packet)->h_vlan_proto == __constant_htons(ETH_P_8021Q)) {
1050 protolen = ntohs( ((struct vlan_ethhdr *)packet)->h_vlan_encapsulated_proto );
1053 protolen = ntohs( ((struct ethhdr *)packet)->h_proto);
1056 dprintk(KERN_DEBUG "%s: nv_getlen: datalen %d, protolen %d, hdrlen %d\n",
1057 dev->name, datalen, protolen, hdrlen);
1058 if (protolen > ETH_DATA_LEN)
1059 return datalen; /* Value in proto field not a len, no checks possible */
1062 /* consistency checks: */
1063 if (datalen > ETH_ZLEN) {
1064 if (datalen >= protolen) {
1065 /* more data on wire than in 802 header, trim of
1068 dprintk(KERN_DEBUG "%s: nv_getlen: accepting %d bytes.\n",
1069 dev->name, protolen);
1072 /* less data on wire than mentioned in header.
1073 * Discard the packet.
1075 dprintk(KERN_DEBUG "%s: nv_getlen: discarding long packet.\n",
1080 /* short packet. Accept only if 802 values are also short */
1081 if (protolen > ETH_ZLEN) {
1082 dprintk(KERN_DEBUG "%s: nv_getlen: discarding short packet.\n",
1086 dprintk(KERN_DEBUG "%s: nv_getlen: accepting %d bytes.\n",
1087 dev->name, datalen);
1092 static void nv_rx_process(struct net_device *dev)
1094 struct fe_priv *np = get_nvpriv(dev);
1098 struct sk_buff *skb;
1101 if (np->cur_rx - np->refill_rx >= RX_RING)
1102 break; /* we scanned the whole ring - do not continue */
1104 i = np->cur_rx % RX_RING;
1105 Flags = le32_to_cpu(np->rx_ring[i].FlagLen);
1106 len = nv_descr_getlength(&np->rx_ring[i], np->desc_ver);
1108 dprintk(KERN_DEBUG "%s: nv_rx_process: looking at packet %d, Flags 0x%x.\n",
1109 dev->name, np->cur_rx, Flags);
1111 if (Flags & NV_RX_AVAIL)
1112 break; /* still owned by hardware, */
1115 * the packet is for us - immediately tear down the pci mapping.
1116 * TODO: check if a prefetch of the first cacheline improves
1119 pci_unmap_single(np->pci_dev, np->rx_dma[i],
1120 np->rx_skbuff[i]->len,
1121 PCI_DMA_FROMDEVICE);
1125 dprintk(KERN_DEBUG "Dumping packet (flags 0x%x).",Flags);
1126 for (j=0; j<64; j++) {
1128 dprintk("\n%03x:", j);
1129 dprintk(" %02x", ((unsigned char*)np->rx_skbuff[i]->data)[j]);
1133 /* look at what we actually got: */
1134 if (np->desc_ver == DESC_VER_1) {
1135 if (!(Flags & NV_RX_DESCRIPTORVALID))
1138 if (Flags & NV_RX_MISSEDFRAME) {
1139 np->stats.rx_missed_errors++;
1140 np->stats.rx_errors++;
1143 if (Flags & (NV_RX_ERROR1|NV_RX_ERROR2|NV_RX_ERROR3)) {
1144 np->stats.rx_errors++;
1147 if (Flags & NV_RX_CRCERR) {
1148 np->stats.rx_crc_errors++;
1149 np->stats.rx_errors++;
1152 if (Flags & NV_RX_OVERFLOW) {
1153 np->stats.rx_over_errors++;
1154 np->stats.rx_errors++;
1157 if (Flags & NV_RX_ERROR4) {
1158 len = nv_getlen(dev, np->rx_skbuff[i]->data, len);
1160 np->stats.rx_errors++;
1164 /* framing errors are soft errors. */
1165 if (Flags & NV_RX_FRAMINGERR) {
1166 if (Flags & NV_RX_SUBSTRACT1) {
1171 if (!(Flags & NV_RX2_DESCRIPTORVALID))
1174 if (Flags & (NV_RX2_ERROR1|NV_RX2_ERROR2|NV_RX2_ERROR3)) {
1175 np->stats.rx_errors++;
1178 if (Flags & NV_RX2_CRCERR) {
1179 np->stats.rx_crc_errors++;
1180 np->stats.rx_errors++;
1183 if (Flags & NV_RX2_OVERFLOW) {
1184 np->stats.rx_over_errors++;
1185 np->stats.rx_errors++;
1188 if (Flags & NV_RX2_ERROR4) {
1189 len = nv_getlen(dev, np->rx_skbuff[i]->data, len);
1191 np->stats.rx_errors++;
1195 /* framing errors are soft errors */
1196 if (Flags & NV_RX2_FRAMINGERR) {
1197 if (Flags & NV_RX2_SUBSTRACT1) {
1201 Flags &= NV_RX2_CHECKSUMMASK;
1202 if (Flags == NV_RX2_CHECKSUMOK1 ||
1203 Flags == NV_RX2_CHECKSUMOK2 ||
1204 Flags == NV_RX2_CHECKSUMOK3) {
1205 dprintk(KERN_DEBUG "%s: hw checksum hit!.\n", dev->name);
1206 np->rx_skbuff[i]->ip_summed = CHECKSUM_UNNECESSARY;
1208 dprintk(KERN_DEBUG "%s: hwchecksum miss!.\n", dev->name);
1211 /* got a valid packet - forward it to the network core */
1212 skb = np->rx_skbuff[i];
1213 np->rx_skbuff[i] = NULL;
1216 skb->protocol = eth_type_trans(skb, dev);
1217 dprintk(KERN_DEBUG "%s: nv_rx_process: packet %d with %d bytes, proto %d accepted.\n",
1218 dev->name, np->cur_rx, len, skb->protocol);
1220 dev->last_rx = jiffies;
1221 np->stats.rx_packets++;
1222 np->stats.rx_bytes += len;
1228 static void set_bufsize(struct net_device *dev)
1230 struct fe_priv *np = netdev_priv(dev);
1232 if (dev->mtu <= ETH_DATA_LEN)
1233 np->rx_buf_sz = ETH_DATA_LEN + NV_RX_HEADERS;
1235 np->rx_buf_sz = dev->mtu + NV_RX_HEADERS;
1239 * nv_change_mtu: dev->change_mtu function
1240 * Called with dev_base_lock held for read.
1242 static int nv_change_mtu(struct net_device *dev, int new_mtu)
1244 struct fe_priv *np = get_nvpriv(dev);
1247 if (new_mtu < 64 || new_mtu > np->pkt_limit)
1253 /* return early if the buffer sizes will not change */
1254 if (old_mtu <= ETH_DATA_LEN && new_mtu <= ETH_DATA_LEN)
1256 if (old_mtu == new_mtu)
1259 /* synchronized against open : rtnl_lock() held by caller */
1260 if (netif_running(dev)) {
1261 u8 *base = get_hwbase(dev);
1263 * It seems that the nic preloads valid ring entries into an
1264 * internal buffer. The procedure for flushing everything is
1265 * guessed, there is probably a simpler approach.
1266 * Changing the MTU is a rare event, it shouldn't matter.
1268 disable_irq(dev->irq);
1269 spin_lock_bh(&dev->xmit_lock);
1270 spin_lock(&np->lock);
1275 /* drain rx queue */
1278 /* reinit driver view of the rx queue */
1281 /* alloc new rx buffers */
1283 if (nv_alloc_rx(dev)) {
1284 if (!np->in_shutdown)
1285 mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
1287 /* reinit nic view of the rx queue */
1288 writel(np->rx_buf_sz, base + NvRegOffloadConfig);
1289 writel((u32) np->ring_addr, base + NvRegRxRingPhysAddr);
1290 writel((u32) (np->ring_addr + RX_RING*sizeof(struct ring_desc)), base + NvRegTxRingPhysAddr);
1291 writel( ((RX_RING-1) << NVREG_RINGSZ_RXSHIFT) + ((TX_RING-1) << NVREG_RINGSZ_TXSHIFT),
1292 base + NvRegRingSizes);
1294 writel(NVREG_TXRXCTL_KICK|np->desc_ver, get_hwbase(dev) + NvRegTxRxControl);
1297 /* restart rx engine */
1300 spin_unlock(&np->lock);
1301 spin_unlock_bh(&dev->xmit_lock);
1302 enable_irq(dev->irq);
1308 * nv_set_multicast: dev->set_multicast function
1309 * Called with dev->xmit_lock held.
1311 static void nv_set_multicast(struct net_device *dev)
1313 struct fe_priv *np = get_nvpriv(dev);
1314 u8 __iomem *base = get_hwbase(dev);
1319 memset(addr, 0, sizeof(addr));
1320 memset(mask, 0, sizeof(mask));
1322 if (dev->flags & IFF_PROMISC) {
1323 printk(KERN_NOTICE "%s: Promiscuous mode enabled.\n", dev->name);
1324 pff = NVREG_PFF_PROMISC;
1326 pff = NVREG_PFF_MYADDR;
1328 if (dev->flags & IFF_ALLMULTI || dev->mc_list) {
1332 alwaysOn[0] = alwaysOn[1] = alwaysOff[0] = alwaysOff[1] = 0xffffffff;
1333 if (dev->flags & IFF_ALLMULTI) {
1334 alwaysOn[0] = alwaysOn[1] = alwaysOff[0] = alwaysOff[1] = 0;
1336 struct dev_mc_list *walk;
1338 walk = dev->mc_list;
1339 while (walk != NULL) {
1341 a = le32_to_cpu(*(u32 *) walk->dmi_addr);
1342 b = le16_to_cpu(*(u16 *) (&walk->dmi_addr[4]));
1350 addr[0] = alwaysOn[0];
1351 addr[1] = alwaysOn[1];
1352 mask[0] = alwaysOn[0] | alwaysOff[0];
1353 mask[1] = alwaysOn[1] | alwaysOff[1];
1356 addr[0] |= NVREG_MCASTADDRA_FORCE;
1357 pff |= NVREG_PFF_ALWAYS;
1358 spin_lock_irq(&np->lock);
1360 writel(addr[0], base + NvRegMulticastAddrA);
1361 writel(addr[1], base + NvRegMulticastAddrB);
1362 writel(mask[0], base + NvRegMulticastMaskA);
1363 writel(mask[1], base + NvRegMulticastMaskB);
1364 writel(pff, base + NvRegPacketFilterFlags);
1365 dprintk(KERN_INFO "%s: reconfiguration for multicast lists.\n",
1368 spin_unlock_irq(&np->lock);
1371 static int nv_update_linkspeed(struct net_device *dev)
1373 struct fe_priv *np = get_nvpriv(dev);
1374 u8 __iomem *base = get_hwbase(dev);
1376 int newls = np->linkspeed;
1377 int newdup = np->duplex;
1380 u32 control_1000, status_1000, phyreg;
1382 /* BMSR_LSTATUS is latched, read it twice:
1383 * we want the current value.
1385 mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ);
1386 mii_status = mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ);
1388 if (!(mii_status & BMSR_LSTATUS)) {
1389 dprintk(KERN_DEBUG "%s: no link detected by phy - falling back to 10HD.\n",
1391 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
1397 if (np->autoneg == 0) {
1398 dprintk(KERN_DEBUG "%s: nv_update_linkspeed: autoneg off, PHY set to 0x%04x.\n",
1399 dev->name, np->fixed_mode);
1400 if (np->fixed_mode & LPA_100FULL) {
1401 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_100;
1403 } else if (np->fixed_mode & LPA_100HALF) {
1404 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_100;
1406 } else if (np->fixed_mode & LPA_10FULL) {
1407 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
1410 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
1416 /* check auto negotiation is complete */
1417 if (!(mii_status & BMSR_ANEGCOMPLETE)) {
1418 /* still in autonegotiation - configure nic for 10 MBit HD and wait. */
1419 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
1422 dprintk(KERN_DEBUG "%s: autoneg not completed - falling back to 10HD.\n", dev->name);
1427 if (np->gigabit == PHY_GIGABIT) {
1428 control_1000 = mii_rw(dev, np->phyaddr, MII_1000BT_CR, MII_READ);
1429 status_1000 = mii_rw(dev, np->phyaddr, MII_1000BT_SR, MII_READ);
1431 if ((control_1000 & ADVERTISE_1000FULL) &&
1432 (status_1000 & LPA_1000FULL)) {
1433 dprintk(KERN_DEBUG "%s: nv_update_linkspeed: GBit ethernet detected.\n",
1435 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_1000;
1441 adv = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ);
1442 lpa = mii_rw(dev, np->phyaddr, MII_LPA, MII_READ);
1443 dprintk(KERN_DEBUG "%s: nv_update_linkspeed: PHY advertises 0x%04x, lpa 0x%04x.\n",
1444 dev->name, adv, lpa);
1446 /* FIXME: handle parallel detection properly */
1448 if (lpa & LPA_100FULL) {
1449 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_100;
1451 } else if (lpa & LPA_100HALF) {
1452 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_100;
1454 } else if (lpa & LPA_10FULL) {
1455 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
1457 } else if (lpa & LPA_10HALF) {
1458 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
1461 dprintk(KERN_DEBUG "%s: bad ability %04x - falling back to 10HD.\n", dev->name, lpa);
1462 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
1467 if (np->duplex == newdup && np->linkspeed == newls)
1470 dprintk(KERN_INFO "%s: changing link setting from %d/%d to %d/%d.\n",
1471 dev->name, np->linkspeed, np->duplex, newls, newdup);
1473 np->duplex = newdup;
1474 np->linkspeed = newls;
1476 if (np->gigabit == PHY_GIGABIT) {
1477 phyreg = readl(base + NvRegRandomSeed);
1478 phyreg &= ~(0x3FF00);
1479 if ((np->linkspeed & 0xFFF) == NVREG_LINKSPEED_10)
1480 phyreg |= NVREG_RNDSEED_FORCE3;
1481 else if ((np->linkspeed & 0xFFF) == NVREG_LINKSPEED_100)
1482 phyreg |= NVREG_RNDSEED_FORCE2;
1483 else if ((np->linkspeed & 0xFFF) == NVREG_LINKSPEED_1000)
1484 phyreg |= NVREG_RNDSEED_FORCE;
1485 writel(phyreg, base + NvRegRandomSeed);
1488 phyreg = readl(base + NvRegPhyInterface);
1489 phyreg &= ~(PHY_HALF|PHY_100|PHY_1000);
1490 if (np->duplex == 0)
1492 if ((np->linkspeed & NVREG_LINKSPEED_MASK) == NVREG_LINKSPEED_100)
1494 else if ((np->linkspeed & NVREG_LINKSPEED_MASK) == NVREG_LINKSPEED_1000)
1496 writel(phyreg, base + NvRegPhyInterface);
1498 writel(NVREG_MISC1_FORCE | ( np->duplex ? 0 : NVREG_MISC1_HD),
1501 writel(np->linkspeed, base + NvRegLinkSpeed);
1507 static void nv_linkchange(struct net_device *dev)
1509 if (nv_update_linkspeed(dev)) {
1510 if (netif_carrier_ok(dev)) {
1513 netif_carrier_on(dev);
1514 printk(KERN_INFO "%s: link up.\n", dev->name);
1518 if (netif_carrier_ok(dev)) {
1519 netif_carrier_off(dev);
1520 printk(KERN_INFO "%s: link down.\n", dev->name);
1526 static void nv_link_irq(struct net_device *dev)
1528 u8 __iomem *base = get_hwbase(dev);
1531 miistat = readl(base + NvRegMIIStatus);
1532 writel(NVREG_MIISTAT_MASK, base + NvRegMIIStatus);
1533 dprintk(KERN_INFO "%s: link change irq, status 0x%x.\n", dev->name, miistat);
1535 if (miistat & (NVREG_MIISTAT_LINKCHANGE))
1537 dprintk(KERN_DEBUG "%s: link change notification done.\n", dev->name);
1540 static irqreturn_t nv_nic_irq(int foo, void *data, struct pt_regs *regs)
1542 struct net_device *dev = (struct net_device *) data;
1543 struct fe_priv *np = get_nvpriv(dev);
1544 u8 __iomem *base = get_hwbase(dev);
1548 dprintk(KERN_DEBUG "%s: nv_nic_irq\n", dev->name);
1551 events = readl(base + NvRegIrqStatus) & NVREG_IRQSTAT_MASK;
1552 writel(NVREG_IRQSTAT_MASK, base + NvRegIrqStatus);
1554 dprintk(KERN_DEBUG "%s: irq: %08x\n", dev->name, events);
1555 if (!(events & np->irqmask))
1558 if (events & (NVREG_IRQ_TX1|NVREG_IRQ_TX2|NVREG_IRQ_TX_ERR)) {
1559 spin_lock(&np->lock);
1561 spin_unlock(&np->lock);
1564 if (events & (NVREG_IRQ_RX_ERROR|NVREG_IRQ_RX|NVREG_IRQ_RX_NOBUF)) {
1566 if (nv_alloc_rx(dev)) {
1567 spin_lock(&np->lock);
1568 if (!np->in_shutdown)
1569 mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
1570 spin_unlock(&np->lock);
1574 if (events & NVREG_IRQ_LINK) {
1575 spin_lock(&np->lock);
1577 spin_unlock(&np->lock);
1579 if (np->need_linktimer && time_after(jiffies, np->link_timeout)) {
1580 spin_lock(&np->lock);
1582 spin_unlock(&np->lock);
1583 np->link_timeout = jiffies + LINK_TIMEOUT;
1585 if (events & (NVREG_IRQ_TX_ERR)) {
1586 dprintk(KERN_DEBUG "%s: received irq with events 0x%x. Probably TX fail.\n",
1589 if (events & (NVREG_IRQ_UNKNOWN)) {
1590 printk(KERN_DEBUG "%s: received irq with unknown events 0x%x. Please report\n",
1593 if (i > max_interrupt_work) {
1594 spin_lock(&np->lock);
1595 /* disable interrupts on the nic */
1596 writel(0, base + NvRegIrqMask);
1599 if (!np->in_shutdown)
1600 mod_timer(&np->nic_poll, jiffies + POLL_WAIT);
1601 printk(KERN_DEBUG "%s: too many iterations (%d) in nv_nic_irq.\n", dev->name, i);
1602 spin_unlock(&np->lock);
1607 dprintk(KERN_DEBUG "%s: nv_nic_irq completed\n", dev->name);
1609 return IRQ_RETVAL(i);
1612 static void nv_do_nic_poll(unsigned long data)
1614 struct net_device *dev = (struct net_device *) data;
1615 struct fe_priv *np = get_nvpriv(dev);
1616 u8 __iomem *base = get_hwbase(dev);
1618 disable_irq(dev->irq);
1619 /* FIXME: Do we need synchronize_irq(dev->irq) here? */
1621 * reenable interrupts on the nic, we have to do this before calling
1622 * nv_nic_irq because that may decide to do otherwise
1624 writel(np->irqmask, base + NvRegIrqMask);
1626 nv_nic_irq((int) 0, (void *) data, (struct pt_regs *) NULL);
1627 enable_irq(dev->irq);
1630 #ifdef CONFIG_NET_POLL_CONTROLLER
1631 static void nv_poll_controller(struct net_device *dev)
1633 nv_do_nic_poll((unsigned long) dev);
1637 static void nv_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
1639 struct fe_priv *np = get_nvpriv(dev);
1640 strcpy(info->driver, "forcedeth");
1641 strcpy(info->version, FORCEDETH_VERSION);
1642 strcpy(info->bus_info, pci_name(np->pci_dev));
1645 static void nv_get_wol(struct net_device *dev, struct ethtool_wolinfo *wolinfo)
1647 struct fe_priv *np = get_nvpriv(dev);
1648 wolinfo->supported = WAKE_MAGIC;
1650 spin_lock_irq(&np->lock);
1652 wolinfo->wolopts = WAKE_MAGIC;
1653 spin_unlock_irq(&np->lock);
1656 static int nv_set_wol(struct net_device *dev, struct ethtool_wolinfo *wolinfo)
1658 struct fe_priv *np = get_nvpriv(dev);
1659 u8 __iomem *base = get_hwbase(dev);
1661 spin_lock_irq(&np->lock);
1662 if (wolinfo->wolopts == 0) {
1663 writel(0, base + NvRegWakeUpFlags);
1666 if (wolinfo->wolopts & WAKE_MAGIC) {
1667 writel(NVREG_WAKEUPFLAGS_ENABLE, base + NvRegWakeUpFlags);
1670 spin_unlock_irq(&np->lock);
1674 static int nv_get_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
1676 struct fe_priv *np = netdev_priv(dev);
1679 spin_lock_irq(&np->lock);
1680 ecmd->port = PORT_MII;
1681 if (!netif_running(dev)) {
1682 /* We do not track link speed / duplex setting if the
1683 * interface is disabled. Force a link check */
1684 nv_update_linkspeed(dev);
1686 switch(np->linkspeed & (NVREG_LINKSPEED_MASK)) {
1687 case NVREG_LINKSPEED_10:
1688 ecmd->speed = SPEED_10;
1690 case NVREG_LINKSPEED_100:
1691 ecmd->speed = SPEED_100;
1693 case NVREG_LINKSPEED_1000:
1694 ecmd->speed = SPEED_1000;
1697 ecmd->duplex = DUPLEX_HALF;
1699 ecmd->duplex = DUPLEX_FULL;
1701 ecmd->autoneg = np->autoneg;
1703 ecmd->advertising = ADVERTISED_MII;
1705 ecmd->advertising |= ADVERTISED_Autoneg;
1706 adv = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ);
1708 adv = np->fixed_mode;
1710 if (adv & ADVERTISE_10HALF)
1711 ecmd->advertising |= ADVERTISED_10baseT_Half;
1712 if (adv & ADVERTISE_10FULL)
1713 ecmd->advertising |= ADVERTISED_10baseT_Full;
1714 if (adv & ADVERTISE_100HALF)
1715 ecmd->advertising |= ADVERTISED_100baseT_Half;
1716 if (adv & ADVERTISE_100FULL)
1717 ecmd->advertising |= ADVERTISED_100baseT_Full;
1718 if (np->autoneg && np->gigabit == PHY_GIGABIT) {
1719 adv = mii_rw(dev, np->phyaddr, MII_1000BT_CR, MII_READ);
1720 if (adv & ADVERTISE_1000FULL)
1721 ecmd->advertising |= ADVERTISED_1000baseT_Full;
1724 ecmd->supported = (SUPPORTED_Autoneg |
1725 SUPPORTED_10baseT_Half | SUPPORTED_10baseT_Full |
1726 SUPPORTED_100baseT_Half | SUPPORTED_100baseT_Full |
1728 if (np->gigabit == PHY_GIGABIT)
1729 ecmd->supported |= SUPPORTED_1000baseT_Full;
1731 ecmd->phy_address = np->phyaddr;
1732 ecmd->transceiver = XCVR_EXTERNAL;
1734 /* ignore maxtxpkt, maxrxpkt for now */
1735 spin_unlock_irq(&np->lock);
1739 static int nv_set_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
1741 struct fe_priv *np = netdev_priv(dev);
1743 if (ecmd->port != PORT_MII)
1745 if (ecmd->transceiver != XCVR_EXTERNAL)
1747 if (ecmd->phy_address != np->phyaddr) {
1748 /* TODO: support switching between multiple phys. Should be
1749 * trivial, but not enabled due to lack of test hardware. */
1752 if (ecmd->autoneg == AUTONEG_ENABLE) {
1755 mask = ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
1756 ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full;
1757 if (np->gigabit == PHY_GIGABIT)
1758 mask |= ADVERTISED_1000baseT_Full;
1760 if ((ecmd->advertising & mask) == 0)
1763 } else if (ecmd->autoneg == AUTONEG_DISABLE) {
1764 /* Note: autonegotiation disable, speed 1000 intentionally
1765 * forbidden - noone should need that. */
1767 if (ecmd->speed != SPEED_10 && ecmd->speed != SPEED_100)
1769 if (ecmd->duplex != DUPLEX_HALF && ecmd->duplex != DUPLEX_FULL)
1775 spin_lock_irq(&np->lock);
1776 if (ecmd->autoneg == AUTONEG_ENABLE) {
1781 /* advertise only what has been requested */
1782 adv = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ);
1783 adv &= ~(ADVERTISE_ALL | ADVERTISE_100BASE4);
1784 if (ecmd->advertising & ADVERTISED_10baseT_Half)
1785 adv |= ADVERTISE_10HALF;
1786 if (ecmd->advertising & ADVERTISED_10baseT_Full)
1787 adv |= ADVERTISE_10FULL;
1788 if (ecmd->advertising & ADVERTISED_100baseT_Half)
1789 adv |= ADVERTISE_100HALF;
1790 if (ecmd->advertising & ADVERTISED_100baseT_Full)
1791 adv |= ADVERTISE_100FULL;
1792 mii_rw(dev, np->phyaddr, MII_ADVERTISE, adv);
1794 if (np->gigabit == PHY_GIGABIT) {
1795 adv = mii_rw(dev, np->phyaddr, MII_1000BT_CR, MII_READ);
1796 adv &= ~ADVERTISE_1000FULL;
1797 if (ecmd->advertising & ADVERTISED_1000baseT_Full)
1798 adv |= ADVERTISE_1000FULL;
1799 mii_rw(dev, np->phyaddr, MII_1000BT_CR, adv);
1802 bmcr = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
1803 bmcr |= (BMCR_ANENABLE | BMCR_ANRESTART);
1804 mii_rw(dev, np->phyaddr, MII_BMCR, bmcr);
1811 adv = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ);
1812 adv &= ~(ADVERTISE_ALL | ADVERTISE_100BASE4);
1813 if (ecmd->speed == SPEED_10 && ecmd->duplex == DUPLEX_HALF)
1814 adv |= ADVERTISE_10HALF;
1815 if (ecmd->speed == SPEED_10 && ecmd->duplex == DUPLEX_FULL)
1816 adv |= ADVERTISE_10FULL;
1817 if (ecmd->speed == SPEED_100 && ecmd->duplex == DUPLEX_HALF)
1818 adv |= ADVERTISE_100HALF;
1819 if (ecmd->speed == SPEED_100 && ecmd->duplex == DUPLEX_FULL)
1820 adv |= ADVERTISE_100FULL;
1821 mii_rw(dev, np->phyaddr, MII_ADVERTISE, adv);
1822 np->fixed_mode = adv;
1824 if (np->gigabit == PHY_GIGABIT) {
1825 adv = mii_rw(dev, np->phyaddr, MII_1000BT_CR, MII_READ);
1826 adv &= ~ADVERTISE_1000FULL;
1827 mii_rw(dev, np->phyaddr, MII_1000BT_CR, adv);
1830 bmcr = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
1831 bmcr |= ~(BMCR_ANENABLE|BMCR_SPEED100|BMCR_FULLDPLX);
1832 if (adv & (ADVERTISE_10FULL|ADVERTISE_100FULL))
1833 bmcr |= BMCR_FULLDPLX;
1834 if (adv & (ADVERTISE_100HALF|ADVERTISE_100FULL))
1835 bmcr |= BMCR_SPEED100;
1836 mii_rw(dev, np->phyaddr, MII_BMCR, bmcr);
1838 if (netif_running(dev)) {
1839 /* Wait a bit and then reconfigure the nic. */
1844 spin_unlock_irq(&np->lock);
1849 static struct ethtool_ops ops = {
1850 .get_drvinfo = nv_get_drvinfo,
1851 .get_link = ethtool_op_get_link,
1852 .get_wol = nv_get_wol,
1853 .set_wol = nv_set_wol,
1854 .get_settings = nv_get_settings,
1855 .set_settings = nv_set_settings,
1858 static int nv_open(struct net_device *dev)
1860 struct fe_priv *np = get_nvpriv(dev);
1861 u8 __iomem *base = get_hwbase(dev);
1864 dprintk(KERN_DEBUG "nv_open: begin\n");
1866 /* 1) erase previous misconfiguration */
1867 /* 4.1-1: stop adapter: ignored, 4.3 seems to be overkill */
1868 writel(NVREG_MCASTADDRA_FORCE, base + NvRegMulticastAddrA);
1869 writel(0, base + NvRegMulticastAddrB);
1870 writel(0, base + NvRegMulticastMaskA);
1871 writel(0, base + NvRegMulticastMaskB);
1872 writel(0, base + NvRegPacketFilterFlags);
1874 writel(0, base + NvRegTransmitterControl);
1875 writel(0, base + NvRegReceiverControl);
1877 writel(0, base + NvRegAdapterControl);
1879 /* 2) initialize descriptor rings */
1881 oom = nv_init_ring(dev);
1883 writel(0, base + NvRegLinkSpeed);
1884 writel(0, base + NvRegUnknownTransmitterReg);
1886 writel(0, base + NvRegUnknownSetupReg6);
1888 np->in_shutdown = 0;
1890 /* 3) set mac address */
1894 mac[0] = (dev->dev_addr[0] << 0) + (dev->dev_addr[1] << 8) +
1895 (dev->dev_addr[2] << 16) + (dev->dev_addr[3] << 24);
1896 mac[1] = (dev->dev_addr[4] << 0) + (dev->dev_addr[5] << 8);
1898 writel(mac[0], base + NvRegMacAddrA);
1899 writel(mac[1], base + NvRegMacAddrB);
1902 /* 4) give hw rings */
1903 writel((u32) np->ring_addr, base + NvRegRxRingPhysAddr);
1904 writel((u32) (np->ring_addr + RX_RING*sizeof(struct ring_desc)), base + NvRegTxRingPhysAddr);
1905 writel( ((RX_RING-1) << NVREG_RINGSZ_RXSHIFT) + ((TX_RING-1) << NVREG_RINGSZ_TXSHIFT),
1906 base + NvRegRingSizes);
1908 /* 5) continue setup */
1909 writel(np->linkspeed, base + NvRegLinkSpeed);
1910 writel(NVREG_UNKSETUP3_VAL1, base + NvRegUnknownSetupReg3);
1911 writel(np->desc_ver, base + NvRegTxRxControl);
1913 writel(NVREG_TXRXCTL_BIT1|np->desc_ver, base + NvRegTxRxControl);
1914 reg_delay(dev, NvRegUnknownSetupReg5, NVREG_UNKSETUP5_BIT31, NVREG_UNKSETUP5_BIT31,
1915 NV_SETUP5_DELAY, NV_SETUP5_DELAYMAX,
1916 KERN_INFO "open: SetupReg5, Bit 31 remained off\n");
1918 writel(0, base + NvRegUnknownSetupReg4);
1919 writel(NVREG_IRQSTAT_MASK, base + NvRegIrqStatus);
1920 writel(NVREG_MIISTAT_MASK2, base + NvRegMIIStatus);
1922 /* 6) continue setup */
1923 writel(NVREG_MISC1_FORCE | NVREG_MISC1_HD, base + NvRegMisc1);
1924 writel(readl(base + NvRegTransmitterStatus), base + NvRegTransmitterStatus);
1925 writel(NVREG_PFF_ALWAYS, base + NvRegPacketFilterFlags);
1926 writel(np->rx_buf_sz, base + NvRegOffloadConfig);
1928 writel(readl(base + NvRegReceiverStatus), base + NvRegReceiverStatus);
1929 get_random_bytes(&i, sizeof(i));
1930 writel(NVREG_RNDSEED_FORCE | (i&NVREG_RNDSEED_MASK), base + NvRegRandomSeed);
1931 writel(NVREG_UNKSETUP1_VAL, base + NvRegUnknownSetupReg1);
1932 writel(NVREG_UNKSETUP2_VAL, base + NvRegUnknownSetupReg2);
1933 writel(NVREG_POLL_DEFAULT, base + NvRegPollingInterval);
1934 writel(NVREG_UNKSETUP6_VAL, base + NvRegUnknownSetupReg6);
1935 writel((np->phyaddr << NVREG_ADAPTCTL_PHYSHIFT)|NVREG_ADAPTCTL_PHYVALID|NVREG_ADAPTCTL_RUNNING,
1936 base + NvRegAdapterControl);
1937 writel(NVREG_MIISPEED_BIT8|NVREG_MIIDELAY, base + NvRegMIISpeed);
1938 writel(NVREG_UNKSETUP4_VAL, base + NvRegUnknownSetupReg4);
1939 writel(NVREG_WAKEUPFLAGS_VAL, base + NvRegWakeUpFlags);
1941 i = readl(base + NvRegPowerState);
1942 if ( (i & NVREG_POWERSTATE_POWEREDUP) == 0)
1943 writel(NVREG_POWERSTATE_POWEREDUP|i, base + NvRegPowerState);
1947 writel(readl(base + NvRegPowerState) | NVREG_POWERSTATE_VALID, base + NvRegPowerState);
1949 writel(0, base + NvRegIrqMask);
1951 writel(NVREG_MIISTAT_MASK2, base + NvRegMIIStatus);
1952 writel(NVREG_IRQSTAT_MASK, base + NvRegIrqStatus);
1955 ret = request_irq(dev->irq, &nv_nic_irq, SA_SHIRQ, dev->name, dev);
1959 /* ask for interrupts */
1960 writel(np->irqmask, base + NvRegIrqMask);
1962 spin_lock_irq(&np->lock);
1963 writel(NVREG_MCASTADDRA_FORCE, base + NvRegMulticastAddrA);
1964 writel(0, base + NvRegMulticastAddrB);
1965 writel(0, base + NvRegMulticastMaskA);
1966 writel(0, base + NvRegMulticastMaskB);
1967 writel(NVREG_PFF_ALWAYS|NVREG_PFF_MYADDR, base + NvRegPacketFilterFlags);
1968 /* One manual link speed update: Interrupts are enabled, future link
1969 * speed changes cause interrupts and are handled by nv_link_irq().
1973 miistat = readl(base + NvRegMIIStatus);
1974 writel(NVREG_MIISTAT_MASK, base + NvRegMIIStatus);
1975 dprintk(KERN_INFO "startup: got 0x%08x.\n", miistat);
1977 ret = nv_update_linkspeed(dev);
1980 netif_start_queue(dev);
1982 netif_carrier_on(dev);
1984 printk("%s: no link during initialization.\n", dev->name);
1985 netif_carrier_off(dev);
1988 mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
1989 spin_unlock_irq(&np->lock);
1997 static int nv_close(struct net_device *dev)
1999 struct fe_priv *np = get_nvpriv(dev);
2002 spin_lock_irq(&np->lock);
2003 np->in_shutdown = 1;
2004 spin_unlock_irq(&np->lock);
2005 synchronize_irq(dev->irq);
2007 del_timer_sync(&np->oom_kick);
2008 del_timer_sync(&np->nic_poll);
2010 netif_stop_queue(dev);
2011 spin_lock_irq(&np->lock);
2016 /* disable interrupts on the nic or we will lock up */
2017 base = get_hwbase(dev);
2018 writel(0, base + NvRegIrqMask);
2020 dprintk(KERN_INFO "%s: Irqmask is zero again\n", dev->name);
2022 spin_unlock_irq(&np->lock);
2024 free_irq(dev->irq, dev);
2031 /* FIXME: power down nic */
2036 static int __devinit nv_probe(struct pci_dev *pci_dev, const struct pci_device_id *id)
2038 struct net_device *dev;
2044 dev = alloc_etherdev(sizeof(struct fe_priv));
2049 np = get_nvpriv(dev);
2050 np->pci_dev = pci_dev;
2051 spin_lock_init(&np->lock);
2052 SET_MODULE_OWNER(dev);
2053 SET_NETDEV_DEV(dev, &pci_dev->dev);
2055 init_timer(&np->oom_kick);
2056 np->oom_kick.data = (unsigned long) dev;
2057 np->oom_kick.function = &nv_do_rx_refill; /* timer handler */
2058 init_timer(&np->nic_poll);
2059 np->nic_poll.data = (unsigned long) dev;
2060 np->nic_poll.function = &nv_do_nic_poll; /* timer handler */
2062 err = pci_enable_device(pci_dev);
2064 printk(KERN_INFO "forcedeth: pci_enable_dev failed (%d) for device %s\n",
2065 err, pci_name(pci_dev));
2069 pci_set_master(pci_dev);
2071 err = pci_request_regions(pci_dev, DRV_NAME);
2077 for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) {
2078 dprintk(KERN_DEBUG "%s: resource %d start %p len %ld flags 0x%08lx.\n",
2079 pci_name(pci_dev), i, (void*)pci_resource_start(pci_dev, i),
2080 pci_resource_len(pci_dev, i),
2081 pci_resource_flags(pci_dev, i));
2082 if (pci_resource_flags(pci_dev, i) & IORESOURCE_MEM &&
2083 pci_resource_len(pci_dev, i) >= NV_PCI_REGSZ) {
2084 addr = pci_resource_start(pci_dev, i);
2088 if (i == DEVICE_COUNT_RESOURCE) {
2089 printk(KERN_INFO "forcedeth: Couldn't find register window for device %s.\n",
2094 /* handle different descriptor versions */
2095 if (pci_dev->device == PCI_DEVICE_ID_NVIDIA_NVENET_1 ||
2096 pci_dev->device == PCI_DEVICE_ID_NVIDIA_NVENET_2 ||
2097 pci_dev->device == PCI_DEVICE_ID_NVIDIA_NVENET_3 ||
2098 pci_dev->device == PCI_DEVICE_ID_NVIDIA_NVENET_12 ||
2099 pci_dev->device == PCI_DEVICE_ID_NVIDIA_NVENET_13) {
2100 np->desc_ver = DESC_VER_1;
2101 np->pkt_limit = NV_PKTLIMIT_1;
2103 np->desc_ver = DESC_VER_2;
2104 np->pkt_limit = NV_PKTLIMIT_2;
2108 np->base = ioremap(addr, NV_PCI_REGSZ);
2111 dev->base_addr = (unsigned long)np->base;
2112 dev->irq = pci_dev->irq;
2113 np->rx_ring = pci_alloc_consistent(pci_dev, sizeof(struct ring_desc) * (RX_RING + TX_RING),
2117 np->tx_ring = &np->rx_ring[RX_RING];
2119 dev->open = nv_open;
2120 dev->stop = nv_close;
2121 dev->hard_start_xmit = nv_start_xmit;
2122 dev->get_stats = nv_get_stats;
2123 dev->change_mtu = nv_change_mtu;
2124 dev->set_multicast_list = nv_set_multicast;
2125 #ifdef CONFIG_NET_POLL_CONTROLLER
2126 dev->poll_controller = nv_poll_controller;
2128 SET_ETHTOOL_OPS(dev, &ops);
2129 dev->tx_timeout = nv_tx_timeout;
2130 dev->watchdog_timeo = NV_WATCHDOG_TIMEO;
2132 pci_set_drvdata(pci_dev, dev);
2134 /* read the mac address */
2135 base = get_hwbase(dev);
2136 np->orig_mac[0] = readl(base + NvRegMacAddrA);
2137 np->orig_mac[1] = readl(base + NvRegMacAddrB);
2139 dev->dev_addr[0] = (np->orig_mac[1] >> 8) & 0xff;
2140 dev->dev_addr[1] = (np->orig_mac[1] >> 0) & 0xff;
2141 dev->dev_addr[2] = (np->orig_mac[0] >> 24) & 0xff;
2142 dev->dev_addr[3] = (np->orig_mac[0] >> 16) & 0xff;
2143 dev->dev_addr[4] = (np->orig_mac[0] >> 8) & 0xff;
2144 dev->dev_addr[5] = (np->orig_mac[0] >> 0) & 0xff;
2146 if (!is_valid_ether_addr(dev->dev_addr)) {
2148 * Bad mac address. At least one bios sets the mac address
2149 * to 01:23:45:67:89:ab
2151 printk(KERN_ERR "%s: Invalid Mac address detected: %02x:%02x:%02x:%02x:%02x:%02x\n",
2153 dev->dev_addr[0], dev->dev_addr[1], dev->dev_addr[2],
2154 dev->dev_addr[3], dev->dev_addr[4], dev->dev_addr[5]);
2155 printk(KERN_ERR "Please complain to your hardware vendor. Switching to a random MAC.\n");
2156 dev->dev_addr[0] = 0x00;
2157 dev->dev_addr[1] = 0x00;
2158 dev->dev_addr[2] = 0x6c;
2159 get_random_bytes(&dev->dev_addr[3], 3);
2162 dprintk(KERN_DEBUG "%s: MAC Address %02x:%02x:%02x:%02x:%02x:%02x\n", pci_name(pci_dev),
2163 dev->dev_addr[0], dev->dev_addr[1], dev->dev_addr[2],
2164 dev->dev_addr[3], dev->dev_addr[4], dev->dev_addr[5]);
2167 writel(0, base + NvRegWakeUpFlags);
2170 if (np->desc_ver == DESC_VER_1) {
2171 np->tx_flags = NV_TX_LASTPACKET|NV_TX_VALID;
2172 if (id->driver_data & DEV_NEED_LASTPACKET1)
2173 np->tx_flags |= NV_TX_LASTPACKET1;
2175 np->tx_flags = NV_TX2_LASTPACKET|NV_TX2_VALID;
2176 if (id->driver_data & DEV_NEED_LASTPACKET1)
2177 np->tx_flags |= NV_TX2_LASTPACKET1;
2179 if (id->driver_data & DEV_IRQMASK_1)
2180 np->irqmask = NVREG_IRQMASK_WANTED_1;
2181 if (id->driver_data & DEV_IRQMASK_2)
2182 np->irqmask = NVREG_IRQMASK_WANTED_2;
2183 if (id->driver_data & DEV_NEED_TIMERIRQ)
2184 np->irqmask |= NVREG_IRQ_TIMER;
2185 if (id->driver_data & DEV_NEED_LINKTIMER) {
2186 dprintk(KERN_INFO "%s: link timer on.\n", pci_name(pci_dev));
2187 np->need_linktimer = 1;
2188 np->link_timeout = jiffies + LINK_TIMEOUT;
2190 dprintk(KERN_INFO "%s: link timer off.\n", pci_name(pci_dev));
2191 np->need_linktimer = 0;
2194 /* find a suitable phy */
2195 for (i = 1; i < 32; i++) {
2198 spin_lock_irq(&np->lock);
2199 id1 = mii_rw(dev, i, MII_PHYSID1, MII_READ);
2200 spin_unlock_irq(&np->lock);
2201 if (id1 < 0 || id1 == 0xffff)
2203 spin_lock_irq(&np->lock);
2204 id2 = mii_rw(dev, i, MII_PHYSID2, MII_READ);
2205 spin_unlock_irq(&np->lock);
2206 if (id2 < 0 || id2 == 0xffff)
2209 id1 = (id1 & PHYID1_OUI_MASK) << PHYID1_OUI_SHFT;
2210 id2 = (id2 & PHYID2_OUI_MASK) >> PHYID2_OUI_SHFT;
2211 dprintk(KERN_DEBUG "%s: open: Found PHY %04x:%04x at address %d.\n",
2212 pci_name(pci_dev), id1, id2, i);
2214 np->phy_oui = id1 | id2;
2218 /* PHY in isolate mode? No phy attached and user wants to
2219 * test loopback? Very odd, but can be correct.
2221 printk(KERN_INFO "%s: open: Could not find a valid PHY.\n",
2230 /* set default link speed settings */
2231 np->linkspeed = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
2235 err = register_netdev(dev);
2237 printk(KERN_INFO "forcedeth: unable to register netdev: %d\n", err);
2240 printk(KERN_INFO "%s: forcedeth.c: subsystem: %05x:%04x bound to %s\n",
2241 dev->name, pci_dev->subsystem_vendor, pci_dev->subsystem_device,
2247 pci_free_consistent(np->pci_dev, sizeof(struct ring_desc) * (RX_RING + TX_RING),
2248 np->rx_ring, np->ring_addr);
2249 pci_set_drvdata(pci_dev, NULL);
2251 iounmap(get_hwbase(dev));
2253 pci_release_regions(pci_dev);
2255 pci_disable_device(pci_dev);
2262 static void __devexit nv_remove(struct pci_dev *pci_dev)
2264 struct net_device *dev = pci_get_drvdata(pci_dev);
2265 struct fe_priv *np = get_nvpriv(dev);
2266 u8 __iomem *base = get_hwbase(dev);
2268 unregister_netdev(dev);
2270 /* special op: write back the misordered MAC address - otherwise
2271 * the next nv_probe would see a wrong address.
2273 writel(np->orig_mac[0], base + NvRegMacAddrA);
2274 writel(np->orig_mac[1], base + NvRegMacAddrB);
2276 /* free all structures */
2277 pci_free_consistent(np->pci_dev, sizeof(struct ring_desc) * (RX_RING + TX_RING), np->rx_ring, np->ring_addr);
2278 iounmap(get_hwbase(dev));
2279 pci_release_regions(pci_dev);
2280 pci_disable_device(pci_dev);
2282 pci_set_drvdata(pci_dev, NULL);
2285 static struct pci_device_id pci_tbl[] = {
2286 { /* nForce Ethernet Controller */
2287 .vendor = PCI_VENDOR_ID_NVIDIA,
2288 .device = PCI_DEVICE_ID_NVIDIA_NVENET_1,
2289 .subvendor = PCI_ANY_ID,
2290 .subdevice = PCI_ANY_ID,
2291 .driver_data = DEV_IRQMASK_1|DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER,
2293 { /* nForce2 Ethernet Controller */
2294 .vendor = PCI_VENDOR_ID_NVIDIA,
2295 .device = PCI_DEVICE_ID_NVIDIA_NVENET_2,
2296 .subvendor = PCI_ANY_ID,
2297 .subdevice = PCI_ANY_ID,
2298 .driver_data = DEV_NEED_LASTPACKET1|DEV_IRQMASK_2|DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER,
2300 { /* nForce3 Ethernet Controller */
2301 .vendor = PCI_VENDOR_ID_NVIDIA,
2302 .device = PCI_DEVICE_ID_NVIDIA_NVENET_3,
2303 .subvendor = PCI_ANY_ID,
2304 .subdevice = PCI_ANY_ID,
2305 .driver_data = DEV_NEED_LASTPACKET1|DEV_IRQMASK_2|DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER,
2307 { /* nForce3 Ethernet Controller */
2308 .vendor = PCI_VENDOR_ID_NVIDIA,
2309 .device = PCI_DEVICE_ID_NVIDIA_NVENET_4,
2310 .subvendor = PCI_ANY_ID,
2311 .subdevice = PCI_ANY_ID,
2312 .driver_data = DEV_NEED_LASTPACKET1|DEV_IRQMASK_2|DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER,
2314 { /* nForce3 Ethernet Controller */
2315 .vendor = PCI_VENDOR_ID_NVIDIA,
2316 .device = PCI_DEVICE_ID_NVIDIA_NVENET_5,
2317 .subvendor = PCI_ANY_ID,
2318 .subdevice = PCI_ANY_ID,
2319 .driver_data = DEV_NEED_LASTPACKET1|DEV_IRQMASK_2|DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER,
2321 { /* nForce3 Ethernet Controller */
2322 .vendor = PCI_VENDOR_ID_NVIDIA,
2323 .device = PCI_DEVICE_ID_NVIDIA_NVENET_6,
2324 .subvendor = PCI_ANY_ID,
2325 .subdevice = PCI_ANY_ID,
2326 .driver_data = DEV_NEED_LASTPACKET1|DEV_IRQMASK_2|DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER,
2328 { /* nForce3 Ethernet Controller */
2329 .vendor = PCI_VENDOR_ID_NVIDIA,
2330 .device = PCI_DEVICE_ID_NVIDIA_NVENET_7,
2331 .subvendor = PCI_ANY_ID,
2332 .subdevice = PCI_ANY_ID,
2333 .driver_data = DEV_NEED_LASTPACKET1|DEV_IRQMASK_2|DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER,
2335 { /* CK804 Ethernet Controller */
2336 .vendor = PCI_VENDOR_ID_NVIDIA,
2337 .device = PCI_DEVICE_ID_NVIDIA_NVENET_8,
2338 .subvendor = PCI_ANY_ID,
2339 .subdevice = PCI_ANY_ID,
2340 .driver_data = DEV_NEED_LASTPACKET1|DEV_IRQMASK_2|DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER,
2342 { /* CK804 Ethernet Controller */
2343 .vendor = PCI_VENDOR_ID_NVIDIA,
2344 .device = PCI_DEVICE_ID_NVIDIA_NVENET_9,
2345 .subvendor = PCI_ANY_ID,
2346 .subdevice = PCI_ANY_ID,
2347 .driver_data = DEV_NEED_LASTPACKET1|DEV_IRQMASK_2|DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER,
2349 { /* MCP04 Ethernet Controller */
2350 .vendor = PCI_VENDOR_ID_NVIDIA,
2351 .device = PCI_DEVICE_ID_NVIDIA_NVENET_10,
2352 .subvendor = PCI_ANY_ID,
2353 .subdevice = PCI_ANY_ID,
2354 .driver_data = DEV_NEED_LASTPACKET1|DEV_IRQMASK_2|DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER,
2356 { /* MCP04 Ethernet Controller */
2357 .vendor = PCI_VENDOR_ID_NVIDIA,
2358 .device = PCI_DEVICE_ID_NVIDIA_NVENET_11,
2359 .subvendor = PCI_ANY_ID,
2360 .subdevice = PCI_ANY_ID,
2361 .driver_data = DEV_NEED_LASTPACKET1|DEV_IRQMASK_2|DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER,
2363 { /* MCP51 Ethernet Controller */
2364 .vendor = PCI_VENDOR_ID_NVIDIA,
2365 .device = PCI_DEVICE_ID_NVIDIA_NVENET_12,
2366 .subvendor = PCI_ANY_ID,
2367 .subdevice = PCI_ANY_ID,
2368 .driver_data = DEV_NEED_LASTPACKET1|DEV_IRQMASK_2|DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER,
2370 { /* MCP51 Ethernet Controller */
2371 .vendor = PCI_VENDOR_ID_NVIDIA,
2372 .device = PCI_DEVICE_ID_NVIDIA_NVENET_13,
2373 .subvendor = PCI_ANY_ID,
2374 .subdevice = PCI_ANY_ID,
2375 .driver_data = DEV_NEED_LASTPACKET1|DEV_IRQMASK_2|DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER,
2377 { /* MCP55 Ethernet Controller */
2378 .vendor = PCI_VENDOR_ID_NVIDIA,
2379 .device = PCI_DEVICE_ID_NVIDIA_NVENET_14,
2380 .subvendor = PCI_ANY_ID,
2381 .subdevice = PCI_ANY_ID,
2382 .driver_data = DEV_NEED_LASTPACKET1|DEV_IRQMASK_2|DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER,
2384 { /* MCP55 Ethernet Controller */
2385 .vendor = PCI_VENDOR_ID_NVIDIA,
2386 .device = PCI_DEVICE_ID_NVIDIA_NVENET_15,
2387 .subvendor = PCI_ANY_ID,
2388 .subdevice = PCI_ANY_ID,
2389 .driver_data = DEV_NEED_LASTPACKET1|DEV_IRQMASK_2|DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER,
2394 static struct pci_driver driver = {
2395 .name = "forcedeth",
2396 .id_table = pci_tbl,
2398 .remove = __devexit_p(nv_remove),
2402 static int __init init_nic(void)
2404 printk(KERN_INFO "forcedeth.c: Reverse Engineered nForce ethernet driver. Version %s.\n", FORCEDETH_VERSION);
2405 return pci_module_init(&driver);
2408 static void __exit exit_nic(void)
2410 pci_unregister_driver(&driver);
2413 module_param(max_interrupt_work, int, 0);
2414 MODULE_PARM_DESC(max_interrupt_work, "forcedeth maximum events handled per interrupt");
2416 MODULE_AUTHOR("Manfred Spraul <manfred@colorfullife.com>");
2417 MODULE_DESCRIPTION("Reverse Engineered nForce ethernet driver");
2418 MODULE_LICENSE("GPL");
2420 MODULE_DEVICE_TABLE(pci, pci_tbl);
2422 module_init(init_nic);
2423 module_exit(exit_nic);