2 * forcedeth: Ethernet driver for NVIDIA nForce media access controllers.
4 * Note: This driver is a cleanroom reimplementation based on reverse
5 * engineered documentation written by Carl-Daniel Hailfinger
6 * and Andrew de Quincey. It's neither supported nor endorsed
7 * by NVIDIA Corp. Use at your own risk.
9 * NVIDIA, nForce and other NVIDIA marks are trademarks or registered
10 * trademarks of NVIDIA Corporation in the United States and other
13 * Copyright (C) 2003,4 Manfred Spraul
14 * Copyright (C) 2004 Andrew de Quincey (wol support)
15 * Copyright (C) 2004 Carl-Daniel Hailfinger (invalid MAC handling, insane
16 * IRQ rate fixes, bigendian fixes, cleanups, verification)
17 * Copyright (c) 2004 NVIDIA Corporation
19 * This program is free software; you can redistribute it and/or modify
20 * it under the terms of the GNU General Public License as published by
21 * the Free Software Foundation; either version 2 of the License, or
22 * (at your option) any later version.
24 * This program is distributed in the hope that it will be useful,
25 * but WITHOUT ANY WARRANTY; without even the implied warranty of
26 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
27 * GNU General Public License for more details.
29 * You should have received a copy of the GNU General Public License
30 * along with this program; if not, write to the Free Software
31 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
34 * 0.01: 05 Oct 2003: First release that compiles without warnings.
35 * 0.02: 05 Oct 2003: Fix bug for nv_drain_tx: do not try to free NULL skbs.
36 * Check all PCI BARs for the register window.
37 * udelay added to mii_rw.
38 * 0.03: 06 Oct 2003: Initialize dev->irq.
39 * 0.04: 07 Oct 2003: Initialize np->lock, reduce handled irqs, add printks.
40 * 0.05: 09 Oct 2003: printk removed again, irq status print tx_timeout.
41 * 0.06: 10 Oct 2003: MAC Address read updated, pff flag generation updated,
43 * 0.07: 14 Oct 2003: Further irq mask updates.
44 * 0.08: 20 Oct 2003: rx_desc.Length initialization added, nv_alloc_rx refill
45 * added into irq handler, NULL check for drain_ring.
46 * 0.09: 20 Oct 2003: Basic link speed irq implementation. Only handle the
47 * requested interrupt sources.
48 * 0.10: 20 Oct 2003: First cleanup for release.
49 * 0.11: 21 Oct 2003: hexdump for tx added, rx buffer sizes increased.
50 * MAC Address init fix, set_multicast cleanup.
51 * 0.12: 23 Oct 2003: Cleanups for release.
52 * 0.13: 25 Oct 2003: Limit for concurrent tx packets increased to 10.
53 * Set link speed correctly. start rx before starting
54 * tx (nv_start_rx sets the link speed).
55 * 0.14: 25 Oct 2003: Nic dependant irq mask.
56 * 0.15: 08 Nov 2003: fix smp deadlock with set_multicast_list during
58 * 0.16: 15 Nov 2003: include file cleanup for ppc64, rx buffer size
59 * increased to 1628 bytes.
60 * 0.17: 16 Nov 2003: undo rx buffer size increase. Substract 1 from
62 * 0.18: 17 Nov 2003: fix oops due to late initialization of dev_stats
63 * 0.19: 29 Nov 2003: Handle RxNoBuf, detect & handle invalid mac
64 * addresses, really stop rx if already running
65 * in nv_start_rx, clean up a bit.
66 * 0.20: 07 Dec 2003: alloc fixes
67 * 0.21: 12 Jan 2004: additional alloc fix, nic polling fix.
68 * 0.22: 19 Jan 2004: reprogram timer to a sane rate, avoid lockup
70 * 0.23: 26 Jan 2004: various small cleanups
71 * 0.24: 27 Feb 2004: make driver even less anonymous in backtraces
72 * 0.25: 09 Mar 2004: wol support
73 * 0.26: 03 Jun 2004: netdriver specific annotation, sparse-related fixes
74 * 0.27: 19 Jun 2004: Gigabit support, new descriptor rings,
75 * added CK804/MCP04 device IDs, code fixes
76 * for registers, link status and other minor fixes.
77 * 0.28: 21 Jun 2004: Big cleanup, making driver mostly endian safe
78 * 0.29: 31 Aug 2004: Add backup timer for link change notification.
79 * 0.30: 25 Sep 2004: rx checksum support for nf 250 Gb. Add rx reset
80 * into nv_close, otherwise reenabling for wol can
81 * cause DMA to kfree'd memory.
82 * 0.31: 14 Nov 2004: ethtool support for getting/setting link
84 * 0.32: 16 Apr 2005: RX_ERROR4 handling added.
85 * 0.33: 16 May 2005: Support for MCP51 added.
86 * 0.34: 18 Jun 2005: Add DEV_NEED_LINKTIMER to all nForce nics.
87 * 0.35: 26 Jun 2005: Support for MCP55 added.
88 * 0.36: 28 Jun 2005: Add jumbo frame support.
89 * 0.37: 10 Jul 2005: Additional ethtool support, cleanup of pci id list
90 * 0.38: 16 Jul 2005: tx irq rewrite: Use global flags instead of
92 * 0.39: 18 Jul 2005: Add 64bit descriptor support.
93 * 0.40: 19 Jul 2005: Add support for mac address change.
96 * We suspect that on some hardware no TX done interrupts are generated.
97 * This means recovery from netif_stop_queue only happens if the hw timer
98 * interrupt fires (100 times/second, configurable with NVREG_POLL_DEFAULT)
99 * and the timer is active in the IRQMask, or if a rx packet arrives by chance.
100 * If your hardware reliably generates tx done interrupts, then you can remove
101 * DEV_NEED_TIMERIRQ from the driver_data flags.
102 * DEV_NEED_TIMERIRQ will not harm you on sane hardware, only generating a few
103 * superfluous timer interrupts from the nic.
105 #define FORCEDETH_VERSION "0.40"
106 #define DRV_NAME "forcedeth"
108 #include <linux/module.h>
109 #include <linux/types.h>
110 #include <linux/pci.h>
111 #include <linux/interrupt.h>
112 #include <linux/netdevice.h>
113 #include <linux/etherdevice.h>
114 #include <linux/delay.h>
115 #include <linux/spinlock.h>
116 #include <linux/ethtool.h>
117 #include <linux/timer.h>
118 #include <linux/skbuff.h>
119 #include <linux/mii.h>
120 #include <linux/random.h>
121 #include <linux/init.h>
122 #include <linux/if_vlan.h>
126 #include <asm/uaccess.h>
127 #include <asm/system.h>
130 #define dprintk printk
132 #define dprintk(x...) do { } while (0)
140 #define DEV_NEED_TIMERIRQ 0x0001 /* set the timer irq flag in the irq mask */
141 #define DEV_NEED_LINKTIMER 0x0002 /* poll link settings. Relies on the timer irq */
142 #define DEV_HAS_LARGEDESC 0x0004 /* device supports jumbo frames and needs packet format 2 */
143 #define DEV_HAS_HIGH_DMA 0x0008 /* device supports 64bit dma */
146 NvRegIrqStatus = 0x000,
147 #define NVREG_IRQSTAT_MIIEVENT 0x040
148 #define NVREG_IRQSTAT_MASK 0x1ff
149 NvRegIrqMask = 0x004,
150 #define NVREG_IRQ_RX_ERROR 0x0001
151 #define NVREG_IRQ_RX 0x0002
152 #define NVREG_IRQ_RX_NOBUF 0x0004
153 #define NVREG_IRQ_TX_ERR 0x0008
154 #define NVREG_IRQ_TX_OK 0x0010
155 #define NVREG_IRQ_TIMER 0x0020
156 #define NVREG_IRQ_LINK 0x0040
157 #define NVREG_IRQ_TX_ERROR 0x0080
158 #define NVREG_IRQ_TX1 0x0100
159 #define NVREG_IRQMASK_WANTED 0x00df
161 #define NVREG_IRQ_UNKNOWN (~(NVREG_IRQ_RX_ERROR|NVREG_IRQ_RX|NVREG_IRQ_RX_NOBUF|NVREG_IRQ_TX_ERR| \
162 NVREG_IRQ_TX_OK|NVREG_IRQ_TIMER|NVREG_IRQ_LINK|NVREG_IRQ_TX_ERROR| \
165 NvRegUnknownSetupReg6 = 0x008,
166 #define NVREG_UNKSETUP6_VAL 3
169 * NVREG_POLL_DEFAULT is the interval length of the timer source on the nic
170 * NVREG_POLL_DEFAULT=97 would result in an interval length of 1 ms
172 NvRegPollingInterval = 0x00c,
173 #define NVREG_POLL_DEFAULT 970
175 #define NVREG_MISC1_HD 0x02
176 #define NVREG_MISC1_FORCE 0x3b0f3c
178 NvRegTransmitterControl = 0x084,
179 #define NVREG_XMITCTL_START 0x01
180 NvRegTransmitterStatus = 0x088,
181 #define NVREG_XMITSTAT_BUSY 0x01
183 NvRegPacketFilterFlags = 0x8c,
184 #define NVREG_PFF_ALWAYS 0x7F0008
185 #define NVREG_PFF_PROMISC 0x80
186 #define NVREG_PFF_MYADDR 0x20
188 NvRegOffloadConfig = 0x90,
189 #define NVREG_OFFLOAD_HOMEPHY 0x601
190 #define NVREG_OFFLOAD_NORMAL RX_NIC_BUFSIZE
191 NvRegReceiverControl = 0x094,
192 #define NVREG_RCVCTL_START 0x01
193 NvRegReceiverStatus = 0x98,
194 #define NVREG_RCVSTAT_BUSY 0x01
196 NvRegRandomSeed = 0x9c,
197 #define NVREG_RNDSEED_MASK 0x00ff
198 #define NVREG_RNDSEED_FORCE 0x7f00
199 #define NVREG_RNDSEED_FORCE2 0x2d00
200 #define NVREG_RNDSEED_FORCE3 0x7400
202 NvRegUnknownSetupReg1 = 0xA0,
203 #define NVREG_UNKSETUP1_VAL 0x16070f
204 NvRegUnknownSetupReg2 = 0xA4,
205 #define NVREG_UNKSETUP2_VAL 0x16
206 NvRegMacAddrA = 0xA8,
207 NvRegMacAddrB = 0xAC,
208 NvRegMulticastAddrA = 0xB0,
209 #define NVREG_MCASTADDRA_FORCE 0x01
210 NvRegMulticastAddrB = 0xB4,
211 NvRegMulticastMaskA = 0xB8,
212 NvRegMulticastMaskB = 0xBC,
214 NvRegPhyInterface = 0xC0,
215 #define PHY_RGMII 0x10000000
217 NvRegTxRingPhysAddr = 0x100,
218 NvRegRxRingPhysAddr = 0x104,
219 NvRegRingSizes = 0x108,
220 #define NVREG_RINGSZ_TXSHIFT 0
221 #define NVREG_RINGSZ_RXSHIFT 16
222 NvRegUnknownTransmitterReg = 0x10c,
223 NvRegLinkSpeed = 0x110,
224 #define NVREG_LINKSPEED_FORCE 0x10000
225 #define NVREG_LINKSPEED_10 1000
226 #define NVREG_LINKSPEED_100 100
227 #define NVREG_LINKSPEED_1000 50
228 #define NVREG_LINKSPEED_MASK (0xFFF)
229 NvRegUnknownSetupReg5 = 0x130,
230 #define NVREG_UNKSETUP5_BIT31 (1<<31)
231 NvRegUnknownSetupReg3 = 0x13c,
232 #define NVREG_UNKSETUP3_VAL1 0x200010
233 NvRegTxRxControl = 0x144,
234 #define NVREG_TXRXCTL_KICK 0x0001
235 #define NVREG_TXRXCTL_BIT1 0x0002
236 #define NVREG_TXRXCTL_BIT2 0x0004
237 #define NVREG_TXRXCTL_IDLE 0x0008
238 #define NVREG_TXRXCTL_RESET 0x0010
239 #define NVREG_TXRXCTL_RXCHECK 0x0400
240 NvRegMIIStatus = 0x180,
241 #define NVREG_MIISTAT_ERROR 0x0001
242 #define NVREG_MIISTAT_LINKCHANGE 0x0008
243 #define NVREG_MIISTAT_MASK 0x000f
244 #define NVREG_MIISTAT_MASK2 0x000f
245 NvRegUnknownSetupReg4 = 0x184,
246 #define NVREG_UNKSETUP4_VAL 8
248 NvRegAdapterControl = 0x188,
249 #define NVREG_ADAPTCTL_START 0x02
250 #define NVREG_ADAPTCTL_LINKUP 0x04
251 #define NVREG_ADAPTCTL_PHYVALID 0x40000
252 #define NVREG_ADAPTCTL_RUNNING 0x100000
253 #define NVREG_ADAPTCTL_PHYSHIFT 24
254 NvRegMIISpeed = 0x18c,
255 #define NVREG_MIISPEED_BIT8 (1<<8)
256 #define NVREG_MIIDELAY 5
257 NvRegMIIControl = 0x190,
258 #define NVREG_MIICTL_INUSE 0x08000
259 #define NVREG_MIICTL_WRITE 0x00400
260 #define NVREG_MIICTL_ADDRSHIFT 5
261 NvRegMIIData = 0x194,
262 NvRegWakeUpFlags = 0x200,
263 #define NVREG_WAKEUPFLAGS_VAL 0x7770
264 #define NVREG_WAKEUPFLAGS_BUSYSHIFT 24
265 #define NVREG_WAKEUPFLAGS_ENABLESHIFT 16
266 #define NVREG_WAKEUPFLAGS_D3SHIFT 12
267 #define NVREG_WAKEUPFLAGS_D2SHIFT 8
268 #define NVREG_WAKEUPFLAGS_D1SHIFT 4
269 #define NVREG_WAKEUPFLAGS_D0SHIFT 0
270 #define NVREG_WAKEUPFLAGS_ACCEPT_MAGPAT 0x01
271 #define NVREG_WAKEUPFLAGS_ACCEPT_WAKEUPPAT 0x02
272 #define NVREG_WAKEUPFLAGS_ACCEPT_LINKCHANGE 0x04
273 #define NVREG_WAKEUPFLAGS_ENABLE 0x1111
275 NvRegPatternCRC = 0x204,
276 NvRegPatternMask = 0x208,
277 NvRegPowerCap = 0x268,
278 #define NVREG_POWERCAP_D3SUPP (1<<30)
279 #define NVREG_POWERCAP_D2SUPP (1<<26)
280 #define NVREG_POWERCAP_D1SUPP (1<<25)
281 NvRegPowerState = 0x26c,
282 #define NVREG_POWERSTATE_POWEREDUP 0x8000
283 #define NVREG_POWERSTATE_VALID 0x0100
284 #define NVREG_POWERSTATE_MASK 0x0003
285 #define NVREG_POWERSTATE_D0 0x0000
286 #define NVREG_POWERSTATE_D1 0x0001
287 #define NVREG_POWERSTATE_D2 0x0002
288 #define NVREG_POWERSTATE_D3 0x0003
291 /* Big endian: should work, but is untested */
297 struct ring_desc_ex {
298 u32 PacketBufferHigh;
304 typedef union _ring_type {
305 struct ring_desc* orig;
306 struct ring_desc_ex* ex;
309 #define FLAG_MASK_V1 0xffff0000
310 #define FLAG_MASK_V2 0xffffc000
311 #define LEN_MASK_V1 (0xffffffff ^ FLAG_MASK_V1)
312 #define LEN_MASK_V2 (0xffffffff ^ FLAG_MASK_V2)
314 #define NV_TX_LASTPACKET (1<<16)
315 #define NV_TX_RETRYERROR (1<<19)
316 #define NV_TX_FORCED_INTERRUPT (1<<24)
317 #define NV_TX_DEFERRED (1<<26)
318 #define NV_TX_CARRIERLOST (1<<27)
319 #define NV_TX_LATECOLLISION (1<<28)
320 #define NV_TX_UNDERFLOW (1<<29)
321 #define NV_TX_ERROR (1<<30)
322 #define NV_TX_VALID (1<<31)
324 #define NV_TX2_LASTPACKET (1<<29)
325 #define NV_TX2_RETRYERROR (1<<18)
326 #define NV_TX2_FORCED_INTERRUPT (1<<30)
327 #define NV_TX2_DEFERRED (1<<25)
328 #define NV_TX2_CARRIERLOST (1<<26)
329 #define NV_TX2_LATECOLLISION (1<<27)
330 #define NV_TX2_UNDERFLOW (1<<28)
331 /* error and valid are the same for both */
332 #define NV_TX2_ERROR (1<<30)
333 #define NV_TX2_VALID (1<<31)
335 #define NV_RX_DESCRIPTORVALID (1<<16)
336 #define NV_RX_MISSEDFRAME (1<<17)
337 #define NV_RX_SUBSTRACT1 (1<<18)
338 #define NV_RX_ERROR1 (1<<23)
339 #define NV_RX_ERROR2 (1<<24)
340 #define NV_RX_ERROR3 (1<<25)
341 #define NV_RX_ERROR4 (1<<26)
342 #define NV_RX_CRCERR (1<<27)
343 #define NV_RX_OVERFLOW (1<<28)
344 #define NV_RX_FRAMINGERR (1<<29)
345 #define NV_RX_ERROR (1<<30)
346 #define NV_RX_AVAIL (1<<31)
348 #define NV_RX2_CHECKSUMMASK (0x1C000000)
349 #define NV_RX2_CHECKSUMOK1 (0x10000000)
350 #define NV_RX2_CHECKSUMOK2 (0x14000000)
351 #define NV_RX2_CHECKSUMOK3 (0x18000000)
352 #define NV_RX2_DESCRIPTORVALID (1<<29)
353 #define NV_RX2_SUBSTRACT1 (1<<25)
354 #define NV_RX2_ERROR1 (1<<18)
355 #define NV_RX2_ERROR2 (1<<19)
356 #define NV_RX2_ERROR3 (1<<20)
357 #define NV_RX2_ERROR4 (1<<21)
358 #define NV_RX2_CRCERR (1<<22)
359 #define NV_RX2_OVERFLOW (1<<23)
360 #define NV_RX2_FRAMINGERR (1<<24)
361 /* error and avail are the same for both */
362 #define NV_RX2_ERROR (1<<30)
363 #define NV_RX2_AVAIL (1<<31)
365 /* Miscelaneous hardware related defines: */
366 #define NV_PCI_REGSZ 0x270
368 /* various timeout delays: all in usec */
369 #define NV_TXRX_RESET_DELAY 4
370 #define NV_TXSTOP_DELAY1 10
371 #define NV_TXSTOP_DELAY1MAX 500000
372 #define NV_TXSTOP_DELAY2 100
373 #define NV_RXSTOP_DELAY1 10
374 #define NV_RXSTOP_DELAY1MAX 500000
375 #define NV_RXSTOP_DELAY2 100
376 #define NV_SETUP5_DELAY 5
377 #define NV_SETUP5_DELAYMAX 50000
378 #define NV_POWERUP_DELAY 5
379 #define NV_POWERUP_DELAYMAX 5000
380 #define NV_MIIBUSY_DELAY 50
381 #define NV_MIIPHY_DELAY 10
382 #define NV_MIIPHY_DELAYMAX 10000
384 #define NV_WAKEUPPATTERNS 5
385 #define NV_WAKEUPMASKENTRIES 4
387 /* General driver defaults */
388 #define NV_WATCHDOG_TIMEO (5*HZ)
393 * If your nic mysteriously hangs then try to reduce the limits
394 * to 1/0: It might be required to set NV_TX_LASTPACKET in the
395 * last valid ring entry. But this would be impossible to
396 * implement - probably a disassembly error.
398 #define TX_LIMIT_STOP 63
399 #define TX_LIMIT_START 62
401 /* rx/tx mac addr + type + vlan + align + slack*/
402 #define NV_RX_HEADERS (64)
403 /* even more slack. */
404 #define NV_RX_ALLOC_PAD (64)
406 /* maximum mtu size */
407 #define NV_PKTLIMIT_1 ETH_DATA_LEN /* hard limit not known */
408 #define NV_PKTLIMIT_2 9100 /* Actual limit according to NVidia: 9202 */
410 #define OOM_REFILL (1+HZ/20)
411 #define POLL_WAIT (1+HZ/100)
412 #define LINK_TIMEOUT (3*HZ)
416 * This field has two purposes:
417 * - Newer nics uses a different ring layout. The layout is selected by
418 * comparing np->desc_ver with DESC_VER_xy.
419 * - It contains bits that are forced on when writing to NvRegTxRxControl.
421 #define DESC_VER_1 0x0
422 #define DESC_VER_2 (0x02100|NVREG_TXRXCTL_RXCHECK)
423 #define DESC_VER_3 (0x02200|NVREG_TXRXCTL_RXCHECK)
426 #define PHY_OUI_MARVELL 0x5043
427 #define PHY_OUI_CICADA 0x03f1
428 #define PHYID1_OUI_MASK 0x03ff
429 #define PHYID1_OUI_SHFT 6
430 #define PHYID2_OUI_MASK 0xfc00
431 #define PHYID2_OUI_SHFT 10
432 #define PHY_INIT1 0x0f000
433 #define PHY_INIT2 0x0e00
434 #define PHY_INIT3 0x01000
435 #define PHY_INIT4 0x0200
436 #define PHY_INIT5 0x0004
437 #define PHY_INIT6 0x02000
438 #define PHY_GIGABIT 0x0100
440 #define PHY_TIMEOUT 0x1
441 #define PHY_ERROR 0x2
445 #define PHY_HALF 0x100
447 /* FIXME: MII defines that should be added to <linux/mii.h> */
448 #define MII_1000BT_CR 0x09
449 #define MII_1000BT_SR 0x0a
450 #define ADVERTISE_1000FULL 0x0200
451 #define ADVERTISE_1000HALF 0x0100
452 #define LPA_1000FULL 0x0800
453 #define LPA_1000HALF 0x0400
458 * All hardware access under dev->priv->lock, except the performance
460 * - rx is (pseudo-) lockless: it relies on the single-threading provided
461 * by the arch code for interrupts.
462 * - tx setup is lockless: it relies on dev->xmit_lock. Actual submission
463 * needs dev->priv->lock :-(
464 * - set_multicast_list: preparation lockless, relies on dev->xmit_lock.
467 /* in dev: base, irq */
472 * Locking: spin_lock(&np->lock); */
473 struct net_device_stats stats;
481 unsigned int phy_oui;
484 /* General data: RO fields */
485 dma_addr_t ring_addr;
486 struct pci_dev *pci_dev;
493 /* rx specific fields.
494 * Locking: Within irq hander or disable_irq+spin_lock(&np->lock);
497 unsigned int cur_rx, refill_rx;
498 struct sk_buff *rx_skbuff[RX_RING];
499 dma_addr_t rx_dma[RX_RING];
500 unsigned int rx_buf_sz;
501 unsigned int pkt_limit;
502 struct timer_list oom_kick;
503 struct timer_list nic_poll;
505 /* media detection workaround.
506 * Locking: Within irq hander or disable_irq+spin_lock(&np->lock);
509 unsigned long link_timeout;
511 * tx specific fields.
514 unsigned int next_tx, nic_tx;
515 struct sk_buff *tx_skbuff[TX_RING];
516 dma_addr_t tx_dma[TX_RING];
521 * Maximum number of loops until we assume that a bit in the irq mask
522 * is stuck. Overridable with module param.
524 static int max_interrupt_work = 5;
526 static inline struct fe_priv *get_nvpriv(struct net_device *dev)
528 return netdev_priv(dev);
531 static inline u8 __iomem *get_hwbase(struct net_device *dev)
533 return get_nvpriv(dev)->base;
536 static inline void pci_push(u8 __iomem *base)
538 /* force out pending posted writes */
542 static inline u32 nv_descr_getlength(struct ring_desc *prd, u32 v)
544 return le32_to_cpu(prd->FlagLen)
545 & ((v == DESC_VER_1) ? LEN_MASK_V1 : LEN_MASK_V2);
548 static inline u32 nv_descr_getlength_ex(struct ring_desc_ex *prd, u32 v)
550 return le32_to_cpu(prd->FlagLen) & LEN_MASK_V2;
553 static int reg_delay(struct net_device *dev, int offset, u32 mask, u32 target,
554 int delay, int delaymax, const char *msg)
556 u8 __iomem *base = get_hwbase(dev);
567 } while ((readl(base + offset) & mask) != target);
571 #define MII_READ (-1)
572 /* mii_rw: read/write a register on the PHY.
574 * Caller must guarantee serialization
576 static int mii_rw(struct net_device *dev, int addr, int miireg, int value)
578 u8 __iomem *base = get_hwbase(dev);
582 writel(NVREG_MIISTAT_MASK, base + NvRegMIIStatus);
584 reg = readl(base + NvRegMIIControl);
585 if (reg & NVREG_MIICTL_INUSE) {
586 writel(NVREG_MIICTL_INUSE, base + NvRegMIIControl);
587 udelay(NV_MIIBUSY_DELAY);
590 reg = (addr << NVREG_MIICTL_ADDRSHIFT) | miireg;
591 if (value != MII_READ) {
592 writel(value, base + NvRegMIIData);
593 reg |= NVREG_MIICTL_WRITE;
595 writel(reg, base + NvRegMIIControl);
597 if (reg_delay(dev, NvRegMIIControl, NVREG_MIICTL_INUSE, 0,
598 NV_MIIPHY_DELAY, NV_MIIPHY_DELAYMAX, NULL)) {
599 dprintk(KERN_DEBUG "%s: mii_rw of reg %d at PHY %d timed out.\n",
600 dev->name, miireg, addr);
602 } else if (value != MII_READ) {
603 /* it was a write operation - fewer failures are detectable */
604 dprintk(KERN_DEBUG "%s: mii_rw wrote 0x%x to reg %d at PHY %d\n",
605 dev->name, value, miireg, addr);
607 } else if (readl(base + NvRegMIIStatus) & NVREG_MIISTAT_ERROR) {
608 dprintk(KERN_DEBUG "%s: mii_rw of reg %d at PHY %d failed.\n",
609 dev->name, miireg, addr);
612 retval = readl(base + NvRegMIIData);
613 dprintk(KERN_DEBUG "%s: mii_rw read from reg %d at PHY %d: 0x%x.\n",
614 dev->name, miireg, addr, retval);
620 static int phy_reset(struct net_device *dev)
622 struct fe_priv *np = get_nvpriv(dev);
624 unsigned int tries = 0;
626 miicontrol = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
627 miicontrol |= BMCR_RESET;
628 if (mii_rw(dev, np->phyaddr, MII_BMCR, miicontrol)) {
635 /* must wait till reset is deasserted */
636 while (miicontrol & BMCR_RESET) {
638 miicontrol = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
639 /* FIXME: 100 tries seem excessive */
646 static int phy_init(struct net_device *dev)
648 struct fe_priv *np = get_nvpriv(dev);
649 u8 __iomem *base = get_hwbase(dev);
650 u32 phyinterface, phy_reserved, mii_status, mii_control, mii_control_1000,reg;
652 /* set advertise register */
653 reg = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ);
654 reg |= (ADVERTISE_10HALF|ADVERTISE_10FULL|ADVERTISE_100HALF|ADVERTISE_100FULL|0x800|0x400);
655 if (mii_rw(dev, np->phyaddr, MII_ADVERTISE, reg)) {
656 printk(KERN_INFO "%s: phy write to advertise failed.\n", pci_name(np->pci_dev));
660 /* get phy interface type */
661 phyinterface = readl(base + NvRegPhyInterface);
663 /* see if gigabit phy */
664 mii_status = mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ);
665 if (mii_status & PHY_GIGABIT) {
666 np->gigabit = PHY_GIGABIT;
667 mii_control_1000 = mii_rw(dev, np->phyaddr, MII_1000BT_CR, MII_READ);
668 mii_control_1000 &= ~ADVERTISE_1000HALF;
669 if (phyinterface & PHY_RGMII)
670 mii_control_1000 |= ADVERTISE_1000FULL;
672 mii_control_1000 &= ~ADVERTISE_1000FULL;
674 if (mii_rw(dev, np->phyaddr, MII_1000BT_CR, mii_control_1000)) {
675 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
683 if (phy_reset(dev)) {
684 printk(KERN_INFO "%s: phy reset failed\n", pci_name(np->pci_dev));
688 /* phy vendor specific configuration */
689 if ((np->phy_oui == PHY_OUI_CICADA) && (phyinterface & PHY_RGMII) ) {
690 phy_reserved = mii_rw(dev, np->phyaddr, MII_RESV1, MII_READ);
691 phy_reserved &= ~(PHY_INIT1 | PHY_INIT2);
692 phy_reserved |= (PHY_INIT3 | PHY_INIT4);
693 if (mii_rw(dev, np->phyaddr, MII_RESV1, phy_reserved)) {
694 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
697 phy_reserved = mii_rw(dev, np->phyaddr, MII_NCONFIG, MII_READ);
698 phy_reserved |= PHY_INIT5;
699 if (mii_rw(dev, np->phyaddr, MII_NCONFIG, phy_reserved)) {
700 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
704 if (np->phy_oui == PHY_OUI_CICADA) {
705 phy_reserved = mii_rw(dev, np->phyaddr, MII_SREVISION, MII_READ);
706 phy_reserved |= PHY_INIT6;
707 if (mii_rw(dev, np->phyaddr, MII_SREVISION, phy_reserved)) {
708 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
713 /* restart auto negotiation */
714 mii_control = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
715 mii_control |= (BMCR_ANRESTART | BMCR_ANENABLE);
716 if (mii_rw(dev, np->phyaddr, MII_BMCR, mii_control)) {
723 static void nv_start_rx(struct net_device *dev)
725 struct fe_priv *np = get_nvpriv(dev);
726 u8 __iomem *base = get_hwbase(dev);
728 dprintk(KERN_DEBUG "%s: nv_start_rx\n", dev->name);
729 /* Already running? Stop it. */
730 if (readl(base + NvRegReceiverControl) & NVREG_RCVCTL_START) {
731 writel(0, base + NvRegReceiverControl);
734 writel(np->linkspeed, base + NvRegLinkSpeed);
736 writel(NVREG_RCVCTL_START, base + NvRegReceiverControl);
737 dprintk(KERN_DEBUG "%s: nv_start_rx to duplex %d, speed 0x%08x.\n",
738 dev->name, np->duplex, np->linkspeed);
742 static void nv_stop_rx(struct net_device *dev)
744 u8 __iomem *base = get_hwbase(dev);
746 dprintk(KERN_DEBUG "%s: nv_stop_rx\n", dev->name);
747 writel(0, base + NvRegReceiverControl);
748 reg_delay(dev, NvRegReceiverStatus, NVREG_RCVSTAT_BUSY, 0,
749 NV_RXSTOP_DELAY1, NV_RXSTOP_DELAY1MAX,
750 KERN_INFO "nv_stop_rx: ReceiverStatus remained busy");
752 udelay(NV_RXSTOP_DELAY2);
753 writel(0, base + NvRegLinkSpeed);
756 static void nv_start_tx(struct net_device *dev)
758 u8 __iomem *base = get_hwbase(dev);
760 dprintk(KERN_DEBUG "%s: nv_start_tx\n", dev->name);
761 writel(NVREG_XMITCTL_START, base + NvRegTransmitterControl);
765 static void nv_stop_tx(struct net_device *dev)
767 u8 __iomem *base = get_hwbase(dev);
769 dprintk(KERN_DEBUG "%s: nv_stop_tx\n", dev->name);
770 writel(0, base + NvRegTransmitterControl);
771 reg_delay(dev, NvRegTransmitterStatus, NVREG_XMITSTAT_BUSY, 0,
772 NV_TXSTOP_DELAY1, NV_TXSTOP_DELAY1MAX,
773 KERN_INFO "nv_stop_tx: TransmitterStatus remained busy");
775 udelay(NV_TXSTOP_DELAY2);
776 writel(0, base + NvRegUnknownTransmitterReg);
779 static void nv_txrx_reset(struct net_device *dev)
781 struct fe_priv *np = get_nvpriv(dev);
782 u8 __iomem *base = get_hwbase(dev);
784 dprintk(KERN_DEBUG "%s: nv_txrx_reset\n", dev->name);
785 writel(NVREG_TXRXCTL_BIT2 | NVREG_TXRXCTL_RESET | np->desc_ver, base + NvRegTxRxControl);
787 udelay(NV_TXRX_RESET_DELAY);
788 writel(NVREG_TXRXCTL_BIT2 | np->desc_ver, base + NvRegTxRxControl);
793 * nv_get_stats: dev->get_stats function
794 * Get latest stats value from the nic.
795 * Called with read_lock(&dev_base_lock) held for read -
796 * only synchronized against unregister_netdevice.
798 static struct net_device_stats *nv_get_stats(struct net_device *dev)
800 struct fe_priv *np = get_nvpriv(dev);
802 /* It seems that the nic always generates interrupts and doesn't
803 * accumulate errors internally. Thus the current values in np->stats
804 * are already up to date.
810 * nv_alloc_rx: fill rx ring entries.
811 * Return 1 if the allocations for the skbs failed and the
812 * rx engine is without Available descriptors
814 static int nv_alloc_rx(struct net_device *dev)
816 struct fe_priv *np = get_nvpriv(dev);
817 unsigned int refill_rx = np->refill_rx;
820 while (np->cur_rx != refill_rx) {
823 nr = refill_rx % RX_RING;
824 if (np->rx_skbuff[nr] == NULL) {
826 skb = dev_alloc_skb(np->rx_buf_sz + NV_RX_ALLOC_PAD);
831 np->rx_skbuff[nr] = skb;
833 skb = np->rx_skbuff[nr];
835 np->rx_dma[nr] = pci_map_single(np->pci_dev, skb->data, skb->len,
837 if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) {
838 np->rx_ring.orig[nr].PacketBuffer = cpu_to_le32(np->rx_dma[nr]);
840 np->rx_ring.orig[nr].FlagLen = cpu_to_le32(np->rx_buf_sz | NV_RX_AVAIL);
842 np->rx_ring.ex[nr].PacketBufferHigh = cpu_to_le64(np->rx_dma[nr]) >> 32;
843 np->rx_ring.ex[nr].PacketBufferLow = cpu_to_le64(np->rx_dma[nr]) & 0x0FFFFFFFF;
845 np->rx_ring.ex[nr].FlagLen = cpu_to_le32(np->rx_buf_sz | NV_RX2_AVAIL);
847 dprintk(KERN_DEBUG "%s: nv_alloc_rx: Packet %d marked as Available\n",
848 dev->name, refill_rx);
851 np->refill_rx = refill_rx;
852 if (np->cur_rx - refill_rx == RX_RING)
857 static void nv_do_rx_refill(unsigned long data)
859 struct net_device *dev = (struct net_device *) data;
860 struct fe_priv *np = get_nvpriv(dev);
862 disable_irq(dev->irq);
863 if (nv_alloc_rx(dev)) {
864 spin_lock(&np->lock);
865 if (!np->in_shutdown)
866 mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
867 spin_unlock(&np->lock);
869 enable_irq(dev->irq);
872 static void nv_init_rx(struct net_device *dev)
874 struct fe_priv *np = get_nvpriv(dev);
877 np->cur_rx = RX_RING;
879 for (i = 0; i < RX_RING; i++)
880 if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2)
881 np->rx_ring.orig[i].FlagLen = 0;
883 np->rx_ring.ex[i].FlagLen = 0;
886 static void nv_init_tx(struct net_device *dev)
888 struct fe_priv *np = get_nvpriv(dev);
891 np->next_tx = np->nic_tx = 0;
892 for (i = 0; i < TX_RING; i++)
893 if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2)
894 np->tx_ring.orig[i].FlagLen = 0;
896 np->tx_ring.ex[i].FlagLen = 0;
899 static int nv_init_ring(struct net_device *dev)
903 return nv_alloc_rx(dev);
906 static void nv_drain_tx(struct net_device *dev)
908 struct fe_priv *np = get_nvpriv(dev);
910 for (i = 0; i < TX_RING; i++) {
911 if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2)
912 np->tx_ring.orig[i].FlagLen = 0;
914 np->tx_ring.ex[i].FlagLen = 0;
915 if (np->tx_skbuff[i]) {
916 pci_unmap_single(np->pci_dev, np->tx_dma[i],
917 np->tx_skbuff[i]->len,
919 dev_kfree_skb(np->tx_skbuff[i]);
920 np->tx_skbuff[i] = NULL;
921 np->stats.tx_dropped++;
926 static void nv_drain_rx(struct net_device *dev)
928 struct fe_priv *np = get_nvpriv(dev);
930 for (i = 0; i < RX_RING; i++) {
931 if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2)
932 np->rx_ring.orig[i].FlagLen = 0;
934 np->rx_ring.ex[i].FlagLen = 0;
936 if (np->rx_skbuff[i]) {
937 pci_unmap_single(np->pci_dev, np->rx_dma[i],
938 np->rx_skbuff[i]->len,
940 dev_kfree_skb(np->rx_skbuff[i]);
941 np->rx_skbuff[i] = NULL;
946 static void drain_ring(struct net_device *dev)
953 * nv_start_xmit: dev->hard_start_xmit function
954 * Called with dev->xmit_lock held.
956 static int nv_start_xmit(struct sk_buff *skb, struct net_device *dev)
958 struct fe_priv *np = get_nvpriv(dev);
959 int nr = np->next_tx % TX_RING;
961 np->tx_skbuff[nr] = skb;
962 np->tx_dma[nr] = pci_map_single(np->pci_dev, skb->data,skb->len,
965 if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2)
966 np->tx_ring.orig[nr].PacketBuffer = cpu_to_le32(np->tx_dma[nr]);
968 np->tx_ring.ex[nr].PacketBufferHigh = cpu_to_le64(np->tx_dma[nr]) >> 32;
969 np->tx_ring.ex[nr].PacketBufferLow = cpu_to_le64(np->tx_dma[nr]) & 0x0FFFFFFFF;
972 spin_lock_irq(&np->lock);
974 if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2)
975 np->tx_ring.orig[nr].FlagLen = cpu_to_le32( (skb->len-1) | np->tx_flags );
977 np->tx_ring.ex[nr].FlagLen = cpu_to_le32( (skb->len-1) | np->tx_flags );
978 dprintk(KERN_DEBUG "%s: nv_start_xmit: packet packet %d queued for transmission.\n",
979 dev->name, np->next_tx);
982 for (j=0; j<64; j++) {
984 dprintk("\n%03x:", j);
985 dprintk(" %02x", ((unsigned char*)skb->data)[j]);
992 dev->trans_start = jiffies;
993 if (np->next_tx - np->nic_tx >= TX_LIMIT_STOP)
994 netif_stop_queue(dev);
995 spin_unlock_irq(&np->lock);
996 writel(NVREG_TXRXCTL_KICK|np->desc_ver, get_hwbase(dev) + NvRegTxRxControl);
997 pci_push(get_hwbase(dev));
1002 * nv_tx_done: check for completed packets, release the skbs.
1004 * Caller must own np->lock.
1006 static void nv_tx_done(struct net_device *dev)
1008 struct fe_priv *np = get_nvpriv(dev);
1012 while (np->nic_tx != np->next_tx) {
1013 i = np->nic_tx % TX_RING;
1015 if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2)
1016 Flags = le32_to_cpu(np->tx_ring.orig[i].FlagLen);
1018 Flags = le32_to_cpu(np->tx_ring.ex[i].FlagLen);
1020 dprintk(KERN_DEBUG "%s: nv_tx_done: looking at packet %d, Flags 0x%x.\n",
1021 dev->name, np->nic_tx, Flags);
1022 if (Flags & NV_TX_VALID)
1024 if (np->desc_ver == DESC_VER_1) {
1025 if (Flags & (NV_TX_RETRYERROR|NV_TX_CARRIERLOST|NV_TX_LATECOLLISION|
1026 NV_TX_UNDERFLOW|NV_TX_ERROR)) {
1027 if (Flags & NV_TX_UNDERFLOW)
1028 np->stats.tx_fifo_errors++;
1029 if (Flags & NV_TX_CARRIERLOST)
1030 np->stats.tx_carrier_errors++;
1031 np->stats.tx_errors++;
1033 np->stats.tx_packets++;
1034 np->stats.tx_bytes += np->tx_skbuff[i]->len;
1037 if (Flags & (NV_TX2_RETRYERROR|NV_TX2_CARRIERLOST|NV_TX2_LATECOLLISION|
1038 NV_TX2_UNDERFLOW|NV_TX2_ERROR)) {
1039 if (Flags & NV_TX2_UNDERFLOW)
1040 np->stats.tx_fifo_errors++;
1041 if (Flags & NV_TX2_CARRIERLOST)
1042 np->stats.tx_carrier_errors++;
1043 np->stats.tx_errors++;
1045 np->stats.tx_packets++;
1046 np->stats.tx_bytes += np->tx_skbuff[i]->len;
1049 pci_unmap_single(np->pci_dev, np->tx_dma[i],
1050 np->tx_skbuff[i]->len,
1052 dev_kfree_skb_irq(np->tx_skbuff[i]);
1053 np->tx_skbuff[i] = NULL;
1056 if (np->next_tx - np->nic_tx < TX_LIMIT_START)
1057 netif_wake_queue(dev);
1061 * nv_tx_timeout: dev->tx_timeout function
1062 * Called with dev->xmit_lock held.
1064 static void nv_tx_timeout(struct net_device *dev)
1066 struct fe_priv *np = get_nvpriv(dev);
1067 u8 __iomem *base = get_hwbase(dev);
1069 printk(KERN_INFO "%s: Got tx_timeout. irq: %08x\n", dev->name,
1070 readl(base + NvRegIrqStatus) & NVREG_IRQSTAT_MASK);
1075 printk(KERN_INFO "%s: Ring at %lx: next %d nic %d\n",
1076 dev->name, (unsigned long)np->ring_addr,
1077 np->next_tx, np->nic_tx);
1078 printk(KERN_INFO "%s: Dumping tx registers\n", dev->name);
1079 for (i=0;i<0x400;i+= 32) {
1080 printk(KERN_INFO "%3x: %08x %08x %08x %08x %08x %08x %08x %08x\n",
1082 readl(base + i + 0), readl(base + i + 4),
1083 readl(base + i + 8), readl(base + i + 12),
1084 readl(base + i + 16), readl(base + i + 20),
1085 readl(base + i + 24), readl(base + i + 28));
1087 printk(KERN_INFO "%s: Dumping tx ring\n", dev->name);
1088 for (i=0;i<TX_RING;i+= 4) {
1089 if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) {
1090 printk(KERN_INFO "%03x: %08x %08x // %08x %08x // %08x %08x // %08x %08x\n",
1092 le32_to_cpu(np->tx_ring.orig[i].PacketBuffer),
1093 le32_to_cpu(np->tx_ring.orig[i].FlagLen),
1094 le32_to_cpu(np->tx_ring.orig[i+1].PacketBuffer),
1095 le32_to_cpu(np->tx_ring.orig[i+1].FlagLen),
1096 le32_to_cpu(np->tx_ring.orig[i+2].PacketBuffer),
1097 le32_to_cpu(np->tx_ring.orig[i+2].FlagLen),
1098 le32_to_cpu(np->tx_ring.orig[i+3].PacketBuffer),
1099 le32_to_cpu(np->tx_ring.orig[i+3].FlagLen));
1101 printk(KERN_INFO "%03x: %08x %08x %08x // %08x %08x %08x // %08x %08x %08x // %08x %08x %08x\n",
1103 le32_to_cpu(np->tx_ring.ex[i].PacketBufferHigh),
1104 le32_to_cpu(np->tx_ring.ex[i].PacketBufferLow),
1105 le32_to_cpu(np->tx_ring.ex[i].FlagLen),
1106 le32_to_cpu(np->tx_ring.ex[i+1].PacketBufferHigh),
1107 le32_to_cpu(np->tx_ring.ex[i+1].PacketBufferLow),
1108 le32_to_cpu(np->tx_ring.ex[i+1].FlagLen),
1109 le32_to_cpu(np->tx_ring.ex[i+2].PacketBufferHigh),
1110 le32_to_cpu(np->tx_ring.ex[i+2].PacketBufferLow),
1111 le32_to_cpu(np->tx_ring.ex[i+2].FlagLen),
1112 le32_to_cpu(np->tx_ring.ex[i+3].PacketBufferHigh),
1113 le32_to_cpu(np->tx_ring.ex[i+3].PacketBufferLow),
1114 le32_to_cpu(np->tx_ring.ex[i+3].FlagLen));
1119 spin_lock_irq(&np->lock);
1121 /* 1) stop tx engine */
1124 /* 2) check that the packets were not sent already: */
1127 /* 3) if there are dead entries: clear everything */
1128 if (np->next_tx != np->nic_tx) {
1129 printk(KERN_DEBUG "%s: tx_timeout: dead entries!\n", dev->name);
1131 np->next_tx = np->nic_tx = 0;
1132 if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2)
1133 writel((u32) (np->ring_addr + RX_RING*sizeof(struct ring_desc)), base + NvRegTxRingPhysAddr);
1135 writel((u32) (np->ring_addr + RX_RING*sizeof(struct ring_desc_ex)), base + NvRegTxRingPhysAddr);
1136 netif_wake_queue(dev);
1139 /* 4) restart tx engine */
1141 spin_unlock_irq(&np->lock);
1145 * Called when the nic notices a mismatch between the actual data len on the
1146 * wire and the len indicated in the 802 header
1148 static int nv_getlen(struct net_device *dev, void *packet, int datalen)
1150 int hdrlen; /* length of the 802 header */
1151 int protolen; /* length as stored in the proto field */
1153 /* 1) calculate len according to header */
1154 if ( ((struct vlan_ethhdr *)packet)->h_vlan_proto == __constant_htons(ETH_P_8021Q)) {
1155 protolen = ntohs( ((struct vlan_ethhdr *)packet)->h_vlan_encapsulated_proto );
1158 protolen = ntohs( ((struct ethhdr *)packet)->h_proto);
1161 dprintk(KERN_DEBUG "%s: nv_getlen: datalen %d, protolen %d, hdrlen %d\n",
1162 dev->name, datalen, protolen, hdrlen);
1163 if (protolen > ETH_DATA_LEN)
1164 return datalen; /* Value in proto field not a len, no checks possible */
1167 /* consistency checks: */
1168 if (datalen > ETH_ZLEN) {
1169 if (datalen >= protolen) {
1170 /* more data on wire than in 802 header, trim of
1173 dprintk(KERN_DEBUG "%s: nv_getlen: accepting %d bytes.\n",
1174 dev->name, protolen);
1177 /* less data on wire than mentioned in header.
1178 * Discard the packet.
1180 dprintk(KERN_DEBUG "%s: nv_getlen: discarding long packet.\n",
1185 /* short packet. Accept only if 802 values are also short */
1186 if (protolen > ETH_ZLEN) {
1187 dprintk(KERN_DEBUG "%s: nv_getlen: discarding short packet.\n",
1191 dprintk(KERN_DEBUG "%s: nv_getlen: accepting %d bytes.\n",
1192 dev->name, datalen);
1197 static void nv_rx_process(struct net_device *dev)
1199 struct fe_priv *np = get_nvpriv(dev);
1203 struct sk_buff *skb;
1206 if (np->cur_rx - np->refill_rx >= RX_RING)
1207 break; /* we scanned the whole ring - do not continue */
1209 i = np->cur_rx % RX_RING;
1210 if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) {
1211 Flags = le32_to_cpu(np->rx_ring.orig[i].FlagLen);
1212 len = nv_descr_getlength(&np->rx_ring.orig[i], np->desc_ver);
1214 Flags = le32_to_cpu(np->rx_ring.ex[i].FlagLen);
1215 len = nv_descr_getlength_ex(&np->rx_ring.ex[i], np->desc_ver);
1218 dprintk(KERN_DEBUG "%s: nv_rx_process: looking at packet %d, Flags 0x%x.\n",
1219 dev->name, np->cur_rx, Flags);
1221 if (Flags & NV_RX_AVAIL)
1222 break; /* still owned by hardware, */
1225 * the packet is for us - immediately tear down the pci mapping.
1226 * TODO: check if a prefetch of the first cacheline improves
1229 pci_unmap_single(np->pci_dev, np->rx_dma[i],
1230 np->rx_skbuff[i]->len,
1231 PCI_DMA_FROMDEVICE);
1235 dprintk(KERN_DEBUG "Dumping packet (flags 0x%x).",Flags);
1236 for (j=0; j<64; j++) {
1238 dprintk("\n%03x:", j);
1239 dprintk(" %02x", ((unsigned char*)np->rx_skbuff[i]->data)[j]);
1243 /* look at what we actually got: */
1244 if (np->desc_ver == DESC_VER_1) {
1245 if (!(Flags & NV_RX_DESCRIPTORVALID))
1248 if (Flags & NV_RX_MISSEDFRAME) {
1249 np->stats.rx_missed_errors++;
1250 np->stats.rx_errors++;
1253 if (Flags & (NV_RX_ERROR1|NV_RX_ERROR2|NV_RX_ERROR3)) {
1254 np->stats.rx_errors++;
1257 if (Flags & NV_RX_CRCERR) {
1258 np->stats.rx_crc_errors++;
1259 np->stats.rx_errors++;
1262 if (Flags & NV_RX_OVERFLOW) {
1263 np->stats.rx_over_errors++;
1264 np->stats.rx_errors++;
1267 if (Flags & NV_RX_ERROR4) {
1268 len = nv_getlen(dev, np->rx_skbuff[i]->data, len);
1270 np->stats.rx_errors++;
1274 /* framing errors are soft errors. */
1275 if (Flags & NV_RX_FRAMINGERR) {
1276 if (Flags & NV_RX_SUBSTRACT1) {
1281 if (!(Flags & NV_RX2_DESCRIPTORVALID))
1284 if (Flags & (NV_RX2_ERROR1|NV_RX2_ERROR2|NV_RX2_ERROR3)) {
1285 np->stats.rx_errors++;
1288 if (Flags & NV_RX2_CRCERR) {
1289 np->stats.rx_crc_errors++;
1290 np->stats.rx_errors++;
1293 if (Flags & NV_RX2_OVERFLOW) {
1294 np->stats.rx_over_errors++;
1295 np->stats.rx_errors++;
1298 if (Flags & NV_RX2_ERROR4) {
1299 len = nv_getlen(dev, np->rx_skbuff[i]->data, len);
1301 np->stats.rx_errors++;
1305 /* framing errors are soft errors */
1306 if (Flags & NV_RX2_FRAMINGERR) {
1307 if (Flags & NV_RX2_SUBSTRACT1) {
1311 Flags &= NV_RX2_CHECKSUMMASK;
1312 if (Flags == NV_RX2_CHECKSUMOK1 ||
1313 Flags == NV_RX2_CHECKSUMOK2 ||
1314 Flags == NV_RX2_CHECKSUMOK3) {
1315 dprintk(KERN_DEBUG "%s: hw checksum hit!.\n", dev->name);
1316 np->rx_skbuff[i]->ip_summed = CHECKSUM_UNNECESSARY;
1318 dprintk(KERN_DEBUG "%s: hwchecksum miss!.\n", dev->name);
1321 /* got a valid packet - forward it to the network core */
1322 skb = np->rx_skbuff[i];
1323 np->rx_skbuff[i] = NULL;
1326 skb->protocol = eth_type_trans(skb, dev);
1327 dprintk(KERN_DEBUG "%s: nv_rx_process: packet %d with %d bytes, proto %d accepted.\n",
1328 dev->name, np->cur_rx, len, skb->protocol);
1330 dev->last_rx = jiffies;
1331 np->stats.rx_packets++;
1332 np->stats.rx_bytes += len;
1338 static void set_bufsize(struct net_device *dev)
1340 struct fe_priv *np = netdev_priv(dev);
1342 if (dev->mtu <= ETH_DATA_LEN)
1343 np->rx_buf_sz = ETH_DATA_LEN + NV_RX_HEADERS;
1345 np->rx_buf_sz = dev->mtu + NV_RX_HEADERS;
1349 * nv_change_mtu: dev->change_mtu function
1350 * Called with dev_base_lock held for read.
1352 static int nv_change_mtu(struct net_device *dev, int new_mtu)
1354 struct fe_priv *np = get_nvpriv(dev);
1357 if (new_mtu < 64 || new_mtu > np->pkt_limit)
1363 /* return early if the buffer sizes will not change */
1364 if (old_mtu <= ETH_DATA_LEN && new_mtu <= ETH_DATA_LEN)
1366 if (old_mtu == new_mtu)
1369 /* synchronized against open : rtnl_lock() held by caller */
1370 if (netif_running(dev)) {
1371 u8 *base = get_hwbase(dev);
1373 * It seems that the nic preloads valid ring entries into an
1374 * internal buffer. The procedure for flushing everything is
1375 * guessed, there is probably a simpler approach.
1376 * Changing the MTU is a rare event, it shouldn't matter.
1378 disable_irq(dev->irq);
1379 spin_lock_bh(&dev->xmit_lock);
1380 spin_lock(&np->lock);
1385 /* drain rx queue */
1388 /* reinit driver view of the rx queue */
1391 /* alloc new rx buffers */
1393 if (nv_alloc_rx(dev)) {
1394 if (!np->in_shutdown)
1395 mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
1397 /* reinit nic view of the rx queue */
1398 writel(np->rx_buf_sz, base + NvRegOffloadConfig);
1399 writel((u32) np->ring_addr, base + NvRegRxRingPhysAddr);
1400 if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2)
1401 writel((u32) (np->ring_addr + RX_RING*sizeof(struct ring_desc)), base + NvRegTxRingPhysAddr);
1403 writel((u32) (np->ring_addr + RX_RING*sizeof(struct ring_desc_ex)), base + NvRegTxRingPhysAddr);
1404 writel( ((RX_RING-1) << NVREG_RINGSZ_RXSHIFT) + ((TX_RING-1) << NVREG_RINGSZ_TXSHIFT),
1405 base + NvRegRingSizes);
1407 writel(NVREG_TXRXCTL_KICK|np->desc_ver, get_hwbase(dev) + NvRegTxRxControl);
1410 /* restart rx engine */
1413 spin_unlock(&np->lock);
1414 spin_unlock_bh(&dev->xmit_lock);
1415 enable_irq(dev->irq);
1420 static void nv_copy_mac_to_hw(struct net_device *dev)
1422 u8 *base = get_hwbase(dev);
1425 mac[0] = (dev->dev_addr[0] << 0) + (dev->dev_addr[1] << 8) +
1426 (dev->dev_addr[2] << 16) + (dev->dev_addr[3] << 24);
1427 mac[1] = (dev->dev_addr[4] << 0) + (dev->dev_addr[5] << 8);
1429 writel(mac[0], base + NvRegMacAddrA);
1430 writel(mac[1], base + NvRegMacAddrB);
1434 * nv_set_mac_address: dev->set_mac_address function
1435 * Called with rtnl_lock() held.
1437 static int nv_set_mac_address(struct net_device *dev, void *addr)
1439 struct fe_priv *np = get_nvpriv(dev);
1440 struct sockaddr *macaddr = (struct sockaddr*)addr;
1442 if(!is_valid_ether_addr(macaddr->sa_data))
1443 return -EADDRNOTAVAIL;
1445 /* synchronized against open : rtnl_lock() held by caller */
1446 memcpy(dev->dev_addr, macaddr->sa_data, ETH_ALEN);
1448 if (netif_running(dev)) {
1449 spin_lock_bh(&dev->xmit_lock);
1450 spin_lock_irq(&np->lock);
1452 /* stop rx engine */
1455 /* set mac address */
1456 nv_copy_mac_to_hw(dev);
1458 /* restart rx engine */
1460 spin_unlock_irq(&np->lock);
1461 spin_unlock_bh(&dev->xmit_lock);
1463 nv_copy_mac_to_hw(dev);
1469 * nv_set_multicast: dev->set_multicast function
1470 * Called with dev->xmit_lock held.
1472 static void nv_set_multicast(struct net_device *dev)
1474 struct fe_priv *np = get_nvpriv(dev);
1475 u8 __iomem *base = get_hwbase(dev);
1480 memset(addr, 0, sizeof(addr));
1481 memset(mask, 0, sizeof(mask));
1483 if (dev->flags & IFF_PROMISC) {
1484 printk(KERN_NOTICE "%s: Promiscuous mode enabled.\n", dev->name);
1485 pff = NVREG_PFF_PROMISC;
1487 pff = NVREG_PFF_MYADDR;
1489 if (dev->flags & IFF_ALLMULTI || dev->mc_list) {
1493 alwaysOn[0] = alwaysOn[1] = alwaysOff[0] = alwaysOff[1] = 0xffffffff;
1494 if (dev->flags & IFF_ALLMULTI) {
1495 alwaysOn[0] = alwaysOn[1] = alwaysOff[0] = alwaysOff[1] = 0;
1497 struct dev_mc_list *walk;
1499 walk = dev->mc_list;
1500 while (walk != NULL) {
1502 a = le32_to_cpu(*(u32 *) walk->dmi_addr);
1503 b = le16_to_cpu(*(u16 *) (&walk->dmi_addr[4]));
1511 addr[0] = alwaysOn[0];
1512 addr[1] = alwaysOn[1];
1513 mask[0] = alwaysOn[0] | alwaysOff[0];
1514 mask[1] = alwaysOn[1] | alwaysOff[1];
1517 addr[0] |= NVREG_MCASTADDRA_FORCE;
1518 pff |= NVREG_PFF_ALWAYS;
1519 spin_lock_irq(&np->lock);
1521 writel(addr[0], base + NvRegMulticastAddrA);
1522 writel(addr[1], base + NvRegMulticastAddrB);
1523 writel(mask[0], base + NvRegMulticastMaskA);
1524 writel(mask[1], base + NvRegMulticastMaskB);
1525 writel(pff, base + NvRegPacketFilterFlags);
1526 dprintk(KERN_INFO "%s: reconfiguration for multicast lists.\n",
1529 spin_unlock_irq(&np->lock);
1532 static int nv_update_linkspeed(struct net_device *dev)
1534 struct fe_priv *np = get_nvpriv(dev);
1535 u8 __iomem *base = get_hwbase(dev);
1537 int newls = np->linkspeed;
1538 int newdup = np->duplex;
1541 u32 control_1000, status_1000, phyreg;
1543 /* BMSR_LSTATUS is latched, read it twice:
1544 * we want the current value.
1546 mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ);
1547 mii_status = mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ);
1549 if (!(mii_status & BMSR_LSTATUS)) {
1550 dprintk(KERN_DEBUG "%s: no link detected by phy - falling back to 10HD.\n",
1552 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
1558 if (np->autoneg == 0) {
1559 dprintk(KERN_DEBUG "%s: nv_update_linkspeed: autoneg off, PHY set to 0x%04x.\n",
1560 dev->name, np->fixed_mode);
1561 if (np->fixed_mode & LPA_100FULL) {
1562 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_100;
1564 } else if (np->fixed_mode & LPA_100HALF) {
1565 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_100;
1567 } else if (np->fixed_mode & LPA_10FULL) {
1568 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
1571 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
1577 /* check auto negotiation is complete */
1578 if (!(mii_status & BMSR_ANEGCOMPLETE)) {
1579 /* still in autonegotiation - configure nic for 10 MBit HD and wait. */
1580 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
1583 dprintk(KERN_DEBUG "%s: autoneg not completed - falling back to 10HD.\n", dev->name);
1588 if (np->gigabit == PHY_GIGABIT) {
1589 control_1000 = mii_rw(dev, np->phyaddr, MII_1000BT_CR, MII_READ);
1590 status_1000 = mii_rw(dev, np->phyaddr, MII_1000BT_SR, MII_READ);
1592 if ((control_1000 & ADVERTISE_1000FULL) &&
1593 (status_1000 & LPA_1000FULL)) {
1594 dprintk(KERN_DEBUG "%s: nv_update_linkspeed: GBit ethernet detected.\n",
1596 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_1000;
1602 adv = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ);
1603 lpa = mii_rw(dev, np->phyaddr, MII_LPA, MII_READ);
1604 dprintk(KERN_DEBUG "%s: nv_update_linkspeed: PHY advertises 0x%04x, lpa 0x%04x.\n",
1605 dev->name, adv, lpa);
1607 /* FIXME: handle parallel detection properly */
1609 if (lpa & LPA_100FULL) {
1610 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_100;
1612 } else if (lpa & LPA_100HALF) {
1613 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_100;
1615 } else if (lpa & LPA_10FULL) {
1616 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
1618 } else if (lpa & LPA_10HALF) {
1619 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
1622 dprintk(KERN_DEBUG "%s: bad ability %04x - falling back to 10HD.\n", dev->name, lpa);
1623 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
1628 if (np->duplex == newdup && np->linkspeed == newls)
1631 dprintk(KERN_INFO "%s: changing link setting from %d/%d to %d/%d.\n",
1632 dev->name, np->linkspeed, np->duplex, newls, newdup);
1634 np->duplex = newdup;
1635 np->linkspeed = newls;
1637 if (np->gigabit == PHY_GIGABIT) {
1638 phyreg = readl(base + NvRegRandomSeed);
1639 phyreg &= ~(0x3FF00);
1640 if ((np->linkspeed & 0xFFF) == NVREG_LINKSPEED_10)
1641 phyreg |= NVREG_RNDSEED_FORCE3;
1642 else if ((np->linkspeed & 0xFFF) == NVREG_LINKSPEED_100)
1643 phyreg |= NVREG_RNDSEED_FORCE2;
1644 else if ((np->linkspeed & 0xFFF) == NVREG_LINKSPEED_1000)
1645 phyreg |= NVREG_RNDSEED_FORCE;
1646 writel(phyreg, base + NvRegRandomSeed);
1649 phyreg = readl(base + NvRegPhyInterface);
1650 phyreg &= ~(PHY_HALF|PHY_100|PHY_1000);
1651 if (np->duplex == 0)
1653 if ((np->linkspeed & NVREG_LINKSPEED_MASK) == NVREG_LINKSPEED_100)
1655 else if ((np->linkspeed & NVREG_LINKSPEED_MASK) == NVREG_LINKSPEED_1000)
1657 writel(phyreg, base + NvRegPhyInterface);
1659 writel(NVREG_MISC1_FORCE | ( np->duplex ? 0 : NVREG_MISC1_HD),
1662 writel(np->linkspeed, base + NvRegLinkSpeed);
1668 static void nv_linkchange(struct net_device *dev)
1670 if (nv_update_linkspeed(dev)) {
1671 if (netif_carrier_ok(dev)) {
1674 netif_carrier_on(dev);
1675 printk(KERN_INFO "%s: link up.\n", dev->name);
1679 if (netif_carrier_ok(dev)) {
1680 netif_carrier_off(dev);
1681 printk(KERN_INFO "%s: link down.\n", dev->name);
1687 static void nv_link_irq(struct net_device *dev)
1689 u8 __iomem *base = get_hwbase(dev);
1692 miistat = readl(base + NvRegMIIStatus);
1693 writel(NVREG_MIISTAT_MASK, base + NvRegMIIStatus);
1694 dprintk(KERN_INFO "%s: link change irq, status 0x%x.\n", dev->name, miistat);
1696 if (miistat & (NVREG_MIISTAT_LINKCHANGE))
1698 dprintk(KERN_DEBUG "%s: link change notification done.\n", dev->name);
1701 static irqreturn_t nv_nic_irq(int foo, void *data, struct pt_regs *regs)
1703 struct net_device *dev = (struct net_device *) data;
1704 struct fe_priv *np = get_nvpriv(dev);
1705 u8 __iomem *base = get_hwbase(dev);
1709 dprintk(KERN_DEBUG "%s: nv_nic_irq\n", dev->name);
1712 events = readl(base + NvRegIrqStatus) & NVREG_IRQSTAT_MASK;
1713 writel(NVREG_IRQSTAT_MASK, base + NvRegIrqStatus);
1715 dprintk(KERN_DEBUG "%s: irq: %08x\n", dev->name, events);
1716 if (!(events & np->irqmask))
1719 if (events & (NVREG_IRQ_TX1|NVREG_IRQ_TX_OK|NVREG_IRQ_TX_ERROR|NVREG_IRQ_TX_ERR)) {
1720 spin_lock(&np->lock);
1722 spin_unlock(&np->lock);
1725 if (events & (NVREG_IRQ_RX_ERROR|NVREG_IRQ_RX|NVREG_IRQ_RX_NOBUF)) {
1727 if (nv_alloc_rx(dev)) {
1728 spin_lock(&np->lock);
1729 if (!np->in_shutdown)
1730 mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
1731 spin_unlock(&np->lock);
1735 if (events & NVREG_IRQ_LINK) {
1736 spin_lock(&np->lock);
1738 spin_unlock(&np->lock);
1740 if (np->need_linktimer && time_after(jiffies, np->link_timeout)) {
1741 spin_lock(&np->lock);
1743 spin_unlock(&np->lock);
1744 np->link_timeout = jiffies + LINK_TIMEOUT;
1746 if (events & (NVREG_IRQ_TX_ERR)) {
1747 dprintk(KERN_DEBUG "%s: received irq with events 0x%x. Probably TX fail.\n",
1750 if (events & (NVREG_IRQ_UNKNOWN)) {
1751 printk(KERN_DEBUG "%s: received irq with unknown events 0x%x. Please report\n",
1754 if (i > max_interrupt_work) {
1755 spin_lock(&np->lock);
1756 /* disable interrupts on the nic */
1757 writel(0, base + NvRegIrqMask);
1760 if (!np->in_shutdown)
1761 mod_timer(&np->nic_poll, jiffies + POLL_WAIT);
1762 printk(KERN_DEBUG "%s: too many iterations (%d) in nv_nic_irq.\n", dev->name, i);
1763 spin_unlock(&np->lock);
1768 dprintk(KERN_DEBUG "%s: nv_nic_irq completed\n", dev->name);
1770 return IRQ_RETVAL(i);
1773 static void nv_do_nic_poll(unsigned long data)
1775 struct net_device *dev = (struct net_device *) data;
1776 struct fe_priv *np = get_nvpriv(dev);
1777 u8 __iomem *base = get_hwbase(dev);
1779 disable_irq(dev->irq);
1780 /* FIXME: Do we need synchronize_irq(dev->irq) here? */
1782 * reenable interrupts on the nic, we have to do this before calling
1783 * nv_nic_irq because that may decide to do otherwise
1785 writel(np->irqmask, base + NvRegIrqMask);
1787 nv_nic_irq((int) 0, (void *) data, (struct pt_regs *) NULL);
1788 enable_irq(dev->irq);
1791 #ifdef CONFIG_NET_POLL_CONTROLLER
1792 static void nv_poll_controller(struct net_device *dev)
1794 nv_do_nic_poll((unsigned long) dev);
1798 static void nv_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
1800 struct fe_priv *np = get_nvpriv(dev);
1801 strcpy(info->driver, "forcedeth");
1802 strcpy(info->version, FORCEDETH_VERSION);
1803 strcpy(info->bus_info, pci_name(np->pci_dev));
1806 static void nv_get_wol(struct net_device *dev, struct ethtool_wolinfo *wolinfo)
1808 struct fe_priv *np = get_nvpriv(dev);
1809 wolinfo->supported = WAKE_MAGIC;
1811 spin_lock_irq(&np->lock);
1813 wolinfo->wolopts = WAKE_MAGIC;
1814 spin_unlock_irq(&np->lock);
1817 static int nv_set_wol(struct net_device *dev, struct ethtool_wolinfo *wolinfo)
1819 struct fe_priv *np = get_nvpriv(dev);
1820 u8 __iomem *base = get_hwbase(dev);
1822 spin_lock_irq(&np->lock);
1823 if (wolinfo->wolopts == 0) {
1824 writel(0, base + NvRegWakeUpFlags);
1827 if (wolinfo->wolopts & WAKE_MAGIC) {
1828 writel(NVREG_WAKEUPFLAGS_ENABLE, base + NvRegWakeUpFlags);
1831 spin_unlock_irq(&np->lock);
1835 static int nv_get_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
1837 struct fe_priv *np = netdev_priv(dev);
1840 spin_lock_irq(&np->lock);
1841 ecmd->port = PORT_MII;
1842 if (!netif_running(dev)) {
1843 /* We do not track link speed / duplex setting if the
1844 * interface is disabled. Force a link check */
1845 nv_update_linkspeed(dev);
1847 switch(np->linkspeed & (NVREG_LINKSPEED_MASK)) {
1848 case NVREG_LINKSPEED_10:
1849 ecmd->speed = SPEED_10;
1851 case NVREG_LINKSPEED_100:
1852 ecmd->speed = SPEED_100;
1854 case NVREG_LINKSPEED_1000:
1855 ecmd->speed = SPEED_1000;
1858 ecmd->duplex = DUPLEX_HALF;
1860 ecmd->duplex = DUPLEX_FULL;
1862 ecmd->autoneg = np->autoneg;
1864 ecmd->advertising = ADVERTISED_MII;
1866 ecmd->advertising |= ADVERTISED_Autoneg;
1867 adv = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ);
1869 adv = np->fixed_mode;
1871 if (adv & ADVERTISE_10HALF)
1872 ecmd->advertising |= ADVERTISED_10baseT_Half;
1873 if (adv & ADVERTISE_10FULL)
1874 ecmd->advertising |= ADVERTISED_10baseT_Full;
1875 if (adv & ADVERTISE_100HALF)
1876 ecmd->advertising |= ADVERTISED_100baseT_Half;
1877 if (adv & ADVERTISE_100FULL)
1878 ecmd->advertising |= ADVERTISED_100baseT_Full;
1879 if (np->autoneg && np->gigabit == PHY_GIGABIT) {
1880 adv = mii_rw(dev, np->phyaddr, MII_1000BT_CR, MII_READ);
1881 if (adv & ADVERTISE_1000FULL)
1882 ecmd->advertising |= ADVERTISED_1000baseT_Full;
1885 ecmd->supported = (SUPPORTED_Autoneg |
1886 SUPPORTED_10baseT_Half | SUPPORTED_10baseT_Full |
1887 SUPPORTED_100baseT_Half | SUPPORTED_100baseT_Full |
1889 if (np->gigabit == PHY_GIGABIT)
1890 ecmd->supported |= SUPPORTED_1000baseT_Full;
1892 ecmd->phy_address = np->phyaddr;
1893 ecmd->transceiver = XCVR_EXTERNAL;
1895 /* ignore maxtxpkt, maxrxpkt for now */
1896 spin_unlock_irq(&np->lock);
1900 static int nv_set_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
1902 struct fe_priv *np = netdev_priv(dev);
1904 if (ecmd->port != PORT_MII)
1906 if (ecmd->transceiver != XCVR_EXTERNAL)
1908 if (ecmd->phy_address != np->phyaddr) {
1909 /* TODO: support switching between multiple phys. Should be
1910 * trivial, but not enabled due to lack of test hardware. */
1913 if (ecmd->autoneg == AUTONEG_ENABLE) {
1916 mask = ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
1917 ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full;
1918 if (np->gigabit == PHY_GIGABIT)
1919 mask |= ADVERTISED_1000baseT_Full;
1921 if ((ecmd->advertising & mask) == 0)
1924 } else if (ecmd->autoneg == AUTONEG_DISABLE) {
1925 /* Note: autonegotiation disable, speed 1000 intentionally
1926 * forbidden - noone should need that. */
1928 if (ecmd->speed != SPEED_10 && ecmd->speed != SPEED_100)
1930 if (ecmd->duplex != DUPLEX_HALF && ecmd->duplex != DUPLEX_FULL)
1936 spin_lock_irq(&np->lock);
1937 if (ecmd->autoneg == AUTONEG_ENABLE) {
1942 /* advertise only what has been requested */
1943 adv = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ);
1944 adv &= ~(ADVERTISE_ALL | ADVERTISE_100BASE4);
1945 if (ecmd->advertising & ADVERTISED_10baseT_Half)
1946 adv |= ADVERTISE_10HALF;
1947 if (ecmd->advertising & ADVERTISED_10baseT_Full)
1948 adv |= ADVERTISE_10FULL;
1949 if (ecmd->advertising & ADVERTISED_100baseT_Half)
1950 adv |= ADVERTISE_100HALF;
1951 if (ecmd->advertising & ADVERTISED_100baseT_Full)
1952 adv |= ADVERTISE_100FULL;
1953 mii_rw(dev, np->phyaddr, MII_ADVERTISE, adv);
1955 if (np->gigabit == PHY_GIGABIT) {
1956 adv = mii_rw(dev, np->phyaddr, MII_1000BT_CR, MII_READ);
1957 adv &= ~ADVERTISE_1000FULL;
1958 if (ecmd->advertising & ADVERTISED_1000baseT_Full)
1959 adv |= ADVERTISE_1000FULL;
1960 mii_rw(dev, np->phyaddr, MII_1000BT_CR, adv);
1963 bmcr = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
1964 bmcr |= (BMCR_ANENABLE | BMCR_ANRESTART);
1965 mii_rw(dev, np->phyaddr, MII_BMCR, bmcr);
1972 adv = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ);
1973 adv &= ~(ADVERTISE_ALL | ADVERTISE_100BASE4);
1974 if (ecmd->speed == SPEED_10 && ecmd->duplex == DUPLEX_HALF)
1975 adv |= ADVERTISE_10HALF;
1976 if (ecmd->speed == SPEED_10 && ecmd->duplex == DUPLEX_FULL)
1977 adv |= ADVERTISE_10FULL;
1978 if (ecmd->speed == SPEED_100 && ecmd->duplex == DUPLEX_HALF)
1979 adv |= ADVERTISE_100HALF;
1980 if (ecmd->speed == SPEED_100 && ecmd->duplex == DUPLEX_FULL)
1981 adv |= ADVERTISE_100FULL;
1982 mii_rw(dev, np->phyaddr, MII_ADVERTISE, adv);
1983 np->fixed_mode = adv;
1985 if (np->gigabit == PHY_GIGABIT) {
1986 adv = mii_rw(dev, np->phyaddr, MII_1000BT_CR, MII_READ);
1987 adv &= ~ADVERTISE_1000FULL;
1988 mii_rw(dev, np->phyaddr, MII_1000BT_CR, adv);
1991 bmcr = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
1992 bmcr |= ~(BMCR_ANENABLE|BMCR_SPEED100|BMCR_FULLDPLX);
1993 if (adv & (ADVERTISE_10FULL|ADVERTISE_100FULL))
1994 bmcr |= BMCR_FULLDPLX;
1995 if (adv & (ADVERTISE_100HALF|ADVERTISE_100FULL))
1996 bmcr |= BMCR_SPEED100;
1997 mii_rw(dev, np->phyaddr, MII_BMCR, bmcr);
1999 if (netif_running(dev)) {
2000 /* Wait a bit and then reconfigure the nic. */
2005 spin_unlock_irq(&np->lock);
2010 #define FORCEDETH_REGS_VER 1
2011 #define FORCEDETH_REGS_SIZE 0x400 /* 256 32-bit registers */
2013 static int nv_get_regs_len(struct net_device *dev)
2015 return FORCEDETH_REGS_SIZE;
2018 static void nv_get_regs(struct net_device *dev, struct ethtool_regs *regs, void *buf)
2020 struct fe_priv *np = get_nvpriv(dev);
2021 u8 __iomem *base = get_hwbase(dev);
2025 regs->version = FORCEDETH_REGS_VER;
2026 spin_lock_irq(&np->lock);
2027 for (i=0;i<FORCEDETH_REGS_SIZE/sizeof(u32);i++)
2028 rbuf[i] = readl(base + i*sizeof(u32));
2029 spin_unlock_irq(&np->lock);
2032 static int nv_nway_reset(struct net_device *dev)
2034 struct fe_priv *np = get_nvpriv(dev);
2037 spin_lock_irq(&np->lock);
2041 bmcr = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
2042 bmcr |= (BMCR_ANENABLE | BMCR_ANRESTART);
2043 mii_rw(dev, np->phyaddr, MII_BMCR, bmcr);
2049 spin_unlock_irq(&np->lock);
2054 static struct ethtool_ops ops = {
2055 .get_drvinfo = nv_get_drvinfo,
2056 .get_link = ethtool_op_get_link,
2057 .get_wol = nv_get_wol,
2058 .set_wol = nv_set_wol,
2059 .get_settings = nv_get_settings,
2060 .set_settings = nv_set_settings,
2061 .get_regs_len = nv_get_regs_len,
2062 .get_regs = nv_get_regs,
2063 .nway_reset = nv_nway_reset,
2066 static int nv_open(struct net_device *dev)
2068 struct fe_priv *np = get_nvpriv(dev);
2069 u8 __iomem *base = get_hwbase(dev);
2072 dprintk(KERN_DEBUG "nv_open: begin\n");
2074 /* 1) erase previous misconfiguration */
2075 /* 4.1-1: stop adapter: ignored, 4.3 seems to be overkill */
2076 writel(NVREG_MCASTADDRA_FORCE, base + NvRegMulticastAddrA);
2077 writel(0, base + NvRegMulticastAddrB);
2078 writel(0, base + NvRegMulticastMaskA);
2079 writel(0, base + NvRegMulticastMaskB);
2080 writel(0, base + NvRegPacketFilterFlags);
2082 writel(0, base + NvRegTransmitterControl);
2083 writel(0, base + NvRegReceiverControl);
2085 writel(0, base + NvRegAdapterControl);
2087 /* 2) initialize descriptor rings */
2089 oom = nv_init_ring(dev);
2091 writel(0, base + NvRegLinkSpeed);
2092 writel(0, base + NvRegUnknownTransmitterReg);
2094 writel(0, base + NvRegUnknownSetupReg6);
2096 np->in_shutdown = 0;
2098 /* 3) set mac address */
2099 nv_copy_mac_to_hw(dev);
2101 /* 4) give hw rings */
2102 writel((u32) np->ring_addr, base + NvRegRxRingPhysAddr);
2103 if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2)
2104 writel((u32) (np->ring_addr + RX_RING*sizeof(struct ring_desc)), base + NvRegTxRingPhysAddr);
2106 writel((u32) (np->ring_addr + RX_RING*sizeof(struct ring_desc_ex)), base + NvRegTxRingPhysAddr);
2107 writel( ((RX_RING-1) << NVREG_RINGSZ_RXSHIFT) + ((TX_RING-1) << NVREG_RINGSZ_TXSHIFT),
2108 base + NvRegRingSizes);
2110 /* 5) continue setup */
2111 writel(np->linkspeed, base + NvRegLinkSpeed);
2112 writel(NVREG_UNKSETUP3_VAL1, base + NvRegUnknownSetupReg3);
2113 writel(np->desc_ver, base + NvRegTxRxControl);
2115 writel(NVREG_TXRXCTL_BIT1|np->desc_ver, base + NvRegTxRxControl);
2116 reg_delay(dev, NvRegUnknownSetupReg5, NVREG_UNKSETUP5_BIT31, NVREG_UNKSETUP5_BIT31,
2117 NV_SETUP5_DELAY, NV_SETUP5_DELAYMAX,
2118 KERN_INFO "open: SetupReg5, Bit 31 remained off\n");
2120 writel(0, base + NvRegUnknownSetupReg4);
2121 writel(NVREG_IRQSTAT_MASK, base + NvRegIrqStatus);
2122 writel(NVREG_MIISTAT_MASK2, base + NvRegMIIStatus);
2124 /* 6) continue setup */
2125 writel(NVREG_MISC1_FORCE | NVREG_MISC1_HD, base + NvRegMisc1);
2126 writel(readl(base + NvRegTransmitterStatus), base + NvRegTransmitterStatus);
2127 writel(NVREG_PFF_ALWAYS, base + NvRegPacketFilterFlags);
2128 writel(np->rx_buf_sz, base + NvRegOffloadConfig);
2130 writel(readl(base + NvRegReceiverStatus), base + NvRegReceiverStatus);
2131 get_random_bytes(&i, sizeof(i));
2132 writel(NVREG_RNDSEED_FORCE | (i&NVREG_RNDSEED_MASK), base + NvRegRandomSeed);
2133 writel(NVREG_UNKSETUP1_VAL, base + NvRegUnknownSetupReg1);
2134 writel(NVREG_UNKSETUP2_VAL, base + NvRegUnknownSetupReg2);
2135 writel(NVREG_POLL_DEFAULT, base + NvRegPollingInterval);
2136 writel(NVREG_UNKSETUP6_VAL, base + NvRegUnknownSetupReg6);
2137 writel((np->phyaddr << NVREG_ADAPTCTL_PHYSHIFT)|NVREG_ADAPTCTL_PHYVALID|NVREG_ADAPTCTL_RUNNING,
2138 base + NvRegAdapterControl);
2139 writel(NVREG_MIISPEED_BIT8|NVREG_MIIDELAY, base + NvRegMIISpeed);
2140 writel(NVREG_UNKSETUP4_VAL, base + NvRegUnknownSetupReg4);
2141 writel(NVREG_WAKEUPFLAGS_VAL, base + NvRegWakeUpFlags);
2143 i = readl(base + NvRegPowerState);
2144 if ( (i & NVREG_POWERSTATE_POWEREDUP) == 0)
2145 writel(NVREG_POWERSTATE_POWEREDUP|i, base + NvRegPowerState);
2149 writel(readl(base + NvRegPowerState) | NVREG_POWERSTATE_VALID, base + NvRegPowerState);
2151 writel(0, base + NvRegIrqMask);
2153 writel(NVREG_MIISTAT_MASK2, base + NvRegMIIStatus);
2154 writel(NVREG_IRQSTAT_MASK, base + NvRegIrqStatus);
2157 ret = request_irq(dev->irq, &nv_nic_irq, SA_SHIRQ, dev->name, dev);
2161 /* ask for interrupts */
2162 writel(np->irqmask, base + NvRegIrqMask);
2164 spin_lock_irq(&np->lock);
2165 writel(NVREG_MCASTADDRA_FORCE, base + NvRegMulticastAddrA);
2166 writel(0, base + NvRegMulticastAddrB);
2167 writel(0, base + NvRegMulticastMaskA);
2168 writel(0, base + NvRegMulticastMaskB);
2169 writel(NVREG_PFF_ALWAYS|NVREG_PFF_MYADDR, base + NvRegPacketFilterFlags);
2170 /* One manual link speed update: Interrupts are enabled, future link
2171 * speed changes cause interrupts and are handled by nv_link_irq().
2175 miistat = readl(base + NvRegMIIStatus);
2176 writel(NVREG_MIISTAT_MASK, base + NvRegMIIStatus);
2177 dprintk(KERN_INFO "startup: got 0x%08x.\n", miistat);
2179 ret = nv_update_linkspeed(dev);
2182 netif_start_queue(dev);
2184 netif_carrier_on(dev);
2186 printk("%s: no link during initialization.\n", dev->name);
2187 netif_carrier_off(dev);
2190 mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
2191 spin_unlock_irq(&np->lock);
2199 static int nv_close(struct net_device *dev)
2201 struct fe_priv *np = get_nvpriv(dev);
2204 spin_lock_irq(&np->lock);
2205 np->in_shutdown = 1;
2206 spin_unlock_irq(&np->lock);
2207 synchronize_irq(dev->irq);
2209 del_timer_sync(&np->oom_kick);
2210 del_timer_sync(&np->nic_poll);
2212 netif_stop_queue(dev);
2213 spin_lock_irq(&np->lock);
2218 /* disable interrupts on the nic or we will lock up */
2219 base = get_hwbase(dev);
2220 writel(0, base + NvRegIrqMask);
2222 dprintk(KERN_INFO "%s: Irqmask is zero again\n", dev->name);
2224 spin_unlock_irq(&np->lock);
2226 free_irq(dev->irq, dev);
2233 /* FIXME: power down nic */
2238 static int __devinit nv_probe(struct pci_dev *pci_dev, const struct pci_device_id *id)
2240 struct net_device *dev;
2246 dev = alloc_etherdev(sizeof(struct fe_priv));
2251 np = get_nvpriv(dev);
2252 np->pci_dev = pci_dev;
2253 spin_lock_init(&np->lock);
2254 SET_MODULE_OWNER(dev);
2255 SET_NETDEV_DEV(dev, &pci_dev->dev);
2257 init_timer(&np->oom_kick);
2258 np->oom_kick.data = (unsigned long) dev;
2259 np->oom_kick.function = &nv_do_rx_refill; /* timer handler */
2260 init_timer(&np->nic_poll);
2261 np->nic_poll.data = (unsigned long) dev;
2262 np->nic_poll.function = &nv_do_nic_poll; /* timer handler */
2264 err = pci_enable_device(pci_dev);
2266 printk(KERN_INFO "forcedeth: pci_enable_dev failed (%d) for device %s\n",
2267 err, pci_name(pci_dev));
2271 pci_set_master(pci_dev);
2273 err = pci_request_regions(pci_dev, DRV_NAME);
2279 for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) {
2280 dprintk(KERN_DEBUG "%s: resource %d start %p len %ld flags 0x%08lx.\n",
2281 pci_name(pci_dev), i, (void*)pci_resource_start(pci_dev, i),
2282 pci_resource_len(pci_dev, i),
2283 pci_resource_flags(pci_dev, i));
2284 if (pci_resource_flags(pci_dev, i) & IORESOURCE_MEM &&
2285 pci_resource_len(pci_dev, i) >= NV_PCI_REGSZ) {
2286 addr = pci_resource_start(pci_dev, i);
2290 if (i == DEVICE_COUNT_RESOURCE) {
2291 printk(KERN_INFO "forcedeth: Couldn't find register window for device %s.\n",
2296 /* handle different descriptor versions */
2297 if (id->driver_data & DEV_HAS_HIGH_DMA) {
2298 /* packet format 3: supports 40-bit addressing */
2299 np->desc_ver = DESC_VER_3;
2300 if (pci_set_dma_mask(pci_dev, 0x0000007fffffffffULL)) {
2301 printk(KERN_INFO "forcedeth: 64-bit DMA failed, using 32-bit addressing for device %s.\n",
2304 } else if (id->driver_data & DEV_HAS_LARGEDESC) {
2305 /* packet format 2: supports jumbo frames */
2306 np->desc_ver = DESC_VER_2;
2308 /* original packet format */
2309 np->desc_ver = DESC_VER_1;
2312 np->pkt_limit = NV_PKTLIMIT_1;
2313 if (id->driver_data & DEV_HAS_LARGEDESC)
2314 np->pkt_limit = NV_PKTLIMIT_2;
2317 np->base = ioremap(addr, NV_PCI_REGSZ);
2320 dev->base_addr = (unsigned long)np->base;
2322 dev->irq = pci_dev->irq;
2324 if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) {
2325 np->rx_ring.orig = pci_alloc_consistent(pci_dev,
2326 sizeof(struct ring_desc) * (RX_RING + TX_RING),
2328 if (!np->rx_ring.orig)
2330 np->tx_ring.orig = &np->rx_ring.orig[RX_RING];
2332 np->rx_ring.ex = pci_alloc_consistent(pci_dev,
2333 sizeof(struct ring_desc_ex) * (RX_RING + TX_RING),
2335 if (!np->rx_ring.ex)
2337 np->tx_ring.ex = &np->rx_ring.ex[RX_RING];
2340 dev->open = nv_open;
2341 dev->stop = nv_close;
2342 dev->hard_start_xmit = nv_start_xmit;
2343 dev->get_stats = nv_get_stats;
2344 dev->change_mtu = nv_change_mtu;
2345 dev->set_mac_address = nv_set_mac_address;
2346 dev->set_multicast_list = nv_set_multicast;
2347 #ifdef CONFIG_NET_POLL_CONTROLLER
2348 dev->poll_controller = nv_poll_controller;
2350 SET_ETHTOOL_OPS(dev, &ops);
2351 dev->tx_timeout = nv_tx_timeout;
2352 dev->watchdog_timeo = NV_WATCHDOG_TIMEO;
2354 pci_set_drvdata(pci_dev, dev);
2356 /* read the mac address */
2357 base = get_hwbase(dev);
2358 np->orig_mac[0] = readl(base + NvRegMacAddrA);
2359 np->orig_mac[1] = readl(base + NvRegMacAddrB);
2361 dev->dev_addr[0] = (np->orig_mac[1] >> 8) & 0xff;
2362 dev->dev_addr[1] = (np->orig_mac[1] >> 0) & 0xff;
2363 dev->dev_addr[2] = (np->orig_mac[0] >> 24) & 0xff;
2364 dev->dev_addr[3] = (np->orig_mac[0] >> 16) & 0xff;
2365 dev->dev_addr[4] = (np->orig_mac[0] >> 8) & 0xff;
2366 dev->dev_addr[5] = (np->orig_mac[0] >> 0) & 0xff;
2368 if (!is_valid_ether_addr(dev->dev_addr)) {
2370 * Bad mac address. At least one bios sets the mac address
2371 * to 01:23:45:67:89:ab
2373 printk(KERN_ERR "%s: Invalid Mac address detected: %02x:%02x:%02x:%02x:%02x:%02x\n",
2375 dev->dev_addr[0], dev->dev_addr[1], dev->dev_addr[2],
2376 dev->dev_addr[3], dev->dev_addr[4], dev->dev_addr[5]);
2377 printk(KERN_ERR "Please complain to your hardware vendor. Switching to a random MAC.\n");
2378 dev->dev_addr[0] = 0x00;
2379 dev->dev_addr[1] = 0x00;
2380 dev->dev_addr[2] = 0x6c;
2381 get_random_bytes(&dev->dev_addr[3], 3);
2384 dprintk(KERN_DEBUG "%s: MAC Address %02x:%02x:%02x:%02x:%02x:%02x\n", pci_name(pci_dev),
2385 dev->dev_addr[0], dev->dev_addr[1], dev->dev_addr[2],
2386 dev->dev_addr[3], dev->dev_addr[4], dev->dev_addr[5]);
2389 writel(0, base + NvRegWakeUpFlags);
2392 if (np->desc_ver == DESC_VER_1) {
2393 np->tx_flags = NV_TX_LASTPACKET|NV_TX_VALID;
2395 np->tx_flags = NV_TX2_LASTPACKET|NV_TX2_VALID;
2397 np->irqmask = NVREG_IRQMASK_WANTED;
2398 if (id->driver_data & DEV_NEED_TIMERIRQ)
2399 np->irqmask |= NVREG_IRQ_TIMER;
2400 if (id->driver_data & DEV_NEED_LINKTIMER) {
2401 dprintk(KERN_INFO "%s: link timer on.\n", pci_name(pci_dev));
2402 np->need_linktimer = 1;
2403 np->link_timeout = jiffies + LINK_TIMEOUT;
2405 dprintk(KERN_INFO "%s: link timer off.\n", pci_name(pci_dev));
2406 np->need_linktimer = 0;
2409 /* find a suitable phy */
2410 for (i = 1; i < 32; i++) {
2413 spin_lock_irq(&np->lock);
2414 id1 = mii_rw(dev, i, MII_PHYSID1, MII_READ);
2415 spin_unlock_irq(&np->lock);
2416 if (id1 < 0 || id1 == 0xffff)
2418 spin_lock_irq(&np->lock);
2419 id2 = mii_rw(dev, i, MII_PHYSID2, MII_READ);
2420 spin_unlock_irq(&np->lock);
2421 if (id2 < 0 || id2 == 0xffff)
2424 id1 = (id1 & PHYID1_OUI_MASK) << PHYID1_OUI_SHFT;
2425 id2 = (id2 & PHYID2_OUI_MASK) >> PHYID2_OUI_SHFT;
2426 dprintk(KERN_DEBUG "%s: open: Found PHY %04x:%04x at address %d.\n",
2427 pci_name(pci_dev), id1, id2, i);
2429 np->phy_oui = id1 | id2;
2433 /* PHY in isolate mode? No phy attached and user wants to
2434 * test loopback? Very odd, but can be correct.
2436 printk(KERN_INFO "%s: open: Could not find a valid PHY.\n",
2445 /* set default link speed settings */
2446 np->linkspeed = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
2450 err = register_netdev(dev);
2452 printk(KERN_INFO "forcedeth: unable to register netdev: %d\n", err);
2455 printk(KERN_INFO "%s: forcedeth.c: subsystem: %05x:%04x bound to %s\n",
2456 dev->name, pci_dev->subsystem_vendor, pci_dev->subsystem_device,
2462 if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2)
2463 pci_free_consistent(np->pci_dev, sizeof(struct ring_desc) * (RX_RING + TX_RING),
2464 np->rx_ring.orig, np->ring_addr);
2466 pci_free_consistent(np->pci_dev, sizeof(struct ring_desc_ex) * (RX_RING + TX_RING),
2467 np->rx_ring.ex, np->ring_addr);
2468 pci_set_drvdata(pci_dev, NULL);
2470 iounmap(get_hwbase(dev));
2472 pci_release_regions(pci_dev);
2474 pci_disable_device(pci_dev);
2481 static void __devexit nv_remove(struct pci_dev *pci_dev)
2483 struct net_device *dev = pci_get_drvdata(pci_dev);
2484 struct fe_priv *np = get_nvpriv(dev);
2485 u8 __iomem *base = get_hwbase(dev);
2487 unregister_netdev(dev);
2489 /* special op: write back the misordered MAC address - otherwise
2490 * the next nv_probe would see a wrong address.
2492 writel(np->orig_mac[0], base + NvRegMacAddrA);
2493 writel(np->orig_mac[1], base + NvRegMacAddrB);
2495 /* free all structures */
2496 if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2)
2497 pci_free_consistent(np->pci_dev, sizeof(struct ring_desc) * (RX_RING + TX_RING), np->rx_ring.orig, np->ring_addr);
2499 pci_free_consistent(np->pci_dev, sizeof(struct ring_desc_ex) * (RX_RING + TX_RING), np->rx_ring.ex, np->ring_addr);
2500 iounmap(get_hwbase(dev));
2501 pci_release_regions(pci_dev);
2502 pci_disable_device(pci_dev);
2504 pci_set_drvdata(pci_dev, NULL);
2507 static struct pci_device_id pci_tbl[] = {
2508 { /* nForce Ethernet Controller */
2509 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_1),
2510 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER,
2512 { /* nForce2 Ethernet Controller */
2513 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_2),
2514 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER,
2516 { /* nForce3 Ethernet Controller */
2517 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_3),
2518 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER,
2520 { /* nForce3 Ethernet Controller */
2521 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_4),
2522 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC,
2524 { /* nForce3 Ethernet Controller */
2525 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_5),
2526 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC,
2528 { /* nForce3 Ethernet Controller */
2529 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_6),
2530 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC,
2532 { /* nForce3 Ethernet Controller */
2533 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_7),
2534 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC,
2536 { /* CK804 Ethernet Controller */
2537 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_8),
2538 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_HIGH_DMA,
2540 { /* CK804 Ethernet Controller */
2541 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_9),
2542 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_HIGH_DMA,
2544 { /* MCP04 Ethernet Controller */
2545 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_10),
2546 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_HIGH_DMA,
2548 { /* MCP04 Ethernet Controller */
2549 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_11),
2550 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_HIGH_DMA,
2552 { /* MCP51 Ethernet Controller */
2553 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_12),
2554 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA,
2556 { /* MCP51 Ethernet Controller */
2557 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_13),
2558 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA,
2560 { /* MCP55 Ethernet Controller */
2561 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_14),
2562 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_HIGH_DMA,
2564 { /* MCP55 Ethernet Controller */
2565 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_15),
2566 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_HIGH_DMA,
2571 static struct pci_driver driver = {
2572 .name = "forcedeth",
2573 .id_table = pci_tbl,
2575 .remove = __devexit_p(nv_remove),
2579 static int __init init_nic(void)
2581 printk(KERN_INFO "forcedeth.c: Reverse Engineered nForce ethernet driver. Version %s.\n", FORCEDETH_VERSION);
2582 return pci_module_init(&driver);
2585 static void __exit exit_nic(void)
2587 pci_unregister_driver(&driver);
2590 module_param(max_interrupt_work, int, 0);
2591 MODULE_PARM_DESC(max_interrupt_work, "forcedeth maximum events handled per interrupt");
2593 MODULE_AUTHOR("Manfred Spraul <manfred@colorfullife.com>");
2594 MODULE_DESCRIPTION("Reverse Engineered nForce ethernet driver");
2595 MODULE_LICENSE("GPL");
2597 MODULE_DEVICE_TABLE(pci, pci_tbl);
2599 module_init(init_nic);
2600 module_exit(exit_nic);