2 * forcedeth: Ethernet driver for NVIDIA nForce media access controllers.
4 * Note: This driver is a cleanroom reimplementation based on reverse
5 * engineered documentation written by Carl-Daniel Hailfinger
6 * and Andrew de Quincey. It's neither supported nor endorsed
7 * by NVIDIA Corp. Use at your own risk.
9 * NVIDIA, nForce and other NVIDIA marks are trademarks or registered
10 * trademarks of NVIDIA Corporation in the United States and other
13 * Copyright (C) 2003,4 Manfred Spraul
14 * Copyright (C) 2004 Andrew de Quincey (wol support)
15 * Copyright (C) 2004 Carl-Daniel Hailfinger (invalid MAC handling, insane
16 * IRQ rate fixes, bigendian fixes, cleanups, verification)
17 * Copyright (c) 2004 NVIDIA Corporation
19 * This program is free software; you can redistribute it and/or modify
20 * it under the terms of the GNU General Public License as published by
21 * the Free Software Foundation; either version 2 of the License, or
22 * (at your option) any later version.
24 * This program is distributed in the hope that it will be useful,
25 * but WITHOUT ANY WARRANTY; without even the implied warranty of
26 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
27 * GNU General Public License for more details.
29 * You should have received a copy of the GNU General Public License
30 * along with this program; if not, write to the Free Software
31 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
34 * 0.01: 05 Oct 2003: First release that compiles without warnings.
35 * 0.02: 05 Oct 2003: Fix bug for nv_drain_tx: do not try to free NULL skbs.
36 * Check all PCI BARs for the register window.
37 * udelay added to mii_rw.
38 * 0.03: 06 Oct 2003: Initialize dev->irq.
39 * 0.04: 07 Oct 2003: Initialize np->lock, reduce handled irqs, add printks.
40 * 0.05: 09 Oct 2003: printk removed again, irq status print tx_timeout.
41 * 0.06: 10 Oct 2003: MAC Address read updated, pff flag generation updated,
43 * 0.07: 14 Oct 2003: Further irq mask updates.
44 * 0.08: 20 Oct 2003: rx_desc.Length initialization added, nv_alloc_rx refill
45 * added into irq handler, NULL check for drain_ring.
46 * 0.09: 20 Oct 2003: Basic link speed irq implementation. Only handle the
47 * requested interrupt sources.
48 * 0.10: 20 Oct 2003: First cleanup for release.
49 * 0.11: 21 Oct 2003: hexdump for tx added, rx buffer sizes increased.
50 * MAC Address init fix, set_multicast cleanup.
51 * 0.12: 23 Oct 2003: Cleanups for release.
52 * 0.13: 25 Oct 2003: Limit for concurrent tx packets increased to 10.
53 * Set link speed correctly. start rx before starting
54 * tx (nv_start_rx sets the link speed).
55 * 0.14: 25 Oct 2003: Nic dependant irq mask.
56 * 0.15: 08 Nov 2003: fix smp deadlock with set_multicast_list during
58 * 0.16: 15 Nov 2003: include file cleanup for ppc64, rx buffer size
59 * increased to 1628 bytes.
60 * 0.17: 16 Nov 2003: undo rx buffer size increase. Substract 1 from
62 * 0.18: 17 Nov 2003: fix oops due to late initialization of dev_stats
63 * 0.19: 29 Nov 2003: Handle RxNoBuf, detect & handle invalid mac
64 * addresses, really stop rx if already running
65 * in nv_start_rx, clean up a bit.
66 * 0.20: 07 Dec 2003: alloc fixes
67 * 0.21: 12 Jan 2004: additional alloc fix, nic polling fix.
68 * 0.22: 19 Jan 2004: reprogram timer to a sane rate, avoid lockup
70 * 0.23: 26 Jan 2004: various small cleanups
71 * 0.24: 27 Feb 2004: make driver even less anonymous in backtraces
72 * 0.25: 09 Mar 2004: wol support
73 * 0.26: 03 Jun 2004: netdriver specific annotation, sparse-related fixes
74 * 0.27: 19 Jun 2004: Gigabit support, new descriptor rings,
75 * added CK804/MCP04 device IDs, code fixes
76 * for registers, link status and other minor fixes.
77 * 0.28: 21 Jun 2004: Big cleanup, making driver mostly endian safe
78 * 0.29: 31 Aug 2004: Add backup timer for link change notification.
79 * 0.30: 25 Sep 2004: rx checksum support for nf 250 Gb. Add rx reset
80 * into nv_close, otherwise reenabling for wol can
81 * cause DMA to kfree'd memory.
82 * 0.31: 14 Nov 2004: ethtool support for getting/setting link
84 * 0.32: 16 Apr 2005: RX_ERROR4 handling added.
85 * 0.33: 16 May 2005: Support for MCP51 added.
86 * 0.34: 18 Jun 2005: Add DEV_NEED_LINKTIMER to all nForce nics.
87 * 0.35: 26 Jun 2005: Support for MCP55 added.
88 * 0.36: 28 Jun 2005: Add jumbo frame support.
89 * 0.37: 10 Jul 2005: Additional ethtool support, cleanup of pci id list
90 * 0.38: 16 Jul 2005: tx irq rewrite: Use global flags instead of
92 * 0.39: 18 Jul 2005: Add 64bit descriptor support.
93 * 0.40: 19 Jul 2005: Add support for mac address change.
94 * 0.41: 30 Jul 2005: Write back original MAC in nv_close instead
96 * 0.42: 06 Aug 2005: Fix lack of link speed initialization
97 * in the second (and later) nv_open call
98 * 0.43: 10 Aug 2005: Add support for tx checksum.
99 * 0.44: 20 Aug 2005: Add support for scatter gather and segmentation.
100 * 0.45: 18 Sep 2005: Remove nv_stop/start_rx from every link check
103 * We suspect that on some hardware no TX done interrupts are generated.
104 * This means recovery from netif_stop_queue only happens if the hw timer
105 * interrupt fires (100 times/second, configurable with NVREG_POLL_DEFAULT)
106 * and the timer is active in the IRQMask, or if a rx packet arrives by chance.
107 * If your hardware reliably generates tx done interrupts, then you can remove
108 * DEV_NEED_TIMERIRQ from the driver_data flags.
109 * DEV_NEED_TIMERIRQ will not harm you on sane hardware, only generating a few
110 * superfluous timer interrupts from the nic.
112 #define FORCEDETH_VERSION "0.45"
113 #define DRV_NAME "forcedeth"
115 #include <linux/module.h>
116 #include <linux/types.h>
117 #include <linux/pci.h>
118 #include <linux/interrupt.h>
119 #include <linux/netdevice.h>
120 #include <linux/etherdevice.h>
121 #include <linux/delay.h>
122 #include <linux/spinlock.h>
123 #include <linux/ethtool.h>
124 #include <linux/timer.h>
125 #include <linux/skbuff.h>
126 #include <linux/mii.h>
127 #include <linux/random.h>
128 #include <linux/init.h>
129 #include <linux/if_vlan.h>
133 #include <asm/uaccess.h>
134 #include <asm/system.h>
137 #define dprintk printk
139 #define dprintk(x...) do { } while (0)
147 #define DEV_NEED_TIMERIRQ 0x0001 /* set the timer irq flag in the irq mask */
148 #define DEV_NEED_LINKTIMER 0x0002 /* poll link settings. Relies on the timer irq */
149 #define DEV_HAS_LARGEDESC 0x0004 /* device supports jumbo frames and needs packet format 2 */
150 #define DEV_HAS_HIGH_DMA 0x0008 /* device supports 64bit dma */
151 #define DEV_HAS_CHECKSUM 0x0010 /* device supports tx and rx checksum offloads */
154 NvRegIrqStatus = 0x000,
155 #define NVREG_IRQSTAT_MIIEVENT 0x040
156 #define NVREG_IRQSTAT_MASK 0x1ff
157 NvRegIrqMask = 0x004,
158 #define NVREG_IRQ_RX_ERROR 0x0001
159 #define NVREG_IRQ_RX 0x0002
160 #define NVREG_IRQ_RX_NOBUF 0x0004
161 #define NVREG_IRQ_TX_ERR 0x0008
162 #define NVREG_IRQ_TX_OK 0x0010
163 #define NVREG_IRQ_TIMER 0x0020
164 #define NVREG_IRQ_LINK 0x0040
165 #define NVREG_IRQ_TX_ERROR 0x0080
166 #define NVREG_IRQ_TX1 0x0100
167 #define NVREG_IRQMASK_WANTED 0x00df
169 #define NVREG_IRQ_UNKNOWN (~(NVREG_IRQ_RX_ERROR|NVREG_IRQ_RX|NVREG_IRQ_RX_NOBUF|NVREG_IRQ_TX_ERR| \
170 NVREG_IRQ_TX_OK|NVREG_IRQ_TIMER|NVREG_IRQ_LINK|NVREG_IRQ_TX_ERROR| \
173 NvRegUnknownSetupReg6 = 0x008,
174 #define NVREG_UNKSETUP6_VAL 3
177 * NVREG_POLL_DEFAULT is the interval length of the timer source on the nic
178 * NVREG_POLL_DEFAULT=97 would result in an interval length of 1 ms
180 NvRegPollingInterval = 0x00c,
181 #define NVREG_POLL_DEFAULT 970
183 #define NVREG_MISC1_HD 0x02
184 #define NVREG_MISC1_FORCE 0x3b0f3c
186 NvRegTransmitterControl = 0x084,
187 #define NVREG_XMITCTL_START 0x01
188 NvRegTransmitterStatus = 0x088,
189 #define NVREG_XMITSTAT_BUSY 0x01
191 NvRegPacketFilterFlags = 0x8c,
192 #define NVREG_PFF_ALWAYS 0x7F0008
193 #define NVREG_PFF_PROMISC 0x80
194 #define NVREG_PFF_MYADDR 0x20
196 NvRegOffloadConfig = 0x90,
197 #define NVREG_OFFLOAD_HOMEPHY 0x601
198 #define NVREG_OFFLOAD_NORMAL RX_NIC_BUFSIZE
199 NvRegReceiverControl = 0x094,
200 #define NVREG_RCVCTL_START 0x01
201 NvRegReceiverStatus = 0x98,
202 #define NVREG_RCVSTAT_BUSY 0x01
204 NvRegRandomSeed = 0x9c,
205 #define NVREG_RNDSEED_MASK 0x00ff
206 #define NVREG_RNDSEED_FORCE 0x7f00
207 #define NVREG_RNDSEED_FORCE2 0x2d00
208 #define NVREG_RNDSEED_FORCE3 0x7400
210 NvRegUnknownSetupReg1 = 0xA0,
211 #define NVREG_UNKSETUP1_VAL 0x16070f
212 NvRegUnknownSetupReg2 = 0xA4,
213 #define NVREG_UNKSETUP2_VAL 0x16
214 NvRegMacAddrA = 0xA8,
215 NvRegMacAddrB = 0xAC,
216 NvRegMulticastAddrA = 0xB0,
217 #define NVREG_MCASTADDRA_FORCE 0x01
218 NvRegMulticastAddrB = 0xB4,
219 NvRegMulticastMaskA = 0xB8,
220 NvRegMulticastMaskB = 0xBC,
222 NvRegPhyInterface = 0xC0,
223 #define PHY_RGMII 0x10000000
225 NvRegTxRingPhysAddr = 0x100,
226 NvRegRxRingPhysAddr = 0x104,
227 NvRegRingSizes = 0x108,
228 #define NVREG_RINGSZ_TXSHIFT 0
229 #define NVREG_RINGSZ_RXSHIFT 16
230 NvRegUnknownTransmitterReg = 0x10c,
231 NvRegLinkSpeed = 0x110,
232 #define NVREG_LINKSPEED_FORCE 0x10000
233 #define NVREG_LINKSPEED_10 1000
234 #define NVREG_LINKSPEED_100 100
235 #define NVREG_LINKSPEED_1000 50
236 #define NVREG_LINKSPEED_MASK (0xFFF)
237 NvRegUnknownSetupReg5 = 0x130,
238 #define NVREG_UNKSETUP5_BIT31 (1<<31)
239 NvRegUnknownSetupReg3 = 0x13c,
240 #define NVREG_UNKSETUP3_VAL1 0x200010
241 NvRegTxRxControl = 0x144,
242 #define NVREG_TXRXCTL_KICK 0x0001
243 #define NVREG_TXRXCTL_BIT1 0x0002
244 #define NVREG_TXRXCTL_BIT2 0x0004
245 #define NVREG_TXRXCTL_IDLE 0x0008
246 #define NVREG_TXRXCTL_RESET 0x0010
247 #define NVREG_TXRXCTL_RXCHECK 0x0400
248 #define NVREG_TXRXCTL_DESC_1 0
249 #define NVREG_TXRXCTL_DESC_2 0x02100
250 #define NVREG_TXRXCTL_DESC_3 0x02200
251 NvRegMIIStatus = 0x180,
252 #define NVREG_MIISTAT_ERROR 0x0001
253 #define NVREG_MIISTAT_LINKCHANGE 0x0008
254 #define NVREG_MIISTAT_MASK 0x000f
255 #define NVREG_MIISTAT_MASK2 0x000f
256 NvRegUnknownSetupReg4 = 0x184,
257 #define NVREG_UNKSETUP4_VAL 8
259 NvRegAdapterControl = 0x188,
260 #define NVREG_ADAPTCTL_START 0x02
261 #define NVREG_ADAPTCTL_LINKUP 0x04
262 #define NVREG_ADAPTCTL_PHYVALID 0x40000
263 #define NVREG_ADAPTCTL_RUNNING 0x100000
264 #define NVREG_ADAPTCTL_PHYSHIFT 24
265 NvRegMIISpeed = 0x18c,
266 #define NVREG_MIISPEED_BIT8 (1<<8)
267 #define NVREG_MIIDELAY 5
268 NvRegMIIControl = 0x190,
269 #define NVREG_MIICTL_INUSE 0x08000
270 #define NVREG_MIICTL_WRITE 0x00400
271 #define NVREG_MIICTL_ADDRSHIFT 5
272 NvRegMIIData = 0x194,
273 NvRegWakeUpFlags = 0x200,
274 #define NVREG_WAKEUPFLAGS_VAL 0x7770
275 #define NVREG_WAKEUPFLAGS_BUSYSHIFT 24
276 #define NVREG_WAKEUPFLAGS_ENABLESHIFT 16
277 #define NVREG_WAKEUPFLAGS_D3SHIFT 12
278 #define NVREG_WAKEUPFLAGS_D2SHIFT 8
279 #define NVREG_WAKEUPFLAGS_D1SHIFT 4
280 #define NVREG_WAKEUPFLAGS_D0SHIFT 0
281 #define NVREG_WAKEUPFLAGS_ACCEPT_MAGPAT 0x01
282 #define NVREG_WAKEUPFLAGS_ACCEPT_WAKEUPPAT 0x02
283 #define NVREG_WAKEUPFLAGS_ACCEPT_LINKCHANGE 0x04
284 #define NVREG_WAKEUPFLAGS_ENABLE 0x1111
286 NvRegPatternCRC = 0x204,
287 NvRegPatternMask = 0x208,
288 NvRegPowerCap = 0x268,
289 #define NVREG_POWERCAP_D3SUPP (1<<30)
290 #define NVREG_POWERCAP_D2SUPP (1<<26)
291 #define NVREG_POWERCAP_D1SUPP (1<<25)
292 NvRegPowerState = 0x26c,
293 #define NVREG_POWERSTATE_POWEREDUP 0x8000
294 #define NVREG_POWERSTATE_VALID 0x0100
295 #define NVREG_POWERSTATE_MASK 0x0003
296 #define NVREG_POWERSTATE_D0 0x0000
297 #define NVREG_POWERSTATE_D1 0x0001
298 #define NVREG_POWERSTATE_D2 0x0002
299 #define NVREG_POWERSTATE_D3 0x0003
302 /* Big endian: should work, but is untested */
308 struct ring_desc_ex {
309 u32 PacketBufferHigh;
315 typedef union _ring_type {
316 struct ring_desc* orig;
317 struct ring_desc_ex* ex;
320 #define FLAG_MASK_V1 0xffff0000
321 #define FLAG_MASK_V2 0xffffc000
322 #define LEN_MASK_V1 (0xffffffff ^ FLAG_MASK_V1)
323 #define LEN_MASK_V2 (0xffffffff ^ FLAG_MASK_V2)
325 #define NV_TX_LASTPACKET (1<<16)
326 #define NV_TX_RETRYERROR (1<<19)
327 #define NV_TX_FORCED_INTERRUPT (1<<24)
328 #define NV_TX_DEFERRED (1<<26)
329 #define NV_TX_CARRIERLOST (1<<27)
330 #define NV_TX_LATECOLLISION (1<<28)
331 #define NV_TX_UNDERFLOW (1<<29)
332 #define NV_TX_ERROR (1<<30)
333 #define NV_TX_VALID (1<<31)
335 #define NV_TX2_LASTPACKET (1<<29)
336 #define NV_TX2_RETRYERROR (1<<18)
337 #define NV_TX2_FORCED_INTERRUPT (1<<30)
338 #define NV_TX2_DEFERRED (1<<25)
339 #define NV_TX2_CARRIERLOST (1<<26)
340 #define NV_TX2_LATECOLLISION (1<<27)
341 #define NV_TX2_UNDERFLOW (1<<28)
342 /* error and valid are the same for both */
343 #define NV_TX2_ERROR (1<<30)
344 #define NV_TX2_VALID (1<<31)
345 #define NV_TX2_TSO (1<<28)
346 #define NV_TX2_TSO_SHIFT 14
347 #define NV_TX2_CHECKSUM_L3 (1<<27)
348 #define NV_TX2_CHECKSUM_L4 (1<<26)
350 #define NV_RX_DESCRIPTORVALID (1<<16)
351 #define NV_RX_MISSEDFRAME (1<<17)
352 #define NV_RX_SUBSTRACT1 (1<<18)
353 #define NV_RX_ERROR1 (1<<23)
354 #define NV_RX_ERROR2 (1<<24)
355 #define NV_RX_ERROR3 (1<<25)
356 #define NV_RX_ERROR4 (1<<26)
357 #define NV_RX_CRCERR (1<<27)
358 #define NV_RX_OVERFLOW (1<<28)
359 #define NV_RX_FRAMINGERR (1<<29)
360 #define NV_RX_ERROR (1<<30)
361 #define NV_RX_AVAIL (1<<31)
363 #define NV_RX2_CHECKSUMMASK (0x1C000000)
364 #define NV_RX2_CHECKSUMOK1 (0x10000000)
365 #define NV_RX2_CHECKSUMOK2 (0x14000000)
366 #define NV_RX2_CHECKSUMOK3 (0x18000000)
367 #define NV_RX2_DESCRIPTORVALID (1<<29)
368 #define NV_RX2_SUBSTRACT1 (1<<25)
369 #define NV_RX2_ERROR1 (1<<18)
370 #define NV_RX2_ERROR2 (1<<19)
371 #define NV_RX2_ERROR3 (1<<20)
372 #define NV_RX2_ERROR4 (1<<21)
373 #define NV_RX2_CRCERR (1<<22)
374 #define NV_RX2_OVERFLOW (1<<23)
375 #define NV_RX2_FRAMINGERR (1<<24)
376 /* error and avail are the same for both */
377 #define NV_RX2_ERROR (1<<30)
378 #define NV_RX2_AVAIL (1<<31)
380 /* Miscelaneous hardware related defines: */
381 #define NV_PCI_REGSZ 0x270
383 /* various timeout delays: all in usec */
384 #define NV_TXRX_RESET_DELAY 4
385 #define NV_TXSTOP_DELAY1 10
386 #define NV_TXSTOP_DELAY1MAX 500000
387 #define NV_TXSTOP_DELAY2 100
388 #define NV_RXSTOP_DELAY1 10
389 #define NV_RXSTOP_DELAY1MAX 500000
390 #define NV_RXSTOP_DELAY2 100
391 #define NV_SETUP5_DELAY 5
392 #define NV_SETUP5_DELAYMAX 50000
393 #define NV_POWERUP_DELAY 5
394 #define NV_POWERUP_DELAYMAX 5000
395 #define NV_MIIBUSY_DELAY 50
396 #define NV_MIIPHY_DELAY 10
397 #define NV_MIIPHY_DELAYMAX 10000
399 #define NV_WAKEUPPATTERNS 5
400 #define NV_WAKEUPMASKENTRIES 4
402 /* General driver defaults */
403 #define NV_WATCHDOG_TIMEO (5*HZ)
408 * If your nic mysteriously hangs then try to reduce the limits
409 * to 1/0: It might be required to set NV_TX_LASTPACKET in the
410 * last valid ring entry. But this would be impossible to
411 * implement - probably a disassembly error.
413 #define TX_LIMIT_STOP 63
414 #define TX_LIMIT_START 62
416 /* rx/tx mac addr + type + vlan + align + slack*/
417 #define NV_RX_HEADERS (64)
418 /* even more slack. */
419 #define NV_RX_ALLOC_PAD (64)
421 /* maximum mtu size */
422 #define NV_PKTLIMIT_1 ETH_DATA_LEN /* hard limit not known */
423 #define NV_PKTLIMIT_2 9100 /* Actual limit according to NVidia: 9202 */
425 #define OOM_REFILL (1+HZ/20)
426 #define POLL_WAIT (1+HZ/100)
427 #define LINK_TIMEOUT (3*HZ)
431 * The nic supports three different descriptor types:
432 * - DESC_VER_1: Original
433 * - DESC_VER_2: support for jumbo frames.
434 * - DESC_VER_3: 64-bit format.
441 #define PHY_OUI_MARVELL 0x5043
442 #define PHY_OUI_CICADA 0x03f1
443 #define PHYID1_OUI_MASK 0x03ff
444 #define PHYID1_OUI_SHFT 6
445 #define PHYID2_OUI_MASK 0xfc00
446 #define PHYID2_OUI_SHFT 10
447 #define PHY_INIT1 0x0f000
448 #define PHY_INIT2 0x0e00
449 #define PHY_INIT3 0x01000
450 #define PHY_INIT4 0x0200
451 #define PHY_INIT5 0x0004
452 #define PHY_INIT6 0x02000
453 #define PHY_GIGABIT 0x0100
455 #define PHY_TIMEOUT 0x1
456 #define PHY_ERROR 0x2
460 #define PHY_HALF 0x100
462 /* FIXME: MII defines that should be added to <linux/mii.h> */
463 #define MII_1000BT_CR 0x09
464 #define MII_1000BT_SR 0x0a
465 #define ADVERTISE_1000FULL 0x0200
466 #define ADVERTISE_1000HALF 0x0100
467 #define LPA_1000FULL 0x0800
468 #define LPA_1000HALF 0x0400
473 * All hardware access under dev->priv->lock, except the performance
475 * - rx is (pseudo-) lockless: it relies on the single-threading provided
476 * by the arch code for interrupts.
477 * - tx setup is lockless: it relies on dev->xmit_lock. Actual submission
478 * needs dev->priv->lock :-(
479 * - set_multicast_list: preparation lockless, relies on dev->xmit_lock.
482 /* in dev: base, irq */
487 * Locking: spin_lock(&np->lock); */
488 struct net_device_stats stats;
496 unsigned int phy_oui;
499 /* General data: RO fields */
500 dma_addr_t ring_addr;
501 struct pci_dev *pci_dev;
509 /* rx specific fields.
510 * Locking: Within irq hander or disable_irq+spin_lock(&np->lock);
513 unsigned int cur_rx, refill_rx;
514 struct sk_buff *rx_skbuff[RX_RING];
515 dma_addr_t rx_dma[RX_RING];
516 unsigned int rx_buf_sz;
517 unsigned int pkt_limit;
518 struct timer_list oom_kick;
519 struct timer_list nic_poll;
521 /* media detection workaround.
522 * Locking: Within irq hander or disable_irq+spin_lock(&np->lock);
525 unsigned long link_timeout;
527 * tx specific fields.
530 unsigned int next_tx, nic_tx;
531 struct sk_buff *tx_skbuff[TX_RING];
532 dma_addr_t tx_dma[TX_RING];
537 * Maximum number of loops until we assume that a bit in the irq mask
538 * is stuck. Overridable with module param.
540 static int max_interrupt_work = 5;
542 static inline struct fe_priv *get_nvpriv(struct net_device *dev)
544 return netdev_priv(dev);
547 static inline u8 __iomem *get_hwbase(struct net_device *dev)
549 return ((struct fe_priv *)netdev_priv(dev))->base;
552 static inline void pci_push(u8 __iomem *base)
554 /* force out pending posted writes */
558 static inline u32 nv_descr_getlength(struct ring_desc *prd, u32 v)
560 return le32_to_cpu(prd->FlagLen)
561 & ((v == DESC_VER_1) ? LEN_MASK_V1 : LEN_MASK_V2);
564 static inline u32 nv_descr_getlength_ex(struct ring_desc_ex *prd, u32 v)
566 return le32_to_cpu(prd->FlagLen) & LEN_MASK_V2;
569 static int reg_delay(struct net_device *dev, int offset, u32 mask, u32 target,
570 int delay, int delaymax, const char *msg)
572 u8 __iomem *base = get_hwbase(dev);
583 } while ((readl(base + offset) & mask) != target);
587 #define MII_READ (-1)
588 /* mii_rw: read/write a register on the PHY.
590 * Caller must guarantee serialization
592 static int mii_rw(struct net_device *dev, int addr, int miireg, int value)
594 u8 __iomem *base = get_hwbase(dev);
598 writel(NVREG_MIISTAT_MASK, base + NvRegMIIStatus);
600 reg = readl(base + NvRegMIIControl);
601 if (reg & NVREG_MIICTL_INUSE) {
602 writel(NVREG_MIICTL_INUSE, base + NvRegMIIControl);
603 udelay(NV_MIIBUSY_DELAY);
606 reg = (addr << NVREG_MIICTL_ADDRSHIFT) | miireg;
607 if (value != MII_READ) {
608 writel(value, base + NvRegMIIData);
609 reg |= NVREG_MIICTL_WRITE;
611 writel(reg, base + NvRegMIIControl);
613 if (reg_delay(dev, NvRegMIIControl, NVREG_MIICTL_INUSE, 0,
614 NV_MIIPHY_DELAY, NV_MIIPHY_DELAYMAX, NULL)) {
615 dprintk(KERN_DEBUG "%s: mii_rw of reg %d at PHY %d timed out.\n",
616 dev->name, miireg, addr);
618 } else if (value != MII_READ) {
619 /* it was a write operation - fewer failures are detectable */
620 dprintk(KERN_DEBUG "%s: mii_rw wrote 0x%x to reg %d at PHY %d\n",
621 dev->name, value, miireg, addr);
623 } else if (readl(base + NvRegMIIStatus) & NVREG_MIISTAT_ERROR) {
624 dprintk(KERN_DEBUG "%s: mii_rw of reg %d at PHY %d failed.\n",
625 dev->name, miireg, addr);
628 retval = readl(base + NvRegMIIData);
629 dprintk(KERN_DEBUG "%s: mii_rw read from reg %d at PHY %d: 0x%x.\n",
630 dev->name, miireg, addr, retval);
636 static int phy_reset(struct net_device *dev)
638 struct fe_priv *np = netdev_priv(dev);
640 unsigned int tries = 0;
642 miicontrol = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
643 miicontrol |= BMCR_RESET;
644 if (mii_rw(dev, np->phyaddr, MII_BMCR, miicontrol)) {
651 /* must wait till reset is deasserted */
652 while (miicontrol & BMCR_RESET) {
654 miicontrol = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
655 /* FIXME: 100 tries seem excessive */
662 static int phy_init(struct net_device *dev)
664 struct fe_priv *np = get_nvpriv(dev);
665 u8 __iomem *base = get_hwbase(dev);
666 u32 phyinterface, phy_reserved, mii_status, mii_control, mii_control_1000,reg;
668 /* set advertise register */
669 reg = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ);
670 reg |= (ADVERTISE_10HALF|ADVERTISE_10FULL|ADVERTISE_100HALF|ADVERTISE_100FULL|0x800|0x400);
671 if (mii_rw(dev, np->phyaddr, MII_ADVERTISE, reg)) {
672 printk(KERN_INFO "%s: phy write to advertise failed.\n", pci_name(np->pci_dev));
676 /* get phy interface type */
677 phyinterface = readl(base + NvRegPhyInterface);
679 /* see if gigabit phy */
680 mii_status = mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ);
681 if (mii_status & PHY_GIGABIT) {
682 np->gigabit = PHY_GIGABIT;
683 mii_control_1000 = mii_rw(dev, np->phyaddr, MII_1000BT_CR, MII_READ);
684 mii_control_1000 &= ~ADVERTISE_1000HALF;
685 if (phyinterface & PHY_RGMII)
686 mii_control_1000 |= ADVERTISE_1000FULL;
688 mii_control_1000 &= ~ADVERTISE_1000FULL;
690 if (mii_rw(dev, np->phyaddr, MII_1000BT_CR, mii_control_1000)) {
691 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
699 if (phy_reset(dev)) {
700 printk(KERN_INFO "%s: phy reset failed\n", pci_name(np->pci_dev));
704 /* phy vendor specific configuration */
705 if ((np->phy_oui == PHY_OUI_CICADA) && (phyinterface & PHY_RGMII) ) {
706 phy_reserved = mii_rw(dev, np->phyaddr, MII_RESV1, MII_READ);
707 phy_reserved &= ~(PHY_INIT1 | PHY_INIT2);
708 phy_reserved |= (PHY_INIT3 | PHY_INIT4);
709 if (mii_rw(dev, np->phyaddr, MII_RESV1, phy_reserved)) {
710 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
713 phy_reserved = mii_rw(dev, np->phyaddr, MII_NCONFIG, MII_READ);
714 phy_reserved |= PHY_INIT5;
715 if (mii_rw(dev, np->phyaddr, MII_NCONFIG, phy_reserved)) {
716 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
720 if (np->phy_oui == PHY_OUI_CICADA) {
721 phy_reserved = mii_rw(dev, np->phyaddr, MII_SREVISION, MII_READ);
722 phy_reserved |= PHY_INIT6;
723 if (mii_rw(dev, np->phyaddr, MII_SREVISION, phy_reserved)) {
724 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
729 /* restart auto negotiation */
730 mii_control = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
731 mii_control |= (BMCR_ANRESTART | BMCR_ANENABLE);
732 if (mii_rw(dev, np->phyaddr, MII_BMCR, mii_control)) {
739 static void nv_start_rx(struct net_device *dev)
741 struct fe_priv *np = netdev_priv(dev);
742 u8 __iomem *base = get_hwbase(dev);
744 dprintk(KERN_DEBUG "%s: nv_start_rx\n", dev->name);
745 /* Already running? Stop it. */
746 if (readl(base + NvRegReceiverControl) & NVREG_RCVCTL_START) {
747 writel(0, base + NvRegReceiverControl);
750 writel(np->linkspeed, base + NvRegLinkSpeed);
752 writel(NVREG_RCVCTL_START, base + NvRegReceiverControl);
753 dprintk(KERN_DEBUG "%s: nv_start_rx to duplex %d, speed 0x%08x.\n",
754 dev->name, np->duplex, np->linkspeed);
758 static void nv_stop_rx(struct net_device *dev)
760 u8 __iomem *base = get_hwbase(dev);
762 dprintk(KERN_DEBUG "%s: nv_stop_rx\n", dev->name);
763 writel(0, base + NvRegReceiverControl);
764 reg_delay(dev, NvRegReceiverStatus, NVREG_RCVSTAT_BUSY, 0,
765 NV_RXSTOP_DELAY1, NV_RXSTOP_DELAY1MAX,
766 KERN_INFO "nv_stop_rx: ReceiverStatus remained busy");
768 udelay(NV_RXSTOP_DELAY2);
769 writel(0, base + NvRegLinkSpeed);
772 static void nv_start_tx(struct net_device *dev)
774 u8 __iomem *base = get_hwbase(dev);
776 dprintk(KERN_DEBUG "%s: nv_start_tx\n", dev->name);
777 writel(NVREG_XMITCTL_START, base + NvRegTransmitterControl);
781 static void nv_stop_tx(struct net_device *dev)
783 u8 __iomem *base = get_hwbase(dev);
785 dprintk(KERN_DEBUG "%s: nv_stop_tx\n", dev->name);
786 writel(0, base + NvRegTransmitterControl);
787 reg_delay(dev, NvRegTransmitterStatus, NVREG_XMITSTAT_BUSY, 0,
788 NV_TXSTOP_DELAY1, NV_TXSTOP_DELAY1MAX,
789 KERN_INFO "nv_stop_tx: TransmitterStatus remained busy");
791 udelay(NV_TXSTOP_DELAY2);
792 writel(0, base + NvRegUnknownTransmitterReg);
795 static void nv_txrx_reset(struct net_device *dev)
797 struct fe_priv *np = netdev_priv(dev);
798 u8 __iomem *base = get_hwbase(dev);
800 dprintk(KERN_DEBUG "%s: nv_txrx_reset\n", dev->name);
801 writel(NVREG_TXRXCTL_BIT2 | NVREG_TXRXCTL_RESET | np->txrxctl_bits, base + NvRegTxRxControl);
803 udelay(NV_TXRX_RESET_DELAY);
804 writel(NVREG_TXRXCTL_BIT2 | np->txrxctl_bits, base + NvRegTxRxControl);
809 * nv_get_stats: dev->get_stats function
810 * Get latest stats value from the nic.
811 * Called with read_lock(&dev_base_lock) held for read -
812 * only synchronized against unregister_netdevice.
814 static struct net_device_stats *nv_get_stats(struct net_device *dev)
816 struct fe_priv *np = netdev_priv(dev);
818 /* It seems that the nic always generates interrupts and doesn't
819 * accumulate errors internally. Thus the current values in np->stats
820 * are already up to date.
826 * nv_alloc_rx: fill rx ring entries.
827 * Return 1 if the allocations for the skbs failed and the
828 * rx engine is without Available descriptors
830 static int nv_alloc_rx(struct net_device *dev)
832 struct fe_priv *np = netdev_priv(dev);
833 unsigned int refill_rx = np->refill_rx;
836 while (np->cur_rx != refill_rx) {
839 nr = refill_rx % RX_RING;
840 if (np->rx_skbuff[nr] == NULL) {
842 skb = dev_alloc_skb(np->rx_buf_sz + NV_RX_ALLOC_PAD);
847 np->rx_skbuff[nr] = skb;
849 skb = np->rx_skbuff[nr];
851 np->rx_dma[nr] = pci_map_single(np->pci_dev, skb->data, skb->len,
853 if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) {
854 np->rx_ring.orig[nr].PacketBuffer = cpu_to_le32(np->rx_dma[nr]);
856 np->rx_ring.orig[nr].FlagLen = cpu_to_le32(np->rx_buf_sz | NV_RX_AVAIL);
858 np->rx_ring.ex[nr].PacketBufferHigh = cpu_to_le64(np->rx_dma[nr]) >> 32;
859 np->rx_ring.ex[nr].PacketBufferLow = cpu_to_le64(np->rx_dma[nr]) & 0x0FFFFFFFF;
861 np->rx_ring.ex[nr].FlagLen = cpu_to_le32(np->rx_buf_sz | NV_RX2_AVAIL);
863 dprintk(KERN_DEBUG "%s: nv_alloc_rx: Packet %d marked as Available\n",
864 dev->name, refill_rx);
867 np->refill_rx = refill_rx;
868 if (np->cur_rx - refill_rx == RX_RING)
873 static void nv_do_rx_refill(unsigned long data)
875 struct net_device *dev = (struct net_device *) data;
876 struct fe_priv *np = netdev_priv(dev);
878 disable_irq(dev->irq);
879 if (nv_alloc_rx(dev)) {
880 spin_lock(&np->lock);
881 if (!np->in_shutdown)
882 mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
883 spin_unlock(&np->lock);
885 enable_irq(dev->irq);
888 static void nv_init_rx(struct net_device *dev)
890 struct fe_priv *np = netdev_priv(dev);
893 np->cur_rx = RX_RING;
895 for (i = 0; i < RX_RING; i++)
896 if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2)
897 np->rx_ring.orig[i].FlagLen = 0;
899 np->rx_ring.ex[i].FlagLen = 0;
902 static void nv_init_tx(struct net_device *dev)
904 struct fe_priv *np = netdev_priv(dev);
907 np->next_tx = np->nic_tx = 0;
908 for (i = 0; i < TX_RING; i++) {
909 if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2)
910 np->tx_ring.orig[i].FlagLen = 0;
912 np->tx_ring.ex[i].FlagLen = 0;
913 np->tx_skbuff[i] = NULL;
917 static int nv_init_ring(struct net_device *dev)
921 return nv_alloc_rx(dev);
924 static void nv_release_txskb(struct net_device *dev, unsigned int skbnr)
926 struct fe_priv *np = netdev_priv(dev);
927 struct sk_buff *skb = np->tx_skbuff[skbnr];
928 unsigned int j, entry, fragments;
930 dprintk(KERN_INFO "%s: nv_release_txskb for skbnr %d, skb %p\n",
931 dev->name, skbnr, np->tx_skbuff[skbnr]);
934 if ((fragments = skb_shinfo(skb)->nr_frags) != 0) {
935 for (j = fragments; j >= 1; j--) {
936 skb_frag_t *frag = &skb_shinfo(skb)->frags[j-1];
937 pci_unmap_page(np->pci_dev, np->tx_dma[entry],
940 entry = (entry - 1) % TX_RING;
943 pci_unmap_single(np->pci_dev, np->tx_dma[entry],
944 skb->len - skb->data_len,
946 dev_kfree_skb_irq(skb);
947 np->tx_skbuff[skbnr] = NULL;
950 static void nv_drain_tx(struct net_device *dev)
952 struct fe_priv *np = netdev_priv(dev);
955 for (i = 0; i < TX_RING; i++) {
956 if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2)
957 np->tx_ring.orig[i].FlagLen = 0;
959 np->tx_ring.ex[i].FlagLen = 0;
960 if (np->tx_skbuff[i]) {
961 nv_release_txskb(dev, i);
962 np->stats.tx_dropped++;
967 static void nv_drain_rx(struct net_device *dev)
969 struct fe_priv *np = netdev_priv(dev);
971 for (i = 0; i < RX_RING; i++) {
972 if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2)
973 np->rx_ring.orig[i].FlagLen = 0;
975 np->rx_ring.ex[i].FlagLen = 0;
977 if (np->rx_skbuff[i]) {
978 pci_unmap_single(np->pci_dev, np->rx_dma[i],
979 np->rx_skbuff[i]->len,
981 dev_kfree_skb(np->rx_skbuff[i]);
982 np->rx_skbuff[i] = NULL;
987 static void drain_ring(struct net_device *dev)
994 * nv_start_xmit: dev->hard_start_xmit function
995 * Called with dev->xmit_lock held.
997 static int nv_start_xmit(struct sk_buff *skb, struct net_device *dev)
999 struct fe_priv *np = netdev_priv(dev);
1000 u32 tx_flags_extra = (np->desc_ver == DESC_VER_1 ? NV_TX_LASTPACKET : NV_TX2_LASTPACKET);
1001 unsigned int fragments = skb_shinfo(skb)->nr_frags;
1002 unsigned int nr = (np->next_tx + fragments) % TX_RING;
1005 spin_lock_irq(&np->lock);
1007 if ((np->next_tx - np->nic_tx + fragments) > TX_LIMIT_STOP) {
1008 spin_unlock_irq(&np->lock);
1009 netif_stop_queue(dev);
1010 return NETDEV_TX_BUSY;
1013 np->tx_skbuff[nr] = skb;
1016 dprintk(KERN_DEBUG "%s: nv_start_xmit: buffer contains %d fragments\n", dev->name, fragments);
1017 /* setup descriptors in reverse order */
1018 for (i = fragments; i >= 1; i--) {
1019 skb_frag_t *frag = &skb_shinfo(skb)->frags[i-1];
1020 np->tx_dma[nr] = pci_map_page(np->pci_dev, frag->page, frag->page_offset, frag->size,
1023 if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) {
1024 np->tx_ring.orig[nr].PacketBuffer = cpu_to_le32(np->tx_dma[nr]);
1025 np->tx_ring.orig[nr].FlagLen = cpu_to_le32( (frag->size-1) | np->tx_flags | tx_flags_extra);
1027 np->tx_ring.ex[nr].PacketBufferHigh = cpu_to_le64(np->tx_dma[nr]) >> 32;
1028 np->tx_ring.ex[nr].PacketBufferLow = cpu_to_le64(np->tx_dma[nr]) & 0x0FFFFFFFF;
1029 np->tx_ring.ex[nr].FlagLen = cpu_to_le32( (frag->size-1) | np->tx_flags | tx_flags_extra);
1032 nr = (nr - 1) % TX_RING;
1034 if (np->desc_ver == DESC_VER_1)
1035 tx_flags_extra &= ~NV_TX_LASTPACKET;
1037 tx_flags_extra &= ~NV_TX2_LASTPACKET;
1042 if (skb_shinfo(skb)->tso_size)
1043 tx_flags_extra |= NV_TX2_TSO | (skb_shinfo(skb)->tso_size << NV_TX2_TSO_SHIFT);
1046 tx_flags_extra |= (skb->ip_summed == CHECKSUM_HW ? (NV_TX2_CHECKSUM_L3|NV_TX2_CHECKSUM_L4) : 0);
1048 np->tx_dma[nr] = pci_map_single(np->pci_dev, skb->data, skb->len-skb->data_len,
1051 if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) {
1052 np->tx_ring.orig[nr].PacketBuffer = cpu_to_le32(np->tx_dma[nr]);
1053 np->tx_ring.orig[nr].FlagLen = cpu_to_le32( (skb->len-skb->data_len-1) | np->tx_flags | tx_flags_extra);
1055 np->tx_ring.ex[nr].PacketBufferHigh = cpu_to_le64(np->tx_dma[nr]) >> 32;
1056 np->tx_ring.ex[nr].PacketBufferLow = cpu_to_le64(np->tx_dma[nr]) & 0x0FFFFFFFF;
1057 np->tx_ring.ex[nr].FlagLen = cpu_to_le32( (skb->len-skb->data_len-1) | np->tx_flags | tx_flags_extra);
1060 dprintk(KERN_DEBUG "%s: nv_start_xmit: packet packet %d queued for transmission. tx_flags_extra: %x\n",
1061 dev->name, np->next_tx, tx_flags_extra);
1064 for (j=0; j<64; j++) {
1066 dprintk("\n%03x:", j);
1067 dprintk(" %02x", ((unsigned char*)skb->data)[j]);
1072 np->next_tx += 1 + fragments;
1074 dev->trans_start = jiffies;
1075 spin_unlock_irq(&np->lock);
1076 writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
1077 pci_push(get_hwbase(dev));
1078 return NETDEV_TX_OK;
1082 * nv_tx_done: check for completed packets, release the skbs.
1084 * Caller must own np->lock.
1086 static void nv_tx_done(struct net_device *dev)
1088 struct fe_priv *np = netdev_priv(dev);
1091 struct sk_buff *skb;
1093 while (np->nic_tx != np->next_tx) {
1094 i = np->nic_tx % TX_RING;
1096 if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2)
1097 Flags = le32_to_cpu(np->tx_ring.orig[i].FlagLen);
1099 Flags = le32_to_cpu(np->tx_ring.ex[i].FlagLen);
1101 dprintk(KERN_DEBUG "%s: nv_tx_done: looking at packet %d, Flags 0x%x.\n",
1102 dev->name, np->nic_tx, Flags);
1103 if (Flags & NV_TX_VALID)
1105 if (np->desc_ver == DESC_VER_1) {
1106 if (Flags & NV_TX_LASTPACKET) {
1107 skb = np->tx_skbuff[i];
1108 if (Flags & (NV_TX_RETRYERROR|NV_TX_CARRIERLOST|NV_TX_LATECOLLISION|
1109 NV_TX_UNDERFLOW|NV_TX_ERROR)) {
1110 if (Flags & NV_TX_UNDERFLOW)
1111 np->stats.tx_fifo_errors++;
1112 if (Flags & NV_TX_CARRIERLOST)
1113 np->stats.tx_carrier_errors++;
1114 np->stats.tx_errors++;
1116 np->stats.tx_packets++;
1117 np->stats.tx_bytes += skb->len;
1119 nv_release_txskb(dev, i);
1122 if (Flags & NV_TX2_LASTPACKET) {
1123 skb = np->tx_skbuff[i];
1124 if (Flags & (NV_TX2_RETRYERROR|NV_TX2_CARRIERLOST|NV_TX2_LATECOLLISION|
1125 NV_TX2_UNDERFLOW|NV_TX2_ERROR)) {
1126 if (Flags & NV_TX2_UNDERFLOW)
1127 np->stats.tx_fifo_errors++;
1128 if (Flags & NV_TX2_CARRIERLOST)
1129 np->stats.tx_carrier_errors++;
1130 np->stats.tx_errors++;
1132 np->stats.tx_packets++;
1133 np->stats.tx_bytes += skb->len;
1135 nv_release_txskb(dev, i);
1140 if (np->next_tx - np->nic_tx < TX_LIMIT_START)
1141 netif_wake_queue(dev);
1145 * nv_tx_timeout: dev->tx_timeout function
1146 * Called with dev->xmit_lock held.
1148 static void nv_tx_timeout(struct net_device *dev)
1150 struct fe_priv *np = netdev_priv(dev);
1151 u8 __iomem *base = get_hwbase(dev);
1153 printk(KERN_INFO "%s: Got tx_timeout. irq: %08x\n", dev->name,
1154 readl(base + NvRegIrqStatus) & NVREG_IRQSTAT_MASK);
1159 printk(KERN_INFO "%s: Ring at %lx: next %d nic %d\n",
1160 dev->name, (unsigned long)np->ring_addr,
1161 np->next_tx, np->nic_tx);
1162 printk(KERN_INFO "%s: Dumping tx registers\n", dev->name);
1163 for (i=0;i<0x400;i+= 32) {
1164 printk(KERN_INFO "%3x: %08x %08x %08x %08x %08x %08x %08x %08x\n",
1166 readl(base + i + 0), readl(base + i + 4),
1167 readl(base + i + 8), readl(base + i + 12),
1168 readl(base + i + 16), readl(base + i + 20),
1169 readl(base + i + 24), readl(base + i + 28));
1171 printk(KERN_INFO "%s: Dumping tx ring\n", dev->name);
1172 for (i=0;i<TX_RING;i+= 4) {
1173 if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) {
1174 printk(KERN_INFO "%03x: %08x %08x // %08x %08x // %08x %08x // %08x %08x\n",
1176 le32_to_cpu(np->tx_ring.orig[i].PacketBuffer),
1177 le32_to_cpu(np->tx_ring.orig[i].FlagLen),
1178 le32_to_cpu(np->tx_ring.orig[i+1].PacketBuffer),
1179 le32_to_cpu(np->tx_ring.orig[i+1].FlagLen),
1180 le32_to_cpu(np->tx_ring.orig[i+2].PacketBuffer),
1181 le32_to_cpu(np->tx_ring.orig[i+2].FlagLen),
1182 le32_to_cpu(np->tx_ring.orig[i+3].PacketBuffer),
1183 le32_to_cpu(np->tx_ring.orig[i+3].FlagLen));
1185 printk(KERN_INFO "%03x: %08x %08x %08x // %08x %08x %08x // %08x %08x %08x // %08x %08x %08x\n",
1187 le32_to_cpu(np->tx_ring.ex[i].PacketBufferHigh),
1188 le32_to_cpu(np->tx_ring.ex[i].PacketBufferLow),
1189 le32_to_cpu(np->tx_ring.ex[i].FlagLen),
1190 le32_to_cpu(np->tx_ring.ex[i+1].PacketBufferHigh),
1191 le32_to_cpu(np->tx_ring.ex[i+1].PacketBufferLow),
1192 le32_to_cpu(np->tx_ring.ex[i+1].FlagLen),
1193 le32_to_cpu(np->tx_ring.ex[i+2].PacketBufferHigh),
1194 le32_to_cpu(np->tx_ring.ex[i+2].PacketBufferLow),
1195 le32_to_cpu(np->tx_ring.ex[i+2].FlagLen),
1196 le32_to_cpu(np->tx_ring.ex[i+3].PacketBufferHigh),
1197 le32_to_cpu(np->tx_ring.ex[i+3].PacketBufferLow),
1198 le32_to_cpu(np->tx_ring.ex[i+3].FlagLen));
1203 spin_lock_irq(&np->lock);
1205 /* 1) stop tx engine */
1208 /* 2) check that the packets were not sent already: */
1211 /* 3) if there are dead entries: clear everything */
1212 if (np->next_tx != np->nic_tx) {
1213 printk(KERN_DEBUG "%s: tx_timeout: dead entries!\n", dev->name);
1215 np->next_tx = np->nic_tx = 0;
1216 if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2)
1217 writel((u32) (np->ring_addr + RX_RING*sizeof(struct ring_desc)), base + NvRegTxRingPhysAddr);
1219 writel((u32) (np->ring_addr + RX_RING*sizeof(struct ring_desc_ex)), base + NvRegTxRingPhysAddr);
1220 netif_wake_queue(dev);
1223 /* 4) restart tx engine */
1225 spin_unlock_irq(&np->lock);
1229 * Called when the nic notices a mismatch between the actual data len on the
1230 * wire and the len indicated in the 802 header
1232 static int nv_getlen(struct net_device *dev, void *packet, int datalen)
1234 int hdrlen; /* length of the 802 header */
1235 int protolen; /* length as stored in the proto field */
1237 /* 1) calculate len according to header */
1238 if ( ((struct vlan_ethhdr *)packet)->h_vlan_proto == __constant_htons(ETH_P_8021Q)) {
1239 protolen = ntohs( ((struct vlan_ethhdr *)packet)->h_vlan_encapsulated_proto );
1242 protolen = ntohs( ((struct ethhdr *)packet)->h_proto);
1245 dprintk(KERN_DEBUG "%s: nv_getlen: datalen %d, protolen %d, hdrlen %d\n",
1246 dev->name, datalen, protolen, hdrlen);
1247 if (protolen > ETH_DATA_LEN)
1248 return datalen; /* Value in proto field not a len, no checks possible */
1251 /* consistency checks: */
1252 if (datalen > ETH_ZLEN) {
1253 if (datalen >= protolen) {
1254 /* more data on wire than in 802 header, trim of
1257 dprintk(KERN_DEBUG "%s: nv_getlen: accepting %d bytes.\n",
1258 dev->name, protolen);
1261 /* less data on wire than mentioned in header.
1262 * Discard the packet.
1264 dprintk(KERN_DEBUG "%s: nv_getlen: discarding long packet.\n",
1269 /* short packet. Accept only if 802 values are also short */
1270 if (protolen > ETH_ZLEN) {
1271 dprintk(KERN_DEBUG "%s: nv_getlen: discarding short packet.\n",
1275 dprintk(KERN_DEBUG "%s: nv_getlen: accepting %d bytes.\n",
1276 dev->name, datalen);
1281 static void nv_rx_process(struct net_device *dev)
1283 struct fe_priv *np = netdev_priv(dev);
1287 struct sk_buff *skb;
1290 if (np->cur_rx - np->refill_rx >= RX_RING)
1291 break; /* we scanned the whole ring - do not continue */
1293 i = np->cur_rx % RX_RING;
1294 if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) {
1295 Flags = le32_to_cpu(np->rx_ring.orig[i].FlagLen);
1296 len = nv_descr_getlength(&np->rx_ring.orig[i], np->desc_ver);
1298 Flags = le32_to_cpu(np->rx_ring.ex[i].FlagLen);
1299 len = nv_descr_getlength_ex(&np->rx_ring.ex[i], np->desc_ver);
1302 dprintk(KERN_DEBUG "%s: nv_rx_process: looking at packet %d, Flags 0x%x.\n",
1303 dev->name, np->cur_rx, Flags);
1305 if (Flags & NV_RX_AVAIL)
1306 break; /* still owned by hardware, */
1309 * the packet is for us - immediately tear down the pci mapping.
1310 * TODO: check if a prefetch of the first cacheline improves
1313 pci_unmap_single(np->pci_dev, np->rx_dma[i],
1314 np->rx_skbuff[i]->len,
1315 PCI_DMA_FROMDEVICE);
1319 dprintk(KERN_DEBUG "Dumping packet (flags 0x%x).",Flags);
1320 for (j=0; j<64; j++) {
1322 dprintk("\n%03x:", j);
1323 dprintk(" %02x", ((unsigned char*)np->rx_skbuff[i]->data)[j]);
1327 /* look at what we actually got: */
1328 if (np->desc_ver == DESC_VER_1) {
1329 if (!(Flags & NV_RX_DESCRIPTORVALID))
1332 if (Flags & NV_RX_MISSEDFRAME) {
1333 np->stats.rx_missed_errors++;
1334 np->stats.rx_errors++;
1337 if (Flags & (NV_RX_ERROR1|NV_RX_ERROR2|NV_RX_ERROR3)) {
1338 np->stats.rx_errors++;
1341 if (Flags & NV_RX_CRCERR) {
1342 np->stats.rx_crc_errors++;
1343 np->stats.rx_errors++;
1346 if (Flags & NV_RX_OVERFLOW) {
1347 np->stats.rx_over_errors++;
1348 np->stats.rx_errors++;
1351 if (Flags & NV_RX_ERROR4) {
1352 len = nv_getlen(dev, np->rx_skbuff[i]->data, len);
1354 np->stats.rx_errors++;
1358 /* framing errors are soft errors. */
1359 if (Flags & NV_RX_FRAMINGERR) {
1360 if (Flags & NV_RX_SUBSTRACT1) {
1365 if (!(Flags & NV_RX2_DESCRIPTORVALID))
1368 if (Flags & (NV_RX2_ERROR1|NV_RX2_ERROR2|NV_RX2_ERROR3)) {
1369 np->stats.rx_errors++;
1372 if (Flags & NV_RX2_CRCERR) {
1373 np->stats.rx_crc_errors++;
1374 np->stats.rx_errors++;
1377 if (Flags & NV_RX2_OVERFLOW) {
1378 np->stats.rx_over_errors++;
1379 np->stats.rx_errors++;
1382 if (Flags & NV_RX2_ERROR4) {
1383 len = nv_getlen(dev, np->rx_skbuff[i]->data, len);
1385 np->stats.rx_errors++;
1389 /* framing errors are soft errors */
1390 if (Flags & NV_RX2_FRAMINGERR) {
1391 if (Flags & NV_RX2_SUBSTRACT1) {
1395 Flags &= NV_RX2_CHECKSUMMASK;
1396 if (Flags == NV_RX2_CHECKSUMOK1 ||
1397 Flags == NV_RX2_CHECKSUMOK2 ||
1398 Flags == NV_RX2_CHECKSUMOK3) {
1399 dprintk(KERN_DEBUG "%s: hw checksum hit!.\n", dev->name);
1400 np->rx_skbuff[i]->ip_summed = CHECKSUM_UNNECESSARY;
1402 dprintk(KERN_DEBUG "%s: hwchecksum miss!.\n", dev->name);
1405 /* got a valid packet - forward it to the network core */
1406 skb = np->rx_skbuff[i];
1407 np->rx_skbuff[i] = NULL;
1410 skb->protocol = eth_type_trans(skb, dev);
1411 dprintk(KERN_DEBUG "%s: nv_rx_process: packet %d with %d bytes, proto %d accepted.\n",
1412 dev->name, np->cur_rx, len, skb->protocol);
1414 dev->last_rx = jiffies;
1415 np->stats.rx_packets++;
1416 np->stats.rx_bytes += len;
1422 static void set_bufsize(struct net_device *dev)
1424 struct fe_priv *np = netdev_priv(dev);
1426 if (dev->mtu <= ETH_DATA_LEN)
1427 np->rx_buf_sz = ETH_DATA_LEN + NV_RX_HEADERS;
1429 np->rx_buf_sz = dev->mtu + NV_RX_HEADERS;
1433 * nv_change_mtu: dev->change_mtu function
1434 * Called with dev_base_lock held for read.
1436 static int nv_change_mtu(struct net_device *dev, int new_mtu)
1438 struct fe_priv *np = netdev_priv(dev);
1441 if (new_mtu < 64 || new_mtu > np->pkt_limit)
1447 /* return early if the buffer sizes will not change */
1448 if (old_mtu <= ETH_DATA_LEN && new_mtu <= ETH_DATA_LEN)
1450 if (old_mtu == new_mtu)
1453 /* synchronized against open : rtnl_lock() held by caller */
1454 if (netif_running(dev)) {
1455 u8 __iomem *base = get_hwbase(dev);
1457 * It seems that the nic preloads valid ring entries into an
1458 * internal buffer. The procedure for flushing everything is
1459 * guessed, there is probably a simpler approach.
1460 * Changing the MTU is a rare event, it shouldn't matter.
1462 disable_irq(dev->irq);
1463 spin_lock_bh(&dev->xmit_lock);
1464 spin_lock(&np->lock);
1469 /* drain rx queue */
1472 /* reinit driver view of the rx queue */
1475 /* alloc new rx buffers */
1477 if (nv_alloc_rx(dev)) {
1478 if (!np->in_shutdown)
1479 mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
1481 /* reinit nic view of the rx queue */
1482 writel(np->rx_buf_sz, base + NvRegOffloadConfig);
1483 writel((u32) np->ring_addr, base + NvRegRxRingPhysAddr);
1484 if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2)
1485 writel((u32) (np->ring_addr + RX_RING*sizeof(struct ring_desc)), base + NvRegTxRingPhysAddr);
1487 writel((u32) (np->ring_addr + RX_RING*sizeof(struct ring_desc_ex)), base + NvRegTxRingPhysAddr);
1488 writel( ((RX_RING-1) << NVREG_RINGSZ_RXSHIFT) + ((TX_RING-1) << NVREG_RINGSZ_TXSHIFT),
1489 base + NvRegRingSizes);
1491 writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
1494 /* restart rx engine */
1497 spin_unlock(&np->lock);
1498 spin_unlock_bh(&dev->xmit_lock);
1499 enable_irq(dev->irq);
1504 static void nv_copy_mac_to_hw(struct net_device *dev)
1506 u8 __iomem *base = get_hwbase(dev);
1509 mac[0] = (dev->dev_addr[0] << 0) + (dev->dev_addr[1] << 8) +
1510 (dev->dev_addr[2] << 16) + (dev->dev_addr[3] << 24);
1511 mac[1] = (dev->dev_addr[4] << 0) + (dev->dev_addr[5] << 8);
1513 writel(mac[0], base + NvRegMacAddrA);
1514 writel(mac[1], base + NvRegMacAddrB);
1518 * nv_set_mac_address: dev->set_mac_address function
1519 * Called with rtnl_lock() held.
1521 static int nv_set_mac_address(struct net_device *dev, void *addr)
1523 struct fe_priv *np = netdev_priv(dev);
1524 struct sockaddr *macaddr = (struct sockaddr*)addr;
1526 if(!is_valid_ether_addr(macaddr->sa_data))
1527 return -EADDRNOTAVAIL;
1529 /* synchronized against open : rtnl_lock() held by caller */
1530 memcpy(dev->dev_addr, macaddr->sa_data, ETH_ALEN);
1532 if (netif_running(dev)) {
1533 spin_lock_bh(&dev->xmit_lock);
1534 spin_lock_irq(&np->lock);
1536 /* stop rx engine */
1539 /* set mac address */
1540 nv_copy_mac_to_hw(dev);
1542 /* restart rx engine */
1544 spin_unlock_irq(&np->lock);
1545 spin_unlock_bh(&dev->xmit_lock);
1547 nv_copy_mac_to_hw(dev);
1553 * nv_set_multicast: dev->set_multicast function
1554 * Called with dev->xmit_lock held.
1556 static void nv_set_multicast(struct net_device *dev)
1558 struct fe_priv *np = netdev_priv(dev);
1559 u8 __iomem *base = get_hwbase(dev);
1564 memset(addr, 0, sizeof(addr));
1565 memset(mask, 0, sizeof(mask));
1567 if (dev->flags & IFF_PROMISC) {
1568 printk(KERN_NOTICE "%s: Promiscuous mode enabled.\n", dev->name);
1569 pff = NVREG_PFF_PROMISC;
1571 pff = NVREG_PFF_MYADDR;
1573 if (dev->flags & IFF_ALLMULTI || dev->mc_list) {
1577 alwaysOn[0] = alwaysOn[1] = alwaysOff[0] = alwaysOff[1] = 0xffffffff;
1578 if (dev->flags & IFF_ALLMULTI) {
1579 alwaysOn[0] = alwaysOn[1] = alwaysOff[0] = alwaysOff[1] = 0;
1581 struct dev_mc_list *walk;
1583 walk = dev->mc_list;
1584 while (walk != NULL) {
1586 a = le32_to_cpu(*(u32 *) walk->dmi_addr);
1587 b = le16_to_cpu(*(u16 *) (&walk->dmi_addr[4]));
1595 addr[0] = alwaysOn[0];
1596 addr[1] = alwaysOn[1];
1597 mask[0] = alwaysOn[0] | alwaysOff[0];
1598 mask[1] = alwaysOn[1] | alwaysOff[1];
1601 addr[0] |= NVREG_MCASTADDRA_FORCE;
1602 pff |= NVREG_PFF_ALWAYS;
1603 spin_lock_irq(&np->lock);
1605 writel(addr[0], base + NvRegMulticastAddrA);
1606 writel(addr[1], base + NvRegMulticastAddrB);
1607 writel(mask[0], base + NvRegMulticastMaskA);
1608 writel(mask[1], base + NvRegMulticastMaskB);
1609 writel(pff, base + NvRegPacketFilterFlags);
1610 dprintk(KERN_INFO "%s: reconfiguration for multicast lists.\n",
1613 spin_unlock_irq(&np->lock);
1617 * nv_update_linkspeed: Setup the MAC according to the link partner
1618 * @dev: Network device to be configured
1620 * The function queries the PHY and checks if there is a link partner.
1621 * If yes, then it sets up the MAC accordingly. Otherwise, the MAC is
1622 * set to 10 MBit HD.
1624 * The function returns 0 if there is no link partner and 1 if there is
1625 * a good link partner.
1627 static int nv_update_linkspeed(struct net_device *dev)
1629 struct fe_priv *np = netdev_priv(dev);
1630 u8 __iomem *base = get_hwbase(dev);
1632 int newls = np->linkspeed;
1633 int newdup = np->duplex;
1636 u32 control_1000, status_1000, phyreg;
1638 /* BMSR_LSTATUS is latched, read it twice:
1639 * we want the current value.
1641 mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ);
1642 mii_status = mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ);
1644 if (!(mii_status & BMSR_LSTATUS)) {
1645 dprintk(KERN_DEBUG "%s: no link detected by phy - falling back to 10HD.\n",
1647 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
1653 if (np->autoneg == 0) {
1654 dprintk(KERN_DEBUG "%s: nv_update_linkspeed: autoneg off, PHY set to 0x%04x.\n",
1655 dev->name, np->fixed_mode);
1656 if (np->fixed_mode & LPA_100FULL) {
1657 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_100;
1659 } else if (np->fixed_mode & LPA_100HALF) {
1660 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_100;
1662 } else if (np->fixed_mode & LPA_10FULL) {
1663 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
1666 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
1672 /* check auto negotiation is complete */
1673 if (!(mii_status & BMSR_ANEGCOMPLETE)) {
1674 /* still in autonegotiation - configure nic for 10 MBit HD and wait. */
1675 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
1678 dprintk(KERN_DEBUG "%s: autoneg not completed - falling back to 10HD.\n", dev->name);
1683 if (np->gigabit == PHY_GIGABIT) {
1684 control_1000 = mii_rw(dev, np->phyaddr, MII_1000BT_CR, MII_READ);
1685 status_1000 = mii_rw(dev, np->phyaddr, MII_1000BT_SR, MII_READ);
1687 if ((control_1000 & ADVERTISE_1000FULL) &&
1688 (status_1000 & LPA_1000FULL)) {
1689 dprintk(KERN_DEBUG "%s: nv_update_linkspeed: GBit ethernet detected.\n",
1691 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_1000;
1697 adv = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ);
1698 lpa = mii_rw(dev, np->phyaddr, MII_LPA, MII_READ);
1699 dprintk(KERN_DEBUG "%s: nv_update_linkspeed: PHY advertises 0x%04x, lpa 0x%04x.\n",
1700 dev->name, adv, lpa);
1702 /* FIXME: handle parallel detection properly */
1704 if (lpa & LPA_100FULL) {
1705 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_100;
1707 } else if (lpa & LPA_100HALF) {
1708 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_100;
1710 } else if (lpa & LPA_10FULL) {
1711 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
1713 } else if (lpa & LPA_10HALF) {
1714 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
1717 dprintk(KERN_DEBUG "%s: bad ability %04x - falling back to 10HD.\n", dev->name, lpa);
1718 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
1723 if (np->duplex == newdup && np->linkspeed == newls)
1726 dprintk(KERN_INFO "%s: changing link setting from %d/%d to %d/%d.\n",
1727 dev->name, np->linkspeed, np->duplex, newls, newdup);
1729 np->duplex = newdup;
1730 np->linkspeed = newls;
1732 if (np->gigabit == PHY_GIGABIT) {
1733 phyreg = readl(base + NvRegRandomSeed);
1734 phyreg &= ~(0x3FF00);
1735 if ((np->linkspeed & 0xFFF) == NVREG_LINKSPEED_10)
1736 phyreg |= NVREG_RNDSEED_FORCE3;
1737 else if ((np->linkspeed & 0xFFF) == NVREG_LINKSPEED_100)
1738 phyreg |= NVREG_RNDSEED_FORCE2;
1739 else if ((np->linkspeed & 0xFFF) == NVREG_LINKSPEED_1000)
1740 phyreg |= NVREG_RNDSEED_FORCE;
1741 writel(phyreg, base + NvRegRandomSeed);
1744 phyreg = readl(base + NvRegPhyInterface);
1745 phyreg &= ~(PHY_HALF|PHY_100|PHY_1000);
1746 if (np->duplex == 0)
1748 if ((np->linkspeed & NVREG_LINKSPEED_MASK) == NVREG_LINKSPEED_100)
1750 else if ((np->linkspeed & NVREG_LINKSPEED_MASK) == NVREG_LINKSPEED_1000)
1752 writel(phyreg, base + NvRegPhyInterface);
1754 writel(NVREG_MISC1_FORCE | ( np->duplex ? 0 : NVREG_MISC1_HD),
1757 writel(np->linkspeed, base + NvRegLinkSpeed);
1763 static void nv_linkchange(struct net_device *dev)
1765 if (nv_update_linkspeed(dev)) {
1766 if (!netif_carrier_ok(dev)) {
1767 netif_carrier_on(dev);
1768 printk(KERN_INFO "%s: link up.\n", dev->name);
1772 if (netif_carrier_ok(dev)) {
1773 netif_carrier_off(dev);
1774 printk(KERN_INFO "%s: link down.\n", dev->name);
1780 static void nv_link_irq(struct net_device *dev)
1782 u8 __iomem *base = get_hwbase(dev);
1785 miistat = readl(base + NvRegMIIStatus);
1786 writel(NVREG_MIISTAT_MASK, base + NvRegMIIStatus);
1787 dprintk(KERN_INFO "%s: link change irq, status 0x%x.\n", dev->name, miistat);
1789 if (miistat & (NVREG_MIISTAT_LINKCHANGE))
1791 dprintk(KERN_DEBUG "%s: link change notification done.\n", dev->name);
1794 static irqreturn_t nv_nic_irq(int foo, void *data, struct pt_regs *regs)
1796 struct net_device *dev = (struct net_device *) data;
1797 struct fe_priv *np = netdev_priv(dev);
1798 u8 __iomem *base = get_hwbase(dev);
1802 dprintk(KERN_DEBUG "%s: nv_nic_irq\n", dev->name);
1805 events = readl(base + NvRegIrqStatus) & NVREG_IRQSTAT_MASK;
1806 writel(NVREG_IRQSTAT_MASK, base + NvRegIrqStatus);
1808 dprintk(KERN_DEBUG "%s: irq: %08x\n", dev->name, events);
1809 if (!(events & np->irqmask))
1812 if (events & (NVREG_IRQ_TX1|NVREG_IRQ_TX_OK|NVREG_IRQ_TX_ERROR|NVREG_IRQ_TX_ERR)) {
1813 spin_lock(&np->lock);
1815 spin_unlock(&np->lock);
1818 if (events & (NVREG_IRQ_RX_ERROR|NVREG_IRQ_RX|NVREG_IRQ_RX_NOBUF)) {
1820 if (nv_alloc_rx(dev)) {
1821 spin_lock(&np->lock);
1822 if (!np->in_shutdown)
1823 mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
1824 spin_unlock(&np->lock);
1828 if (events & NVREG_IRQ_LINK) {
1829 spin_lock(&np->lock);
1831 spin_unlock(&np->lock);
1833 if (np->need_linktimer && time_after(jiffies, np->link_timeout)) {
1834 spin_lock(&np->lock);
1836 spin_unlock(&np->lock);
1837 np->link_timeout = jiffies + LINK_TIMEOUT;
1839 if (events & (NVREG_IRQ_TX_ERR)) {
1840 dprintk(KERN_DEBUG "%s: received irq with events 0x%x. Probably TX fail.\n",
1843 if (events & (NVREG_IRQ_UNKNOWN)) {
1844 printk(KERN_DEBUG "%s: received irq with unknown events 0x%x. Please report\n",
1847 if (i > max_interrupt_work) {
1848 spin_lock(&np->lock);
1849 /* disable interrupts on the nic */
1850 writel(0, base + NvRegIrqMask);
1853 if (!np->in_shutdown)
1854 mod_timer(&np->nic_poll, jiffies + POLL_WAIT);
1855 printk(KERN_DEBUG "%s: too many iterations (%d) in nv_nic_irq.\n", dev->name, i);
1856 spin_unlock(&np->lock);
1861 dprintk(KERN_DEBUG "%s: nv_nic_irq completed\n", dev->name);
1863 return IRQ_RETVAL(i);
1866 static void nv_do_nic_poll(unsigned long data)
1868 struct net_device *dev = (struct net_device *) data;
1869 struct fe_priv *np = netdev_priv(dev);
1870 u8 __iomem *base = get_hwbase(dev);
1872 disable_irq(dev->irq);
1873 /* FIXME: Do we need synchronize_irq(dev->irq) here? */
1875 * reenable interrupts on the nic, we have to do this before calling
1876 * nv_nic_irq because that may decide to do otherwise
1878 writel(np->irqmask, base + NvRegIrqMask);
1880 nv_nic_irq((int) 0, (void *) data, (struct pt_regs *) NULL);
1881 enable_irq(dev->irq);
1884 #ifdef CONFIG_NET_POLL_CONTROLLER
1885 static void nv_poll_controller(struct net_device *dev)
1887 nv_do_nic_poll((unsigned long) dev);
1891 static void nv_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
1893 struct fe_priv *np = netdev_priv(dev);
1894 strcpy(info->driver, "forcedeth");
1895 strcpy(info->version, FORCEDETH_VERSION);
1896 strcpy(info->bus_info, pci_name(np->pci_dev));
1899 static void nv_get_wol(struct net_device *dev, struct ethtool_wolinfo *wolinfo)
1901 struct fe_priv *np = netdev_priv(dev);
1902 wolinfo->supported = WAKE_MAGIC;
1904 spin_lock_irq(&np->lock);
1906 wolinfo->wolopts = WAKE_MAGIC;
1907 spin_unlock_irq(&np->lock);
1910 static int nv_set_wol(struct net_device *dev, struct ethtool_wolinfo *wolinfo)
1912 struct fe_priv *np = netdev_priv(dev);
1913 u8 __iomem *base = get_hwbase(dev);
1915 spin_lock_irq(&np->lock);
1916 if (wolinfo->wolopts == 0) {
1917 writel(0, base + NvRegWakeUpFlags);
1920 if (wolinfo->wolopts & WAKE_MAGIC) {
1921 writel(NVREG_WAKEUPFLAGS_ENABLE, base + NvRegWakeUpFlags);
1924 spin_unlock_irq(&np->lock);
1928 static int nv_get_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
1930 struct fe_priv *np = netdev_priv(dev);
1933 spin_lock_irq(&np->lock);
1934 ecmd->port = PORT_MII;
1935 if (!netif_running(dev)) {
1936 /* We do not track link speed / duplex setting if the
1937 * interface is disabled. Force a link check */
1938 nv_update_linkspeed(dev);
1940 switch(np->linkspeed & (NVREG_LINKSPEED_MASK)) {
1941 case NVREG_LINKSPEED_10:
1942 ecmd->speed = SPEED_10;
1944 case NVREG_LINKSPEED_100:
1945 ecmd->speed = SPEED_100;
1947 case NVREG_LINKSPEED_1000:
1948 ecmd->speed = SPEED_1000;
1951 ecmd->duplex = DUPLEX_HALF;
1953 ecmd->duplex = DUPLEX_FULL;
1955 ecmd->autoneg = np->autoneg;
1957 ecmd->advertising = ADVERTISED_MII;
1959 ecmd->advertising |= ADVERTISED_Autoneg;
1960 adv = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ);
1962 adv = np->fixed_mode;
1964 if (adv & ADVERTISE_10HALF)
1965 ecmd->advertising |= ADVERTISED_10baseT_Half;
1966 if (adv & ADVERTISE_10FULL)
1967 ecmd->advertising |= ADVERTISED_10baseT_Full;
1968 if (adv & ADVERTISE_100HALF)
1969 ecmd->advertising |= ADVERTISED_100baseT_Half;
1970 if (adv & ADVERTISE_100FULL)
1971 ecmd->advertising |= ADVERTISED_100baseT_Full;
1972 if (np->autoneg && np->gigabit == PHY_GIGABIT) {
1973 adv = mii_rw(dev, np->phyaddr, MII_1000BT_CR, MII_READ);
1974 if (adv & ADVERTISE_1000FULL)
1975 ecmd->advertising |= ADVERTISED_1000baseT_Full;
1978 ecmd->supported = (SUPPORTED_Autoneg |
1979 SUPPORTED_10baseT_Half | SUPPORTED_10baseT_Full |
1980 SUPPORTED_100baseT_Half | SUPPORTED_100baseT_Full |
1982 if (np->gigabit == PHY_GIGABIT)
1983 ecmd->supported |= SUPPORTED_1000baseT_Full;
1985 ecmd->phy_address = np->phyaddr;
1986 ecmd->transceiver = XCVR_EXTERNAL;
1988 /* ignore maxtxpkt, maxrxpkt for now */
1989 spin_unlock_irq(&np->lock);
1993 static int nv_set_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
1995 struct fe_priv *np = netdev_priv(dev);
1997 if (ecmd->port != PORT_MII)
1999 if (ecmd->transceiver != XCVR_EXTERNAL)
2001 if (ecmd->phy_address != np->phyaddr) {
2002 /* TODO: support switching between multiple phys. Should be
2003 * trivial, but not enabled due to lack of test hardware. */
2006 if (ecmd->autoneg == AUTONEG_ENABLE) {
2009 mask = ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
2010 ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full;
2011 if (np->gigabit == PHY_GIGABIT)
2012 mask |= ADVERTISED_1000baseT_Full;
2014 if ((ecmd->advertising & mask) == 0)
2017 } else if (ecmd->autoneg == AUTONEG_DISABLE) {
2018 /* Note: autonegotiation disable, speed 1000 intentionally
2019 * forbidden - noone should need that. */
2021 if (ecmd->speed != SPEED_10 && ecmd->speed != SPEED_100)
2023 if (ecmd->duplex != DUPLEX_HALF && ecmd->duplex != DUPLEX_FULL)
2029 spin_lock_irq(&np->lock);
2030 if (ecmd->autoneg == AUTONEG_ENABLE) {
2035 /* advertise only what has been requested */
2036 adv = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ);
2037 adv &= ~(ADVERTISE_ALL | ADVERTISE_100BASE4);
2038 if (ecmd->advertising & ADVERTISED_10baseT_Half)
2039 adv |= ADVERTISE_10HALF;
2040 if (ecmd->advertising & ADVERTISED_10baseT_Full)
2041 adv |= ADVERTISE_10FULL;
2042 if (ecmd->advertising & ADVERTISED_100baseT_Half)
2043 adv |= ADVERTISE_100HALF;
2044 if (ecmd->advertising & ADVERTISED_100baseT_Full)
2045 adv |= ADVERTISE_100FULL;
2046 mii_rw(dev, np->phyaddr, MII_ADVERTISE, adv);
2048 if (np->gigabit == PHY_GIGABIT) {
2049 adv = mii_rw(dev, np->phyaddr, MII_1000BT_CR, MII_READ);
2050 adv &= ~ADVERTISE_1000FULL;
2051 if (ecmd->advertising & ADVERTISED_1000baseT_Full)
2052 adv |= ADVERTISE_1000FULL;
2053 mii_rw(dev, np->phyaddr, MII_1000BT_CR, adv);
2056 bmcr = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
2057 bmcr |= (BMCR_ANENABLE | BMCR_ANRESTART);
2058 mii_rw(dev, np->phyaddr, MII_BMCR, bmcr);
2065 adv = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ);
2066 adv &= ~(ADVERTISE_ALL | ADVERTISE_100BASE4);
2067 if (ecmd->speed == SPEED_10 && ecmd->duplex == DUPLEX_HALF)
2068 adv |= ADVERTISE_10HALF;
2069 if (ecmd->speed == SPEED_10 && ecmd->duplex == DUPLEX_FULL)
2070 adv |= ADVERTISE_10FULL;
2071 if (ecmd->speed == SPEED_100 && ecmd->duplex == DUPLEX_HALF)
2072 adv |= ADVERTISE_100HALF;
2073 if (ecmd->speed == SPEED_100 && ecmd->duplex == DUPLEX_FULL)
2074 adv |= ADVERTISE_100FULL;
2075 mii_rw(dev, np->phyaddr, MII_ADVERTISE, adv);
2076 np->fixed_mode = adv;
2078 if (np->gigabit == PHY_GIGABIT) {
2079 adv = mii_rw(dev, np->phyaddr, MII_1000BT_CR, MII_READ);
2080 adv &= ~ADVERTISE_1000FULL;
2081 mii_rw(dev, np->phyaddr, MII_1000BT_CR, adv);
2084 bmcr = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
2085 bmcr |= ~(BMCR_ANENABLE|BMCR_SPEED100|BMCR_FULLDPLX);
2086 if (adv & (ADVERTISE_10FULL|ADVERTISE_100FULL))
2087 bmcr |= BMCR_FULLDPLX;
2088 if (adv & (ADVERTISE_100HALF|ADVERTISE_100FULL))
2089 bmcr |= BMCR_SPEED100;
2090 mii_rw(dev, np->phyaddr, MII_BMCR, bmcr);
2092 if (netif_running(dev)) {
2093 /* Wait a bit and then reconfigure the nic. */
2098 spin_unlock_irq(&np->lock);
2103 #define FORCEDETH_REGS_VER 1
2104 #define FORCEDETH_REGS_SIZE 0x400 /* 256 32-bit registers */
2106 static int nv_get_regs_len(struct net_device *dev)
2108 return FORCEDETH_REGS_SIZE;
2111 static void nv_get_regs(struct net_device *dev, struct ethtool_regs *regs, void *buf)
2113 struct fe_priv *np = netdev_priv(dev);
2114 u8 __iomem *base = get_hwbase(dev);
2118 regs->version = FORCEDETH_REGS_VER;
2119 spin_lock_irq(&np->lock);
2120 for (i=0;i<FORCEDETH_REGS_SIZE/sizeof(u32);i++)
2121 rbuf[i] = readl(base + i*sizeof(u32));
2122 spin_unlock_irq(&np->lock);
2125 static int nv_nway_reset(struct net_device *dev)
2127 struct fe_priv *np = netdev_priv(dev);
2130 spin_lock_irq(&np->lock);
2134 bmcr = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
2135 bmcr |= (BMCR_ANENABLE | BMCR_ANRESTART);
2136 mii_rw(dev, np->phyaddr, MII_BMCR, bmcr);
2142 spin_unlock_irq(&np->lock);
2147 static struct ethtool_ops ops = {
2148 .get_drvinfo = nv_get_drvinfo,
2149 .get_link = ethtool_op_get_link,
2150 .get_wol = nv_get_wol,
2151 .set_wol = nv_set_wol,
2152 .get_settings = nv_get_settings,
2153 .set_settings = nv_set_settings,
2154 .get_regs_len = nv_get_regs_len,
2155 .get_regs = nv_get_regs,
2156 .nway_reset = nv_nway_reset,
2157 .get_perm_addr = ethtool_op_get_perm_addr,
2160 static int nv_open(struct net_device *dev)
2162 struct fe_priv *np = netdev_priv(dev);
2163 u8 __iomem *base = get_hwbase(dev);
2166 dprintk(KERN_DEBUG "nv_open: begin\n");
2168 /* 1) erase previous misconfiguration */
2169 /* 4.1-1: stop adapter: ignored, 4.3 seems to be overkill */
2170 writel(NVREG_MCASTADDRA_FORCE, base + NvRegMulticastAddrA);
2171 writel(0, base + NvRegMulticastAddrB);
2172 writel(0, base + NvRegMulticastMaskA);
2173 writel(0, base + NvRegMulticastMaskB);
2174 writel(0, base + NvRegPacketFilterFlags);
2176 writel(0, base + NvRegTransmitterControl);
2177 writel(0, base + NvRegReceiverControl);
2179 writel(0, base + NvRegAdapterControl);
2181 /* 2) initialize descriptor rings */
2183 oom = nv_init_ring(dev);
2185 writel(0, base + NvRegLinkSpeed);
2186 writel(0, base + NvRegUnknownTransmitterReg);
2188 writel(0, base + NvRegUnknownSetupReg6);
2190 np->in_shutdown = 0;
2192 /* 3) set mac address */
2193 nv_copy_mac_to_hw(dev);
2195 /* 4) give hw rings */
2196 writel((u32) np->ring_addr, base + NvRegRxRingPhysAddr);
2197 if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2)
2198 writel((u32) (np->ring_addr + RX_RING*sizeof(struct ring_desc)), base + NvRegTxRingPhysAddr);
2200 writel((u32) (np->ring_addr + RX_RING*sizeof(struct ring_desc_ex)), base + NvRegTxRingPhysAddr);
2201 writel( ((RX_RING-1) << NVREG_RINGSZ_RXSHIFT) + ((TX_RING-1) << NVREG_RINGSZ_TXSHIFT),
2202 base + NvRegRingSizes);
2204 /* 5) continue setup */
2205 writel(np->linkspeed, base + NvRegLinkSpeed);
2206 writel(NVREG_UNKSETUP3_VAL1, base + NvRegUnknownSetupReg3);
2207 writel(np->txrxctl_bits, base + NvRegTxRxControl);
2209 writel(NVREG_TXRXCTL_BIT1|np->txrxctl_bits, base + NvRegTxRxControl);
2210 reg_delay(dev, NvRegUnknownSetupReg5, NVREG_UNKSETUP5_BIT31, NVREG_UNKSETUP5_BIT31,
2211 NV_SETUP5_DELAY, NV_SETUP5_DELAYMAX,
2212 KERN_INFO "open: SetupReg5, Bit 31 remained off\n");
2214 writel(0, base + NvRegUnknownSetupReg4);
2215 writel(NVREG_IRQSTAT_MASK, base + NvRegIrqStatus);
2216 writel(NVREG_MIISTAT_MASK2, base + NvRegMIIStatus);
2218 /* 6) continue setup */
2219 writel(NVREG_MISC1_FORCE | NVREG_MISC1_HD, base + NvRegMisc1);
2220 writel(readl(base + NvRegTransmitterStatus), base + NvRegTransmitterStatus);
2221 writel(NVREG_PFF_ALWAYS, base + NvRegPacketFilterFlags);
2222 writel(np->rx_buf_sz, base + NvRegOffloadConfig);
2224 writel(readl(base + NvRegReceiverStatus), base + NvRegReceiverStatus);
2225 get_random_bytes(&i, sizeof(i));
2226 writel(NVREG_RNDSEED_FORCE | (i&NVREG_RNDSEED_MASK), base + NvRegRandomSeed);
2227 writel(NVREG_UNKSETUP1_VAL, base + NvRegUnknownSetupReg1);
2228 writel(NVREG_UNKSETUP2_VAL, base + NvRegUnknownSetupReg2);
2229 writel(NVREG_POLL_DEFAULT, base + NvRegPollingInterval);
2230 writel(NVREG_UNKSETUP6_VAL, base + NvRegUnknownSetupReg6);
2231 writel((np->phyaddr << NVREG_ADAPTCTL_PHYSHIFT)|NVREG_ADAPTCTL_PHYVALID|NVREG_ADAPTCTL_RUNNING,
2232 base + NvRegAdapterControl);
2233 writel(NVREG_MIISPEED_BIT8|NVREG_MIIDELAY, base + NvRegMIISpeed);
2234 writel(NVREG_UNKSETUP4_VAL, base + NvRegUnknownSetupReg4);
2235 writel(NVREG_WAKEUPFLAGS_VAL, base + NvRegWakeUpFlags);
2237 i = readl(base + NvRegPowerState);
2238 if ( (i & NVREG_POWERSTATE_POWEREDUP) == 0)
2239 writel(NVREG_POWERSTATE_POWEREDUP|i, base + NvRegPowerState);
2243 writel(readl(base + NvRegPowerState) | NVREG_POWERSTATE_VALID, base + NvRegPowerState);
2245 writel(0, base + NvRegIrqMask);
2247 writel(NVREG_MIISTAT_MASK2, base + NvRegMIIStatus);
2248 writel(NVREG_IRQSTAT_MASK, base + NvRegIrqStatus);
2251 ret = request_irq(dev->irq, &nv_nic_irq, SA_SHIRQ, dev->name, dev);
2255 /* ask for interrupts */
2256 writel(np->irqmask, base + NvRegIrqMask);
2258 spin_lock_irq(&np->lock);
2259 writel(NVREG_MCASTADDRA_FORCE, base + NvRegMulticastAddrA);
2260 writel(0, base + NvRegMulticastAddrB);
2261 writel(0, base + NvRegMulticastMaskA);
2262 writel(0, base + NvRegMulticastMaskB);
2263 writel(NVREG_PFF_ALWAYS|NVREG_PFF_MYADDR, base + NvRegPacketFilterFlags);
2264 /* One manual link speed update: Interrupts are enabled, future link
2265 * speed changes cause interrupts and are handled by nv_link_irq().
2269 miistat = readl(base + NvRegMIIStatus);
2270 writel(NVREG_MIISTAT_MASK, base + NvRegMIIStatus);
2271 dprintk(KERN_INFO "startup: got 0x%08x.\n", miistat);
2273 /* set linkspeed to invalid value, thus force nv_update_linkspeed
2276 ret = nv_update_linkspeed(dev);
2279 netif_start_queue(dev);
2281 netif_carrier_on(dev);
2283 printk("%s: no link during initialization.\n", dev->name);
2284 netif_carrier_off(dev);
2287 mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
2288 spin_unlock_irq(&np->lock);
2296 static int nv_close(struct net_device *dev)
2298 struct fe_priv *np = netdev_priv(dev);
2301 spin_lock_irq(&np->lock);
2302 np->in_shutdown = 1;
2303 spin_unlock_irq(&np->lock);
2304 synchronize_irq(dev->irq);
2306 del_timer_sync(&np->oom_kick);
2307 del_timer_sync(&np->nic_poll);
2309 netif_stop_queue(dev);
2310 spin_lock_irq(&np->lock);
2315 /* disable interrupts on the nic or we will lock up */
2316 base = get_hwbase(dev);
2317 writel(0, base + NvRegIrqMask);
2319 dprintk(KERN_INFO "%s: Irqmask is zero again\n", dev->name);
2321 spin_unlock_irq(&np->lock);
2323 free_irq(dev->irq, dev);
2330 /* special op: write back the misordered MAC address - otherwise
2331 * the next nv_probe would see a wrong address.
2333 writel(np->orig_mac[0], base + NvRegMacAddrA);
2334 writel(np->orig_mac[1], base + NvRegMacAddrB);
2336 /* FIXME: power down nic */
2341 static int __devinit nv_probe(struct pci_dev *pci_dev, const struct pci_device_id *id)
2343 struct net_device *dev;
2349 dev = alloc_etherdev(sizeof(struct fe_priv));
2354 np = netdev_priv(dev);
2355 np->pci_dev = pci_dev;
2356 spin_lock_init(&np->lock);
2357 SET_MODULE_OWNER(dev);
2358 SET_NETDEV_DEV(dev, &pci_dev->dev);
2360 init_timer(&np->oom_kick);
2361 np->oom_kick.data = (unsigned long) dev;
2362 np->oom_kick.function = &nv_do_rx_refill; /* timer handler */
2363 init_timer(&np->nic_poll);
2364 np->nic_poll.data = (unsigned long) dev;
2365 np->nic_poll.function = &nv_do_nic_poll; /* timer handler */
2367 err = pci_enable_device(pci_dev);
2369 printk(KERN_INFO "forcedeth: pci_enable_dev failed (%d) for device %s\n",
2370 err, pci_name(pci_dev));
2374 pci_set_master(pci_dev);
2376 err = pci_request_regions(pci_dev, DRV_NAME);
2382 for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) {
2383 dprintk(KERN_DEBUG "%s: resource %d start %p len %ld flags 0x%08lx.\n",
2384 pci_name(pci_dev), i, (void*)pci_resource_start(pci_dev, i),
2385 pci_resource_len(pci_dev, i),
2386 pci_resource_flags(pci_dev, i));
2387 if (pci_resource_flags(pci_dev, i) & IORESOURCE_MEM &&
2388 pci_resource_len(pci_dev, i) >= NV_PCI_REGSZ) {
2389 addr = pci_resource_start(pci_dev, i);
2393 if (i == DEVICE_COUNT_RESOURCE) {
2394 printk(KERN_INFO "forcedeth: Couldn't find register window for device %s.\n",
2399 /* handle different descriptor versions */
2400 if (id->driver_data & DEV_HAS_HIGH_DMA) {
2401 /* packet format 3: supports 40-bit addressing */
2402 np->desc_ver = DESC_VER_3;
2403 if (pci_set_dma_mask(pci_dev, 0x0000007fffffffffULL)) {
2404 printk(KERN_INFO "forcedeth: 64-bit DMA failed, using 32-bit addressing for device %s.\n",
2407 dev->features |= NETIF_F_HIGHDMA;
2409 np->txrxctl_bits = NVREG_TXRXCTL_DESC_3;
2410 } else if (id->driver_data & DEV_HAS_LARGEDESC) {
2411 /* packet format 2: supports jumbo frames */
2412 np->desc_ver = DESC_VER_2;
2413 np->txrxctl_bits = NVREG_TXRXCTL_DESC_2;
2415 /* original packet format */
2416 np->desc_ver = DESC_VER_1;
2417 np->txrxctl_bits = NVREG_TXRXCTL_DESC_1;
2420 np->pkt_limit = NV_PKTLIMIT_1;
2421 if (id->driver_data & DEV_HAS_LARGEDESC)
2422 np->pkt_limit = NV_PKTLIMIT_2;
2424 if (id->driver_data & DEV_HAS_CHECKSUM) {
2425 np->txrxctl_bits |= NVREG_TXRXCTL_RXCHECK;
2426 dev->features |= NETIF_F_HW_CSUM | NETIF_F_SG;
2428 dev->features |= NETIF_F_TSO;
2433 np->base = ioremap(addr, NV_PCI_REGSZ);
2436 dev->base_addr = (unsigned long)np->base;
2438 dev->irq = pci_dev->irq;
2440 if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) {
2441 np->rx_ring.orig = pci_alloc_consistent(pci_dev,
2442 sizeof(struct ring_desc) * (RX_RING + TX_RING),
2444 if (!np->rx_ring.orig)
2446 np->tx_ring.orig = &np->rx_ring.orig[RX_RING];
2448 np->rx_ring.ex = pci_alloc_consistent(pci_dev,
2449 sizeof(struct ring_desc_ex) * (RX_RING + TX_RING),
2451 if (!np->rx_ring.ex)
2453 np->tx_ring.ex = &np->rx_ring.ex[RX_RING];
2456 dev->open = nv_open;
2457 dev->stop = nv_close;
2458 dev->hard_start_xmit = nv_start_xmit;
2459 dev->get_stats = nv_get_stats;
2460 dev->change_mtu = nv_change_mtu;
2461 dev->set_mac_address = nv_set_mac_address;
2462 dev->set_multicast_list = nv_set_multicast;
2463 #ifdef CONFIG_NET_POLL_CONTROLLER
2464 dev->poll_controller = nv_poll_controller;
2466 SET_ETHTOOL_OPS(dev, &ops);
2467 dev->tx_timeout = nv_tx_timeout;
2468 dev->watchdog_timeo = NV_WATCHDOG_TIMEO;
2470 pci_set_drvdata(pci_dev, dev);
2472 /* read the mac address */
2473 base = get_hwbase(dev);
2474 np->orig_mac[0] = readl(base + NvRegMacAddrA);
2475 np->orig_mac[1] = readl(base + NvRegMacAddrB);
2477 dev->dev_addr[0] = (np->orig_mac[1] >> 8) & 0xff;
2478 dev->dev_addr[1] = (np->orig_mac[1] >> 0) & 0xff;
2479 dev->dev_addr[2] = (np->orig_mac[0] >> 24) & 0xff;
2480 dev->dev_addr[3] = (np->orig_mac[0] >> 16) & 0xff;
2481 dev->dev_addr[4] = (np->orig_mac[0] >> 8) & 0xff;
2482 dev->dev_addr[5] = (np->orig_mac[0] >> 0) & 0xff;
2483 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
2485 if (!is_valid_ether_addr(dev->perm_addr)) {
2487 * Bad mac address. At least one bios sets the mac address
2488 * to 01:23:45:67:89:ab
2490 printk(KERN_ERR "%s: Invalid Mac address detected: %02x:%02x:%02x:%02x:%02x:%02x\n",
2492 dev->dev_addr[0], dev->dev_addr[1], dev->dev_addr[2],
2493 dev->dev_addr[3], dev->dev_addr[4], dev->dev_addr[5]);
2494 printk(KERN_ERR "Please complain to your hardware vendor. Switching to a random MAC.\n");
2495 dev->dev_addr[0] = 0x00;
2496 dev->dev_addr[1] = 0x00;
2497 dev->dev_addr[2] = 0x6c;
2498 get_random_bytes(&dev->dev_addr[3], 3);
2501 dprintk(KERN_DEBUG "%s: MAC Address %02x:%02x:%02x:%02x:%02x:%02x\n", pci_name(pci_dev),
2502 dev->dev_addr[0], dev->dev_addr[1], dev->dev_addr[2],
2503 dev->dev_addr[3], dev->dev_addr[4], dev->dev_addr[5]);
2506 writel(0, base + NvRegWakeUpFlags);
2509 if (np->desc_ver == DESC_VER_1) {
2510 np->tx_flags = NV_TX_VALID;
2512 np->tx_flags = NV_TX2_VALID;
2514 np->irqmask = NVREG_IRQMASK_WANTED;
2515 if (id->driver_data & DEV_NEED_TIMERIRQ)
2516 np->irqmask |= NVREG_IRQ_TIMER;
2517 if (id->driver_data & DEV_NEED_LINKTIMER) {
2518 dprintk(KERN_INFO "%s: link timer on.\n", pci_name(pci_dev));
2519 np->need_linktimer = 1;
2520 np->link_timeout = jiffies + LINK_TIMEOUT;
2522 dprintk(KERN_INFO "%s: link timer off.\n", pci_name(pci_dev));
2523 np->need_linktimer = 0;
2526 /* find a suitable phy */
2527 for (i = 1; i < 32; i++) {
2530 spin_lock_irq(&np->lock);
2531 id1 = mii_rw(dev, i, MII_PHYSID1, MII_READ);
2532 spin_unlock_irq(&np->lock);
2533 if (id1 < 0 || id1 == 0xffff)
2535 spin_lock_irq(&np->lock);
2536 id2 = mii_rw(dev, i, MII_PHYSID2, MII_READ);
2537 spin_unlock_irq(&np->lock);
2538 if (id2 < 0 || id2 == 0xffff)
2541 id1 = (id1 & PHYID1_OUI_MASK) << PHYID1_OUI_SHFT;
2542 id2 = (id2 & PHYID2_OUI_MASK) >> PHYID2_OUI_SHFT;
2543 dprintk(KERN_DEBUG "%s: open: Found PHY %04x:%04x at address %d.\n",
2544 pci_name(pci_dev), id1, id2, i);
2546 np->phy_oui = id1 | id2;
2550 /* PHY in isolate mode? No phy attached and user wants to
2551 * test loopback? Very odd, but can be correct.
2553 printk(KERN_INFO "%s: open: Could not find a valid PHY.\n",
2562 /* set default link speed settings */
2563 np->linkspeed = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
2567 err = register_netdev(dev);
2569 printk(KERN_INFO "forcedeth: unable to register netdev: %d\n", err);
2572 printk(KERN_INFO "%s: forcedeth.c: subsystem: %05x:%04x bound to %s\n",
2573 dev->name, pci_dev->subsystem_vendor, pci_dev->subsystem_device,
2579 if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2)
2580 pci_free_consistent(np->pci_dev, sizeof(struct ring_desc) * (RX_RING + TX_RING),
2581 np->rx_ring.orig, np->ring_addr);
2583 pci_free_consistent(np->pci_dev, sizeof(struct ring_desc_ex) * (RX_RING + TX_RING),
2584 np->rx_ring.ex, np->ring_addr);
2585 pci_set_drvdata(pci_dev, NULL);
2587 iounmap(get_hwbase(dev));
2589 pci_release_regions(pci_dev);
2591 pci_disable_device(pci_dev);
2598 static void __devexit nv_remove(struct pci_dev *pci_dev)
2600 struct net_device *dev = pci_get_drvdata(pci_dev);
2601 struct fe_priv *np = netdev_priv(dev);
2603 unregister_netdev(dev);
2605 /* free all structures */
2606 if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2)
2607 pci_free_consistent(np->pci_dev, sizeof(struct ring_desc) * (RX_RING + TX_RING), np->rx_ring.orig, np->ring_addr);
2609 pci_free_consistent(np->pci_dev, sizeof(struct ring_desc_ex) * (RX_RING + TX_RING), np->rx_ring.ex, np->ring_addr);
2610 iounmap(get_hwbase(dev));
2611 pci_release_regions(pci_dev);
2612 pci_disable_device(pci_dev);
2614 pci_set_drvdata(pci_dev, NULL);
2617 static struct pci_device_id pci_tbl[] = {
2618 { /* nForce Ethernet Controller */
2619 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_1),
2620 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER,
2622 { /* nForce2 Ethernet Controller */
2623 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_2),
2624 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER,
2626 { /* nForce3 Ethernet Controller */
2627 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_3),
2628 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER,
2630 { /* nForce3 Ethernet Controller */
2631 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_4),
2632 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM,
2634 { /* nForce3 Ethernet Controller */
2635 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_5),
2636 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM,
2638 { /* nForce3 Ethernet Controller */
2639 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_6),
2640 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM,
2642 { /* nForce3 Ethernet Controller */
2643 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_7),
2644 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM,
2646 { /* CK804 Ethernet Controller */
2647 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_8),
2648 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA,
2650 { /* CK804 Ethernet Controller */
2651 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_9),
2652 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA,
2654 { /* MCP04 Ethernet Controller */
2655 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_10),
2656 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA,
2658 { /* MCP04 Ethernet Controller */
2659 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_11),
2660 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA,
2662 { /* MCP51 Ethernet Controller */
2663 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_12),
2664 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA,
2666 { /* MCP51 Ethernet Controller */
2667 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_13),
2668 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA,
2670 { /* MCP55 Ethernet Controller */
2671 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_14),
2672 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA,
2674 { /* MCP55 Ethernet Controller */
2675 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_15),
2676 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA,
2681 static struct pci_driver driver = {
2682 .name = "forcedeth",
2683 .id_table = pci_tbl,
2685 .remove = __devexit_p(nv_remove),
2689 static int __init init_nic(void)
2691 printk(KERN_INFO "forcedeth.c: Reverse Engineered nForce ethernet driver. Version %s.\n", FORCEDETH_VERSION);
2692 return pci_module_init(&driver);
2695 static void __exit exit_nic(void)
2697 pci_unregister_driver(&driver);
2700 module_param(max_interrupt_work, int, 0);
2701 MODULE_PARM_DESC(max_interrupt_work, "forcedeth maximum events handled per interrupt");
2703 MODULE_AUTHOR("Manfred Spraul <manfred@colorfullife.com>");
2704 MODULE_DESCRIPTION("Reverse Engineered nForce ethernet driver");
2705 MODULE_LICENSE("GPL");
2707 MODULE_DEVICE_TABLE(pci, pci_tbl);
2709 module_init(init_nic);
2710 module_exit(exit_nic);