err.no Git - linux-2.6/blob - drivers/net/forcedeth.c

   1 /*
   2  * forcedeth: Ethernet driver for NVIDIA nForce media access controllers.
   3  *
   4  * Note: This driver is a cleanroom reimplementation based on reverse
   5  *      engineered documentation written by Carl-Daniel Hailfinger
   6  *      and Andrew de Quincey.
   7  *
   8  * NVIDIA, nForce and other NVIDIA marks are trademarks or registered
   9  * trademarks of NVIDIA Corporation in the United States and other
  10  * countries.
  11  *
  12  * Copyright (C) 2003,4,5 Manfred Spraul
  13  * Copyright (C) 2004 Andrew de Quincey (wol support)
  14  * Copyright (C) 2004 Carl-Daniel Hailfinger (invalid MAC handling, insane
  15  *              IRQ rate fixes, bigendian fixes, cleanups, verification)
  16  * Copyright (c) 2004,5,6 NVIDIA Corporation
  17  *
  18  * This program is free software; you can redistribute it and/or modify
  19  * it under the terms of the GNU General Public License as published by
  20  * the Free Software Foundation; either version 2 of the License, or
  21  * (at your option) any later version.
  22  *
  23  * This program is distributed in the hope that it will be useful,
  24  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  25  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  26  * GNU General Public License for more details.
  27  *
  28  * You should have received a copy of the GNU General Public License
  29  * along with this program; if not, write to the Free Software
  30  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  31  *
  32  * Changelog:
  33  *      0.01: 05 Oct 2003: First release that compiles without warnings.
  34  *      0.02: 05 Oct 2003: Fix bug for nv_drain_tx: do not try to free NULL skbs.
  35  *                         Check all PCI BARs for the register window.
  36  *                         udelay added to mii_rw.
  37  *      0.03: 06 Oct 2003: Initialize dev->irq.
  38  *      0.04: 07 Oct 2003: Initialize np->lock, reduce handled irqs, add printks.
  39  *      0.05: 09 Oct 2003: printk removed again, irq status print tx_timeout.
  40  *      0.06: 10 Oct 2003: MAC Address read updated, pff flag generation updated,
  41  *                         irq mask updated
  42  *      0.07: 14 Oct 2003: Further irq mask updates.
  43  *      0.08: 20 Oct 2003: rx_desc.Length initialization added, nv_alloc_rx refill
  44  *                         added into irq handler, NULL check for drain_ring.
  45  *      0.09: 20 Oct 2003: Basic link speed irq implementation. Only handle the
  46  *                         requested interrupt sources.
  47  *      0.10: 20 Oct 2003: First cleanup for release.
  48  *      0.11: 21 Oct 2003: hexdump for tx added, rx buffer sizes increased.
  49  *                         MAC Address init fix, set_multicast cleanup.
  50  *      0.12: 23 Oct 2003: Cleanups for release.
  51  *      0.13: 25 Oct 2003: Limit for concurrent tx packets increased to 10.
  52  *                         Set link speed correctly. start rx before starting
  53  *                         tx (nv_start_rx sets the link speed).
  54  *      0.14: 25 Oct 2003: Nic dependant irq mask.
  55  *      0.15: 08 Nov 2003: fix smp deadlock with set_multicast_list during
  56  *                         open.
  57  *      0.16: 15 Nov 2003: include file cleanup for ppc64, rx buffer size
  58  *                         increased to 1628 bytes.
  59  *      0.17: 16 Nov 2003: undo rx buffer size increase. Substract 1 from
  60  *                         the tx length.
  61  *      0.18: 17 Nov 2003: fix oops due to late initialization of dev_stats
  62  *      0.19: 29 Nov 2003: Handle RxNoBuf, detect & handle invalid mac
  63  *                         addresses, really stop rx if already running
  64  *                         in nv_start_rx, clean up a bit.
  65  *      0.20: 07 Dec 2003: alloc fixes
  66  *      0.21: 12 Jan 2004: additional alloc fix, nic polling fix.
  67  *      0.22: 19 Jan 2004: reprogram timer to a sane rate, avoid lockup
  68  *                         on close.
  69  *      0.23: 26 Jan 2004: various small cleanups
  70  *      0.24: 27 Feb 2004: make driver even less anonymous in backtraces
  71  *      0.25: 09 Mar 2004: wol support
  72  *      0.26: 03 Jun 2004: netdriver specific annotation, sparse-related fixes
  73  *      0.27: 19 Jun 2004: Gigabit support, new descriptor rings,
  74  *                         added CK804/MCP04 device IDs, code fixes
  75  *                         for registers, link status and other minor fixes.
  76  *      0.28: 21 Jun 2004: Big cleanup, making driver mostly endian safe
  77  *      0.29: 31 Aug 2004: Add backup timer for link change notification.
  78  *      0.30: 25 Sep 2004: rx checksum support for nf 250 Gb. Add rx reset
  79  *                         into nv_close, otherwise reenabling for wol can
  80  *                         cause DMA to kfree'd memory.
  81  *      0.31: 14 Nov 2004: ethtool support for getting/setting link
  82  *                         capabilities.
  83  *      0.32: 16 Apr 2005: RX_ERROR4 handling added.
  84  *      0.33: 16 May 2005: Support for MCP51 added.
  85  *      0.34: 18 Jun 2005: Add DEV_NEED_LINKTIMER to all nForce nics.
  86  *      0.35: 26 Jun 2005: Support for MCP55 added.
  87  *      0.36: 28 Jun 2005: Add jumbo frame support.
  88  *      0.37: 10 Jul 2005: Additional ethtool support, cleanup of pci id list
  89  *      0.38: 16 Jul 2005: tx irq rewrite: Use global flags instead of
  90  *                         per-packet flags.
  91  *      0.39: 18 Jul 2005: Add 64bit descriptor support.
  92  *      0.40: 19 Jul 2005: Add support for mac address change.
  93  *      0.41: 30 Jul 2005: Write back original MAC in nv_close instead
  94  *                         of nv_remove
  95  *      0.42: 06 Aug 2005: Fix lack of link speed initialization
  96  *                         in the second (and later) nv_open call
  97  *      0.43: 10 Aug 2005: Add support for tx checksum.
  98  *      0.44: 20 Aug 2005: Add support for scatter gather and segmentation.
  99  *      0.45: 18 Sep 2005: Remove nv_stop/start_rx from every link check
 100  *      0.46: 20 Oct 2005: Add irq optimization modes.
 101  *      0.47: 26 Oct 2005: Add phyaddr 0 in phy scan.
 102  *      0.48: 24 Dec 2005: Disable TSO, bugfix for pci_map_single
 103  *      0.49: 10 Dec 2005: Fix tso for large buffers.
 104  *      0.50: 20 Jan 2006: Add 8021pq tagging support.
 105  *      0.51: 20 Jan 2006: Add 64bit consistent memory allocation for rings.
 106  *      0.52: 20 Jan 2006: Add MSI/MSIX support.
 107  *      0.53: 19 Mar 2006: Fix init from low power mode and add hw reset.
 108  *      0.54: 21 Mar 2006: Fix spin locks for multi irqs and cleanup.
 109  *      0.55: 22 Mar 2006: Add flow control (pause frame).
 110  *      0.56: 22 Mar 2006: Additional ethtool config and moduleparam support.
 111  *      0.57: 14 May 2006: Mac address set in probe/remove and order corrections.
 112  *      0.58: 30 Oct 2006: Added support for sideband management unit.
 113  *      0.59: 30 Oct 2006: Added support for recoverable error.
 114  *
 115  * Known bugs:
 116  * We suspect that on some hardware no TX done interrupts are generated.
 117  * This means recovery from netif_stop_queue only happens if the hw timer
 118  * interrupt fires (100 times/second, configurable with NVREG_POLL_DEFAULT)
 119  * and the timer is active in the IRQMask, or if a rx packet arrives by chance.
 120  * If your hardware reliably generates tx done interrupts, then you can remove
 121  * DEV_NEED_TIMERIRQ from the driver_data flags.
 122  * DEV_NEED_TIMERIRQ will not harm you on sane hardware, only generating a few
 123  * superfluous timer interrupts from the nic.
 124  */
 125 #ifdef CONFIG_FORCEDETH_NAPI
 126 #define DRIVERNAPI "-NAPI"
 127 #else
 128 #define DRIVERNAPI
 129 #endif
 130 #define FORCEDETH_VERSION               "0.59"
 131 #define DRV_NAME                        "forcedeth"
 132
 133 #include <linux/module.h>
 134 #include <linux/types.h>
 135 #include <linux/pci.h>
 136 #include <linux/interrupt.h>
 137 #include <linux/netdevice.h>
 138 #include <linux/etherdevice.h>
 139 #include <linux/delay.h>
 140 #include <linux/spinlock.h>
 141 #include <linux/ethtool.h>
 142 #include <linux/timer.h>
 143 #include <linux/skbuff.h>
 144 #include <linux/mii.h>
 145 #include <linux/random.h>
 146 #include <linux/init.h>
 147 #include <linux/if_vlan.h>
 148 #include <linux/dma-mapping.h>
 149
 150 #include <asm/irq.h>
 151 #include <asm/io.h>
 152 #include <asm/uaccess.h>
 153 #include <asm/system.h>
 154
 155 #if 0
 156 #define dprintk                 printk
 157 #else
 158 #define dprintk(x...)           do { } while (0)
 159 #endif
 160
 161
 162 /*
 163  * Hardware access:
 164  */
 165
 166 #define DEV_NEED_TIMERIRQ       0x0001  /* set the timer irq flag in the irq mask */
 167 #define DEV_NEED_LINKTIMER      0x0002  /* poll link settings. Relies on the timer irq */
 168 #define DEV_HAS_LARGEDESC       0x0004  /* device supports jumbo frames and needs packet format 2 */
 169 #define DEV_HAS_HIGH_DMA        0x0008  /* device supports 64bit dma */
 170 #define DEV_HAS_CHECKSUM        0x0010  /* device supports tx and rx checksum offloads */
 171 #define DEV_HAS_VLAN            0x0020  /* device supports vlan tagging and striping */
 172 #define DEV_HAS_MSI             0x0040  /* device supports MSI */
 173 #define DEV_HAS_MSI_X           0x0080  /* device supports MSI-X */
 174 #define DEV_HAS_POWER_CNTRL     0x0100  /* device supports power savings */
 175 #define DEV_HAS_PAUSEFRAME_TX   0x0200  /* device supports tx pause frames */
 176 #define DEV_HAS_STATISTICS      0x0400  /* device supports hw statistics */
 177 #define DEV_HAS_TEST_EXTENDED   0x0800  /* device supports extended diagnostic test */
 178 #define DEV_HAS_MGMT_UNIT       0x1000  /* device supports management unit */
 179
 180 enum {
 181         NvRegIrqStatus = 0x000,
 182 #define NVREG_IRQSTAT_MIIEVENT  0x040
 183 #define NVREG_IRQSTAT_MASK              0x81ff
 184         NvRegIrqMask = 0x004,
 185 #define NVREG_IRQ_RX_ERROR              0x0001
 186 #define NVREG_IRQ_RX                    0x0002
 187 #define NVREG_IRQ_RX_NOBUF              0x0004
 188 #define NVREG_IRQ_TX_ERR                0x0008
 189 #define NVREG_IRQ_TX_OK                 0x0010
 190 #define NVREG_IRQ_TIMER                 0x0020
 191 #define NVREG_IRQ_LINK                  0x0040
 192 #define NVREG_IRQ_RX_FORCED             0x0080
 193 #define NVREG_IRQ_TX_FORCED             0x0100
 194 #define NVREG_IRQ_RECOVER_ERROR         0x8000
 195 #define NVREG_IRQMASK_THROUGHPUT        0x00df
 196 #define NVREG_IRQMASK_CPU               0x0040
 197 #define NVREG_IRQ_TX_ALL                (NVREG_IRQ_TX_ERR|NVREG_IRQ_TX_OK|NVREG_IRQ_TX_FORCED)
 198 #define NVREG_IRQ_RX_ALL                (NVREG_IRQ_RX_ERROR|NVREG_IRQ_RX|NVREG_IRQ_RX_NOBUF|NVREG_IRQ_RX_FORCED)
 199 #define NVREG_IRQ_OTHER                 (NVREG_IRQ_TIMER|NVREG_IRQ_LINK|NVREG_IRQ_RECOVER_ERROR)
 200
 201 #define NVREG_IRQ_UNKNOWN       (~(NVREG_IRQ_RX_ERROR|NVREG_IRQ_RX|NVREG_IRQ_RX_NOBUF|NVREG_IRQ_TX_ERR| \
 202                                         NVREG_IRQ_TX_OK|NVREG_IRQ_TIMER|NVREG_IRQ_LINK|NVREG_IRQ_RX_FORCED| \
 203                                         NVREG_IRQ_TX_FORCED|NVREG_IRQ_RECOVER_ERROR))
 204
 205         NvRegUnknownSetupReg6 = 0x008,
 206 #define NVREG_UNKSETUP6_VAL             3
 207
 208 /*
 209  * NVREG_POLL_DEFAULT is the interval length of the timer source on the nic
 210  * NVREG_POLL_DEFAULT=97 would result in an interval length of 1 ms
 211  */
 212         NvRegPollingInterval = 0x00c,
 213 #define NVREG_POLL_DEFAULT_THROUGHPUT   970
 214 #define NVREG_POLL_DEFAULT_CPU  13
 215         NvRegMSIMap0 = 0x020,
 216         NvRegMSIMap1 = 0x024,
 217         NvRegMSIIrqMask = 0x030,
 218 #define NVREG_MSI_VECTOR_0_ENABLED 0x01
 219         NvRegMisc1 = 0x080,
 220 #define NVREG_MISC1_PAUSE_TX    0x01
 221 #define NVREG_MISC1_HD          0x02
 222 #define NVREG_MISC1_FORCE       0x3b0f3c
 223
 224         NvRegMacReset = 0x3c,
 225 #define NVREG_MAC_RESET_ASSERT  0x0F3
 226         NvRegTransmitterControl = 0x084,
 227 #define NVREG_XMITCTL_START     0x01
 228 #define NVREG_XMITCTL_MGMT_ST   0x40000000
 229 #define NVREG_XMITCTL_SYNC_MASK         0x000f0000
 230 #define NVREG_XMITCTL_SYNC_NOT_READY    0x0
 231 #define NVREG_XMITCTL_SYNC_PHY_INIT     0x00040000
 232 #define NVREG_XMITCTL_MGMT_SEMA_MASK    0x00000f00
 233 #define NVREG_XMITCTL_MGMT_SEMA_FREE    0x0
 234 #define NVREG_XMITCTL_HOST_SEMA_MASK    0x0000f000
 235 #define NVREG_XMITCTL_HOST_SEMA_ACQ     0x0000f000
 236 #define NVREG_XMITCTL_HOST_LOADED       0x00004000
 237 #define NVREG_XMITCTL_TX_PATH_EN        0x01000000
 238         NvRegTransmitterStatus = 0x088,
 239 #define NVREG_XMITSTAT_BUSY     0x01
 240
 241         NvRegPacketFilterFlags = 0x8c,
 242 #define NVREG_PFF_PAUSE_RX      0x08
 243 #define NVREG_PFF_ALWAYS        0x7F0000
 244 #define NVREG_PFF_PROMISC       0x80
 245 #define NVREG_PFF_MYADDR        0x20
 246 #define NVREG_PFF_LOOPBACK      0x10
 247
 248         NvRegOffloadConfig = 0x90,
 249 #define NVREG_OFFLOAD_HOMEPHY   0x601
 250 #define NVREG_OFFLOAD_NORMAL    RX_NIC_BUFSIZE
 251         NvRegReceiverControl = 0x094,
 252 #define NVREG_RCVCTL_START      0x01
 253 #define NVREG_RCVCTL_RX_PATH_EN 0x01000000
 254         NvRegReceiverStatus = 0x98,
 255 #define NVREG_RCVSTAT_BUSY      0x01
 256
 257         NvRegRandomSeed = 0x9c,
 258 #define NVREG_RNDSEED_MASK      0x00ff
 259 #define NVREG_RNDSEED_FORCE     0x7f00
 260 #define NVREG_RNDSEED_FORCE2    0x2d00
 261 #define NVREG_RNDSEED_FORCE3    0x7400
 262
 263         NvRegTxDeferral = 0xA0,
 264 #define NVREG_TX_DEFERRAL_DEFAULT       0x15050f
 265 #define NVREG_TX_DEFERRAL_RGMII_10_100  0x16070f
 266 #define NVREG_TX_DEFERRAL_RGMII_1000    0x14050f
 267         NvRegRxDeferral = 0xA4,
 268 #define NVREG_RX_DEFERRAL_DEFAULT       0x16
 269         NvRegMacAddrA = 0xA8,
 270         NvRegMacAddrB = 0xAC,
 271         NvRegMulticastAddrA = 0xB0,
 272 #define NVREG_MCASTADDRA_FORCE  0x01
 273         NvRegMulticastAddrB = 0xB4,
 274         NvRegMulticastMaskA = 0xB8,
 275         NvRegMulticastMaskB = 0xBC,
 276
 277         NvRegPhyInterface = 0xC0,
 278 #define PHY_RGMII               0x10000000
 279
 280         NvRegTxRingPhysAddr = 0x100,
 281         NvRegRxRingPhysAddr = 0x104,
 282         NvRegRingSizes = 0x108,
 283 #define NVREG_RINGSZ_TXSHIFT 0
 284 #define NVREG_RINGSZ_RXSHIFT 16
 285         NvRegTransmitPoll = 0x10c,
 286 #define NVREG_TRANSMITPOLL_MAC_ADDR_REV 0x00008000
 287         NvRegLinkSpeed = 0x110,
 288 #define NVREG_LINKSPEED_FORCE 0x10000
 289 #define NVREG_LINKSPEED_10      1000
 290 #define NVREG_LINKSPEED_100     100
 291 #define NVREG_LINKSPEED_1000    50
 292 #define NVREG_LINKSPEED_MASK    (0xFFF)
 293         NvRegUnknownSetupReg5 = 0x130,
 294 #define NVREG_UNKSETUP5_BIT31   (1<<31)
 295         NvRegTxWatermark = 0x13c,
 296 #define NVREG_TX_WM_DESC1_DEFAULT       0x0200010
 297 #define NVREG_TX_WM_DESC2_3_DEFAULT     0x1e08000
 298 #define NVREG_TX_WM_DESC2_3_1000        0xfe08000
 299         NvRegTxRxControl = 0x144,
 300 #define NVREG_TXRXCTL_KICK      0x0001
 301 #define NVREG_TXRXCTL_BIT1      0x0002
 302 #define NVREG_TXRXCTL_BIT2      0x0004
 303 #define NVREG_TXRXCTL_IDLE      0x0008
 304 #define NVREG_TXRXCTL_RESET     0x0010
 305 #define NVREG_TXRXCTL_RXCHECK   0x0400
 306 #define NVREG_TXRXCTL_DESC_1    0
 307 #define NVREG_TXRXCTL_DESC_2    0x002100
 308 #define NVREG_TXRXCTL_DESC_3    0xc02200
 309 #define NVREG_TXRXCTL_VLANSTRIP 0x00040
 310 #define NVREG_TXRXCTL_VLANINS   0x00080
 311         NvRegTxRingPhysAddrHigh = 0x148,
 312         NvRegRxRingPhysAddrHigh = 0x14C,
 313         NvRegTxPauseFrame = 0x170,
 314 #define NVREG_TX_PAUSEFRAME_DISABLE     0x1ff0080
 315 #define NVREG_TX_PAUSEFRAME_ENABLE      0x0c00030
 316         NvRegMIIStatus = 0x180,
 317 #define NVREG_MIISTAT_ERROR             0x0001
 318 #define NVREG_MIISTAT_LINKCHANGE        0x0008
 319 #define NVREG_MIISTAT_MASK              0x000f
 320 #define NVREG_MIISTAT_MASK2             0x000f
 321         NvRegMIIMask = 0x184,
 322 #define NVREG_MII_LINKCHANGE            0x0008
 323
 324         NvRegAdapterControl = 0x188,
 325 #define NVREG_ADAPTCTL_START    0x02
 326 #define NVREG_ADAPTCTL_LINKUP   0x04
 327 #define NVREG_ADAPTCTL_PHYVALID 0x40000
 328 #define NVREG_ADAPTCTL_RUNNING  0x100000
 329 #define NVREG_ADAPTCTL_PHYSHIFT 24
 330         NvRegMIISpeed = 0x18c,
 331 #define NVREG_MIISPEED_BIT8     (1<<8)
 332 #define NVREG_MIIDELAY  5
 333         NvRegMIIControl = 0x190,
 334 #define NVREG_MIICTL_INUSE      0x08000
 335 #define NVREG_MIICTL_WRITE      0x00400
 336 #define NVREG_MIICTL_ADDRSHIFT  5
 337         NvRegMIIData = 0x194,
 338         NvRegWakeUpFlags = 0x200,
 339 #define NVREG_WAKEUPFLAGS_VAL           0x7770
 340 #define NVREG_WAKEUPFLAGS_BUSYSHIFT     24
 341 #define NVREG_WAKEUPFLAGS_ENABLESHIFT   16
 342 #define NVREG_WAKEUPFLAGS_D3SHIFT       12
 343 #define NVREG_WAKEUPFLAGS_D2SHIFT       8
 344 #define NVREG_WAKEUPFLAGS_D1SHIFT       4
 345 #define NVREG_WAKEUPFLAGS_D0SHIFT       0
 346 #define NVREG_WAKEUPFLAGS_ACCEPT_MAGPAT         0x01
 347 #define NVREG_WAKEUPFLAGS_ACCEPT_WAKEUPPAT      0x02
 348 #define NVREG_WAKEUPFLAGS_ACCEPT_LINKCHANGE     0x04
 349 #define NVREG_WAKEUPFLAGS_ENABLE        0x1111
 350
 351         NvRegPatternCRC = 0x204,
 352         NvRegPatternMask = 0x208,
 353         NvRegPowerCap = 0x268,
 354 #define NVREG_POWERCAP_D3SUPP   (1<<30)
 355 #define NVREG_POWERCAP_D2SUPP   (1<<26)
 356 #define NVREG_POWERCAP_D1SUPP   (1<<25)
 357         NvRegPowerState = 0x26c,
 358 #define NVREG_POWERSTATE_POWEREDUP      0x8000
 359 #define NVREG_POWERSTATE_VALID          0x0100
 360 #define NVREG_POWERSTATE_MASK           0x0003
 361 #define NVREG_POWERSTATE_D0             0x0000
 362 #define NVREG_POWERSTATE_D1             0x0001
 363 #define NVREG_POWERSTATE_D2             0x0002
 364 #define NVREG_POWERSTATE_D3             0x0003
 365         NvRegTxCnt = 0x280,
 366         NvRegTxZeroReXmt = 0x284,
 367         NvRegTxOneReXmt = 0x288,
 368         NvRegTxManyReXmt = 0x28c,
 369         NvRegTxLateCol = 0x290,
 370         NvRegTxUnderflow = 0x294,
 371         NvRegTxLossCarrier = 0x298,
 372         NvRegTxExcessDef = 0x29c,
 373         NvRegTxRetryErr = 0x2a0,
 374         NvRegRxFrameErr = 0x2a4,
 375         NvRegRxExtraByte = 0x2a8,
 376         NvRegRxLateCol = 0x2ac,
 377         NvRegRxRunt = 0x2b0,
 378         NvRegRxFrameTooLong = 0x2b4,
 379         NvRegRxOverflow = 0x2b8,
 380         NvRegRxFCSErr = 0x2bc,
 381         NvRegRxFrameAlignErr = 0x2c0,
 382         NvRegRxLenErr = 0x2c4,
 383         NvRegRxUnicast = 0x2c8,
 384         NvRegRxMulticast = 0x2cc,
 385         NvRegRxBroadcast = 0x2d0,
 386         NvRegTxDef = 0x2d4,
 387         NvRegTxFrame = 0x2d8,
 388         NvRegRxCnt = 0x2dc,
 389         NvRegTxPause = 0x2e0,
 390         NvRegRxPause = 0x2e4,
 391         NvRegRxDropFrame = 0x2e8,
 392         NvRegVlanControl = 0x300,
 393 #define NVREG_VLANCONTROL_ENABLE        0x2000
 394         NvRegMSIXMap0 = 0x3e0,
 395         NvRegMSIXMap1 = 0x3e4,
 396         NvRegMSIXIrqStatus = 0x3f0,
 397
 398         NvRegPowerState2 = 0x600,
 399 #define NVREG_POWERSTATE2_POWERUP_MASK          0x0F11
 400 #define NVREG_POWERSTATE2_POWERUP_REV_A3        0x0001
 401 };
 402
 403 /* Big endian: should work, but is untested */
 404 struct ring_desc {
 405         __le32 buf;
 406         __le32 flaglen;
 407 };
 408
 409 struct ring_desc_ex {
 410         __le32 bufhigh;
 411         __le32 buflow;
 412         __le32 txvlan;
 413         __le32 flaglen;
 414 };
 415
 416 union ring_type {
 417         struct ring_desc* orig;
 418         struct ring_desc_ex* ex;
 419 };
 420
 421 #define FLAG_MASK_V1 0xffff0000
 422 #define FLAG_MASK_V2 0xffffc000
 423 #define LEN_MASK_V1 (0xffffffff ^ FLAG_MASK_V1)
 424 #define LEN_MASK_V2 (0xffffffff ^ FLAG_MASK_V2)
 425
 426 #define NV_TX_LASTPACKET        (1<<16)
 427 #define NV_TX_RETRYERROR        (1<<19)
 428 #define NV_TX_FORCED_INTERRUPT  (1<<24)
 429 #define NV_TX_DEFERRED          (1<<26)
 430 #define NV_TX_CARRIERLOST       (1<<27)
 431 #define NV_TX_LATECOLLISION     (1<<28)
 432 #define NV_TX_UNDERFLOW         (1<<29)
 433 #define NV_TX_ERROR             (1<<30)
 434 #define NV_TX_VALID             (1<<31)
 435
 436 #define NV_TX2_LASTPACKET       (1<<29)
 437 #define NV_TX2_RETRYERROR       (1<<18)
 438 #define NV_TX2_FORCED_INTERRUPT (1<<30)
 439 #define NV_TX2_DEFERRED         (1<<25)
 440 #define NV_TX2_CARRIERLOST      (1<<26)
 441 #define NV_TX2_LATECOLLISION    (1<<27)
 442 #define NV_TX2_UNDERFLOW        (1<<28)
 443 /* error and valid are the same for both */
 444 #define NV_TX2_ERROR            (1<<30)
 445 #define NV_TX2_VALID            (1<<31)
 446 #define NV_TX2_TSO              (1<<28)
 447 #define NV_TX2_TSO_SHIFT        14
 448 #define NV_TX2_TSO_MAX_SHIFT    14
 449 #define NV_TX2_TSO_MAX_SIZE     (1<<NV_TX2_TSO_MAX_SHIFT)
 450 #define NV_TX2_CHECKSUM_L3      (1<<27)
 451 #define NV_TX2_CHECKSUM_L4      (1<<26)
 452
 453 #define NV_TX3_VLAN_TAG_PRESENT (1<<18)
 454
 455 #define NV_RX_DESCRIPTORVALID   (1<<16)
 456 #define NV_RX_MISSEDFRAME       (1<<17)
 457 #define NV_RX_SUBSTRACT1        (1<<18)
 458 #define NV_RX_ERROR1            (1<<23)
 459 #define NV_RX_ERROR2            (1<<24)
 460 #define NV_RX_ERROR3            (1<<25)
 461 #define NV_RX_ERROR4            (1<<26)
 462 #define NV_RX_CRCERR            (1<<27)
 463 #define NV_RX_OVERFLOW          (1<<28)
 464 #define NV_RX_FRAMINGERR        (1<<29)
 465 #define NV_RX_ERROR             (1<<30)
 466 #define NV_RX_AVAIL             (1<<31)
 467
 468 #define NV_RX2_CHECKSUMMASK     (0x1C000000)
 469 #define NV_RX2_CHECKSUMOK1      (0x10000000)
 470 #define NV_RX2_CHECKSUMOK2      (0x14000000)
 471 #define NV_RX2_CHECKSUMOK3      (0x18000000)
 472 #define NV_RX2_DESCRIPTORVALID  (1<<29)
 473 #define NV_RX2_SUBSTRACT1       (1<<25)
 474 #define NV_RX2_ERROR1           (1<<18)
 475 #define NV_RX2_ERROR2           (1<<19)
 476 #define NV_RX2_ERROR3           (1<<20)
 477 #define NV_RX2_ERROR4           (1<<21)
 478 #define NV_RX2_CRCERR           (1<<22)
 479 #define NV_RX2_OVERFLOW         (1<<23)
 480 #define NV_RX2_FRAMINGERR       (1<<24)
 481 /* error and avail are the same for both */
 482 #define NV_RX2_ERROR            (1<<30)
 483 #define NV_RX2_AVAIL            (1<<31)
 484
 485 #define NV_RX3_VLAN_TAG_PRESENT (1<<16)
 486 #define NV_RX3_VLAN_TAG_MASK    (0x0000FFFF)
 487
 488 /* Miscelaneous hardware related defines: */
 489 #define NV_PCI_REGSZ_VER1       0x270
 490 #define NV_PCI_REGSZ_VER2       0x604
 491
 492 /* various timeout delays: all in usec */
 493 #define NV_TXRX_RESET_DELAY     4
 494 #define NV_TXSTOP_DELAY1        10
 495 #define NV_TXSTOP_DELAY1MAX     500000
 496 #define NV_TXSTOP_DELAY2        100
 497 #define NV_RXSTOP_DELAY1        10
 498 #define NV_RXSTOP_DELAY1MAX     500000
 499 #define NV_RXSTOP_DELAY2        100
 500 #define NV_SETUP5_DELAY         5
 501 #define NV_SETUP5_DELAYMAX      50000
 502 #define NV_POWERUP_DELAY        5
 503 #define NV_POWERUP_DELAYMAX     5000
 504 #define NV_MIIBUSY_DELAY        50
 505 #define NV_MIIPHY_DELAY 10
 506 #define NV_MIIPHY_DELAYMAX      10000
 507 #define NV_MAC_RESET_DELAY      64
 508
 509 #define NV_WAKEUPPATTERNS       5
 510 #define NV_WAKEUPMASKENTRIES    4
 511
 512 /* General driver defaults */
 513 #define NV_WATCHDOG_TIMEO       (5*HZ)
 514
 515 #define RX_RING_DEFAULT         128
 516 #define TX_RING_DEFAULT         256
 517 #define RX_RING_MIN             128
 518 #define TX_RING_MIN             64
 519 #define RING_MAX_DESC_VER_1     1024
 520 #define RING_MAX_DESC_VER_2_3   16384
 521 /*
 522  * Difference between the get and put pointers for the tx ring.
 523  * This is used to throttle the amount of data outstanding in the
 524  * tx ring.
 525  */
 526 #define TX_LIMIT_DIFFERENCE     1
 527
 528 /* rx/tx mac addr + type + vlan + align + slack*/
 529 #define NV_RX_HEADERS           (64)
 530 /* even more slack. */
 531 #define NV_RX_ALLOC_PAD         (64)
 532
 533 /* maximum mtu size */
 534 #define NV_PKTLIMIT_1   ETH_DATA_LEN    /* hard limit not known */
 535 #define NV_PKTLIMIT_2   9100    /* Actual limit according to NVidia: 9202 */
 536
 537 #define OOM_REFILL      (1+HZ/20)
 538 #define POLL_WAIT       (1+HZ/100)
 539 #define LINK_TIMEOUT    (3*HZ)
 540 #define STATS_INTERVAL  (10*HZ)
 541
 542 /*
 543  * desc_ver values:
 544  * The nic supports three different descriptor types:
 545  * - DESC_VER_1: Original
 546  * - DESC_VER_2: support for jumbo frames.
 547  * - DESC_VER_3: 64-bit format.
 548  */
 549 #define DESC_VER_1      1
 550 #define DESC_VER_2      2
 551 #define DESC_VER_3      3
 552
 553 /* PHY defines */
 554 #define PHY_OUI_MARVELL 0x5043
 555 #define PHY_OUI_CICADA  0x03f1
 556 #define PHYID1_OUI_MASK 0x03ff
 557 #define PHYID1_OUI_SHFT 6
 558 #define PHYID2_OUI_MASK 0xfc00
 559 #define PHYID2_OUI_SHFT 10
 560 #define PHYID2_MODEL_MASK               0x03f0
 561 #define PHY_MODEL_MARVELL_E3016         0x220
 562 #define PHY_MARVELL_E3016_INITMASK      0x0300
 563 #define PHY_INIT1       0x0f000
 564 #define PHY_INIT2       0x0e00
 565 #define PHY_INIT3       0x01000
 566 #define PHY_INIT4       0x0200
 567 #define PHY_INIT5       0x0004
 568 #define PHY_INIT6       0x02000
 569 #define PHY_GIGABIT     0x0100
 570
 571 #define PHY_TIMEOUT     0x1
 572 #define PHY_ERROR       0x2
 573
 574 #define PHY_100 0x1
 575 #define PHY_1000        0x2
 576 #define PHY_HALF        0x100
 577
 578 #define NV_PAUSEFRAME_RX_CAPABLE 0x0001
 579 #define NV_PAUSEFRAME_TX_CAPABLE 0x0002
 580 #define NV_PAUSEFRAME_RX_ENABLE  0x0004
 581 #define NV_PAUSEFRAME_TX_ENABLE  0x0008
 582 #define NV_PAUSEFRAME_RX_REQ     0x0010
 583 #define NV_PAUSEFRAME_TX_REQ     0x0020
 584 #define NV_PAUSEFRAME_AUTONEG    0x0040
 585
 586 /* MSI/MSI-X defines */
 587 #define NV_MSI_X_MAX_VECTORS  8
 588 #define NV_MSI_X_VECTORS_MASK 0x000f
 589 #define NV_MSI_CAPABLE        0x0010
 590 #define NV_MSI_X_CAPABLE      0x0020
 591 #define NV_MSI_ENABLED        0x0040
 592 #define NV_MSI_X_ENABLED      0x0080
 593
 594 #define NV_MSI_X_VECTOR_ALL   0x0
 595 #define NV_MSI_X_VECTOR_RX    0x0
 596 #define NV_MSI_X_VECTOR_TX    0x1
 597 #define NV_MSI_X_VECTOR_OTHER 0x2
 598
 599 /* statistics */
 600 struct nv_ethtool_str {
 601         char name[ETH_GSTRING_LEN];
 602 };
 603
 604 static const struct nv_ethtool_str nv_estats_str[] = {
 605         { "tx_bytes" },
 606         { "tx_zero_rexmt" },
 607         { "tx_one_rexmt" },
 608         { "tx_many_rexmt" },
 609         { "tx_late_collision" },
 610         { "tx_fifo_errors" },
 611         { "tx_carrier_errors" },
 612         { "tx_excess_deferral" },
 613         { "tx_retry_error" },
 614         { "tx_deferral" },
 615         { "tx_packets" },
 616         { "tx_pause" },
 617         { "rx_frame_error" },
 618         { "rx_extra_byte" },
 619         { "rx_late_collision" },
 620         { "rx_runt" },
 621         { "rx_frame_too_long" },
 622         { "rx_over_errors" },
 623         { "rx_crc_errors" },
 624         { "rx_frame_align_error" },
 625         { "rx_length_error" },
 626         { "rx_unicast" },
 627         { "rx_multicast" },
 628         { "rx_broadcast" },
 629         { "rx_bytes" },
 630         { "rx_pause" },
 631         { "rx_drop_frame" },
 632         { "rx_packets" },
 633         { "rx_errors_total" }
 634 };
 635
 636 struct nv_ethtool_stats {
 637         u64 tx_bytes;
 638         u64 tx_zero_rexmt;
 639         u64 tx_one_rexmt;
 640         u64 tx_many_rexmt;
 641         u64 tx_late_collision;
 642         u64 tx_fifo_errors;
 643         u64 tx_carrier_errors;
 644         u64 tx_excess_deferral;
 645         u64 tx_retry_error;
 646         u64 tx_deferral;
 647         u64 tx_packets;
 648         u64 tx_pause;
 649         u64 rx_frame_error;
 650         u64 rx_extra_byte;
 651         u64 rx_late_collision;
 652         u64 rx_runt;
 653         u64 rx_frame_too_long;
 654         u64 rx_over_errors;
 655         u64 rx_crc_errors;
 656         u64 rx_frame_align_error;
 657         u64 rx_length_error;
 658         u64 rx_unicast;
 659         u64 rx_multicast;
 660         u64 rx_broadcast;
 661         u64 rx_bytes;
 662         u64 rx_pause;
 663         u64 rx_drop_frame;
 664         u64 rx_packets;
 665         u64 rx_errors_total;
 666 };
 667
 668 /* diagnostics */
 669 #define NV_TEST_COUNT_BASE 3
 670 #define NV_TEST_COUNT_EXTENDED 4
 671
 672 static const struct nv_ethtool_str nv_etests_str[] = {
 673         { "link      (online/offline)" },
 674         { "register  (offline)       " },
 675         { "interrupt (offline)       " },
 676         { "loopback  (offline)       " }
 677 };
 678
 679 struct register_test {
 680         __le32 reg;
 681         __le32 mask;
 682 };
 683
 684 static const struct register_test nv_registers_test[] = {
 685         { NvRegUnknownSetupReg6, 0x01 },
 686         { NvRegMisc1, 0x03c },
 687         { NvRegOffloadConfig, 0x03ff },
 688         { NvRegMulticastAddrA, 0xffffffff },
 689         { NvRegTxWatermark, 0x0ff },
 690         { NvRegWakeUpFlags, 0x07777 },
 691         { 0,0 }
 692 };
 693
 694 struct nv_skb_map {
 695         struct sk_buff *skb;
 696         dma_addr_t dma;
 697         unsigned int dma_len;
 698 };
 699
 700 /*
 701  * SMP locking:
 702  * All hardware access under dev->priv->lock, except the performance
 703  * critical parts:
 704  * - rx is (pseudo-) lockless: it relies on the single-threading provided
 705  *      by the arch code for interrupts.
 706  * - tx setup is lockless: it relies on netif_tx_lock. Actual submission
 707  *      needs dev->priv->lock :-(
 708  * - set_multicast_list: preparation lockless, relies on netif_tx_lock.
 709  */
 710
 711 /* in dev: base, irq */
 712 struct fe_priv {
 713         spinlock_t lock;
 714
 715         /* General data:
 716          * Locking: spin_lock(&np->lock); */
 717         struct net_device_stats stats;
 718         struct nv_ethtool_stats estats;
 719         int in_shutdown;
 720         u32 linkspeed;
 721         int duplex;
 722         int autoneg;
 723         int fixed_mode;
 724         int phyaddr;
 725         int wolenabled;
 726         unsigned int phy_oui;
 727         unsigned int phy_model;
 728         u16 gigabit;
 729         int intr_test;
 730         int recover_error;
 731
 732         /* General data: RO fields */
 733         dma_addr_t ring_addr;
 734         struct pci_dev *pci_dev;
 735         u32 orig_mac[2];
 736         u32 irqmask;
 737         u32 desc_ver;
 738         u32 txrxctl_bits;
 739         u32 vlanctl_bits;
 740         u32 driver_data;
 741         u32 register_size;
 742         int rx_csum;
 743         u32 mac_in_use;
 744
 745         void __iomem *base;
 746
 747         /* rx specific fields.
 748          * Locking: Within irq hander or disable_irq+spin_lock(&np->lock);
 749          */
 750         union ring_type get_rx, put_rx, first_rx, last_rx;
 751         struct nv_skb_map *get_rx_ctx, *put_rx_ctx;
 752         struct nv_skb_map *first_rx_ctx, *last_rx_ctx;
 753         struct nv_skb_map *rx_skb;
 754
 755         union ring_type rx_ring;
 756         unsigned int rx_buf_sz;
 757         unsigned int pkt_limit;
 758         struct timer_list oom_kick;
 759         struct timer_list nic_poll;
 760         struct timer_list stats_poll;
 761         u32 nic_poll_irq;
 762         int rx_ring_size;
 763
 764         /* media detection workaround.
 765          * Locking: Within irq hander or disable_irq+spin_lock(&np->lock);
 766          */
 767         int need_linktimer;
 768         unsigned long link_timeout;
 769         /*
 770          * tx specific fields.
 771          */
 772         union ring_type get_tx, put_tx, first_tx, last_tx;
 773         struct nv_skb_map *get_tx_ctx, *put_tx_ctx;
 774         struct nv_skb_map *first_tx_ctx, *last_tx_ctx;
 775         struct nv_skb_map *tx_skb;
 776
 777         union ring_type tx_ring;
 778         u32 tx_flags;
 779         int tx_ring_size;
 780         int tx_limit_start;
 781         int tx_limit_stop;
 782
 783         /* vlan fields */
 784         struct vlan_group *vlangrp;
 785
 786         /* msi/msi-x fields */
 787         u32 msi_flags;
 788         struct msix_entry msi_x_entry[NV_MSI_X_MAX_VECTORS];
 789
 790         /* flow control */
 791         u32 pause_flags;
 792 };
 793
 794 /*
 795  * Maximum number of loops until we assume that a bit in the irq mask
 796  * is stuck. Overridable with module param.
 797  */
 798 static int max_interrupt_work = 5;
 799
 800 /*
 801  * Optimization can be either throuput mode or cpu mode
 802  *
 803  * Throughput Mode: Every tx and rx packet will generate an interrupt.
 804  * CPU Mode: Interrupts are controlled by a timer.
 805  */
 806 enum {
 807         NV_OPTIMIZATION_MODE_THROUGHPUT,
 808         NV_OPTIMIZATION_MODE_CPU
 809 };
 810 static int optimization_mode = NV_OPTIMIZATION_MODE_THROUGHPUT;
 811
 812 /*
 813  * Poll interval for timer irq
 814  *
 815  * This interval determines how frequent an interrupt is generated.
 816  * The is value is determined by [(time_in_micro_secs * 100) / (2^10)]
 817  * Min = 0, and Max = 65535
 818  */
 819 static int poll_interval = -1;
 820
 821 /*
 822  * MSI interrupts
 823  */
 824 enum {
 825         NV_MSI_INT_DISABLED,
 826         NV_MSI_INT_ENABLED
 827 };
 828 static int msi = NV_MSI_INT_ENABLED;
 829
 830 /*
 831  * MSIX interrupts
 832  */
 833 enum {
 834         NV_MSIX_INT_DISABLED,
 835         NV_MSIX_INT_ENABLED
 836 };
 837 static int msix = NV_MSIX_INT_ENABLED;
 838
 839 /*
 840  * DMA 64bit
 841  */
 842 enum {
 843         NV_DMA_64BIT_DISABLED,
 844         NV_DMA_64BIT_ENABLED
 845 };
 846 static int dma_64bit = NV_DMA_64BIT_ENABLED;
 847
 848 static inline struct fe_priv *get_nvpriv(struct net_device *dev)
 849 {
 850         return netdev_priv(dev);
 851 }
 852
 853 static inline u8 __iomem *get_hwbase(struct net_device *dev)
 854 {
 855         return ((struct fe_priv *)netdev_priv(dev))->base;
 856 }
 857
 858 static inline void pci_push(u8 __iomem *base)
 859 {
 860         /* force out pending posted writes */
 861         readl(base);
 862 }
 863
 864 static inline u32 nv_descr_getlength(struct ring_desc *prd, u32 v)
 865 {
 866         return le32_to_cpu(prd->flaglen)
 867                 & ((v == DESC_VER_1) ? LEN_MASK_V1 : LEN_MASK_V2);
 868 }
 869
 870 static inline u32 nv_descr_getlength_ex(struct ring_desc_ex *prd, u32 v)
 871 {
 872         return le32_to_cpu(prd->flaglen) & LEN_MASK_V2;
 873 }
 874
 875 static int reg_delay(struct net_device *dev, int offset, u32 mask, u32 target,
 876                                 int delay, int delaymax, const char *msg)
 877 {
 878         u8 __iomem *base = get_hwbase(dev);
 879
 880         pci_push(base);
 881         do {
 882                 udelay(delay);
 883                 delaymax -= delay;
 884                 if (delaymax < 0) {
 885                         if (msg)
 886                                 printk(msg);
 887                         return 1;
 888                 }
 889         } while ((readl(base + offset) & mask) != target);
 890         return 0;
 891 }
 892
 893 #define NV_SETUP_RX_RING 0x01
 894 #define NV_SETUP_TX_RING 0x02
 895
 896 static void setup_hw_rings(struct net_device *dev, int rxtx_flags)
 897 {
 898         struct fe_priv *np = get_nvpriv(dev);
 899         u8 __iomem *base = get_hwbase(dev);
 900
 901         if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) {
 902                 if (rxtx_flags & NV_SETUP_RX_RING) {
 903                         writel((u32) cpu_to_le64(np->ring_addr), base + NvRegRxRingPhysAddr);
 904                 }
 905                 if (rxtx_flags & NV_SETUP_TX_RING) {
 906                         writel((u32) cpu_to_le64(np->ring_addr + np->rx_ring_size*sizeof(struct ring_desc)), base + NvRegTxRingPhysAddr);
 907                 }
 908         } else {
 909                 if (rxtx_flags & NV_SETUP_RX_RING) {
 910                         writel((u32) cpu_to_le64(np->ring_addr), base + NvRegRxRingPhysAddr);
 911                         writel((u32) (cpu_to_le64(np->ring_addr) >> 32), base + NvRegRxRingPhysAddrHigh);
 912                 }
 913                 if (rxtx_flags & NV_SETUP_TX_RING) {
 914                         writel((u32) cpu_to_le64(np->ring_addr + np->rx_ring_size*sizeof(struct ring_desc_ex)), base + NvRegTxRingPhysAddr);
 915                         writel((u32) (cpu_to_le64(np->ring_addr + np->rx_ring_size*sizeof(struct ring_desc_ex)) >> 32), base + NvRegTxRingPhysAddrHigh);
 916                 }
 917         }
 918 }
 919
 920 static void free_rings(struct net_device *dev)
 921 {
 922         struct fe_priv *np = get_nvpriv(dev);
 923
 924         if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) {
 925                 if (np->rx_ring.orig)
 926                         pci_free_consistent(np->pci_dev, sizeof(struct ring_desc) * (np->rx_ring_size + np->tx_ring_size),
 927                                             np->rx_ring.orig, np->ring_addr);
 928         } else {
 929                 if (np->rx_ring.ex)
 930                         pci_free_consistent(np->pci_dev, sizeof(struct ring_desc_ex) * (np->rx_ring_size + np->tx_ring_size),
 931                                             np->rx_ring.ex, np->ring_addr);
 932         }
 933         if (np->rx_skb)
 934                 kfree(np->rx_skb);
 935         if (np->tx_skb)
 936                 kfree(np->tx_skb);
 937 }
 938
 939 static int using_multi_irqs(struct net_device *dev)
 940 {
 941         struct fe_priv *np = get_nvpriv(dev);
 942
 943         if (!(np->msi_flags & NV_MSI_X_ENABLED) ||
 944             ((np->msi_flags & NV_MSI_X_ENABLED) &&
 945              ((np->msi_flags & NV_MSI_X_VECTORS_MASK) == 0x1)))
 946                 return 0;
 947         else
 948                 return 1;
 949 }
 950
 951 static void nv_enable_irq(struct net_device *dev)
 952 {
 953         struct fe_priv *np = get_nvpriv(dev);
 954
 955         if (!using_multi_irqs(dev)) {
 956                 if (np->msi_flags & NV_MSI_X_ENABLED)
 957                         enable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_ALL].vector);
 958                 else
 959                         enable_irq(dev->irq);
 960         } else {
 961                 enable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector);
 962                 enable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_TX].vector);
 963                 enable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_OTHER].vector);
 964         }
 965 }
 966
 967 static void nv_disable_irq(struct net_device *dev)
 968 {
 969         struct fe_priv *np = get_nvpriv(dev);
 970
 971         if (!using_multi_irqs(dev)) {
 972                 if (np->msi_flags & NV_MSI_X_ENABLED)
 973                         disable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_ALL].vector);
 974                 else
 975                         disable_irq(dev->irq);
 976         } else {
 977                 disable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector);
 978                 disable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_TX].vector);
 979                 disable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_OTHER].vector);
 980         }
 981 }
 982
 983 /* In MSIX mode, a write to irqmask behaves as XOR */
 984 static void nv_enable_hw_interrupts(struct net_device *dev, u32 mask)
 985 {
 986         u8 __iomem *base = get_hwbase(dev);
 987
 988         writel(mask, base + NvRegIrqMask);
 989 }
 990
 991 static void nv_disable_hw_interrupts(struct net_device *dev, u32 mask)
 992 {
 993         struct fe_priv *np = get_nvpriv(dev);
 994         u8 __iomem *base = get_hwbase(dev);
 995
 996         if (np->msi_flags & NV_MSI_X_ENABLED) {
 997                 writel(mask, base + NvRegIrqMask);
 998         } else {
 999                 if (np->msi_flags & NV_MSI_ENABLED)
1000                         writel(0, base + NvRegMSIIrqMask);
1001                 writel(0, base + NvRegIrqMask);
1002         }
1003 }
1004
1005 #define MII_READ        (-1)
1006 /* mii_rw: read/write a register on the PHY.
1007  *
1008  * Caller must guarantee serialization
1009  */
1010 static int mii_rw(struct net_device *dev, int addr, int miireg, int value)
1011 {
1012         u8 __iomem *base = get_hwbase(dev);
1013         u32 reg;
1014         int retval;
1015
1016         writel(NVREG_MIISTAT_MASK, base + NvRegMIIStatus);
1017
1018         reg = readl(base + NvRegMIIControl);
1019         if (reg & NVREG_MIICTL_INUSE) {
1020                 writel(NVREG_MIICTL_INUSE, base + NvRegMIIControl);
1021                 udelay(NV_MIIBUSY_DELAY);
1022         }
1023
1024         reg = (addr << NVREG_MIICTL_ADDRSHIFT) | miireg;
1025         if (value != MII_READ) {
1026                 writel(value, base + NvRegMIIData);
1027                 reg |= NVREG_MIICTL_WRITE;
1028         }
1029         writel(reg, base + NvRegMIIControl);
1030
1031         if (reg_delay(dev, NvRegMIIControl, NVREG_MIICTL_INUSE, 0,
1032                         NV_MIIPHY_DELAY, NV_MIIPHY_DELAYMAX, NULL)) {
1033                 dprintk(KERN_DEBUG "%s: mii_rw of reg %d at PHY %d timed out.\n",
1034                                 dev->name, miireg, addr);
1035                 retval = -1;
1036         } else if (value != MII_READ) {
1037                 /* it was a write operation - fewer failures are detectable */
1038                 dprintk(KERN_DEBUG "%s: mii_rw wrote 0x%x to reg %d at PHY %d\n",
1039                                 dev->name, value, miireg, addr);
1040                 retval = 0;
1041         } else if (readl(base + NvRegMIIStatus) & NVREG_MIISTAT_ERROR) {
1042                 dprintk(KERN_DEBUG "%s: mii_rw of reg %d at PHY %d failed.\n",
1043                                 dev->name, miireg, addr);
1044                 retval = -1;
1045         } else {
1046                 retval = readl(base + NvRegMIIData);
1047                 dprintk(KERN_DEBUG "%s: mii_rw read from reg %d at PHY %d: 0x%x.\n",
1048                                 dev->name, miireg, addr, retval);
1049         }
1050
1051         return retval;
1052 }
1053
1054 static int phy_reset(struct net_device *dev, u32 bmcr_setup)
1055 {
1056         struct fe_priv *np = netdev_priv(dev);
1057         u32 miicontrol;
1058         unsigned int tries = 0;
1059
1060         miicontrol = BMCR_RESET | bmcr_setup;
1061         if (mii_rw(dev, np->phyaddr, MII_BMCR, miicontrol)) {
1062                 return -1;
1063         }
1064
1065         /* wait for 500ms */
1066         msleep(500);
1067
1068         /* must wait till reset is deasserted */
1069         while (miicontrol & BMCR_RESET) {
1070                 msleep(10);
1071                 miicontrol = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
1072                 /* FIXME: 100 tries seem excessive */
1073                 if (tries++ > 100)
1074                         return -1;
1075         }
1076         return 0;
1077 }
1078
1079 static int phy_init(struct net_device *dev)
1080 {
1081         struct fe_priv *np = get_nvpriv(dev);
1082         u8 __iomem *base = get_hwbase(dev);
1083         u32 phyinterface, phy_reserved, mii_status, mii_control, mii_control_1000,reg;
1084
1085         /* phy errata for E3016 phy */
1086         if (np->phy_model == PHY_MODEL_MARVELL_E3016) {
1087                 reg = mii_rw(dev, np->phyaddr, MII_NCONFIG, MII_READ);
1088                 reg &= ~PHY_MARVELL_E3016_INITMASK;
1089                 if (mii_rw(dev, np->phyaddr, MII_NCONFIG, reg)) {
1090                         printk(KERN_INFO "%s: phy write to errata reg failed.\n", pci_name(np->pci_dev));
1091                         return PHY_ERROR;
1092                 }
1093         }
1094
1095         /* set advertise register */
1096         reg = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ);
1097         reg |= (ADVERTISE_10HALF|ADVERTISE_10FULL|ADVERTISE_100HALF|ADVERTISE_100FULL|ADVERTISE_PAUSE_ASYM|ADVERTISE_PAUSE_CAP);
1098         if (mii_rw(dev, np->phyaddr, MII_ADVERTISE, reg)) {
1099                 printk(KERN_INFO "%s: phy write to advertise failed.\n", pci_name(np->pci_dev));
1100                 return PHY_ERROR;
1101         }
1102
1103         /* get phy interface type */
1104         phyinterface = readl(base + NvRegPhyInterface);
1105
1106         /* see if gigabit phy */
1107         mii_status = mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ);
1108         if (mii_status & PHY_GIGABIT) {
1109                 np->gigabit = PHY_GIGABIT;
1110                 mii_control_1000 = mii_rw(dev, np->phyaddr, MII_CTRL1000, MII_READ);
1111                 mii_control_1000 &= ~ADVERTISE_1000HALF;
1112                 if (phyinterface & PHY_RGMII)
1113                         mii_control_1000 |= ADVERTISE_1000FULL;
1114                 else
1115                         mii_control_1000 &= ~ADVERTISE_1000FULL;
1116
1117                 if (mii_rw(dev, np->phyaddr, MII_CTRL1000, mii_control_1000)) {
1118                         printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1119                         return PHY_ERROR;
1120                 }
1121         }
1122         else
1123                 np->gigabit = 0;
1124
1125         mii_control = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
1126         mii_control |= BMCR_ANENABLE;
1127
1128         /* reset the phy
1129          * (certain phys need bmcr to be setup with reset)
1130          */
1131         if (phy_reset(dev, mii_control)) {
1132                 printk(KERN_INFO "%s: phy reset failed\n", pci_name(np->pci_dev));
1133                 return PHY_ERROR;
1134         }
1135
1136         /* phy vendor specific configuration */
1137         if ((np->phy_oui == PHY_OUI_CICADA) && (phyinterface & PHY_RGMII) ) {
1138                 phy_reserved = mii_rw(dev, np->phyaddr, MII_RESV1, MII_READ);
1139                 phy_reserved &= ~(PHY_INIT1 | PHY_INIT2);
1140                 phy_reserved |= (PHY_INIT3 | PHY_INIT4);
1141                 if (mii_rw(dev, np->phyaddr, MII_RESV1, phy_reserved)) {
1142                         printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1143                         return PHY_ERROR;
1144                 }
1145                 phy_reserved = mii_rw(dev, np->phyaddr, MII_NCONFIG, MII_READ);
1146                 phy_reserved |= PHY_INIT5;
1147                 if (mii_rw(dev, np->phyaddr, MII_NCONFIG, phy_reserved)) {
1148                         printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1149                         return PHY_ERROR;
1150                 }
1151         }
1152         if (np->phy_oui == PHY_OUI_CICADA) {
1153                 phy_reserved = mii_rw(dev, np->phyaddr, MII_SREVISION, MII_READ);
1154                 phy_reserved |= PHY_INIT6;
1155                 if (mii_rw(dev, np->phyaddr, MII_SREVISION, phy_reserved)) {
1156                         printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1157                         return PHY_ERROR;
1158                 }
1159         }
1160         /* some phys clear out pause advertisment on reset, set it back */
1161         mii_rw(dev, np->phyaddr, MII_ADVERTISE, reg);
1162
1163         /* restart auto negotiation */
1164         mii_control = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
1165         mii_control |= (BMCR_ANRESTART | BMCR_ANENABLE);
1166         if (mii_rw(dev, np->phyaddr, MII_BMCR, mii_control)) {
1167                 return PHY_ERROR;
1168         }
1169
1170         return 0;
1171 }
1172
1173 static void nv_start_rx(struct net_device *dev)
1174 {
1175         struct fe_priv *np = netdev_priv(dev);
1176         u8 __iomem *base = get_hwbase(dev);
1177         u32 rx_ctrl = readl(base + NvRegReceiverControl);
1178
1179         dprintk(KERN_DEBUG "%s: nv_start_rx\n", dev->name);
1180         /* Already running? Stop it. */
1181         if ((readl(base + NvRegReceiverControl) & NVREG_RCVCTL_START) && !np->mac_in_use) {
1182                 rx_ctrl &= ~NVREG_RCVCTL_START;
1183                 writel(rx_ctrl, base + NvRegReceiverControl);
1184                 pci_push(base);
1185         }
1186         writel(np->linkspeed, base + NvRegLinkSpeed);
1187         pci_push(base);
1188         rx_ctrl |= NVREG_RCVCTL_START;
1189         if (np->mac_in_use)
1190                 rx_ctrl &= ~NVREG_RCVCTL_RX_PATH_EN;
1191         writel(rx_ctrl, base + NvRegReceiverControl);
1192         dprintk(KERN_DEBUG "%s: nv_start_rx to duplex %d, speed 0x%08x.\n",
1193                                 dev->name, np->duplex, np->linkspeed);
1194         pci_push(base);
1195 }
1196
1197 static void nv_stop_rx(struct net_device *dev)
1198 {
1199         struct fe_priv *np = netdev_priv(dev);
1200         u8 __iomem *base = get_hwbase(dev);
1201         u32 rx_ctrl = readl(base + NvRegReceiverControl);
1202
1203         dprintk(KERN_DEBUG "%s: nv_stop_rx\n", dev->name);
1204         if (!np->mac_in_use)
1205                 rx_ctrl &= ~NVREG_RCVCTL_START;
1206         else
1207                 rx_ctrl |= NVREG_RCVCTL_RX_PATH_EN;
1208         writel(rx_ctrl, base + NvRegReceiverControl);
1209         reg_delay(dev, NvRegReceiverStatus, NVREG_RCVSTAT_BUSY, 0,
1210                         NV_RXSTOP_DELAY1, NV_RXSTOP_DELAY1MAX,
1211                         KERN_INFO "nv_stop_rx: ReceiverStatus remained busy");
1212
1213         udelay(NV_RXSTOP_DELAY2);
1214         if (!np->mac_in_use)
1215                 writel(0, base + NvRegLinkSpeed);
1216 }
1217
1218 static void nv_start_tx(struct net_device *dev)
1219 {
1220         struct fe_priv *np = netdev_priv(dev);
1221         u8 __iomem *base = get_hwbase(dev);
1222         u32 tx_ctrl = readl(base + NvRegTransmitterControl);
1223
1224         dprintk(KERN_DEBUG "%s: nv_start_tx\n", dev->name);
1225         tx_ctrl |= NVREG_XMITCTL_START;
1226         if (np->mac_in_use)
1227                 tx_ctrl &= ~NVREG_XMITCTL_TX_PATH_EN;
1228         writel(tx_ctrl, base + NvRegTransmitterControl);
1229         pci_push(base);
1230 }
1231
1232 static void nv_stop_tx(struct net_device *dev)
1233 {
1234         struct fe_priv *np = netdev_priv(dev);
1235         u8 __iomem *base = get_hwbase(dev);
1236         u32 tx_ctrl = readl(base + NvRegTransmitterControl);
1237
1238         dprintk(KERN_DEBUG "%s: nv_stop_tx\n", dev->name);
1239         if (!np->mac_in_use)
1240                 tx_ctrl &= ~NVREG_XMITCTL_START;
1241         else
1242                 tx_ctrl |= NVREG_XMITCTL_TX_PATH_EN;
1243         writel(tx_ctrl, base + NvRegTransmitterControl);
1244         reg_delay(dev, NvRegTransmitterStatus, NVREG_XMITSTAT_BUSY, 0,
1245                         NV_TXSTOP_DELAY1, NV_TXSTOP_DELAY1MAX,
1246                         KERN_INFO "nv_stop_tx: TransmitterStatus remained busy");
1247
1248         udelay(NV_TXSTOP_DELAY2);
1249         if (!np->mac_in_use)
1250                 writel(readl(base + NvRegTransmitPoll) & NVREG_TRANSMITPOLL_MAC_ADDR_REV,
1251                        base + NvRegTransmitPoll);
1252 }
1253
1254 static void nv_txrx_reset(struct net_device *dev)
1255 {
1256         struct fe_priv *np = netdev_priv(dev);
1257         u8 __iomem *base = get_hwbase(dev);
1258
1259         dprintk(KERN_DEBUG "%s: nv_txrx_reset\n", dev->name);
1260         writel(NVREG_TXRXCTL_BIT2 | NVREG_TXRXCTL_RESET | np->txrxctl_bits, base + NvRegTxRxControl);
1261         pci_push(base);
1262         udelay(NV_TXRX_RESET_DELAY);
1263         writel(NVREG_TXRXCTL_BIT2 | np->txrxctl_bits, base + NvRegTxRxControl);
1264         pci_push(base);
1265 }
1266
1267 static void nv_mac_reset(struct net_device *dev)
1268 {
1269         struct fe_priv *np = netdev_priv(dev);
1270         u8 __iomem *base = get_hwbase(dev);
1271
1272         dprintk(KERN_DEBUG "%s: nv_mac_reset\n", dev->name);
1273         writel(NVREG_TXRXCTL_BIT2 | NVREG_TXRXCTL_RESET | np->txrxctl_bits, base + NvRegTxRxControl);
1274         pci_push(base);
1275         writel(NVREG_MAC_RESET_ASSERT, base + NvRegMacReset);
1276         pci_push(base);
1277         udelay(NV_MAC_RESET_DELAY);
1278         writel(0, base + NvRegMacReset);
1279         pci_push(base);
1280         udelay(NV_MAC_RESET_DELAY);
1281         writel(NVREG_TXRXCTL_BIT2 | np->txrxctl_bits, base + NvRegTxRxControl);
1282         pci_push(base);
1283 }
1284
1285 /*
1286  * nv_get_stats: dev->get_stats function
1287  * Get latest stats value from the nic.
1288  * Called with read_lock(&dev_base_lock) held for read -
1289  * only synchronized against unregister_netdevice.
1290  */
1291 static struct net_device_stats *nv_get_stats(struct net_device *dev)
1292 {
1293         struct fe_priv *np = netdev_priv(dev);
1294
1295         /* It seems that the nic always generates interrupts and doesn't
1296          * accumulate errors internally. Thus the current values in np->stats
1297          * are already up to date.
1298          */
1299         return &np->stats;
1300 }
1301
1302 /*
1303  * nv_alloc_rx: fill rx ring entries.
1304  * Return 1 if the allocations for the skbs failed and the
1305  * rx engine is without Available descriptors
1306  */
1307 static int nv_alloc_rx(struct net_device *dev)
1308 {
1309         struct fe_priv *np = netdev_priv(dev);
1310         union ring_type less_rx;
1311
1312         if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) {
1313                 less_rx.orig = np->get_rx.orig;
1314                 if (less_rx.orig-- == np->first_rx.orig)
1315                         less_rx.orig = np->last_rx.orig;
1316         } else {
1317                 less_rx.ex = np->get_rx.ex;
1318                 if (less_rx.ex-- == np->first_rx.ex)
1319                         less_rx.ex = np->last_rx.ex;
1320         }
1321
1322         while (1) {
1323                 struct sk_buff *skb;
1324
1325                 if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) {
1326                         if (np->put_rx.orig == less_rx.orig)
1327                                 break;
1328                 } else {
1329                         if (np->put_rx.ex == less_rx.ex)
1330                                 break;
1331                 }
1332
1333                 skb = dev_alloc_skb(np->rx_buf_sz + NV_RX_ALLOC_PAD);
1334                 if (skb) {
1335                         skb->dev = dev;
1336                         np->put_rx_ctx->skb = skb;
1337                         np->put_rx_ctx->dma = pci_map_single(np->pci_dev, skb->data,
1338                                                              skb->end-skb->data, PCI_DMA_FROMDEVICE);
1339                         np->put_rx_ctx->dma_len = skb->end-skb->data;
1340                         if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) {
1341                                 np->put_rx.orig->buf = cpu_to_le32(np->put_rx_ctx->dma);
1342                                 wmb();
1343                                 np->put_rx.orig->flaglen = cpu_to_le32(np->rx_buf_sz | NV_RX_AVAIL);
1344                                 if (np->put_rx.orig++ == np->last_rx.orig)
1345                                         np->put_rx.orig = np->first_rx.orig;
1346                         } else {
1347                                 np->put_rx.ex->bufhigh = cpu_to_le64(np->put_rx_ctx->dma) >> 32;
1348                                 np->put_rx.ex->buflow = cpu_to_le64(np->put_rx_ctx->dma) & 0x0FFFFFFFF;
1349                                 wmb();
1350                                 np->put_rx.ex->flaglen = cpu_to_le32(np->rx_buf_sz | NV_RX2_AVAIL);
1351                                 if (np->put_rx.ex++ == np->last_rx.ex)
1352                                         np->put_rx.ex = np->first_rx.ex;
1353                         }
1354                         if (np->put_rx_ctx++ == np->last_rx_ctx)
1355                                 np->put_rx_ctx = np->first_rx_ctx;
1356                 } else {
1357                         return 1;
1358                 }
1359         }
1360         return 0;
1361 }
1362
1363 /* If rx bufs are exhausted called after 50ms to attempt to refresh */
1364 #ifdef CONFIG_FORCEDETH_NAPI
1365 static void nv_do_rx_refill(unsigned long data)
1366 {
1367         struct net_device *dev = (struct net_device *) data;
1368
1369         /* Just reschedule NAPI rx processing */
1370         netif_rx_schedule(dev);
1371 }
1372 #else
1373 static void nv_do_rx_refill(unsigned long data)
1374 {
1375         struct net_device *dev = (struct net_device *) data;
1376         struct fe_priv *np = netdev_priv(dev);
1377
1378         if (!using_multi_irqs(dev)) {
1379                 if (np->msi_flags & NV_MSI_X_ENABLED)
1380                         disable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_ALL].vector);
1381                 else
1382                         disable_irq(dev->irq);
1383         } else {
1384                 disable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector);
1385         }
1386         if (nv_alloc_rx(dev)) {
1387                 spin_lock_irq(&np->lock);
1388                 if (!np->in_shutdown)
1389                         mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
1390                 spin_unlock_irq(&np->lock);
1391         }
1392         if (!using_multi_irqs(dev)) {
1393                 if (np->msi_flags & NV_MSI_X_ENABLED)
1394                         enable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_ALL].vector);
1395                 else
1396                         enable_irq(dev->irq);
1397         } else {
1398                 enable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector);
1399         }
1400 }
1401 #endif
1402
1403 static void nv_init_rx(struct net_device *dev)
1404 {
1405         struct fe_priv *np = netdev_priv(dev);
1406         int i;
1407         np->get_rx = np->put_rx = np->first_rx = np->rx_ring;
1408         if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2)
1409                 np->last_rx.orig = &np->rx_ring.orig[np->rx_ring_size-1];
1410         else
1411                 np->last_rx.ex = &np->rx_ring.ex[np->rx_ring_size-1];
1412         np->get_rx_ctx = np->put_rx_ctx = np->first_rx_ctx = np->rx_skb;
1413         np->last_rx_ctx = &np->rx_skb[np->rx_ring_size-1];
1414
1415         for (i = 0; i < np->rx_ring_size; i++) {
1416                 if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) {
1417                         np->rx_ring.orig[i].flaglen = 0;
1418                         np->rx_ring.orig[i].buf = 0;
1419                 } else {
1420                         np->rx_ring.ex[i].flaglen = 0;
1421                         np->rx_ring.ex[i].txvlan = 0;
1422                         np->rx_ring.ex[i].bufhigh = 0;
1423                         np->rx_ring.ex[i].buflow = 0;
1424                 }
1425                 np->rx_skb[i].skb = NULL;
1426                 np->rx_skb[i].dma = 0;
1427         }
1428 }
1429
1430 static void nv_init_tx(struct net_device *dev)
1431 {
1432         struct fe_priv *np = netdev_priv(dev);
1433         int i;
1434         np->get_tx = np->put_tx = np->first_tx = np->tx_ring;
1435         if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2)
1436                 np->last_tx.orig = &np->tx_ring.orig[np->tx_ring_size-1];
1437         else
1438                 np->last_tx.ex = &np->tx_ring.ex[np->tx_ring_size-1];
1439         np->get_tx_ctx = np->put_tx_ctx = np->first_tx_ctx = np->tx_skb;
1440         np->last_tx_ctx = &np->tx_skb[np->tx_ring_size-1];
1441
1442         for (i = 0; i < np->tx_ring_size; i++) {
1443                 if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) {
1444                         np->tx_ring.orig[i].flaglen = 0;
1445                         np->tx_ring.orig[i].buf = 0;
1446                 } else {
1447                         np->tx_ring.ex[i].flaglen = 0;
1448                         np->tx_ring.ex[i].txvlan = 0;
1449                         np->tx_ring.ex[i].bufhigh = 0;
1450                         np->tx_ring.ex[i].buflow = 0;
1451                 }
1452                 np->tx_skb[i].skb = NULL;
1453                 np->tx_skb[i].dma = 0;
1454         }
1455 }
1456
1457 static int nv_init_ring(struct net_device *dev)
1458 {
1459         nv_init_tx(dev);
1460         nv_init_rx(dev);
1461         return nv_alloc_rx(dev);
1462 }
1463
1464 static int nv_release_txskb(struct net_device *dev, struct nv_skb_map* tx_skb)
1465 {
1466         struct fe_priv *np = netdev_priv(dev);
1467
1468         if (tx_skb->dma) {
1469                 pci_unmap_page(np->pci_dev, tx_skb->dma,
1470                                tx_skb->dma_len,
1471                                PCI_DMA_TODEVICE);
1472                 tx_skb->dma = 0;
1473         }
1474         if (tx_skb->skb) {
1475                 dev_kfree_skb_any(tx_skb->skb);
1476                 tx_skb->skb = NULL;
1477                 return 1;
1478         } else {
1479                 return 0;
1480         }
1481 }
1482
1483 static void nv_drain_tx(struct net_device *dev)
1484 {
1485         struct fe_priv *np = netdev_priv(dev);
1486         unsigned int i;
1487
1488         for (i = 0; i < np->tx_ring_size; i++) {
1489                 if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) {
1490                         np->tx_ring.orig[i].flaglen = 0;
1491                         np->tx_ring.orig[i].buf = 0;
1492                 } else {
1493                         np->tx_ring.ex[i].flaglen = 0;
1494                         np->tx_ring.ex[i].txvlan = 0;
1495                         np->tx_ring.ex[i].bufhigh = 0;
1496                         np->tx_ring.ex[i].buflow = 0;
1497                 }
1498                 if (nv_release_txskb(dev, &np->tx_skb[i]))
1499                         np->stats.tx_dropped++;
1500         }
1501 }
1502
1503 static void nv_drain_rx(struct net_device *dev)
1504 {
1505         struct fe_priv *np = netdev_priv(dev);
1506         int i;
1507
1508         for (i = 0; i < np->rx_ring_size; i++) {
1509                 if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) {
1510                         np->rx_ring.orig[i].flaglen = 0;
1511                         np->rx_ring.orig[i].buf = 0;
1512                 } else {
1513                         np->rx_ring.ex[i].flaglen = 0;
1514                         np->rx_ring.ex[i].txvlan = 0;
1515                         np->rx_ring.ex[i].bufhigh = 0;
1516                         np->rx_ring.ex[i].buflow = 0;
1517                 }
1518                 wmb();
1519                 if (np->rx_skb[i].skb) {
1520                         pci_unmap_single(np->pci_dev, np->rx_skb[i].dma,
1521                                                 np->rx_skb[i].skb->end-np->rx_skb[i].skb->data,
1522                                                 PCI_DMA_FROMDEVICE);
1523                         dev_kfree_skb(np->rx_skb[i].skb);
1524                         np->rx_skb[i].skb = NULL;
1525                 }
1526         }
1527 }
1528
1529 static void drain_ring(struct net_device *dev)
1530 {
1531         nv_drain_tx(dev);
1532         nv_drain_rx(dev);
1533 }
1534
1535 static inline u32 nv_get_empty_tx_slots(struct fe_priv *np)
1536 {
1537         return (u32)(np->tx_ring_size - ((np->tx_ring_size + (np->put_tx_ctx - np->get_tx_ctx)) % np->tx_ring_size));
1538 }
1539
1540 /*
1541  * nv_start_xmit: dev->hard_start_xmit function
1542  * Called with netif_tx_lock held.
1543  */
1544 static int nv_start_xmit(struct sk_buff *skb, struct net_device *dev)
1545 {
1546         struct fe_priv *np = netdev_priv(dev);
1547         u32 tx_flags = 0;
1548         u32 tx_flags_extra = (np->desc_ver == DESC_VER_1 ? NV_TX_LASTPACKET : NV_TX2_LASTPACKET);
1549         unsigned int fragments = skb_shinfo(skb)->nr_frags;
1550         unsigned int i;
1551         u32 offset = 0;
1552         u32 bcnt;
1553         u32 size = skb->len-skb->data_len;
1554         u32 entries = (size >> NV_TX2_TSO_MAX_SHIFT) + ((size & (NV_TX2_TSO_MAX_SIZE-1)) ? 1 : 0);
1555         u32 empty_slots;
1556         u32 tx_flags_vlan = 0;
1557         union ring_type put_tx;
1558         union ring_type start_tx;
1559         union ring_type prev_tx;
1560         struct nv_skb_map* prev_tx_ctx;
1561
1562         /* add fragments to entries count */
1563         for (i = 0; i < fragments; i++) {
1564                 entries += (skb_shinfo(skb)->frags[i].size >> NV_TX2_TSO_MAX_SHIFT) +
1565                            ((skb_shinfo(skb)->frags[i].size & (NV_TX2_TSO_MAX_SIZE-1)) ? 1 : 0);
1566         }
1567
1568         empty_slots = nv_get_empty_tx_slots(np);
1569         if ((empty_slots - np->tx_limit_stop) <= entries) {
1570                 spin_lock_irq(&np->lock);
1571                 netif_stop_queue(dev);
1572                 spin_unlock_irq(&np->lock);
1573                 return NETDEV_TX_BUSY;
1574         }
1575
1576         if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2)
1577                 start_tx.orig = put_tx.orig = np->put_tx.orig;
1578         else
1579                 start_tx.ex = put_tx.ex = np->put_tx.ex;
1580
1581         /* setup the header buffer */
1582         do {
1583                 prev_tx = put_tx;
1584                 prev_tx_ctx = np->put_tx_ctx;
1585                 bcnt = (size > NV_TX2_TSO_MAX_SIZE) ? NV_TX2_TSO_MAX_SIZE : size;
1586                 np->put_tx_ctx->dma = pci_map_single(np->pci_dev, skb->data + offset, bcnt,
1587                                                 PCI_DMA_TODEVICE);
1588                 np->put_tx_ctx->dma_len = bcnt;
1589                 if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) {
1590                         put_tx.orig->buf = cpu_to_le32(np->put_tx_ctx->dma);
1591                         put_tx.orig->flaglen = cpu_to_le32((bcnt-1) | tx_flags);
1592                 } else {
1593                         put_tx.ex->bufhigh = cpu_to_le64(np->put_tx_ctx->dma) >> 32;
1594                         put_tx.ex->buflow = cpu_to_le64(np->put_tx_ctx->dma) & 0x0FFFFFFFF;
1595                         put_tx.ex->flaglen = cpu_to_le32((bcnt-1) | tx_flags);
1596                 }
1597                 tx_flags = np->tx_flags;
1598                 offset += bcnt;
1599                 size -= bcnt;
1600                 if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) {
1601                         if (put_tx.orig++ == np->last_tx.orig)
1602                                 put_tx.orig = np->first_tx.orig;
1603                 } else {
1604                         if (put_tx.ex++ == np->last_tx.ex)
1605                                 put_tx.ex = np->first_tx.ex;
1606                 }
1607                 if (np->put_tx_ctx++ == np->last_tx_ctx)
1608                         np->put_tx_ctx = np->first_tx_ctx;
1609         } while (size);
1610
1611         /* setup the fragments */
1612         for (i = 0; i < fragments; i++) {
1613                 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
1614                 u32 size = frag->size;
1615                 offset = 0;
1616
1617                 do {
1618                         prev_tx = put_tx;
1619                         prev_tx_ctx = np->put_tx_ctx;
1620                         bcnt = (size > NV_TX2_TSO_MAX_SIZE) ? NV_TX2_TSO_MAX_SIZE : size;
1621                         np->put_tx_ctx->dma = pci_map_page(np->pci_dev, frag->page, frag->page_offset+offset, bcnt,
1622                                                            PCI_DMA_TODEVICE);
1623                         np->put_tx_ctx->dma_len = bcnt;
1624
1625                         if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) {
1626                                 put_tx.orig->buf = cpu_to_le32(np->put_tx_ctx->dma);
1627                                 put_tx.orig->flaglen = cpu_to_le32((bcnt-1) | tx_flags);
1628                         } else {
1629                                 put_tx.ex->bufhigh = cpu_to_le64(np->put_tx_ctx->dma) >> 32;
1630                                 put_tx.ex->buflow = cpu_to_le64(np->put_tx_ctx->dma) & 0x0FFFFFFFF;
1631                                 put_tx.ex->flaglen = cpu_to_le32((bcnt-1) | tx_flags);
1632                         }
1633                         offset += bcnt;
1634                         size -= bcnt;
1635                         if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) {
1636                                 if (put_tx.orig++ == np->last_tx.orig)
1637                                         put_tx.orig = np->first_tx.orig;
1638                         } else {
1639                                 if (put_tx.ex++ == np->last_tx.ex)
1640                                         put_tx.ex = np->first_tx.ex;
1641                         }
1642                         if (np->put_tx_ctx++ == np->last_tx_ctx)
1643                                 np->put_tx_ctx = np->first_tx_ctx;
1644                 } while (size);
1645         }
1646
1647         /* set last fragment flag  */
1648         if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2)
1649                 prev_tx.orig->flaglen |= cpu_to_le32(tx_flags_extra);
1650         else
1651                 prev_tx.ex->flaglen |= cpu_to_le32(tx_flags_extra);
1652
1653         /* save skb in this slot's context area */
1654         prev_tx_ctx->skb = skb;
1655
1656         if (skb_is_gso(skb))
1657                 tx_flags_extra = NV_TX2_TSO | (skb_shinfo(skb)->gso_size << NV_TX2_TSO_SHIFT);
1658         else
1659                 tx_flags_extra = skb->ip_summed == CHECKSUM_PARTIAL ?
1660                          NV_TX2_CHECKSUM_L3 | NV_TX2_CHECKSUM_L4 : 0;
1661
1662         /* vlan tag */
1663         if (np->vlangrp && vlan_tx_tag_present(skb)) {
1664                 tx_flags_vlan = NV_TX3_VLAN_TAG_PRESENT | vlan_tx_tag_get(skb);
1665         }
1666
1667         spin_lock_irq(&np->lock);
1668
1669         /* set tx flags */
1670         if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) {
1671                 start_tx.orig->flaglen |= cpu_to_le32(tx_flags | tx_flags_extra);
1672                 np->put_tx.orig = put_tx.orig;
1673         } else {
1674                 start_tx.ex->txvlan = cpu_to_le32(tx_flags_vlan);
1675                 start_tx.ex->flaglen |= cpu_to_le32(tx_flags | tx_flags_extra);
1676                 np->put_tx.ex = put_tx.ex;
1677         }
1678
1679         spin_unlock_irq(&np->lock);
1680
1681         dprintk(KERN_DEBUG "%s: nv_start_xmit: entries %d queued for transmission. tx_flags_extra: %x\n",
1682                 dev->name, entries, tx_flags_extra);
1683         {
1684                 int j;
1685                 for (j=0; j<64; j++) {
1686                         if ((j%16) == 0)
1687                                 dprintk("\n%03x:", j);
1688                         dprintk(" %02x", ((unsigned char*)skb->data)[j]);
1689                 }
1690                 dprintk("\n");
1691         }
1692
1693         dev->trans_start = jiffies;
1694         writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
1695         pci_push(get_hwbase(dev));
1696         return NETDEV_TX_OK;
1697 }
1698
1699 /*
1700  * nv_tx_done: check for completed packets, release the skbs.
1701  *
1702  * Caller must own np->lock.
1703  */
1704 static void nv_tx_done(struct net_device *dev)
1705 {
1706         struct fe_priv *np = netdev_priv(dev);
1707         u32 flags;
1708         struct sk_buff *skb;
1709
1710         while (1) {
1711                 if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) {
1712                         if (np->get_tx.orig == np->put_tx.orig)
1713                                 break;
1714                         flags = le32_to_cpu(np->get_tx.orig->flaglen);
1715                 } else {
1716                         if (np->get_tx.ex == np->put_tx.ex)
1717                                 break;
1718                         flags = le32_to_cpu(np->get_tx.ex->flaglen);
1719                 }
1720
1721                 dprintk(KERN_DEBUG "%s: nv_tx_done: flags 0x%x.\n",
1722                                         dev->name, flags);
1723                 if (flags & NV_TX_VALID)
1724                         break;
1725                 if (np->desc_ver == DESC_VER_1) {
1726                         if (flags & NV_TX_LASTPACKET) {
1727                                 skb = np->get_tx_ctx->skb;
1728                                 if (flags & (NV_TX_RETRYERROR|NV_TX_CARRIERLOST|NV_TX_LATECOLLISION|
1729                                              NV_TX_UNDERFLOW|NV_TX_ERROR)) {
1730                                         if (flags & NV_TX_UNDERFLOW)
1731                                                 np->stats.tx_fifo_errors++;
1732                                         if (flags & NV_TX_CARRIERLOST)
1733                                                 np->stats.tx_carrier_errors++;
1734                                         np->stats.tx_errors++;
1735                                 } else {
1736                                         np->stats.tx_packets++;
1737                                         np->stats.tx_bytes += skb->len;
1738                                 }
1739                         }
1740                 } else {
1741                         if (flags & NV_TX2_LASTPACKET) {
1742                                 skb = np->get_tx_ctx->skb;
1743                                 if (flags & (NV_TX2_RETRYERROR|NV_TX2_CARRIERLOST|NV_TX2_LATECOLLISION|
1744                                              NV_TX2_UNDERFLOW|NV_TX2_ERROR)) {
1745                                         if (flags & NV_TX2_UNDERFLOW)
1746                                                 np->stats.tx_fifo_errors++;
1747                                         if (flags & NV_TX2_CARRIERLOST)
1748                                                 np->stats.tx_carrier_errors++;
1749                                         np->stats.tx_errors++;
1750                                 } else {
1751                                         np->stats.tx_packets++;
1752                                         np->stats.tx_bytes += skb->len;
1753                                 }
1754                         }
1755                 }
1756                 nv_release_txskb(dev, np->get_tx_ctx);
1757                 if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) {
1758                         if (np->get_tx.orig++ == np->last_tx.orig)
1759                                 np->get_tx.orig = np->first_tx.orig;
1760                 } else {
1761                         if (np->get_tx.ex++ == np->last_tx.ex)
1762                                 np->get_tx.ex = np->first_tx.ex;
1763                 }
1764                 if (np->get_tx_ctx++ == np->last_tx_ctx)
1765                         np->get_tx_ctx = np->first_tx_ctx;
1766         }
1767         if (nv_get_empty_tx_slots(np) > np->tx_limit_start)
1768                 netif_wake_queue(dev);
1769 }
1770
1771 /*
1772  * nv_tx_timeout: dev->tx_timeout function
1773  * Called with netif_tx_lock held.
1774  */
1775 static void nv_tx_timeout(struct net_device *dev)
1776 {
1777         struct fe_priv *np = netdev_priv(dev);
1778         u8 __iomem *base = get_hwbase(dev);
1779         u32 status;
1780
1781         if (np->msi_flags & NV_MSI_X_ENABLED)
1782                 status = readl(base + NvRegMSIXIrqStatus) & NVREG_IRQSTAT_MASK;
1783         else
1784                 status = readl(base + NvRegIrqStatus) & NVREG_IRQSTAT_MASK;
1785
1786         printk(KERN_INFO "%s: Got tx_timeout. irq: %08x\n", dev->name, status);
1787
1788         {
1789                 int i;
1790
1791                 printk(KERN_INFO "%s: Ring at %lx\n",
1792                        dev->name, (unsigned long)np->ring_addr);
1793                 printk(KERN_INFO "%s: Dumping tx registers\n", dev->name);
1794                 for (i=0;i<=np->register_size;i+= 32) {
1795                         printk(KERN_INFO "%3x: %08x %08x %08x %08x %08x %08x %08x %08x\n",
1796                                         i,
1797                                         readl(base + i + 0), readl(base + i + 4),
1798                                         readl(base + i + 8), readl(base + i + 12),
1799                                         readl(base + i + 16), readl(base + i + 20),
1800                                         readl(base + i + 24), readl(base + i + 28));
1801                 }
1802                 printk(KERN_INFO "%s: Dumping tx ring\n", dev->name);
1803                 for (i=0;i<np->tx_ring_size;i+= 4) {
1804                         if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) {
1805                                 printk(KERN_INFO "%03x: %08x %08x // %08x %08x // %08x %08x // %08x %08x\n",
1806                                        i,
1807                                        le32_to_cpu(np->tx_ring.orig[i].buf),
1808                                        le32_to_cpu(np->tx_ring.orig[i].flaglen),
1809                                        le32_to_cpu(np->tx_ring.orig[i+1].buf),
1810                                        le32_to_cpu(np->tx_ring.orig[i+1].flaglen),
1811                                        le32_to_cpu(np->tx_ring.orig[i+2].buf),
1812                                        le32_to_cpu(np->tx_ring.orig[i+2].flaglen),
1813                                        le32_to_cpu(np->tx_ring.orig[i+3].buf),
1814                                        le32_to_cpu(np->tx_ring.orig[i+3].flaglen));
1815                         } else {
1816                                 printk(KERN_INFO "%03x: %08x %08x %08x // %08x %08x %08x // %08x %08x %08x // %08x %08x %08x\n",
1817                                        i,
1818                                        le32_to_cpu(np->tx_ring.ex[i].bufhigh),
1819                                        le32_to_cpu(np->tx_ring.ex[i].buflow),
1820                                        le32_to_cpu(np->tx_ring.ex[i].flaglen),
1821                                        le32_to_cpu(np->tx_ring.ex[i+1].bufhigh),
1822                                        le32_to_cpu(np->tx_ring.ex[i+1].buflow),
1823                                        le32_to_cpu(np->tx_ring.ex[i+1].flaglen),
1824                                        le32_to_cpu(np->tx_ring.ex[i+2].bufhigh),
1825                                        le32_to_cpu(np->tx_ring.ex[i+2].buflow),
1826                                        le32_to_cpu(np->tx_ring.ex[i+2].flaglen),
1827                                        le32_to_cpu(np->tx_ring.ex[i+3].bufhigh),
1828                                        le32_to_cpu(np->tx_ring.ex[i+3].buflow),
1829                                        le32_to_cpu(np->tx_ring.ex[i+3].flaglen));
1830                         }
1831                 }
1832         }
1833
1834         spin_lock_irq(&np->lock);
1835
1836         /* 1) stop tx engine */
1837         nv_stop_tx(dev);
1838
1839         /* 2) check that the packets were not sent already: */
1840         nv_tx_done(dev);
1841
1842         /* 3) if there are dead entries: clear everything */
1843         if (np->get_tx_ctx != np->put_tx_ctx) {
1844                 printk(KERN_DEBUG "%s: tx_timeout: dead entries!\n", dev->name);
1845                 nv_drain_tx(dev);
1846                 nv_init_tx(dev);
1847                 setup_hw_rings(dev, NV_SETUP_TX_RING);
1848                 netif_wake_queue(dev);
1849         }
1850
1851         /* 4) restart tx engine */
1852         nv_start_tx(dev);
1853         spin_unlock_irq(&np->lock);
1854 }
1855
1856 /*
1857  * Called when the nic notices a mismatch between the actual data len on the
1858  * wire and the len indicated in the 802 header
1859  */
1860 static int nv_getlen(struct net_device *dev, void *packet, int datalen)
1861 {
1862         int hdrlen;     /* length of the 802 header */
1863         int protolen;   /* length as stored in the proto field */
1864
1865         /* 1) calculate len according to header */
1866         if ( ((struct vlan_ethhdr *)packet)->h_vlan_proto == htons(ETH_P_8021Q)) {
1867                 protolen = ntohs( ((struct vlan_ethhdr *)packet)->h_vlan_encapsulated_proto );
1868                 hdrlen = VLAN_HLEN;
1869         } else {
1870                 protolen = ntohs( ((struct ethhdr *)packet)->h_proto);
1871                 hdrlen = ETH_HLEN;
1872         }
1873         dprintk(KERN_DEBUG "%s: nv_getlen: datalen %d, protolen %d, hdrlen %d\n",
1874                                 dev->name, datalen, protolen, hdrlen);
1875         if (protolen > ETH_DATA_LEN)
1876                 return datalen; /* Value in proto field not a len, no checks possible */
1877
1878         protolen += hdrlen;
1879         /* consistency checks: */
1880         if (datalen > ETH_ZLEN) {
1881                 if (datalen >= protolen) {
1882                         /* more data on wire than in 802 header, trim of
1883                          * additional data.
1884                          */
1885                         dprintk(KERN_DEBUG "%s: nv_getlen: accepting %d bytes.\n",
1886                                         dev->name, protolen);
1887                         return protolen;
1888                 } else {
1889                         /* less data on wire than mentioned in header.
1890                          * Discard the packet.
1891                          */
1892                         dprintk(KERN_DEBUG "%s: nv_getlen: discarding long packet.\n",
1893                                         dev->name);
1894                         return -1;
1895                 }
1896         } else {
1897                 /* short packet. Accept only if 802 values are also short */
1898                 if (protolen > ETH_ZLEN) {
1899                         dprintk(KERN_DEBUG "%s: nv_getlen: discarding short packet.\n",
1900                                         dev->name);
1901                         return -1;
1902                 }
1903                 dprintk(KERN_DEBUG "%s: nv_getlen: accepting %d bytes.\n",
1904                                 dev->name, datalen);
1905                 return datalen;
1906         }
1907 }
1908
1909 static int nv_rx_process(struct net_device *dev, int limit)
1910 {
1911         struct fe_priv *np = netdev_priv(dev);
1912         u32 flags;
1913         u32 vlanflags = 0;
1914         int count;
1915
1916         for (count = 0; count < limit; ++count) {
1917                 struct sk_buff *skb;
1918                 int len;
1919
1920                 if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) {
1921                         if (np->get_rx.orig == np->put_rx.orig)
1922                                 break;  /* we scanned the whole ring - do not continue */
1923                         flags = le32_to_cpu(np->get_rx.orig->flaglen);
1924                         len = nv_descr_getlength(np->get_rx.orig, np->desc_ver);
1925                 } else {
1926                         if (np->get_rx.ex == np->put_rx.ex)
1927                                 break;  /* we scanned the whole ring - do not continue */
1928                         flags = le32_to_cpu(np->get_rx.ex->flaglen);
1929                         len = nv_descr_getlength_ex(np->get_rx.ex, np->desc_ver);
1930                         vlanflags = le32_to_cpu(np->get_rx.ex->buflow);
1931                 }
1932
1933                 dprintk(KERN_DEBUG "%s: nv_rx_process: flags 0x%x.\n",
1934                                         dev->name, flags);
1935
1936                 if (flags & NV_RX_AVAIL)
1937                         break;  /* still owned by hardware, */
1938
1939                 /*
1940                  * the packet is for us - immediately tear down the pci mapping.
1941                  * TODO: check if a prefetch of the first cacheline improves
1942                  * the performance.
1943                  */
1944                 pci_unmap_single(np->pci_dev, np->get_rx_ctx->dma,
1945                                 np->get_rx_ctx->dma_len,
1946                                 PCI_DMA_FROMDEVICE);
1947                 skb = np->get_rx_ctx->skb;
1948                 np->get_rx_ctx->skb = NULL;
1949
1950                 {
1951                         int j;
1952                         dprintk(KERN_DEBUG "Dumping packet (flags 0x%x).",flags);
1953                         for (j=0; j<64; j++) {
1954                                 if ((j%16) == 0)
1955                                         dprintk("\n%03x:", j);
1956                                 dprintk(" %02x", ((unsigned char*)skb->data)[j]);
1957                         }
1958                         dprintk("\n");
1959                 }
1960                 /* look at what we actually got: */
1961                 if (np->desc_ver == DESC_VER_1) {
1962                         if (!(flags & NV_RX_DESCRIPTORVALID)) {
1963                                 dev_kfree_skb(skb);
1964                                 goto next_pkt;
1965                         }
1966
1967                         if (flags & NV_RX_ERROR) {
1968                                 if (flags & NV_RX_MISSEDFRAME) {
1969                                         np->stats.rx_missed_errors++;
1970                                         np->stats.rx_errors++;
1971                                         dev_kfree_skb(skb);
1972                                         goto next_pkt;
1973                                 }
1974                                 if (flags & (NV_RX_ERROR1|NV_RX_ERROR2|NV_RX_ERROR3)) {
1975                                         np->stats.rx_errors++;
1976                                         dev_kfree_skb(skb);
1977                                         goto next_pkt;
1978                                 }
1979                                 if (flags & NV_RX_CRCERR) {
1980                                         np->stats.rx_crc_errors++;
1981                                         np->stats.rx_errors++;
1982                                         dev_kfree_skb(skb);
1983                                         goto next_pkt;
1984                                 }
1985                                 if (flags & NV_RX_OVERFLOW) {
1986                                         np->stats.rx_over_errors++;
1987                                         np->stats.rx_errors++;
1988                                         dev_kfree_skb(skb);
1989                                         goto next_pkt;
1990                                 }
1991                                 if (flags & NV_RX_ERROR4) {
1992                                         len = nv_getlen(dev, skb->data, len);
1993                                         if (len < 0) {
1994                                                 np->stats.rx_errors++;
1995                                                 dev_kfree_skb(skb);
1996                                                 goto next_pkt;
1997                                         }
1998                                 }
1999                                 /* framing errors are soft errors. */
2000                                 if (flags & NV_RX_FRAMINGERR) {
2001                                         if (flags & NV_RX_SUBSTRACT1) {
2002                                                 len--;
2003                                         }
2004                                 }
2005                         }
2006                 } else {
2007                         if (!(flags & NV_RX2_DESCRIPTORVALID)) {
2008                                 dev_kfree_skb(skb);
2009                                 goto next_pkt;
2010                         }
2011
2012                         if (flags & NV_RX2_ERROR) {
2013                                 if (flags & (NV_RX2_ERROR1|NV_RX2_ERROR2|NV_RX2_ERROR3)) {
2014                                         np->stats.rx_errors++;
2015                                         dev_kfree_skb(skb);
2016                                         goto next_pkt;
2017                                 }
2018                                 if (flags & NV_RX2_CRCERR) {
2019                                         np->stats.rx_crc_errors++;
2020                                         np->stats.rx_errors++;
2021                                         dev_kfree_skb(skb);
2022                                         goto next_pkt;
2023                                 }
2024                                 if (flags & NV_RX2_OVERFLOW) {
2025                                         np->stats.rx_over_errors++;
2026                                         np->stats.rx_errors++;
2027                                         dev_kfree_skb(skb);
2028                                         goto next_pkt;
2029                                 }
2030                                 if (flags & NV_RX2_ERROR4) {
2031                                         len = nv_getlen(dev, skb->data, len);
2032                                         if (len < 0) {
2033                                                 np->stats.rx_errors++;
2034                                                 dev_kfree_skb(skb);
2035                                                 goto next_pkt;
2036                                         }
2037                                 }
2038                                 /* framing errors are soft errors */
2039                                 if (flags & NV_RX2_FRAMINGERR) {
2040                                         if (flags & NV_RX2_SUBSTRACT1) {
2041                                                 len--;
2042                                         }
2043                                 }
2044                         }
2045                         if (np->rx_csum) {
2046                                 flags &= NV_RX2_CHECKSUMMASK;
2047                                 if (flags == NV_RX2_CHECKSUMOK1 ||
2048                                     flags == NV_RX2_CHECKSUMOK2 ||
2049                                     flags == NV_RX2_CHECKSUMOK3) {
2050                                         dprintk(KERN_DEBUG "%s: hw checksum hit!.\n", dev->name);
2051                                         skb->ip_summed = CHECKSUM_UNNECESSARY;
2052                                 } else {
2053                                         dprintk(KERN_DEBUG "%s: hwchecksum miss!.\n", dev->name);
2054                                 }
2055                         }
2056                 }
2057                 /* got a valid packet - forward it to the network core */
2058                 skb_put(skb, len);
2059                 skb->protocol = eth_type_trans(skb, dev);
2060                 dprintk(KERN_DEBUG "%s: nv_rx_process: %d bytes, proto %d accepted.\n",
2061                                         dev->name, len, skb->protocol);
2062 #ifdef CONFIG_FORCEDETH_NAPI
2063                 if (np->vlangrp && (vlanflags & NV_RX3_VLAN_TAG_PRESENT))
2064                         vlan_hwaccel_receive_skb(skb, np->vlangrp,
2065                                                  vlanflags & NV_RX3_VLAN_TAG_MASK);
2066                 else
2067                         netif_receive_skb(skb);
2068 #else
2069                 if (np->vlangrp && (vlanflags & NV_RX3_VLAN_TAG_PRESENT))
2070                         vlan_hwaccel_rx(skb, np->vlangrp,
2071                                         vlanflags & NV_RX3_VLAN_TAG_MASK);
2072                 else
2073                         netif_rx(skb);
2074 #endif
2075                 dev->last_rx = jiffies;
2076                 np->stats.rx_packets++;
2077                 np->stats.rx_bytes += len;
2078 next_pkt:
2079                 if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) {
2080                         if (np->get_rx.orig++ == np->last_rx.orig)
2081                                 np->get_rx.orig = np->first_rx.orig;
2082                 } else {
2083                         if (np->get_rx.ex++ == np->last_rx.ex)
2084                                 np->get_rx.ex = np->first_rx.ex;
2085                 }
2086                 if (np->get_rx_ctx++ == np->last_rx_ctx)
2087                         np->get_rx_ctx = np->first_rx_ctx;
2088         }
2089
2090         return count;
2091 }
2092
2093 static void set_bufsize(struct net_device *dev)
2094 {
2095         struct fe_priv *np = netdev_priv(dev);
2096
2097         if (dev->mtu <= ETH_DATA_LEN)
2098                 np->rx_buf_sz = ETH_DATA_LEN + NV_RX_HEADERS;
2099         else
2100                 np->rx_buf_sz = dev->mtu + NV_RX_HEADERS;
2101 }
2102
2103 /*
2104  * nv_change_mtu: dev->change_mtu function
2105  * Called with dev_base_lock held for read.
2106  */
2107 static int nv_change_mtu(struct net_device *dev, int new_mtu)
2108 {
2109         struct fe_priv *np = netdev_priv(dev);
2110         int old_mtu;
2111
2112         if (new_mtu < 64 || new_mtu > np->pkt_limit)
2113                 return -EINVAL;
2114
2115         old_mtu = dev->mtu;
2116         dev->mtu = new_mtu;
2117
2118         /* return early if the buffer sizes will not change */
2119         if (old_mtu <= ETH_DATA_LEN && new_mtu <= ETH_DATA_LEN)
2120                 return 0;
2121         if (old_mtu == new_mtu)
2122                 return 0;
2123
2124         /* synchronized against open : rtnl_lock() held by caller */
2125         if (netif_running(dev)) {
2126                 u8 __iomem *base = get_hwbase(dev);
2127                 /*
2128                  * It seems that the nic preloads valid ring entries into an
2129                  * internal buffer. The procedure for flushing everything is
2130                  * guessed, there is probably a simpler approach.
2131                  * Changing the MTU is a rare event, it shouldn't matter.
2132                  */
2133                 nv_disable_irq(dev);
2134                 netif_tx_lock_bh(dev);
2135                 spin_lock(&np->lock);
2136                 /* stop engines */
2137                 nv_stop_rx(dev);
2138                 nv_stop_tx(dev);
2139                 nv_txrx_reset(dev);
2140                 /* drain rx queue */
2141                 nv_drain_rx(dev);
2142                 nv_drain_tx(dev);
2143                 /* reinit driver view of the rx queue */
2144                 set_bufsize(dev);
2145                 if (nv_init_ring(dev)) {
2146                         if (!np->in_shutdown)
2147                                 mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
2148                 }
2149                 /* reinit nic view of the rx queue */
2150                 writel(np->rx_buf_sz, base + NvRegOffloadConfig);
2151                 setup_hw_rings(dev, NV_SETUP_RX_RING | NV_SETUP_TX_RING);
2152                 writel( ((np->rx_ring_size-1) << NVREG_RINGSZ_RXSHIFT) + ((np->tx_ring_size-1) << NVREG_RINGSZ_TXSHIFT),
2153                         base + NvRegRingSizes);
2154                 pci_push(base);
2155                 writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
2156                 pci_push(base);
2157
2158                 /* restart rx engine */
2159                 nv_start_rx(dev);
2160                 nv_start_tx(dev);
2161                 spin_unlock(&np->lock);
2162                 netif_tx_unlock_bh(dev);
2163                 nv_enable_irq(dev);
2164         }
2165         return 0;
2166 }
2167
2168 static void nv_copy_mac_to_hw(struct net_device *dev)
2169 {
2170         u8 __iomem *base = get_hwbase(dev);
2171         u32 mac[2];
2172
2173         mac[0] = (dev->dev_addr[0] << 0) + (dev->dev_addr[1] << 8) +
2174                         (dev->dev_addr[2] << 16) + (dev->dev_addr[3] << 24);
2175         mac[1] = (dev->dev_addr[4] << 0) + (dev->dev_addr[5] << 8);
2176
2177         writel(mac[0], base + NvRegMacAddrA);
2178         writel(mac[1], base + NvRegMacAddrB);
2179 }
2180
2181 /*
2182  * nv_set_mac_address: dev->set_mac_address function
2183  * Called with rtnl_lock() held.
2184  */
2185 static int nv_set_mac_address(struct net_device *dev, void *addr)
2186 {
2187         struct fe_priv *np = netdev_priv(dev);
2188         struct sockaddr *macaddr = (struct sockaddr*)addr;
2189
2190         if (!is_valid_ether_addr(macaddr->sa_data))
2191                 return -EADDRNOTAVAIL;
2192
2193         /* synchronized against open : rtnl_lock() held by caller */
2194         memcpy(dev->dev_addr, macaddr->sa_data, ETH_ALEN);
2195
2196         if (netif_running(dev)) {
2197                 netif_tx_lock_bh(dev);
2198                 spin_lock_irq(&np->lock);
2199
2200                 /* stop rx engine */
2201                 nv_stop_rx(dev);
2202
2203                 /* set mac address */
2204                 nv_copy_mac_to_hw(dev);
2205
2206                 /* restart rx engine */
2207                 nv_start_rx(dev);
2208                 spin_unlock_irq(&np->lock);
2209                 netif_tx_unlock_bh(dev);
2210         } else {
2211                 nv_copy_mac_to_hw(dev);
2212         }
2213         return 0;
2214 }
2215
2216 /*
2217  * nv_set_multicast: dev->set_multicast function
2218  * Called with netif_tx_lock held.
2219  */
2220 static void nv_set_multicast(struct net_device *dev)
2221 {
2222         struct fe_priv *np = netdev_priv(dev);
2223         u8 __iomem *base = get_hwbase(dev);
2224         u32 addr[2];
2225         u32 mask[2];
2226         u32 pff = readl(base + NvRegPacketFilterFlags) & NVREG_PFF_PAUSE_RX;
2227
2228         memset(addr, 0, sizeof(addr));
2229         memset(mask, 0, sizeof(mask));
2230
2231         if (dev->flags & IFF_PROMISC) {
2232                 pff |= NVREG_PFF_PROMISC;
2233         } else {
2234                 pff |= NVREG_PFF_MYADDR;
2235
2236                 if (dev->flags & IFF_ALLMULTI || dev->mc_list) {
2237                         u32 alwaysOff[2];
2238                         u32 alwaysOn[2];
2239
2240                         alwaysOn[0] = alwaysOn[1] = alwaysOff[0] = alwaysOff[1] = 0xffffffff;
2241                         if (dev->flags & IFF_ALLMULTI) {
2242                                 alwaysOn[0] = alwaysOn[1] = alwaysOff[0] = alwaysOff[1] = 0;
2243                         } else {
2244                                 struct dev_mc_list *walk;
2245
2246                                 walk = dev->mc_list;
2247                                 while (walk != NULL) {
2248                                         u32 a, b;
2249                                         a = le32_to_cpu(*(u32 *) walk->dmi_addr);
2250                                         b = le16_to_cpu(*(u16 *) (&walk->dmi_addr[4]));
2251                                         alwaysOn[0] &= a;
2252                                         alwaysOff[0] &= ~a;
2253                                         alwaysOn[1] &= b;
2254                                         alwaysOff[1] &= ~b;
2255                                         walk = walk->next;
2256                                 }
2257                         }
2258                         addr[0] = alwaysOn[0];
2259                         addr[1] = alwaysOn[1];
2260                         mask[0] = alwaysOn[0] | alwaysOff[0];
2261                         mask[1] = alwaysOn[1] | alwaysOff[1];
2262                 }
2263         }
2264         addr[0] |= NVREG_MCASTADDRA_FORCE;
2265         pff |= NVREG_PFF_ALWAYS;
2266         spin_lock_irq(&np->lock);
2267         nv_stop_rx(dev);
2268         writel(addr[0], base + NvRegMulticastAddrA);
2269         writel(addr[1], base + NvRegMulticastAddrB);
2270         writel(mask[0], base + NvRegMulticastMaskA);
2271         writel(mask[1], base + NvRegMulticastMaskB);
2272         writel(pff, base + NvRegPacketFilterFlags);
2273         dprintk(KERN_INFO "%s: reconfiguration for multicast lists.\n",
2274                 dev->name);
2275         nv_start_rx(dev);
2276         spin_unlock_irq(&np->lock);
2277 }
2278
2279 static void nv_update_pause(struct net_device *dev, u32 pause_flags)
2280 {
2281         struct fe_priv *np = netdev_priv(dev);
2282         u8 __iomem *base = get_hwbase(dev);
2283
2284         np->pause_flags &= ~(NV_PAUSEFRAME_TX_ENABLE | NV_PAUSEFRAME_RX_ENABLE);
2285
2286         if (np->pause_flags & NV_PAUSEFRAME_RX_CAPABLE) {
2287                 u32 pff = readl(base + NvRegPacketFilterFlags) & ~NVREG_PFF_PAUSE_RX;
2288                 if (pause_flags & NV_PAUSEFRAME_RX_ENABLE) {
2289                         writel(pff|NVREG_PFF_PAUSE_RX, base + NvRegPacketFilterFlags);
2290                         np->pause_flags |= NV_PAUSEFRAME_RX_ENABLE;
2291                 } else {
2292                         writel(pff, base + NvRegPacketFilterFlags);
2293                 }
2294         }
2295         if (np->pause_flags & NV_PAUSEFRAME_TX_CAPABLE) {
2296                 u32 regmisc = readl(base + NvRegMisc1) & ~NVREG_MISC1_PAUSE_TX;
2297                 if (pause_flags & NV_PAUSEFRAME_TX_ENABLE) {
2298                         writel(NVREG_TX_PAUSEFRAME_ENABLE,  base + NvRegTxPauseFrame);
2299                         writel(regmisc|NVREG_MISC1_PAUSE_TX, base + NvRegMisc1);
2300                         np->pause_flags |= NV_PAUSEFRAME_TX_ENABLE;
2301                 } else {
2302                         writel(NVREG_TX_PAUSEFRAME_DISABLE,  base + NvRegTxPauseFrame);
2303                         writel(regmisc, base + NvRegMisc1);
2304                 }
2305         }
2306 }
2307
2308 /**
2309  * nv_update_linkspeed: Setup the MAC according to the link partner
2310  * @dev: Network device to be configured
2311  *
2312  * The function queries the PHY and checks if there is a link partner.
2313  * If yes, then it sets up the MAC accordingly. Otherwise, the MAC is
2314  * set to 10 MBit HD.
2315  *
2316  * The function returns 0 if there is no link partner and 1 if there is
2317  * a good link partner.
2318  */
2319 static int nv_update_linkspeed(struct net_device *dev)
2320 {
2321         struct fe_priv *np = netdev_priv(dev);
2322         u8 __iomem *base = get_hwbase(dev);
2323         int adv = 0;
2324         int lpa = 0;
2325         int adv_lpa, adv_pause, lpa_pause;
2326         int newls = np->linkspeed;
2327         int newdup = np->duplex;
2328         int mii_status;
2329         int retval = 0;
2330         u32 control_1000, status_1000, phyreg, pause_flags, txreg;
2331
2332         /* BMSR_LSTATUS is latched, read it twice:
2333          * we want the current value.
2334          */
2335         mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ);
2336         mii_status = mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ);
2337
2338         if (!(mii_status & BMSR_LSTATUS)) {
2339                 dprintk(KERN_DEBUG "%s: no link detected by phy - falling back to 10HD.\n",
2340                                 dev->name);
2341                 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
2342                 newdup = 0;
2343                 retval = 0;
2344                 goto set_speed;
2345         }
2346
2347         if (np->autoneg == 0) {
2348                 dprintk(KERN_DEBUG "%s: nv_update_linkspeed: autoneg off, PHY set to 0x%04x.\n",
2349                                 dev->name, np->fixed_mode);
2350                 if (np->fixed_mode & LPA_100FULL) {
2351                         newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_100;
2352                         newdup = 1;
2353                 } else if (np->fixed_mode & LPA_100HALF) {
2354                         newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_100;
2355                         newdup = 0;
2356                 } else if (np->fixed_mode & LPA_10FULL) {
2357                         newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
2358                         newdup = 1;
2359                 } else {
2360                         newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
2361                         newdup = 0;
2362                 }
2363                 retval = 1;
2364                 goto set_speed;
2365         }
2366         /* check auto negotiation is complete */
2367         if (!(mii_status & BMSR_ANEGCOMPLETE)) {
2368                 /* still in autonegotiation - configure nic for 10 MBit HD and wait. */
2369                 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
2370                 newdup = 0;
2371                 retval = 0;
2372                 dprintk(KERN_DEBUG "%s: autoneg not completed - falling back to 10HD.\n", dev->name);
2373                 goto set_speed;
2374         }
2375
2376         adv = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ);
2377         lpa = mii_rw(dev, np->phyaddr, MII_LPA, MII_READ);
2378         dprintk(KERN_DEBUG "%s: nv_update_linkspeed: PHY advertises 0x%04x, lpa 0x%04x.\n",
2379                                 dev->name, adv, lpa);
2380
2381         retval = 1;
2382         if (np->gigabit == PHY_GIGABIT) {
2383                 control_1000 = mii_rw(dev, np->phyaddr, MII_CTRL1000, MII_READ);
2384                 status_1000 = mii_rw(dev, np->phyaddr, MII_STAT1000, MII_READ);
2385
2386                 if ((control_1000 & ADVERTISE_1000FULL) &&
2387                         (status_1000 & LPA_1000FULL)) {
2388                         dprintk(KERN_DEBUG "%s: nv_update_linkspeed: GBit ethernet detected.\n",
2389                                 dev->name);
2390                         newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_1000;
2391                         newdup = 1;
2392                         goto set_speed;
2393                 }
2394         }
2395
2396         /* FIXME: handle parallel detection properly */
2397         adv_lpa = lpa & adv;
2398         if (adv_lpa & LPA_100FULL) {
2399                 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_100;
2400                 newdup = 1;
2401         } else if (adv_lpa & LPA_100HALF) {
2402                 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_100;
2403                 newdup = 0;
2404         } else if (adv_lpa & LPA_10FULL) {
2405                 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
2406                 newdup = 1;
2407         } else if (adv_lpa & LPA_10HALF) {
2408                 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
2409                 newdup = 0;
2410         } else {
2411                 dprintk(KERN_DEBUG "%s: bad ability %04x - falling back to 10HD.\n", dev->name, adv_lpa);
2412                 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
2413                 newdup = 0;
2414         }
2415
2416 set_speed:
2417         if (np->duplex == newdup && np->linkspeed == newls)
2418                 return retval;
2419
2420         dprintk(KERN_INFO "%s: changing link setting from %d/%d to %d/%d.\n",
2421                         dev->name, np->linkspeed, np->duplex, newls, newdup);
2422
2423         np->duplex = newdup;
2424         np->linkspeed = newls;
2425
2426         if (np->gigabit == PHY_GIGABIT) {
2427                 phyreg = readl(base + NvRegRandomSeed);
2428                 phyreg &= ~(0x3FF00);
2429                 if ((np->linkspeed & 0xFFF) == NVREG_LINKSPEED_10)
2430                         phyreg |= NVREG_RNDSEED_FORCE3;
2431                 else if ((np->linkspeed & 0xFFF) == NVREG_LINKSPEED_100)
2432                         phyreg |= NVREG_RNDSEED_FORCE2;
2433                 else if ((np->linkspeed & 0xFFF) == NVREG_LINKSPEED_1000)
2434                         phyreg |= NVREG_RNDSEED_FORCE;
2435                 writel(phyreg, base + NvRegRandomSeed);
2436         }
2437
2438         phyreg = readl(base + NvRegPhyInterface);
2439         phyreg &= ~(PHY_HALF|PHY_100|PHY_1000);
2440         if (np->duplex == 0)
2441                 phyreg |= PHY_HALF;
2442         if ((np->linkspeed & NVREG_LINKSPEED_MASK) == NVREG_LINKSPEED_100)
2443                 phyreg |= PHY_100;
2444         else if ((np->linkspeed & NVREG_LINKSPEED_MASK) == NVREG_LINKSPEED_1000)
2445                 phyreg |= PHY_1000;
2446         writel(phyreg, base + NvRegPhyInterface);
2447
2448         if (phyreg & PHY_RGMII) {
2449                 if ((np->linkspeed & NVREG_LINKSPEED_MASK) == NVREG_LINKSPEED_1000)
2450                         txreg = NVREG_TX_DEFERRAL_RGMII_1000;
2451                 else
2452                         txreg = NVREG_TX_DEFERRAL_RGMII_10_100;
2453         } else {
2454                 txreg = NVREG_TX_DEFERRAL_DEFAULT;
2455         }
2456         writel(txreg, base + NvRegTxDeferral);
2457
2458         if (np->desc_ver == DESC_VER_1) {
2459                 txreg = NVREG_TX_WM_DESC1_DEFAULT;
2460         } else {
2461                 if ((np->linkspeed & NVREG_LINKSPEED_MASK) == NVREG_LINKSPEED_1000)
2462                         txreg = NVREG_TX_WM_DESC2_3_1000;
2463                 else
2464                         txreg = NVREG_TX_WM_DESC2_3_DEFAULT;
2465         }
2466         writel(txreg, base + NvRegTxWatermark);
2467
2468         writel(NVREG_MISC1_FORCE | ( np->duplex ? 0 : NVREG_MISC1_HD),
2469                 base + NvRegMisc1);
2470         pci_push(base);
2471         writel(np->linkspeed, base + NvRegLinkSpeed);
2472         pci_push(base);
2473
2474         pause_flags = 0;
2475         /* setup pause frame */
2476         if (np->duplex != 0) {
2477                 if (np->autoneg && np->pause_flags & NV_PAUSEFRAME_AUTONEG) {
2478                         adv_pause = adv & (ADVERTISE_PAUSE_CAP| ADVERTISE_PAUSE_ASYM);
2479                         lpa_pause = lpa & (LPA_PAUSE_CAP| LPA_PAUSE_ASYM);
2480
2481                         switch (adv_pause) {
2482                         case ADVERTISE_PAUSE_CAP:
2483                                 if (lpa_pause & LPA_PAUSE_CAP) {
2484                                         pause_flags |= NV_PAUSEFRAME_RX_ENABLE;
2485                                         if (np->pause_flags & NV_PAUSEFRAME_TX_REQ)
2486                                                 pause_flags |= NV_PAUSEFRAME_TX_ENABLE;
2487                                 }
2488                                 break;
2489                         case ADVERTISE_PAUSE_ASYM:
2490                                 if (lpa_pause == (LPA_PAUSE_CAP| LPA_PAUSE_ASYM))
2491                                 {
2492                                         pause_flags |= NV_PAUSEFRAME_TX_ENABLE;
2493                                 }
2494                                 break;
2495                         case ADVERTISE_PAUSE_CAP| ADVERTISE_PAUSE_ASYM:
2496                                 if (lpa_pause & LPA_PAUSE_CAP)
2497                                 {
2498                                         pause_flags |=  NV_PAUSEFRAME_RX_ENABLE;
2499                                         if (np->pause_flags & NV_PAUSEFRAME_TX_REQ)
2500                                                 pause_flags |= NV_PAUSEFRAME_TX_ENABLE;
2501                                 }
2502                                 if (lpa_pause == LPA_PAUSE_ASYM)
2503                                 {
2504                                         pause_flags |= NV_PAUSEFRAME_RX_ENABLE;
2505                                 }
2506                                 break;
2507                         }
2508                 } else {
2509                         pause_flags = np->pause_flags;
2510                 }
2511         }
2512         nv_update_pause(dev, pause_flags);
2513
2514         return retval;
2515 }
2516
2517 static void nv_linkchange(struct net_device *dev)
2518 {
2519         if (nv_update_linkspeed(dev)) {
2520                 if (!netif_carrier_ok(dev)) {
2521                         netif_carrier_on(dev);
2522                         printk(KERN_INFO "%s: link up.\n", dev->name);
2523                         nv_start_rx(dev);
2524                 }
2525         } else {
2526                 if (netif_carrier_ok(dev)) {
2527                         netif_carrier_off(dev);
2528                         printk(KERN_INFO "%s: link down.\n", dev->name);
2529                         nv_stop_rx(dev);
2530                 }
2531         }
2532 }
2533
2534 static void nv_link_irq(struct net_device *dev)
2535 {
2536         u8 __iomem *base = get_hwbase(dev);
2537         u32 miistat;
2538
2539         miistat = readl(base + NvRegMIIStatus);
2540         writel(NVREG_MIISTAT_MASK, base + NvRegMIIStatus);
2541         dprintk(KERN_INFO "%s: link change irq, status 0x%x.\n", dev->name, miistat);
2542
2543         if (miistat & (NVREG_MIISTAT_LINKCHANGE))
2544                 nv_linkchange(dev);
2545         dprintk(KERN_DEBUG "%s: link change notification done.\n", dev->name);
2546 }
2547
2548 static irqreturn_t nv_nic_irq(int foo, void *data)
2549 {
2550         struct net_device *dev = (struct net_device *) data;
2551         struct fe_priv *np = netdev_priv(dev);
2552         u8 __iomem *base = get_hwbase(dev);
2553         u32 events;
2554         int i;
2555
2556         dprintk(KERN_DEBUG "%s: nv_nic_irq\n", dev->name);
2557
2558         for (i=0; ; i++) {
2559                 if (!(np->msi_flags & NV_MSI_X_ENABLED)) {
2560                         events = readl(base + NvRegIrqStatus) & NVREG_IRQSTAT_MASK;
2561                         writel(NVREG_IRQSTAT_MASK, base + NvRegIrqStatus);
2562                 } else {
2563                         events = readl(base + NvRegMSIXIrqStatus) & NVREG_IRQSTAT_MASK;
2564                         writel(NVREG_IRQSTAT_MASK, base + NvRegMSIXIrqStatus);
2565                 }
2566                 pci_push(base);
2567                 dprintk(KERN_DEBUG "%s: irq: %08x\n", dev->name, events);
2568                 if (!(events & np->irqmask))
2569                         break;
2570
2571                 spin_lock(&np->lock);
2572                 nv_tx_done(dev);
2573                 spin_unlock(&np->lock);
2574
2575                 if (events & NVREG_IRQ_LINK) {
2576                         spin_lock(&np->lock);
2577                         nv_link_irq(dev);
2578                         spin_unlock(&np->lock);
2579                 }
2580                 if (np->need_linktimer && time_after(jiffies, np->link_timeout)) {
2581                         spin_lock(&np->lock);
2582                         nv_linkchange(dev);
2583                         spin_unlock(&np->lock);
2584                         np->link_timeout = jiffies + LINK_TIMEOUT;
2585                 }
2586                 if (events & (NVREG_IRQ_TX_ERR)) {
2587                         dprintk(KERN_DEBUG "%s: received irq with events 0x%x. Probably TX fail.\n",
2588                                                 dev->name, events);
2589                 }
2590                 if (events & (NVREG_IRQ_UNKNOWN)) {
2591                         printk(KERN_DEBUG "%s: received irq with unknown events 0x%x. Please report\n",
2592                                                 dev->name, events);
2593                 }
2594                 if (unlikely(events & NVREG_IRQ_RECOVER_ERROR)) {
2595                         spin_lock(&np->lock);
2596                         /* disable interrupts on the nic */
2597                         if (!(np->msi_flags & NV_MSI_X_ENABLED))
2598                                 writel(0, base + NvRegIrqMask);
2599                         else
2600                                 writel(np->irqmask, base + NvRegIrqMask);
2601                         pci_push(base);
2602
2603                         if (!np->in_shutdown) {
2604                                 np->nic_poll_irq = np->irqmask;
2605                                 np->recover_error = 1;
2606                                 mod_timer(&np->nic_poll, jiffies + POLL_WAIT);
2607                         }
2608                         spin_unlock(&np->lock);
2609                         break;
2610                 }
2611 #ifdef CONFIG_FORCEDETH_NAPI
2612                 if (events & NVREG_IRQ_RX_ALL) {
2613                         netif_rx_schedule(dev);
2614
2615                         /* Disable furthur receive irq's */
2616                         spin_lock(&np->lock);
2617                         np->irqmask &= ~NVREG_IRQ_RX_ALL;
2618
2619                         if (np->msi_flags & NV_MSI_X_ENABLED)
2620                                 writel(NVREG_IRQ_RX_ALL, base + NvRegIrqMask);
2621                         else
2622                                 writel(np->irqmask, base + NvRegIrqMask);
2623                         spin_unlock(&np->lock);
2624                 }
2625 #else
2626                 nv_rx_process(dev, dev->weight);
2627                 if (nv_alloc_rx(dev)) {
2628                         spin_lock(&np->lock);
2629                         if (!np->in_shutdown)
2630                                 mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
2631                         spin_unlock(&np->lock);
2632                 }
2633 #endif
2634                 if (i > max_interrupt_work) {
2635                         spin_lock(&np->lock);
2636                         /* disable interrupts on the nic */
2637                         if (!(np->msi_flags & NV_MSI_X_ENABLED))
2638                                 writel(0, base + NvRegIrqMask);
2639                         else
2640                                 writel(np->irqmask, base + NvRegIrqMask);
2641                         pci_push(base);
2642
2643                         if (!np->in_shutdown) {
2644                                 np->nic_poll_irq = np->irqmask;
2645                                 mod_timer(&np->nic_poll, jiffies + POLL_WAIT);
2646                         }
2647                         printk(KERN_DEBUG "%s: too many iterations (%d) in nv_nic_irq.\n", dev->name, i);
2648                         spin_unlock(&np->lock);
2649                         break;
2650                 }
2651
2652         }
2653         dprintk(KERN_DEBUG "%s: nv_nic_irq completed\n", dev->name);
2654
2655         return IRQ_RETVAL(i);
2656 }
2657
2658 static irqreturn_t nv_nic_irq_tx(int foo, void *data)
2659 {
2660         struct net_device *dev = (struct net_device *) data;
2661         struct fe_priv *np = netdev_priv(dev);
2662         u8 __iomem *base = get_hwbase(dev);
2663         u32 events;
2664         int i;
2665         unsigned long flags;
2666
2667         dprintk(KERN_DEBUG "%s: nv_nic_irq_tx\n", dev->name);
2668
2669         for (i=0; ; i++) {
2670                 events = readl(base + NvRegMSIXIrqStatus) & NVREG_IRQ_TX_ALL;
2671                 writel(NVREG_IRQ_TX_ALL, base + NvRegMSIXIrqStatus);
2672                 pci_push(base);
2673                 dprintk(KERN_DEBUG "%s: tx irq: %08x\n", dev->name, events);
2674                 if (!(events & np->irqmask))
2675                         break;
2676
2677                 spin_lock_irqsave(&np->lock, flags);
2678                 nv_tx_done(dev);
2679                 spin_unlock_irqrestore(&np->lock, flags);
2680
2681                 if (events & (NVREG_IRQ_TX_ERR)) {
2682                         dprintk(KERN_DEBUG "%s: received irq with events 0x%x. Probably TX fail.\n",
2683                                                 dev->name, events);
2684                 }
2685                 if (i > max_interrupt_work) {
2686                         spin_lock_irqsave(&np->lock, flags);
2687                         /* disable interrupts on the nic */
2688                         writel(NVREG_IRQ_TX_ALL, base + NvRegIrqMask);
2689                         pci_push(base);
2690
2691                         if (!np->in_shutdown) {
2692                                 np->nic_poll_irq |= NVREG_IRQ_TX_ALL;
2693                                 mod_timer(&np->nic_poll, jiffies + POLL_WAIT);
2694                         }
2695                         printk(KERN_DEBUG "%s: too many iterations (%d) in nv_nic_irq_tx.\n", dev->name, i);
2696                         spin_unlock_irqrestore(&np->lock, flags);
2697                         break;
2698                 }
2699
2700         }
2701         dprintk(KERN_DEBUG "%s: nv_nic_irq_tx completed\n", dev->name);
2702
2703         return IRQ_RETVAL(i);
2704 }
2705
2706 #ifdef CONFIG_FORCEDETH_NAPI
2707 static int nv_napi_poll(struct net_device *dev, int *budget)
2708 {
2709         int pkts, limit = min(*budget, dev->quota);
2710         struct fe_priv *np = netdev_priv(dev);
2711         u8 __iomem *base = get_hwbase(dev);
2712         unsigned long flags;
2713
2714         pkts = nv_rx_process(dev, limit);
2715
2716         if (nv_alloc_rx(dev)) {
2717                 spin_lock_irqsave(&np->lock, flags);
2718                 if (!np->in_shutdown)
2719                         mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
2720                 spin_unlock_irqrestore(&np->lock, flags);
2721         }
2722
2723         if (pkts < limit) {
2724                 /* all done, no more packets present */
2725                 netif_rx_complete(dev);
2726
2727                 /* re-enable receive interrupts */
2728                 spin_lock_irqsave(&np->lock, flags);
2729
2730                 np->irqmask |= NVREG_IRQ_RX_ALL;
2731                 if (np->msi_flags & NV_MSI_X_ENABLED)
2732                         writel(NVREG_IRQ_RX_ALL, base + NvRegIrqMask);
2733                 else
2734                         writel(np->irqmask, base + NvRegIrqMask);
2735
2736                 spin_unlock_irqrestore(&np->lock, flags);
2737                 return 0;
2738         } else {
2739                 /* used up our quantum, so reschedule */
2740                 dev->quota -= pkts;
2741                 *budget -= pkts;
2742                 return 1;
2743         }
2744 }
2745 #endif
2746
2747 #ifdef CONFIG_FORCEDETH_NAPI
2748 static irqreturn_t nv_nic_irq_rx(int foo, void *data)
2749 {
2750         struct net_device *dev = (struct net_device *) data;
2751         u8 __iomem *base = get_hwbase(dev);
2752         u32 events;
2753
2754         events = readl(base + NvRegMSIXIrqStatus) & NVREG_IRQ_RX_ALL;
2755         writel(NVREG_IRQ_RX_ALL, base + NvRegMSIXIrqStatus);
2756
2757         if (events) {
2758                 netif_rx_schedule(dev);
2759                 /* disable receive interrupts on the nic */
2760                 writel(NVREG_IRQ_RX_ALL, base + NvRegIrqMask);
2761                 pci_push(base);
2762         }
2763         return IRQ_HANDLED;
2764 }
2765 #else
2766 static irqreturn_t nv_nic_irq_rx(int foo, void *data)
2767 {
2768         struct net_device *dev = (struct net_device *) data;
2769         struct fe_priv *np = netdev_priv(dev);
2770         u8 __iomem *base = get_hwbase(dev);
2771         u32 events;
2772         int i;
2773         unsigned long flags;
2774
2775         dprintk(KERN_DEBUG "%s: nv_nic_irq_rx\n", dev->name);
2776
2777         for (i=0; ; i++) {
2778                 events = readl(base + NvRegMSIXIrqStatus) & NVREG_IRQ_RX_ALL;
2779                 writel(NVREG_IRQ_RX_ALL, base + NvRegMSIXIrqStatus);
2780                 pci_push(base);
2781                 dprintk(KERN_DEBUG "%s: rx irq: %08x\n", dev->name, events);
2782                 if (!(events & np->irqmask))
2783                         break;
2784
2785                 nv_rx_process(dev, dev->weight);
2786                 if (nv_alloc_rx(dev)) {
2787                         spin_lock_irqsave(&np->lock, flags);
2788                         if (!np->in_shutdown)
2789                                 mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
2790                         spin_unlock_irqrestore(&np->lock, flags);
2791                 }
2792
2793                 if (i > max_interrupt_work) {
2794                         spin_lock_irqsave(&np->lock, flags);
2795                         /* disable interrupts on the nic */
2796                         writel(NVREG_IRQ_RX_ALL, base + NvRegIrqMask);
2797                         pci_push(base);
2798
2799                         if (!np->in_shutdown) {
2800                                 np->nic_poll_irq |= NVREG_IRQ_RX_ALL;
2801                                 mod_timer(&np->nic_poll, jiffies + POLL_WAIT);
2802                         }
2803                         printk(KERN_DEBUG "%s: too many iterations (%d) in nv_nic_irq_rx.\n", dev->name, i);
2804                         spin_unlock_irqrestore(&np->lock, flags);
2805                         break;
2806                 }
2807         }
2808         dprintk(KERN_DEBUG "%s: nv_nic_irq_rx completed\n", dev->name);
2809
2810         return IRQ_RETVAL(i);
2811 }
2812 #endif
2813
2814 static irqreturn_t nv_nic_irq_other(int foo, void *data)
2815 {
2816         struct net_device *dev = (struct net_device *) data;
2817         struct fe_priv *np = netdev_priv(dev);
2818         u8 __iomem *base = get_hwbase(dev);
2819         u32 events;
2820         int i;
2821         unsigned long flags;
2822
2823         dprintk(KERN_DEBUG "%s: nv_nic_irq_other\n", dev->name);
2824
2825         for (i=0; ; i++) {
2826                 events = readl(base + NvRegMSIXIrqStatus) & NVREG_IRQ_OTHER;
2827                 writel(NVREG_IRQ_OTHER, base + NvRegMSIXIrqStatus);
2828                 pci_push(base);
2829                 dprintk(KERN_DEBUG "%s: irq: %08x\n", dev->name, events);
2830                 if (!(events & np->irqmask))
2831                         break;
2832
2833                 if (events & NVREG_IRQ_LINK) {
2834                         spin_lock_irqsave(&np->lock, flags);
2835                         nv_link_irq(dev);
2836                         spin_unlock_irqrestore(&np->lock, flags);
2837                 }
2838                 if (np->need_linktimer && time_after(jiffies, np->link_timeout)) {
2839                         spin_lock_irqsave(&np->lock, flags);
2840                         nv_linkchange(dev);
2841                         spin_unlock_irqrestore(&np->lock, flags);
2842                         np->link_timeout = jiffies + LINK_TIMEOUT;
2843                 }
2844                 if (events & NVREG_IRQ_RECOVER_ERROR) {
2845                         spin_lock_irq(&np->lock);
2846                         /* disable interrupts on the nic */
2847                         writel(NVREG_IRQ_OTHER, base + NvRegIrqMask);
2848                         pci_push(base);
2849
2850                         if (!np->in_shutdown) {
2851                                 np->nic_poll_irq |= NVREG_IRQ_OTHER;
2852                                 np->recover_error = 1;
2853                                 mod_timer(&np->nic_poll, jiffies + POLL_WAIT);
2854                         }
2855                         spin_unlock_irq(&np->lock);
2856                         break;
2857                 }
2858                 if (events & (NVREG_IRQ_UNKNOWN)) {
2859                         printk(KERN_DEBUG "%s: received irq with unknown events 0x%x. Please report\n",
2860                                                 dev->name, events);
2861                 }
2862                 if (i > max_interrupt_work) {
2863                         spin_lock_irqsave(&np->lock, flags);
2864                         /* disable interrupts on the nic */
2865                         writel(NVREG_IRQ_OTHER, base + NvRegIrqMask);
2866                         pci_push(base);
2867
2868                         if (!np->in_shutdown) {
2869                                 np->nic_poll_irq |= NVREG_IRQ_OTHER;
2870                                 mod_timer(&np->nic_poll, jiffies + POLL_WAIT);
2871                         }
2872                         printk(KERN_DEBUG "%s: too many iterations (%d) in nv_nic_irq_other.\n", dev->name, i);
2873                         spin_unlock_irqrestore(&np->lock, flags);
2874                         break;
2875                 }
2876
2877         }
2878         dprintk(KERN_DEBUG "%s: nv_nic_irq_other completed\n", dev->name);
2879
2880         return IRQ_RETVAL(i);
2881 }
2882
2883 static irqreturn_t nv_nic_irq_test(int foo, void *data)
2884 {
2885         struct net_device *dev = (struct net_device *) data;
2886         struct fe_priv *np = netdev_priv(dev);
2887         u8 __iomem *base = get_hwbase(dev);
2888         u32 events;
2889
2890         dprintk(KERN_DEBUG "%s: nv_nic_irq_test\n", dev->name);
2891
2892         if (!(np->msi_flags & NV_MSI_X_ENABLED)) {
2893                 events = readl(base + NvRegIrqStatus) & NVREG_IRQSTAT_MASK;
2894                 writel(NVREG_IRQ_TIMER, base + NvRegIrqStatus);
2895         } else {
2896                 events = readl(base + NvRegMSIXIrqStatus) & NVREG_IRQSTAT_MASK;
2897                 writel(NVREG_IRQ_TIMER, base + NvRegMSIXIrqStatus);
2898         }
2899         pci_push(base);
2900         dprintk(KERN_DEBUG "%s: irq: %08x\n", dev->name, events);
2901         if (!(events & NVREG_IRQ_TIMER))
2902                 return IRQ_RETVAL(0);
2903
2904         spin_lock(&np->lock);
2905         np->intr_test = 1;
2906         spin_unlock(&np->lock);
2907
2908         dprintk(KERN_DEBUG "%s: nv_nic_irq_test completed\n", dev->name);
2909
2910         return IRQ_RETVAL(1);
2911 }
2912
2913 static void set_msix_vector_map(struct net_device *dev, u32 vector, u32 irqmask)
2914 {
2915         u8 __iomem *base = get_hwbase(dev);
2916         int i;
2917         u32 msixmap = 0;
2918
2919         /* Each interrupt bit can be mapped to a MSIX vector (4 bits).
2920          * MSIXMap0 represents the first 8 interrupts and MSIXMap1 represents
2921          * the remaining 8 interrupts.
2922          */
2923         for (i = 0; i < 8; i++) {
2924                 if ((irqmask >> i) & 0x1) {
2925                         msixmap |= vector << (i << 2);
2926                 }
2927         }
2928         writel(readl(base + NvRegMSIXMap0) | msixmap, base + NvRegMSIXMap0);
2929
2930         msixmap = 0;
2931         for (i = 0; i < 8; i++) {
2932                 if ((irqmask >> (i + 8)) & 0x1) {
2933                         msixmap |= vector << (i << 2);
2934                 }
2935         }
2936         writel(readl(base + NvRegMSIXMap1) | msixmap, base + NvRegMSIXMap1);
2937 }
2938
2939 static int nv_request_irq(struct net_device *dev, int intr_test)
2940 {
2941         struct fe_priv *np = get_nvpriv(dev);
2942         u8 __iomem *base = get_hwbase(dev);
2943         int ret = 1;
2944         int i;
2945
2946         if (np->msi_flags & NV_MSI_X_CAPABLE) {
2947                 for (i = 0; i < (np->msi_flags & NV_MSI_X_VECTORS_MASK); i++) {
2948                         np->msi_x_entry[i].entry = i;
2949                 }
2950                 if ((ret = pci_enable_msix(np->pci_dev, np->msi_x_entry, (np->msi_flags & NV_MSI_X_VECTORS_MASK))) == 0) {
2951                         np->msi_flags |= NV_MSI_X_ENABLED;
2952                         if (optimization_mode == NV_OPTIMIZATION_MODE_THROUGHPUT && !intr_test) {
2953                                 /* Request irq for rx handling */
2954                                 if (request_irq(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector, &nv_nic_irq_rx, IRQF_SHARED, dev->name, dev) != 0) {
2955                                         printk(KERN_INFO "forcedeth: request_irq failed for rx %d\n", ret);
2956                                         pci_disable_msix(np->pci_dev);
2957                                         np->msi_flags &= ~NV_MSI_X_ENABLED;
2958                                         goto out_err;
2959                                 }
2960                                 /* Request irq for tx handling */
2961                                 if (request_irq(np->msi_x_entry[NV_MSI_X_VECTOR_TX].vector, &nv_nic_irq_tx, IRQF_SHARED, dev->name, dev) != 0) {
2962                                         printk(KERN_INFO "forcedeth: request_irq failed for tx %d\n", ret);
2963                                         pci_disable_msix(np->pci_dev);
2964                                         np->msi_flags &= ~NV_MSI_X_ENABLED;
2965                                         goto out_free_rx;
2966                                 }
2967                                 /* Request irq for link and timer handling */
2968                                 if (request_irq(np->msi_x_entry[NV_MSI_X_VECTOR_OTHER].vector, &nv_nic_irq_other, IRQF_SHARED, dev->name, dev) != 0) {
2969                                         printk(KERN_INFO "forcedeth: request_irq failed for link %d\n", ret);
2970                                         pci_disable_msix(np->pci_dev);
2971                                         np->msi_flags &= ~NV_MSI_X_ENABLED;
2972                                         goto out_free_tx;
2973                                 }
2974                                 /* map interrupts to their respective vector */
2975                                 writel(0, base + NvRegMSIXMap0);
2976                                 writel(0, base + NvRegMSIXMap1);
2977                                 set_msix_vector_map(dev, NV_MSI_X_VECTOR_RX, NVREG_IRQ_RX_ALL);
2978                                 set_msix_vector_map(dev, NV_MSI_X_VECTOR_TX, NVREG_IRQ_TX_ALL);
2979                                 set_msix_vector_map(dev, NV_MSI_X_VECTOR_OTHER, NVREG_IRQ_OTHER);
2980                         } else {
2981                                 /* Request irq for all interrupts */
2982                                 if ((!intr_test &&
2983                                      request_irq(np->msi_x_entry[NV_MSI_X_VECTOR_ALL].vector, &nv_nic_irq, IRQF_SHARED, dev->name, dev) != 0) ||
2984                                     (intr_test &&
2985                                      request_irq(np->msi_x_entry[NV_MSI_X_VECTOR_ALL].vector, &nv_nic_irq_test, IRQF_SHARED, dev->name, dev) != 0)) {
2986                                         printk(KERN_INFO "forcedeth: request_irq failed %d\n", ret);
2987                                         pci_disable_msix(np->pci_dev);
2988                                         np->msi_flags &= ~NV_MSI_X_ENABLED;
2989                                         goto out_err;
2990                                 }
2991
2992                                 /* map interrupts to vector 0 */
2993                                 writel(0, base + NvRegMSIXMap0);
2994                                 writel(0, base + NvRegMSIXMap1);
2995                         }
2996                 }
2997         }
2998         if (ret != 0 && np->msi_flags & NV_MSI_CAPABLE) {
2999                 if ((ret = pci_enable_msi(np->pci_dev)) == 0) {
3000                         np->msi_flags |= NV_MSI_ENABLED;
3001                         if ((!intr_test && request_irq(np->pci_dev->irq, &nv_nic_irq, IRQF_SHARED, dev->name, dev) != 0) ||
3002                             (intr_test && request_irq(np->pci_dev->irq, &nv_nic_irq_test, IRQF_SHARED, dev->name, dev) != 0)) {
3003                                 printk(KERN_INFO "forcedeth: request_irq failed %d\n", ret);
3004                                 pci_disable_msi(np->pci_dev);
3005                                 np->msi_flags &= ~NV_MSI_ENABLED;
3006                                 goto out_err;
3007                         }
3008
3009                         /* map interrupts to vector 0 */
3010                         writel(0, base + NvRegMSIMap0);
3011                         writel(0, base + NvRegMSIMap1);
3012                         /* enable msi vector 0 */
3013                         writel(NVREG_MSI_VECTOR_0_ENABLED, base + NvRegMSIIrqMask);
3014                 }
3015         }
3016         if (ret != 0) {
3017                 if ((!intr_test && request_irq(np->pci_dev->irq, &nv_nic_irq, IRQF_SHARED, dev->name, dev) != 0) ||
3018                     (intr_test && request_irq(np->pci_dev->irq, &nv_nic_irq_test, IRQF_SHARED, dev->name, dev) != 0))
3019                         goto out_err;
3020
3021         }
3022
3023         return 0;
3024 out_free_tx:
3025         free_irq(np->msi_x_entry[NV_MSI_X_VECTOR_TX].vector, dev);
3026 out_free_rx:
3027         free_irq(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector, dev);
3028 out_err:
3029         return 1;
3030 }
3031
3032 static void nv_free_irq(struct net_device *dev)
3033 {
3034         struct fe_priv *np = get_nvpriv(dev);
3035         int i;
3036
3037         if (np->msi_flags & NV_MSI_X_ENABLED) {
3038                 for (i = 0; i < (np->msi_flags & NV_MSI_X_VECTORS_MASK); i++) {
3039                         free_irq(np->msi_x_entry[i].vector, dev);
3040                 }
3041                 pci_disable_msix(np->pci_dev);
3042                 np->msi_flags &= ~NV_MSI_X_ENABLED;
3043         } else {
3044                 free_irq(np->pci_dev->irq, dev);
3045                 if (np->msi_flags & NV_MSI_ENABLED) {
3046                         pci_disable_msi(np->pci_dev);
3047                         np->msi_flags &= ~NV_MSI_ENABLED;
3048                 }
3049         }
3050 }
3051
3052 static void nv_do_nic_poll(unsigned long data)
3053 {
3054         struct net_device *dev = (struct net_device *) data;
3055         struct fe_priv *np = netdev_priv(dev);
3056         u8 __iomem *base = get_hwbase(dev);
3057         u32 mask = 0;
3058
3059         /*
3060          * First disable irq(s) and then
3061          * reenable interrupts on the nic, we have to do this before calling
3062          * nv_nic_irq because that may decide to do otherwise
3063          */
3064
3065         if (!using_multi_irqs(dev)) {
3066                 if (np->msi_flags & NV_MSI_X_ENABLED)
3067                         disable_irq_lockdep(np->msi_x_entry[NV_MSI_X_VECTOR_ALL].vector);
3068                 else
3069                         disable_irq_lockdep(dev->irq);
3070                 mask = np->irqmask;
3071         } else {
3072                 if (np->nic_poll_irq & NVREG_IRQ_RX_ALL) {
3073                         disable_irq_lockdep(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector);
3074                         mask |= NVREG_IRQ_RX_ALL;
3075                 }
3076                 if (np->nic_poll_irq & NVREG_IRQ_TX_ALL) {
3077                         disable_irq_lockdep(np->msi_x_entry[NV_MSI_X_VECTOR_TX].vector);
3078                         mask |= NVREG_IRQ_TX_ALL;
3079                 }
3080                 if (np->nic_poll_irq & NVREG_IRQ_OTHER) {
3081                         disable_irq_lockdep(np->msi_x_entry[NV_MSI_X_VECTOR_OTHER].vector);
3082                         mask |= NVREG_IRQ_OTHER;
3083                 }
3084         }
3085         np->nic_poll_irq = 0;
3086
3087         if (np->recover_error) {
3088                 np->recover_error = 0;
3089                 printk(KERN_INFO "forcedeth: MAC in recoverable error state\n");
3090                 if (netif_running(dev)) {
3091                         netif_tx_lock_bh(dev);
3092                         spin_lock(&np->lock);
3093                         /* stop engines */
3094                         nv_stop_rx(dev);
3095                         nv_stop_tx(dev);
3096                         nv_txrx_reset(dev);
3097                         /* drain rx queue */
3098                         nv_drain_rx(dev);
3099                         nv_drain_tx(dev);
3100                         /* reinit driver view of the rx queue */
3101                         set_bufsize(dev);
3102                         if (nv_init_ring(dev)) {
3103                                 if (!np->in_shutdown)
3104                                         mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
3105                         }
3106                         /* reinit nic view of the rx queue */
3107                         writel(np->rx_buf_sz, base + NvRegOffloadConfig);
3108                         setup_hw_rings(dev, NV_SETUP_RX_RING | NV_SETUP_TX_RING);
3109                         writel( ((np->rx_ring_size-1) << NVREG_RINGSZ_RXSHIFT) + ((np->tx_ring_size-1) << NVREG_RINGSZ_TXSHIFT),
3110                                 base + NvRegRingSizes);
3111                         pci_push(base);
3112                         writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
3113                         pci_push(base);
3114
3115                         /* restart rx engine */
3116                         nv_start_rx(dev);
3117                         nv_start_tx(dev);
3118                         spin_unlock(&np->lock);
3119                         netif_tx_unlock_bh(dev);
3120                 }
3121         }
3122
3123         /* FIXME: Do we need synchronize_irq(dev->irq) here? */
3124
3125         writel(mask, base + NvRegIrqMask);
3126         pci_push(base);
3127
3128         if (!using_multi_irqs(dev)) {
3129                 nv_nic_irq(0, dev);
3130                 if (np->msi_flags & NV_MSI_X_ENABLED)
3131                         enable_irq_lockdep(np->msi_x_entry[NV_MSI_X_VECTOR_ALL].vector);
3132                 else
3133                         enable_irq_lockdep(dev->irq);
3134         } else {
3135                 if (np->nic_poll_irq & NVREG_IRQ_RX_ALL) {
3136                         nv_nic_irq_rx(0, dev);
3137                         enable_irq_lockdep(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector);
3138                 }
3139                 if (np->nic_poll_irq & NVREG_IRQ_TX_ALL) {
3140                         nv_nic_irq_tx(0, dev);
3141                         enable_irq_lockdep(np->msi_x_entry[NV_MSI_X_VECTOR_TX].vector);
3142                 }
3143                 if (np->nic_poll_irq & NVREG_IRQ_OTHER) {
3144                         nv_nic_irq_other(0, dev);
3145                         enable_irq_lockdep(np->msi_x_entry[NV_MSI_X_VECTOR_OTHER].vector);
3146                 }
3147         }
3148 }
3149
3150 #ifdef CONFIG_NET_POLL_CONTROLLER
3151 static void nv_poll_controller(struct net_device *dev)
3152 {
3153         nv_do_nic_poll((unsigned long) dev);
3154 }
3155 #endif
3156
3157 static void nv_do_stats_poll(unsigned long data)
3158 {
3159         struct net_device *dev = (struct net_device *) data;
3160         struct fe_priv *np = netdev_priv(dev);
3161         u8 __iomem *base = get_hwbase(dev);
3162
3163         np->estats.tx_bytes += readl(base + NvRegTxCnt);
3164         np->estats.tx_zero_rexmt += readl(base + NvRegTxZeroReXmt);
3165         np->estats.tx_one_rexmt += readl(base + NvRegTxOneReXmt);
3166         np->estats.tx_many_rexmt += readl(base + NvRegTxManyReXmt);
3167         np->estats.tx_late_collision += readl(base + NvRegTxLateCol);
3168         np->estats.tx_fifo_errors += readl(base + NvRegTxUnderflow);
3169         np->estats.tx_carrier_errors += readl(base + NvRegTxLossCarrier);
3170         np->estats.tx_excess_deferral += readl(base + NvRegTxExcessDef);
3171         np->estats.tx_retry_error += readl(base + NvRegTxRetryErr);
3172         np->estats.tx_deferral += readl(base + NvRegTxDef);
3173         np->estats.tx_packets += readl(base + NvRegTxFrame);
3174         np->estats.tx_pause += readl(base + NvRegTxPause);
3175         np->estats.rx_frame_error += readl(base + NvRegRxFrameErr);
3176         np->estats.rx_extra_byte += readl(base + NvRegRxExtraByte);
3177         np->estats.rx_late_collision += readl(base + NvRegRxLateCol);
3178         np->estats.rx_runt += readl(base + NvRegRxRunt);
3179         np->estats.rx_frame_too_long += readl(base + NvRegRxFrameTooLong);
3180         np->estats.rx_over_errors += readl(base + NvRegRxOverflow);
3181         np->estats.rx_crc_errors += readl(base + NvRegRxFCSErr);
3182         np->estats.rx_frame_align_error += readl(base + NvRegRxFrameAlignErr);
3183         np->estats.rx_length_error += readl(base + NvRegRxLenErr);
3184         np->estats.rx_unicast += readl(base + NvRegRxUnicast);
3185         np->estats.rx_multicast += readl(base + NvRegRxMulticast);
3186         np->estats.rx_broadcast += readl(base + NvRegRxBroadcast);
3187         np->estats.rx_bytes += readl(base + NvRegRxCnt);
3188         np->estats.rx_pause += readl(base + NvRegRxPause);
3189         np->estats.rx_drop_frame += readl(base + NvRegRxDropFrame);
3190         np->estats.rx_packets =
3191                 np->estats.rx_unicast +
3192                 np->estats.rx_multicast +
3193                 np->estats.rx_broadcast;
3194         np->estats.rx_errors_total =
3195                 np->estats.rx_crc_errors +
3196                 np->estats.rx_over_errors +
3197                 np->estats.rx_frame_error +
3198                 (np->estats.rx_frame_align_error - np->estats.rx_extra_byte) +
3199                 np->estats.rx_late_collision +
3200                 np->estats.rx_runt +
3201                 np->estats.rx_frame_too_long;
3202
3203         if (!np->in_shutdown)
3204                 mod_timer(&np->stats_poll, jiffies + STATS_INTERVAL);
3205 }
3206
3207 static void nv_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
3208 {
3209         struct fe_priv *np = netdev_priv(dev);
3210         strcpy(info->driver, "forcedeth");
3211         strcpy(info->version, FORCEDETH_VERSION);
3212         strcpy(info->bus_info, pci_name(np->pci_dev));
3213 }
3214
3215 static void nv_get_wol(struct net_device *dev, struct ethtool_wolinfo *wolinfo)
3216 {
3217         struct fe_priv *np = netdev_priv(dev);
3218         wolinfo->supported = WAKE_MAGIC;
3219
3220         spin_lock_irq(&np->lock);
3221         if (np->wolenabled)
3222                 wolinfo->wolopts = WAKE_MAGIC;
3223         spin_unlock_irq(&np->lock);
3224 }
3225
3226 static int nv_set_wol(struct net_device *dev, struct ethtool_wolinfo *wolinfo)
3227 {
3228         struct fe_priv *np = netdev_priv(dev);
3229         u8 __iomem *base = get_hwbase(dev);
3230         u32 flags = 0;
3231
3232         if (wolinfo->wolopts == 0) {
3233                 np->wolenabled = 0;
3234         } else if (wolinfo->wolopts & WAKE_MAGIC) {
3235                 np->wolenabled = 1;
3236                 flags = NVREG_WAKEUPFLAGS_ENABLE;
3237         }
3238         if (netif_running(dev)) {
3239                 spin_lock_irq(&np->lock);
3240                 writel(flags, base + NvRegWakeUpFlags);
3241                 spin_unlock_irq(&np->lock);
3242         }
3243         return 0;
3244 }
3245
3246 static int nv_get_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
3247 {
3248         struct fe_priv *np = netdev_priv(dev);
3249         int adv;
3250
3251         spin_lock_irq(&np->lock);
3252         ecmd->port = PORT_MII;
3253         if (!netif_running(dev)) {
3254                 /* We do not track link speed / duplex setting if the
3255                  * interface is disabled. Force a link check */
3256                 if (nv_update_linkspeed(dev)) {
3257                         if (!netif_carrier_ok(dev))
3258                                 netif_carrier_on(dev);
3259                 } else {
3260                         if (netif_carrier_ok(dev))
3261                                 netif_carrier_off(dev);
3262                 }
3263         }
3264
3265         if (netif_carrier_ok(dev)) {
3266                 switch(np->linkspeed & (NVREG_LINKSPEED_MASK)) {
3267                 case NVREG_LINKSPEED_10:
3268                         ecmd->speed = SPEED_10;
3269                         break;
3270                 case NVREG_LINKSPEED_100:
3271                         ecmd->speed = SPEED_100;
3272                         break;
3273                 case NVREG_LINKSPEED_1000:
3274                         ecmd->speed = SPEED_1000;
3275                         break;
3276                 }
3277                 ecmd->duplex = DUPLEX_HALF;
3278                 if (np->duplex)
3279                         ecmd->duplex = DUPLEX_FULL;
3280         } else {
3281                 ecmd->speed = -1;
3282                 ecmd->duplex = -1;
3283         }
3284
3285         ecmd->autoneg = np->autoneg;
3286
3287         ecmd->advertising = ADVERTISED_MII;
3288         if (np->autoneg) {
3289                 ecmd->advertising |= ADVERTISED_Autoneg;
3290                 adv = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ);
3291                 if (adv & ADVERTISE_10HALF)
3292                         ecmd->advertising |= ADVERTISED_10baseT_Half;
3293                 if (adv & ADVERTISE_10FULL)
3294                         ecmd->advertising |= ADVERTISED_10baseT_Full;
3295                 if (adv & ADVERTISE_100HALF)
3296                         ecmd->advertising |= ADVERTISED_100baseT_Half;
3297                 if (adv & ADVERTISE_100FULL)
3298                         ecmd->advertising |= ADVERTISED_100baseT_Full;
3299                 if (np->gigabit == PHY_GIGABIT) {
3300                         adv = mii_rw(dev, np->phyaddr, MII_CTRL1000, MII_READ);
3301                         if (adv & ADVERTISE_1000FULL)
3302                                 ecmd->advertising |= ADVERTISED_1000baseT_Full;
3303                 }
3304         }
3305         ecmd->supported = (SUPPORTED_Autoneg |
3306                 SUPPORTED_10baseT_Half | SUPPORTED_10baseT_Full |
3307                 SUPPORTED_100baseT_Half | SUPPORTED_100baseT_Full |
3308                 SUPPORTED_MII);
3309         if (np->gigabit == PHY_GIGABIT)
3310                 ecmd->supported |= SUPPORTED_1000baseT_Full;
3311
3312         ecmd->phy_address = np->phyaddr;
3313         ecmd->transceiver = XCVR_EXTERNAL;
3314
3315         /* ignore maxtxpkt, maxrxpkt for now */
3316         spin_unlock_irq(&np->lock);
3317         return 0;
3318 }
3319
3320 static int nv_set_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
3321 {
3322         struct fe_priv *np = netdev_priv(dev);
3323
3324         if (ecmd->port != PORT_MII)
3325                 return -EINVAL;
3326         if (ecmd->transceiver != XCVR_EXTERNAL)
3327                 return -EINVAL;
3328         if (ecmd->phy_address != np->phyaddr) {
3329                 /* TODO: support switching between multiple phys. Should be
3330                  * trivial, but not enabled due to lack of test hardware. */
3331                 return -EINVAL;
3332         }
3333         if (ecmd->autoneg == AUTONEG_ENABLE) {
3334                 u32 mask;
3335
3336                 mask = ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
3337                           ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full;
3338                 if (np->gigabit == PHY_GIGABIT)
3339                         mask |= ADVERTISED_1000baseT_Full;
3340
3341                 if ((ecmd->advertising & mask) == 0)
3342                         return -EINVAL;
3343
3344         } else if (ecmd->autoneg == AUTONEG_DISABLE) {
3345                 /* Note: autonegotiation disable, speed 1000 intentionally
3346                  * forbidden - noone should need that. */
3347
3348                 if (ecmd->speed != SPEED_10 && ecmd->speed != SPEED_100)
3349                         return -EINVAL;
3350                 if (ecmd->duplex != DUPLEX_HALF && ecmd->duplex != DUPLEX_FULL)
3351                         return -EINVAL;
3352         } else {
3353                 return -EINVAL;
3354         }
3355
3356         netif_carrier_off(dev);
3357         if (netif_running(dev)) {
3358                 nv_disable_irq(dev);
3359                 netif_tx_lock_bh(dev);
3360                 spin_lock(&np->lock);
3361                 /* stop engines */
3362                 nv_stop_rx(dev);
3363                 nv_stop_tx(dev);
3364                 spin_unlock(&np->lock);
3365                 netif_tx_unlock_bh(dev);
3366         }
3367
3368         if (ecmd->autoneg == AUTONEG_ENABLE) {
3369                 int adv, bmcr;
3370
3371                 np->autoneg = 1;
3372
3373                 /* advertise only what has been requested */
3374                 adv = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ);
3375                 adv &= ~(ADVERTISE_ALL | ADVERTISE_100BASE4 | ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
3376                 if (ecmd->advertising & ADVERTISED_10baseT_Half)
3377                         adv |= ADVERTISE_10HALF;
3378                 if (ecmd->advertising & ADVERTISED_10baseT_Full)
3379                         adv |= ADVERTISE_10FULL;
3380                 if (ecmd->advertising & ADVERTISED_100baseT_Half)
3381                         adv |= ADVERTISE_100HALF;
3382                 if (ecmd->advertising & ADVERTISED_100baseT_Full)
3383                         adv |= ADVERTISE_100FULL;
3384                 if (np->pause_flags & NV_PAUSEFRAME_RX_REQ)  /* for rx we set both advertisments but disable tx pause */
3385                         adv |=  ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
3386                 if (np->pause_flags & NV_PAUSEFRAME_TX_REQ)
3387                         adv |=  ADVERTISE_PAUSE_ASYM;
3388                 mii_rw(dev, np->phyaddr, MII_ADVERTISE, adv);
3389
3390                 if (np->gigabit == PHY_GIGABIT) {
3391                         adv = mii_rw(dev, np->phyaddr, MII_CTRL1000, MII_READ);
3392                         adv &= ~ADVERTISE_1000FULL;
3393                         if (ecmd->advertising & ADVERTISED_1000baseT_Full)
3394                                 adv |= ADVERTISE_1000FULL;
3395                         mii_rw(dev, np->phyaddr, MII_CTRL1000, adv);
3396                 }
3397
3398                 if (netif_running(dev))
3399                         printk(KERN_INFO "%s: link down.\n", dev->name);
3400                 bmcr = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
3401                 if (np->phy_model == PHY_MODEL_MARVELL_E3016) {
3402                         bmcr |= BMCR_ANENABLE;
3403                         /* reset the phy in order for settings to stick,
3404                          * and cause autoneg to start */
3405                         if (phy_reset(dev, bmcr)) {
3406                                 printk(KERN_INFO "%s: phy reset failed\n", dev->name);
3407                                 return -EINVAL;
3408                         }
3409                 } else {
3410                         bmcr |= (BMCR_ANENABLE | BMCR_ANRESTART);
3411                         mii_rw(dev, np->phyaddr, MII_BMCR, bmcr);
3412                 }
3413         } else {
3414                 int adv, bmcr;
3415
3416                 np->autoneg = 0;
3417
3418                 adv = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ);
3419                 adv &= ~(ADVERTISE_ALL | ADVERTISE_100BASE4 | ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
3420                 if (ecmd->speed == SPEED_10 && ecmd->duplex == DUPLEX_HALF)
3421                         adv |= ADVERTISE_10HALF;
3422                 if (ecmd->speed == SPEED_10 && ecmd->duplex == DUPLEX_FULL)
3423                         adv |= ADVERTISE_10FULL;
3424                 if (ecmd->speed == SPEED_100 && ecmd->duplex == DUPLEX_HALF)
3425                         adv |= ADVERTISE_100HALF;
3426                 if (ecmd->speed == SPEED_100 && ecmd->duplex == DUPLEX_FULL)
3427                         adv |= ADVERTISE_100FULL;
3428                 np->pause_flags &= ~(NV_PAUSEFRAME_AUTONEG|NV_PAUSEFRAME_RX_ENABLE|NV_PAUSEFRAME_TX_ENABLE);
3429                 if (np->pause_flags & NV_PAUSEFRAME_RX_REQ) {/* for rx we set both advertisments but disable tx pause */
3430                         adv |=  ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
3431                         np->pause_flags |= NV_PAUSEFRAME_RX_ENABLE;
3432                 }
3433                 if (np->pause_flags & NV_PAUSEFRAME_TX_REQ) {
3434                         adv |=  ADVERTISE_PAUSE_ASYM;
3435                         np->pause_flags |= NV_PAUSEFRAME_TX_ENABLE;
3436                 }
3437                 mii_rw(dev, np->phyaddr, MII_ADVERTISE, adv);
3438                 np->fixed_mode = adv;
3439
3440                 if (np->gigabit == PHY_GIGABIT) {
3441                         adv = mii_rw(dev, np->phyaddr, MII_CTRL1000, MII_READ);
3442                         adv &= ~ADVERTISE_1000FULL;
3443                         mii_rw(dev, np->phyaddr, MII_CTRL1000, adv);
3444                 }
3445
3446                 bmcr = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
3447                 bmcr &= ~(BMCR_ANENABLE|BMCR_SPEED100|BMCR_SPEED1000|BMCR_FULLDPLX);
3448                 if (np->fixed_mode & (ADVERTISE_10FULL|ADVERTISE_100FULL))
3449                         bmcr |= BMCR_FULLDPLX;
3450                 if (np->fixed_mode & (ADVERTISE_100HALF|ADVERTISE_100FULL))
3451                         bmcr |= BMCR_SPEED100;
3452                 if (np->phy_oui == PHY_OUI_MARVELL) {
3453                         /* reset the phy in order for forced mode settings to stick */
3454                         if (phy_reset(dev, bmcr)) {
3455                                 printk(KERN_INFO "%s: phy reset failed\n", dev->name);
3456                                 return -EINVAL;
3457                         }
3458                 } else {
3459                         mii_rw(dev, np->phyaddr, MII_BMCR, bmcr);
3460                         if (netif_running(dev)) {
3461                                 /* Wait a bit and then reconfigure the nic. */
3462                                 udelay(10);
3463                                 nv_linkchange(dev);
3464                         }
3465                 }
3466         }
3467
3468         if (netif_running(dev)) {
3469                 nv_start_rx(dev);
3470                 nv_start_tx(dev);
3471                 nv_enable_irq(dev);
3472         }
3473
3474         return 0;
3475 }
3476
3477 #define FORCEDETH_REGS_VER      1
3478
3479 static int nv_get_regs_len(struct net_device *dev)
3480 {
3481         struct fe_priv *np = netdev_priv(dev);
3482         return np->register_size;
3483 }
3484
3485 static void nv_get_regs(struct net_device *dev, struct ethtool_regs *regs, void *buf)
3486 {
3487         struct fe_priv *np = netdev_priv(dev);
3488         u8 __iomem *base = get_hwbase(dev);
3489         u32 *rbuf = buf;
3490         int i;
3491
3492         regs->version = FORCEDETH_REGS_VER;
3493         spin_lock_irq(&np->lock);
3494         for (i = 0;i <= np->register_size/sizeof(u32); i++)
3495                 rbuf[i] = readl(base + i*sizeof(u32));
3496         spin_unlock_irq(&np->lock);
3497 }
3498
3499 static int nv_nway_reset(struct net_device *dev)
3500 {
3501         struct fe_priv *np = netdev_priv(dev);
3502         int ret;
3503
3504         if (np->autoneg) {
3505                 int bmcr;
3506
3507                 netif_carrier_off(dev);
3508                 if (netif_running(dev)) {
3509                         nv_disable_irq(dev);
3510                         netif_tx_lock_bh(dev);
3511                         spin_lock(&np->lock);
3512                         /* stop engines */
3513                         nv_stop_rx(dev);
3514                         nv_stop_tx(dev);
3515                         spin_unlock(&np->lock);
3516                         netif_tx_unlock_bh(dev);
3517                         printk(KERN_INFO "%s: link down.\n", dev->name);
3518                 }
3519
3520                 bmcr = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
3521                 if (np->phy_model == PHY_MODEL_MARVELL_E3016) {
3522                         bmcr |= BMCR_ANENABLE;
3523                         /* reset the phy in order for settings to stick*/
3524                         if (phy_reset(dev, bmcr)) {
3525                                 printk(KERN_INFO "%s: phy reset failed\n", dev->name);
3526                                 return -EINVAL;
3527                         }
3528                 } else {
3529                         bmcr |= (BMCR_ANENABLE | BMCR_ANRESTART);
3530                         mii_rw(dev, np->phyaddr, MII_BMCR, bmcr);
3531                 }
3532
3533                 if (netif_running(dev)) {
3534                         nv_start_rx(dev);
3535                         nv_start_tx(dev);
3536                         nv_enable_irq(dev);
3537                 }
3538                 ret = 0;
3539         } else {
3540                 ret = -EINVAL;
3541         }
3542
3543         return ret;
3544 }
3545
3546 static int nv_set_tso(struct net_device *dev, u32 value)
3547 {
3548         struct fe_priv *np = netdev_priv(dev);
3549
3550         if ((np->driver_data & DEV_HAS_CHECKSUM))
3551                 return ethtool_op_set_tso(dev, value);
3552         else
3553                 return -EOPNOTSUPP;
3554 }
3555
3556 static void nv_get_ringparam(struct net_device *dev, struct ethtool_ringparam* ring)
3557 {
3558         struct fe_priv *np = netdev_priv(dev);
3559
3560         ring->rx_max_pending = (np->desc_ver == DESC_VER_1) ? RING_MAX_DESC_VER_1 : RING_MAX_DESC_VER_2_3;
3561         ring->rx_mini_max_pending = 0;
3562         ring->rx_jumbo_max_pending = 0;
3563         ring->tx_max_pending = (np->desc_ver == DESC_VER_1) ? RING_MAX_DESC_VER_1 : RING_MAX_DESC_VER_2_3;
3564
3565         ring->rx_pending = np->rx_ring_size;
3566         ring->rx_mini_pending = 0;
3567         ring->rx_jumbo_pending = 0;
3568         ring->tx_pending = np->tx_ring_size;
3569 }
3570
3571 static int nv_set_ringparam(struct net_device *dev, struct ethtool_ringparam* ring)
3572 {
3573         struct fe_priv *np = netdev_priv(dev);
3574         u8 __iomem *base = get_hwbase(dev);
3575         u8 *rxtx_ring, *rx_skbuff, *tx_skbuff;
3576         dma_addr_t ring_addr;
3577
3578         if (ring->rx_pending < RX_RING_MIN ||
3579             ring->tx_pending < TX_RING_MIN ||
3580             ring->rx_mini_pending != 0 ||
3581             ring->rx_jumbo_pending != 0 ||
3582             (np->desc_ver == DESC_VER_1 &&
3583              (ring->rx_pending > RING_MAX_DESC_VER_1 ||
3584               ring->tx_pending > RING_MAX_DESC_VER_1)) ||
3585             (np->desc_ver != DESC_VER_1 &&
3586              (ring->rx_pending > RING_MAX_DESC_VER_2_3 ||
3587               ring->tx_pending > RING_MAX_DESC_VER_2_3))) {
3588                 return -EINVAL;
3589         }
3590
3591         /* allocate new rings */
3592         if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) {
3593                 rxtx_ring = pci_alloc_consistent(np->pci_dev,
3594                                             sizeof(struct ring_desc) * (ring->rx_pending + ring->tx_pending),
3595                                             &ring_addr);
3596         } else {
3597                 rxtx_ring = pci_alloc_consistent(np->pci_dev,
3598                                             sizeof(struct ring_desc_ex) * (ring->rx_pending + ring->tx_pending),
3599                                             &ring_addr);
3600         }
3601         rx_skbuff = kmalloc(sizeof(struct nv_skb_map) * ring->rx_pending, GFP_KERNEL);
3602         tx_skbuff = kmalloc(sizeof(struct nv_skb_map) * ring->tx_pending, GFP_KERNEL);
3603         if (!rxtx_ring || !rx_skbuff || !tx_skbuff) {
3604                 /* fall back to old rings */
3605                 if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) {
3606                         if (rxtx_ring)
3607                                 pci_free_consistent(np->pci_dev, sizeof(struct ring_desc) * (ring->rx_pending + ring->tx_pending),
3608                                                     rxtx_ring, ring_addr);
3609                 } else {
3610                         if (rxtx_ring)
3611                                 pci_free_consistent(np->pci_dev, sizeof(struct ring_desc_ex) * (ring->rx_pending + ring->tx_pending),
3612                                                     rxtx_ring, ring_addr);
3613                 }
3614                 if (rx_skbuff)
3615                         kfree(rx_skbuff);
3616                 if (tx_skbuff)
3617                         kfree(tx_skbuff);
3618                 goto exit;
3619         }
3620
3621         if (netif_running(dev)) {
3622                 nv_disable_irq(dev);
3623                 netif_tx_lock_bh(dev);
3624                 spin_lock(&np->lock);
3625                 /* stop engines */
3626                 nv_stop_rx(dev);
3627                 nv_stop_tx(dev);
3628                 nv_txrx_reset(dev);
3629                 /* drain queues */
3630                 nv_drain_rx(dev);
3631                 nv_drain_tx(dev);
3632                 /* delete queues */
3633                 free_rings(dev);
3634         }
3635
3636         /* set new values */
3637         np->rx_ring_size = ring->rx_pending;
3638         np->tx_ring_size = ring->tx_pending;
3639         np->tx_limit_stop = TX_LIMIT_DIFFERENCE;
3640         np->tx_limit_start = TX_LIMIT_DIFFERENCE;
3641         if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) {
3642                 np->rx_ring.orig = (struct ring_desc*)rxtx_ring;
3643                 np->tx_ring.orig = &np->rx_ring.orig[np->rx_ring_size];
3644         } else {
3645                 np->rx_ring.ex = (struct ring_desc_ex*)rxtx_ring;
3646                 np->tx_ring.ex = &np->rx_ring.ex[np->rx_ring_size];
3647         }
3648         np->rx_skb = (struct nv_skb_map*)rx_skbuff;
3649         np->tx_skb = (struct nv_skb_map*)tx_skbuff;
3650         np->ring_addr = ring_addr;
3651
3652         memset(np->rx_skb, 0, sizeof(struct nv_skb_map) * np->rx_ring_size);
3653         memset(np->tx_skb, 0, sizeof(struct nv_skb_map) * np->tx_ring_size);
3654
3655         if (netif_running(dev)) {
3656                 /* reinit driver view of the queues */
3657                 set_bufsize(dev);
3658                 if (nv_init_ring(dev)) {
3659                         if (!np->in_shutdown)
3660                                 mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
3661                 }
3662
3663                 /* reinit nic view of the queues */
3664                 writel(np->rx_buf_sz, base + NvRegOffloadConfig);
3665                 setup_hw_rings(dev, NV_SETUP_RX_RING | NV_SETUP_TX_RING);
3666                 writel( ((np->rx_ring_size-1) << NVREG_RINGSZ_RXSHIFT) + ((np->tx_ring_size-1) << NVREG_RINGSZ_TXSHIFT),
3667                         base + NvRegRingSizes);
3668                 pci_push(base);
3669                 writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
3670                 pci_push(base);
3671
3672                 /* restart engines */
3673                 nv_start_rx(dev);
3674                 nv_start_tx(dev);
3675                 spin_unlock(&np->lock);
3676                 netif_tx_unlock_bh(dev);
3677                 nv_enable_irq(dev);
3678         }
3679         return 0;
3680 exit:
3681         return -ENOMEM;
3682 }
3683
3684 static void nv_get_pauseparam(struct net_device *dev, struct ethtool_pauseparam* pause)
3685 {
3686         struct fe_priv *np = netdev_priv(dev);
3687
3688         pause->autoneg = (np->pause_flags & NV_PAUSEFRAME_AUTONEG) != 0;
3689         pause->rx_pause = (np->pause_flags & NV_PAUSEFRAME_RX_ENABLE) != 0;
3690         pause->tx_pause = (np->pause_flags & NV_PAUSEFRAME_TX_ENABLE) != 0;
3691 }
3692
3693 static int nv_set_pauseparam(struct net_device *dev, struct ethtool_pauseparam* pause)
3694 {
3695         struct fe_priv *np = netdev_priv(dev);
3696         int adv, bmcr;
3697
3698         if ((!np->autoneg && np->duplex == 0) ||
3699             (np->autoneg && !pause->autoneg && np->duplex == 0)) {
3700                 printk(KERN_INFO "%s: can not set pause settings when forced link is in half duplex.\n",
3701                        dev->name);
3702                 return -EINVAL;
3703         }
3704         if (pause->tx_pause && !(np->pause_flags & NV_PAUSEFRAME_TX_CAPABLE)) {
3705                 printk(KERN_INFO "%s: hardware does not support tx pause frames.\n", dev->name);
3706                 return -EINVAL;
3707         }
3708
3709         netif_carrier_off(dev);
3710         if (netif_running(dev)) {
3711                 nv_disable_irq(dev);
3712                 netif_tx_lock_bh(dev);
3713                 spin_lock(&np->lock);
3714                 /* stop engines */
3715                 nv_stop_rx(dev);
3716                 nv_stop_tx(dev);
3717                 spin_unlock(&np->lock);
3718                 netif_tx_unlock_bh(dev);
3719         }
3720
3721         np->pause_flags &= ~(NV_PAUSEFRAME_RX_REQ|NV_PAUSEFRAME_TX_REQ);
3722         if (pause->rx_pause)
3723                 np->pause_flags |= NV_PAUSEFRAME_RX_REQ;
3724         if (pause->tx_pause)
3725                 np->pause_flags |= NV_PAUSEFRAME_TX_REQ;
3726
3727         if (np->autoneg && pause->autoneg) {
3728                 np->pause_flags |= NV_PAUSEFRAME_AUTONEG;
3729
3730                 adv = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ);
3731                 adv &= ~(ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
3732                 if (np->pause_flags & NV_PAUSEFRAME_RX_REQ) /* for rx we set both advertisments but disable tx pause */
3733                         adv |=  ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
3734                 if (np->pause_flags & NV_PAUSEFRAME_TX_REQ)
3735                         adv |=  ADVERTISE_PAUSE_ASYM;
3736                 mii_rw(dev, np->phyaddr, MII_ADVERTISE, adv);
3737
3738                 if (netif_running(dev))
3739                         printk(KERN_INFO "%s: link down.\n", dev->name);
3740                 bmcr = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
3741                 bmcr |= (BMCR_ANENABLE | BMCR_ANRESTART);
3742                 mii_rw(dev, np->phyaddr, MII_BMCR, bmcr);
3743         } else {
3744                 np->pause_flags &= ~(NV_PAUSEFRAME_AUTONEG|NV_PAUSEFRAME_RX_ENABLE|NV_PAUSEFRAME_TX_ENABLE);
3745                 if (pause->rx_pause)
3746                         np->pause_flags |= NV_PAUSEFRAME_RX_ENABLE;
3747                 if (pause->tx_pause)
3748                         np->pause_flags |= NV_PAUSEFRAME_TX_ENABLE;
3749
3750                 if (!netif_running(dev))
3751                         nv_update_linkspeed(dev);
3752                 else
3753                         nv_update_pause(dev, np->pause_flags);
3754         }
3755
3756         if (netif_running(dev)) {
3757                 nv_start_rx(dev);
3758                 nv_start_tx(dev);
3759                 nv_enable_irq(dev);
3760         }
3761         return 0;
3762 }
3763
3764 static u32 nv_get_rx_csum(struct net_device *dev)
3765 {
3766         struct fe_priv *np = netdev_priv(dev);
3767         return (np->rx_csum) != 0;
3768 }
3769
3770 static int nv_set_rx_csum(struct net_device *dev, u32 data)
3771 {
3772         struct fe_priv *np = netdev_priv(dev);
3773         u8 __iomem *base = get_hwbase(dev);
3774         int retcode = 0;
3775
3776         if (np->driver_data & DEV_HAS_CHECKSUM) {
3777                 if (data) {
3778                         np->rx_csum = 1;
3779                         np->txrxctl_bits |= NVREG_TXRXCTL_RXCHECK;
3780                 } else {
3781                         np->rx_csum = 0;
3782                         /* vlan is dependent on rx checksum offload */
3783                         if (!(np->vlanctl_bits & NVREG_VLANCONTROL_ENABLE))
3784                                 np->txrxctl_bits &= ~NVREG_TXRXCTL_RXCHECK;
3785                 }
3786                 if (netif_running(dev)) {
3787                         spin_lock_irq(&np->lock);
3788                         writel(np->txrxctl_bits, base + NvRegTxRxControl);
3789                         spin_unlock_irq(&np->lock);
3790                 }
3791         } else {
3792                 return -EINVAL;
3793         }
3794
3795         return retcode;
3796 }
3797
3798 static int nv_set_tx_csum(struct net_device *dev, u32 data)
3799 {
3800         struct fe_priv *np = netdev_priv(dev);
3801
3802         if (np->driver_data & DEV_HAS_CHECKSUM)
3803                 return ethtool_op_set_tx_hw_csum(dev, data);
3804         else
3805                 return -EOPNOTSUPP;
3806 }
3807
3808 static int nv_set_sg(struct net_device *dev, u32 data)
3809 {
3810         struct fe_priv *np = netdev_priv(dev);
3811
3812         if (np->driver_data & DEV_HAS_CHECKSUM)
3813                 return ethtool_op_set_sg(dev, data);
3814         else
3815                 return -EOPNOTSUPP;
3816 }
3817
3818 static int nv_get_stats_count(struct net_device *dev)
3819 {
3820         struct fe_priv *np = netdev_priv(dev);
3821
3822         if (np->driver_data & DEV_HAS_STATISTICS)
3823                 return sizeof(struct nv_ethtool_stats)/sizeof(u64);
3824         else
3825                 return 0;
3826 }
3827
3828 static void nv_get_ethtool_stats(struct net_device *dev, struct ethtool_stats *estats, u64 *buffer)
3829 {
3830         struct fe_priv *np = netdev_priv(dev);
3831
3832         /* update stats */
3833         nv_do_stats_poll((unsigned long)dev);
3834
3835         memcpy(buffer, &np->estats, nv_get_stats_count(dev)*sizeof(u64));
3836 }
3837
3838 static int nv_self_test_count(struct net_device *dev)
3839 {
3840         struct fe_priv *np = netdev_priv(dev);
3841
3842         if (np->driver_data & DEV_HAS_TEST_EXTENDED)
3843                 return NV_TEST_COUNT_EXTENDED;
3844         else
3845                 return NV_TEST_COUNT_BASE;
3846 }
3847
3848 static int nv_link_test(struct net_device *dev)
3849 {
3850         struct fe_priv *np = netdev_priv(dev);
3851         int mii_status;
3852
3853         mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ);
3854         mii_status = mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ);
3855
3856         /* check phy link status */
3857         if (!(mii_status & BMSR_LSTATUS))
3858                 return 0;
3859         else
3860                 return 1;
3861 }
3862
3863 static int nv_register_test(struct net_device *dev)
3864 {
3865         u8 __iomem *base = get_hwbase(dev);
3866         int i = 0;
3867         u32 orig_read, new_read;
3868
3869         do {
3870                 orig_read = readl(base + nv_registers_test[i].reg);
3871
3872                 /* xor with mask to toggle bits */
3873                 orig_read ^= nv_registers_test[i].mask;
3874
3875                 writel(orig_read, base + nv_registers_test[i].reg);
3876
3877                 new_read = readl(base + nv_registers_test[i].reg);
3878
3879                 if ((new_read & nv_registers_test[i].mask) != (orig_read & nv_registers_test[i].mask))
3880                         return 0;
3881
3882                 /* restore original value */
3883                 orig_read ^= nv_registers_test[i].mask;
3884                 writel(orig_read, base + nv_registers_test[i].reg);
3885
3886         } while (nv_registers_test[++i].reg != 0);
3887
3888         return 1;
3889 }
3890
3891 static int nv_interrupt_test(struct net_device *dev)
3892 {
3893         struct fe_priv *np = netdev_priv(dev);
3894         u8 __iomem *base = get_hwbase(dev);
3895         int ret = 1;
3896         int testcnt;
3897         u32 save_msi_flags, save_poll_interval = 0;
3898
3899         if (netif_running(dev)) {
3900                 /* free current irq */
3901                 nv_free_irq(dev);
3902                 save_poll_interval = readl(base+NvRegPollingInterval);
3903         }
3904
3905         /* flag to test interrupt handler */
3906         np->intr_test = 0;
3907
3908         /* setup test irq */
3909         save_msi_flags = np->msi_flags;
3910         np->msi_flags &= ~NV_MSI_X_VECTORS_MASK;
3911         np->msi_flags |= 0x001; /* setup 1 vector */
3912         if (nv_request_irq(dev, 1))
3913                 return 0;
3914
3915         /* setup timer interrupt */
3916         writel(NVREG_POLL_DEFAULT_CPU, base + NvRegPollingInterval);
3917         writel(NVREG_UNKSETUP6_VAL, base + NvRegUnknownSetupReg6);
3918
3919         nv_enable_hw_interrupts(dev, NVREG_IRQ_TIMER);
3920
3921         /* wait for at least one interrupt */
3922         msleep(100);
3923
3924         spin_lock_irq(&np->lock);
3925
3926         /* flag should be set within ISR */
3927         testcnt = np->intr_test;
3928         if (!testcnt)
3929                 ret = 2;
3930
3931         nv_disable_hw_interrupts(dev, NVREG_IRQ_TIMER);
3932         if (!(np->msi_flags & NV_MSI_X_ENABLED))
3933                 writel(NVREG_IRQSTAT_MASK, base + NvRegIrqStatus);
3934         else
3935                 writel(NVREG_IRQSTAT_MASK, base + NvRegMSIXIrqStatus);
3936
3937         spin_unlock_irq(&np->lock);
3938
3939         nv_free_irq(dev);
3940
3941         np->msi_flags = save_msi_flags;
3942
3943         if (netif_running(dev)) {
3944                 writel(save_poll_interval, base + NvRegPollingInterval);
3945                 writel(NVREG_UNKSETUP6_VAL, base + NvRegUnknownSetupReg6);
3946                 /* restore original irq */
3947                 if (nv_request_irq(dev, 0))
3948                         return 0;
3949         }
3950
3951         return ret;
3952 }
3953
3954 static int nv_loopback_test(struct net_device *dev)
3955 {
3956         struct fe_priv *np = netdev_priv(dev);
3957         u8 __iomem *base = get_hwbase(dev);
3958         struct sk_buff *tx_skb, *rx_skb;
3959         dma_addr_t test_dma_addr;
3960         u32 tx_flags_extra = (np->desc_ver == DESC_VER_1 ? NV_TX_LASTPACKET : NV_TX2_LASTPACKET);
3961         u32 flags;
3962         int len, i, pkt_len;
3963         u8 *pkt_data;
3964         u32 filter_flags = 0;
3965         u32 misc1_flags = 0;
3966         int ret = 1;
3967
3968         if (netif_running(dev)) {
3969                 nv_disable_irq(dev);
3970                 filter_flags = readl(base + NvRegPacketFilterFlags);
3971                 misc1_flags = readl(base + NvRegMisc1);
3972         } else {
3973                 nv_txrx_reset(dev);
3974         }
3975
3976         /* reinit driver view of the rx queue */
3977         set_bufsize(dev);
3978         nv_init_ring(dev);
3979
3980         /* setup hardware for loopback */
3981         writel(NVREG_MISC1_FORCE, base + NvRegMisc1);
3982         writel(NVREG_PFF_ALWAYS | NVREG_PFF_LOOPBACK, base + NvRegPacketFilterFlags);
3983
3984         /* reinit nic view of the rx queue */
3985         writel(np->rx_buf_sz, base + NvRegOffloadConfig);
3986         setup_hw_rings(dev, NV_SETUP_RX_RING | NV_SETUP_TX_RING);
3987         writel( ((np->rx_ring_size-1) << NVREG_RINGSZ_RXSHIFT) + ((np->tx_ring_size-1) << NVREG_RINGSZ_TXSHIFT),
3988                 base + NvRegRingSizes);
3989         pci_push(base);
3990
3991         /* restart rx engine */
3992         nv_start_rx(dev);
3993         nv_start_tx(dev);
3994
3995         /* setup packet for tx */
3996         pkt_len = ETH_DATA_LEN;
3997         tx_skb = dev_alloc_skb(pkt_len);
3998         if (!tx_skb) {
3999                 printk(KERN_ERR "dev_alloc_skb() failed during loopback test"
4000                          " of %s\n", dev->name);
4001                 ret = 0;
4002                 goto out;
4003         }
4004         pkt_data = skb_put(tx_skb, pkt_len);
4005         for (i = 0; i < pkt_len; i++)
4006                 pkt_data[i] = (u8)(i & 0xff);
4007         test_dma_addr = pci_map_single(np->pci_dev, tx_skb->data,
4008                                        tx_skb->end-tx_skb->data, PCI_DMA_FROMDEVICE);
4009
4010         if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) {
4011                 np->tx_ring.orig[0].buf = cpu_to_le32(test_dma_addr);
4012                 np->tx_ring.orig[0].flaglen = cpu_to_le32((pkt_len-1) | np->tx_flags | tx_flags_extra);
4013         } else {
4014                 np->tx_ring.ex[0].bufhigh = cpu_to_le64(test_dma_addr) >> 32;
4015                 np->tx_ring.ex[0].buflow = cpu_to_le64(test_dma_addr) & 0x0FFFFFFFF;
4016                 np->tx_ring.ex[0].flaglen = cpu_to_le32((pkt_len-1) | np->tx_flags | tx_flags_extra);
4017         }
4018         writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
4019         pci_push(get_hwbase(dev));
4020
4021         msleep(500);
4022
4023         /* check for rx of the packet */
4024         if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) {
4025                 flags = le32_to_cpu(np->rx_ring.orig[0].flaglen);
4026                 len = nv_descr_getlength(&np->rx_ring.orig[0], np->desc_ver);
4027
4028         } else {
4029                 flags = le32_to_cpu(np->rx_ring.ex[0].flaglen);
4030                 len = nv_descr_getlength_ex(&np->rx_ring.ex[0], np->desc_ver);
4031         }
4032
4033         if (flags & NV_RX_AVAIL) {
4034                 ret = 0;
4035         } else if (np->desc_ver == DESC_VER_1) {
4036                 if (flags & NV_RX_ERROR)
4037                         ret = 0;
4038         } else {
4039                 if (flags & NV_RX2_ERROR) {
4040                         ret = 0;
4041                 }
4042         }
4043
4044         if (ret) {
4045                 if (len != pkt_len) {
4046                         ret = 0;
4047                         dprintk(KERN_DEBUG "%s: loopback len mismatch %d vs %d\n",
4048                                 dev->name, len, pkt_len);
4049                 } else {
4050                         rx_skb = np->rx_skb[0].skb;
4051                         for (i = 0; i < pkt_len; i++) {
4052                                 if (rx_skb->data[i] != (u8)(i & 0xff)) {
4053                                         ret = 0;
4054                                         dprintk(KERN_DEBUG "%s: loopback pattern check failed on byte %d\n",
4055                                                 dev->name, i);
4056                                         break;
4057                                 }
4058                         }
4059                 }
4060         } else {
4061                 dprintk(KERN_DEBUG "%s: loopback - did not receive test packet\n", dev->name);
4062         }
4063
4064         pci_unmap_page(np->pci_dev, test_dma_addr,
4065                        tx_skb->end-tx_skb->data,
4066                        PCI_DMA_TODEVICE);
4067         dev_kfree_skb_any(tx_skb);
4068  out:
4069         /* stop engines */
4070         nv_stop_rx(dev);
4071         nv_stop_tx(dev);
4072         nv_txrx_reset(dev);
4073         /* drain rx queue */
4074         nv_drain_rx(dev);
4075         nv_drain_tx(dev);
4076
4077         if (netif_running(dev)) {
4078                 writel(misc1_flags, base + NvRegMisc1);
4079                 writel(filter_flags, base + NvRegPacketFilterFlags);
4080                 nv_enable_irq(dev);
4081         }
4082
4083         return ret;
4084 }
4085
4086 static void nv_self_test(struct net_device *dev, struct ethtool_test *test, u64 *buffer)
4087 {
4088         struct fe_priv *np = netdev_priv(dev);
4089         u8 __iomem *base = get_hwbase(dev);
4090         int result;
4091         memset(buffer, 0, nv_self_test_count(dev)*sizeof(u64));
4092
4093         if (!nv_link_test(dev)) {
4094                 test->flags |= ETH_TEST_FL_FAILED;
4095                 buffer[0] = 1;
4096         }
4097
4098         if (test->flags & ETH_TEST_FL_OFFLINE) {
4099                 if (netif_running(dev)) {
4100                         netif_stop_queue(dev);
4101                         netif_poll_disable(dev);
4102                         netif_tx_lock_bh(dev);
4103                         spin_lock_irq(&np->lock);
4104                         nv_disable_hw_interrupts(dev, np->irqmask);
4105                         if (!(np->msi_flags & NV_MSI_X_ENABLED)) {
4106                                 writel(NVREG_IRQSTAT_MASK, base + NvRegIrqStatus);
4107                         } else {
4108                                 writel(NVREG_IRQSTAT_MASK, base + NvRegMSIXIrqStatus);
4109                         }
4110                         /* stop engines */
4111                         nv_stop_rx(dev);
4112                         nv_stop_tx(dev);
4113                         nv_txrx_reset(dev);
4114                         /* drain rx queue */
4115                         nv_drain_rx(dev);
4116                         nv_drain_tx(dev);
4117                         spin_unlock_irq(&np->lock);
4118                         netif_tx_unlock_bh(dev);
4119                 }
4120
4121                 if (!nv_register_test(dev)) {
4122                         test->flags |= ETH_TEST_FL_FAILED;
4123                         buffer[1] = 1;
4124                 }
4125
4126                 result = nv_interrupt_test(dev);
4127                 if (result != 1) {
4128                         test->flags |= ETH_TEST_FL_FAILED;
4129                         buffer[2] = 1;
4130                 }
4131                 if (result == 0) {
4132                         /* bail out */
4133                         return;
4134                 }
4135
4136                 if (!nv_loopback_test(dev)) {
4137                         test->flags |= ETH_TEST_FL_FAILED;
4138                         buffer[3] = 1;
4139                 }
4140
4141                 if (netif_running(dev)) {
4142                         /* reinit driver view of the rx queue */
4143                         set_bufsize(dev);
4144                         if (nv_init_ring(dev)) {
4145                                 if (!np->in_shutdown)
4146                                         mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
4147                         }
4148                         /* reinit nic view of the rx queue */
4149                         writel(np->rx_buf_sz, base + NvRegOffloadConfig);
4150                         setup_hw_rings(dev, NV_SETUP_RX_RING | NV_SETUP_TX_RING);
4151                         writel( ((np->rx_ring_size-1) << NVREG_RINGSZ_RXSHIFT) + ((np->tx_ring_size-1) << NVREG_RINGSZ_TXSHIFT),
4152                                 base + NvRegRingSizes);
4153                         pci_push(base);
4154                         writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
4155                         pci_push(base);
4156                         /* restart rx engine */
4157                         nv_start_rx(dev);
4158                         nv_start_tx(dev);
4159                         netif_start_queue(dev);
4160                         netif_poll_enable(dev);
4161                         nv_enable_hw_interrupts(dev, np->irqmask);
4162                 }
4163         }
4164 }
4165
4166 static void nv_get_strings(struct net_device *dev, u32 stringset, u8 *buffer)
4167 {
4168         switch (stringset) {
4169         case ETH_SS_STATS:
4170                 memcpy(buffer, &nv_estats_str, nv_get_stats_count(dev)*sizeof(struct nv_ethtool_str));
4171                 break;
4172         case ETH_SS_TEST:
4173                 memcpy(buffer, &nv_etests_str, nv_self_test_count(dev)*sizeof(struct nv_ethtool_str));
4174                 break;
4175         }
4176 }
4177
4178 static const struct ethtool_ops ops = {
4179         .get_drvinfo = nv_get_drvinfo,
4180         .get_link = ethtool_op_get_link,
4181         .get_wol = nv_get_wol,
4182         .set_wol = nv_set_wol,
4183         .get_settings = nv_get_settings,
4184         .set_settings = nv_set_settings,
4185         .get_regs_len = nv_get_regs_len,
4186         .get_regs = nv_get_regs,
4187         .nway_reset = nv_nway_reset,
4188         .get_perm_addr = ethtool_op_get_perm_addr,
4189         .get_tso = ethtool_op_get_tso,
4190         .set_tso = nv_set_tso,
4191         .get_ringparam = nv_get_ringparam,
4192         .set_ringparam = nv_set_ringparam,
4193         .get_pauseparam = nv_get_pauseparam,
4194         .set_pauseparam = nv_set_pauseparam,
4195         .get_rx_csum = nv_get_rx_csum,
4196         .set_rx_csum = nv_set_rx_csum,
4197         .get_tx_csum = ethtool_op_get_tx_csum,
4198         .set_tx_csum = nv_set_tx_csum,
4199         .get_sg = ethtool_op_get_sg,
4200         .set_sg = nv_set_sg,
4201         .get_strings = nv_get_strings,
4202         .get_stats_count = nv_get_stats_count,
4203         .get_ethtool_stats = nv_get_ethtool_stats,
4204         .self_test_count = nv_self_test_count,
4205         .self_test = nv_self_test,
4206 };
4207
4208 static void nv_vlan_rx_register(struct net_device *dev, struct vlan_group *grp)
4209 {
4210         struct fe_priv *np = get_nvpriv(dev);
4211
4212         spin_lock_irq(&np->lock);
4213
4214         /* save vlan group */
4215         np->vlangrp = grp;
4216
4217         if (grp) {
4218                 /* enable vlan on MAC */
4219                 np->txrxctl_bits |= NVREG_TXRXCTL_VLANSTRIP | NVREG_TXRXCTL_VLANINS;
4220         } else {
4221                 /* disable vlan on MAC */
4222                 np->txrxctl_bits &= ~NVREG_TXRXCTL_VLANSTRIP;
4223                 np->txrxctl_bits &= ~NVREG_TXRXCTL_VLANINS;
4224         }
4225
4226         writel(np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
4227
4228         spin_unlock_irq(&np->lock);
4229 };
4230
4231 static void nv_vlan_rx_kill_vid(struct net_device *dev, unsigned short vid)
4232 {
4233         /* nothing to do */
4234 };
4235
4236 /* The mgmt unit and driver use a semaphore to access the phy during init */
4237 static int nv_mgmt_acquire_sema(struct net_device *dev)
4238 {
4239         u8 __iomem *base = get_hwbase(dev);
4240         int i;
4241         u32 tx_ctrl, mgmt_sema;
4242
4243         for (i = 0; i < 10; i++) {
4244                 mgmt_sema = readl(base + NvRegTransmitterControl) & NVREG_XMITCTL_MGMT_SEMA_MASK;
4245                 if (mgmt_sema == NVREG_XMITCTL_MGMT_SEMA_FREE)
4246                         break;
4247                 msleep(500);
4248         }
4249
4250         if (mgmt_sema != NVREG_XMITCTL_MGMT_SEMA_FREE)
4251                 return 0;
4252
4253         for (i = 0; i < 2; i++) {
4254                 tx_ctrl = readl(base + NvRegTransmitterControl);
4255                 tx_ctrl |= NVREG_XMITCTL_HOST_SEMA_ACQ;
4256                 writel(tx_ctrl, base + NvRegTransmitterControl);
4257
4258                 /* verify that semaphore was acquired */
4259                 tx_ctrl = readl(base + NvRegTransmitterControl);
4260                 if (((tx_ctrl & NVREG_XMITCTL_HOST_SEMA_MASK) == NVREG_XMITCTL_HOST_SEMA_ACQ) &&
4261                     ((tx_ctrl & NVREG_XMITCTL_MGMT_SEMA_MASK) == NVREG_XMITCTL_MGMT_SEMA_FREE))
4262                         return 1;
4263                 else
4264                         udelay(50);
4265         }
4266
4267         return 0;
4268 }
4269
4270 static int nv_open(struct net_device *dev)
4271 {
4272         struct fe_priv *np = netdev_priv(dev);
4273         u8 __iomem *base = get_hwbase(dev);
4274         int ret = 1;
4275         int oom, i;
4276
4277         dprintk(KERN_DEBUG "nv_open: begin\n");
4278
4279         /* erase previous misconfiguration */
4280         if (np->driver_data & DEV_HAS_POWER_CNTRL)
4281                 nv_mac_reset(dev);
4282         writel(NVREG_MCASTADDRA_FORCE, base + NvRegMulticastAddrA);
4283         writel(0, base + NvRegMulticastAddrB);
4284         writel(0, base + NvRegMulticastMaskA);
4285         writel(0, base + NvRegMulticastMaskB);
4286         writel(0, base + NvRegPacketFilterFlags);
4287
4288         writel(0, base + NvRegTransmitterControl);
4289         writel(0, base + NvRegReceiverControl);
4290
4291         writel(0, base + NvRegAdapterControl);
4292
4293         if (np->pause_flags & NV_PAUSEFRAME_TX_CAPABLE)
4294                 writel(NVREG_TX_PAUSEFRAME_DISABLE,  base + NvRegTxPauseFrame);
4295
4296         /* initialize descriptor rings */
4297         set_bufsize(dev);
4298         oom = nv_init_ring(dev);
4299
4300         writel(0, base + NvRegLinkSpeed);
4301         writel(readl(base + NvRegTransmitPoll) & NVREG_TRANSMITPOLL_MAC_ADDR_REV, base + NvRegTransmitPoll);
4302         nv_txrx_reset(dev);
4303         writel(0, base + NvRegUnknownSetupReg6);
4304
4305         np->in_shutdown = 0;
4306
4307         /* give hw rings */
4308         setup_hw_rings(dev, NV_SETUP_RX_RING | NV_SETUP_TX_RING);
4309         writel( ((np->rx_ring_size-1) << NVREG_RINGSZ_RXSHIFT) + ((np->tx_ring_size-1) << NVREG_RINGSZ_TXSHIFT),
4310                 base + NvRegRingSizes);
4311
4312         writel(np->linkspeed, base + NvRegLinkSpeed);
4313         if (np->desc_ver == DESC_VER_1)
4314                 writel(NVREG_TX_WM_DESC1_DEFAULT, base + NvRegTxWatermark);
4315         else
4316                 writel(NVREG_TX_WM_DESC2_3_DEFAULT, base + NvRegTxWatermark);
4317         writel(np->txrxctl_bits, base + NvRegTxRxControl);
4318         writel(np->vlanctl_bits, base + NvRegVlanControl);
4319         pci_push(base);
4320         writel(NVREG_TXRXCTL_BIT1|np->txrxctl_bits, base + NvRegTxRxControl);
4321         reg_delay(dev, NvRegUnknownSetupReg5, NVREG_UNKSETUP5_BIT31, NVREG_UNKSETUP5_BIT31,
4322                         NV_SETUP5_DELAY, NV_SETUP5_DELAYMAX,
4323                         KERN_INFO "open: SetupReg5, Bit 31 remained off\n");
4324
4325         writel(0, base + NvRegMIIMask);
4326         writel(NVREG_IRQSTAT_MASK, base + NvRegIrqStatus);
4327         writel(NVREG_MIISTAT_MASK2, base + NvRegMIIStatus);
4328
4329         writel(NVREG_MISC1_FORCE | NVREG_MISC1_HD, base + NvRegMisc1);
4330         writel(readl(base + NvRegTransmitterStatus), base + NvRegTransmitterStatus);
4331         writel(NVREG_PFF_ALWAYS, base + NvRegPacketFilterFlags);
4332         writel(np->rx_buf_sz, base + NvRegOffloadConfig);
4333
4334         writel(readl(base + NvRegReceiverStatus), base + NvRegReceiverStatus);
4335         get_random_bytes(&i, sizeof(i));
4336         writel(NVREG_RNDSEED_FORCE | (i&NVREG_RNDSEED_MASK), base + NvRegRandomSeed);
4337         writel(NVREG_TX_DEFERRAL_DEFAULT, base + NvRegTxDeferral);
4338         writel(NVREG_RX_DEFERRAL_DEFAULT, base + NvRegRxDeferral);
4339         if (poll_interval == -1) {
4340                 if (optimization_mode == NV_OPTIMIZATION_MODE_THROUGHPUT)
4341                         writel(NVREG_POLL_DEFAULT_THROUGHPUT, base + NvRegPollingInterval);
4342                 else
4343                         writel(NVREG_POLL_DEFAULT_CPU, base + NvRegPollingInterval);
4344         }
4345         else
4346                 writel(poll_interval & 0xFFFF, base + NvRegPollingInterval);
4347         writel(NVREG_UNKSETUP6_VAL, base + NvRegUnknownSetupReg6);
4348         writel((np->phyaddr << NVREG_ADAPTCTL_PHYSHIFT)|NVREG_ADAPTCTL_PHYVALID|NVREG_ADAPTCTL_RUNNING,
4349                         base + NvRegAdapterControl);
4350         writel(NVREG_MIISPEED_BIT8|NVREG_MIIDELAY, base + NvRegMIISpeed);
4351         writel(NVREG_MII_LINKCHANGE, base + NvRegMIIMask);
4352         if (np->wolenabled)
4353                 writel(NVREG_WAKEUPFLAGS_ENABLE , base + NvRegWakeUpFlags);
4354
4355         i = readl(base + NvRegPowerState);
4356         if ( (i & NVREG_POWERSTATE_POWEREDUP) == 0)
4357                 writel(NVREG_POWERSTATE_POWEREDUP|i, base + NvRegPowerState);
4358
4359         pci_push(base);
4360         udelay(10);
4361         writel(readl(base + NvRegPowerState) | NVREG_POWERSTATE_VALID, base + NvRegPowerState);
4362
4363         nv_disable_hw_interrupts(dev, np->irqmask);
4364         pci_push(base);
4365         writel(NVREG_MIISTAT_MASK2, base + NvRegMIIStatus);
4366         writel(NVREG_IRQSTAT_MASK, base + NvRegIrqStatus);
4367         pci_push(base);
4368
4369         if (nv_request_irq(dev, 0)) {
4370                 goto out_drain;
4371         }
4372
4373         /* ask for interrupts */
4374         nv_enable_hw_interrupts(dev, np->irqmask);
4375
4376         spin_lock_irq(&np->lock);
4377         writel(NVREG_MCASTADDRA_FORCE, base + NvRegMulticastAddrA);
4378         writel(0, base + NvRegMulticastAddrB);
4379         writel(0, base + NvRegMulticastMaskA);
4380         writel(0, base + NvRegMulticastMaskB);
4381         writel(NVREG_PFF_ALWAYS|NVREG_PFF_MYADDR, base + NvRegPacketFilterFlags);
4382         /* One manual link speed update: Interrupts are enabled, future link
4383          * speed changes cause interrupts and are handled by nv_link_irq().
4384          */
4385         {
4386                 u32 miistat;
4387                 miistat = readl(base + NvRegMIIStatus);
4388                 writel(NVREG_MIISTAT_MASK, base + NvRegMIIStatus);
4389                 dprintk(KERN_INFO "startup: got 0x%08x.\n", miistat);
4390         }
4391         /* set linkspeed to invalid value, thus force nv_update_linkspeed
4392          * to init hw */
4393         np->linkspeed = 0;
4394         ret = nv_update_linkspeed(dev);
4395         nv_start_rx(dev);
4396         nv_start_tx(dev);
4397         netif_start_queue(dev);
4398         netif_poll_enable(dev);
4399
4400         if (ret) {
4401                 netif_carrier_on(dev);
4402         } else {
4403                 printk("%s: no link during initialization.\n", dev->name);
4404                 netif_carrier_off(dev);
4405         }
4406         if (oom)
4407                 mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
4408
4409         /* start statistics timer */
4410         if (np->driver_data & DEV_HAS_STATISTICS)
4411                 mod_timer(&np->stats_poll, jiffies + STATS_INTERVAL);
4412
4413         spin_unlock_irq(&np->lock);
4414
4415         return 0;
4416 out_drain:
4417         drain_ring(dev);
4418         return ret;
4419 }
4420
4421 static int nv_close(struct net_device *dev)
4422 {
4423         struct fe_priv *np = netdev_priv(dev);
4424         u8 __iomem *base;
4425
4426         spin_lock_irq(&np->lock);
4427         np->in_shutdown = 1;
4428         spin_unlock_irq(&np->lock);
4429         netif_poll_disable(dev);
4430         synchronize_irq(dev->irq);
4431
4432         del_timer_sync(&np->oom_kick);
4433         del_timer_sync(&np->nic_poll);
4434         del_timer_sync(&np->stats_poll);
4435
4436         netif_stop_queue(dev);
4437         spin_lock_irq(&np->lock);
4438         nv_stop_tx(dev);
4439         nv_stop_rx(dev);
4440         nv_txrx_reset(dev);
4441
4442         /* disable interrupts on the nic or we will lock up */
4443         base = get_hwbase(dev);
4444         nv_disable_hw_interrupts(dev, np->irqmask);
4445         pci_push(base);
4446         dprintk(KERN_INFO "%s: Irqmask is zero again\n", dev->name);
4447
4448         spin_unlock_irq(&np->lock);
4449
4450         nv_free_irq(dev);
4451
4452         drain_ring(dev);
4453
4454         if (np->wolenabled)
4455                 nv_start_rx(dev);
4456
4457         /* FIXME: power down nic */
4458
4459         return 0;
4460 }
4461
4462 static int __devinit nv_probe(struct pci_dev *pci_dev, const struct pci_device_id *id)
4463 {
4464         struct net_device *dev;
4465         struct fe_priv *np;
4466         unsigned long addr;
4467         u8 __iomem *base;
4468         int err, i;
4469         u32 powerstate, txreg;
4470         u32 phystate_orig = 0, phystate;
4471         int phyinitialized = 0;
4472
4473         dev = alloc_etherdev(sizeof(struct fe_priv));
4474         err = -ENOMEM;
4475         if (!dev)
4476                 goto out;
4477
4478         np = netdev_priv(dev);
4479         np->pci_dev = pci_dev;
4480         spin_lock_init(&np->lock);
4481         SET_MODULE_OWNER(dev);
4482         SET_NETDEV_DEV(dev, &pci_dev->dev);
4483
4484         init_timer(&np->oom_kick);
4485         np->oom_kick.data = (unsigned long) dev;
4486         np->oom_kick.function = &nv_do_rx_refill;       /* timer handler */
4487         init_timer(&np->nic_poll);
4488         np->nic_poll.data = (unsigned long) dev;
4489         np->nic_poll.function = &nv_do_nic_poll;        /* timer handler */
4490         init_timer(&np->stats_poll);
4491         np->stats_poll.data = (unsigned long) dev;
4492         np->stats_poll.function = &nv_do_stats_poll;    /* timer handler */
4493
4494         err = pci_enable_device(pci_dev);
4495         if (err) {
4496                 printk(KERN_INFO "forcedeth: pci_enable_dev failed (%d) for device %s\n",
4497                                 err, pci_name(pci_dev));
4498                 goto out_free;
4499         }
4500
4501         pci_set_master(pci_dev);
4502
4503         err = pci_request_regions(pci_dev, DRV_NAME);
4504         if (err < 0)
4505                 goto out_disable;
4506
4507         if (id->driver_data & (DEV_HAS_VLAN|DEV_HAS_MSI_X|DEV_HAS_POWER_CNTRL|DEV_HAS_STATISTICS))
4508                 np->register_size = NV_PCI_REGSZ_VER2;
4509         else
4510                 np->register_size = NV_PCI_REGSZ_VER1;
4511
4512         err = -EINVAL;
4513         addr = 0;
4514         for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) {
4515                 dprintk(KERN_DEBUG "%s: resource %d start %p len %ld flags 0x%08lx.\n",
4516                                 pci_name(pci_dev), i, (void*)pci_resource_start(pci_dev, i),
4517                                 pci_resource_len(pci_dev, i),
4518                                 pci_resource_flags(pci_dev, i));
4519                 if (pci_resource_flags(pci_dev, i) & IORESOURCE_MEM &&
4520                                 pci_resource_len(pci_dev, i) >= np->register_size) {
4521                         addr = pci_resource_start(pci_dev, i);
4522                         break;
4523                 }
4524         }
4525         if (i == DEVICE_COUNT_RESOURCE) {
4526                 printk(KERN_INFO "forcedeth: Couldn't find register window for device %s.\n",
4527                                         pci_name(pci_dev));
4528                 goto out_relreg;
4529         }
4530
4531         /* copy of driver data */
4532         np->driver_data = id->driver_data;
4533
4534         /* handle different descriptor versions */
4535         if (id->driver_data & DEV_HAS_HIGH_DMA) {
4536                 /* packet format 3: supports 40-bit addressing */
4537                 np->desc_ver = DESC_VER_3;
4538                 np->txrxctl_bits = NVREG_TXRXCTL_DESC_3;
4539                 if (dma_64bit) {
4540                         if (pci_set_dma_mask(pci_dev, DMA_39BIT_MASK)) {
4541                                 printk(KERN_INFO "forcedeth: 64-bit DMA failed, using 32-bit addressing for device %s.\n",
4542                                        pci_name(pci_dev));
4543                         } else {
4544                                 dev->features |= NETIF_F_HIGHDMA;
4545                                 printk(KERN_INFO "forcedeth: using HIGHDMA\n");
4546                         }
4547                         if (pci_set_consistent_dma_mask(pci_dev, DMA_39BIT_MASK)) {
4548                                 printk(KERN_INFO "forcedeth: 64-bit DMA (consistent) failed, using 32-bit ring buffers for device %s.\n",
4549                                        pci_name(pci_dev));
4550                         }
4551                 }
4552         } else if (id->driver_data & DEV_HAS_LARGEDESC) {
4553                 /* packet format 2: supports jumbo frames */
4554                 np->desc_ver = DESC_VER_2;
4555                 np->txrxctl_bits = NVREG_TXRXCTL_DESC_2;
4556         } else {
4557                 /* original packet format */
4558                 np->desc_ver = DESC_VER_1;
4559                 np->txrxctl_bits = NVREG_TXRXCTL_DESC_1;
4560         }
4561
4562         np->pkt_limit = NV_PKTLIMIT_1;
4563         if (id->driver_data & DEV_HAS_LARGEDESC)
4564                 np->pkt_limit = NV_PKTLIMIT_2;
4565
4566         if (id->driver_data & DEV_HAS_CHECKSUM) {
4567                 np->rx_csum = 1;
4568                 np->txrxctl_bits |= NVREG_TXRXCTL_RXCHECK;
4569                 dev->features |= NETIF_F_HW_CSUM | NETIF_F_SG;
4570                 dev->features |= NETIF_F_TSO;
4571         }
4572
4573         np->vlanctl_bits = 0;
4574         if (id->driver_data & DEV_HAS_VLAN) {
4575                 np->vlanctl_bits = NVREG_VLANCONTROL_ENABLE;
4576                 dev->features |= NETIF_F_HW_VLAN_RX | NETIF_F_HW_VLAN_TX;
4577                 dev->vlan_rx_register = nv_vlan_rx_register;
4578                 dev->vlan_rx_kill_vid = nv_vlan_rx_kill_vid;
4579         }
4580
4581         np->msi_flags = 0;
4582         if ((id->driver_data & DEV_HAS_MSI) && msi) {
4583                 np->msi_flags |= NV_MSI_CAPABLE;
4584         }
4585         if ((id->driver_data & DEV_HAS_MSI_X) && msix) {
4586                 np->msi_flags |= NV_MSI_X_CAPABLE;
4587         }
4588
4589         np->pause_flags = NV_PAUSEFRAME_RX_CAPABLE | NV_PAUSEFRAME_RX_REQ | NV_PAUSEFRAME_AUTONEG;
4590         if (id->driver_data & DEV_HAS_PAUSEFRAME_TX) {
4591                 np->pause_flags |= NV_PAUSEFRAME_TX_CAPABLE | NV_PAUSEFRAME_TX_REQ;
4592         }
4593
4594
4595         err = -ENOMEM;
4596         np->base = ioremap(addr, np->register_size);
4597         if (!np->base)
4598                 goto out_relreg;
4599         dev->base_addr = (unsigned long)np->base;
4600
4601         dev->irq = pci_dev->irq;
4602
4603         np->rx_ring_size = RX_RING_DEFAULT;
4604         np->tx_ring_size = TX_RING_DEFAULT;
4605         np->tx_limit_stop = TX_LIMIT_DIFFERENCE;
4606         np->tx_limit_start = TX_LIMIT_DIFFERENCE;
4607
4608         if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) {
4609                 np->rx_ring.orig = pci_alloc_consistent(pci_dev,
4610                                         sizeof(struct ring_desc) * (np->rx_ring_size + np->tx_ring_size),
4611                                         &np->ring_addr);
4612                 if (!np->rx_ring.orig)
4613                         goto out_unmap;
4614                 np->tx_ring.orig = &np->rx_ring.orig[np->rx_ring_size];
4615         } else {
4616                 np->rx_ring.ex = pci_alloc_consistent(pci_dev,
4617                                         sizeof(struct ring_desc_ex) * (np->rx_ring_size + np->tx_ring_size),
4618                                         &np->ring_addr);
4619                 if (!np->rx_ring.ex)
4620                         goto out_unmap;
4621                 np->tx_ring.ex = &np->rx_ring.ex[np->rx_ring_size];
4622         }
4623         np->rx_skb = kmalloc(sizeof(struct nv_skb_map) * np->rx_ring_size, GFP_KERNEL);
4624         np->tx_skb = kmalloc(sizeof(struct nv_skb_map) * np->tx_ring_size, GFP_KERNEL);
4625         if (!np->rx_skb || !np->tx_skb)
4626                 goto out_freering;
4627         memset(np->rx_skb, 0, sizeof(struct nv_skb_map) * np->rx_ring_size);
4628         memset(np->tx_skb, 0, sizeof(struct nv_skb_map) * np->tx_ring_size);
4629
4630         dev->open = nv_open;
4631         dev->stop = nv_close;
4632         dev->hard_start_xmit = nv_start_xmit;
4633         dev->get_stats = nv_get_stats;
4634         dev->change_mtu = nv_change_mtu;
4635         dev->set_mac_address = nv_set_mac_address;
4636         dev->set_multicast_list = nv_set_multicast;
4637 #ifdef CONFIG_NET_POLL_CONTROLLER
4638         dev->poll_controller = nv_poll_controller;
4639 #endif
4640         dev->weight = 64;
4641 #ifdef CONFIG_FORCEDETH_NAPI
4642         dev->poll = nv_napi_poll;
4643 #endif
4644         SET_ETHTOOL_OPS(dev, &ops);
4645         dev->tx_timeout = nv_tx_timeout;
4646         dev->watchdog_timeo = NV_WATCHDOG_TIMEO;
4647
4648         pci_set_drvdata(pci_dev, dev);
4649
4650         /* read the mac address */
4651         base = get_hwbase(dev);
4652         np->orig_mac[0] = readl(base + NvRegMacAddrA);
4653         np->orig_mac[1] = readl(base + NvRegMacAddrB);
4654
4655         /* check the workaround bit for correct mac address order */
4656         txreg = readl(base + NvRegTransmitPoll);
4657         if (txreg & NVREG_TRANSMITPOLL_MAC_ADDR_REV) {
4658                 /* mac address is already in correct order */
4659                 dev->dev_addr[0] = (np->orig_mac[0] >>  0) & 0xff;
4660                 dev->dev_addr[1] = (np->orig_mac[0] >>  8) & 0xff;
4661                 dev->dev_addr[2] = (np->orig_mac[0] >> 16) & 0xff;
4662                 dev->dev_addr[3] = (np->orig_mac[0] >> 24) & 0xff;
4663                 dev->dev_addr[4] = (np->orig_mac[1] >>  0) & 0xff;
4664                 dev->dev_addr[5] = (np->orig_mac[1] >>  8) & 0xff;
4665         } else {
4666                 /* need to reverse mac address to correct order */
4667                 dev->dev_addr[0] = (np->orig_mac[1] >>  8) & 0xff;
4668                 dev->dev_addr[1] = (np->orig_mac[1] >>  0) & 0xff;
4669                 dev->dev_addr[2] = (np->orig_mac[0] >> 24) & 0xff;
4670                 dev->dev_addr[3] = (np->orig_mac[0] >> 16) & 0xff;
4671                 dev->dev_addr[4] = (np->orig_mac[0] >>  8) & 0xff;
4672                 dev->dev_addr[5] = (np->orig_mac[0] >>  0) & 0xff;
4673                 /* set permanent address to be correct aswell */
4674                 np->orig_mac[0] = (dev->dev_addr[0] << 0) + (dev->dev_addr[1] << 8) +
4675                         (dev->dev_addr[2] << 16) + (dev->dev_addr[3] << 24);
4676                 np->orig_mac[1] = (dev->dev_addr[4] << 0) + (dev->dev_addr[5] << 8);
4677                 writel(txreg|NVREG_TRANSMITPOLL_MAC_ADDR_REV, base + NvRegTransmitPoll);
4678         }
4679         memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
4680
4681         if (!is_valid_ether_addr(dev->perm_addr)) {
4682                 /*
4683                  * Bad mac address. At least one bios sets the mac address
4684                  * to 01:23:45:67:89:ab
4685                  */
4686                 printk(KERN_ERR "%s: Invalid Mac address detected: %02x:%02x:%02x:%02x:%02x:%02x\n",
4687                         pci_name(pci_dev),
4688                         dev->dev_addr[0], dev->dev_addr[1], dev->dev_addr[2],
4689                         dev->dev_addr[3], dev->dev_addr[4], dev->dev_addr[5]);
4690                 printk(KERN_ERR "Please complain to your hardware vendor. Switching to a random MAC.\n");
4691                 dev->dev_addr[0] = 0x00;
4692                 dev->dev_addr[1] = 0x00;
4693                 dev->dev_addr[2] = 0x6c;
4694                 get_random_bytes(&dev->dev_addr[3], 3);
4695         }
4696
4697         dprintk(KERN_DEBUG "%s: MAC Address %02x:%02x:%02x:%02x:%02x:%02x\n", pci_name(pci_dev),
4698                         dev->dev_addr[0], dev->dev_addr[1], dev->dev_addr[2],
4699                         dev->dev_addr[3], dev->dev_addr[4], dev->dev_addr[5]);
4700
4701         /* set mac address */
4702         nv_copy_mac_to_hw(dev);
4703
4704         /* disable WOL */
4705         writel(0, base + NvRegWakeUpFlags);
4706         np->wolenabled = 0;
4707
4708         if (id->driver_data & DEV_HAS_POWER_CNTRL) {
4709                 u8 revision_id;
4710                 pci_read_config_byte(pci_dev, PCI_REVISION_ID, &revision_id);
4711
4712                 /* take phy and nic out of low power mode */
4713                 powerstate = readl(base + NvRegPowerState2);
4714                 powerstate &= ~NVREG_POWERSTATE2_POWERUP_MASK;
4715                 if ((id->device == PCI_DEVICE_ID_NVIDIA_NVENET_12 ||
4716                      id->device == PCI_DEVICE_ID_NVIDIA_NVENET_13) &&
4717                     revision_id >= 0xA3)
4718                         powerstate |= NVREG_POWERSTATE2_POWERUP_REV_A3;
4719                 writel(powerstate, base + NvRegPowerState2);
4720         }
4721
4722         if (np->desc_ver == DESC_VER_1) {
4723                 np->tx_flags = NV_TX_VALID;
4724         } else {
4725                 np->tx_flags = NV_TX2_VALID;
4726         }
4727         if (optimization_mode == NV_OPTIMIZATION_MODE_THROUGHPUT) {
4728                 np->irqmask = NVREG_IRQMASK_THROUGHPUT;
4729                 if (np->msi_flags & NV_MSI_X_CAPABLE) /* set number of vectors */
4730                         np->msi_flags |= 0x0003;
4731         } else {
4732                 np->irqmask = NVREG_IRQMASK_CPU;
4733                 if (np->msi_flags & NV_MSI_X_CAPABLE) /* set number of vectors */
4734                         np->msi_flags |= 0x0001;
4735         }
4736
4737         if (id->driver_data & DEV_NEED_TIMERIRQ)
4738                 np->irqmask |= NVREG_IRQ_TIMER;
4739         if (id->driver_data & DEV_NEED_LINKTIMER) {
4740                 dprintk(KERN_INFO "%s: link timer on.\n", pci_name(pci_dev));
4741                 np->need_linktimer = 1;
4742                 np->link_timeout = jiffies + LINK_TIMEOUT;
4743         } else {
4744                 dprintk(KERN_INFO "%s: link timer off.\n", pci_name(pci_dev));
4745                 np->need_linktimer = 0;
4746         }
4747
4748         /* clear phy state and temporarily halt phy interrupts */
4749         writel(0, base + NvRegMIIMask);
4750         phystate = readl(base + NvRegAdapterControl);
4751         if (phystate & NVREG_ADAPTCTL_RUNNING) {
4752                 phystate_orig = 1;
4753                 phystate &= ~NVREG_ADAPTCTL_RUNNING;
4754                 writel(phystate, base + NvRegAdapterControl);
4755         }
4756         writel(NVREG_MIISTAT_MASK, base + NvRegMIIStatus);
4757
4758         if (id->driver_data & DEV_HAS_MGMT_UNIT) {
4759                 /* management unit running on the mac? */
4760                 if (readl(base + NvRegTransmitterControl) & NVREG_XMITCTL_SYNC_PHY_INIT) {
4761                         np->mac_in_use = readl(base + NvRegTransmitterControl) & NVREG_XMITCTL_MGMT_ST;
4762                         dprintk(KERN_INFO "%s: mgmt unit is running. mac in use %x.\n", pci_name(pci_dev), np->mac_in_use);
4763                         for (i = 0; i < 5000; i++) {
4764                                 msleep(1);
4765                                 if (nv_mgmt_acquire_sema(dev)) {
4766                                         /* management unit setup the phy already? */
4767                                         if ((readl(base + NvRegTransmitterControl) & NVREG_XMITCTL_SYNC_MASK) ==
4768                                             NVREG_XMITCTL_SYNC_PHY_INIT) {
4769                                                 /* phy is inited by mgmt unit */
4770                                                 phyinitialized = 1;
4771                                                 dprintk(KERN_INFO "%s: Phy already initialized by mgmt unit.\n", pci_name(pci_dev));
4772                                         } else {
4773                                                 /* we need to init the phy */
4774                                         }
4775                                         break;
4776                                 }
4777                         }
4778                 }
4779         }
4780
4781         /* find a suitable phy */
4782         for (i = 1; i <= 32; i++) {
4783                 int id1, id2;
4784                 int phyaddr = i & 0x1F;
4785
4786                 spin_lock_irq(&np->lock);
4787                 id1 = mii_rw(dev, phyaddr, MII_PHYSID1, MII_READ);
4788                 spin_unlock_irq(&np->lock);
4789                 if (id1 < 0 || id1 == 0xffff)
4790                         continue;
4791                 spin_lock_irq(&np->lock);
4792                 id2 = mii_rw(dev, phyaddr, MII_PHYSID2, MII_READ);
4793                 spin_unlock_irq(&np->lock);
4794                 if (id2 < 0 || id2 == 0xffff)
4795                         continue;
4796
4797                 np->phy_model = id2 & PHYID2_MODEL_MASK;
4798                 id1 = (id1 & PHYID1_OUI_MASK) << PHYID1_OUI_SHFT;
4799                 id2 = (id2 & PHYID2_OUI_MASK) >> PHYID2_OUI_SHFT;
4800                 dprintk(KERN_DEBUG "%s: open: Found PHY %04x:%04x at address %d.\n",
4801                         pci_name(pci_dev), id1, id2, phyaddr);
4802                 np->phyaddr = phyaddr;
4803                 np->phy_oui = id1 | id2;
4804                 break;
4805         }
4806         if (i == 33) {
4807                 printk(KERN_INFO "%s: open: Could not find a valid PHY.\n",
4808                        pci_name(pci_dev));
4809                 goto out_error;
4810         }
4811
4812         if (!phyinitialized) {
4813                 /* reset it */
4814                 phy_init(dev);
4815         } else {
4816                 /* see if it is a gigabit phy */
4817                 u32 mii_status = mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ);
4818                 if (mii_status & PHY_GIGABIT) {
4819                         np->gigabit = PHY_GIGABIT;
4820                 }
4821         }
4822
4823         /* set default link speed settings */
4824         np->linkspeed = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
4825         np->duplex = 0;
4826         np->autoneg = 1;
4827
4828         err = register_netdev(dev);
4829         if (err) {
4830                 printk(KERN_INFO "forcedeth: unable to register netdev: %d\n", err);
4831                 goto out_error;
4832         }
4833         printk(KERN_INFO "%s: forcedeth.c: subsystem: %05x:%04x bound to %s\n",
4834                         dev->name, pci_dev->subsystem_vendor, pci_dev->subsystem_device,
4835                         pci_name(pci_dev));
4836
4837         return 0;
4838
4839 out_error:
4840         if (phystate_orig)
4841                 writel(phystate|NVREG_ADAPTCTL_RUNNING, base + NvRegAdapterControl);
4842         pci_set_drvdata(pci_dev, NULL);
4843 out_freering:
4844         free_rings(dev);
4845 out_unmap:
4846         iounmap(get_hwbase(dev));
4847 out_relreg:
4848         pci_release_regions(pci_dev);
4849 out_disable:
4850         pci_disable_device(pci_dev);
4851 out_free:
4852         free_netdev(dev);
4853 out:
4854         return err;
4855 }
4856
4857 static void __devexit nv_remove(struct pci_dev *pci_dev)
4858 {
4859         struct net_device *dev = pci_get_drvdata(pci_dev);
4860         struct fe_priv *np = netdev_priv(dev);
4861         u8 __iomem *base = get_hwbase(dev);
4862
4863         unregister_netdev(dev);
4864
4865         /* special op: write back the misordered MAC address - otherwise
4866          * the next nv_probe would see a wrong address.
4867          */
4868         writel(np->orig_mac[0], base + NvRegMacAddrA);
4869         writel(np->orig_mac[1], base + NvRegMacAddrB);
4870
4871         /* free all structures */
4872         free_rings(dev);
4873         iounmap(get_hwbase(dev));
4874         pci_release_regions(pci_dev);
4875         pci_disable_device(pci_dev);
4876         free_netdev(dev);
4877         pci_set_drvdata(pci_dev, NULL);
4878 }
4879
4880 #ifdef CONFIG_PM
4881 static int nv_suspend(struct pci_dev *pdev, pm_message_t state)
4882 {
4883         struct net_device *dev = pci_get_drvdata(pdev);
4884         struct fe_priv *np = netdev_priv(dev);
4885
4886         if (!netif_running(dev))
4887                 goto out;
4888
4889         netif_device_detach(dev);
4890
4891         // Gross.
4892         nv_close(dev);
4893
4894         pci_save_state(pdev);
4895         pci_enable_wake(pdev, pci_choose_state(pdev, state), np->wolenabled);
4896         pci_set_power_state(pdev, pci_choose_state(pdev, state));
4897 out:
4898         return 0;
4899 }
4900
4901 static int nv_resume(struct pci_dev *pdev)
4902 {
4903         struct net_device *dev = pci_get_drvdata(pdev);
4904         int rc = 0;
4905
4906         if (!netif_running(dev))
4907                 goto out;
4908
4909         netif_device_attach(dev);
4910
4911         pci_set_power_state(pdev, PCI_D0);
4912         pci_restore_state(pdev);
4913         pci_enable_wake(pdev, PCI_D0, 0);
4914
4915         rc = nv_open(dev);
4916 out:
4917         return rc;
4918 }
4919 #else
4920 #define nv_suspend NULL
4921 #define nv_resume NULL
4922 #endif /* CONFIG_PM */
4923
4924 static struct pci_device_id pci_tbl[] = {
4925         {       /* nForce Ethernet Controller */
4926                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_1),
4927                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER,
4928         },
4929         {       /* nForce2 Ethernet Controller */
4930                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_2),
4931                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER,
4932         },
4933         {       /* nForce3 Ethernet Controller */
4934                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_3),
4935                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER,
4936         },
4937         {       /* nForce3 Ethernet Controller */
4938                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_4),
4939                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM,
4940         },
4941         {       /* nForce3 Ethernet Controller */
4942                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_5),
4943                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM,
4944         },
4945         {       /* nForce3 Ethernet Controller */
4946                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_6),
4947                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM,
4948         },
4949         {       /* nForce3 Ethernet Controller */
4950                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_7),
4951                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM,
4952         },
4953         {       /* CK804 Ethernet Controller */
4954                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_8),
4955                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA,
4956         },
4957         {       /* CK804 Ethernet Controller */
4958                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_9),
4959                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA,
4960         },
4961         {       /* MCP04 Ethernet Controller */
4962                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_10),
4963                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA,
4964         },
4965         {       /* MCP04 Ethernet Controller */
4966                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_11),
4967                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA,
4968         },
4969         {       /* MCP51 Ethernet Controller */
4970                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_12),
4971                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL,
4972         },
4973         {       /* MCP51 Ethernet Controller */
4974                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_13),
4975                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL,
4976         },
4977         {       /* MCP55 Ethernet Controller */
4978                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_14),
4979                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_VLAN|DEV_HAS_MSI|DEV_HAS_MSI_X|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX|DEV_HAS_STATISTICS|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT,
4980         },
4981         {       /* MCP55 Ethernet Controller */
4982                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_15),
4983                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_VLAN|DEV_HAS_MSI|DEV_HAS_MSI_X|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX|DEV_HAS_STATISTICS|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT,
4984         },
4985         {       /* MCP61 Ethernet Controller */
4986                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_16),
4987                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX|DEV_HAS_STATISTICS|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT,
4988         },
4989         {       /* MCP61 Ethernet Controller */
4990                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_17),
4991                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX|DEV_HAS_STATISTICS|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT,
4992         },
4993         {       /* MCP61 Ethernet Controller */
4994                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_18),
4995                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX|DEV_HAS_STATISTICS|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT,
4996         },
4997         {       /* MCP61 Ethernet Controller */
4998                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_19),
4999                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX|DEV_HAS_STATISTICS|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT,
5000         },
5001         {       /* MCP65 Ethernet Controller */
5002                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_20),
5003                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX|DEV_HAS_STATISTICS|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT,
5004         },
5005         {       /* MCP65 Ethernet Controller */
5006                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_21),
5007                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX|DEV_HAS_STATISTICS|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT,
5008         },
5009         {       /* MCP65 Ethernet Controller */
5010                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_22),
5011                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX|DEV_HAS_STATISTICS|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT,
5012         },
5013         {       /* MCP65 Ethernet Controller */
5014                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_23),
5015                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX|DEV_HAS_STATISTICS|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT,
5016         },
5017         {       /* MCP67 Ethernet Controller */
5018                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_24),
5019                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX|DEV_HAS_STATISTICS|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT,
5020         },
5021         {       /* MCP67 Ethernet Controller */
5022                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_25),
5023                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX|DEV_HAS_STATISTICS|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT,
5024         },
5025         {       /* MCP67 Ethernet Controller */
5026                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_26),
5027                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX|DEV_HAS_STATISTICS|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT,
5028         },
5029         {       /* MCP67 Ethernet Controller */
5030                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_27),
5031                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX|DEV_HAS_STATISTICS|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT,
5032         },
5033         {0,},
5034 };
5035
5036 static struct pci_driver driver = {
5037         .name = "forcedeth",
5038         .id_table = pci_tbl,
5039         .probe = nv_probe,
5040         .remove = __devexit_p(nv_remove),
5041         .suspend = nv_suspend,
5042         .resume = nv_resume,
5043 };
5044
5045 static int __init init_nic(void)
5046 {
5047         printk(KERN_INFO "forcedeth.c: Reverse Engineered nForce ethernet driver. Version %s.\n", FORCEDETH_VERSION);
5048         return pci_register_driver(&driver);
5049 }
5050
5051 static void __exit exit_nic(void)
5052 {
5053         pci_unregister_driver(&driver);
5054 }
5055
5056 module_param(max_interrupt_work, int, 0);
5057 MODULE_PARM_DESC(max_interrupt_work, "forcedeth maximum events handled per interrupt");
5058 module_param(optimization_mode, int, 0);
5059 MODULE_PARM_DESC(optimization_mode, "In throughput mode (0), every tx & rx packet will generate an interrupt. In CPU mode (1), interrupts are controlled by a timer.");
5060 module_param(poll_interval, int, 0);
5061 MODULE_PARM_DESC(poll_interval, "Interval determines how frequent timer interrupt is generated by [(time_in_micro_secs * 100) / (2^10)]. Min is 0 and Max is 65535.");
5062 module_param(msi, int, 0);
5063 MODULE_PARM_DESC(msi, "MSI interrupts are enabled by setting to 1 and disabled by setting to 0.");
5064 module_param(msix, int, 0);
5065 MODULE_PARM_DESC(msix, "MSIX interrupts are enabled by setting to 1 and disabled by setting to 0.");
5066 module_param(dma_64bit, int, 0);
5067 MODULE_PARM_DESC(dma_64bit, "High DMA is enabled by setting to 1 and disabled by setting to 0.");
5068
5069 MODULE_AUTHOR("Manfred Spraul <manfred@colorfullife.com>");
5070 MODULE_DESCRIPTION("Reverse Engineered nForce ethernet driver");
5071 MODULE_LICENSE("GPL");
5072
5073 MODULE_DEVICE_TABLE(pci, pci_tbl);
5074
5075 module_init(init_nic);
5076 module_exit(exit_nic);