2 * Fast Ethernet Controller (FEC) driver for Motorola MPC8xx.
3 * Copyright (c) 1997 Dan Malek (dmalek@jlc.net)
5 * This version of the driver is specific to the FADS implementation,
6 * since the board contains control registers external to the processor
7 * for the control of the LevelOne LXT970 transceiver. The MPC860T manual
8 * describes connections using the internal parallel port I/O, which
9 * is basically all of Port D.
11 * Right now, I am very wasteful with the buffers. I allocate memory
12 * pages and then divide them into 2K frame buffers. This way I know I
13 * have buffers large enough to hold one frame within one buffer descriptor.
14 * Once I get this working, I will use 64 or 128 byte CPM buffers, which
15 * will be much more memory efficient and will easily handle lots of
18 * Much better multiple PHY support by Magnus Damm.
19 * Copyright (c) 2000 Ericsson Radio Systems AB.
21 * Support for FEC controller of ColdFire processors.
22 * Copyright (c) 2001-2005 Greg Ungerer (gerg@snapgear.com)
24 * Bug fixes and cleanup by Philippe De Muyter (phdm@macqel.be)
25 * Copyright (c) 2004-2006 Macq Electronique SA.
28 #include <linux/module.h>
29 #include <linux/kernel.h>
30 #include <linux/string.h>
31 #include <linux/ptrace.h>
32 #include <linux/errno.h>
33 #include <linux/ioport.h>
34 #include <linux/slab.h>
35 #include <linux/interrupt.h>
36 #include <linux/pci.h>
37 #include <linux/init.h>
38 #include <linux/delay.h>
39 #include <linux/netdevice.h>
40 #include <linux/etherdevice.h>
41 #include <linux/skbuff.h>
42 #include <linux/spinlock.h>
43 #include <linux/workqueue.h>
44 #include <linux/bitops.h>
47 #include <asm/uaccess.h>
49 #include <asm/pgtable.h>
50 #include <asm/cacheflush.h>
52 #if defined(CONFIG_M523x) || defined(CONFIG_M527x) || \
53 defined(CONFIG_M5272) || defined(CONFIG_M528x) || \
54 defined(CONFIG_M520x) || defined(CONFIG_M532x)
55 #include <asm/coldfire.h>
56 #include <asm/mcfsim.h>
59 #include <asm/8xx_immap.h>
60 #include <asm/mpc8xx.h>
64 #if defined(CONFIG_FEC2)
65 #define FEC_MAX_PORTS 2
67 #define FEC_MAX_PORTS 1
70 #if defined(CONFIG_FADS) || defined(CONFIG_RPXCLASSIC) || defined(CONFIG_M5272)
71 #define HAVE_mii_link_interrupt
75 * Define the fixed address of the FEC hardware.
77 static unsigned int fec_hw[] = {
78 #if defined(CONFIG_M5272)
80 #elif defined(CONFIG_M527x)
83 #elif defined(CONFIG_M523x) || defined(CONFIG_M528x)
85 #elif defined(CONFIG_M520x)
87 #elif defined(CONFIG_M532x)
88 (MCF_MBAR+0xfc030000),
90 &(((immap_t *)IMAP_ADDR)->im_cpm.cp_fec),
94 static unsigned char fec_mac_default[] = {
95 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
99 * Some hardware gets it MAC address out of local flash memory.
100 * if this is non-zero then assume it is the address to get MAC from.
102 #if defined(CONFIG_NETtel)
103 #define FEC_FLASHMAC 0xf0006006
104 #elif defined(CONFIG_GILBARCONAP) || defined(CONFIG_SCALES)
105 #define FEC_FLASHMAC 0xf0006000
106 #elif defined(CONFIG_CANCam)
107 #define FEC_FLASHMAC 0xf0020000
108 #elif defined (CONFIG_M5272C3)
109 #define FEC_FLASHMAC (0xffe04000 + 4)
110 #elif defined(CONFIG_MOD5272)
111 #define FEC_FLASHMAC 0xffc0406b
113 #define FEC_FLASHMAC 0
116 /* Forward declarations of some structures to support different PHYs
121 void (*funct)(uint mii_reg, struct net_device *dev);
128 const phy_cmd_t *config;
129 const phy_cmd_t *startup;
130 const phy_cmd_t *ack_int;
131 const phy_cmd_t *shutdown;
134 /* The number of Tx and Rx buffers. These are allocated from the page
135 * pool. The code may assume these are power of two, so it it best
136 * to keep them that size.
137 * We don't need to allocate pages for the transmitter. We just use
138 * the skbuffer directly.
140 #define FEC_ENET_RX_PAGES 8
141 #define FEC_ENET_RX_FRSIZE 2048
142 #define FEC_ENET_RX_FRPPG (PAGE_SIZE / FEC_ENET_RX_FRSIZE)
143 #define RX_RING_SIZE (FEC_ENET_RX_FRPPG * FEC_ENET_RX_PAGES)
144 #define FEC_ENET_TX_FRSIZE 2048
145 #define FEC_ENET_TX_FRPPG (PAGE_SIZE / FEC_ENET_TX_FRSIZE)
146 #define TX_RING_SIZE 16 /* Must be power of two */
147 #define TX_RING_MOD_MASK 15 /* for this to work */
149 #if (((RX_RING_SIZE + TX_RING_SIZE) * 8) > PAGE_SIZE)
150 #error "FEC: descriptor ring size constants too large"
153 /* Interrupt events/masks.
155 #define FEC_ENET_HBERR ((uint)0x80000000) /* Heartbeat error */
156 #define FEC_ENET_BABR ((uint)0x40000000) /* Babbling receiver */
157 #define FEC_ENET_BABT ((uint)0x20000000) /* Babbling transmitter */
158 #define FEC_ENET_GRA ((uint)0x10000000) /* Graceful stop complete */
159 #define FEC_ENET_TXF ((uint)0x08000000) /* Full frame transmitted */
160 #define FEC_ENET_TXB ((uint)0x04000000) /* A buffer was transmitted */
161 #define FEC_ENET_RXF ((uint)0x02000000) /* Full frame received */
162 #define FEC_ENET_RXB ((uint)0x01000000) /* A buffer was received */
163 #define FEC_ENET_MII ((uint)0x00800000) /* MII interrupt */
164 #define FEC_ENET_EBERR ((uint)0x00400000) /* SDMA bus error */
166 /* The FEC stores dest/src/type, data, and checksum for receive packets.
168 #define PKT_MAXBUF_SIZE 1518
169 #define PKT_MINBUF_SIZE 64
170 #define PKT_MAXBLR_SIZE 1520
174 * The 5270/5271/5280/5282/532x RX control register also contains maximum frame
175 * size bits. Other FEC hardware does not, so we need to take that into
176 * account when setting it.
178 #if defined(CONFIG_M523x) || defined(CONFIG_M527x) || defined(CONFIG_M528x) || \
179 defined(CONFIG_M520x) || defined(CONFIG_M532x)
180 #define OPT_FRAME_SIZE (PKT_MAXBUF_SIZE << 16)
182 #define OPT_FRAME_SIZE 0
185 /* The FEC buffer descriptors track the ring buffers. The rx_bd_base and
186 * tx_bd_base always point to the base of the buffer descriptors. The
187 * cur_rx and cur_tx point to the currently available buffer.
188 * The dirty_tx tracks the current buffer that is being sent by the
189 * controller. The cur_tx and dirty_tx are equal under both completely
190 * empty and completely full conditions. The empty/ready indicator in
191 * the buffer descriptor determines the actual condition.
193 struct fec_enet_private {
194 /* Hardware registers of the FEC device */
197 struct net_device *netdev;
199 /* The saved address of a sent-in-place packet/buffer, for skfree(). */
200 unsigned char *tx_bounce[TX_RING_SIZE];
201 struct sk_buff* tx_skbuff[TX_RING_SIZE];
205 /* CPM dual port RAM relative addresses.
207 cbd_t *rx_bd_base; /* Address of Rx and Tx buffers. */
209 cbd_t *cur_rx, *cur_tx; /* The next free ring entry */
210 cbd_t *dirty_tx; /* The ring entries to be free()ed. */
218 phy_info_t const *phy;
219 struct work_struct phy_task;
222 uint mii_phy_task_queued;
233 static int fec_enet_open(struct net_device *dev);
234 static int fec_enet_start_xmit(struct sk_buff *skb, struct net_device *dev);
235 static void fec_enet_mii(struct net_device *dev);
236 static irqreturn_t fec_enet_interrupt(int irq, void * dev_id);
237 static void fec_enet_tx(struct net_device *dev);
238 static void fec_enet_rx(struct net_device *dev);
239 static int fec_enet_close(struct net_device *dev);
240 static void set_multicast_list(struct net_device *dev);
241 static void fec_restart(struct net_device *dev, int duplex);
242 static void fec_stop(struct net_device *dev);
243 static void fec_set_mac_address(struct net_device *dev);
246 /* MII processing. We keep this as simple as possible. Requests are
247 * placed on the list (if there is room). When the request is finished
248 * by the MII, an optional function may be called.
250 typedef struct mii_list {
252 void (*mii_func)(uint val, struct net_device *dev);
253 struct mii_list *mii_next;
257 static mii_list_t mii_cmds[NMII];
258 static mii_list_t *mii_free;
259 static mii_list_t *mii_head;
260 static mii_list_t *mii_tail;
262 static int mii_queue(struct net_device *dev, int request,
263 void (*func)(uint, struct net_device *));
265 /* Make MII read/write commands for the FEC.
267 #define mk_mii_read(REG) (0x60020000 | ((REG & 0x1f) << 18))
268 #define mk_mii_write(REG, VAL) (0x50020000 | ((REG & 0x1f) << 18) | \
272 /* Transmitter timeout.
274 #define TX_TIMEOUT (2*HZ)
276 /* Register definitions for the PHY.
279 #define MII_REG_CR 0 /* Control Register */
280 #define MII_REG_SR 1 /* Status Register */
281 #define MII_REG_PHYIR1 2 /* PHY Identification Register 1 */
282 #define MII_REG_PHYIR2 3 /* PHY Identification Register 2 */
283 #define MII_REG_ANAR 4 /* A-N Advertisement Register */
284 #define MII_REG_ANLPAR 5 /* A-N Link Partner Ability Register */
285 #define MII_REG_ANER 6 /* A-N Expansion Register */
286 #define MII_REG_ANNPTR 7 /* A-N Next Page Transmit Register */
287 #define MII_REG_ANLPRNPR 8 /* A-N Link Partner Received Next Page Reg. */
289 /* values for phy_status */
291 #define PHY_CONF_ANE 0x0001 /* 1 auto-negotiation enabled */
292 #define PHY_CONF_LOOP 0x0002 /* 1 loopback mode enabled */
293 #define PHY_CONF_SPMASK 0x00f0 /* mask for speed */
294 #define PHY_CONF_10HDX 0x0010 /* 10 Mbit half duplex supported */
295 #define PHY_CONF_10FDX 0x0020 /* 10 Mbit full duplex supported */
296 #define PHY_CONF_100HDX 0x0040 /* 100 Mbit half duplex supported */
297 #define PHY_CONF_100FDX 0x0080 /* 100 Mbit full duplex supported */
299 #define PHY_STAT_LINK 0x0100 /* 1 up - 0 down */
300 #define PHY_STAT_FAULT 0x0200 /* 1 remote fault */
301 #define PHY_STAT_ANC 0x0400 /* 1 auto-negotiation complete */
302 #define PHY_STAT_SPMASK 0xf000 /* mask for speed */
303 #define PHY_STAT_10HDX 0x1000 /* 10 Mbit half duplex selected */
304 #define PHY_STAT_10FDX 0x2000 /* 10 Mbit full duplex selected */
305 #define PHY_STAT_100HDX 0x4000 /* 100 Mbit half duplex selected */
306 #define PHY_STAT_100FDX 0x8000 /* 100 Mbit full duplex selected */
310 fec_enet_start_xmit(struct sk_buff *skb, struct net_device *dev)
312 struct fec_enet_private *fep;
313 volatile fec_t *fecp;
315 unsigned short status;
317 fep = netdev_priv(dev);
318 fecp = (volatile fec_t*)dev->base_addr;
321 /* Link is down or autonegotiation is in progress. */
325 /* Fill in a Tx ring entry */
328 status = bdp->cbd_sc;
329 #ifndef final_version
330 if (status & BD_ENET_TX_READY) {
331 /* Ooops. All transmit buffers are full. Bail out.
332 * This should not happen, since dev->tbusy should be set.
334 printk("%s: tx queue full!.\n", dev->name);
339 /* Clear all of the status flags.
341 status &= ~BD_ENET_TX_STATS;
343 /* Set buffer length and buffer pointer.
345 bdp->cbd_bufaddr = __pa(skb->data);
346 bdp->cbd_datlen = skb->len;
349 * On some FEC implementations data must be aligned on
350 * 4-byte boundaries. Use bounce buffers to copy data
351 * and get it aligned. Ugh.
353 if (bdp->cbd_bufaddr & 0x3) {
355 index = bdp - fep->tx_bd_base;
356 memcpy(fep->tx_bounce[index], (void *) bdp->cbd_bufaddr, bdp->cbd_datlen);
357 bdp->cbd_bufaddr = __pa(fep->tx_bounce[index]);
362 fep->tx_skbuff[fep->skb_cur] = skb;
364 dev->stats.tx_bytes += skb->len;
365 fep->skb_cur = (fep->skb_cur+1) & TX_RING_MOD_MASK;
367 /* Push the data cache so the CPM does not get stale memory
370 flush_dcache_range((unsigned long)skb->data,
371 (unsigned long)skb->data + skb->len);
373 spin_lock_irq(&fep->lock);
375 /* Send it on its way. Tell FEC it's ready, interrupt when done,
376 * it's the last BD of the frame, and to put the CRC on the end.
379 status |= (BD_ENET_TX_READY | BD_ENET_TX_INTR
380 | BD_ENET_TX_LAST | BD_ENET_TX_TC);
381 bdp->cbd_sc = status;
383 dev->trans_start = jiffies;
385 /* Trigger transmission start */
386 fecp->fec_x_des_active = 0;
388 /* If this was the last BD in the ring, start at the beginning again.
390 if (status & BD_ENET_TX_WRAP) {
391 bdp = fep->tx_bd_base;
396 if (bdp == fep->dirty_tx) {
398 netif_stop_queue(dev);
401 fep->cur_tx = (cbd_t *)bdp;
403 spin_unlock_irq(&fep->lock);
409 fec_timeout(struct net_device *dev)
411 struct fec_enet_private *fep = netdev_priv(dev);
413 printk("%s: transmit timed out.\n", dev->name);
414 dev->stats.tx_errors++;
415 #ifndef final_version
420 printk("Ring data dump: cur_tx %lx%s, dirty_tx %lx cur_rx: %lx\n",
421 (unsigned long)fep->cur_tx, fep->tx_full ? " (full)" : "",
422 (unsigned long)fep->dirty_tx,
423 (unsigned long)fep->cur_rx);
425 bdp = fep->tx_bd_base;
426 printk(" tx: %u buffers\n", TX_RING_SIZE);
427 for (i = 0 ; i < TX_RING_SIZE; i++) {
428 printk(" %08x: %04x %04x %08x\n",
432 (int) bdp->cbd_bufaddr);
436 bdp = fep->rx_bd_base;
437 printk(" rx: %lu buffers\n", (unsigned long) RX_RING_SIZE);
438 for (i = 0 ; i < RX_RING_SIZE; i++) {
439 printk(" %08x: %04x %04x %08x\n",
443 (int) bdp->cbd_bufaddr);
448 fec_restart(dev, fep->full_duplex);
449 netif_wake_queue(dev);
452 /* The interrupt handler.
453 * This is called from the MPC core interrupt.
456 fec_enet_interrupt(int irq, void * dev_id)
458 struct net_device *dev = dev_id;
459 volatile fec_t *fecp;
463 fecp = (volatile fec_t*)dev->base_addr;
465 /* Get the interrupt events that caused us to be here.
467 while ((int_events = fecp->fec_ievent) != 0) {
468 fecp->fec_ievent = int_events;
470 /* Handle receive event in its own function.
472 if (int_events & FEC_ENET_RXF) {
477 /* Transmit OK, or non-fatal error. Update the buffer
478 descriptors. FEC handles all errors, we just discover
479 them as part of the transmit process.
481 if (int_events & FEC_ENET_TXF) {
486 if (int_events & FEC_ENET_MII) {
492 return IRQ_RETVAL(handled);
497 fec_enet_tx(struct net_device *dev)
499 struct fec_enet_private *fep;
501 unsigned short status;
504 fep = netdev_priv(dev);
505 spin_lock(&fep->lock);
508 while (((status = bdp->cbd_sc) & BD_ENET_TX_READY) == 0) {
509 if (bdp == fep->cur_tx && fep->tx_full == 0) break;
511 skb = fep->tx_skbuff[fep->skb_dirty];
512 /* Check for errors. */
513 if (status & (BD_ENET_TX_HB | BD_ENET_TX_LC |
514 BD_ENET_TX_RL | BD_ENET_TX_UN |
516 dev->stats.tx_errors++;
517 if (status & BD_ENET_TX_HB) /* No heartbeat */
518 dev->stats.tx_heartbeat_errors++;
519 if (status & BD_ENET_TX_LC) /* Late collision */
520 dev->stats.tx_window_errors++;
521 if (status & BD_ENET_TX_RL) /* Retrans limit */
522 dev->stats.tx_aborted_errors++;
523 if (status & BD_ENET_TX_UN) /* Underrun */
524 dev->stats.tx_fifo_errors++;
525 if (status & BD_ENET_TX_CSL) /* Carrier lost */
526 dev->stats.tx_carrier_errors++;
528 dev->stats.tx_packets++;
531 #ifndef final_version
532 if (status & BD_ENET_TX_READY)
533 printk("HEY! Enet xmit interrupt and TX_READY.\n");
535 /* Deferred means some collisions occurred during transmit,
536 * but we eventually sent the packet OK.
538 if (status & BD_ENET_TX_DEF)
539 dev->stats.collisions++;
541 /* Free the sk buffer associated with this last transmit.
543 dev_kfree_skb_any(skb);
544 fep->tx_skbuff[fep->skb_dirty] = NULL;
545 fep->skb_dirty = (fep->skb_dirty + 1) & TX_RING_MOD_MASK;
547 /* Update pointer to next buffer descriptor to be transmitted.
549 if (status & BD_ENET_TX_WRAP)
550 bdp = fep->tx_bd_base;
554 /* Since we have freed up a buffer, the ring is no longer
559 if (netif_queue_stopped(dev))
560 netif_wake_queue(dev);
563 fep->dirty_tx = (cbd_t *)bdp;
564 spin_unlock(&fep->lock);
568 /* During a receive, the cur_rx points to the current incoming buffer.
569 * When we update through the ring, if the next incoming buffer has
570 * not been given to the system, we just set the empty indicator,
571 * effectively tossing the packet.
574 fec_enet_rx(struct net_device *dev)
576 struct fec_enet_private *fep;
577 volatile fec_t *fecp;
579 unsigned short status;
588 fep = netdev_priv(dev);
589 fecp = (volatile fec_t*)dev->base_addr;
591 /* First, grab all of the stats for the incoming packet.
592 * These get messed up if we get called due to a busy condition.
596 while (!((status = bdp->cbd_sc) & BD_ENET_RX_EMPTY)) {
598 #ifndef final_version
599 /* Since we have allocated space to hold a complete frame,
600 * the last indicator should be set.
602 if ((status & BD_ENET_RX_LAST) == 0)
603 printk("FEC ENET: rcv is not +last\n");
607 goto rx_processing_done;
609 /* Check for errors. */
610 if (status & (BD_ENET_RX_LG | BD_ENET_RX_SH | BD_ENET_RX_NO |
611 BD_ENET_RX_CR | BD_ENET_RX_OV)) {
612 dev->stats.rx_errors++;
613 if (status & (BD_ENET_RX_LG | BD_ENET_RX_SH)) {
614 /* Frame too long or too short. */
615 dev->stats.rx_length_errors++;
617 if (status & BD_ENET_RX_NO) /* Frame alignment */
618 dev->stats.rx_frame_errors++;
619 if (status & BD_ENET_RX_CR) /* CRC Error */
620 dev->stats.rx_crc_errors++;
621 if (status & BD_ENET_RX_OV) /* FIFO overrun */
622 dev->stats.rx_fifo_errors++;
625 /* Report late collisions as a frame error.
626 * On this error, the BD is closed, but we don't know what we
627 * have in the buffer. So, just drop this frame on the floor.
629 if (status & BD_ENET_RX_CL) {
630 dev->stats.rx_errors++;
631 dev->stats.rx_frame_errors++;
632 goto rx_processing_done;
635 /* Process the incoming frame.
637 dev->stats.rx_packets++;
638 pkt_len = bdp->cbd_datlen;
639 dev->stats.rx_bytes += pkt_len;
640 data = (__u8*)__va(bdp->cbd_bufaddr);
642 /* This does 16 byte alignment, exactly what we need.
643 * The packet length includes FCS, but we don't want to
644 * include that when passing upstream as it messes up
645 * bridging applications.
647 skb = dev_alloc_skb(pkt_len-4);
650 printk("%s: Memory squeeze, dropping packet.\n", dev->name);
651 dev->stats.rx_dropped++;
653 skb_put(skb,pkt_len-4); /* Make room */
654 skb_copy_to_linear_data(skb, data, pkt_len-4);
655 skb->protocol=eth_type_trans(skb,dev);
660 /* Clear the status flags for this buffer.
662 status &= ~BD_ENET_RX_STATS;
664 /* Mark the buffer empty.
666 status |= BD_ENET_RX_EMPTY;
667 bdp->cbd_sc = status;
669 /* Update BD pointer to next entry.
671 if (status & BD_ENET_RX_WRAP)
672 bdp = fep->rx_bd_base;
677 /* Doing this here will keep the FEC running while we process
678 * incoming frames. On a heavily loaded network, we should be
679 * able to keep up at the expense of system resources.
681 fecp->fec_r_des_active = 0;
683 } /* while (!((status = bdp->cbd_sc) & BD_ENET_RX_EMPTY)) */
684 fep->cur_rx = (cbd_t *)bdp;
687 /* Doing this here will allow us to process all frames in the
688 * ring before the FEC is allowed to put more there. On a heavily
689 * loaded network, some frames may be lost. Unfortunately, this
690 * increases the interrupt overhead since we can potentially work
691 * our way back to the interrupt return only to come right back
694 fecp->fec_r_des_active = 0;
699 /* called from interrupt context */
701 fec_enet_mii(struct net_device *dev)
703 struct fec_enet_private *fep;
708 fep = netdev_priv(dev);
710 mii_reg = ep->fec_mii_data;
712 spin_lock(&fep->lock);
714 if ((mip = mii_head) == NULL) {
715 printk("MII and no head!\n");
719 if (mip->mii_func != NULL)
720 (*(mip->mii_func))(mii_reg, dev);
722 mii_head = mip->mii_next;
723 mip->mii_next = mii_free;
726 if ((mip = mii_head) != NULL)
727 ep->fec_mii_data = mip->mii_regval;
730 spin_unlock(&fep->lock);
734 mii_queue(struct net_device *dev, int regval, void (*func)(uint, struct net_device *))
736 struct fec_enet_private *fep;
741 /* Add PHY address to register command.
743 fep = netdev_priv(dev);
744 regval |= fep->phy_addr << 23;
748 spin_lock_irqsave(&fep->lock,flags);
750 if ((mip = mii_free) != NULL) {
751 mii_free = mip->mii_next;
752 mip->mii_regval = regval;
753 mip->mii_func = func;
754 mip->mii_next = NULL;
756 mii_tail->mii_next = mip;
759 mii_head = mii_tail = mip;
760 fep->hwp->fec_mii_data = regval;
766 spin_unlock_irqrestore(&fep->lock,flags);
771 static void mii_do_cmd(struct net_device *dev, const phy_cmd_t *c)
776 for (; c->mii_data != mk_mii_end; c++)
777 mii_queue(dev, c->mii_data, c->funct);
780 static void mii_parse_sr(uint mii_reg, struct net_device *dev)
782 struct fec_enet_private *fep = netdev_priv(dev);
783 volatile uint *s = &(fep->phy_status);
786 status = *s & ~(PHY_STAT_LINK | PHY_STAT_FAULT | PHY_STAT_ANC);
788 if (mii_reg & 0x0004)
789 status |= PHY_STAT_LINK;
790 if (mii_reg & 0x0010)
791 status |= PHY_STAT_FAULT;
792 if (mii_reg & 0x0020)
793 status |= PHY_STAT_ANC;
797 static void mii_parse_cr(uint mii_reg, struct net_device *dev)
799 struct fec_enet_private *fep = netdev_priv(dev);
800 volatile uint *s = &(fep->phy_status);
803 status = *s & ~(PHY_CONF_ANE | PHY_CONF_LOOP);
805 if (mii_reg & 0x1000)
806 status |= PHY_CONF_ANE;
807 if (mii_reg & 0x4000)
808 status |= PHY_CONF_LOOP;
812 static void mii_parse_anar(uint mii_reg, struct net_device *dev)
814 struct fec_enet_private *fep = netdev_priv(dev);
815 volatile uint *s = &(fep->phy_status);
818 status = *s & ~(PHY_CONF_SPMASK);
820 if (mii_reg & 0x0020)
821 status |= PHY_CONF_10HDX;
822 if (mii_reg & 0x0040)
823 status |= PHY_CONF_10FDX;
824 if (mii_reg & 0x0080)
825 status |= PHY_CONF_100HDX;
826 if (mii_reg & 0x00100)
827 status |= PHY_CONF_100FDX;
831 /* ------------------------------------------------------------------------- */
832 /* The Level one LXT970 is used by many boards */
834 #define MII_LXT970_MIRROR 16 /* Mirror register */
835 #define MII_LXT970_IER 17 /* Interrupt Enable Register */
836 #define MII_LXT970_ISR 18 /* Interrupt Status Register */
837 #define MII_LXT970_CONFIG 19 /* Configuration Register */
838 #define MII_LXT970_CSR 20 /* Chip Status Register */
840 static void mii_parse_lxt970_csr(uint mii_reg, struct net_device *dev)
842 struct fec_enet_private *fep = netdev_priv(dev);
843 volatile uint *s = &(fep->phy_status);
846 status = *s & ~(PHY_STAT_SPMASK);
847 if (mii_reg & 0x0800) {
848 if (mii_reg & 0x1000)
849 status |= PHY_STAT_100FDX;
851 status |= PHY_STAT_100HDX;
853 if (mii_reg & 0x1000)
854 status |= PHY_STAT_10FDX;
856 status |= PHY_STAT_10HDX;
861 static phy_cmd_t const phy_cmd_lxt970_config[] = {
862 { mk_mii_read(MII_REG_CR), mii_parse_cr },
863 { mk_mii_read(MII_REG_ANAR), mii_parse_anar },
866 static phy_cmd_t const phy_cmd_lxt970_startup[] = { /* enable interrupts */
867 { mk_mii_write(MII_LXT970_IER, 0x0002), NULL },
868 { mk_mii_write(MII_REG_CR, 0x1200), NULL }, /* autonegotiate */
871 static phy_cmd_t const phy_cmd_lxt970_ack_int[] = {
872 /* read SR and ISR to acknowledge */
873 { mk_mii_read(MII_REG_SR), mii_parse_sr },
874 { mk_mii_read(MII_LXT970_ISR), NULL },
876 /* find out the current status */
877 { mk_mii_read(MII_LXT970_CSR), mii_parse_lxt970_csr },
880 static phy_cmd_t const phy_cmd_lxt970_shutdown[] = { /* disable interrupts */
881 { mk_mii_write(MII_LXT970_IER, 0x0000), NULL },
884 static phy_info_t const phy_info_lxt970 = {
887 .config = phy_cmd_lxt970_config,
888 .startup = phy_cmd_lxt970_startup,
889 .ack_int = phy_cmd_lxt970_ack_int,
890 .shutdown = phy_cmd_lxt970_shutdown
893 /* ------------------------------------------------------------------------- */
894 /* The Level one LXT971 is used on some of my custom boards */
896 /* register definitions for the 971 */
898 #define MII_LXT971_PCR 16 /* Port Control Register */
899 #define MII_LXT971_SR2 17 /* Status Register 2 */
900 #define MII_LXT971_IER 18 /* Interrupt Enable Register */
901 #define MII_LXT971_ISR 19 /* Interrupt Status Register */
902 #define MII_LXT971_LCR 20 /* LED Control Register */
903 #define MII_LXT971_TCR 30 /* Transmit Control Register */
906 * I had some nice ideas of running the MDIO faster...
907 * The 971 should support 8MHz and I tried it, but things acted really
908 * weird, so 2.5 MHz ought to be enough for anyone...
911 static void mii_parse_lxt971_sr2(uint mii_reg, struct net_device *dev)
913 struct fec_enet_private *fep = netdev_priv(dev);
914 volatile uint *s = &(fep->phy_status);
917 status = *s & ~(PHY_STAT_SPMASK | PHY_STAT_LINK | PHY_STAT_ANC);
919 if (mii_reg & 0x0400) {
921 status |= PHY_STAT_LINK;
925 if (mii_reg & 0x0080)
926 status |= PHY_STAT_ANC;
927 if (mii_reg & 0x4000) {
928 if (mii_reg & 0x0200)
929 status |= PHY_STAT_100FDX;
931 status |= PHY_STAT_100HDX;
933 if (mii_reg & 0x0200)
934 status |= PHY_STAT_10FDX;
936 status |= PHY_STAT_10HDX;
938 if (mii_reg & 0x0008)
939 status |= PHY_STAT_FAULT;
944 static phy_cmd_t const phy_cmd_lxt971_config[] = {
945 /* limit to 10MBit because my prototype board
946 * doesn't work with 100. */
947 { mk_mii_read(MII_REG_CR), mii_parse_cr },
948 { mk_mii_read(MII_REG_ANAR), mii_parse_anar },
949 { mk_mii_read(MII_LXT971_SR2), mii_parse_lxt971_sr2 },
952 static phy_cmd_t const phy_cmd_lxt971_startup[] = { /* enable interrupts */
953 { mk_mii_write(MII_LXT971_IER, 0x00f2), NULL },
954 { mk_mii_write(MII_REG_CR, 0x1200), NULL }, /* autonegotiate */
955 { mk_mii_write(MII_LXT971_LCR, 0xd422), NULL }, /* LED config */
956 /* Somehow does the 971 tell me that the link is down
957 * the first read after power-up.
958 * read here to get a valid value in ack_int */
959 { mk_mii_read(MII_REG_SR), mii_parse_sr },
962 static phy_cmd_t const phy_cmd_lxt971_ack_int[] = {
963 /* acknowledge the int before reading status ! */
964 { mk_mii_read(MII_LXT971_ISR), NULL },
965 /* find out the current status */
966 { mk_mii_read(MII_REG_SR), mii_parse_sr },
967 { mk_mii_read(MII_LXT971_SR2), mii_parse_lxt971_sr2 },
970 static phy_cmd_t const phy_cmd_lxt971_shutdown[] = { /* disable interrupts */
971 { mk_mii_write(MII_LXT971_IER, 0x0000), NULL },
974 static phy_info_t const phy_info_lxt971 = {
977 .config = phy_cmd_lxt971_config,
978 .startup = phy_cmd_lxt971_startup,
979 .ack_int = phy_cmd_lxt971_ack_int,
980 .shutdown = phy_cmd_lxt971_shutdown
983 /* ------------------------------------------------------------------------- */
984 /* The Quality Semiconductor QS6612 is used on the RPX CLLF */
986 /* register definitions */
988 #define MII_QS6612_MCR 17 /* Mode Control Register */
989 #define MII_QS6612_FTR 27 /* Factory Test Register */
990 #define MII_QS6612_MCO 28 /* Misc. Control Register */
991 #define MII_QS6612_ISR 29 /* Interrupt Source Register */
992 #define MII_QS6612_IMR 30 /* Interrupt Mask Register */
993 #define MII_QS6612_PCR 31 /* 100BaseTx PHY Control Reg. */
995 static void mii_parse_qs6612_pcr(uint mii_reg, struct net_device *dev)
997 struct fec_enet_private *fep = netdev_priv(dev);
998 volatile uint *s = &(fep->phy_status);
1001 status = *s & ~(PHY_STAT_SPMASK);
1003 switch((mii_reg >> 2) & 7) {
1004 case 1: status |= PHY_STAT_10HDX; break;
1005 case 2: status |= PHY_STAT_100HDX; break;
1006 case 5: status |= PHY_STAT_10FDX; break;
1007 case 6: status |= PHY_STAT_100FDX; break;
1013 static phy_cmd_t const phy_cmd_qs6612_config[] = {
1014 /* The PHY powers up isolated on the RPX,
1015 * so send a command to allow operation.
1017 { mk_mii_write(MII_QS6612_PCR, 0x0dc0), NULL },
1019 /* parse cr and anar to get some info */
1020 { mk_mii_read(MII_REG_CR), mii_parse_cr },
1021 { mk_mii_read(MII_REG_ANAR), mii_parse_anar },
1024 static phy_cmd_t const phy_cmd_qs6612_startup[] = { /* enable interrupts */
1025 { mk_mii_write(MII_QS6612_IMR, 0x003a), NULL },
1026 { mk_mii_write(MII_REG_CR, 0x1200), NULL }, /* autonegotiate */
1029 static phy_cmd_t const phy_cmd_qs6612_ack_int[] = {
1030 /* we need to read ISR, SR and ANER to acknowledge */
1031 { mk_mii_read(MII_QS6612_ISR), NULL },
1032 { mk_mii_read(MII_REG_SR), mii_parse_sr },
1033 { mk_mii_read(MII_REG_ANER), NULL },
1035 /* read pcr to get info */
1036 { mk_mii_read(MII_QS6612_PCR), mii_parse_qs6612_pcr },
1039 static phy_cmd_t const phy_cmd_qs6612_shutdown[] = { /* disable interrupts */
1040 { mk_mii_write(MII_QS6612_IMR, 0x0000), NULL },
1043 static phy_info_t const phy_info_qs6612 = {
1046 .config = phy_cmd_qs6612_config,
1047 .startup = phy_cmd_qs6612_startup,
1048 .ack_int = phy_cmd_qs6612_ack_int,
1049 .shutdown = phy_cmd_qs6612_shutdown
1052 /* ------------------------------------------------------------------------- */
1053 /* AMD AM79C874 phy */
1055 /* register definitions for the 874 */
1057 #define MII_AM79C874_MFR 16 /* Miscellaneous Feature Register */
1058 #define MII_AM79C874_ICSR 17 /* Interrupt/Status Register */
1059 #define MII_AM79C874_DR 18 /* Diagnostic Register */
1060 #define MII_AM79C874_PMLR 19 /* Power and Loopback Register */
1061 #define MII_AM79C874_MCR 21 /* ModeControl Register */
1062 #define MII_AM79C874_DC 23 /* Disconnect Counter */
1063 #define MII_AM79C874_REC 24 /* Recieve Error Counter */
1065 static void mii_parse_am79c874_dr(uint mii_reg, struct net_device *dev)
1067 struct fec_enet_private *fep = netdev_priv(dev);
1068 volatile uint *s = &(fep->phy_status);
1071 status = *s & ~(PHY_STAT_SPMASK | PHY_STAT_ANC);
1073 if (mii_reg & 0x0080)
1074 status |= PHY_STAT_ANC;
1075 if (mii_reg & 0x0400)
1076 status |= ((mii_reg & 0x0800) ? PHY_STAT_100FDX : PHY_STAT_100HDX);
1078 status |= ((mii_reg & 0x0800) ? PHY_STAT_10FDX : PHY_STAT_10HDX);
1083 static phy_cmd_t const phy_cmd_am79c874_config[] = {
1084 { mk_mii_read(MII_REG_CR), mii_parse_cr },
1085 { mk_mii_read(MII_REG_ANAR), mii_parse_anar },
1086 { mk_mii_read(MII_AM79C874_DR), mii_parse_am79c874_dr },
1089 static phy_cmd_t const phy_cmd_am79c874_startup[] = { /* enable interrupts */
1090 { mk_mii_write(MII_AM79C874_ICSR, 0xff00), NULL },
1091 { mk_mii_write(MII_REG_CR, 0x1200), NULL }, /* autonegotiate */
1092 { mk_mii_read(MII_REG_SR), mii_parse_sr },
1095 static phy_cmd_t const phy_cmd_am79c874_ack_int[] = {
1096 /* find out the current status */
1097 { mk_mii_read(MII_REG_SR), mii_parse_sr },
1098 { mk_mii_read(MII_AM79C874_DR), mii_parse_am79c874_dr },
1099 /* we only need to read ISR to acknowledge */
1100 { mk_mii_read(MII_AM79C874_ICSR), NULL },
1103 static phy_cmd_t const phy_cmd_am79c874_shutdown[] = { /* disable interrupts */
1104 { mk_mii_write(MII_AM79C874_ICSR, 0x0000), NULL },
1107 static phy_info_t const phy_info_am79c874 = {
1110 .config = phy_cmd_am79c874_config,
1111 .startup = phy_cmd_am79c874_startup,
1112 .ack_int = phy_cmd_am79c874_ack_int,
1113 .shutdown = phy_cmd_am79c874_shutdown
1117 /* ------------------------------------------------------------------------- */
1118 /* Kendin KS8721BL phy */
1120 /* register definitions for the 8721 */
1122 #define MII_KS8721BL_RXERCR 21
1123 #define MII_KS8721BL_ICSR 22
1124 #define MII_KS8721BL_PHYCR 31
1126 static phy_cmd_t const phy_cmd_ks8721bl_config[] = {
1127 { mk_mii_read(MII_REG_CR), mii_parse_cr },
1128 { mk_mii_read(MII_REG_ANAR), mii_parse_anar },
1131 static phy_cmd_t const phy_cmd_ks8721bl_startup[] = { /* enable interrupts */
1132 { mk_mii_write(MII_KS8721BL_ICSR, 0xff00), NULL },
1133 { mk_mii_write(MII_REG_CR, 0x1200), NULL }, /* autonegotiate */
1134 { mk_mii_read(MII_REG_SR), mii_parse_sr },
1137 static phy_cmd_t const phy_cmd_ks8721bl_ack_int[] = {
1138 /* find out the current status */
1139 { mk_mii_read(MII_REG_SR), mii_parse_sr },
1140 /* we only need to read ISR to acknowledge */
1141 { mk_mii_read(MII_KS8721BL_ICSR), NULL },
1144 static phy_cmd_t const phy_cmd_ks8721bl_shutdown[] = { /* disable interrupts */
1145 { mk_mii_write(MII_KS8721BL_ICSR, 0x0000), NULL },
1148 static phy_info_t const phy_info_ks8721bl = {
1151 .config = phy_cmd_ks8721bl_config,
1152 .startup = phy_cmd_ks8721bl_startup,
1153 .ack_int = phy_cmd_ks8721bl_ack_int,
1154 .shutdown = phy_cmd_ks8721bl_shutdown
1157 /* ------------------------------------------------------------------------- */
1158 /* register definitions for the DP83848 */
1160 #define MII_DP8384X_PHYSTST 16 /* PHY Status Register */
1162 static void mii_parse_dp8384x_sr2(uint mii_reg, struct net_device *dev)
1164 struct fec_enet_private *fep = dev->priv;
1165 volatile uint *s = &(fep->phy_status);
1167 *s &= ~(PHY_STAT_SPMASK | PHY_STAT_LINK | PHY_STAT_ANC);
1170 if (mii_reg & 0x0001) {
1172 *s |= PHY_STAT_LINK;
1175 /* Status of link */
1176 if (mii_reg & 0x0010) /* Autonegotioation complete */
1178 if (mii_reg & 0x0002) { /* 10MBps? */
1179 if (mii_reg & 0x0004) /* Full Duplex? */
1180 *s |= PHY_STAT_10FDX;
1182 *s |= PHY_STAT_10HDX;
1183 } else { /* 100 Mbps? */
1184 if (mii_reg & 0x0004) /* Full Duplex? */
1185 *s |= PHY_STAT_100FDX;
1187 *s |= PHY_STAT_100HDX;
1189 if (mii_reg & 0x0008)
1190 *s |= PHY_STAT_FAULT;
1193 static phy_info_t phy_info_dp83848= {
1197 (const phy_cmd_t []) { /* config */
1198 { mk_mii_read(MII_REG_CR), mii_parse_cr },
1199 { mk_mii_read(MII_REG_ANAR), mii_parse_anar },
1200 { mk_mii_read(MII_DP8384X_PHYSTST), mii_parse_dp8384x_sr2 },
1203 (const phy_cmd_t []) { /* startup - enable interrupts */
1204 { mk_mii_write(MII_REG_CR, 0x1200), NULL }, /* autonegotiate */
1205 { mk_mii_read(MII_REG_SR), mii_parse_sr },
1208 (const phy_cmd_t []) { /* ack_int - never happens, no interrupt */
1211 (const phy_cmd_t []) { /* shutdown */
1216 /* ------------------------------------------------------------------------- */
1218 static phy_info_t const * const phy_info[] = {
1228 /* ------------------------------------------------------------------------- */
1229 #ifdef HAVE_mii_link_interrupt
1230 #ifdef CONFIG_RPXCLASSIC
1232 mii_link_interrupt(void *dev_id);
1235 mii_link_interrupt(int irq, void * dev_id);
1239 #if defined(CONFIG_M5272)
1241 * Code specific to Coldfire 5272 setup.
1243 static void __inline__ fec_request_intrs(struct net_device *dev)
1245 volatile unsigned long *icrp;
1246 static const struct idesc {
1249 irq_handler_t handler;
1251 { "fec(RX)", 86, fec_enet_interrupt },
1252 { "fec(TX)", 87, fec_enet_interrupt },
1253 { "fec(OTHER)", 88, fec_enet_interrupt },
1254 { "fec(MII)", 66, mii_link_interrupt },
1258 /* Setup interrupt handlers. */
1259 for (idp = id; idp->name; idp++) {
1260 if (request_irq(idp->irq, idp->handler, IRQF_DISABLED, idp->name, dev) != 0)
1261 printk("FEC: Could not allocate %s IRQ(%d)!\n", idp->name, idp->irq);
1264 /* Unmask interrupt at ColdFire 5272 SIM */
1265 icrp = (volatile unsigned long *) (MCF_MBAR + MCFSIM_ICR3);
1267 icrp = (volatile unsigned long *) (MCF_MBAR + MCFSIM_ICR1);
1271 static void __inline__ fec_set_mii(struct net_device *dev, struct fec_enet_private *fep)
1273 volatile fec_t *fecp;
1276 fecp->fec_r_cntrl = OPT_FRAME_SIZE | 0x04;
1277 fecp->fec_x_cntrl = 0x00;
1280 * Set MII speed to 2.5 MHz
1281 * See 5272 manual section 11.5.8: MSCR
1283 fep->phy_speed = ((((MCF_CLK / 4) / (2500000 / 10)) + 5) / 10) * 2;
1284 fecp->fec_mii_speed = fep->phy_speed;
1286 fec_restart(dev, 0);
1289 static void __inline__ fec_get_mac(struct net_device *dev)
1291 struct fec_enet_private *fep = netdev_priv(dev);
1292 volatile fec_t *fecp;
1293 unsigned char *iap, tmpaddr[ETH_ALEN];
1299 * Get MAC address from FLASH.
1300 * If it is all 1's or 0's, use the default.
1302 iap = (unsigned char *)FEC_FLASHMAC;
1303 if ((iap[0] == 0) && (iap[1] == 0) && (iap[2] == 0) &&
1304 (iap[3] == 0) && (iap[4] == 0) && (iap[5] == 0))
1305 iap = fec_mac_default;
1306 if ((iap[0] == 0xff) && (iap[1] == 0xff) && (iap[2] == 0xff) &&
1307 (iap[3] == 0xff) && (iap[4] == 0xff) && (iap[5] == 0xff))
1308 iap = fec_mac_default;
1310 *((unsigned long *) &tmpaddr[0]) = fecp->fec_addr_low;
1311 *((unsigned short *) &tmpaddr[4]) = (fecp->fec_addr_high >> 16);
1315 memcpy(dev->dev_addr, iap, ETH_ALEN);
1317 /* Adjust MAC if using default MAC address */
1318 if (iap == fec_mac_default)
1319 dev->dev_addr[ETH_ALEN-1] = fec_mac_default[ETH_ALEN-1] + fep->index;
1322 static void __inline__ fec_enable_phy_intr(void)
1326 static void __inline__ fec_disable_phy_intr(void)
1328 volatile unsigned long *icrp;
1329 icrp = (volatile unsigned long *) (MCF_MBAR + MCFSIM_ICR1);
1333 static void __inline__ fec_phy_ack_intr(void)
1335 volatile unsigned long *icrp;
1336 /* Acknowledge the interrupt */
1337 icrp = (volatile unsigned long *) (MCF_MBAR + MCFSIM_ICR1);
1341 static void __inline__ fec_localhw_setup(void)
1346 * Do not need to make region uncached on 5272.
1348 static void __inline__ fec_uncache(unsigned long addr)
1352 /* ------------------------------------------------------------------------- */
1354 #elif defined(CONFIG_M523x) || defined(CONFIG_M527x) || defined(CONFIG_M528x)
1357 * Code specific to Coldfire 5230/5231/5232/5234/5235,
1358 * the 5270/5271/5274/5275 and 5280/5282 setups.
1360 static void __inline__ fec_request_intrs(struct net_device *dev)
1362 struct fec_enet_private *fep;
1364 static const struct idesc {
1374 fep = netdev_priv(dev);
1375 b = (fep->index) ? 128 : 64;
1377 /* Setup interrupt handlers. */
1378 for (idp = id; idp->name; idp++) {
1379 if (request_irq(b+idp->irq, fec_enet_interrupt, IRQF_DISABLED, idp->name, dev) != 0)
1380 printk("FEC: Could not allocate %s IRQ(%d)!\n", idp->name, b+idp->irq);
1383 /* Unmask interrupts at ColdFire 5280/5282 interrupt controller */
1385 volatile unsigned char *icrp;
1386 volatile unsigned long *imrp;
1389 b = (fep->index) ? MCFICM_INTC1 : MCFICM_INTC0;
1390 icrp = (volatile unsigned char *) (MCF_IPSBAR + b +
1392 for (i = 23, ilip = 0x28; (i < 36); i++)
1395 imrp = (volatile unsigned long *) (MCF_IPSBAR + b +
1397 *imrp &= ~0x0000000f;
1398 imrp = (volatile unsigned long *) (MCF_IPSBAR + b +
1400 *imrp &= ~0xff800001;
1403 #if defined(CONFIG_M528x)
1404 /* Set up gpio outputs for MII lines */
1406 volatile u16 *gpio_paspar;
1407 volatile u8 *gpio_pehlpar;
1409 gpio_paspar = (volatile u16 *) (MCF_IPSBAR + 0x100056);
1410 gpio_pehlpar = (volatile u16 *) (MCF_IPSBAR + 0x100058);
1411 *gpio_paspar |= 0x0f00;
1412 *gpio_pehlpar = 0xc0;
1416 #if defined(CONFIG_M527x)
1417 /* Set up gpio outputs for MII lines */
1419 volatile u8 *gpio_par_fec;
1420 volatile u16 *gpio_par_feci2c;
1422 gpio_par_feci2c = (volatile u16 *)(MCF_IPSBAR + 0x100082);
1423 /* Set up gpio outputs for FEC0 MII lines */
1424 gpio_par_fec = (volatile u8 *)(MCF_IPSBAR + 0x100078);
1426 *gpio_par_feci2c |= 0x0f00;
1427 *gpio_par_fec |= 0xc0;
1429 #if defined(CONFIG_FEC2)
1430 /* Set up gpio outputs for FEC1 MII lines */
1431 gpio_par_fec = (volatile u8 *)(MCF_IPSBAR + 0x100079);
1433 *gpio_par_feci2c |= 0x00a0;
1434 *gpio_par_fec |= 0xc0;
1435 #endif /* CONFIG_FEC2 */
1437 #endif /* CONFIG_M527x */
1440 static void __inline__ fec_set_mii(struct net_device *dev, struct fec_enet_private *fep)
1442 volatile fec_t *fecp;
1445 fecp->fec_r_cntrl = OPT_FRAME_SIZE | 0x04;
1446 fecp->fec_x_cntrl = 0x00;
1449 * Set MII speed to 2.5 MHz
1450 * See 5282 manual section 17.5.4.7: MSCR
1452 fep->phy_speed = ((((MCF_CLK / 2) / (2500000 / 10)) + 5) / 10) * 2;
1453 fecp->fec_mii_speed = fep->phy_speed;
1455 fec_restart(dev, 0);
1458 static void __inline__ fec_get_mac(struct net_device *dev)
1460 struct fec_enet_private *fep = netdev_priv(dev);
1461 volatile fec_t *fecp;
1462 unsigned char *iap, tmpaddr[ETH_ALEN];
1468 * Get MAC address from FLASH.
1469 * If it is all 1's or 0's, use the default.
1472 if ((iap[0] == 0) && (iap[1] == 0) && (iap[2] == 0) &&
1473 (iap[3] == 0) && (iap[4] == 0) && (iap[5] == 0))
1474 iap = fec_mac_default;
1475 if ((iap[0] == 0xff) && (iap[1] == 0xff) && (iap[2] == 0xff) &&
1476 (iap[3] == 0xff) && (iap[4] == 0xff) && (iap[5] == 0xff))
1477 iap = fec_mac_default;
1479 *((unsigned long *) &tmpaddr[0]) = fecp->fec_addr_low;
1480 *((unsigned short *) &tmpaddr[4]) = (fecp->fec_addr_high >> 16);
1484 memcpy(dev->dev_addr, iap, ETH_ALEN);
1486 /* Adjust MAC if using default MAC address */
1487 if (iap == fec_mac_default)
1488 dev->dev_addr[ETH_ALEN-1] = fec_mac_default[ETH_ALEN-1] + fep->index;
1491 static void __inline__ fec_enable_phy_intr(void)
1495 static void __inline__ fec_disable_phy_intr(void)
1499 static void __inline__ fec_phy_ack_intr(void)
1503 static void __inline__ fec_localhw_setup(void)
1508 * Do not need to make region uncached on 5272.
1510 static void __inline__ fec_uncache(unsigned long addr)
1514 /* ------------------------------------------------------------------------- */
1516 #elif defined(CONFIG_M520x)
1519 * Code specific to Coldfire 520x
1521 static void __inline__ fec_request_intrs(struct net_device *dev)
1523 struct fec_enet_private *fep;
1525 static const struct idesc {
1535 fep = netdev_priv(dev);
1538 /* Setup interrupt handlers. */
1539 for (idp = id; idp->name; idp++) {
1540 if (request_irq(b+idp->irq, fec_enet_interrupt, IRQF_DISABLED, idp->name,dev) != 0)
1541 printk("FEC: Could not allocate %s IRQ(%d)!\n", idp->name, b+idp->irq);
1544 /* Unmask interrupts at ColdFire interrupt controller */
1546 volatile unsigned char *icrp;
1547 volatile unsigned long *imrp;
1549 icrp = (volatile unsigned char *) (MCF_IPSBAR + MCFICM_INTC0 +
1551 for (b = 36; (b < 49); b++)
1553 imrp = (volatile unsigned long *) (MCF_IPSBAR + MCFICM_INTC0 +
1555 *imrp &= ~0x0001FFF0;
1557 *(volatile unsigned char *)(MCF_IPSBAR + MCF_GPIO_PAR_FEC) |= 0xf0;
1558 *(volatile unsigned char *)(MCF_IPSBAR + MCF_GPIO_PAR_FECI2C) |= 0x0f;
1561 static void __inline__ fec_set_mii(struct net_device *dev, struct fec_enet_private *fep)
1563 volatile fec_t *fecp;
1566 fecp->fec_r_cntrl = OPT_FRAME_SIZE | 0x04;
1567 fecp->fec_x_cntrl = 0x00;
1570 * Set MII speed to 2.5 MHz
1571 * See 5282 manual section 17.5.4.7: MSCR
1573 fep->phy_speed = ((((MCF_CLK / 2) / (2500000 / 10)) + 5) / 10) * 2;
1574 fecp->fec_mii_speed = fep->phy_speed;
1576 fec_restart(dev, 0);
1579 static void __inline__ fec_get_mac(struct net_device *dev)
1581 struct fec_enet_private *fep = netdev_priv(dev);
1582 volatile fec_t *fecp;
1583 unsigned char *iap, tmpaddr[ETH_ALEN];
1589 * Get MAC address from FLASH.
1590 * If it is all 1's or 0's, use the default.
1593 if ((iap[0] == 0) && (iap[1] == 0) && (iap[2] == 0) &&
1594 (iap[3] == 0) && (iap[4] == 0) && (iap[5] == 0))
1595 iap = fec_mac_default;
1596 if ((iap[0] == 0xff) && (iap[1] == 0xff) && (iap[2] == 0xff) &&
1597 (iap[3] == 0xff) && (iap[4] == 0xff) && (iap[5] == 0xff))
1598 iap = fec_mac_default;
1600 *((unsigned long *) &tmpaddr[0]) = fecp->fec_addr_low;
1601 *((unsigned short *) &tmpaddr[4]) = (fecp->fec_addr_high >> 16);
1605 memcpy(dev->dev_addr, iap, ETH_ALEN);
1607 /* Adjust MAC if using default MAC address */
1608 if (iap == fec_mac_default)
1609 dev->dev_addr[ETH_ALEN-1] = fec_mac_default[ETH_ALEN-1] + fep->index;
1612 static void __inline__ fec_enable_phy_intr(void)
1616 static void __inline__ fec_disable_phy_intr(void)
1620 static void __inline__ fec_phy_ack_intr(void)
1624 static void __inline__ fec_localhw_setup(void)
1628 static void __inline__ fec_uncache(unsigned long addr)
1632 /* ------------------------------------------------------------------------- */
1634 #elif defined(CONFIG_M532x)
1636 * Code specific for M532x
1638 static void __inline__ fec_request_intrs(struct net_device *dev)
1640 struct fec_enet_private *fep;
1642 static const struct idesc {
1652 fep = netdev_priv(dev);
1653 b = (fep->index) ? 128 : 64;
1655 /* Setup interrupt handlers. */
1656 for (idp = id; idp->name; idp++) {
1657 if (request_irq(b+idp->irq, fec_enet_interrupt, IRQF_DISABLED, idp->name,dev) != 0)
1658 printk("FEC: Could not allocate %s IRQ(%d)!\n",
1659 idp->name, b+idp->irq);
1662 /* Unmask interrupts */
1663 MCF_INTC0_ICR36 = 0x2;
1664 MCF_INTC0_ICR37 = 0x2;
1665 MCF_INTC0_ICR38 = 0x2;
1666 MCF_INTC0_ICR39 = 0x2;
1667 MCF_INTC0_ICR40 = 0x2;
1668 MCF_INTC0_ICR41 = 0x2;
1669 MCF_INTC0_ICR42 = 0x2;
1670 MCF_INTC0_ICR43 = 0x2;
1671 MCF_INTC0_ICR44 = 0x2;
1672 MCF_INTC0_ICR45 = 0x2;
1673 MCF_INTC0_ICR46 = 0x2;
1674 MCF_INTC0_ICR47 = 0x2;
1675 MCF_INTC0_ICR48 = 0x2;
1677 MCF_INTC0_IMRH &= ~(
1678 MCF_INTC_IMRH_INT_MASK36 |
1679 MCF_INTC_IMRH_INT_MASK37 |
1680 MCF_INTC_IMRH_INT_MASK38 |
1681 MCF_INTC_IMRH_INT_MASK39 |
1682 MCF_INTC_IMRH_INT_MASK40 |
1683 MCF_INTC_IMRH_INT_MASK41 |
1684 MCF_INTC_IMRH_INT_MASK42 |
1685 MCF_INTC_IMRH_INT_MASK43 |
1686 MCF_INTC_IMRH_INT_MASK44 |
1687 MCF_INTC_IMRH_INT_MASK45 |
1688 MCF_INTC_IMRH_INT_MASK46 |
1689 MCF_INTC_IMRH_INT_MASK47 |
1690 MCF_INTC_IMRH_INT_MASK48 );
1692 /* Set up gpio outputs for MII lines */
1693 MCF_GPIO_PAR_FECI2C |= (0 |
1694 MCF_GPIO_PAR_FECI2C_PAR_MDC_EMDC |
1695 MCF_GPIO_PAR_FECI2C_PAR_MDIO_EMDIO);
1696 MCF_GPIO_PAR_FEC = (0 |
1697 MCF_GPIO_PAR_FEC_PAR_FEC_7W_FEC |
1698 MCF_GPIO_PAR_FEC_PAR_FEC_MII_FEC);
1701 static void __inline__ fec_set_mii(struct net_device *dev, struct fec_enet_private *fep)
1703 volatile fec_t *fecp;
1706 fecp->fec_r_cntrl = OPT_FRAME_SIZE | 0x04;
1707 fecp->fec_x_cntrl = 0x00;
1710 * Set MII speed to 2.5 MHz
1712 fep->phy_speed = ((((MCF_CLK / 2) / (2500000 / 10)) + 5) / 10) * 2;
1713 fecp->fec_mii_speed = fep->phy_speed;
1715 fec_restart(dev, 0);
1718 static void __inline__ fec_get_mac(struct net_device *dev)
1720 struct fec_enet_private *fep = netdev_priv(dev);
1721 volatile fec_t *fecp;
1722 unsigned char *iap, tmpaddr[ETH_ALEN];
1728 * Get MAC address from FLASH.
1729 * If it is all 1's or 0's, use the default.
1732 if ((iap[0] == 0) && (iap[1] == 0) && (iap[2] == 0) &&
1733 (iap[3] == 0) && (iap[4] == 0) && (iap[5] == 0))
1734 iap = fec_mac_default;
1735 if ((iap[0] == 0xff) && (iap[1] == 0xff) && (iap[2] == 0xff) &&
1736 (iap[3] == 0xff) && (iap[4] == 0xff) && (iap[5] == 0xff))
1737 iap = fec_mac_default;
1739 *((unsigned long *) &tmpaddr[0]) = fecp->fec_addr_low;
1740 *((unsigned short *) &tmpaddr[4]) = (fecp->fec_addr_high >> 16);
1744 memcpy(dev->dev_addr, iap, ETH_ALEN);
1746 /* Adjust MAC if using default MAC address */
1747 if (iap == fec_mac_default)
1748 dev->dev_addr[ETH_ALEN-1] = fec_mac_default[ETH_ALEN-1] + fep->index;
1751 static void __inline__ fec_enable_phy_intr(void)
1755 static void __inline__ fec_disable_phy_intr(void)
1759 static void __inline__ fec_phy_ack_intr(void)
1763 static void __inline__ fec_localhw_setup(void)
1768 * Do not need to make region uncached on 532x.
1770 static void __inline__ fec_uncache(unsigned long addr)
1774 /* ------------------------------------------------------------------------- */
1780 * Code specific to the MPC860T setup.
1782 static void __inline__ fec_request_intrs(struct net_device *dev)
1784 volatile immap_t *immap;
1786 immap = (immap_t *)IMAP_ADDR; /* pointer to internal registers */
1788 if (request_8xxirq(FEC_INTERRUPT, fec_enet_interrupt, 0, "fec", dev) != 0)
1789 panic("Could not allocate FEC IRQ!");
1791 #ifdef CONFIG_RPXCLASSIC
1792 /* Make Port C, bit 15 an input that causes interrupts.
1794 immap->im_ioport.iop_pcpar &= ~0x0001;
1795 immap->im_ioport.iop_pcdir &= ~0x0001;
1796 immap->im_ioport.iop_pcso &= ~0x0001;
1797 immap->im_ioport.iop_pcint |= 0x0001;
1798 cpm_install_handler(CPMVEC_PIO_PC15, mii_link_interrupt, dev);
1800 /* Make LEDS reflect Link status.
1802 *((uint *) RPX_CSR_ADDR) &= ~BCSR2_FETHLEDMODE;
1805 if (request_8xxirq(SIU_IRQ2, mii_link_interrupt, 0, "mii", dev) != 0)
1806 panic("Could not allocate MII IRQ!");
1810 static void __inline__ fec_get_mac(struct net_device *dev)
1815 memcpy(dev->dev_addr, bd->bi_enetaddr, ETH_ALEN);
1817 #ifdef CONFIG_RPXCLASSIC
1818 /* The Embedded Planet boards have only one MAC address in
1819 * the EEPROM, but can have two Ethernet ports. For the
1820 * FEC port, we create another address by setting one of
1821 * the address bits above something that would have (up to
1822 * now) been allocated.
1824 dev->dev_adrd[3] |= 0x80;
1828 static void __inline__ fec_set_mii(struct net_device *dev, struct fec_enet_private *fep)
1830 extern uint _get_IMMR(void);
1831 volatile immap_t *immap;
1832 volatile fec_t *fecp;
1835 immap = (immap_t *)IMAP_ADDR; /* pointer to internal registers */
1837 /* Configure all of port D for MII.
1839 immap->im_ioport.iop_pdpar = 0x1fff;
1841 /* Bits moved from Rev. D onward.
1843 if ((_get_IMMR() & 0xffff) < 0x0501)
1844 immap->im_ioport.iop_pddir = 0x1c58; /* Pre rev. D */
1846 immap->im_ioport.iop_pddir = 0x1fff; /* Rev. D and later */
1848 /* Set MII speed to 2.5 MHz
1850 fecp->fec_mii_speed = fep->phy_speed =
1851 ((bd->bi_busfreq * 1000000) / 2500000) & 0x7e;
1854 static void __inline__ fec_enable_phy_intr(void)
1856 volatile fec_t *fecp;
1860 /* Enable MII command finished interrupt
1862 fecp->fec_ivec = (FEC_INTERRUPT/2) << 29;
1865 static void __inline__ fec_disable_phy_intr(void)
1869 static void __inline__ fec_phy_ack_intr(void)
1873 static void __inline__ fec_localhw_setup(void)
1875 volatile fec_t *fecp;
1878 fecp->fec_r_hash = PKT_MAXBUF_SIZE;
1879 /* Enable big endian and don't care about SDMA FC.
1881 fecp->fec_fun_code = 0x78000000;
1884 static void __inline__ fec_uncache(unsigned long addr)
1887 pte = va_to_pte(mem_addr);
1888 pte_val(*pte) |= _PAGE_NO_CACHE;
1889 flush_tlb_page(init_mm.mmap, mem_addr);
1894 /* ------------------------------------------------------------------------- */
1896 static void mii_display_status(struct net_device *dev)
1898 struct fec_enet_private *fep = netdev_priv(dev);
1899 volatile uint *s = &(fep->phy_status);
1901 if (!fep->link && !fep->old_link) {
1902 /* Link is still down - don't print anything */
1906 printk("%s: status: ", dev->name);
1909 printk("link down");
1913 switch(*s & PHY_STAT_SPMASK) {
1914 case PHY_STAT_100FDX: printk(", 100MBit Full Duplex"); break;
1915 case PHY_STAT_100HDX: printk(", 100MBit Half Duplex"); break;
1916 case PHY_STAT_10FDX: printk(", 10MBit Full Duplex"); break;
1917 case PHY_STAT_10HDX: printk(", 10MBit Half Duplex"); break;
1919 printk(", Unknown speed/duplex");
1922 if (*s & PHY_STAT_ANC)
1923 printk(", auto-negotiation complete");
1926 if (*s & PHY_STAT_FAULT)
1927 printk(", remote fault");
1932 static void mii_display_config(struct work_struct *work)
1934 struct fec_enet_private *fep = container_of(work, struct fec_enet_private, phy_task);
1935 struct net_device *dev = fep->netdev;
1936 uint status = fep->phy_status;
1939 ** When we get here, phy_task is already removed from
1940 ** the workqueue. It is thus safe to allow to reuse it.
1942 fep->mii_phy_task_queued = 0;
1943 printk("%s: config: auto-negotiation ", dev->name);
1945 if (status & PHY_CONF_ANE)
1950 if (status & PHY_CONF_100FDX)
1952 if (status & PHY_CONF_100HDX)
1954 if (status & PHY_CONF_10FDX)
1956 if (status & PHY_CONF_10HDX)
1958 if (!(status & PHY_CONF_SPMASK))
1959 printk(", No speed/duplex selected?");
1961 if (status & PHY_CONF_LOOP)
1962 printk(", loopback enabled");
1966 fep->sequence_done = 1;
1969 static void mii_relink(struct work_struct *work)
1971 struct fec_enet_private *fep = container_of(work, struct fec_enet_private, phy_task);
1972 struct net_device *dev = fep->netdev;
1976 ** When we get here, phy_task is already removed from
1977 ** the workqueue. It is thus safe to allow to reuse it.
1979 fep->mii_phy_task_queued = 0;
1980 fep->link = (fep->phy_status & PHY_STAT_LINK) ? 1 : 0;
1981 mii_display_status(dev);
1982 fep->old_link = fep->link;
1987 & (PHY_STAT_100FDX | PHY_STAT_10FDX))
1989 fec_restart(dev, duplex);
1994 enable_irq(fep->mii_irq);
1999 /* mii_queue_relink is called in interrupt context from mii_link_interrupt */
2000 static void mii_queue_relink(uint mii_reg, struct net_device *dev)
2002 struct fec_enet_private *fep = netdev_priv(dev);
2005 ** We cannot queue phy_task twice in the workqueue. It
2006 ** would cause an endless loop in the workqueue.
2007 ** Fortunately, if the last mii_relink entry has not yet been
2008 ** executed now, it will do the job for the current interrupt,
2009 ** which is just what we want.
2011 if (fep->mii_phy_task_queued)
2014 fep->mii_phy_task_queued = 1;
2015 INIT_WORK(&fep->phy_task, mii_relink);
2016 schedule_work(&fep->phy_task);
2019 /* mii_queue_config is called in interrupt context from fec_enet_mii */
2020 static void mii_queue_config(uint mii_reg, struct net_device *dev)
2022 struct fec_enet_private *fep = netdev_priv(dev);
2024 if (fep->mii_phy_task_queued)
2027 fep->mii_phy_task_queued = 1;
2028 INIT_WORK(&fep->phy_task, mii_display_config);
2029 schedule_work(&fep->phy_task);
2032 phy_cmd_t const phy_cmd_relink[] = {
2033 { mk_mii_read(MII_REG_CR), mii_queue_relink },
2036 phy_cmd_t const phy_cmd_config[] = {
2037 { mk_mii_read(MII_REG_CR), mii_queue_config },
2041 /* Read remainder of PHY ID.
2044 mii_discover_phy3(uint mii_reg, struct net_device *dev)
2046 struct fec_enet_private *fep;
2049 fep = netdev_priv(dev);
2050 fep->phy_id |= (mii_reg & 0xffff);
2051 printk("fec: PHY @ 0x%x, ID 0x%08x", fep->phy_addr, fep->phy_id);
2053 for(i = 0; phy_info[i]; i++) {
2054 if(phy_info[i]->id == (fep->phy_id >> 4))
2059 printk(" -- %s\n", phy_info[i]->name);
2061 printk(" -- unknown PHY!\n");
2063 fep->phy = phy_info[i];
2064 fep->phy_id_done = 1;
2067 /* Scan all of the MII PHY addresses looking for someone to respond
2068 * with a valid ID. This usually happens quickly.
2071 mii_discover_phy(uint mii_reg, struct net_device *dev)
2073 struct fec_enet_private *fep;
2074 volatile fec_t *fecp;
2077 fep = netdev_priv(dev);
2080 if (fep->phy_addr < 32) {
2081 if ((phytype = (mii_reg & 0xffff)) != 0xffff && phytype != 0) {
2083 /* Got first part of ID, now get remainder.
2085 fep->phy_id = phytype << 16;
2086 mii_queue(dev, mk_mii_read(MII_REG_PHYIR2),
2090 mii_queue(dev, mk_mii_read(MII_REG_PHYIR1),
2094 printk("FEC: No PHY device found.\n");
2095 /* Disable external MII interface */
2096 fecp->fec_mii_speed = fep->phy_speed = 0;
2097 fec_disable_phy_intr();
2101 /* This interrupt occurs when the PHY detects a link change.
2103 #ifdef HAVE_mii_link_interrupt
2104 #ifdef CONFIG_RPXCLASSIC
2106 mii_link_interrupt(void *dev_id)
2109 mii_link_interrupt(int irq, void * dev_id)
2112 struct net_device *dev = dev_id;
2113 struct fec_enet_private *fep = netdev_priv(dev);
2118 disable_irq(fep->mii_irq); /* disable now, enable later */
2121 mii_do_cmd(dev, fep->phy->ack_int);
2122 mii_do_cmd(dev, phy_cmd_relink); /* restart and display status */
2129 fec_enet_open(struct net_device *dev)
2131 struct fec_enet_private *fep = netdev_priv(dev);
2133 /* I should reset the ring buffers here, but I don't yet know
2134 * a simple way to do that.
2136 fec_set_mac_address(dev);
2138 fep->sequence_done = 0;
2142 mii_do_cmd(dev, fep->phy->ack_int);
2143 mii_do_cmd(dev, fep->phy->config);
2144 mii_do_cmd(dev, phy_cmd_config); /* display configuration */
2146 /* Poll until the PHY tells us its configuration
2148 * Request is initiated by mii_do_cmd above, but answer
2149 * comes by interrupt.
2150 * This should take about 25 usec per register at 2.5 MHz,
2151 * and we read approximately 5 registers.
2153 while(!fep->sequence_done)
2156 mii_do_cmd(dev, fep->phy->startup);
2158 /* Set the initial link state to true. A lot of hardware
2159 * based on this device does not implement a PHY interrupt,
2160 * so we are never notified of link change.
2164 fep->link = 1; /* lets just try it and see */
2165 /* no phy, go full duplex, it's most likely a hub chip */
2166 fec_restart(dev, 1);
2169 netif_start_queue(dev);
2171 return 0; /* Success */
2175 fec_enet_close(struct net_device *dev)
2177 struct fec_enet_private *fep = netdev_priv(dev);
2179 /* Don't know what to do yet.
2182 netif_stop_queue(dev);
2188 /* Set or clear the multicast filter for this adaptor.
2189 * Skeleton taken from sunlance driver.
2190 * The CPM Ethernet implementation allows Multicast as well as individual
2191 * MAC address filtering. Some of the drivers check to make sure it is
2192 * a group multicast address, and discard those that are not. I guess I
2193 * will do the same for now, but just remove the test if you want
2194 * individual filtering as well (do the upper net layers want or support
2195 * this kind of feature?).
2198 #define HASH_BITS 6 /* #bits in hash */
2199 #define CRC32_POLY 0xEDB88320
2201 static void set_multicast_list(struct net_device *dev)
2203 struct fec_enet_private *fep;
2205 struct dev_mc_list *dmi;
2206 unsigned int i, j, bit, data, crc;
2209 fep = netdev_priv(dev);
2212 if (dev->flags&IFF_PROMISC) {
2213 ep->fec_r_cntrl |= 0x0008;
2216 ep->fec_r_cntrl &= ~0x0008;
2218 if (dev->flags & IFF_ALLMULTI) {
2219 /* Catch all multicast addresses, so set the
2220 * filter to all 1's.
2222 ep->fec_grp_hash_table_high = 0xffffffff;
2223 ep->fec_grp_hash_table_low = 0xffffffff;
2225 /* Clear filter and add the addresses in hash register.
2227 ep->fec_grp_hash_table_high = 0;
2228 ep->fec_grp_hash_table_low = 0;
2232 for (j = 0; j < dev->mc_count; j++, dmi = dmi->next)
2234 /* Only support group multicast for now.
2236 if (!(dmi->dmi_addr[0] & 1))
2239 /* calculate crc32 value of mac address
2243 for (i = 0; i < dmi->dmi_addrlen; i++)
2245 data = dmi->dmi_addr[i];
2246 for (bit = 0; bit < 8; bit++, data >>= 1)
2249 (((crc ^ data) & 1) ? CRC32_POLY : 0);
2253 /* only upper 6 bits (HASH_BITS) are used
2254 which point to specific bit in he hash registers
2256 hash = (crc >> (32 - HASH_BITS)) & 0x3f;
2259 ep->fec_grp_hash_table_high |= 1 << (hash - 32);
2261 ep->fec_grp_hash_table_low |= 1 << hash;
2267 /* Set a MAC change in hardware.
2270 fec_set_mac_address(struct net_device *dev)
2272 volatile fec_t *fecp;
2274 fecp = ((struct fec_enet_private *)netdev_priv(dev))->hwp;
2276 /* Set station address. */
2277 fecp->fec_addr_low = dev->dev_addr[3] | (dev->dev_addr[2] << 8) |
2278 (dev->dev_addr[1] << 16) | (dev->dev_addr[0] << 24);
2279 fecp->fec_addr_high = (dev->dev_addr[5] << 16) |
2280 (dev->dev_addr[4] << 24);
2284 /* Initialize the FEC Ethernet on 860T (or ColdFire 5272).
2287 * XXX: We need to clean up on failure exits here.
2289 int __init fec_enet_init(struct net_device *dev)
2291 struct fec_enet_private *fep = netdev_priv(dev);
2292 unsigned long mem_addr;
2293 volatile cbd_t *bdp;
2295 volatile fec_t *fecp;
2297 static int index = 0;
2299 /* Only allow us to be probed once. */
2300 if (index >= FEC_MAX_PORTS)
2303 /* Allocate memory for buffer descriptors.
2305 mem_addr = __get_free_page(GFP_KERNEL);
2306 if (mem_addr == 0) {
2307 printk("FEC: allocate descriptor memory failed?\n");
2311 /* Create an Ethernet device instance.
2313 fecp = (volatile fec_t *) fec_hw[index];
2319 /* Whack a reset. We should wait for this.
2321 fecp->fec_ecntrl = 1;
2324 /* Set the Ethernet address. If using multiple Enets on the 8xx,
2325 * this needs some work to get unique addresses.
2327 * This is our default MAC address unless the user changes
2328 * it via eth_mac_addr (our dev->set_mac_addr handler).
2332 cbd_base = (cbd_t *)mem_addr;
2333 /* XXX: missing check for allocation failure */
2335 fec_uncache(mem_addr);
2337 /* Set receive and transmit descriptor base.
2339 fep->rx_bd_base = cbd_base;
2340 fep->tx_bd_base = cbd_base + RX_RING_SIZE;
2342 fep->dirty_tx = fep->cur_tx = fep->tx_bd_base;
2343 fep->cur_rx = fep->rx_bd_base;
2345 fep->skb_cur = fep->skb_dirty = 0;
2347 /* Initialize the receive buffer descriptors.
2349 bdp = fep->rx_bd_base;
2350 for (i=0; i<FEC_ENET_RX_PAGES; i++) {
2354 mem_addr = __get_free_page(GFP_KERNEL);
2355 /* XXX: missing check for allocation failure */
2357 fec_uncache(mem_addr);
2359 /* Initialize the BD for every fragment in the page.
2361 for (j=0; j<FEC_ENET_RX_FRPPG; j++) {
2362 bdp->cbd_sc = BD_ENET_RX_EMPTY;
2363 bdp->cbd_bufaddr = __pa(mem_addr);
2364 mem_addr += FEC_ENET_RX_FRSIZE;
2369 /* Set the last buffer to wrap.
2372 bdp->cbd_sc |= BD_SC_WRAP;
2374 /* ...and the same for transmmit.
2376 bdp = fep->tx_bd_base;
2377 for (i=0, j=FEC_ENET_TX_FRPPG; i<TX_RING_SIZE; i++) {
2378 if (j >= FEC_ENET_TX_FRPPG) {
2379 mem_addr = __get_free_page(GFP_KERNEL);
2382 mem_addr += FEC_ENET_TX_FRSIZE;
2385 fep->tx_bounce[i] = (unsigned char *) mem_addr;
2387 /* Initialize the BD for every fragment in the page.
2390 bdp->cbd_bufaddr = 0;
2394 /* Set the last buffer to wrap.
2397 bdp->cbd_sc |= BD_SC_WRAP;
2399 /* Set receive and transmit descriptor base.
2401 fecp->fec_r_des_start = __pa((uint)(fep->rx_bd_base));
2402 fecp->fec_x_des_start = __pa((uint)(fep->tx_bd_base));
2404 /* Install our interrupt handlers. This varies depending on
2407 fec_request_intrs(dev);
2409 fecp->fec_grp_hash_table_high = 0;
2410 fecp->fec_grp_hash_table_low = 0;
2411 fecp->fec_r_buff_size = PKT_MAXBLR_SIZE;
2412 fecp->fec_ecntrl = 2;
2413 fecp->fec_r_des_active = 0;
2414 #ifndef CONFIG_M5272
2415 fecp->fec_hash_table_high = 0;
2416 fecp->fec_hash_table_low = 0;
2419 dev->base_addr = (unsigned long)fecp;
2421 /* The FEC Ethernet specific entries in the device structure. */
2422 dev->open = fec_enet_open;
2423 dev->hard_start_xmit = fec_enet_start_xmit;
2424 dev->tx_timeout = fec_timeout;
2425 dev->watchdog_timeo = TX_TIMEOUT;
2426 dev->stop = fec_enet_close;
2427 dev->set_multicast_list = set_multicast_list;
2429 for (i=0; i<NMII-1; i++)
2430 mii_cmds[i].mii_next = &mii_cmds[i+1];
2431 mii_free = mii_cmds;
2433 /* setup MII interface */
2434 fec_set_mii(dev, fep);
2436 /* Clear and enable interrupts */
2437 fecp->fec_ievent = 0xffc00000;
2438 fecp->fec_imask = (FEC_ENET_TXF | FEC_ENET_RXF | FEC_ENET_MII);
2440 /* Queue up command to detect the PHY and initialize the
2441 * remainder of the interface.
2443 fep->phy_id_done = 0;
2445 mii_queue(dev, mk_mii_read(MII_REG_PHYIR1), mii_discover_phy);
2451 /* This function is called to start or restart the FEC during a link
2452 * change. This only happens when switching between half and full
2456 fec_restart(struct net_device *dev, int duplex)
2458 struct fec_enet_private *fep;
2459 volatile cbd_t *bdp;
2460 volatile fec_t *fecp;
2463 fep = netdev_priv(dev);
2466 /* Whack a reset. We should wait for this.
2468 fecp->fec_ecntrl = 1;
2471 /* Clear any outstanding interrupt.
2473 fecp->fec_ievent = 0xffc00000;
2474 fec_enable_phy_intr();
2476 /* Set station address.
2478 fec_set_mac_address(dev);
2480 /* Reset all multicast.
2482 fecp->fec_grp_hash_table_high = 0;
2483 fecp->fec_grp_hash_table_low = 0;
2485 /* Set maximum receive buffer size.
2487 fecp->fec_r_buff_size = PKT_MAXBLR_SIZE;
2489 fec_localhw_setup();
2491 /* Set receive and transmit descriptor base.
2493 fecp->fec_r_des_start = __pa((uint)(fep->rx_bd_base));
2494 fecp->fec_x_des_start = __pa((uint)(fep->tx_bd_base));
2496 fep->dirty_tx = fep->cur_tx = fep->tx_bd_base;
2497 fep->cur_rx = fep->rx_bd_base;
2499 /* Reset SKB transmit buffers.
2501 fep->skb_cur = fep->skb_dirty = 0;
2502 for (i=0; i<=TX_RING_MOD_MASK; i++) {
2503 if (fep->tx_skbuff[i] != NULL) {
2504 dev_kfree_skb_any(fep->tx_skbuff[i]);
2505 fep->tx_skbuff[i] = NULL;
2509 /* Initialize the receive buffer descriptors.
2511 bdp = fep->rx_bd_base;
2512 for (i=0; i<RX_RING_SIZE; i++) {
2514 /* Initialize the BD for every fragment in the page.
2516 bdp->cbd_sc = BD_ENET_RX_EMPTY;
2520 /* Set the last buffer to wrap.
2523 bdp->cbd_sc |= BD_SC_WRAP;
2525 /* ...and the same for transmmit.
2527 bdp = fep->tx_bd_base;
2528 for (i=0; i<TX_RING_SIZE; i++) {
2530 /* Initialize the BD for every fragment in the page.
2533 bdp->cbd_bufaddr = 0;
2537 /* Set the last buffer to wrap.
2540 bdp->cbd_sc |= BD_SC_WRAP;
2545 fecp->fec_r_cntrl = OPT_FRAME_SIZE | 0x04;/* MII enable */
2546 fecp->fec_x_cntrl = 0x04; /* FD enable */
2548 /* MII enable|No Rcv on Xmit */
2549 fecp->fec_r_cntrl = OPT_FRAME_SIZE | 0x06;
2550 fecp->fec_x_cntrl = 0x00;
2552 fep->full_duplex = duplex;
2556 fecp->fec_mii_speed = fep->phy_speed;
2558 /* And last, enable the transmit and receive processing.
2560 fecp->fec_ecntrl = 2;
2561 fecp->fec_r_des_active = 0;
2563 /* Enable interrupts we wish to service.
2565 fecp->fec_imask = (FEC_ENET_TXF | FEC_ENET_RXF | FEC_ENET_MII);
2569 fec_stop(struct net_device *dev)
2571 volatile fec_t *fecp;
2572 struct fec_enet_private *fep;
2574 fep = netdev_priv(dev);
2578 ** We cannot expect a graceful transmit stop without link !!!
2582 fecp->fec_x_cntrl = 0x01; /* Graceful transmit stop */
2584 if (!(fecp->fec_ievent & FEC_ENET_GRA))
2585 printk("fec_stop : Graceful transmit stop did not complete !\n");
2588 /* Whack a reset. We should wait for this.
2590 fecp->fec_ecntrl = 1;
2593 /* Clear outstanding MII command interrupts.
2595 fecp->fec_ievent = FEC_ENET_MII;
2596 fec_enable_phy_intr();
2598 fecp->fec_imask = FEC_ENET_MII;
2599 fecp->fec_mii_speed = fep->phy_speed;
2602 static int __init fec_enet_module_init(void)
2604 struct net_device *dev;
2606 DECLARE_MAC_BUF(mac);
2608 printk("FEC ENET Version 0.2\n");
2610 for (i = 0; (i < FEC_MAX_PORTS); i++) {
2611 dev = alloc_etherdev(sizeof(struct fec_enet_private));
2614 err = fec_enet_init(dev);
2619 if (register_netdev(dev) != 0) {
2620 /* XXX: missing cleanup here */
2625 printk("%s: ethernet %s\n",
2626 dev->name, print_mac(mac, dev->dev_addr));
2631 module_init(fec_enet_module_init);
2633 MODULE_LICENSE("GPL");