2 * Fast Ethernet Controller (FEC) driver for Motorola MPC8xx.
3 * Copyright (c) 1997 Dan Malek (dmalek@jlc.net)
5 * This version of the driver is specific to the FADS implementation,
6 * since the board contains control registers external to the processor
7 * for the control of the LevelOne LXT970 transceiver. The MPC860T manual
8 * describes connections using the internal parallel port I/O, which
9 * is basically all of Port D.
11 * Right now, I am very wasteful with the buffers. I allocate memory
12 * pages and then divide them into 2K frame buffers. This way I know I
13 * have buffers large enough to hold one frame within one buffer descriptor.
14 * Once I get this working, I will use 64 or 128 byte CPM buffers, which
15 * will be much more memory efficient and will easily handle lots of
18 * Much better multiple PHY support by Magnus Damm.
19 * Copyright (c) 2000 Ericsson Radio Systems AB.
21 * Support for FEC controller of ColdFire processors.
22 * Copyright (c) 2001-2005 Greg Ungerer (gerg@snapgear.com)
24 * Bug fixes and cleanup by Philippe De Muyter (phdm@macqel.be)
25 * Copyright (c) 2004-2006 Macq Electronique SA.
28 #include <linux/config.h>
29 #include <linux/module.h>
30 #include <linux/kernel.h>
31 #include <linux/string.h>
32 #include <linux/ptrace.h>
33 #include <linux/errno.h>
34 #include <linux/ioport.h>
35 #include <linux/slab.h>
36 #include <linux/interrupt.h>
37 #include <linux/pci.h>
38 #include <linux/init.h>
39 #include <linux/delay.h>
40 #include <linux/netdevice.h>
41 #include <linux/etherdevice.h>
42 #include <linux/skbuff.h>
43 #include <linux/spinlock.h>
44 #include <linux/workqueue.h>
45 #include <linux/bitops.h>
48 #include <asm/uaccess.h>
50 #include <asm/pgtable.h>
52 #if defined(CONFIG_M523x) || defined(CONFIG_M527x) || \
53 defined(CONFIG_M5272) || defined(CONFIG_M528x) || \
54 defined(CONFIG_M520x) || defined(CONFIG_M532x)
55 #include <asm/coldfire.h>
56 #include <asm/mcfsim.h>
59 #include <asm/8xx_immap.h>
60 #include <asm/mpc8xx.h>
64 #if defined(CONFIG_FEC2)
65 #define FEC_MAX_PORTS 2
67 #define FEC_MAX_PORTS 1
71 * Define the fixed address of the FEC hardware.
73 static unsigned int fec_hw[] = {
74 #if defined(CONFIG_M5272)
76 #elif defined(CONFIG_M527x)
79 #elif defined(CONFIG_M523x) || defined(CONFIG_M528x)
81 #elif defined(CONFIG_M520x)
83 #elif defined(CONFIG_M532x)
84 (MCF_MBAR+0xfc030000),
86 &(((immap_t *)IMAP_ADDR)->im_cpm.cp_fec),
90 static unsigned char fec_mac_default[] = {
91 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
95 * Some hardware gets it MAC address out of local flash memory.
96 * if this is non-zero then assume it is the address to get MAC from.
98 #if defined(CONFIG_NETtel)
99 #define FEC_FLASHMAC 0xf0006006
100 #elif defined(CONFIG_GILBARCONAP) || defined(CONFIG_SCALES)
101 #define FEC_FLASHMAC 0xf0006000
102 #elif defined (CONFIG_MTD_KeyTechnology)
103 #define FEC_FLASHMAC 0xffe04000
104 #elif defined(CONFIG_CANCam)
105 #define FEC_FLASHMAC 0xf0020000
106 #elif defined (CONFIG_M5272C3)
107 #define FEC_FLASHMAC (0xffe04000 + 4)
108 #elif defined(CONFIG_MOD5272)
109 #define FEC_FLASHMAC 0xffc0406b
111 #define FEC_FLASHMAC 0
114 /* Forward declarations of some structures to support different PHYs
119 void (*funct)(uint mii_reg, struct net_device *dev);
126 const phy_cmd_t *config;
127 const phy_cmd_t *startup;
128 const phy_cmd_t *ack_int;
129 const phy_cmd_t *shutdown;
132 /* The number of Tx and Rx buffers. These are allocated from the page
133 * pool. The code may assume these are power of two, so it it best
134 * to keep them that size.
135 * We don't need to allocate pages for the transmitter. We just use
136 * the skbuffer directly.
138 #define FEC_ENET_RX_PAGES 8
139 #define FEC_ENET_RX_FRSIZE 2048
140 #define FEC_ENET_RX_FRPPG (PAGE_SIZE / FEC_ENET_RX_FRSIZE)
141 #define RX_RING_SIZE (FEC_ENET_RX_FRPPG * FEC_ENET_RX_PAGES)
142 #define FEC_ENET_TX_FRSIZE 2048
143 #define FEC_ENET_TX_FRPPG (PAGE_SIZE / FEC_ENET_TX_FRSIZE)
144 #define TX_RING_SIZE 16 /* Must be power of two */
145 #define TX_RING_MOD_MASK 15 /* for this to work */
147 #if (((RX_RING_SIZE + TX_RING_SIZE) * 8) > PAGE_SIZE)
148 #error "FEC: descriptor ring size constants too large"
151 /* Interrupt events/masks.
153 #define FEC_ENET_HBERR ((uint)0x80000000) /* Heartbeat error */
154 #define FEC_ENET_BABR ((uint)0x40000000) /* Babbling receiver */
155 #define FEC_ENET_BABT ((uint)0x20000000) /* Babbling transmitter */
156 #define FEC_ENET_GRA ((uint)0x10000000) /* Graceful stop complete */
157 #define FEC_ENET_TXF ((uint)0x08000000) /* Full frame transmitted */
158 #define FEC_ENET_TXB ((uint)0x04000000) /* A buffer was transmitted */
159 #define FEC_ENET_RXF ((uint)0x02000000) /* Full frame received */
160 #define FEC_ENET_RXB ((uint)0x01000000) /* A buffer was received */
161 #define FEC_ENET_MII ((uint)0x00800000) /* MII interrupt */
162 #define FEC_ENET_EBERR ((uint)0x00400000) /* SDMA bus error */
164 /* The FEC stores dest/src/type, data, and checksum for receive packets.
166 #define PKT_MAXBUF_SIZE 1518
167 #define PKT_MINBUF_SIZE 64
168 #define PKT_MAXBLR_SIZE 1520
172 * The 5270/5271/5280/5282/532x RX control register also contains maximum frame
173 * size bits. Other FEC hardware does not, so we need to take that into
174 * account when setting it.
176 #if defined(CONFIG_M523x) || defined(CONFIG_M527x) || defined(CONFIG_M528x) || \
177 defined(CONFIG_M520x) || defined(CONFIG_M532x)
178 #define OPT_FRAME_SIZE (PKT_MAXBUF_SIZE << 16)
180 #define OPT_FRAME_SIZE 0
183 /* The FEC buffer descriptors track the ring buffers. The rx_bd_base and
184 * tx_bd_base always point to the base of the buffer descriptors. The
185 * cur_rx and cur_tx point to the currently available buffer.
186 * The dirty_tx tracks the current buffer that is being sent by the
187 * controller. The cur_tx and dirty_tx are equal under both completely
188 * empty and completely full conditions. The empty/ready indicator in
189 * the buffer descriptor determines the actual condition.
191 struct fec_enet_private {
192 /* Hardware registers of the FEC device */
195 /* The saved address of a sent-in-place packet/buffer, for skfree(). */
196 unsigned char *tx_bounce[TX_RING_SIZE];
197 struct sk_buff* tx_skbuff[TX_RING_SIZE];
201 /* CPM dual port RAM relative addresses.
203 cbd_t *rx_bd_base; /* Address of Rx and Tx buffers. */
205 cbd_t *cur_rx, *cur_tx; /* The next free ring entry */
206 cbd_t *dirty_tx; /* The ring entries to be free()ed. */
207 struct net_device_stats stats;
215 phy_info_t const *phy;
216 struct work_struct phy_task;
219 uint mii_phy_task_queued;
230 static int fec_enet_open(struct net_device *dev);
231 static int fec_enet_start_xmit(struct sk_buff *skb, struct net_device *dev);
232 static void fec_enet_mii(struct net_device *dev);
233 static irqreturn_t fec_enet_interrupt(int irq, void * dev_id, struct pt_regs * regs);
234 static void fec_enet_tx(struct net_device *dev);
235 static void fec_enet_rx(struct net_device *dev);
236 static int fec_enet_close(struct net_device *dev);
237 static struct net_device_stats *fec_enet_get_stats(struct net_device *dev);
238 static void set_multicast_list(struct net_device *dev);
239 static void fec_restart(struct net_device *dev, int duplex);
240 static void fec_stop(struct net_device *dev);
241 static void fec_set_mac_address(struct net_device *dev);
244 /* MII processing. We keep this as simple as possible. Requests are
245 * placed on the list (if there is room). When the request is finished
246 * by the MII, an optional function may be called.
248 typedef struct mii_list {
250 void (*mii_func)(uint val, struct net_device *dev);
251 struct mii_list *mii_next;
255 static mii_list_t mii_cmds[NMII];
256 static mii_list_t *mii_free;
257 static mii_list_t *mii_head;
258 static mii_list_t *mii_tail;
260 static int mii_queue(struct net_device *dev, int request,
261 void (*func)(uint, struct net_device *));
263 /* Make MII read/write commands for the FEC.
265 #define mk_mii_read(REG) (0x60020000 | ((REG & 0x1f) << 18))
266 #define mk_mii_write(REG, VAL) (0x50020000 | ((REG & 0x1f) << 18) | \
270 /* Transmitter timeout.
272 #define TX_TIMEOUT (2*HZ)
274 /* Register definitions for the PHY.
277 #define MII_REG_CR 0 /* Control Register */
278 #define MII_REG_SR 1 /* Status Register */
279 #define MII_REG_PHYIR1 2 /* PHY Identification Register 1 */
280 #define MII_REG_PHYIR2 3 /* PHY Identification Register 2 */
281 #define MII_REG_ANAR 4 /* A-N Advertisement Register */
282 #define MII_REG_ANLPAR 5 /* A-N Link Partner Ability Register */
283 #define MII_REG_ANER 6 /* A-N Expansion Register */
284 #define MII_REG_ANNPTR 7 /* A-N Next Page Transmit Register */
285 #define MII_REG_ANLPRNPR 8 /* A-N Link Partner Received Next Page Reg. */
287 /* values for phy_status */
289 #define PHY_CONF_ANE 0x0001 /* 1 auto-negotiation enabled */
290 #define PHY_CONF_LOOP 0x0002 /* 1 loopback mode enabled */
291 #define PHY_CONF_SPMASK 0x00f0 /* mask for speed */
292 #define PHY_CONF_10HDX 0x0010 /* 10 Mbit half duplex supported */
293 #define PHY_CONF_10FDX 0x0020 /* 10 Mbit full duplex supported */
294 #define PHY_CONF_100HDX 0x0040 /* 100 Mbit half duplex supported */
295 #define PHY_CONF_100FDX 0x0080 /* 100 Mbit full duplex supported */
297 #define PHY_STAT_LINK 0x0100 /* 1 up - 0 down */
298 #define PHY_STAT_FAULT 0x0200 /* 1 remote fault */
299 #define PHY_STAT_ANC 0x0400 /* 1 auto-negotiation complete */
300 #define PHY_STAT_SPMASK 0xf000 /* mask for speed */
301 #define PHY_STAT_10HDX 0x1000 /* 10 Mbit half duplex selected */
302 #define PHY_STAT_10FDX 0x2000 /* 10 Mbit full duplex selected */
303 #define PHY_STAT_100HDX 0x4000 /* 100 Mbit half duplex selected */
304 #define PHY_STAT_100FDX 0x8000 /* 100 Mbit full duplex selected */
308 fec_enet_start_xmit(struct sk_buff *skb, struct net_device *dev)
310 struct fec_enet_private *fep;
311 volatile fec_t *fecp;
314 fep = netdev_priv(dev);
315 fecp = (volatile fec_t*)dev->base_addr;
318 /* Link is down or autonegotiation is in progress. */
322 /* Fill in a Tx ring entry */
325 #ifndef final_version
326 if (bdp->cbd_sc & BD_ENET_TX_READY) {
327 /* Ooops. All transmit buffers are full. Bail out.
328 * This should not happen, since dev->tbusy should be set.
330 printk("%s: tx queue full!.\n", dev->name);
335 /* Clear all of the status flags.
337 bdp->cbd_sc &= ~BD_ENET_TX_STATS;
339 /* Set buffer length and buffer pointer.
341 bdp->cbd_bufaddr = __pa(skb->data);
342 bdp->cbd_datlen = skb->len;
345 * On some FEC implementations data must be aligned on
346 * 4-byte boundaries. Use bounce buffers to copy data
347 * and get it aligned. Ugh.
349 if (bdp->cbd_bufaddr & 0x3) {
351 index = bdp - fep->tx_bd_base;
352 memcpy(fep->tx_bounce[index], (void *) bdp->cbd_bufaddr, bdp->cbd_datlen);
353 bdp->cbd_bufaddr = __pa(fep->tx_bounce[index]);
358 fep->tx_skbuff[fep->skb_cur] = skb;
360 fep->stats.tx_bytes += skb->len;
361 fep->skb_cur = (fep->skb_cur+1) & TX_RING_MOD_MASK;
363 /* Push the data cache so the CPM does not get stale memory
366 flush_dcache_range((unsigned long)skb->data,
367 (unsigned long)skb->data + skb->len);
369 spin_lock_irq(&fep->lock);
371 /* Send it on its way. Tell FEC its ready, interrupt when done,
372 * its the last BD of the frame, and to put the CRC on the end.
375 bdp->cbd_sc |= (BD_ENET_TX_READY | BD_ENET_TX_INTR
376 | BD_ENET_TX_LAST | BD_ENET_TX_TC);
378 dev->trans_start = jiffies;
380 /* Trigger transmission start */
381 fecp->fec_x_des_active = 0x01000000;
383 /* If this was the last BD in the ring, start at the beginning again.
385 if (bdp->cbd_sc & BD_ENET_TX_WRAP) {
386 bdp = fep->tx_bd_base;
391 if (bdp == fep->dirty_tx) {
393 netif_stop_queue(dev);
396 fep->cur_tx = (cbd_t *)bdp;
398 spin_unlock_irq(&fep->lock);
404 fec_timeout(struct net_device *dev)
406 struct fec_enet_private *fep = netdev_priv(dev);
408 printk("%s: transmit timed out.\n", dev->name);
409 fep->stats.tx_errors++;
410 #ifndef final_version
415 printk("Ring data dump: cur_tx %lx%s, dirty_tx %lx cur_rx: %lx\n",
416 (unsigned long)fep->cur_tx, fep->tx_full ? " (full)" : "",
417 (unsigned long)fep->dirty_tx,
418 (unsigned long)fep->cur_rx);
420 bdp = fep->tx_bd_base;
421 printk(" tx: %u buffers\n", TX_RING_SIZE);
422 for (i = 0 ; i < TX_RING_SIZE; i++) {
423 printk(" %08x: %04x %04x %08x\n",
427 (int) bdp->cbd_bufaddr);
431 bdp = fep->rx_bd_base;
432 printk(" rx: %lu buffers\n", (unsigned long) RX_RING_SIZE);
433 for (i = 0 ; i < RX_RING_SIZE; i++) {
434 printk(" %08x: %04x %04x %08x\n",
438 (int) bdp->cbd_bufaddr);
443 fec_restart(dev, fep->full_duplex);
444 netif_wake_queue(dev);
447 /* The interrupt handler.
448 * This is called from the MPC core interrupt.
451 fec_enet_interrupt(int irq, void * dev_id, struct pt_regs * regs)
453 struct net_device *dev = dev_id;
454 volatile fec_t *fecp;
458 fecp = (volatile fec_t*)dev->base_addr;
460 /* Get the interrupt events that caused us to be here.
462 while ((int_events = fecp->fec_ievent) != 0) {
463 fecp->fec_ievent = int_events;
465 /* Handle receive event in its own function.
467 if (int_events & FEC_ENET_RXF) {
472 /* Transmit OK, or non-fatal error. Update the buffer
473 descriptors. FEC handles all errors, we just discover
474 them as part of the transmit process.
476 if (int_events & FEC_ENET_TXF) {
481 if (int_events & FEC_ENET_MII) {
487 return IRQ_RETVAL(handled);
492 fec_enet_tx(struct net_device *dev)
494 struct fec_enet_private *fep;
498 fep = netdev_priv(dev);
499 spin_lock(&fep->lock);
502 while ((bdp->cbd_sc&BD_ENET_TX_READY) == 0) {
503 if (bdp == fep->cur_tx && fep->tx_full == 0) break;
505 skb = fep->tx_skbuff[fep->skb_dirty];
506 /* Check for errors. */
507 if (bdp->cbd_sc & (BD_ENET_TX_HB | BD_ENET_TX_LC |
508 BD_ENET_TX_RL | BD_ENET_TX_UN |
510 fep->stats.tx_errors++;
511 if (bdp->cbd_sc & BD_ENET_TX_HB) /* No heartbeat */
512 fep->stats.tx_heartbeat_errors++;
513 if (bdp->cbd_sc & BD_ENET_TX_LC) /* Late collision */
514 fep->stats.tx_window_errors++;
515 if (bdp->cbd_sc & BD_ENET_TX_RL) /* Retrans limit */
516 fep->stats.tx_aborted_errors++;
517 if (bdp->cbd_sc & BD_ENET_TX_UN) /* Underrun */
518 fep->stats.tx_fifo_errors++;
519 if (bdp->cbd_sc & BD_ENET_TX_CSL) /* Carrier lost */
520 fep->stats.tx_carrier_errors++;
522 fep->stats.tx_packets++;
525 #ifndef final_version
526 if (bdp->cbd_sc & BD_ENET_TX_READY)
527 printk("HEY! Enet xmit interrupt and TX_READY.\n");
529 /* Deferred means some collisions occurred during transmit,
530 * but we eventually sent the packet OK.
532 if (bdp->cbd_sc & BD_ENET_TX_DEF)
533 fep->stats.collisions++;
535 /* Free the sk buffer associated with this last transmit.
537 dev_kfree_skb_any(skb);
538 fep->tx_skbuff[fep->skb_dirty] = NULL;
539 fep->skb_dirty = (fep->skb_dirty + 1) & TX_RING_MOD_MASK;
541 /* Update pointer to next buffer descriptor to be transmitted.
543 if (bdp->cbd_sc & BD_ENET_TX_WRAP)
544 bdp = fep->tx_bd_base;
548 /* Since we have freed up a buffer, the ring is no longer
553 if (netif_queue_stopped(dev))
554 netif_wake_queue(dev);
557 fep->dirty_tx = (cbd_t *)bdp;
558 spin_unlock(&fep->lock);
562 /* During a receive, the cur_rx points to the current incoming buffer.
563 * When we update through the ring, if the next incoming buffer has
564 * not been given to the system, we just set the empty indicator,
565 * effectively tossing the packet.
568 fec_enet_rx(struct net_device *dev)
570 struct fec_enet_private *fep;
571 volatile fec_t *fecp;
577 fep = netdev_priv(dev);
578 fecp = (volatile fec_t*)dev->base_addr;
580 /* First, grab all of the stats for the incoming packet.
581 * These get messed up if we get called due to a busy condition.
585 while (!(bdp->cbd_sc & BD_ENET_RX_EMPTY)) {
587 #ifndef final_version
588 /* Since we have allocated space to hold a complete frame,
589 * the last indicator should be set.
591 if ((bdp->cbd_sc & BD_ENET_RX_LAST) == 0)
592 printk("FEC ENET: rcv is not +last\n");
596 goto rx_processing_done;
598 /* Check for errors. */
599 if (bdp->cbd_sc & (BD_ENET_RX_LG | BD_ENET_RX_SH | BD_ENET_RX_NO |
600 BD_ENET_RX_CR | BD_ENET_RX_OV)) {
601 fep->stats.rx_errors++;
602 if (bdp->cbd_sc & (BD_ENET_RX_LG | BD_ENET_RX_SH)) {
603 /* Frame too long or too short. */
604 fep->stats.rx_length_errors++;
606 if (bdp->cbd_sc & BD_ENET_RX_NO) /* Frame alignment */
607 fep->stats.rx_frame_errors++;
608 if (bdp->cbd_sc & BD_ENET_RX_CR) /* CRC Error */
609 fep->stats.rx_crc_errors++;
610 if (bdp->cbd_sc & BD_ENET_RX_OV) /* FIFO overrun */
611 fep->stats.rx_crc_errors++;
614 /* Report late collisions as a frame error.
615 * On this error, the BD is closed, but we don't know what we
616 * have in the buffer. So, just drop this frame on the floor.
618 if (bdp->cbd_sc & BD_ENET_RX_CL) {
619 fep->stats.rx_errors++;
620 fep->stats.rx_frame_errors++;
621 goto rx_processing_done;
624 /* Process the incoming frame.
626 fep->stats.rx_packets++;
627 pkt_len = bdp->cbd_datlen;
628 fep->stats.rx_bytes += pkt_len;
629 data = (__u8*)__va(bdp->cbd_bufaddr);
631 /* This does 16 byte alignment, exactly what we need.
632 * The packet length includes FCS, but we don't want to
633 * include that when passing upstream as it messes up
634 * bridging applications.
636 skb = dev_alloc_skb(pkt_len-4);
639 printk("%s: Memory squeeze, dropping packet.\n", dev->name);
640 fep->stats.rx_dropped++;
643 skb_put(skb,pkt_len-4); /* Make room */
644 eth_copy_and_sum(skb,
645 (unsigned char *)__va(bdp->cbd_bufaddr),
647 skb->protocol=eth_type_trans(skb,dev);
652 /* Clear the status flags for this buffer.
654 bdp->cbd_sc &= ~BD_ENET_RX_STATS;
656 /* Mark the buffer empty.
658 bdp->cbd_sc |= BD_ENET_RX_EMPTY;
660 /* Update BD pointer to next entry.
662 if (bdp->cbd_sc & BD_ENET_RX_WRAP)
663 bdp = fep->rx_bd_base;
668 /* Doing this here will keep the FEC running while we process
669 * incoming frames. On a heavily loaded network, we should be
670 * able to keep up at the expense of system resources.
672 fecp->fec_r_des_active = 0x01000000;
674 } /* while (!(bdp->cbd_sc & BD_ENET_RX_EMPTY)) */
675 fep->cur_rx = (cbd_t *)bdp;
678 /* Doing this here will allow us to process all frames in the
679 * ring before the FEC is allowed to put more there. On a heavily
680 * loaded network, some frames may be lost. Unfortunately, this
681 * increases the interrupt overhead since we can potentially work
682 * our way back to the interrupt return only to come right back
685 fecp->fec_r_des_active = 0x01000000;
691 fec_enet_mii(struct net_device *dev)
693 struct fec_enet_private *fep;
698 fep = netdev_priv(dev);
700 mii_reg = ep->fec_mii_data;
702 if ((mip = mii_head) == NULL) {
703 printk("MII and no head!\n");
707 if (mip->mii_func != NULL)
708 (*(mip->mii_func))(mii_reg, dev);
710 mii_head = mip->mii_next;
711 mip->mii_next = mii_free;
714 if ((mip = mii_head) != NULL)
715 ep->fec_mii_data = mip->mii_regval;
719 mii_queue(struct net_device *dev, int regval, void (*func)(uint, struct net_device *))
721 struct fec_enet_private *fep;
726 /* Add PHY address to register command.
728 fep = netdev_priv(dev);
729 regval |= fep->phy_addr << 23;
736 if ((mip = mii_free) != NULL) {
737 mii_free = mip->mii_next;
738 mip->mii_regval = regval;
739 mip->mii_func = func;
740 mip->mii_next = NULL;
742 mii_tail->mii_next = mip;
746 mii_head = mii_tail = mip;
747 fep->hwp->fec_mii_data = regval;
754 restore_flags(flags);
759 static void mii_do_cmd(struct net_device *dev, const phy_cmd_t *c)
766 for(k = 0; (c+k)->mii_data != mk_mii_end; k++) {
767 mii_queue(dev, (c+k)->mii_data, (c+k)->funct);
771 static void mii_parse_sr(uint mii_reg, struct net_device *dev)
773 struct fec_enet_private *fep = netdev_priv(dev);
774 volatile uint *s = &(fep->phy_status);
777 status = *s & ~(PHY_STAT_LINK | PHY_STAT_FAULT | PHY_STAT_ANC);
779 if (mii_reg & 0x0004)
780 status |= PHY_STAT_LINK;
781 if (mii_reg & 0x0010)
782 status |= PHY_STAT_FAULT;
783 if (mii_reg & 0x0020)
784 status |= PHY_STAT_ANC;
789 static void mii_parse_cr(uint mii_reg, struct net_device *dev)
791 struct fec_enet_private *fep = netdev_priv(dev);
792 volatile uint *s = &(fep->phy_status);
795 status = *s & ~(PHY_CONF_ANE | PHY_CONF_LOOP);
797 if (mii_reg & 0x1000)
798 status |= PHY_CONF_ANE;
799 if (mii_reg & 0x4000)
800 status |= PHY_CONF_LOOP;
804 static void mii_parse_anar(uint mii_reg, struct net_device *dev)
806 struct fec_enet_private *fep = netdev_priv(dev);
807 volatile uint *s = &(fep->phy_status);
810 status = *s & ~(PHY_CONF_SPMASK);
812 if (mii_reg & 0x0020)
813 status |= PHY_CONF_10HDX;
814 if (mii_reg & 0x0040)
815 status |= PHY_CONF_10FDX;
816 if (mii_reg & 0x0080)
817 status |= PHY_CONF_100HDX;
818 if (mii_reg & 0x00100)
819 status |= PHY_CONF_100FDX;
823 /* ------------------------------------------------------------------------- */
824 /* The Level one LXT970 is used by many boards */
826 #define MII_LXT970_MIRROR 16 /* Mirror register */
827 #define MII_LXT970_IER 17 /* Interrupt Enable Register */
828 #define MII_LXT970_ISR 18 /* Interrupt Status Register */
829 #define MII_LXT970_CONFIG 19 /* Configuration Register */
830 #define MII_LXT970_CSR 20 /* Chip Status Register */
832 static void mii_parse_lxt970_csr(uint mii_reg, struct net_device *dev)
834 struct fec_enet_private *fep = netdev_priv(dev);
835 volatile uint *s = &(fep->phy_status);
838 status = *s & ~(PHY_STAT_SPMASK);
839 if (mii_reg & 0x0800) {
840 if (mii_reg & 0x1000)
841 status |= PHY_STAT_100FDX;
843 status |= PHY_STAT_100HDX;
845 if (mii_reg & 0x1000)
846 status |= PHY_STAT_10FDX;
848 status |= PHY_STAT_10HDX;
853 static phy_cmd_t const phy_cmd_lxt970_config[] = {
854 { mk_mii_read(MII_REG_CR), mii_parse_cr },
855 { mk_mii_read(MII_REG_ANAR), mii_parse_anar },
858 static phy_cmd_t const phy_cmd_lxt970_startup[] = { /* enable interrupts */
859 { mk_mii_write(MII_LXT970_IER, 0x0002), NULL },
860 { mk_mii_write(MII_REG_CR, 0x1200), NULL }, /* autonegotiate */
863 static phy_cmd_t const phy_cmd_lxt970_ack_int[] = {
864 /* read SR and ISR to acknowledge */
865 { mk_mii_read(MII_REG_SR), mii_parse_sr },
866 { mk_mii_read(MII_LXT970_ISR), NULL },
868 /* find out the current status */
869 { mk_mii_read(MII_LXT970_CSR), mii_parse_lxt970_csr },
872 static phy_cmd_t const phy_cmd_lxt970_shutdown[] = { /* disable interrupts */
873 { mk_mii_write(MII_LXT970_IER, 0x0000), NULL },
876 static phy_info_t const phy_info_lxt970 = {
879 .config = phy_cmd_lxt970_config,
880 .startup = phy_cmd_lxt970_startup,
881 .ack_int = phy_cmd_lxt970_ack_int,
882 .shutdown = phy_cmd_lxt970_shutdown
885 /* ------------------------------------------------------------------------- */
886 /* The Level one LXT971 is used on some of my custom boards */
888 /* register definitions for the 971 */
890 #define MII_LXT971_PCR 16 /* Port Control Register */
891 #define MII_LXT971_SR2 17 /* Status Register 2 */
892 #define MII_LXT971_IER 18 /* Interrupt Enable Register */
893 #define MII_LXT971_ISR 19 /* Interrupt Status Register */
894 #define MII_LXT971_LCR 20 /* LED Control Register */
895 #define MII_LXT971_TCR 30 /* Transmit Control Register */
898 * I had some nice ideas of running the MDIO faster...
899 * The 971 should support 8MHz and I tried it, but things acted really
900 * weird, so 2.5 MHz ought to be enough for anyone...
903 static void mii_parse_lxt971_sr2(uint mii_reg, struct net_device *dev)
905 struct fec_enet_private *fep = netdev_priv(dev);
906 volatile uint *s = &(fep->phy_status);
909 status = *s & ~(PHY_STAT_SPMASK | PHY_STAT_LINK | PHY_STAT_ANC);
911 if (mii_reg & 0x0400) {
913 status |= PHY_STAT_LINK;
917 if (mii_reg & 0x0080)
918 status |= PHY_STAT_ANC;
919 if (mii_reg & 0x4000) {
920 if (mii_reg & 0x0200)
921 status |= PHY_STAT_100FDX;
923 status |= PHY_STAT_100HDX;
925 if (mii_reg & 0x0200)
926 status |= PHY_STAT_10FDX;
928 status |= PHY_STAT_10HDX;
930 if (mii_reg & 0x0008)
931 status |= PHY_STAT_FAULT;
936 static phy_cmd_t const phy_cmd_lxt971_config[] = {
937 /* limit to 10MBit because my prototype board
938 * doesn't work with 100. */
939 { mk_mii_read(MII_REG_CR), mii_parse_cr },
940 { mk_mii_read(MII_REG_ANAR), mii_parse_anar },
941 { mk_mii_read(MII_LXT971_SR2), mii_parse_lxt971_sr2 },
944 static phy_cmd_t const phy_cmd_lxt971_startup[] = { /* enable interrupts */
945 { mk_mii_write(MII_LXT971_IER, 0x00f2), NULL },
946 { mk_mii_write(MII_REG_CR, 0x1200), NULL }, /* autonegotiate */
947 { mk_mii_write(MII_LXT971_LCR, 0xd422), NULL }, /* LED config */
948 /* Somehow does the 971 tell me that the link is down
949 * the first read after power-up.
950 * read here to get a valid value in ack_int */
951 { mk_mii_read(MII_REG_SR), mii_parse_sr },
954 static phy_cmd_t const phy_cmd_lxt971_ack_int[] = {
955 /* acknowledge the int before reading status ! */
956 { mk_mii_read(MII_LXT971_ISR), NULL },
957 /* find out the current status */
958 { mk_mii_read(MII_REG_SR), mii_parse_sr },
959 { mk_mii_read(MII_LXT971_SR2), mii_parse_lxt971_sr2 },
962 static phy_cmd_t const phy_cmd_lxt971_shutdown[] = { /* disable interrupts */
963 { mk_mii_write(MII_LXT971_IER, 0x0000), NULL },
966 static phy_info_t const phy_info_lxt971 = {
969 .config = phy_cmd_lxt971_config,
970 .startup = phy_cmd_lxt971_startup,
971 .ack_int = phy_cmd_lxt971_ack_int,
972 .shutdown = phy_cmd_lxt971_shutdown
975 /* ------------------------------------------------------------------------- */
976 /* The Quality Semiconductor QS6612 is used on the RPX CLLF */
978 /* register definitions */
980 #define MII_QS6612_MCR 17 /* Mode Control Register */
981 #define MII_QS6612_FTR 27 /* Factory Test Register */
982 #define MII_QS6612_MCO 28 /* Misc. Control Register */
983 #define MII_QS6612_ISR 29 /* Interrupt Source Register */
984 #define MII_QS6612_IMR 30 /* Interrupt Mask Register */
985 #define MII_QS6612_PCR 31 /* 100BaseTx PHY Control Reg. */
987 static void mii_parse_qs6612_pcr(uint mii_reg, struct net_device *dev)
989 struct fec_enet_private *fep = netdev_priv(dev);
990 volatile uint *s = &(fep->phy_status);
993 status = *s & ~(PHY_STAT_SPMASK);
995 switch((mii_reg >> 2) & 7) {
996 case 1: status |= PHY_STAT_10HDX; break;
997 case 2: status |= PHY_STAT_100HDX; break;
998 case 5: status |= PHY_STAT_10FDX; break;
999 case 6: status |= PHY_STAT_100FDX; break;
1005 static phy_cmd_t const phy_cmd_qs6612_config[] = {
1006 /* The PHY powers up isolated on the RPX,
1007 * so send a command to allow operation.
1009 { mk_mii_write(MII_QS6612_PCR, 0x0dc0), NULL },
1011 /* parse cr and anar to get some info */
1012 { mk_mii_read(MII_REG_CR), mii_parse_cr },
1013 { mk_mii_read(MII_REG_ANAR), mii_parse_anar },
1016 static phy_cmd_t const phy_cmd_qs6612_startup[] = { /* enable interrupts */
1017 { mk_mii_write(MII_QS6612_IMR, 0x003a), NULL },
1018 { mk_mii_write(MII_REG_CR, 0x1200), NULL }, /* autonegotiate */
1021 static phy_cmd_t const phy_cmd_qs6612_ack_int[] = {
1022 /* we need to read ISR, SR and ANER to acknowledge */
1023 { mk_mii_read(MII_QS6612_ISR), NULL },
1024 { mk_mii_read(MII_REG_SR), mii_parse_sr },
1025 { mk_mii_read(MII_REG_ANER), NULL },
1027 /* read pcr to get info */
1028 { mk_mii_read(MII_QS6612_PCR), mii_parse_qs6612_pcr },
1031 static phy_cmd_t const phy_cmd_qs6612_shutdown[] = { /* disable interrupts */
1032 { mk_mii_write(MII_QS6612_IMR, 0x0000), NULL },
1035 static phy_info_t const phy_info_qs6612 = {
1038 .config = phy_cmd_qs6612_config,
1039 .startup = phy_cmd_qs6612_startup,
1040 .ack_int = phy_cmd_qs6612_ack_int,
1041 .shutdown = phy_cmd_qs6612_shutdown
1044 /* ------------------------------------------------------------------------- */
1045 /* AMD AM79C874 phy */
1047 /* register definitions for the 874 */
1049 #define MII_AM79C874_MFR 16 /* Miscellaneous Feature Register */
1050 #define MII_AM79C874_ICSR 17 /* Interrupt/Status Register */
1051 #define MII_AM79C874_DR 18 /* Diagnostic Register */
1052 #define MII_AM79C874_PMLR 19 /* Power and Loopback Register */
1053 #define MII_AM79C874_MCR 21 /* ModeControl Register */
1054 #define MII_AM79C874_DC 23 /* Disconnect Counter */
1055 #define MII_AM79C874_REC 24 /* Recieve Error Counter */
1057 static void mii_parse_am79c874_dr(uint mii_reg, struct net_device *dev)
1059 struct fec_enet_private *fep = netdev_priv(dev);
1060 volatile uint *s = &(fep->phy_status);
1063 status = *s & ~(PHY_STAT_SPMASK | PHY_STAT_ANC);
1065 if (mii_reg & 0x0080)
1066 status |= PHY_STAT_ANC;
1067 if (mii_reg & 0x0400)
1068 status |= ((mii_reg & 0x0800) ? PHY_STAT_100FDX : PHY_STAT_100HDX);
1070 status |= ((mii_reg & 0x0800) ? PHY_STAT_10FDX : PHY_STAT_10HDX);
1075 static phy_cmd_t const phy_cmd_am79c874_config[] = {
1076 { mk_mii_read(MII_REG_CR), mii_parse_cr },
1077 { mk_mii_read(MII_REG_ANAR), mii_parse_anar },
1078 { mk_mii_read(MII_AM79C874_DR), mii_parse_am79c874_dr },
1081 static phy_cmd_t const phy_cmd_am79c874_startup[] = { /* enable interrupts */
1082 { mk_mii_write(MII_AM79C874_ICSR, 0xff00), NULL },
1083 { mk_mii_write(MII_REG_CR, 0x1200), NULL }, /* autonegotiate */
1084 { mk_mii_read(MII_REG_SR), mii_parse_sr },
1087 static phy_cmd_t const phy_cmd_am79c874_ack_int[] = {
1088 /* find out the current status */
1089 { mk_mii_read(MII_REG_SR), mii_parse_sr },
1090 { mk_mii_read(MII_AM79C874_DR), mii_parse_am79c874_dr },
1091 /* we only need to read ISR to acknowledge */
1092 { mk_mii_read(MII_AM79C874_ICSR), NULL },
1095 static phy_cmd_t const phy_cmd_am79c874_shutdown[] = { /* disable interrupts */
1096 { mk_mii_write(MII_AM79C874_ICSR, 0x0000), NULL },
1099 static phy_info_t const phy_info_am79c874 = {
1102 .config = phy_cmd_am79c874_config,
1103 .startup = phy_cmd_am79c874_startup,
1104 .ack_int = phy_cmd_am79c874_ack_int,
1105 .shutdown = phy_cmd_am79c874_shutdown
1109 /* ------------------------------------------------------------------------- */
1110 /* Kendin KS8721BL phy */
1112 /* register definitions for the 8721 */
1114 #define MII_KS8721BL_RXERCR 21
1115 #define MII_KS8721BL_ICSR 22
1116 #define MII_KS8721BL_PHYCR 31
1118 static phy_cmd_t const phy_cmd_ks8721bl_config[] = {
1119 { mk_mii_read(MII_REG_CR), mii_parse_cr },
1120 { mk_mii_read(MII_REG_ANAR), mii_parse_anar },
1123 static phy_cmd_t const phy_cmd_ks8721bl_startup[] = { /* enable interrupts */
1124 { mk_mii_write(MII_KS8721BL_ICSR, 0xff00), NULL },
1125 { mk_mii_write(MII_REG_CR, 0x1200), NULL }, /* autonegotiate */
1126 { mk_mii_read(MII_REG_SR), mii_parse_sr },
1129 static phy_cmd_t const phy_cmd_ks8721bl_ack_int[] = {
1130 /* find out the current status */
1131 { mk_mii_read(MII_REG_SR), mii_parse_sr },
1132 /* we only need to read ISR to acknowledge */
1133 { mk_mii_read(MII_KS8721BL_ICSR), NULL },
1136 static phy_cmd_t const phy_cmd_ks8721bl_shutdown[] = { /* disable interrupts */
1137 { mk_mii_write(MII_KS8721BL_ICSR, 0x0000), NULL },
1140 static phy_info_t const phy_info_ks8721bl = {
1143 .config = phy_cmd_ks8721bl_config,
1144 .startup = phy_cmd_ks8721bl_startup,
1145 .ack_int = phy_cmd_ks8721bl_ack_int,
1146 .shutdown = phy_cmd_ks8721bl_shutdown
1149 /* ------------------------------------------------------------------------- */
1150 /* register definitions for the DP83848 */
1152 #define MII_DP8384X_PHYSTST 16 /* PHY Status Register */
1154 static void mii_parse_dp8384x_sr2(uint mii_reg, struct net_device *dev)
1156 struct fec_enet_private *fep = dev->priv;
1157 volatile uint *s = &(fep->phy_status);
1159 *s &= ~(PHY_STAT_SPMASK | PHY_STAT_LINK | PHY_STAT_ANC);
1162 if (mii_reg & 0x0001) {
1164 *s |= PHY_STAT_LINK;
1167 /* Status of link */
1168 if (mii_reg & 0x0010) /* Autonegotioation complete */
1170 if (mii_reg & 0x0002) { /* 10MBps? */
1171 if (mii_reg & 0x0004) /* Full Duplex? */
1172 *s |= PHY_STAT_10FDX;
1174 *s |= PHY_STAT_10HDX;
1175 } else { /* 100 Mbps? */
1176 if (mii_reg & 0x0004) /* Full Duplex? */
1177 *s |= PHY_STAT_100FDX;
1179 *s |= PHY_STAT_100HDX;
1181 if (mii_reg & 0x0008)
1182 *s |= PHY_STAT_FAULT;
1185 static phy_info_t phy_info_dp83848= {
1189 (const phy_cmd_t []) { /* config */
1190 { mk_mii_read(MII_REG_CR), mii_parse_cr },
1191 { mk_mii_read(MII_REG_ANAR), mii_parse_anar },
1192 { mk_mii_read(MII_DP8384X_PHYSTST), mii_parse_dp8384x_sr2 },
1195 (const phy_cmd_t []) { /* startup - enable interrupts */
1196 { mk_mii_write(MII_REG_CR, 0x1200), NULL }, /* autonegotiate */
1197 { mk_mii_read(MII_REG_SR), mii_parse_sr },
1200 (const phy_cmd_t []) { /* ack_int - never happens, no interrupt */
1203 (const phy_cmd_t []) { /* shutdown */
1208 /* ------------------------------------------------------------------------- */
1210 static phy_info_t const * const phy_info[] = {
1220 /* ------------------------------------------------------------------------- */
1221 #if !defined(CONFIG_M532x)
1222 #ifdef CONFIG_RPXCLASSIC
1224 mii_link_interrupt(void *dev_id);
1227 mii_link_interrupt(int irq, void * dev_id, struct pt_regs * regs);
1231 #if defined(CONFIG_M5272)
1234 * Code specific to Coldfire 5272 setup.
1236 static void __inline__ fec_request_intrs(struct net_device *dev)
1238 volatile unsigned long *icrp;
1239 static const struct idesc {
1242 irqreturn_t (*handler)(int, void *, struct pt_regs *);
1244 { "fec(RX)", 86, fec_enet_interrupt },
1245 { "fec(TX)", 87, fec_enet_interrupt },
1246 { "fec(OTHER)", 88, fec_enet_interrupt },
1247 { "fec(MII)", 66, mii_link_interrupt },
1251 /* Setup interrupt handlers. */
1252 for (idp = id; idp->name; idp++) {
1253 if (request_irq(idp->irq, idp->handler, 0, idp->name, dev) != 0)
1254 printk("FEC: Could not allocate %s IRQ(%d)!\n", idp->name, idp->irq);
1257 /* Unmask interrupt at ColdFire 5272 SIM */
1258 icrp = (volatile unsigned long *) (MCF_MBAR + MCFSIM_ICR3);
1260 icrp = (volatile unsigned long *) (MCF_MBAR + MCFSIM_ICR1);
1261 *icrp = (*icrp & 0x70777777) | 0x0d000000;
1264 static void __inline__ fec_set_mii(struct net_device *dev, struct fec_enet_private *fep)
1266 volatile fec_t *fecp;
1269 fecp->fec_r_cntrl = OPT_FRAME_SIZE | 0x04;
1270 fecp->fec_x_cntrl = 0x00;
1273 * Set MII speed to 2.5 MHz
1274 * See 5272 manual section 11.5.8: MSCR
1276 fep->phy_speed = ((((MCF_CLK / 4) / (2500000 / 10)) + 5) / 10) * 2;
1277 fecp->fec_mii_speed = fep->phy_speed;
1279 fec_restart(dev, 0);
1282 static void __inline__ fec_get_mac(struct net_device *dev)
1284 struct fec_enet_private *fep = netdev_priv(dev);
1285 volatile fec_t *fecp;
1286 unsigned char *iap, tmpaddr[ETH_ALEN];
1292 * Get MAC address from FLASH.
1293 * If it is all 1's or 0's, use the default.
1295 iap = (unsigned char *)FEC_FLASHMAC;
1296 if ((iap[0] == 0) && (iap[1] == 0) && (iap[2] == 0) &&
1297 (iap[3] == 0) && (iap[4] == 0) && (iap[5] == 0))
1298 iap = fec_mac_default;
1299 if ((iap[0] == 0xff) && (iap[1] == 0xff) && (iap[2] == 0xff) &&
1300 (iap[3] == 0xff) && (iap[4] == 0xff) && (iap[5] == 0xff))
1301 iap = fec_mac_default;
1303 *((unsigned long *) &tmpaddr[0]) = fecp->fec_addr_low;
1304 *((unsigned short *) &tmpaddr[4]) = (fecp->fec_addr_high >> 16);
1308 memcpy(dev->dev_addr, iap, ETH_ALEN);
1310 /* Adjust MAC if using default MAC address */
1311 if (iap == fec_mac_default)
1312 dev->dev_addr[ETH_ALEN-1] = fec_mac_default[ETH_ALEN-1] + fep->index;
1315 static void __inline__ fec_enable_phy_intr(void)
1319 static void __inline__ fec_disable_phy_intr(void)
1321 volatile unsigned long *icrp;
1322 icrp = (volatile unsigned long *) (MCF_MBAR + MCFSIM_ICR1);
1323 *icrp = (*icrp & 0x70777777) | 0x08000000;
1326 static void __inline__ fec_phy_ack_intr(void)
1328 volatile unsigned long *icrp;
1329 /* Acknowledge the interrupt */
1330 icrp = (volatile unsigned long *) (MCF_MBAR + MCFSIM_ICR1);
1331 *icrp = (*icrp & 0x77777777) | 0x08000000;
1334 static void __inline__ fec_localhw_setup(void)
1339 * Do not need to make region uncached on 5272.
1341 static void __inline__ fec_uncache(unsigned long addr)
1345 /* ------------------------------------------------------------------------- */
1347 #elif defined(CONFIG_M523x) || defined(CONFIG_M527x) || defined(CONFIG_M528x)
1350 * Code specific to Coldfire 5230/5231/5232/5234/5235,
1351 * the 5270/5271/5274/5275 and 5280/5282 setups.
1353 static void __inline__ fec_request_intrs(struct net_device *dev)
1355 struct fec_enet_private *fep;
1357 static const struct idesc {
1363 { "fec(TXFIFO)", 25 },
1364 { "fec(TXCR)", 26 },
1369 { "fec(HBERR)", 31 },
1371 { "fec(EBERR)", 33 },
1372 { "fec(BABT)", 34 },
1373 { "fec(BABR)", 35 },
1377 fep = netdev_priv(dev);
1378 b = (fep->index) ? 128 : 64;
1380 /* Setup interrupt handlers. */
1381 for (idp = id; idp->name; idp++) {
1382 if (request_irq(b+idp->irq, fec_enet_interrupt, 0, idp->name, dev) != 0)
1383 printk("FEC: Could not allocate %s IRQ(%d)!\n", idp->name, b+idp->irq);
1386 /* Unmask interrupts at ColdFire 5280/5282 interrupt controller */
1388 volatile unsigned char *icrp;
1389 volatile unsigned long *imrp;
1392 b = (fep->index) ? MCFICM_INTC1 : MCFICM_INTC0;
1393 icrp = (volatile unsigned char *) (MCF_IPSBAR + b +
1395 for (i = 23; (i < 36); i++)
1398 imrp = (volatile unsigned long *) (MCF_IPSBAR + b +
1400 *imrp &= ~0x0000000f;
1401 imrp = (volatile unsigned long *) (MCF_IPSBAR + b +
1403 *imrp &= ~0xff800001;
1406 #if defined(CONFIG_M528x)
1407 /* Set up gpio outputs for MII lines */
1409 volatile u16 *gpio_paspar;
1410 volatile u8 *gpio_pehlpar;
1412 gpio_paspar = (volatile u16 *) (MCF_IPSBAR + 0x100056);
1413 gpio_pehlpar = (volatile u16 *) (MCF_IPSBAR + 0x100058);
1414 *gpio_paspar |= 0x0f00;
1415 *gpio_pehlpar = 0xc0;
1420 static void __inline__ fec_set_mii(struct net_device *dev, struct fec_enet_private *fep)
1422 volatile fec_t *fecp;
1425 fecp->fec_r_cntrl = OPT_FRAME_SIZE | 0x04;
1426 fecp->fec_x_cntrl = 0x00;
1429 * Set MII speed to 2.5 MHz
1430 * See 5282 manual section 17.5.4.7: MSCR
1432 fep->phy_speed = ((((MCF_CLK / 2) / (2500000 / 10)) + 5) / 10) * 2;
1433 fecp->fec_mii_speed = fep->phy_speed;
1435 fec_restart(dev, 0);
1438 static void __inline__ fec_get_mac(struct net_device *dev)
1440 struct fec_enet_private *fep = netdev_priv(dev);
1441 volatile fec_t *fecp;
1442 unsigned char *iap, tmpaddr[ETH_ALEN];
1448 * Get MAC address from FLASH.
1449 * If it is all 1's or 0's, use the default.
1452 if ((iap[0] == 0) && (iap[1] == 0) && (iap[2] == 0) &&
1453 (iap[3] == 0) && (iap[4] == 0) && (iap[5] == 0))
1454 iap = fec_mac_default;
1455 if ((iap[0] == 0xff) && (iap[1] == 0xff) && (iap[2] == 0xff) &&
1456 (iap[3] == 0xff) && (iap[4] == 0xff) && (iap[5] == 0xff))
1457 iap = fec_mac_default;
1459 *((unsigned long *) &tmpaddr[0]) = fecp->fec_addr_low;
1460 *((unsigned short *) &tmpaddr[4]) = (fecp->fec_addr_high >> 16);
1464 memcpy(dev->dev_addr, iap, ETH_ALEN);
1466 /* Adjust MAC if using default MAC address */
1467 if (iap == fec_mac_default)
1468 dev->dev_addr[ETH_ALEN-1] = fec_mac_default[ETH_ALEN-1] + fep->index;
1471 static void __inline__ fec_enable_phy_intr(void)
1475 static void __inline__ fec_disable_phy_intr(void)
1479 static void __inline__ fec_phy_ack_intr(void)
1483 static void __inline__ fec_localhw_setup(void)
1488 * Do not need to make region uncached on 5272.
1490 static void __inline__ fec_uncache(unsigned long addr)
1494 /* ------------------------------------------------------------------------- */
1496 #elif defined(CONFIG_M520x)
1499 * Code specific to Coldfire 520x
1501 static void __inline__ fec_request_intrs(struct net_device *dev)
1503 struct fec_enet_private *fep;
1505 static const struct idesc {
1511 { "fec(TXFIFO)", 25 },
1512 { "fec(TXCR)", 26 },
1517 { "fec(HBERR)", 31 },
1519 { "fec(EBERR)", 33 },
1520 { "fec(BABT)", 34 },
1521 { "fec(BABR)", 35 },
1525 fep = netdev_priv(dev);
1528 /* Setup interrupt handlers. */
1529 for (idp = id; idp->name; idp++) {
1530 if (request_irq(b+idp->irq,fec_enet_interrupt,0,idp->name,dev)!=0)
1531 printk("FEC: Could not allocate %s IRQ(%d)!\n", idp->name, b+idp->irq);
1534 /* Unmask interrupts at ColdFire interrupt controller */
1536 volatile unsigned char *icrp;
1537 volatile unsigned long *imrp;
1539 icrp = (volatile unsigned char *) (MCF_IPSBAR + MCFICM_INTC0 +
1541 for (b = 36; (b < 49); b++)
1543 imrp = (volatile unsigned long *) (MCF_IPSBAR + MCFICM_INTC0 +
1545 *imrp &= ~0x0001FFF0;
1547 *(volatile unsigned char *)(MCF_IPSBAR + MCF_GPIO_PAR_FEC) |= 0xf0;
1548 *(volatile unsigned char *)(MCF_IPSBAR + MCF_GPIO_PAR_FECI2C) |= 0x0f;
1551 static void __inline__ fec_set_mii(struct net_device *dev, struct fec_enet_private *fep)
1553 volatile fec_t *fecp;
1556 fecp->fec_r_cntrl = OPT_FRAME_SIZE | 0x04;
1557 fecp->fec_x_cntrl = 0x00;
1560 * Set MII speed to 2.5 MHz
1561 * See 5282 manual section 17.5.4.7: MSCR
1563 fep->phy_speed = ((((MCF_CLK / 2) / (2500000 / 10)) + 5) / 10) * 2;
1564 fecp->fec_mii_speed = fep->phy_speed;
1566 fec_restart(dev, 0);
1569 static void __inline__ fec_get_mac(struct net_device *dev)
1571 struct fec_enet_private *fep = netdev_priv(dev);
1572 volatile fec_t *fecp;
1573 unsigned char *iap, tmpaddr[ETH_ALEN];
1579 * Get MAC address from FLASH.
1580 * If it is all 1's or 0's, use the default.
1583 if ((iap[0] == 0) && (iap[1] == 0) && (iap[2] == 0) &&
1584 (iap[3] == 0) && (iap[4] == 0) && (iap[5] == 0))
1585 iap = fec_mac_default;
1586 if ((iap[0] == 0xff) && (iap[1] == 0xff) && (iap[2] == 0xff) &&
1587 (iap[3] == 0xff) && (iap[4] == 0xff) && (iap[5] == 0xff))
1588 iap = fec_mac_default;
1590 *((unsigned long *) &tmpaddr[0]) = fecp->fec_addr_low;
1591 *((unsigned short *) &tmpaddr[4]) = (fecp->fec_addr_high >> 16);
1595 memcpy(dev->dev_addr, iap, ETH_ALEN);
1597 /* Adjust MAC if using default MAC address */
1598 if (iap == fec_mac_default)
1599 dev->dev_addr[ETH_ALEN-1] = fec_mac_default[ETH_ALEN-1] + fep->index;
1602 static void __inline__ fec_enable_phy_intr(void)
1606 static void __inline__ fec_disable_phy_intr(void)
1610 static void __inline__ fec_phy_ack_intr(void)
1614 static void __inline__ fec_localhw_setup(void)
1618 static void __inline__ fec_uncache(unsigned long addr)
1622 /* ------------------------------------------------------------------------- */
1624 #elif defined(CONFIG_M532x)
1626 * Code specific for M532x
1628 static void __inline__ fec_request_intrs(struct net_device *dev)
1630 struct fec_enet_private *fep;
1632 static const struct idesc {
1638 { "fec(TXFIFO)", 38 },
1639 { "fec(TXCR)", 39 },
1644 { "fec(HBERR)", 44 },
1646 { "fec(EBERR)", 46 },
1647 { "fec(BABT)", 47 },
1648 { "fec(BABR)", 48 },
1652 fep = netdev_priv(dev);
1653 b = (fep->index) ? 128 : 64;
1655 /* Setup interrupt handlers. */
1656 for (idp = id; idp->name; idp++) {
1657 if (request_irq(b+idp->irq,fec_enet_interrupt,0,idp->name,dev)!=0)
1658 printk("FEC: Could not allocate %s IRQ(%d)!\n",
1659 idp->name, b+idp->irq);
1662 /* Unmask interrupts */
1663 MCF_INTC0_ICR36 = 0x2;
1664 MCF_INTC0_ICR37 = 0x2;
1665 MCF_INTC0_ICR38 = 0x2;
1666 MCF_INTC0_ICR39 = 0x2;
1667 MCF_INTC0_ICR40 = 0x2;
1668 MCF_INTC0_ICR41 = 0x2;
1669 MCF_INTC0_ICR42 = 0x2;
1670 MCF_INTC0_ICR43 = 0x2;
1671 MCF_INTC0_ICR44 = 0x2;
1672 MCF_INTC0_ICR45 = 0x2;
1673 MCF_INTC0_ICR46 = 0x2;
1674 MCF_INTC0_ICR47 = 0x2;
1675 MCF_INTC0_ICR48 = 0x2;
1677 MCF_INTC0_IMRH &= ~(
1678 MCF_INTC_IMRH_INT_MASK36 |
1679 MCF_INTC_IMRH_INT_MASK37 |
1680 MCF_INTC_IMRH_INT_MASK38 |
1681 MCF_INTC_IMRH_INT_MASK39 |
1682 MCF_INTC_IMRH_INT_MASK40 |
1683 MCF_INTC_IMRH_INT_MASK41 |
1684 MCF_INTC_IMRH_INT_MASK42 |
1685 MCF_INTC_IMRH_INT_MASK43 |
1686 MCF_INTC_IMRH_INT_MASK44 |
1687 MCF_INTC_IMRH_INT_MASK45 |
1688 MCF_INTC_IMRH_INT_MASK46 |
1689 MCF_INTC_IMRH_INT_MASK47 |
1690 MCF_INTC_IMRH_INT_MASK48 );
1692 /* Set up gpio outputs for MII lines */
1693 MCF_GPIO_PAR_FECI2C |= (0 |
1694 MCF_GPIO_PAR_FECI2C_PAR_MDC_EMDC |
1695 MCF_GPIO_PAR_FECI2C_PAR_MDIO_EMDIO);
1696 MCF_GPIO_PAR_FEC = (0 |
1697 MCF_GPIO_PAR_FEC_PAR_FEC_7W_FEC |
1698 MCF_GPIO_PAR_FEC_PAR_FEC_MII_FEC);
1701 static void __inline__ fec_set_mii(struct net_device *dev, struct fec_enet_private *fep)
1703 volatile fec_t *fecp;
1706 fecp->fec_r_cntrl = OPT_FRAME_SIZE | 0x04;
1707 fecp->fec_x_cntrl = 0x00;
1710 * Set MII speed to 2.5 MHz
1712 fep->phy_speed = ((((MCF_CLK / 2) / (2500000 / 10)) + 5) / 10) * 2;
1713 fecp->fec_mii_speed = fep->phy_speed;
1715 fec_restart(dev, 0);
1718 static void __inline__ fec_get_mac(struct net_device *dev)
1720 struct fec_enet_private *fep = netdev_priv(dev);
1721 volatile fec_t *fecp;
1722 unsigned char *iap, tmpaddr[ETH_ALEN];
1728 * Get MAC address from FLASH.
1729 * If it is all 1's or 0's, use the default.
1732 if ((iap[0] == 0) && (iap[1] == 0) && (iap[2] == 0) &&
1733 (iap[3] == 0) && (iap[4] == 0) && (iap[5] == 0))
1734 iap = fec_mac_default;
1735 if ((iap[0] == 0xff) && (iap[1] == 0xff) && (iap[2] == 0xff) &&
1736 (iap[3] == 0xff) && (iap[4] == 0xff) && (iap[5] == 0xff))
1737 iap = fec_mac_default;
1739 *((unsigned long *) &tmpaddr[0]) = fecp->fec_addr_low;
1740 *((unsigned short *) &tmpaddr[4]) = (fecp->fec_addr_high >> 16);
1744 memcpy(dev->dev_addr, iap, ETH_ALEN);
1746 /* Adjust MAC if using default MAC address */
1747 if (iap == fec_mac_default)
1748 dev->dev_addr[ETH_ALEN-1] = fec_mac_default[ETH_ALEN-1] + fep->index;
1751 static void __inline__ fec_enable_phy_intr(void)
1755 static void __inline__ fec_disable_phy_intr(void)
1759 static void __inline__ fec_phy_ack_intr(void)
1763 static void __inline__ fec_localhw_setup(void)
1768 * Do not need to make region uncached on 532x.
1770 static void __inline__ fec_uncache(unsigned long addr)
1774 /* ------------------------------------------------------------------------- */
1780 * Code specific to the MPC860T setup.
1782 static void __inline__ fec_request_intrs(struct net_device *dev)
1784 volatile immap_t *immap;
1786 immap = (immap_t *)IMAP_ADDR; /* pointer to internal registers */
1788 if (request_8xxirq(FEC_INTERRUPT, fec_enet_interrupt, 0, "fec", dev) != 0)
1789 panic("Could not allocate FEC IRQ!");
1791 #ifdef CONFIG_RPXCLASSIC
1792 /* Make Port C, bit 15 an input that causes interrupts.
1794 immap->im_ioport.iop_pcpar &= ~0x0001;
1795 immap->im_ioport.iop_pcdir &= ~0x0001;
1796 immap->im_ioport.iop_pcso &= ~0x0001;
1797 immap->im_ioport.iop_pcint |= 0x0001;
1798 cpm_install_handler(CPMVEC_PIO_PC15, mii_link_interrupt, dev);
1800 /* Make LEDS reflect Link status.
1802 *((uint *) RPX_CSR_ADDR) &= ~BCSR2_FETHLEDMODE;
1805 if (request_8xxirq(SIU_IRQ2, mii_link_interrupt, 0, "mii", dev) != 0)
1806 panic("Could not allocate MII IRQ!");
1810 static void __inline__ fec_get_mac(struct net_device *dev)
1815 memcpy(dev->dev_addr, bd->bi_enetaddr, ETH_ALEN);
1817 #ifdef CONFIG_RPXCLASSIC
1818 /* The Embedded Planet boards have only one MAC address in
1819 * the EEPROM, but can have two Ethernet ports. For the
1820 * FEC port, we create another address by setting one of
1821 * the address bits above something that would have (up to
1822 * now) been allocated.
1824 dev->dev_adrd[3] |= 0x80;
1828 static void __inline__ fec_set_mii(struct net_device *dev, struct fec_enet_private *fep)
1830 extern uint _get_IMMR(void);
1831 volatile immap_t *immap;
1832 volatile fec_t *fecp;
1835 immap = (immap_t *)IMAP_ADDR; /* pointer to internal registers */
1837 /* Configure all of port D for MII.
1839 immap->im_ioport.iop_pdpar = 0x1fff;
1841 /* Bits moved from Rev. D onward.
1843 if ((_get_IMMR() & 0xffff) < 0x0501)
1844 immap->im_ioport.iop_pddir = 0x1c58; /* Pre rev. D */
1846 immap->im_ioport.iop_pddir = 0x1fff; /* Rev. D and later */
1848 /* Set MII speed to 2.5 MHz
1850 fecp->fec_mii_speed = fep->phy_speed =
1851 ((bd->bi_busfreq * 1000000) / 2500000) & 0x7e;
1854 static void __inline__ fec_enable_phy_intr(void)
1856 volatile fec_t *fecp;
1860 /* Enable MII command finished interrupt
1862 fecp->fec_ivec = (FEC_INTERRUPT/2) << 29;
1865 static void __inline__ fec_disable_phy_intr(void)
1869 static void __inline__ fec_phy_ack_intr(void)
1873 static void __inline__ fec_localhw_setup(void)
1875 volatile fec_t *fecp;
1878 fecp->fec_r_hash = PKT_MAXBUF_SIZE;
1879 /* Enable big endian and don't care about SDMA FC.
1881 fecp->fec_fun_code = 0x78000000;
1884 static void __inline__ fec_uncache(unsigned long addr)
1887 pte = va_to_pte(mem_addr);
1888 pte_val(*pte) |= _PAGE_NO_CACHE;
1889 flush_tlb_page(init_mm.mmap, mem_addr);
1894 /* ------------------------------------------------------------------------- */
1896 static void mii_display_status(struct net_device *dev)
1898 struct fec_enet_private *fep = netdev_priv(dev);
1899 volatile uint *s = &(fep->phy_status);
1901 if (!fep->link && !fep->old_link) {
1902 /* Link is still down - don't print anything */
1906 printk("%s: status: ", dev->name);
1909 printk("link down");
1913 switch(*s & PHY_STAT_SPMASK) {
1914 case PHY_STAT_100FDX: printk(", 100MBit Full Duplex"); break;
1915 case PHY_STAT_100HDX: printk(", 100MBit Half Duplex"); break;
1916 case PHY_STAT_10FDX: printk(", 10MBit Full Duplex"); break;
1917 case PHY_STAT_10HDX: printk(", 10MBit Half Duplex"); break;
1919 printk(", Unknown speed/duplex");
1922 if (*s & PHY_STAT_ANC)
1923 printk(", auto-negotiation complete");
1926 if (*s & PHY_STAT_FAULT)
1927 printk(", remote fault");
1932 static void mii_display_config(struct net_device *dev)
1934 struct fec_enet_private *fep = netdev_priv(dev);
1935 uint status = fep->phy_status;
1938 ** When we get here, phy_task is already removed from
1939 ** the workqueue. It is thus safe to allow to reuse it.
1941 fep->mii_phy_task_queued = 0;
1942 printk("%s: config: auto-negotiation ", dev->name);
1944 if (status & PHY_CONF_ANE)
1949 if (status & PHY_CONF_100FDX)
1951 if (status & PHY_CONF_100HDX)
1953 if (status & PHY_CONF_10FDX)
1955 if (status & PHY_CONF_10HDX)
1957 if (!(status & PHY_CONF_SPMASK))
1958 printk(", No speed/duplex selected?");
1960 if (status & PHY_CONF_LOOP)
1961 printk(", loopback enabled");
1965 fep->sequence_done = 1;
1968 static void mii_relink(struct net_device *dev)
1970 struct fec_enet_private *fep = netdev_priv(dev);
1974 ** When we get here, phy_task is already removed from
1975 ** the workqueue. It is thus safe to allow to reuse it.
1977 fep->mii_phy_task_queued = 0;
1978 fep->link = (fep->phy_status & PHY_STAT_LINK) ? 1 : 0;
1979 mii_display_status(dev);
1980 fep->old_link = fep->link;
1985 & (PHY_STAT_100FDX | PHY_STAT_10FDX))
1987 fec_restart(dev, duplex);
1993 enable_irq(fep->mii_irq);
1998 /* mii_queue_relink is called in interrupt context from mii_link_interrupt */
1999 static void mii_queue_relink(uint mii_reg, struct net_device *dev)
2001 struct fec_enet_private *fep = netdev_priv(dev);
2004 ** We cannot queue phy_task twice in the workqueue. It
2005 ** would cause an endless loop in the workqueue.
2006 ** Fortunately, if the last mii_relink entry has not yet been
2007 ** executed now, it will do the job for the current interrupt,
2008 ** which is just what we want.
2010 if (fep->mii_phy_task_queued)
2013 fep->mii_phy_task_queued = 1;
2014 INIT_WORK(&fep->phy_task, (void*)mii_relink, dev);
2015 schedule_work(&fep->phy_task);
2018 /* mii_queue_config is called in interrupt context from fec_enet_mii */
2019 static void mii_queue_config(uint mii_reg, struct net_device *dev)
2021 struct fec_enet_private *fep = netdev_priv(dev);
2023 if (fep->mii_phy_task_queued)
2026 fep->mii_phy_task_queued = 1;
2027 INIT_WORK(&fep->phy_task, (void*)mii_display_config, dev);
2028 schedule_work(&fep->phy_task);
2031 phy_cmd_t const phy_cmd_relink[] = {
2032 { mk_mii_read(MII_REG_CR), mii_queue_relink },
2035 phy_cmd_t const phy_cmd_config[] = {
2036 { mk_mii_read(MII_REG_CR), mii_queue_config },
2040 /* Read remainder of PHY ID.
2043 mii_discover_phy3(uint mii_reg, struct net_device *dev)
2045 struct fec_enet_private *fep;
2048 fep = netdev_priv(dev);
2049 fep->phy_id |= (mii_reg & 0xffff);
2050 printk("fec: PHY @ 0x%x, ID 0x%08x", fep->phy_addr, fep->phy_id);
2052 for(i = 0; phy_info[i]; i++) {
2053 if(phy_info[i]->id == (fep->phy_id >> 4))
2058 printk(" -- %s\n", phy_info[i]->name);
2060 printk(" -- unknown PHY!\n");
2062 fep->phy = phy_info[i];
2063 fep->phy_id_done = 1;
2066 /* Scan all of the MII PHY addresses looking for someone to respond
2067 * with a valid ID. This usually happens quickly.
2070 mii_discover_phy(uint mii_reg, struct net_device *dev)
2072 struct fec_enet_private *fep;
2073 volatile fec_t *fecp;
2076 fep = netdev_priv(dev);
2079 if (fep->phy_addr < 32) {
2080 if ((phytype = (mii_reg & 0xffff)) != 0xffff && phytype != 0) {
2082 /* Got first part of ID, now get remainder.
2084 fep->phy_id = phytype << 16;
2085 mii_queue(dev, mk_mii_read(MII_REG_PHYIR2),
2090 mii_queue(dev, mk_mii_read(MII_REG_PHYIR1),
2094 printk("FEC: No PHY device found.\n");
2095 /* Disable external MII interface */
2096 fecp->fec_mii_speed = fep->phy_speed = 0;
2097 fec_disable_phy_intr();
2101 /* This interrupt occurs when the PHY detects a link change.
2103 #ifdef CONFIG_RPXCLASSIC
2105 mii_link_interrupt(void *dev_id)
2108 mii_link_interrupt(int irq, void * dev_id, struct pt_regs * regs)
2111 struct net_device *dev = dev_id;
2112 struct fec_enet_private *fep = netdev_priv(dev);
2117 disable_irq(fep->mii_irq); /* disable now, enable later */
2120 mii_do_cmd(dev, fep->phy->ack_int);
2121 mii_do_cmd(dev, phy_cmd_relink); /* restart and display status */
2127 fec_enet_open(struct net_device *dev)
2129 struct fec_enet_private *fep = netdev_priv(dev);
2131 /* I should reset the ring buffers here, but I don't yet know
2132 * a simple way to do that.
2134 fec_set_mac_address(dev);
2136 fep->sequence_done = 0;
2140 mii_do_cmd(dev, fep->phy->ack_int);
2141 mii_do_cmd(dev, fep->phy->config);
2142 mii_do_cmd(dev, phy_cmd_config); /* display configuration */
2144 /* Poll until the PHY tells us its configuration
2146 * Request is initiated by mii_do_cmd above, but answer
2147 * comes by interrupt.
2148 * This should take about 25 usec per register at 2.5 MHz,
2149 * and we read approximately 5 registers.
2151 while(!fep->sequence_done)
2154 mii_do_cmd(dev, fep->phy->startup);
2156 /* Set the initial link state to true. A lot of hardware
2157 * based on this device does not implement a PHY interrupt,
2158 * so we are never notified of link change.
2162 fep->link = 1; /* lets just try it and see */
2163 /* no phy, go full duplex, it's most likely a hub chip */
2164 fec_restart(dev, 1);
2167 netif_start_queue(dev);
2169 return 0; /* Success */
2173 fec_enet_close(struct net_device *dev)
2175 struct fec_enet_private *fep = netdev_priv(dev);
2177 /* Don't know what to do yet.
2180 netif_stop_queue(dev);
2186 static struct net_device_stats *fec_enet_get_stats(struct net_device *dev)
2188 struct fec_enet_private *fep = netdev_priv(dev);
2193 /* Set or clear the multicast filter for this adaptor.
2194 * Skeleton taken from sunlance driver.
2195 * The CPM Ethernet implementation allows Multicast as well as individual
2196 * MAC address filtering. Some of the drivers check to make sure it is
2197 * a group multicast address, and discard those that are not. I guess I
2198 * will do the same for now, but just remove the test if you want
2199 * individual filtering as well (do the upper net layers want or support
2200 * this kind of feature?).
2203 #define HASH_BITS 6 /* #bits in hash */
2204 #define CRC32_POLY 0xEDB88320
2206 static void set_multicast_list(struct net_device *dev)
2208 struct fec_enet_private *fep;
2210 struct dev_mc_list *dmi;
2211 unsigned int i, j, bit, data, crc;
2214 fep = netdev_priv(dev);
2217 if (dev->flags&IFF_PROMISC) {
2218 /* Log any net taps. */
2219 printk("%s: Promiscuous mode enabled.\n", dev->name);
2220 ep->fec_r_cntrl |= 0x0008;
2223 ep->fec_r_cntrl &= ~0x0008;
2225 if (dev->flags & IFF_ALLMULTI) {
2226 /* Catch all multicast addresses, so set the
2227 * filter to all 1's.
2229 ep->fec_hash_table_high = 0xffffffff;
2230 ep->fec_hash_table_low = 0xffffffff;
2232 /* Clear filter and add the addresses in hash register.
2234 ep->fec_hash_table_high = 0;
2235 ep->fec_hash_table_low = 0;
2239 for (j = 0; j < dev->mc_count; j++, dmi = dmi->next)
2241 /* Only support group multicast for now.
2243 if (!(dmi->dmi_addr[0] & 1))
2246 /* calculate crc32 value of mac address
2250 for (i = 0; i < dmi->dmi_addrlen; i++)
2252 data = dmi->dmi_addr[i];
2253 for (bit = 0; bit < 8; bit++, data >>= 1)
2256 (((crc ^ data) & 1) ? CRC32_POLY : 0);
2260 /* only upper 6 bits (HASH_BITS) are used
2261 which point to specific bit in he hash registers
2263 hash = (crc >> (32 - HASH_BITS)) & 0x3f;
2266 ep->fec_hash_table_high |= 1 << (hash - 32);
2268 ep->fec_hash_table_low |= 1 << hash;
2274 /* Set a MAC change in hardware.
2277 fec_set_mac_address(struct net_device *dev)
2279 volatile fec_t *fecp;
2281 fecp = ((struct fec_enet_private *)netdev_priv(dev))->hwp;
2283 /* Set station address. */
2284 fecp->fec_addr_low = dev->dev_addr[3] | (dev->dev_addr[2] << 8) |
2285 (dev->dev_addr[1] << 16) | (dev->dev_addr[0] << 24);
2286 fecp->fec_addr_high = (dev->dev_addr[5] << 16) |
2287 (dev->dev_addr[4] << 24);
2291 /* Initialize the FEC Ethernet on 860T (or ColdFire 5272).
2294 * XXX: We need to clean up on failure exits here.
2296 int __init fec_enet_init(struct net_device *dev)
2298 struct fec_enet_private *fep = netdev_priv(dev);
2299 unsigned long mem_addr;
2300 volatile cbd_t *bdp;
2302 volatile fec_t *fecp;
2304 static int index = 0;
2306 /* Only allow us to be probed once. */
2307 if (index >= FEC_MAX_PORTS)
2310 /* Allocate memory for buffer descriptors.
2312 mem_addr = __get_free_page(GFP_KERNEL);
2313 if (mem_addr == 0) {
2314 printk("FEC: allocate descriptor memory failed?\n");
2318 /* Create an Ethernet device instance.
2320 fecp = (volatile fec_t *) fec_hw[index];
2325 /* Whack a reset. We should wait for this.
2327 fecp->fec_ecntrl = 1;
2330 /* Set the Ethernet address. If using multiple Enets on the 8xx,
2331 * this needs some work to get unique addresses.
2333 * This is our default MAC address unless the user changes
2334 * it via eth_mac_addr (our dev->set_mac_addr handler).
2338 cbd_base = (cbd_t *)mem_addr;
2339 /* XXX: missing check for allocation failure */
2341 fec_uncache(mem_addr);
2343 /* Set receive and transmit descriptor base.
2345 fep->rx_bd_base = cbd_base;
2346 fep->tx_bd_base = cbd_base + RX_RING_SIZE;
2348 fep->dirty_tx = fep->cur_tx = fep->tx_bd_base;
2349 fep->cur_rx = fep->rx_bd_base;
2351 fep->skb_cur = fep->skb_dirty = 0;
2353 /* Initialize the receive buffer descriptors.
2355 bdp = fep->rx_bd_base;
2356 for (i=0; i<FEC_ENET_RX_PAGES; i++) {
2360 mem_addr = __get_free_page(GFP_KERNEL);
2361 /* XXX: missing check for allocation failure */
2363 fec_uncache(mem_addr);
2365 /* Initialize the BD for every fragment in the page.
2367 for (j=0; j<FEC_ENET_RX_FRPPG; j++) {
2368 bdp->cbd_sc = BD_ENET_RX_EMPTY;
2369 bdp->cbd_bufaddr = __pa(mem_addr);
2370 mem_addr += FEC_ENET_RX_FRSIZE;
2375 /* Set the last buffer to wrap.
2378 bdp->cbd_sc |= BD_SC_WRAP;
2380 /* ...and the same for transmmit.
2382 bdp = fep->tx_bd_base;
2383 for (i=0, j=FEC_ENET_TX_FRPPG; i<TX_RING_SIZE; i++) {
2384 if (j >= FEC_ENET_TX_FRPPG) {
2385 mem_addr = __get_free_page(GFP_KERNEL);
2388 mem_addr += FEC_ENET_TX_FRSIZE;
2391 fep->tx_bounce[i] = (unsigned char *) mem_addr;
2393 /* Initialize the BD for every fragment in the page.
2396 bdp->cbd_bufaddr = 0;
2400 /* Set the last buffer to wrap.
2403 bdp->cbd_sc |= BD_SC_WRAP;
2405 /* Set receive and transmit descriptor base.
2407 fecp->fec_r_des_start = __pa((uint)(fep->rx_bd_base));
2408 fecp->fec_x_des_start = __pa((uint)(fep->tx_bd_base));
2410 /* Install our interrupt handlers. This varies depending on
2413 fec_request_intrs(dev);
2415 fecp->fec_hash_table_high = 0;
2416 fecp->fec_hash_table_low = 0;
2417 fecp->fec_r_buff_size = PKT_MAXBLR_SIZE;
2418 fecp->fec_ecntrl = 2;
2419 fecp->fec_r_des_active = 0;
2421 dev->base_addr = (unsigned long)fecp;
2423 /* The FEC Ethernet specific entries in the device structure. */
2424 dev->open = fec_enet_open;
2425 dev->hard_start_xmit = fec_enet_start_xmit;
2426 dev->tx_timeout = fec_timeout;
2427 dev->watchdog_timeo = TX_TIMEOUT;
2428 dev->stop = fec_enet_close;
2429 dev->get_stats = fec_enet_get_stats;
2430 dev->set_multicast_list = set_multicast_list;
2432 for (i=0; i<NMII-1; i++)
2433 mii_cmds[i].mii_next = &mii_cmds[i+1];
2434 mii_free = mii_cmds;
2436 /* setup MII interface */
2437 fec_set_mii(dev, fep);
2439 /* Clear and enable interrupts */
2440 fecp->fec_ievent = 0xffc00000;
2441 fecp->fec_imask = (FEC_ENET_TXF | FEC_ENET_TXB |
2442 FEC_ENET_RXF | FEC_ENET_RXB | FEC_ENET_MII);
2444 /* Queue up command to detect the PHY and initialize the
2445 * remainder of the interface.
2447 fep->phy_id_done = 0;
2449 mii_queue(dev, mk_mii_read(MII_REG_PHYIR1), mii_discover_phy);
2455 /* This function is called to start or restart the FEC during a link
2456 * change. This only happens when switching between half and full
2460 fec_restart(struct net_device *dev, int duplex)
2462 struct fec_enet_private *fep;
2463 volatile cbd_t *bdp;
2464 volatile fec_t *fecp;
2467 fep = netdev_priv(dev);
2470 /* Whack a reset. We should wait for this.
2472 fecp->fec_ecntrl = 1;
2475 /* Clear any outstanding interrupt.
2477 fecp->fec_ievent = 0xffc00000;
2478 fec_enable_phy_intr();
2480 /* Set station address.
2482 fec_set_mac_address(dev);
2484 /* Reset all multicast.
2486 fecp->fec_hash_table_high = 0;
2487 fecp->fec_hash_table_low = 0;
2489 /* Set maximum receive buffer size.
2491 fecp->fec_r_buff_size = PKT_MAXBLR_SIZE;
2493 fec_localhw_setup();
2495 /* Set receive and transmit descriptor base.
2497 fecp->fec_r_des_start = __pa((uint)(fep->rx_bd_base));
2498 fecp->fec_x_des_start = __pa((uint)(fep->tx_bd_base));
2500 fep->dirty_tx = fep->cur_tx = fep->tx_bd_base;
2501 fep->cur_rx = fep->rx_bd_base;
2503 /* Reset SKB transmit buffers.
2505 fep->skb_cur = fep->skb_dirty = 0;
2506 for (i=0; i<=TX_RING_MOD_MASK; i++) {
2507 if (fep->tx_skbuff[i] != NULL) {
2508 dev_kfree_skb_any(fep->tx_skbuff[i]);
2509 fep->tx_skbuff[i] = NULL;
2513 /* Initialize the receive buffer descriptors.
2515 bdp = fep->rx_bd_base;
2516 for (i=0; i<RX_RING_SIZE; i++) {
2518 /* Initialize the BD for every fragment in the page.
2520 bdp->cbd_sc = BD_ENET_RX_EMPTY;
2524 /* Set the last buffer to wrap.
2527 bdp->cbd_sc |= BD_SC_WRAP;
2529 /* ...and the same for transmmit.
2531 bdp = fep->tx_bd_base;
2532 for (i=0; i<TX_RING_SIZE; i++) {
2534 /* Initialize the BD for every fragment in the page.
2537 bdp->cbd_bufaddr = 0;
2541 /* Set the last buffer to wrap.
2544 bdp->cbd_sc |= BD_SC_WRAP;
2549 fecp->fec_r_cntrl = OPT_FRAME_SIZE | 0x04;/* MII enable */
2550 fecp->fec_x_cntrl = 0x04; /* FD enable */
2553 /* MII enable|No Rcv on Xmit */
2554 fecp->fec_r_cntrl = OPT_FRAME_SIZE | 0x06;
2555 fecp->fec_x_cntrl = 0x00;
2557 fep->full_duplex = duplex;
2561 fecp->fec_mii_speed = fep->phy_speed;
2563 /* And last, enable the transmit and receive processing.
2565 fecp->fec_ecntrl = 2;
2566 fecp->fec_r_des_active = 0;
2568 /* Enable interrupts we wish to service.
2570 fecp->fec_imask = (FEC_ENET_TXF | FEC_ENET_TXB |
2571 FEC_ENET_RXF | FEC_ENET_RXB | FEC_ENET_MII);
2575 fec_stop(struct net_device *dev)
2577 volatile fec_t *fecp;
2578 struct fec_enet_private *fep;
2580 fep = netdev_priv(dev);
2584 ** We cannot expect a graceful transmit stop without link !!!
2588 fecp->fec_x_cntrl = 0x01; /* Graceful transmit stop */
2590 if (!(fecp->fec_ievent & FEC_ENET_GRA))
2591 printk("fec_stop : Graceful transmit stop did not complete !\n");
2594 /* Whack a reset. We should wait for this.
2596 fecp->fec_ecntrl = 1;
2599 /* Clear outstanding MII command interrupts.
2601 fecp->fec_ievent = FEC_ENET_MII;
2602 fec_enable_phy_intr();
2604 fecp->fec_imask = FEC_ENET_MII;
2605 fecp->fec_mii_speed = fep->phy_speed;
2608 static int __init fec_enet_module_init(void)
2610 struct net_device *dev;
2613 printk("FEC ENET Version 0.2\n");
2615 for (i = 0; (i < FEC_MAX_PORTS); i++) {
2616 dev = alloc_etherdev(sizeof(struct fec_enet_private));
2619 err = fec_enet_init(dev);
2624 if (register_netdev(dev) != 0) {
2625 /* XXX: missing cleanup here */
2630 printk("%s: ethernet ", dev->name);
2631 for (j = 0; (j < 5); j++)
2632 printk("%02x:", dev->dev_addr[j]);
2633 printk("%02x\n", dev->dev_addr[5]);
2638 module_init(fec_enet_module_init);
2640 MODULE_LICENSE("GPL");