1 /*******************************************************************************
3 Intel PRO/1000 Linux driver
4 Copyright(c) 1999 - 2008 Intel Corporation.
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
23 Linux NICS <linux.nics@intel.com>
24 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
25 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
27 *******************************************************************************/
29 #include <linux/netdevice.h>
30 #include <linux/ethtool.h>
31 #include <linux/delay.h>
32 #include <linux/pci.h>
37 e1000_mng_mode_none = 0,
41 e1000_mng_mode_host_if_only
44 #define E1000_FACTPS_MNGCG 0x20000000
46 /* Intel(R) Active Management Technology signature */
47 #define E1000_IAMT_SIGNATURE 0x544D4149
50 * e1000e_get_bus_info_pcie - Get PCIe bus information
51 * @hw: pointer to the HW structure
53 * Determines and stores the system bus information for a particular
54 * network interface. The following bus information is determined and stored:
55 * bus speed, bus width, type (PCIe), and PCIe function.
57 s32 e1000e_get_bus_info_pcie(struct e1000_hw *hw)
59 struct e1000_bus_info *bus = &hw->bus;
60 struct e1000_adapter *adapter = hw->adapter;
62 u16 pcie_link_status, pci_header_type, cap_offset;
64 cap_offset = pci_find_capability(adapter->pdev, PCI_CAP_ID_EXP);
66 bus->width = e1000_bus_width_unknown;
68 pci_read_config_word(adapter->pdev,
69 cap_offset + PCIE_LINK_STATUS,
71 bus->width = (enum e1000_bus_width)((pcie_link_status &
72 PCIE_LINK_WIDTH_MASK) >>
73 PCIE_LINK_WIDTH_SHIFT);
76 pci_read_config_word(adapter->pdev, PCI_HEADER_TYPE_REGISTER,
78 if (pci_header_type & PCI_HEADER_TYPE_MULTIFUNC) {
79 status = er32(STATUS);
80 bus->func = (status & E1000_STATUS_FUNC_MASK)
81 >> E1000_STATUS_FUNC_SHIFT;
90 * e1000e_write_vfta - Write value to VLAN filter table
91 * @hw: pointer to the HW structure
92 * @offset: register offset in VLAN filter table
93 * @value: register value written to VLAN filter table
95 * Writes value at the given offset in the register array which stores
96 * the VLAN filter table.
98 void e1000e_write_vfta(struct e1000_hw *hw, u32 offset, u32 value)
100 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, offset, value);
105 * e1000e_init_rx_addrs - Initialize receive address's
106 * @hw: pointer to the HW structure
107 * @rar_count: receive address registers
109 * Setups the receive address registers by setting the base receive address
110 * register to the devices MAC address and clearing all the other receive
111 * address registers to 0.
113 void e1000e_init_rx_addrs(struct e1000_hw *hw, u16 rar_count)
117 /* Setup the receive address */
118 hw_dbg(hw, "Programming MAC Address into RAR[0]\n");
120 e1000e_rar_set(hw, hw->mac.addr, 0);
122 /* Zero out the other (rar_entry_count - 1) receive addresses */
123 hw_dbg(hw, "Clearing RAR[1-%u]\n", rar_count-1);
124 for (i = 1; i < rar_count; i++) {
125 E1000_WRITE_REG_ARRAY(hw, E1000_RA, (i << 1), 0);
127 E1000_WRITE_REG_ARRAY(hw, E1000_RA, ((i << 1) + 1), 0);
133 * e1000e_rar_set - Set receive address register
134 * @hw: pointer to the HW structure
135 * @addr: pointer to the receive address
136 * @index: receive address array register
138 * Sets the receive address array register at index to the address passed
141 void e1000e_rar_set(struct e1000_hw *hw, u8 *addr, u32 index)
143 u32 rar_low, rar_high;
146 * HW expects these in little endian so we reverse the byte order
147 * from network order (big endian) to little endian
149 rar_low = ((u32) addr[0] |
150 ((u32) addr[1] << 8) |
151 ((u32) addr[2] << 16) | ((u32) addr[3] << 24));
153 rar_high = ((u32) addr[4] | ((u32) addr[5] << 8));
155 rar_high |= E1000_RAH_AV;
157 E1000_WRITE_REG_ARRAY(hw, E1000_RA, (index << 1), rar_low);
158 E1000_WRITE_REG_ARRAY(hw, E1000_RA, ((index << 1) + 1), rar_high);
162 * e1000_mta_set - Set multicast filter table address
163 * @hw: pointer to the HW structure
164 * @hash_value: determines the MTA register and bit to set
166 * The multicast table address is a register array of 32-bit registers.
167 * The hash_value is used to determine what register the bit is in, the
168 * current value is read, the new bit is OR'd in and the new value is
169 * written back into the register.
171 static void e1000_mta_set(struct e1000_hw *hw, u32 hash_value)
173 u32 hash_bit, hash_reg, mta;
176 * The MTA is a register array of 32-bit registers. It is
177 * treated like an array of (32*mta_reg_count) bits. We want to
178 * set bit BitArray[hash_value]. So we figure out what register
179 * the bit is in, read it, OR in the new bit, then write
180 * back the new value. The (hw->mac.mta_reg_count - 1) serves as a
181 * mask to bits 31:5 of the hash value which gives us the
182 * register we're modifying. The hash bit within that register
183 * is determined by the lower 5 bits of the hash value.
185 hash_reg = (hash_value >> 5) & (hw->mac.mta_reg_count - 1);
186 hash_bit = hash_value & 0x1F;
188 mta = E1000_READ_REG_ARRAY(hw, E1000_MTA, hash_reg);
190 mta |= (1 << hash_bit);
192 E1000_WRITE_REG_ARRAY(hw, E1000_MTA, hash_reg, mta);
197 * e1000_hash_mc_addr - Generate a multicast hash value
198 * @hw: pointer to the HW structure
199 * @mc_addr: pointer to a multicast address
201 * Generates a multicast address hash value which is used to determine
202 * the multicast filter table array address and new table value. See
203 * e1000_mta_set_generic()
205 static u32 e1000_hash_mc_addr(struct e1000_hw *hw, u8 *mc_addr)
207 u32 hash_value, hash_mask;
210 /* Register count multiplied by bits per register */
211 hash_mask = (hw->mac.mta_reg_count * 32) - 1;
214 * For a mc_filter_type of 0, bit_shift is the number of left-shifts
215 * where 0xFF would still fall within the hash mask.
217 while (hash_mask >> bit_shift != 0xFF)
221 * The portion of the address that is used for the hash table
222 * is determined by the mc_filter_type setting.
223 * The algorithm is such that there is a total of 8 bits of shifting.
224 * The bit_shift for a mc_filter_type of 0 represents the number of
225 * left-shifts where the MSB of mc_addr[5] would still fall within
226 * the hash_mask. Case 0 does this exactly. Since there are a total
227 * of 8 bits of shifting, then mc_addr[4] will shift right the
228 * remaining number of bits. Thus 8 - bit_shift. The rest of the
229 * cases are a variation of this algorithm...essentially raising the
230 * number of bits to shift mc_addr[5] left, while still keeping the
231 * 8-bit shifting total.
233 * For example, given the following Destination MAC Address and an
234 * mta register count of 128 (thus a 4096-bit vector and 0xFFF mask),
235 * we can see that the bit_shift for case 0 is 4. These are the hash
236 * values resulting from each mc_filter_type...
237 * [0] [1] [2] [3] [4] [5]
241 * case 0: hash_value = ((0x34 >> 4) | (0x56 << 4)) & 0xFFF = 0x563
242 * case 1: hash_value = ((0x34 >> 3) | (0x56 << 5)) & 0xFFF = 0xAC6
243 * case 2: hash_value = ((0x34 >> 2) | (0x56 << 6)) & 0xFFF = 0x163
244 * case 3: hash_value = ((0x34 >> 0) | (0x56 << 8)) & 0xFFF = 0x634
246 switch (hw->mac.mc_filter_type) {
261 hash_value = hash_mask & (((mc_addr[4] >> (8 - bit_shift)) |
262 (((u16) mc_addr[5]) << bit_shift)));
268 * e1000e_update_mc_addr_list_generic - Update Multicast addresses
269 * @hw: pointer to the HW structure
270 * @mc_addr_list: array of multicast addresses to program
271 * @mc_addr_count: number of multicast addresses to program
272 * @rar_used_count: the first RAR register free to program
273 * @rar_count: total number of supported Receive Address Registers
275 * Updates the Receive Address Registers and Multicast Table Array.
276 * The caller must have a packed mc_addr_list of multicast addresses.
277 * The parameter rar_count will usually be hw->mac.rar_entry_count
278 * unless there are workarounds that change this.
280 void e1000e_update_mc_addr_list_generic(struct e1000_hw *hw,
281 u8 *mc_addr_list, u32 mc_addr_count,
282 u32 rar_used_count, u32 rar_count)
288 * Load the first set of multicast addresses into the exact
289 * filters (RAR). If there are not enough to fill the RAR
290 * array, clear the filters.
292 for (i = rar_used_count; i < rar_count; i++) {
294 e1000e_rar_set(hw, mc_addr_list, i);
296 mc_addr_list += ETH_ALEN;
298 E1000_WRITE_REG_ARRAY(hw, E1000_RA, i << 1, 0);
300 E1000_WRITE_REG_ARRAY(hw, E1000_RA, (i << 1) + 1, 0);
305 /* Clear the old settings from the MTA */
306 hw_dbg(hw, "Clearing MTA\n");
307 for (i = 0; i < hw->mac.mta_reg_count; i++) {
308 E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, 0);
312 /* Load any remaining multicast addresses into the hash table. */
313 for (; mc_addr_count > 0; mc_addr_count--) {
314 hash_value = e1000_hash_mc_addr(hw, mc_addr_list);
315 hw_dbg(hw, "Hash value = 0x%03X\n", hash_value);
316 e1000_mta_set(hw, hash_value);
317 mc_addr_list += ETH_ALEN;
322 * e1000e_clear_hw_cntrs_base - Clear base hardware counters
323 * @hw: pointer to the HW structure
325 * Clears the base hardware counters by reading the counter registers.
327 void e1000e_clear_hw_cntrs_base(struct e1000_hw *hw)
331 temp = er32(CRCERRS);
332 temp = er32(SYMERRS);
337 temp = er32(LATECOL);
344 temp = er32(XOFFRXC);
345 temp = er32(XOFFTXC);
371 * e1000e_check_for_copper_link - Check for link (Copper)
372 * @hw: pointer to the HW structure
374 * Checks to see of the link status of the hardware has changed. If a
375 * change in link status has been detected, then we read the PHY registers
376 * to get the current speed/duplex if link exists.
378 s32 e1000e_check_for_copper_link(struct e1000_hw *hw)
380 struct e1000_mac_info *mac = &hw->mac;
385 * We only want to go out to the PHY registers to see if Auto-Neg
386 * has completed and/or if our link status has changed. The
387 * get_link_status flag is set upon receiving a Link Status
388 * Change or Rx Sequence Error interrupt.
390 if (!mac->get_link_status)
394 * First we want to see if the MII Status Register reports
395 * link. If so, then we want to get the current speed/duplex
398 ret_val = e1000e_phy_has_link_generic(hw, 1, 0, &link);
403 return ret_val; /* No link detected */
405 mac->get_link_status = 0;
408 * Check if there was DownShift, must be checked
409 * immediately after link-up
411 e1000e_check_downshift(hw);
414 * If we are forcing speed/duplex, then we simply return since
415 * we have already determined whether we have link or not.
418 ret_val = -E1000_ERR_CONFIG;
423 * Auto-Neg is enabled. Auto Speed Detection takes care
424 * of MAC speed/duplex configuration. So we only need to
425 * configure Collision Distance in the MAC.
427 e1000e_config_collision_dist(hw);
430 * Configure Flow Control now that Auto-Neg has completed.
431 * First, we need to restore the desired flow control
432 * settings because we may have had to re-autoneg with a
433 * different link partner.
435 ret_val = e1000e_config_fc_after_link_up(hw);
437 hw_dbg(hw, "Error configuring flow control\n");
444 * e1000e_check_for_fiber_link - Check for link (Fiber)
445 * @hw: pointer to the HW structure
447 * Checks for link up on the hardware. If link is not up and we have
448 * a signal, then we need to force link up.
450 s32 e1000e_check_for_fiber_link(struct e1000_hw *hw)
452 struct e1000_mac_info *mac = &hw->mac;
459 status = er32(STATUS);
463 * If we don't have link (auto-negotiation failed or link partner
464 * cannot auto-negotiate), the cable is plugged in (we have signal),
465 * and our link partner is not trying to auto-negotiate with us (we
466 * are receiving idles or data), we need to force link up. We also
467 * need to give auto-negotiation time to complete, in case the cable
468 * was just plugged in. The autoneg_failed flag does this.
470 /* (ctrl & E1000_CTRL_SWDPIN1) == 1 == have signal */
471 if ((ctrl & E1000_CTRL_SWDPIN1) && (!(status & E1000_STATUS_LU)) &&
472 (!(rxcw & E1000_RXCW_C))) {
473 if (mac->autoneg_failed == 0) {
474 mac->autoneg_failed = 1;
477 hw_dbg(hw, "NOT RXing /C/, disable AutoNeg and force link.\n");
479 /* Disable auto-negotiation in the TXCW register */
480 ew32(TXCW, (mac->txcw & ~E1000_TXCW_ANE));
482 /* Force link-up and also force full-duplex. */
484 ctrl |= (E1000_CTRL_SLU | E1000_CTRL_FD);
487 /* Configure Flow Control after forcing link up. */
488 ret_val = e1000e_config_fc_after_link_up(hw);
490 hw_dbg(hw, "Error configuring flow control\n");
493 } else if ((ctrl & E1000_CTRL_SLU) && (rxcw & E1000_RXCW_C)) {
495 * If we are forcing link and we are receiving /C/ ordered
496 * sets, re-enable auto-negotiation in the TXCW register
497 * and disable forced link in the Device Control register
498 * in an attempt to auto-negotiate with our link partner.
500 hw_dbg(hw, "RXing /C/, enable AutoNeg and stop forcing link.\n");
501 ew32(TXCW, mac->txcw);
502 ew32(CTRL, (ctrl & ~E1000_CTRL_SLU));
504 mac->serdes_has_link = 1;
511 * e1000e_check_for_serdes_link - Check for link (Serdes)
512 * @hw: pointer to the HW structure
514 * Checks for link up on the hardware. If link is not up and we have
515 * a signal, then we need to force link up.
517 s32 e1000e_check_for_serdes_link(struct e1000_hw *hw)
519 struct e1000_mac_info *mac = &hw->mac;
526 status = er32(STATUS);
530 * If we don't have link (auto-negotiation failed or link partner
531 * cannot auto-negotiate), and our link partner is not trying to
532 * auto-negotiate with us (we are receiving idles or data),
533 * we need to force link up. We also need to give auto-negotiation
536 /* (ctrl & E1000_CTRL_SWDPIN1) == 1 == have signal */
537 if ((!(status & E1000_STATUS_LU)) && (!(rxcw & E1000_RXCW_C))) {
538 if (mac->autoneg_failed == 0) {
539 mac->autoneg_failed = 1;
542 hw_dbg(hw, "NOT RXing /C/, disable AutoNeg and force link.\n");
544 /* Disable auto-negotiation in the TXCW register */
545 ew32(TXCW, (mac->txcw & ~E1000_TXCW_ANE));
547 /* Force link-up and also force full-duplex. */
549 ctrl |= (E1000_CTRL_SLU | E1000_CTRL_FD);
552 /* Configure Flow Control after forcing link up. */
553 ret_val = e1000e_config_fc_after_link_up(hw);
555 hw_dbg(hw, "Error configuring flow control\n");
558 } else if ((ctrl & E1000_CTRL_SLU) && (rxcw & E1000_RXCW_C)) {
560 * If we are forcing link and we are receiving /C/ ordered
561 * sets, re-enable auto-negotiation in the TXCW register
562 * and disable forced link in the Device Control register
563 * in an attempt to auto-negotiate with our link partner.
565 hw_dbg(hw, "RXing /C/, enable AutoNeg and stop forcing link.\n");
566 ew32(TXCW, mac->txcw);
567 ew32(CTRL, (ctrl & ~E1000_CTRL_SLU));
569 mac->serdes_has_link = 1;
570 } else if (!(E1000_TXCW_ANE & er32(TXCW))) {
572 * If we force link for non-auto-negotiation switch, check
573 * link status based on MAC synchronization for internal
576 /* SYNCH bit and IV bit are sticky. */
578 if (E1000_RXCW_SYNCH & er32(RXCW)) {
579 if (!(rxcw & E1000_RXCW_IV)) {
580 mac->serdes_has_link = 1;
581 hw_dbg(hw, "SERDES: Link is up.\n");
584 mac->serdes_has_link = 0;
585 hw_dbg(hw, "SERDES: Link is down.\n");
589 if (E1000_TXCW_ANE & er32(TXCW)) {
590 status = er32(STATUS);
591 mac->serdes_has_link = (status & E1000_STATUS_LU);
598 * e1000_set_default_fc_generic - Set flow control default values
599 * @hw: pointer to the HW structure
601 * Read the EEPROM for the default values for flow control and store the
604 static s32 e1000_set_default_fc_generic(struct e1000_hw *hw)
606 struct e1000_mac_info *mac = &hw->mac;
611 * Read and store word 0x0F of the EEPROM. This word contains bits
612 * that determine the hardware's default PAUSE (flow control) mode,
613 * a bit that determines whether the HW defaults to enabling or
614 * disabling auto-negotiation, and the direction of the
615 * SW defined pins. If there is no SW over-ride of the flow
616 * control setting, then the variable hw->fc will
617 * be initialized based on a value in the EEPROM.
619 ret_val = e1000_read_nvm(hw, NVM_INIT_CONTROL2_REG, 1, &nvm_data);
622 hw_dbg(hw, "NVM Read Error\n");
626 if ((nvm_data & NVM_WORD0F_PAUSE_MASK) == 0)
627 mac->fc = e1000_fc_none;
628 else if ((nvm_data & NVM_WORD0F_PAUSE_MASK) ==
630 mac->fc = e1000_fc_tx_pause;
632 mac->fc = e1000_fc_full;
638 * e1000e_setup_link - Setup flow control and link settings
639 * @hw: pointer to the HW structure
641 * Determines which flow control settings to use, then configures flow
642 * control. Calls the appropriate media-specific link configuration
643 * function. Assuming the adapter has a valid link partner, a valid link
644 * should be established. Assumes the hardware has previously been reset
645 * and the transmitter and receiver are not enabled.
647 s32 e1000e_setup_link(struct e1000_hw *hw)
649 struct e1000_mac_info *mac = &hw->mac;
653 * In the case of the phy reset being blocked, we already have a link.
654 * We do not need to set it up again.
656 if (e1000_check_reset_block(hw))
660 * If flow control is set to default, set flow control based on
661 * the EEPROM flow control settings.
663 if (mac->fc == e1000_fc_default) {
664 ret_val = e1000_set_default_fc_generic(hw);
670 * We want to save off the original Flow Control configuration just
671 * in case we get disconnected and then reconnected into a different
672 * hub or switch with different Flow Control capabilities.
674 mac->original_fc = mac->fc;
676 hw_dbg(hw, "After fix-ups FlowControl is now = %x\n", mac->fc);
678 /* Call the necessary media_type subroutine to configure the link. */
679 ret_val = mac->ops.setup_physical_interface(hw);
684 * Initialize the flow control address, type, and PAUSE timer
685 * registers to their default values. This is done even if flow
686 * control is disabled, because it does not hurt anything to
687 * initialize these registers.
689 hw_dbg(hw, "Initializing the Flow Control address, type and timer regs\n");
690 ew32(FCT, FLOW_CONTROL_TYPE);
691 ew32(FCAH, FLOW_CONTROL_ADDRESS_HIGH);
692 ew32(FCAL, FLOW_CONTROL_ADDRESS_LOW);
694 ew32(FCTTV, mac->fc_pause_time);
696 return e1000e_set_fc_watermarks(hw);
700 * e1000_commit_fc_settings_generic - Configure flow control
701 * @hw: pointer to the HW structure
703 * Write the flow control settings to the Transmit Config Word Register (TXCW)
704 * base on the flow control settings in e1000_mac_info.
706 static s32 e1000_commit_fc_settings_generic(struct e1000_hw *hw)
708 struct e1000_mac_info *mac = &hw->mac;
712 * Check for a software override of the flow control settings, and
713 * setup the device accordingly. If auto-negotiation is enabled, then
714 * software will have to set the "PAUSE" bits to the correct value in
715 * the Transmit Config Word Register (TXCW) and re-start auto-
716 * negotiation. However, if auto-negotiation is disabled, then
717 * software will have to manually configure the two flow control enable
718 * bits in the CTRL register.
720 * The possible values of the "fc" parameter are:
721 * 0: Flow control is completely disabled
722 * 1: Rx flow control is enabled (we can receive pause frames,
723 * but not send pause frames).
724 * 2: Tx flow control is enabled (we can send pause frames but we
725 * do not support receiving pause frames).
726 * 3: Both Rx and Tx flow control (symmetric) are enabled.
730 /* Flow control completely disabled by a software over-ride. */
731 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD);
733 case e1000_fc_rx_pause:
735 * Rx Flow control is enabled and Tx Flow control is disabled
736 * by a software over-ride. Since there really isn't a way to
737 * advertise that we are capable of Rx Pause ONLY, we will
738 * advertise that we support both symmetric and asymmetric Rx
739 * PAUSE. Later, we will disable the adapter's ability to send
742 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_PAUSE_MASK);
744 case e1000_fc_tx_pause:
746 * Tx Flow control is enabled, and Rx Flow control is disabled,
747 * by a software over-ride.
749 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_ASM_DIR);
753 * Flow control (both Rx and Tx) is enabled by a software
756 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_PAUSE_MASK);
759 hw_dbg(hw, "Flow control param set incorrectly\n");
760 return -E1000_ERR_CONFIG;
771 * e1000_poll_fiber_serdes_link_generic - Poll for link up
772 * @hw: pointer to the HW structure
774 * Polls for link up by reading the status register, if link fails to come
775 * up with auto-negotiation, then the link is forced if a signal is detected.
777 static s32 e1000_poll_fiber_serdes_link_generic(struct e1000_hw *hw)
779 struct e1000_mac_info *mac = &hw->mac;
784 * If we have a signal (the cable is plugged in, or assumed true for
785 * serdes media) then poll for a "Link-Up" indication in the Device
786 * Status Register. Time-out if a link isn't seen in 500 milliseconds
787 * seconds (Auto-negotiation should complete in less than 500
788 * milliseconds even if the other end is doing it in SW).
790 for (i = 0; i < FIBER_LINK_UP_LIMIT; i++) {
792 status = er32(STATUS);
793 if (status & E1000_STATUS_LU)
796 if (i == FIBER_LINK_UP_LIMIT) {
797 hw_dbg(hw, "Never got a valid link from auto-neg!!!\n");
798 mac->autoneg_failed = 1;
800 * AutoNeg failed to achieve a link, so we'll call
801 * mac->check_for_link. This routine will force the
802 * link up if we detect a signal. This will allow us to
803 * communicate with non-autonegotiating link partners.
805 ret_val = mac->ops.check_for_link(hw);
807 hw_dbg(hw, "Error while checking for link\n");
810 mac->autoneg_failed = 0;
812 mac->autoneg_failed = 0;
813 hw_dbg(hw, "Valid Link Found\n");
820 * e1000e_setup_fiber_serdes_link - Setup link for fiber/serdes
821 * @hw: pointer to the HW structure
823 * Configures collision distance and flow control for fiber and serdes
824 * links. Upon successful setup, poll for link.
826 s32 e1000e_setup_fiber_serdes_link(struct e1000_hw *hw)
833 /* Take the link out of reset */
834 ctrl &= ~E1000_CTRL_LRST;
836 e1000e_config_collision_dist(hw);
838 ret_val = e1000_commit_fc_settings_generic(hw);
843 * Since auto-negotiation is enabled, take the link out of reset (the
844 * link will be in reset, because we previously reset the chip). This
845 * will restart auto-negotiation. If auto-negotiation is successful
846 * then the link-up status bit will be set and the flow control enable
847 * bits (RFCE and TFCE) will be set according to their negotiated value.
849 hw_dbg(hw, "Auto-negotiation enabled\n");
856 * For these adapters, the SW definable pin 1 is set when the optics
857 * detect a signal. If we have a signal, then poll for a "Link-Up"
860 if (hw->media_type == e1000_media_type_internal_serdes ||
861 (er32(CTRL) & E1000_CTRL_SWDPIN1)) {
862 ret_val = e1000_poll_fiber_serdes_link_generic(hw);
864 hw_dbg(hw, "No signal detected\n");
871 * e1000e_config_collision_dist - Configure collision distance
872 * @hw: pointer to the HW structure
874 * Configures the collision distance to the default value and is used
875 * during link setup. Currently no func pointer exists and all
876 * implementations are handled in the generic version of this function.
878 void e1000e_config_collision_dist(struct e1000_hw *hw)
884 tctl &= ~E1000_TCTL_COLD;
885 tctl |= E1000_COLLISION_DISTANCE << E1000_COLD_SHIFT;
892 * e1000e_set_fc_watermarks - Set flow control high/low watermarks
893 * @hw: pointer to the HW structure
895 * Sets the flow control high/low threshold (watermark) registers. If
896 * flow control XON frame transmission is enabled, then set XON frame
897 * transmission as well.
899 s32 e1000e_set_fc_watermarks(struct e1000_hw *hw)
901 struct e1000_mac_info *mac = &hw->mac;
902 u32 fcrtl = 0, fcrth = 0;
905 * Set the flow control receive threshold registers. Normally,
906 * these registers will be set to a default threshold that may be
907 * adjusted later by the driver's runtime code. However, if the
908 * ability to transmit pause frames is not enabled, then these
909 * registers will be set to 0.
911 if (mac->fc & e1000_fc_tx_pause) {
913 * We need to set up the Receive Threshold high and low water
914 * marks as well as (optionally) enabling the transmission of
917 fcrtl = mac->fc_low_water;
918 fcrtl |= E1000_FCRTL_XONE;
919 fcrth = mac->fc_high_water;
928 * e1000e_force_mac_fc - Force the MAC's flow control settings
929 * @hw: pointer to the HW structure
931 * Force the MAC's flow control settings. Sets the TFCE and RFCE bits in the
932 * device control register to reflect the adapter settings. TFCE and RFCE
933 * need to be explicitly set by software when a copper PHY is used because
934 * autonegotiation is managed by the PHY rather than the MAC. Software must
935 * also configure these bits when link is forced on a fiber connection.
937 s32 e1000e_force_mac_fc(struct e1000_hw *hw)
939 struct e1000_mac_info *mac = &hw->mac;
945 * Because we didn't get link via the internal auto-negotiation
946 * mechanism (we either forced link or we got link via PHY
947 * auto-neg), we have to manually enable/disable transmit an
948 * receive flow control.
950 * The "Case" statement below enables/disable flow control
951 * according to the "mac->fc" parameter.
953 * The possible values of the "fc" parameter are:
954 * 0: Flow control is completely disabled
955 * 1: Rx flow control is enabled (we can receive pause
956 * frames but not send pause frames).
957 * 2: Tx flow control is enabled (we can send pause frames
958 * frames but we do not receive pause frames).
959 * 3: Both Rx and Tx flow control (symmetric) is enabled.
960 * other: No other values should be possible at this point.
962 hw_dbg(hw, "mac->fc = %u\n", mac->fc);
966 ctrl &= (~(E1000_CTRL_TFCE | E1000_CTRL_RFCE));
968 case e1000_fc_rx_pause:
969 ctrl &= (~E1000_CTRL_TFCE);
970 ctrl |= E1000_CTRL_RFCE;
972 case e1000_fc_tx_pause:
973 ctrl &= (~E1000_CTRL_RFCE);
974 ctrl |= E1000_CTRL_TFCE;
977 ctrl |= (E1000_CTRL_TFCE | E1000_CTRL_RFCE);
980 hw_dbg(hw, "Flow control param set incorrectly\n");
981 return -E1000_ERR_CONFIG;
990 * e1000e_config_fc_after_link_up - Configures flow control after link
991 * @hw: pointer to the HW structure
993 * Checks the status of auto-negotiation after link up to ensure that the
994 * speed and duplex were not forced. If the link needed to be forced, then
995 * flow control needs to be forced also. If auto-negotiation is enabled
996 * and did not fail, then we configure flow control based on our link
999 s32 e1000e_config_fc_after_link_up(struct e1000_hw *hw)
1001 struct e1000_mac_info *mac = &hw->mac;
1003 u16 mii_status_reg, mii_nway_adv_reg, mii_nway_lp_ability_reg;
1007 * Check for the case where we have fiber media and auto-neg failed
1008 * so we had to force link. In this case, we need to force the
1009 * configuration of the MAC to match the "fc" parameter.
1011 if (mac->autoneg_failed) {
1012 if (hw->media_type == e1000_media_type_fiber ||
1013 hw->media_type == e1000_media_type_internal_serdes)
1014 ret_val = e1000e_force_mac_fc(hw);
1016 if (hw->media_type == e1000_media_type_copper)
1017 ret_val = e1000e_force_mac_fc(hw);
1021 hw_dbg(hw, "Error forcing flow control settings\n");
1026 * Check for the case where we have copper media and auto-neg is
1027 * enabled. In this case, we need to check and see if Auto-Neg
1028 * has completed, and if so, how the PHY and link partner has
1029 * flow control configured.
1031 if ((hw->media_type == e1000_media_type_copper) && mac->autoneg) {
1033 * Read the MII Status Register and check to see if AutoNeg
1034 * has completed. We read this twice because this reg has
1035 * some "sticky" (latched) bits.
1037 ret_val = e1e_rphy(hw, PHY_STATUS, &mii_status_reg);
1040 ret_val = e1e_rphy(hw, PHY_STATUS, &mii_status_reg);
1044 if (!(mii_status_reg & MII_SR_AUTONEG_COMPLETE)) {
1045 hw_dbg(hw, "Copper PHY and Auto Neg "
1046 "has not completed.\n");
1051 * The AutoNeg process has completed, so we now need to
1052 * read both the Auto Negotiation Advertisement
1053 * Register (Address 4) and the Auto_Negotiation Base
1054 * Page Ability Register (Address 5) to determine how
1055 * flow control was negotiated.
1057 ret_val = e1e_rphy(hw, PHY_AUTONEG_ADV, &mii_nway_adv_reg);
1060 ret_val = e1e_rphy(hw, PHY_LP_ABILITY, &mii_nway_lp_ability_reg);
1065 * Two bits in the Auto Negotiation Advertisement Register
1066 * (Address 4) and two bits in the Auto Negotiation Base
1067 * Page Ability Register (Address 5) determine flow control
1068 * for both the PHY and the link partner. The following
1069 * table, taken out of the IEEE 802.3ab/D6.0 dated March 25,
1070 * 1999, describes these PAUSE resolution bits and how flow
1071 * control is determined based upon these settings.
1072 * NOTE: DC = Don't Care
1074 * LOCAL DEVICE | LINK PARTNER
1075 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | NIC Resolution
1076 *-------|---------|-------|---------|--------------------
1077 * 0 | 0 | DC | DC | e1000_fc_none
1078 * 0 | 1 | 0 | DC | e1000_fc_none
1079 * 0 | 1 | 1 | 0 | e1000_fc_none
1080 * 0 | 1 | 1 | 1 | e1000_fc_tx_pause
1081 * 1 | 0 | 0 | DC | e1000_fc_none
1082 * 1 | DC | 1 | DC | e1000_fc_full
1083 * 1 | 1 | 0 | 0 | e1000_fc_none
1084 * 1 | 1 | 0 | 1 | e1000_fc_rx_pause
1087 * Are both PAUSE bits set to 1? If so, this implies
1088 * Symmetric Flow Control is enabled at both ends. The
1089 * ASM_DIR bits are irrelevant per the spec.
1091 * For Symmetric Flow Control:
1093 * LOCAL DEVICE | LINK PARTNER
1094 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
1095 *-------|---------|-------|---------|--------------------
1096 * 1 | DC | 1 | DC | E1000_fc_full
1099 if ((mii_nway_adv_reg & NWAY_AR_PAUSE) &&
1100 (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE)) {
1102 * Now we need to check if the user selected Rx ONLY
1103 * of pause frames. In this case, we had to advertise
1104 * FULL flow control because we could not advertise Rx
1105 * ONLY. Hence, we must now check to see if we need to
1106 * turn OFF the TRANSMISSION of PAUSE frames.
1108 if (mac->original_fc == e1000_fc_full) {
1109 mac->fc = e1000_fc_full;
1110 hw_dbg(hw, "Flow Control = FULL.\r\n");
1112 mac->fc = e1000_fc_rx_pause;
1113 hw_dbg(hw, "Flow Control = "
1114 "RX PAUSE frames only.\r\n");
1118 * For receiving PAUSE frames ONLY.
1120 * LOCAL DEVICE | LINK PARTNER
1121 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
1122 *-------|---------|-------|---------|--------------------
1123 * 0 | 1 | 1 | 1 | e1000_fc_tx_pause
1126 else if (!(mii_nway_adv_reg & NWAY_AR_PAUSE) &&
1127 (mii_nway_adv_reg & NWAY_AR_ASM_DIR) &&
1128 (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) &&
1129 (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR)) {
1130 mac->fc = e1000_fc_tx_pause;
1131 hw_dbg(hw, "Flow Control = TX PAUSE frames only.\r\n");
1134 * For transmitting PAUSE frames ONLY.
1136 * LOCAL DEVICE | LINK PARTNER
1137 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
1138 *-------|---------|-------|---------|--------------------
1139 * 1 | 1 | 0 | 1 | e1000_fc_rx_pause
1142 else if ((mii_nway_adv_reg & NWAY_AR_PAUSE) &&
1143 (mii_nway_adv_reg & NWAY_AR_ASM_DIR) &&
1144 !(mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) &&
1145 (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR)) {
1146 mac->fc = e1000_fc_rx_pause;
1147 hw_dbg(hw, "Flow Control = RX PAUSE frames only.\r\n");
1150 * Per the IEEE spec, at this point flow control
1151 * should be disabled.
1153 mac->fc = e1000_fc_none;
1154 hw_dbg(hw, "Flow Control = NONE.\r\n");
1158 * Now we need to do one last check... If we auto-
1159 * negotiated to HALF DUPLEX, flow control should not be
1160 * enabled per IEEE 802.3 spec.
1162 ret_val = mac->ops.get_link_up_info(hw, &speed, &duplex);
1164 hw_dbg(hw, "Error getting link speed and duplex\n");
1168 if (duplex == HALF_DUPLEX)
1169 mac->fc = e1000_fc_none;
1172 * Now we call a subroutine to actually force the MAC
1173 * controller to use the correct flow control settings.
1175 ret_val = e1000e_force_mac_fc(hw);
1177 hw_dbg(hw, "Error forcing flow control settings\n");
1186 * e1000e_get_speed_and_duplex_copper - Retrieve current speed/duplex
1187 * @hw: pointer to the HW structure
1188 * @speed: stores the current speed
1189 * @duplex: stores the current duplex
1191 * Read the status register for the current speed/duplex and store the current
1192 * speed and duplex for copper connections.
1194 s32 e1000e_get_speed_and_duplex_copper(struct e1000_hw *hw, u16 *speed, u16 *duplex)
1198 status = er32(STATUS);
1199 if (status & E1000_STATUS_SPEED_1000) {
1200 *speed = SPEED_1000;
1201 hw_dbg(hw, "1000 Mbs, ");
1202 } else if (status & E1000_STATUS_SPEED_100) {
1204 hw_dbg(hw, "100 Mbs, ");
1207 hw_dbg(hw, "10 Mbs, ");
1210 if (status & E1000_STATUS_FD) {
1211 *duplex = FULL_DUPLEX;
1212 hw_dbg(hw, "Full Duplex\n");
1214 *duplex = HALF_DUPLEX;
1215 hw_dbg(hw, "Half Duplex\n");
1222 * e1000e_get_speed_and_duplex_fiber_serdes - Retrieve current speed/duplex
1223 * @hw: pointer to the HW structure
1224 * @speed: stores the current speed
1225 * @duplex: stores the current duplex
1227 * Sets the speed and duplex to gigabit full duplex (the only possible option)
1228 * for fiber/serdes links.
1230 s32 e1000e_get_speed_and_duplex_fiber_serdes(struct e1000_hw *hw, u16 *speed, u16 *duplex)
1232 *speed = SPEED_1000;
1233 *duplex = FULL_DUPLEX;
1239 * e1000e_get_hw_semaphore - Acquire hardware semaphore
1240 * @hw: pointer to the HW structure
1242 * Acquire the HW semaphore to access the PHY or NVM
1244 s32 e1000e_get_hw_semaphore(struct e1000_hw *hw)
1247 s32 timeout = hw->nvm.word_size + 1;
1250 /* Get the SW semaphore */
1251 while (i < timeout) {
1253 if (!(swsm & E1000_SWSM_SMBI))
1261 hw_dbg(hw, "Driver can't access device - SMBI bit is set.\n");
1262 return -E1000_ERR_NVM;
1265 /* Get the FW semaphore. */
1266 for (i = 0; i < timeout; i++) {
1268 ew32(SWSM, swsm | E1000_SWSM_SWESMBI);
1270 /* Semaphore acquired if bit latched */
1271 if (er32(SWSM) & E1000_SWSM_SWESMBI)
1278 /* Release semaphores */
1279 e1000e_put_hw_semaphore(hw);
1280 hw_dbg(hw, "Driver can't access the NVM\n");
1281 return -E1000_ERR_NVM;
1288 * e1000e_put_hw_semaphore - Release hardware semaphore
1289 * @hw: pointer to the HW structure
1291 * Release hardware semaphore used to access the PHY or NVM
1293 void e1000e_put_hw_semaphore(struct e1000_hw *hw)
1298 swsm &= ~(E1000_SWSM_SMBI | E1000_SWSM_SWESMBI);
1303 * e1000e_get_auto_rd_done - Check for auto read completion
1304 * @hw: pointer to the HW structure
1306 * Check EEPROM for Auto Read done bit.
1308 s32 e1000e_get_auto_rd_done(struct e1000_hw *hw)
1312 while (i < AUTO_READ_DONE_TIMEOUT) {
1313 if (er32(EECD) & E1000_EECD_AUTO_RD)
1319 if (i == AUTO_READ_DONE_TIMEOUT) {
1320 hw_dbg(hw, "Auto read by HW from NVM has not completed.\n");
1321 return -E1000_ERR_RESET;
1328 * e1000e_valid_led_default - Verify a valid default LED config
1329 * @hw: pointer to the HW structure
1330 * @data: pointer to the NVM (EEPROM)
1332 * Read the EEPROM for the current default LED configuration. If the
1333 * LED configuration is not valid, set to a valid LED configuration.
1335 s32 e1000e_valid_led_default(struct e1000_hw *hw, u16 *data)
1339 ret_val = e1000_read_nvm(hw, NVM_ID_LED_SETTINGS, 1, data);
1341 hw_dbg(hw, "NVM Read Error\n");
1345 if (*data == ID_LED_RESERVED_0000 || *data == ID_LED_RESERVED_FFFF)
1346 *data = ID_LED_DEFAULT;
1352 * e1000e_id_led_init -
1353 * @hw: pointer to the HW structure
1356 s32 e1000e_id_led_init(struct e1000_hw *hw)
1358 struct e1000_mac_info *mac = &hw->mac;
1360 const u32 ledctl_mask = 0x000000FF;
1361 const u32 ledctl_on = E1000_LEDCTL_MODE_LED_ON;
1362 const u32 ledctl_off = E1000_LEDCTL_MODE_LED_OFF;
1364 const u16 led_mask = 0x0F;
1366 ret_val = hw->nvm.ops.valid_led_default(hw, &data);
1370 mac->ledctl_default = er32(LEDCTL);
1371 mac->ledctl_mode1 = mac->ledctl_default;
1372 mac->ledctl_mode2 = mac->ledctl_default;
1374 for (i = 0; i < 4; i++) {
1375 temp = (data >> (i << 2)) & led_mask;
1377 case ID_LED_ON1_DEF2:
1378 case ID_LED_ON1_ON2:
1379 case ID_LED_ON1_OFF2:
1380 mac->ledctl_mode1 &= ~(ledctl_mask << (i << 3));
1381 mac->ledctl_mode1 |= ledctl_on << (i << 3);
1383 case ID_LED_OFF1_DEF2:
1384 case ID_LED_OFF1_ON2:
1385 case ID_LED_OFF1_OFF2:
1386 mac->ledctl_mode1 &= ~(ledctl_mask << (i << 3));
1387 mac->ledctl_mode1 |= ledctl_off << (i << 3);
1394 case ID_LED_DEF1_ON2:
1395 case ID_LED_ON1_ON2:
1396 case ID_LED_OFF1_ON2:
1397 mac->ledctl_mode2 &= ~(ledctl_mask << (i << 3));
1398 mac->ledctl_mode2 |= ledctl_on << (i << 3);
1400 case ID_LED_DEF1_OFF2:
1401 case ID_LED_ON1_OFF2:
1402 case ID_LED_OFF1_OFF2:
1403 mac->ledctl_mode2 &= ~(ledctl_mask << (i << 3));
1404 mac->ledctl_mode2 |= ledctl_off << (i << 3);
1416 * e1000e_cleanup_led_generic - Set LED config to default operation
1417 * @hw: pointer to the HW structure
1419 * Remove the current LED configuration and set the LED configuration
1420 * to the default value, saved from the EEPROM.
1422 s32 e1000e_cleanup_led_generic(struct e1000_hw *hw)
1424 ew32(LEDCTL, hw->mac.ledctl_default);
1429 * e1000e_blink_led - Blink LED
1430 * @hw: pointer to the HW structure
1432 * Blink the LEDs which are set to be on.
1434 s32 e1000e_blink_led(struct e1000_hw *hw)
1436 u32 ledctl_blink = 0;
1439 if (hw->media_type == e1000_media_type_fiber) {
1440 /* always blink LED0 for PCI-E fiber */
1441 ledctl_blink = E1000_LEDCTL_LED0_BLINK |
1442 (E1000_LEDCTL_MODE_LED_ON << E1000_LEDCTL_LED0_MODE_SHIFT);
1445 * set the blink bit for each LED that's "on" (0x0E)
1448 ledctl_blink = hw->mac.ledctl_mode2;
1449 for (i = 0; i < 4; i++)
1450 if (((hw->mac.ledctl_mode2 >> (i * 8)) & 0xFF) ==
1451 E1000_LEDCTL_MODE_LED_ON)
1452 ledctl_blink |= (E1000_LEDCTL_LED0_BLINK <<
1456 ew32(LEDCTL, ledctl_blink);
1462 * e1000e_led_on_generic - Turn LED on
1463 * @hw: pointer to the HW structure
1467 s32 e1000e_led_on_generic(struct e1000_hw *hw)
1471 switch (hw->media_type) {
1472 case e1000_media_type_fiber:
1474 ctrl &= ~E1000_CTRL_SWDPIN0;
1475 ctrl |= E1000_CTRL_SWDPIO0;
1478 case e1000_media_type_copper:
1479 ew32(LEDCTL, hw->mac.ledctl_mode2);
1489 * e1000e_led_off_generic - Turn LED off
1490 * @hw: pointer to the HW structure
1494 s32 e1000e_led_off_generic(struct e1000_hw *hw)
1498 switch (hw->media_type) {
1499 case e1000_media_type_fiber:
1501 ctrl |= E1000_CTRL_SWDPIN0;
1502 ctrl |= E1000_CTRL_SWDPIO0;
1505 case e1000_media_type_copper:
1506 ew32(LEDCTL, hw->mac.ledctl_mode1);
1516 * e1000e_set_pcie_no_snoop - Set PCI-express capabilities
1517 * @hw: pointer to the HW structure
1518 * @no_snoop: bitmap of snoop events
1520 * Set the PCI-express register to snoop for events enabled in 'no_snoop'.
1522 void e1000e_set_pcie_no_snoop(struct e1000_hw *hw, u32 no_snoop)
1528 gcr &= ~(PCIE_NO_SNOOP_ALL);
1535 * e1000e_disable_pcie_master - Disables PCI-express master access
1536 * @hw: pointer to the HW structure
1538 * Returns 0 if successful, else returns -10
1539 * (-E1000_ERR_MASTER_REQUESTS_PENDING) if master disable bit has not caused
1540 * the master requests to be disabled.
1542 * Disables PCI-Express master access and verifies there are no pending
1545 s32 e1000e_disable_pcie_master(struct e1000_hw *hw)
1548 s32 timeout = MASTER_DISABLE_TIMEOUT;
1551 ctrl |= E1000_CTRL_GIO_MASTER_DISABLE;
1555 if (!(er32(STATUS) &
1556 E1000_STATUS_GIO_MASTER_ENABLE))
1563 hw_dbg(hw, "Master requests are pending.\n");
1564 return -E1000_ERR_MASTER_REQUESTS_PENDING;
1571 * e1000e_reset_adaptive - Reset Adaptive Interframe Spacing
1572 * @hw: pointer to the HW structure
1574 * Reset the Adaptive Interframe Spacing throttle to default values.
1576 void e1000e_reset_adaptive(struct e1000_hw *hw)
1578 struct e1000_mac_info *mac = &hw->mac;
1580 mac->current_ifs_val = 0;
1581 mac->ifs_min_val = IFS_MIN;
1582 mac->ifs_max_val = IFS_MAX;
1583 mac->ifs_step_size = IFS_STEP;
1584 mac->ifs_ratio = IFS_RATIO;
1586 mac->in_ifs_mode = 0;
1591 * e1000e_update_adaptive - Update Adaptive Interframe Spacing
1592 * @hw: pointer to the HW structure
1594 * Update the Adaptive Interframe Spacing Throttle value based on the
1595 * time between transmitted packets and time between collisions.
1597 void e1000e_update_adaptive(struct e1000_hw *hw)
1599 struct e1000_mac_info *mac = &hw->mac;
1601 if ((mac->collision_delta * mac->ifs_ratio) > mac->tx_packet_delta) {
1602 if (mac->tx_packet_delta > MIN_NUM_XMITS) {
1603 mac->in_ifs_mode = 1;
1604 if (mac->current_ifs_val < mac->ifs_max_val) {
1605 if (!mac->current_ifs_val)
1606 mac->current_ifs_val = mac->ifs_min_val;
1608 mac->current_ifs_val +=
1610 ew32(AIT, mac->current_ifs_val);
1614 if (mac->in_ifs_mode &&
1615 (mac->tx_packet_delta <= MIN_NUM_XMITS)) {
1616 mac->current_ifs_val = 0;
1617 mac->in_ifs_mode = 0;
1624 * e1000_raise_eec_clk - Raise EEPROM clock
1625 * @hw: pointer to the HW structure
1626 * @eecd: pointer to the EEPROM
1628 * Enable/Raise the EEPROM clock bit.
1630 static void e1000_raise_eec_clk(struct e1000_hw *hw, u32 *eecd)
1632 *eecd = *eecd | E1000_EECD_SK;
1635 udelay(hw->nvm.delay_usec);
1639 * e1000_lower_eec_clk - Lower EEPROM clock
1640 * @hw: pointer to the HW structure
1641 * @eecd: pointer to the EEPROM
1643 * Clear/Lower the EEPROM clock bit.
1645 static void e1000_lower_eec_clk(struct e1000_hw *hw, u32 *eecd)
1647 *eecd = *eecd & ~E1000_EECD_SK;
1650 udelay(hw->nvm.delay_usec);
1654 * e1000_shift_out_eec_bits - Shift data bits our to the EEPROM
1655 * @hw: pointer to the HW structure
1656 * @data: data to send to the EEPROM
1657 * @count: number of bits to shift out
1659 * We need to shift 'count' bits out to the EEPROM. So, the value in the
1660 * "data" parameter will be shifted out to the EEPROM one bit at a time.
1661 * In order to do this, "data" must be broken down into bits.
1663 static void e1000_shift_out_eec_bits(struct e1000_hw *hw, u16 data, u16 count)
1665 struct e1000_nvm_info *nvm = &hw->nvm;
1666 u32 eecd = er32(EECD);
1669 mask = 0x01 << (count - 1);
1670 if (nvm->type == e1000_nvm_eeprom_spi)
1671 eecd |= E1000_EECD_DO;
1674 eecd &= ~E1000_EECD_DI;
1677 eecd |= E1000_EECD_DI;
1682 udelay(nvm->delay_usec);
1684 e1000_raise_eec_clk(hw, &eecd);
1685 e1000_lower_eec_clk(hw, &eecd);
1690 eecd &= ~E1000_EECD_DI;
1695 * e1000_shift_in_eec_bits - Shift data bits in from the EEPROM
1696 * @hw: pointer to the HW structure
1697 * @count: number of bits to shift in
1699 * In order to read a register from the EEPROM, we need to shift 'count' bits
1700 * in from the EEPROM. Bits are "shifted in" by raising the clock input to
1701 * the EEPROM (setting the SK bit), and then reading the value of the data out
1702 * "DO" bit. During this "shifting in" process the data in "DI" bit should
1705 static u16 e1000_shift_in_eec_bits(struct e1000_hw *hw, u16 count)
1713 eecd &= ~(E1000_EECD_DO | E1000_EECD_DI);
1716 for (i = 0; i < count; i++) {
1718 e1000_raise_eec_clk(hw, &eecd);
1722 eecd &= ~E1000_EECD_DI;
1723 if (eecd & E1000_EECD_DO)
1726 e1000_lower_eec_clk(hw, &eecd);
1733 * e1000e_poll_eerd_eewr_done - Poll for EEPROM read/write completion
1734 * @hw: pointer to the HW structure
1735 * @ee_reg: EEPROM flag for polling
1737 * Polls the EEPROM status bit for either read or write completion based
1738 * upon the value of 'ee_reg'.
1740 s32 e1000e_poll_eerd_eewr_done(struct e1000_hw *hw, int ee_reg)
1742 u32 attempts = 100000;
1745 for (i = 0; i < attempts; i++) {
1746 if (ee_reg == E1000_NVM_POLL_READ)
1751 if (reg & E1000_NVM_RW_REG_DONE)
1757 return -E1000_ERR_NVM;
1761 * e1000e_acquire_nvm - Generic request for access to EEPROM
1762 * @hw: pointer to the HW structure
1764 * Set the EEPROM access request bit and wait for EEPROM access grant bit.
1765 * Return successful if access grant bit set, else clear the request for
1766 * EEPROM access and return -E1000_ERR_NVM (-1).
1768 s32 e1000e_acquire_nvm(struct e1000_hw *hw)
1770 u32 eecd = er32(EECD);
1771 s32 timeout = E1000_NVM_GRANT_ATTEMPTS;
1773 ew32(EECD, eecd | E1000_EECD_REQ);
1777 if (eecd & E1000_EECD_GNT)
1785 eecd &= ~E1000_EECD_REQ;
1787 hw_dbg(hw, "Could not acquire NVM grant\n");
1788 return -E1000_ERR_NVM;
1795 * e1000_standby_nvm - Return EEPROM to standby state
1796 * @hw: pointer to the HW structure
1798 * Return the EEPROM to a standby state.
1800 static void e1000_standby_nvm(struct e1000_hw *hw)
1802 struct e1000_nvm_info *nvm = &hw->nvm;
1803 u32 eecd = er32(EECD);
1805 if (nvm->type == e1000_nvm_eeprom_spi) {
1806 /* Toggle CS to flush commands */
1807 eecd |= E1000_EECD_CS;
1810 udelay(nvm->delay_usec);
1811 eecd &= ~E1000_EECD_CS;
1814 udelay(nvm->delay_usec);
1819 * e1000_stop_nvm - Terminate EEPROM command
1820 * @hw: pointer to the HW structure
1822 * Terminates the current command by inverting the EEPROM's chip select pin.
1824 static void e1000_stop_nvm(struct e1000_hw *hw)
1829 if (hw->nvm.type == e1000_nvm_eeprom_spi) {
1831 eecd |= E1000_EECD_CS;
1832 e1000_lower_eec_clk(hw, &eecd);
1837 * e1000e_release_nvm - Release exclusive access to EEPROM
1838 * @hw: pointer to the HW structure
1840 * Stop any current commands to the EEPROM and clear the EEPROM request bit.
1842 void e1000e_release_nvm(struct e1000_hw *hw)
1849 eecd &= ~E1000_EECD_REQ;
1854 * e1000_ready_nvm_eeprom - Prepares EEPROM for read/write
1855 * @hw: pointer to the HW structure
1857 * Setups the EEPROM for reading and writing.
1859 static s32 e1000_ready_nvm_eeprom(struct e1000_hw *hw)
1861 struct e1000_nvm_info *nvm = &hw->nvm;
1862 u32 eecd = er32(EECD);
1866 if (nvm->type == e1000_nvm_eeprom_spi) {
1867 /* Clear SK and CS */
1868 eecd &= ~(E1000_EECD_CS | E1000_EECD_SK);
1871 timeout = NVM_MAX_RETRY_SPI;
1874 * Read "Status Register" repeatedly until the LSB is cleared.
1875 * The EEPROM will signal that the command has been completed
1876 * by clearing bit 0 of the internal status register. If it's
1877 * not cleared within 'timeout', then error out.
1880 e1000_shift_out_eec_bits(hw, NVM_RDSR_OPCODE_SPI,
1881 hw->nvm.opcode_bits);
1882 spi_stat_reg = (u8)e1000_shift_in_eec_bits(hw, 8);
1883 if (!(spi_stat_reg & NVM_STATUS_RDY_SPI))
1887 e1000_standby_nvm(hw);
1892 hw_dbg(hw, "SPI NVM Status error\n");
1893 return -E1000_ERR_NVM;
1901 * e1000e_read_nvm_eerd - Reads EEPROM using EERD register
1902 * @hw: pointer to the HW structure
1903 * @offset: offset of word in the EEPROM to read
1904 * @words: number of words to read
1905 * @data: word read from the EEPROM
1907 * Reads a 16 bit word from the EEPROM using the EERD register.
1909 s32 e1000e_read_nvm_eerd(struct e1000_hw *hw, u16 offset, u16 words, u16 *data)
1911 struct e1000_nvm_info *nvm = &hw->nvm;
1916 * A check for invalid values: offset too large, too many words,
1917 * too many words for the offset, and not enough words.
1919 if ((offset >= nvm->word_size) || (words > (nvm->word_size - offset)) ||
1921 hw_dbg(hw, "nvm parameter(s) out of bounds\n");
1922 return -E1000_ERR_NVM;
1925 for (i = 0; i < words; i++) {
1926 eerd = ((offset+i) << E1000_NVM_RW_ADDR_SHIFT) +
1927 E1000_NVM_RW_REG_START;
1930 ret_val = e1000e_poll_eerd_eewr_done(hw, E1000_NVM_POLL_READ);
1934 data[i] = (er32(EERD) >> E1000_NVM_RW_REG_DATA);
1941 * e1000e_write_nvm_spi - Write to EEPROM using SPI
1942 * @hw: pointer to the HW structure
1943 * @offset: offset within the EEPROM to be written to
1944 * @words: number of words to write
1945 * @data: 16 bit word(s) to be written to the EEPROM
1947 * Writes data to EEPROM at offset using SPI interface.
1949 * If e1000e_update_nvm_checksum is not called after this function , the
1950 * EEPROM will most likely contain an invalid checksum.
1952 s32 e1000e_write_nvm_spi(struct e1000_hw *hw, u16 offset, u16 words, u16 *data)
1954 struct e1000_nvm_info *nvm = &hw->nvm;
1959 * A check for invalid values: offset too large, too many words,
1960 * and not enough words.
1962 if ((offset >= nvm->word_size) || (words > (nvm->word_size - offset)) ||
1964 hw_dbg(hw, "nvm parameter(s) out of bounds\n");
1965 return -E1000_ERR_NVM;
1968 ret_val = nvm->ops.acquire_nvm(hw);
1974 while (widx < words) {
1975 u8 write_opcode = NVM_WRITE_OPCODE_SPI;
1977 ret_val = e1000_ready_nvm_eeprom(hw);
1979 nvm->ops.release_nvm(hw);
1983 e1000_standby_nvm(hw);
1985 /* Send the WRITE ENABLE command (8 bit opcode) */
1986 e1000_shift_out_eec_bits(hw, NVM_WREN_OPCODE_SPI,
1989 e1000_standby_nvm(hw);
1992 * Some SPI eeproms use the 8th address bit embedded in the
1995 if ((nvm->address_bits == 8) && (offset >= 128))
1996 write_opcode |= NVM_A8_OPCODE_SPI;
1998 /* Send the Write command (8-bit opcode + addr) */
1999 e1000_shift_out_eec_bits(hw, write_opcode, nvm->opcode_bits);
2000 e1000_shift_out_eec_bits(hw, (u16)((offset + widx) * 2),
2003 /* Loop to allow for up to whole page write of eeprom */
2004 while (widx < words) {
2005 u16 word_out = data[widx];
2006 word_out = (word_out >> 8) | (word_out << 8);
2007 e1000_shift_out_eec_bits(hw, word_out, 16);
2010 if ((((offset + widx) * 2) % nvm->page_size) == 0) {
2011 e1000_standby_nvm(hw);
2022 * e1000e_read_mac_addr - Read device MAC address
2023 * @hw: pointer to the HW structure
2025 * Reads the device MAC address from the EEPROM and stores the value.
2026 * Since devices with two ports use the same EEPROM, we increment the
2027 * last bit in the MAC address for the second port.
2029 s32 e1000e_read_mac_addr(struct e1000_hw *hw)
2032 u16 offset, nvm_data, i;
2033 u16 mac_addr_offset = 0;
2035 if (hw->mac.type == e1000_82571) {
2036 /* Check for an alternate MAC address. An alternate MAC
2037 * address can be setup by pre-boot software and must be
2038 * treated like a permanent address and must override the
2039 * actual permanent MAC address.*/
2040 ret_val = e1000_read_nvm(hw, NVM_ALT_MAC_ADDR_PTR, 1,
2043 hw_dbg(hw, "NVM Read Error\n");
2046 if (mac_addr_offset == 0xFFFF)
2047 mac_addr_offset = 0;
2049 if (mac_addr_offset) {
2050 if (hw->bus.func == E1000_FUNC_1)
2051 mac_addr_offset += ETH_ALEN/sizeof(u16);
2053 /* make sure we have a valid mac address here
2054 * before using it */
2055 ret_val = e1000_read_nvm(hw, mac_addr_offset, 1,
2058 hw_dbg(hw, "NVM Read Error\n");
2061 if (nvm_data & 0x0001)
2062 mac_addr_offset = 0;
2065 if (mac_addr_offset)
2066 hw->dev_spec.e82571.alt_mac_addr_is_present = 1;
2069 for (i = 0; i < ETH_ALEN; i += 2) {
2070 offset = mac_addr_offset + (i >> 1);
2071 ret_val = e1000_read_nvm(hw, offset, 1, &nvm_data);
2073 hw_dbg(hw, "NVM Read Error\n");
2076 hw->mac.perm_addr[i] = (u8)(nvm_data & 0xFF);
2077 hw->mac.perm_addr[i+1] = (u8)(nvm_data >> 8);
2080 /* Flip last bit of mac address if we're on second port */
2081 if (!mac_addr_offset && hw->bus.func == E1000_FUNC_1)
2082 hw->mac.perm_addr[5] ^= 1;
2084 for (i = 0; i < ETH_ALEN; i++)
2085 hw->mac.addr[i] = hw->mac.perm_addr[i];
2091 * e1000e_validate_nvm_checksum_generic - Validate EEPROM checksum
2092 * @hw: pointer to the HW structure
2094 * Calculates the EEPROM checksum by reading/adding each word of the EEPROM
2095 * and then verifies that the sum of the EEPROM is equal to 0xBABA.
2097 s32 e1000e_validate_nvm_checksum_generic(struct e1000_hw *hw)
2103 for (i = 0; i < (NVM_CHECKSUM_REG + 1); i++) {
2104 ret_val = e1000_read_nvm(hw, i, 1, &nvm_data);
2106 hw_dbg(hw, "NVM Read Error\n");
2109 checksum += nvm_data;
2112 if (checksum != (u16) NVM_SUM) {
2113 hw_dbg(hw, "NVM Checksum Invalid\n");
2114 return -E1000_ERR_NVM;
2121 * e1000e_update_nvm_checksum_generic - Update EEPROM checksum
2122 * @hw: pointer to the HW structure
2124 * Updates the EEPROM checksum by reading/adding each word of the EEPROM
2125 * up to the checksum. Then calculates the EEPROM checksum and writes the
2126 * value to the EEPROM.
2128 s32 e1000e_update_nvm_checksum_generic(struct e1000_hw *hw)
2134 for (i = 0; i < NVM_CHECKSUM_REG; i++) {
2135 ret_val = e1000_read_nvm(hw, i, 1, &nvm_data);
2137 hw_dbg(hw, "NVM Read Error while updating checksum.\n");
2140 checksum += nvm_data;
2142 checksum = (u16) NVM_SUM - checksum;
2143 ret_val = e1000_write_nvm(hw, NVM_CHECKSUM_REG, 1, &checksum);
2145 hw_dbg(hw, "NVM Write Error while updating checksum.\n");
2151 * e1000e_reload_nvm - Reloads EEPROM
2152 * @hw: pointer to the HW structure
2154 * Reloads the EEPROM by setting the "Reinitialize from EEPROM" bit in the
2155 * extended control register.
2157 void e1000e_reload_nvm(struct e1000_hw *hw)
2162 ctrl_ext = er32(CTRL_EXT);
2163 ctrl_ext |= E1000_CTRL_EXT_EE_RST;
2164 ew32(CTRL_EXT, ctrl_ext);
2169 * e1000_calculate_checksum - Calculate checksum for buffer
2170 * @buffer: pointer to EEPROM
2171 * @length: size of EEPROM to calculate a checksum for
2173 * Calculates the checksum for some buffer on a specified length. The
2174 * checksum calculated is returned.
2176 static u8 e1000_calculate_checksum(u8 *buffer, u32 length)
2184 for (i = 0; i < length; i++)
2187 return (u8) (0 - sum);
2191 * e1000_mng_enable_host_if - Checks host interface is enabled
2192 * @hw: pointer to the HW structure
2194 * Returns E1000_success upon success, else E1000_ERR_HOST_INTERFACE_COMMAND
2196 * This function checks whether the HOST IF is enabled for command operation
2197 * and also checks whether the previous command is completed. It busy waits
2198 * in case of previous command is not completed.
2200 static s32 e1000_mng_enable_host_if(struct e1000_hw *hw)
2205 /* Check that the host interface is enabled. */
2207 if ((hicr & E1000_HICR_EN) == 0) {
2208 hw_dbg(hw, "E1000_HOST_EN bit disabled.\n");
2209 return -E1000_ERR_HOST_INTERFACE_COMMAND;
2211 /* check the previous command is completed */
2212 for (i = 0; i < E1000_MNG_DHCP_COMMAND_TIMEOUT; i++) {
2214 if (!(hicr & E1000_HICR_C))
2219 if (i == E1000_MNG_DHCP_COMMAND_TIMEOUT) {
2220 hw_dbg(hw, "Previous command timeout failed .\n");
2221 return -E1000_ERR_HOST_INTERFACE_COMMAND;
2228 * e1000e_check_mng_mode - check management mode
2229 * @hw: pointer to the HW structure
2231 * Reads the firmware semaphore register and returns true (>0) if
2232 * manageability is enabled, else false (0).
2234 bool e1000e_check_mng_mode(struct e1000_hw *hw)
2236 u32 fwsm = er32(FWSM);
2238 return (fwsm & E1000_FWSM_MODE_MASK) == hw->mac.ops.mng_mode_enab;
2242 * e1000e_enable_tx_pkt_filtering - Enable packet filtering on Tx
2243 * @hw: pointer to the HW structure
2245 * Enables packet filtering on transmit packets if manageability is enabled
2246 * and host interface is enabled.
2248 bool e1000e_enable_tx_pkt_filtering(struct e1000_hw *hw)
2250 struct e1000_host_mng_dhcp_cookie *hdr = &hw->mng_cookie;
2251 u32 *buffer = (u32 *)&hw->mng_cookie;
2253 s32 ret_val, hdr_csum, csum;
2256 /* No manageability, no filtering */
2257 if (!e1000e_check_mng_mode(hw)) {
2258 hw->mac.tx_pkt_filtering = 0;
2263 * If we can't read from the host interface for whatever
2264 * reason, disable filtering.
2266 ret_val = e1000_mng_enable_host_if(hw);
2268 hw->mac.tx_pkt_filtering = 0;
2272 /* Read in the header. Length and offset are in dwords. */
2273 len = E1000_MNG_DHCP_COOKIE_LENGTH >> 2;
2274 offset = E1000_MNG_DHCP_COOKIE_OFFSET >> 2;
2275 for (i = 0; i < len; i++)
2276 *(buffer + i) = E1000_READ_REG_ARRAY(hw, E1000_HOST_IF, offset + i);
2277 hdr_csum = hdr->checksum;
2279 csum = e1000_calculate_checksum((u8 *)hdr,
2280 E1000_MNG_DHCP_COOKIE_LENGTH);
2282 * If either the checksums or signature don't match, then
2283 * the cookie area isn't considered valid, in which case we
2284 * take the safe route of assuming Tx filtering is enabled.
2286 if ((hdr_csum != csum) || (hdr->signature != E1000_IAMT_SIGNATURE)) {
2287 hw->mac.tx_pkt_filtering = 1;
2291 /* Cookie area is valid, make the final check for filtering. */
2292 if (!(hdr->status & E1000_MNG_DHCP_COOKIE_STATUS_PARSING)) {
2293 hw->mac.tx_pkt_filtering = 0;
2297 hw->mac.tx_pkt_filtering = 1;
2302 * e1000_mng_write_cmd_header - Writes manageability command header
2303 * @hw: pointer to the HW structure
2304 * @hdr: pointer to the host interface command header
2306 * Writes the command header after does the checksum calculation.
2308 static s32 e1000_mng_write_cmd_header(struct e1000_hw *hw,
2309 struct e1000_host_mng_command_header *hdr)
2311 u16 i, length = sizeof(struct e1000_host_mng_command_header);
2313 /* Write the whole command header structure with new checksum. */
2315 hdr->checksum = e1000_calculate_checksum((u8 *)hdr, length);
2318 /* Write the relevant command block into the ram area. */
2319 for (i = 0; i < length; i++) {
2320 E1000_WRITE_REG_ARRAY(hw, E1000_HOST_IF, i,
2321 *((u32 *) hdr + i));
2329 * e1000_mng_host_if_write - Writes to the manageability host interface
2330 * @hw: pointer to the HW structure
2331 * @buffer: pointer to the host interface buffer
2332 * @length: size of the buffer
2333 * @offset: location in the buffer to write to
2334 * @sum: sum of the data (not checksum)
2336 * This function writes the buffer content at the offset given on the host if.
2337 * It also does alignment considerations to do the writes in most efficient
2338 * way. Also fills up the sum of the buffer in *buffer parameter.
2340 static s32 e1000_mng_host_if_write(struct e1000_hw *hw, u8 *buffer,
2341 u16 length, u16 offset, u8 *sum)
2344 u8 *bufptr = buffer;
2346 u16 remaining, i, j, prev_bytes;
2348 /* sum = only sum of the data and it is not checksum */
2350 if (length == 0 || offset + length > E1000_HI_MAX_MNG_DATA_LENGTH)
2351 return -E1000_ERR_PARAM;
2354 prev_bytes = offset & 0x3;
2358 data = E1000_READ_REG_ARRAY(hw, E1000_HOST_IF, offset);
2359 for (j = prev_bytes; j < sizeof(u32); j++) {
2360 *(tmp + j) = *bufptr++;
2363 E1000_WRITE_REG_ARRAY(hw, E1000_HOST_IF, offset, data);
2364 length -= j - prev_bytes;
2368 remaining = length & 0x3;
2369 length -= remaining;
2371 /* Calculate length in DWORDs */
2375 * The device driver writes the relevant command block into the
2378 for (i = 0; i < length; i++) {
2379 for (j = 0; j < sizeof(u32); j++) {
2380 *(tmp + j) = *bufptr++;
2384 E1000_WRITE_REG_ARRAY(hw, E1000_HOST_IF, offset + i, data);
2387 for (j = 0; j < sizeof(u32); j++) {
2389 *(tmp + j) = *bufptr++;
2395 E1000_WRITE_REG_ARRAY(hw, E1000_HOST_IF, offset + i, data);
2402 * e1000e_mng_write_dhcp_info - Writes DHCP info to host interface
2403 * @hw: pointer to the HW structure
2404 * @buffer: pointer to the host interface
2405 * @length: size of the buffer
2407 * Writes the DHCP information to the host interface.
2409 s32 e1000e_mng_write_dhcp_info(struct e1000_hw *hw, u8 *buffer, u16 length)
2411 struct e1000_host_mng_command_header hdr;
2415 hdr.command_id = E1000_MNG_DHCP_TX_PAYLOAD_CMD;
2416 hdr.command_length = length;
2421 /* Enable the host interface */
2422 ret_val = e1000_mng_enable_host_if(hw);
2426 /* Populate the host interface with the contents of "buffer". */
2427 ret_val = e1000_mng_host_if_write(hw, buffer, length,
2428 sizeof(hdr), &(hdr.checksum));
2432 /* Write the manageability command header */
2433 ret_val = e1000_mng_write_cmd_header(hw, &hdr);
2437 /* Tell the ARC a new command is pending. */
2439 ew32(HICR, hicr | E1000_HICR_C);
2445 * e1000e_enable_mng_pass_thru - Enable processing of ARP's
2446 * @hw: pointer to the HW structure
2448 * Verifies the hardware needs to allow ARPs to be processed by the host.
2450 bool e1000e_enable_mng_pass_thru(struct e1000_hw *hw)
2458 if (!(manc & E1000_MANC_RCV_TCO_EN) ||
2459 !(manc & E1000_MANC_EN_MAC_ADDR_FILTER))
2462 if (hw->mac.arc_subsystem_valid) {
2464 factps = er32(FACTPS);
2466 if (!(factps & E1000_FACTPS_MNGCG) &&
2467 ((fwsm & E1000_FWSM_MODE_MASK) ==
2468 (e1000_mng_mode_pt << E1000_FWSM_MODE_SHIFT))) {
2473 if ((manc & E1000_MANC_SMBUS_EN) &&
2474 !(manc & E1000_MANC_ASF_EN)) {
2483 s32 e1000e_read_part_num(struct e1000_hw *hw, u32 *part_num)
2488 ret_val = e1000_read_nvm(hw, NVM_PBA_OFFSET_0, 1, &nvm_data);
2490 hw_dbg(hw, "NVM Read Error\n");
2493 *part_num = (u32)(nvm_data << 16);
2495 ret_val = e1000_read_nvm(hw, NVM_PBA_OFFSET_1, 1, &nvm_data);
2497 hw_dbg(hw, "NVM Read Error\n");
2500 *part_num |= nvm_data;