1 /*******************************************************************************
3 Intel PRO/1000 Linux driver
4 Copyright(c) 1999 - 2008 Intel Corporation.
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
23 Linux NICS <linux.nics@intel.com>
24 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
25 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
27 *******************************************************************************/
30 * 80003ES2LAN Gigabit Ethernet Controller (Copper)
31 * 80003ES2LAN Gigabit Ethernet Controller (Serdes)
34 #include <linux/netdevice.h>
35 #include <linux/ethtool.h>
36 #include <linux/delay.h>
37 #include <linux/pci.h>
41 #define E1000_KMRNCTRLSTA_OFFSET_FIFO_CTRL 0x00
42 #define E1000_KMRNCTRLSTA_OFFSET_INB_CTRL 0x02
43 #define E1000_KMRNCTRLSTA_OFFSET_HD_CTRL 0x10
45 #define E1000_KMRNCTRLSTA_FIFO_CTRL_RX_BYPASS 0x0008
46 #define E1000_KMRNCTRLSTA_FIFO_CTRL_TX_BYPASS 0x0800
47 #define E1000_KMRNCTRLSTA_INB_CTRL_DIS_PADDING 0x0010
49 #define E1000_KMRNCTRLSTA_HD_CTRL_10_100_DEFAULT 0x0004
50 #define E1000_KMRNCTRLSTA_HD_CTRL_1000_DEFAULT 0x0000
52 #define E1000_TCTL_EXT_GCEX_MASK 0x000FFC00 /* Gigabit Carry Extend Padding */
53 #define DEFAULT_TCTL_EXT_GCEX_80003ES2LAN 0x00010000
55 #define DEFAULT_TIPG_IPGT_1000_80003ES2LAN 0x8
56 #define DEFAULT_TIPG_IPGT_10_100_80003ES2LAN 0x9
58 /* GG82563 PHY Specific Status Register (Page 0, Register 16 */
59 #define GG82563_PSCR_POLARITY_REVERSAL_DISABLE 0x0002 /* 1=Reversal Disab. */
60 #define GG82563_PSCR_CROSSOVER_MODE_MASK 0x0060
61 #define GG82563_PSCR_CROSSOVER_MODE_MDI 0x0000 /* 00=Manual MDI */
62 #define GG82563_PSCR_CROSSOVER_MODE_MDIX 0x0020 /* 01=Manual MDIX */
63 #define GG82563_PSCR_CROSSOVER_MODE_AUTO 0x0060 /* 11=Auto crossover */
65 /* PHY Specific Control Register 2 (Page 0, Register 26) */
66 #define GG82563_PSCR2_REVERSE_AUTO_NEG 0x2000
67 /* 1=Reverse Auto-Negotiation */
69 /* MAC Specific Control Register (Page 2, Register 21) */
70 /* Tx clock speed for Link Down and 1000BASE-T for the following speeds */
71 #define GG82563_MSCR_TX_CLK_MASK 0x0007
72 #define GG82563_MSCR_TX_CLK_10MBPS_2_5 0x0004
73 #define GG82563_MSCR_TX_CLK_100MBPS_25 0x0005
74 #define GG82563_MSCR_TX_CLK_1000MBPS_25 0x0007
76 #define GG82563_MSCR_ASSERT_CRS_ON_TX 0x0010 /* 1=Assert */
78 /* DSP Distance Register (Page 5, Register 26) */
79 #define GG82563_DSPD_CABLE_LENGTH 0x0007 /* 0 = <50M
85 /* Kumeran Mode Control Register (Page 193, Register 16) */
86 #define GG82563_KMCR_PASS_FALSE_CARRIER 0x0800
88 /* Power Management Control Register (Page 193, Register 20) */
89 #define GG82563_PMCR_ENABLE_ELECTRICAL_IDLE 0x0001
90 /* 1=Enable SERDES Electrical Idle */
92 /* In-Band Control Register (Page 194, Register 18) */
93 #define GG82563_ICR_DIS_PADDING 0x0010 /* Disable Padding */
96 * A table for the GG82563 cable length where the range is defined
97 * with a lower bound at "index" and the upper bound at
100 static const u16 e1000_gg82563_cable_length_table[] =
101 { 0, 60, 115, 150, 150, 60, 115, 150, 180, 180, 0xFF };
103 static s32 e1000_setup_copper_link_80003es2lan(struct e1000_hw *hw);
104 static s32 e1000_acquire_swfw_sync_80003es2lan(struct e1000_hw *hw, u16 mask);
105 static void e1000_release_swfw_sync_80003es2lan(struct e1000_hw *hw, u16 mask);
106 static void e1000_initialize_hw_bits_80003es2lan(struct e1000_hw *hw);
107 static void e1000_clear_hw_cntrs_80003es2lan(struct e1000_hw *hw);
108 static s32 e1000_cfg_kmrn_1000_80003es2lan(struct e1000_hw *hw);
109 static s32 e1000_cfg_kmrn_10_100_80003es2lan(struct e1000_hw *hw, u16 duplex);
112 * e1000_init_phy_params_80003es2lan - Init ESB2 PHY func ptrs.
113 * @hw: pointer to the HW structure
115 * This is a function pointer entry point called by the api module.
117 static s32 e1000_init_phy_params_80003es2lan(struct e1000_hw *hw)
119 struct e1000_phy_info *phy = &hw->phy;
122 if (hw->phy.media_type != e1000_media_type_copper) {
123 phy->type = e1000_phy_none;
128 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT;
129 phy->reset_delay_us = 100;
130 phy->type = e1000_phy_gg82563;
132 /* This can only be done after all function pointers are setup. */
133 ret_val = e1000e_get_phy_id(hw);
136 if (phy->id != GG82563_E_PHY_ID)
137 return -E1000_ERR_PHY;
143 * e1000_init_nvm_params_80003es2lan - Init ESB2 NVM func ptrs.
144 * @hw: pointer to the HW structure
146 * This is a function pointer entry point called by the api module.
148 static s32 e1000_init_nvm_params_80003es2lan(struct e1000_hw *hw)
150 struct e1000_nvm_info *nvm = &hw->nvm;
151 u32 eecd = er32(EECD);
154 nvm->opcode_bits = 8;
156 switch (nvm->override) {
157 case e1000_nvm_override_spi_large:
159 nvm->address_bits = 16;
161 case e1000_nvm_override_spi_small:
163 nvm->address_bits = 8;
166 nvm->page_size = eecd & E1000_EECD_ADDR_BITS ? 32 : 8;
167 nvm->address_bits = eecd & E1000_EECD_ADDR_BITS ? 16 : 8;
171 nvm->type = e1000_nvm_eeprom_spi;
173 size = (u16)((eecd & E1000_EECD_SIZE_EX_MASK) >>
174 E1000_EECD_SIZE_EX_SHIFT);
177 * Added to a constant, "size" becomes the left-shift value
178 * for setting word_size.
180 size += NVM_WORD_SIZE_BASE_SHIFT;
181 nvm->word_size = 1 << size;
187 * e1000_init_mac_params_80003es2lan - Init ESB2 MAC func ptrs.
188 * @hw: pointer to the HW structure
190 * This is a function pointer entry point called by the api module.
192 static s32 e1000_init_mac_params_80003es2lan(struct e1000_adapter *adapter)
194 struct e1000_hw *hw = &adapter->hw;
195 struct e1000_mac_info *mac = &hw->mac;
196 struct e1000_mac_operations *func = &mac->ops;
199 switch (adapter->pdev->device) {
200 case E1000_DEV_ID_80003ES2LAN_SERDES_DPT:
201 hw->phy.media_type = e1000_media_type_internal_serdes;
204 hw->phy.media_type = e1000_media_type_copper;
208 /* Set mta register count */
209 mac->mta_reg_count = 128;
210 /* Set rar entry count */
211 mac->rar_entry_count = E1000_RAR_ENTRIES;
212 /* Set if manageability features are enabled. */
213 mac->arc_subsystem_valid = (er32(FWSM) & E1000_FWSM_MODE_MASK) ? 1 : 0;
216 switch (hw->phy.media_type) {
217 case e1000_media_type_copper:
218 func->setup_physical_interface = e1000_setup_copper_link_80003es2lan;
219 func->check_for_link = e1000e_check_for_copper_link;
221 case e1000_media_type_fiber:
222 func->setup_physical_interface = e1000e_setup_fiber_serdes_link;
223 func->check_for_link = e1000e_check_for_fiber_link;
225 case e1000_media_type_internal_serdes:
226 func->setup_physical_interface = e1000e_setup_fiber_serdes_link;
227 func->check_for_link = e1000e_check_for_serdes_link;
230 return -E1000_ERR_CONFIG;
237 static s32 e1000_get_invariants_80003es2lan(struct e1000_adapter *adapter)
239 struct e1000_hw *hw = &adapter->hw;
242 rc = e1000_init_mac_params_80003es2lan(adapter);
246 rc = e1000_init_nvm_params_80003es2lan(hw);
250 rc = e1000_init_phy_params_80003es2lan(hw);
258 * e1000_acquire_phy_80003es2lan - Acquire rights to access PHY
259 * @hw: pointer to the HW structure
261 * A wrapper to acquire access rights to the correct PHY. This is a
262 * function pointer entry point called by the api module.
264 static s32 e1000_acquire_phy_80003es2lan(struct e1000_hw *hw)
268 mask = hw->bus.func ? E1000_SWFW_PHY1_SM : E1000_SWFW_PHY0_SM;
270 return e1000_acquire_swfw_sync_80003es2lan(hw, mask);
274 * e1000_release_phy_80003es2lan - Release rights to access PHY
275 * @hw: pointer to the HW structure
277 * A wrapper to release access rights to the correct PHY. This is a
278 * function pointer entry point called by the api module.
280 static void e1000_release_phy_80003es2lan(struct e1000_hw *hw)
284 mask = hw->bus.func ? E1000_SWFW_PHY1_SM : E1000_SWFW_PHY0_SM;
285 e1000_release_swfw_sync_80003es2lan(hw, mask);
289 * e1000_acquire_nvm_80003es2lan - Acquire rights to access NVM
290 * @hw: pointer to the HW structure
292 * Acquire the semaphore to access the EEPROM. This is a function
293 * pointer entry point called by the api module.
295 static s32 e1000_acquire_nvm_80003es2lan(struct e1000_hw *hw)
299 ret_val = e1000_acquire_swfw_sync_80003es2lan(hw, E1000_SWFW_EEP_SM);
303 ret_val = e1000e_acquire_nvm(hw);
306 e1000_release_swfw_sync_80003es2lan(hw, E1000_SWFW_EEP_SM);
312 * e1000_release_nvm_80003es2lan - Relinquish rights to access NVM
313 * @hw: pointer to the HW structure
315 * Release the semaphore used to access the EEPROM. This is a
316 * function pointer entry point called by the api module.
318 static void e1000_release_nvm_80003es2lan(struct e1000_hw *hw)
320 e1000e_release_nvm(hw);
321 e1000_release_swfw_sync_80003es2lan(hw, E1000_SWFW_EEP_SM);
325 * e1000_acquire_swfw_sync_80003es2lan - Acquire SW/FW semaphore
326 * @hw: pointer to the HW structure
327 * @mask: specifies which semaphore to acquire
329 * Acquire the SW/FW semaphore to access the PHY or NVM. The mask
330 * will also specify which port we're acquiring the lock for.
332 static s32 e1000_acquire_swfw_sync_80003es2lan(struct e1000_hw *hw, u16 mask)
336 u32 fwmask = mask << 16;
340 while (i < timeout) {
341 if (e1000e_get_hw_semaphore(hw))
342 return -E1000_ERR_SWFW_SYNC;
344 swfw_sync = er32(SW_FW_SYNC);
345 if (!(swfw_sync & (fwmask | swmask)))
349 * Firmware currently using resource (fwmask)
350 * or other software thread using resource (swmask)
352 e1000e_put_hw_semaphore(hw);
359 "Driver can't access resource, SW_FW_SYNC timeout.\n");
360 return -E1000_ERR_SWFW_SYNC;
364 ew32(SW_FW_SYNC, swfw_sync);
366 e1000e_put_hw_semaphore(hw);
372 * e1000_release_swfw_sync_80003es2lan - Release SW/FW semaphore
373 * @hw: pointer to the HW structure
374 * @mask: specifies which semaphore to acquire
376 * Release the SW/FW semaphore used to access the PHY or NVM. The mask
377 * will also specify which port we're releasing the lock for.
379 static void e1000_release_swfw_sync_80003es2lan(struct e1000_hw *hw, u16 mask)
383 while (e1000e_get_hw_semaphore(hw) != 0);
386 swfw_sync = er32(SW_FW_SYNC);
388 ew32(SW_FW_SYNC, swfw_sync);
390 e1000e_put_hw_semaphore(hw);
394 * e1000_read_phy_reg_gg82563_80003es2lan - Read GG82563 PHY register
395 * @hw: pointer to the HW structure
396 * @offset: offset of the register to read
397 * @data: pointer to the data returned from the operation
399 * Read the GG82563 PHY register. This is a function pointer entry
400 * point called by the api module.
402 static s32 e1000_read_phy_reg_gg82563_80003es2lan(struct e1000_hw *hw,
403 u32 offset, u16 *data)
409 /* Select Configuration Page */
410 if ((offset & MAX_PHY_REG_ADDRESS) < GG82563_MIN_ALT_REG)
411 page_select = GG82563_PHY_PAGE_SELECT;
414 * Use Alternative Page Select register to access
415 * registers 30 and 31
417 page_select = GG82563_PHY_PAGE_SELECT_ALT;
419 temp = (u16)((u16)offset >> GG82563_PAGE_SHIFT);
420 ret_val = e1000e_write_phy_reg_m88(hw, page_select, temp);
425 * The "ready" bit in the MDIC register may be incorrectly set
426 * before the device has completed the "Page Select" MDI
427 * transaction. So we wait 200us after each MDI command...
431 /* ...and verify the command was successful. */
432 ret_val = e1000e_read_phy_reg_m88(hw, page_select, &temp);
434 if (((u16)offset >> GG82563_PAGE_SHIFT) != temp) {
435 ret_val = -E1000_ERR_PHY;
441 ret_val = e1000e_read_phy_reg_m88(hw,
442 MAX_PHY_REG_ADDRESS & offset,
451 * e1000_write_phy_reg_gg82563_80003es2lan - Write GG82563 PHY register
452 * @hw: pointer to the HW structure
453 * @offset: offset of the register to read
454 * @data: value to write to the register
456 * Write to the GG82563 PHY register. This is a function pointer entry
457 * point called by the api module.
459 static s32 e1000_write_phy_reg_gg82563_80003es2lan(struct e1000_hw *hw,
460 u32 offset, u16 data)
466 /* Select Configuration Page */
467 if ((offset & MAX_PHY_REG_ADDRESS) < GG82563_MIN_ALT_REG)
468 page_select = GG82563_PHY_PAGE_SELECT;
471 * Use Alternative Page Select register to access
472 * registers 30 and 31
474 page_select = GG82563_PHY_PAGE_SELECT_ALT;
476 temp = (u16)((u16)offset >> GG82563_PAGE_SHIFT);
477 ret_val = e1000e_write_phy_reg_m88(hw, page_select, temp);
483 * The "ready" bit in the MDIC register may be incorrectly set
484 * before the device has completed the "Page Select" MDI
485 * transaction. So we wait 200us after each MDI command...
489 /* ...and verify the command was successful. */
490 ret_val = e1000e_read_phy_reg_m88(hw, page_select, &temp);
492 if (((u16)offset >> GG82563_PAGE_SHIFT) != temp)
493 return -E1000_ERR_PHY;
497 ret_val = e1000e_write_phy_reg_m88(hw,
498 MAX_PHY_REG_ADDRESS & offset,
507 * e1000_write_nvm_80003es2lan - Write to ESB2 NVM
508 * @hw: pointer to the HW structure
509 * @offset: offset of the register to read
510 * @words: number of words to write
511 * @data: buffer of data to write to the NVM
513 * Write "words" of data to the ESB2 NVM. This is a function
514 * pointer entry point called by the api module.
516 static s32 e1000_write_nvm_80003es2lan(struct e1000_hw *hw, u16 offset,
517 u16 words, u16 *data)
519 return e1000e_write_nvm_spi(hw, offset, words, data);
523 * e1000_get_cfg_done_80003es2lan - Wait for configuration to complete
524 * @hw: pointer to the HW structure
526 * Wait a specific amount of time for manageability processes to complete.
527 * This is a function pointer entry point called by the phy module.
529 static s32 e1000_get_cfg_done_80003es2lan(struct e1000_hw *hw)
531 s32 timeout = PHY_CFG_TIMEOUT;
532 u32 mask = E1000_NVM_CFG_DONE_PORT_0;
534 if (hw->bus.func == 1)
535 mask = E1000_NVM_CFG_DONE_PORT_1;
538 if (er32(EEMNGCTL) & mask)
544 hw_dbg(hw, "MNG configuration cycle has not completed.\n");
545 return -E1000_ERR_RESET;
552 * e1000_phy_force_speed_duplex_80003es2lan - Force PHY speed and duplex
553 * @hw: pointer to the HW structure
555 * Force the speed and duplex settings onto the PHY. This is a
556 * function pointer entry point called by the phy module.
558 static s32 e1000_phy_force_speed_duplex_80003es2lan(struct e1000_hw *hw)
565 * Clear Auto-Crossover to force MDI manually. M88E1000 requires MDI
566 * forced whenever speed and duplex are forced.
568 ret_val = e1e_rphy(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
572 phy_data &= ~GG82563_PSCR_CROSSOVER_MODE_AUTO;
573 ret_val = e1e_wphy(hw, GG82563_PHY_SPEC_CTRL, phy_data);
577 hw_dbg(hw, "GG82563 PSCR: %X\n", phy_data);
579 ret_val = e1e_rphy(hw, PHY_CONTROL, &phy_data);
583 e1000e_phy_force_speed_duplex_setup(hw, &phy_data);
585 /* Reset the phy to commit changes. */
586 phy_data |= MII_CR_RESET;
588 ret_val = e1e_wphy(hw, PHY_CONTROL, phy_data);
594 if (hw->phy.autoneg_wait_to_complete) {
595 hw_dbg(hw, "Waiting for forced speed/duplex link "
596 "on GG82563 phy.\n");
598 ret_val = e1000e_phy_has_link_generic(hw, PHY_FORCE_LIMIT,
605 * We didn't get link.
606 * Reset the DSP and cross our fingers.
608 ret_val = e1000e_phy_reset_dsp(hw);
614 ret_val = e1000e_phy_has_link_generic(hw, PHY_FORCE_LIMIT,
620 ret_val = e1e_rphy(hw, GG82563_PHY_MAC_SPEC_CTRL, &phy_data);
625 * Resetting the phy means we need to verify the TX_CLK corresponds
626 * to the link speed. 10Mbps -> 2.5MHz, else 25MHz.
628 phy_data &= ~GG82563_MSCR_TX_CLK_MASK;
629 if (hw->mac.forced_speed_duplex & E1000_ALL_10_SPEED)
630 phy_data |= GG82563_MSCR_TX_CLK_10MBPS_2_5;
632 phy_data |= GG82563_MSCR_TX_CLK_100MBPS_25;
635 * In addition, we must re-enable CRS on Tx for both half and full
638 phy_data |= GG82563_MSCR_ASSERT_CRS_ON_TX;
639 ret_val = e1e_wphy(hw, GG82563_PHY_MAC_SPEC_CTRL, phy_data);
645 * e1000_get_cable_length_80003es2lan - Set approximate cable length
646 * @hw: pointer to the HW structure
648 * Find the approximate cable length as measured by the GG82563 PHY.
649 * This is a function pointer entry point called by the phy module.
651 static s32 e1000_get_cable_length_80003es2lan(struct e1000_hw *hw)
653 struct e1000_phy_info *phy = &hw->phy;
658 ret_val = e1e_rphy(hw, GG82563_PHY_DSP_DISTANCE, &phy_data);
662 index = phy_data & GG82563_DSPD_CABLE_LENGTH;
663 phy->min_cable_length = e1000_gg82563_cable_length_table[index];
664 phy->max_cable_length = e1000_gg82563_cable_length_table[index+5];
666 phy->cable_length = (phy->min_cable_length + phy->max_cable_length) / 2;
672 * e1000_get_link_up_info_80003es2lan - Report speed and duplex
673 * @hw: pointer to the HW structure
674 * @speed: pointer to speed buffer
675 * @duplex: pointer to duplex buffer
677 * Retrieve the current speed and duplex configuration.
678 * This is a function pointer entry point called by the api module.
680 static s32 e1000_get_link_up_info_80003es2lan(struct e1000_hw *hw, u16 *speed,
685 if (hw->phy.media_type == e1000_media_type_copper) {
686 ret_val = e1000e_get_speed_and_duplex_copper(hw,
691 if (*speed == SPEED_1000)
692 ret_val = e1000_cfg_kmrn_1000_80003es2lan(hw);
694 ret_val = e1000_cfg_kmrn_10_100_80003es2lan(hw,
697 ret_val = e1000e_get_speed_and_duplex_fiber_serdes(hw,
706 * e1000_reset_hw_80003es2lan - Reset the ESB2 controller
707 * @hw: pointer to the HW structure
709 * Perform a global reset to the ESB2 controller.
710 * This is a function pointer entry point called by the api module.
712 static s32 e1000_reset_hw_80003es2lan(struct e1000_hw *hw)
719 * Prevent the PCI-E bus from sticking if there is no TLP connection
720 * on the last TLP read/write transaction when MAC is reset.
722 ret_val = e1000e_disable_pcie_master(hw);
724 hw_dbg(hw, "PCI-E Master disable polling has failed.\n");
726 hw_dbg(hw, "Masking off all interrupts\n");
727 ew32(IMC, 0xffffffff);
730 ew32(TCTL, E1000_TCTL_PSP);
737 hw_dbg(hw, "Issuing a global reset to MAC\n");
738 ew32(CTRL, ctrl | E1000_CTRL_RST);
740 ret_val = e1000e_get_auto_rd_done(hw);
742 /* We don't want to continue accessing MAC registers. */
745 /* Clear any pending interrupt events. */
746 ew32(IMC, 0xffffffff);
753 * e1000_init_hw_80003es2lan - Initialize the ESB2 controller
754 * @hw: pointer to the HW structure
756 * Initialize the hw bits, LED, VFTA, MTA, link and hw counters.
757 * This is a function pointer entry point called by the api module.
759 static s32 e1000_init_hw_80003es2lan(struct e1000_hw *hw)
761 struct e1000_mac_info *mac = &hw->mac;
766 e1000_initialize_hw_bits_80003es2lan(hw);
768 /* Initialize identification LED */
769 ret_val = e1000e_id_led_init(hw);
771 hw_dbg(hw, "Error initializing identification LED\n");
775 /* Disabling VLAN filtering */
776 hw_dbg(hw, "Initializing the IEEE VLAN\n");
777 e1000e_clear_vfta(hw);
779 /* Setup the receive address. */
780 e1000e_init_rx_addrs(hw, mac->rar_entry_count);
782 /* Zero out the Multicast HASH table */
783 hw_dbg(hw, "Zeroing the MTA\n");
784 for (i = 0; i < mac->mta_reg_count; i++)
785 E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, 0);
787 /* Setup link and flow control */
788 ret_val = e1000e_setup_link(hw);
790 /* Set the transmit descriptor write-back policy */
791 reg_data = er32(TXDCTL);
792 reg_data = (reg_data & ~E1000_TXDCTL_WTHRESH) |
793 E1000_TXDCTL_FULL_TX_DESC_WB | E1000_TXDCTL_COUNT_DESC;
794 ew32(TXDCTL, reg_data);
796 /* ...for both queues. */
797 reg_data = er32(TXDCTL1);
798 reg_data = (reg_data & ~E1000_TXDCTL_WTHRESH) |
799 E1000_TXDCTL_FULL_TX_DESC_WB | E1000_TXDCTL_COUNT_DESC;
800 ew32(TXDCTL1, reg_data);
802 /* Enable retransmit on late collisions */
803 reg_data = er32(TCTL);
804 reg_data |= E1000_TCTL_RTLC;
805 ew32(TCTL, reg_data);
807 /* Configure Gigabit Carry Extend Padding */
808 reg_data = er32(TCTL_EXT);
809 reg_data &= ~E1000_TCTL_EXT_GCEX_MASK;
810 reg_data |= DEFAULT_TCTL_EXT_GCEX_80003ES2LAN;
811 ew32(TCTL_EXT, reg_data);
813 /* Configure Transmit Inter-Packet Gap */
814 reg_data = er32(TIPG);
815 reg_data &= ~E1000_TIPG_IPGT_MASK;
816 reg_data |= DEFAULT_TIPG_IPGT_1000_80003ES2LAN;
817 ew32(TIPG, reg_data);
819 reg_data = E1000_READ_REG_ARRAY(hw, E1000_FFLT, 0x0001);
820 reg_data &= ~0x00100000;
821 E1000_WRITE_REG_ARRAY(hw, E1000_FFLT, 0x0001, reg_data);
824 * Clear all of the statistics registers (clear on read). It is
825 * important that we do this after we have tried to establish link
826 * because the symbol error count will increment wildly if there
829 e1000_clear_hw_cntrs_80003es2lan(hw);
835 * e1000_initialize_hw_bits_80003es2lan - Init hw bits of ESB2
836 * @hw: pointer to the HW structure
838 * Initializes required hardware-dependent bits needed for normal operation.
840 static void e1000_initialize_hw_bits_80003es2lan(struct e1000_hw *hw)
844 /* Transmit Descriptor Control 0 */
849 /* Transmit Descriptor Control 1 */
854 /* Transmit Arbitration Control 0 */
856 reg &= ~(0xF << 27); /* 30:27 */
857 if (hw->phy.media_type != e1000_media_type_copper)
861 /* Transmit Arbitration Control 1 */
863 if (er32(TCTL) & E1000_TCTL_MULR)
871 * e1000_copper_link_setup_gg82563_80003es2lan - Configure GG82563 Link
872 * @hw: pointer to the HW structure
874 * Setup some GG82563 PHY registers for obtaining link
876 static s32 e1000_copper_link_setup_gg82563_80003es2lan(struct e1000_hw *hw)
878 struct e1000_phy_info *phy = &hw->phy;
883 ret_val = e1e_rphy(hw, GG82563_PHY_MAC_SPEC_CTRL,
888 data |= GG82563_MSCR_ASSERT_CRS_ON_TX;
889 /* Use 25MHz for both link down and 1000Base-T for Tx clock. */
890 data |= GG82563_MSCR_TX_CLK_1000MBPS_25;
892 ret_val = e1e_wphy(hw, GG82563_PHY_MAC_SPEC_CTRL,
899 * MDI/MDI-X = 0 (default)
900 * 0 - Auto for all speeds
903 * 3 - Auto for 1000Base-T only (MDI-X for 10/100Base-T modes)
905 ret_val = e1e_rphy(hw, GG82563_PHY_SPEC_CTRL, &data);
909 data &= ~GG82563_PSCR_CROSSOVER_MODE_MASK;
913 data |= GG82563_PSCR_CROSSOVER_MODE_MDI;
916 data |= GG82563_PSCR_CROSSOVER_MODE_MDIX;
920 data |= GG82563_PSCR_CROSSOVER_MODE_AUTO;
926 * disable_polarity_correction = 0 (default)
927 * Automatic Correction for Reversed Cable Polarity
931 data &= ~GG82563_PSCR_POLARITY_REVERSAL_DISABLE;
932 if (phy->disable_polarity_correction)
933 data |= GG82563_PSCR_POLARITY_REVERSAL_DISABLE;
935 ret_val = e1e_wphy(hw, GG82563_PHY_SPEC_CTRL, data);
939 /* SW Reset the PHY so all changes take effect */
940 ret_val = e1000e_commit_phy(hw);
942 hw_dbg(hw, "Error Resetting the PHY\n");
946 /* Bypass Rx and Tx FIFO's */
947 ret_val = e1000e_write_kmrn_reg(hw, E1000_KMRNCTRLSTA_OFFSET_FIFO_CTRL,
948 E1000_KMRNCTRLSTA_FIFO_CTRL_RX_BYPASS |
949 E1000_KMRNCTRLSTA_FIFO_CTRL_TX_BYPASS);
953 ret_val = e1e_rphy(hw, GG82563_PHY_SPEC_CTRL_2, &data);
957 data &= ~GG82563_PSCR2_REVERSE_AUTO_NEG;
958 ret_val = e1e_wphy(hw, GG82563_PHY_SPEC_CTRL_2, data);
962 ctrl_ext = er32(CTRL_EXT);
963 ctrl_ext &= ~(E1000_CTRL_EXT_LINK_MODE_MASK);
964 ew32(CTRL_EXT, ctrl_ext);
966 ret_val = e1e_rphy(hw, GG82563_PHY_PWR_MGMT_CTRL, &data);
971 * Do not init these registers when the HW is in IAMT mode, since the
972 * firmware will have already initialized them. We only initialize
973 * them if the HW is not in IAMT mode.
975 if (!e1000e_check_mng_mode(hw)) {
976 /* Enable Electrical Idle on the PHY */
977 data |= GG82563_PMCR_ENABLE_ELECTRICAL_IDLE;
978 ret_val = e1e_wphy(hw, GG82563_PHY_PWR_MGMT_CTRL, data);
982 ret_val = e1e_rphy(hw, GG82563_PHY_KMRN_MODE_CTRL, &data);
986 data &= ~GG82563_KMCR_PASS_FALSE_CARRIER;
987 ret_val = e1e_wphy(hw, GG82563_PHY_KMRN_MODE_CTRL, data);
993 * Workaround: Disable padding in Kumeran interface in the MAC
994 * and in the PHY to avoid CRC errors.
996 ret_val = e1e_rphy(hw, GG82563_PHY_INBAND_CTRL, &data);
1000 data |= GG82563_ICR_DIS_PADDING;
1001 ret_val = e1e_wphy(hw, GG82563_PHY_INBAND_CTRL, data);
1009 * e1000_setup_copper_link_80003es2lan - Setup Copper Link for ESB2
1010 * @hw: pointer to the HW structure
1012 * Essentially a wrapper for setting up all things "copper" related.
1013 * This is a function pointer entry point called by the mac module.
1015 static s32 e1000_setup_copper_link_80003es2lan(struct e1000_hw *hw)
1022 ctrl |= E1000_CTRL_SLU;
1023 ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
1027 * Set the mac to wait the maximum time between each
1028 * iteration and increase the max iterations when
1029 * polling the phy; this fixes erroneous timeouts at 10Mbps.
1031 ret_val = e1000e_write_kmrn_reg(hw, GG82563_REG(0x34, 4), 0xFFFF);
1034 ret_val = e1000e_read_kmrn_reg(hw, GG82563_REG(0x34, 9), ®_data);
1038 ret_val = e1000e_write_kmrn_reg(hw, GG82563_REG(0x34, 9), reg_data);
1041 ret_val = e1000e_read_kmrn_reg(hw,
1042 E1000_KMRNCTRLSTA_OFFSET_INB_CTRL,
1046 reg_data |= E1000_KMRNCTRLSTA_INB_CTRL_DIS_PADDING;
1047 ret_val = e1000e_write_kmrn_reg(hw, E1000_KMRNCTRLSTA_OFFSET_INB_CTRL,
1052 ret_val = e1000_copper_link_setup_gg82563_80003es2lan(hw);
1056 ret_val = e1000e_setup_copper_link(hw);
1062 * e1000_cfg_kmrn_10_100_80003es2lan - Apply "quirks" for 10/100 operation
1063 * @hw: pointer to the HW structure
1064 * @duplex: current duplex setting
1066 * Configure the KMRN interface by applying last minute quirks for
1069 static s32 e1000_cfg_kmrn_10_100_80003es2lan(struct e1000_hw *hw, u16 duplex)
1075 reg_data = E1000_KMRNCTRLSTA_HD_CTRL_10_100_DEFAULT;
1076 ret_val = e1000e_write_kmrn_reg(hw, E1000_KMRNCTRLSTA_OFFSET_HD_CTRL,
1081 /* Configure Transmit Inter-Packet Gap */
1083 tipg &= ~E1000_TIPG_IPGT_MASK;
1084 tipg |= DEFAULT_TIPG_IPGT_10_100_80003ES2LAN;
1087 ret_val = e1e_rphy(hw, GG82563_PHY_KMRN_MODE_CTRL, ®_data);
1091 if (duplex == HALF_DUPLEX)
1092 reg_data |= GG82563_KMCR_PASS_FALSE_CARRIER;
1094 reg_data &= ~GG82563_KMCR_PASS_FALSE_CARRIER;
1096 ret_val = e1e_wphy(hw, GG82563_PHY_KMRN_MODE_CTRL, reg_data);
1102 * e1000_cfg_kmrn_1000_80003es2lan - Apply "quirks" for gigabit operation
1103 * @hw: pointer to the HW structure
1105 * Configure the KMRN interface by applying last minute quirks for
1106 * gigabit operation.
1108 static s32 e1000_cfg_kmrn_1000_80003es2lan(struct e1000_hw *hw)
1114 reg_data = E1000_KMRNCTRLSTA_HD_CTRL_1000_DEFAULT;
1115 ret_val = e1000e_write_kmrn_reg(hw, E1000_KMRNCTRLSTA_OFFSET_HD_CTRL,
1120 /* Configure Transmit Inter-Packet Gap */
1122 tipg &= ~E1000_TIPG_IPGT_MASK;
1123 tipg |= DEFAULT_TIPG_IPGT_1000_80003ES2LAN;
1126 ret_val = e1e_rphy(hw, GG82563_PHY_KMRN_MODE_CTRL, ®_data);
1130 reg_data &= ~GG82563_KMCR_PASS_FALSE_CARRIER;
1131 ret_val = e1e_wphy(hw, GG82563_PHY_KMRN_MODE_CTRL, reg_data);
1137 * e1000_clear_hw_cntrs_80003es2lan - Clear device specific hardware counters
1138 * @hw: pointer to the HW structure
1140 * Clears the hardware counters by reading the counter registers.
1142 static void e1000_clear_hw_cntrs_80003es2lan(struct e1000_hw *hw)
1146 e1000e_clear_hw_cntrs_base(hw);
1149 temp = er32(PRC127);
1150 temp = er32(PRC255);
1151 temp = er32(PRC511);
1152 temp = er32(PRC1023);
1153 temp = er32(PRC1522);
1155 temp = er32(PTC127);
1156 temp = er32(PTC255);
1157 temp = er32(PTC511);
1158 temp = er32(PTC1023);
1159 temp = er32(PTC1522);
1161 temp = er32(ALGNERRC);
1162 temp = er32(RXERRC);
1164 temp = er32(CEXTERR);
1166 temp = er32(TSCTFC);
1168 temp = er32(MGTPRC);
1169 temp = er32(MGTPDC);
1170 temp = er32(MGTPTC);
1173 temp = er32(ICRXOC);
1175 temp = er32(ICRXPTC);
1176 temp = er32(ICRXATC);
1177 temp = er32(ICTXPTC);
1178 temp = er32(ICTXATC);
1179 temp = er32(ICTXQEC);
1180 temp = er32(ICTXQMTC);
1181 temp = er32(ICRXDMTC);
1184 static struct e1000_mac_operations es2_mac_ops = {
1185 .mng_mode_enab = E1000_MNG_IAMT_MODE << E1000_FWSM_MODE_SHIFT,
1186 /* check_for_link dependent on media type */
1187 .cleanup_led = e1000e_cleanup_led_generic,
1188 .clear_hw_cntrs = e1000_clear_hw_cntrs_80003es2lan,
1189 .get_bus_info = e1000e_get_bus_info_pcie,
1190 .get_link_up_info = e1000_get_link_up_info_80003es2lan,
1191 .led_on = e1000e_led_on_generic,
1192 .led_off = e1000e_led_off_generic,
1193 .update_mc_addr_list = e1000e_update_mc_addr_list_generic,
1194 .reset_hw = e1000_reset_hw_80003es2lan,
1195 .init_hw = e1000_init_hw_80003es2lan,
1196 .setup_link = e1000e_setup_link,
1197 /* setup_physical_interface dependent on media type */
1200 static struct e1000_phy_operations es2_phy_ops = {
1201 .acquire_phy = e1000_acquire_phy_80003es2lan,
1202 .check_reset_block = e1000e_check_reset_block_generic,
1203 .commit_phy = e1000e_phy_sw_reset,
1204 .force_speed_duplex = e1000_phy_force_speed_duplex_80003es2lan,
1205 .get_cfg_done = e1000_get_cfg_done_80003es2lan,
1206 .get_cable_length = e1000_get_cable_length_80003es2lan,
1207 .get_phy_info = e1000e_get_phy_info_m88,
1208 .read_phy_reg = e1000_read_phy_reg_gg82563_80003es2lan,
1209 .release_phy = e1000_release_phy_80003es2lan,
1210 .reset_phy = e1000e_phy_hw_reset_generic,
1211 .set_d0_lplu_state = NULL,
1212 .set_d3_lplu_state = e1000e_set_d3_lplu_state,
1213 .write_phy_reg = e1000_write_phy_reg_gg82563_80003es2lan,
1216 static struct e1000_nvm_operations es2_nvm_ops = {
1217 .acquire_nvm = e1000_acquire_nvm_80003es2lan,
1218 .read_nvm = e1000e_read_nvm_eerd,
1219 .release_nvm = e1000_release_nvm_80003es2lan,
1220 .update_nvm = e1000e_update_nvm_checksum_generic,
1221 .valid_led_default = e1000e_valid_led_default,
1222 .validate_nvm = e1000e_validate_nvm_checksum_generic,
1223 .write_nvm = e1000_write_nvm_80003es2lan,
1226 struct e1000_info e1000_es2_info = {
1227 .mac = e1000_80003es2lan,
1228 .flags = FLAG_HAS_HW_VLAN_FILTER
1229 | FLAG_HAS_JUMBO_FRAMES
1230 | FLAG_HAS_STATS_PTC_PRC
1232 | FLAG_APME_IN_CTRL3
1233 | FLAG_RX_CSUM_ENABLED
1234 | FLAG_HAS_CTRLEXT_ON_LOAD
1235 | FLAG_HAS_STATS_ICR_ICT
1236 | FLAG_RX_NEEDS_RESTART /* errata */
1237 | FLAG_TARC_SET_BIT_ZERO /* errata */
1238 | FLAG_APME_CHECK_PORT_B
1239 | FLAG_DISABLE_FC_PAUSE_TIME /* errata */
1240 | FLAG_TIPG_MEDIUM_FOR_80003ESLAN,
1242 .get_invariants = e1000_get_invariants_80003es2lan,
1243 .mac_ops = &es2_mac_ops,
1244 .phy_ops = &es2_phy_ops,
1245 .nvm_ops = &es2_nvm_ops,