1 /*******************************************************************************
4 Copyright(c) 1999 - 2005 Intel Corporation. All rights reserved.
6 This program is free software; you can redistribute it and/or modify it
7 under the terms of the GNU General Public License as published by the Free
8 Software Foundation; either version 2 of the License, or (at your option)
11 This program is distributed in the hope that it will be useful, but WITHOUT
12 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
16 You should have received a copy of the GNU General Public License along with
17 this program; if not, write to the Free Software Foundation, Inc., 59
18 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
20 The full GNU General Public License is included in this distribution in the
24 Linux NICS <linux.nics@intel.com>
25 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
27 *******************************************************************************/
30 * Structures, enums, and macros for the MAC
36 #include "e1000_osdep.h"
39 /* Forward declarations of structures used by the shared code */
41 struct e1000_hw_stats;
43 /* Enumerated types specific to the e1000 hardware */
44 /* Media Access Controlers */
68 e1000_eeprom_uninitialized = 0,
70 e1000_eeprom_microwire,
72 e1000_eeprom_none, /* No NVM support */
73 e1000_num_eeprom_types
78 e1000_media_type_copper = 0,
79 e1000_media_type_fiber = 1,
80 e1000_media_type_internal_serdes = 2,
89 } e1000_speed_duplex_type;
91 /* Flow Control Settings */
94 e1000_fc_rx_pause = 1,
95 e1000_fc_tx_pause = 2,
97 e1000_fc_default = 0xFF
102 e1000_bus_type_unknown = 0,
105 e1000_bus_type_pci_express,
106 e1000_bus_type_reserved
111 e1000_bus_speed_unknown = 0,
117 e1000_bus_speed_2500,
118 e1000_bus_speed_reserved
123 e1000_bus_width_unknown = 0,
126 e1000_bus_width_pciex_1,
127 e1000_bus_width_pciex_2,
128 e1000_bus_width_pciex_4,
129 e1000_bus_width_reserved
132 /* PHY status info structure and supporting enums */
134 e1000_cable_length_50 = 0,
135 e1000_cable_length_50_80,
136 e1000_cable_length_80_110,
137 e1000_cable_length_110_140,
138 e1000_cable_length_140,
139 e1000_cable_length_undefined = 0xFF
140 } e1000_cable_length;
143 e1000_gg_cable_length_60 = 0,
144 e1000_gg_cable_length_60_115 = 1,
145 e1000_gg_cable_length_115_150 = 2,
146 e1000_gg_cable_length_150 = 4
147 } e1000_gg_cable_length;
150 e1000_igp_cable_length_10 = 10,
151 e1000_igp_cable_length_20 = 20,
152 e1000_igp_cable_length_30 = 30,
153 e1000_igp_cable_length_40 = 40,
154 e1000_igp_cable_length_50 = 50,
155 e1000_igp_cable_length_60 = 60,
156 e1000_igp_cable_length_70 = 70,
157 e1000_igp_cable_length_80 = 80,
158 e1000_igp_cable_length_90 = 90,
159 e1000_igp_cable_length_100 = 100,
160 e1000_igp_cable_length_110 = 110,
161 e1000_igp_cable_length_115 = 115,
162 e1000_igp_cable_length_120 = 120,
163 e1000_igp_cable_length_130 = 130,
164 e1000_igp_cable_length_140 = 140,
165 e1000_igp_cable_length_150 = 150,
166 e1000_igp_cable_length_160 = 160,
167 e1000_igp_cable_length_170 = 170,
168 e1000_igp_cable_length_180 = 180
169 } e1000_igp_cable_length;
172 e1000_10bt_ext_dist_enable_normal = 0,
173 e1000_10bt_ext_dist_enable_lower,
174 e1000_10bt_ext_dist_enable_undefined = 0xFF
175 } e1000_10bt_ext_dist_enable;
178 e1000_rev_polarity_normal = 0,
179 e1000_rev_polarity_reversed,
180 e1000_rev_polarity_undefined = 0xFF
181 } e1000_rev_polarity;
184 e1000_downshift_normal = 0,
185 e1000_downshift_activated,
186 e1000_downshift_undefined = 0xFF
190 e1000_smart_speed_default = 0,
191 e1000_smart_speed_on,
192 e1000_smart_speed_off
196 e1000_polarity_reversal_enabled = 0,
197 e1000_polarity_reversal_disabled,
198 e1000_polarity_reversal_undefined = 0xFF
199 } e1000_polarity_reversal;
202 e1000_auto_x_mode_manual_mdi = 0,
203 e1000_auto_x_mode_manual_mdix,
204 e1000_auto_x_mode_auto1,
205 e1000_auto_x_mode_auto2,
206 e1000_auto_x_mode_undefined = 0xFF
210 e1000_1000t_rx_status_not_ok = 0,
211 e1000_1000t_rx_status_ok,
212 e1000_1000t_rx_status_undefined = 0xFF
213 } e1000_1000t_rx_status;
220 e1000_phy_undefined = 0xFF
224 e1000_ms_hw_default = 0,
225 e1000_ms_force_master,
226 e1000_ms_force_slave,
231 e1000_ffe_config_enabled = 0,
232 e1000_ffe_config_active,
233 e1000_ffe_config_blocked
237 e1000_dsp_config_disabled = 0,
238 e1000_dsp_config_enabled,
239 e1000_dsp_config_activated,
240 e1000_dsp_config_undefined = 0xFF
243 struct e1000_phy_info {
244 e1000_cable_length cable_length;
245 e1000_10bt_ext_dist_enable extended_10bt_distance;
246 e1000_rev_polarity cable_polarity;
247 e1000_downshift downshift;
248 e1000_polarity_reversal polarity_correction;
249 e1000_auto_x_mode mdix_mode;
250 e1000_1000t_rx_status local_rx;
251 e1000_1000t_rx_status remote_rx;
254 struct e1000_phy_stats {
255 uint32_t idle_errors;
256 uint32_t receive_errors;
259 struct e1000_eeprom_info {
260 e1000_eeprom_type type;
262 uint16_t opcode_bits;
263 uint16_t address_bits;
270 /* Flex ASF Information */
271 #define E1000_HOST_IF_MAX_SIZE 2048
274 e1000_byte_align = 0,
275 e1000_word_align = 1,
276 e1000_dword_align = 2
282 #define E1000_SUCCESS 0
283 #define E1000_ERR_EEPROM 1
284 #define E1000_ERR_PHY 2
285 #define E1000_ERR_CONFIG 3
286 #define E1000_ERR_PARAM 4
287 #define E1000_ERR_MAC_TYPE 5
288 #define E1000_ERR_PHY_TYPE 6
289 #define E1000_ERR_RESET 9
290 #define E1000_ERR_MASTER_REQUESTS_PENDING 10
291 #define E1000_ERR_HOST_INTERFACE_COMMAND 11
292 #define E1000_BLK_PHY_RESET 12
293 #define E1000_ERR_SWFW_SYNC 13
295 /* Function prototypes */
297 int32_t e1000_reset_hw(struct e1000_hw *hw);
298 int32_t e1000_init_hw(struct e1000_hw *hw);
299 int32_t e1000_set_mac_type(struct e1000_hw *hw);
300 void e1000_set_media_type(struct e1000_hw *hw);
302 /* Link Configuration */
303 int32_t e1000_setup_link(struct e1000_hw *hw);
304 int32_t e1000_phy_setup_autoneg(struct e1000_hw *hw);
305 void e1000_config_collision_dist(struct e1000_hw *hw);
306 int32_t e1000_check_for_link(struct e1000_hw *hw);
307 int32_t e1000_get_speed_and_duplex(struct e1000_hw *hw, uint16_t * speed, uint16_t * duplex);
308 int32_t e1000_force_mac_fc(struct e1000_hw *hw);
311 int32_t e1000_read_phy_reg(struct e1000_hw *hw, uint32_t reg_addr, uint16_t *phy_data);
312 int32_t e1000_write_phy_reg(struct e1000_hw *hw, uint32_t reg_addr, uint16_t data);
313 int32_t e1000_phy_hw_reset(struct e1000_hw *hw);
314 int32_t e1000_phy_reset(struct e1000_hw *hw);
315 int32_t e1000_phy_get_info(struct e1000_hw *hw, struct e1000_phy_info *phy_info);
316 int32_t e1000_validate_mdi_setting(struct e1000_hw *hw);
317 int32_t e1000_read_kmrn_reg(struct e1000_hw *hw, uint32_t reg_addr, uint16_t *data);
318 int32_t e1000_write_kmrn_reg(struct e1000_hw *hw, uint32_t reg_addr, uint16_t data);
320 /* EEPROM Functions */
321 int32_t e1000_init_eeprom_params(struct e1000_hw *hw);
323 /* MNG HOST IF functions */
324 uint32_t e1000_enable_mng_pass_thru(struct e1000_hw *hw);
326 #define E1000_MNG_DHCP_TX_PAYLOAD_CMD 64
327 #define E1000_HI_MAX_MNG_DATA_LENGTH 0x6F8 /* Host Interface data length */
329 #define E1000_MNG_DHCP_COMMAND_TIMEOUT 10 /* Time in ms to process MNG command */
330 #define E1000_MNG_DHCP_COOKIE_OFFSET 0x6F0 /* Cookie offset */
331 #define E1000_MNG_DHCP_COOKIE_LENGTH 0x10 /* Cookie length */
332 #define E1000_MNG_IAMT_MODE 0x3
333 #define E1000_IAMT_SIGNATURE 0x544D4149 /* Intel(R) Active Management Technology signature */
335 #define E1000_MNG_DHCP_COOKIE_STATUS_PARSING_SUPPORT 0x1 /* DHCP parsing enabled */
336 #define E1000_MNG_DHCP_COOKIE_STATUS_VLAN_SUPPORT 0x2 /* DHCP parsing enabled */
337 #define E1000_VFTA_ENTRY_SHIFT 0x5
338 #define E1000_VFTA_ENTRY_MASK 0x7F
339 #define E1000_VFTA_ENTRY_BIT_SHIFT_MASK 0x1F
341 struct e1000_host_mng_command_header {
346 uint16_t command_length;
349 struct e1000_host_mng_command_info {
350 struct e1000_host_mng_command_header command_header; /* Command Head/Command Result Head has 4 bytes */
351 uint8_t command_data[E1000_HI_MAX_MNG_DATA_LENGTH]; /* Command data can length 0..0x658*/
354 struct e1000_host_mng_dhcp_cookie{
365 struct e1000_host_mng_dhcp_cookie{
377 int32_t e1000_mng_write_dhcp_info(struct e1000_hw *hw, uint8_t *buffer,
379 boolean_t e1000_check_mng_mode(struct e1000_hw *hw);
380 boolean_t e1000_enable_tx_pkt_filtering(struct e1000_hw *hw);
382 int32_t e1000_read_eeprom(struct e1000_hw *hw, uint16_t reg, uint16_t words, uint16_t *data);
383 int32_t e1000_validate_eeprom_checksum(struct e1000_hw *hw);
384 int32_t e1000_update_eeprom_checksum(struct e1000_hw *hw);
385 int32_t e1000_write_eeprom(struct e1000_hw *hw, uint16_t reg, uint16_t words, uint16_t *data);
386 int32_t e1000_read_part_num(struct e1000_hw *hw, uint32_t * part_num);
387 int32_t e1000_read_mac_addr(struct e1000_hw * hw);
388 int32_t e1000_swfw_sync_acquire(struct e1000_hw *hw, uint16_t mask);
389 void e1000_swfw_sync_release(struct e1000_hw *hw, uint16_t mask);
391 /* Filters (multicast, vlan, receive) */
392 void e1000_mc_addr_list_update(struct e1000_hw *hw, uint8_t * mc_addr_list, uint32_t mc_addr_count, uint32_t pad, uint32_t rar_used_count);
393 uint32_t e1000_hash_mc_addr(struct e1000_hw *hw, uint8_t * mc_addr);
394 void e1000_mta_set(struct e1000_hw *hw, uint32_t hash_value);
395 void e1000_rar_set(struct e1000_hw *hw, uint8_t * mc_addr, uint32_t rar_index);
396 void e1000_write_vfta(struct e1000_hw *hw, uint32_t offset, uint32_t value);
399 int32_t e1000_setup_led(struct e1000_hw *hw);
400 int32_t e1000_cleanup_led(struct e1000_hw *hw);
401 int32_t e1000_led_on(struct e1000_hw *hw);
402 int32_t e1000_led_off(struct e1000_hw *hw);
404 /* Adaptive IFS Functions */
406 /* Everything else */
407 void e1000_reset_adaptive(struct e1000_hw *hw);
408 void e1000_update_adaptive(struct e1000_hw *hw);
409 void e1000_tbi_adjust_stats(struct e1000_hw *hw, struct e1000_hw_stats *stats, uint32_t frame_len, uint8_t * mac_addr);
410 void e1000_get_bus_info(struct e1000_hw *hw);
411 void e1000_pci_set_mwi(struct e1000_hw *hw);
412 void e1000_pci_clear_mwi(struct e1000_hw *hw);
413 void e1000_read_pci_cfg(struct e1000_hw *hw, uint32_t reg, uint16_t * value);
414 void e1000_write_pci_cfg(struct e1000_hw *hw, uint32_t reg, uint16_t * value);
415 /* Port I/O is only supported on 82544 and newer */
416 uint32_t e1000_io_read(struct e1000_hw *hw, unsigned long port);
417 uint32_t e1000_read_reg_io(struct e1000_hw *hw, uint32_t offset);
418 void e1000_io_write(struct e1000_hw *hw, unsigned long port, uint32_t value);
419 void e1000_enable_pciex_master(struct e1000_hw *hw);
420 int32_t e1000_disable_pciex_master(struct e1000_hw *hw);
421 int32_t e1000_get_software_semaphore(struct e1000_hw *hw);
422 void e1000_release_software_semaphore(struct e1000_hw *hw);
423 int32_t e1000_check_phy_reset_block(struct e1000_hw *hw);
426 #define E1000_DEV_ID_82542 0x1000
427 #define E1000_DEV_ID_82543GC_FIBER 0x1001
428 #define E1000_DEV_ID_82543GC_COPPER 0x1004
429 #define E1000_DEV_ID_82544EI_COPPER 0x1008
430 #define E1000_DEV_ID_82544EI_FIBER 0x1009
431 #define E1000_DEV_ID_82544GC_COPPER 0x100C
432 #define E1000_DEV_ID_82544GC_LOM 0x100D
433 #define E1000_DEV_ID_82540EM 0x100E
434 #define E1000_DEV_ID_82540EM_LOM 0x1015
435 #define E1000_DEV_ID_82540EP_LOM 0x1016
436 #define E1000_DEV_ID_82540EP 0x1017
437 #define E1000_DEV_ID_82540EP_LP 0x101E
438 #define E1000_DEV_ID_82545EM_COPPER 0x100F
439 #define E1000_DEV_ID_82545EM_FIBER 0x1011
440 #define E1000_DEV_ID_82545GM_COPPER 0x1026
441 #define E1000_DEV_ID_82545GM_FIBER 0x1027
442 #define E1000_DEV_ID_82545GM_SERDES 0x1028
443 #define E1000_DEV_ID_82546EB_COPPER 0x1010
444 #define E1000_DEV_ID_82546EB_FIBER 0x1012
445 #define E1000_DEV_ID_82546EB_QUAD_COPPER 0x101D
446 #define E1000_DEV_ID_82541EI 0x1013
447 #define E1000_DEV_ID_82541EI_MOBILE 0x1018
448 #define E1000_DEV_ID_82541ER 0x1078
449 #define E1000_DEV_ID_82547GI 0x1075
450 #define E1000_DEV_ID_82541GI 0x1076
451 #define E1000_DEV_ID_82541GI_MOBILE 0x1077
452 #define E1000_DEV_ID_82541GI_LF 0x107C
453 #define E1000_DEV_ID_82546GB_COPPER 0x1079
454 #define E1000_DEV_ID_82546GB_FIBER 0x107A
455 #define E1000_DEV_ID_82546GB_SERDES 0x107B
456 #define E1000_DEV_ID_82546GB_PCIE 0x108A
457 #define E1000_DEV_ID_82546GB_QUAD_COPPER 0x1099
458 #define E1000_DEV_ID_82547EI 0x1019
459 #define E1000_DEV_ID_82571EB_COPPER 0x105E
460 #define E1000_DEV_ID_82571EB_FIBER 0x105F
461 #define E1000_DEV_ID_82571EB_SERDES 0x1060
462 #define E1000_DEV_ID_82572EI_COPPER 0x107D
463 #define E1000_DEV_ID_82572EI_FIBER 0x107E
464 #define E1000_DEV_ID_82572EI_SERDES 0x107F
465 #define E1000_DEV_ID_82573E 0x108B
466 #define E1000_DEV_ID_82573E_IAMT 0x108C
467 #define E1000_DEV_ID_82573L 0x109A
468 #define E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3 0x10B5
469 #define E1000_DEV_ID_80003ES2LAN_COPPER_DPT 0x1096
470 #define E1000_DEV_ID_80003ES2LAN_SERDES_DPT 0x1098
473 #define NODE_ADDRESS_SIZE 6
474 #define ETH_LENGTH_OF_ADDRESS 6
476 /* MAC decode size is 128K - This is the size of BAR0 */
477 #define MAC_DECODE_SIZE (128 * 1024)
479 #define E1000_82542_2_0_REV_ID 2
480 #define E1000_82542_2_1_REV_ID 3
481 #define E1000_REVISION_0 0
482 #define E1000_REVISION_1 1
483 #define E1000_REVISION_2 2
484 #define E1000_REVISION_3 3
487 #define SPEED_100 100
488 #define SPEED_1000 1000
489 #define HALF_DUPLEX 1
490 #define FULL_DUPLEX 2
492 /* The sizes (in bytes) of a ethernet packet */
493 #define ENET_HEADER_SIZE 14
494 #define MAXIMUM_ETHERNET_FRAME_SIZE 1518 /* With FCS */
495 #define MINIMUM_ETHERNET_FRAME_SIZE 64 /* With FCS */
496 #define ETHERNET_FCS_SIZE 4
497 #define MAXIMUM_ETHERNET_PACKET_SIZE \
498 (MAXIMUM_ETHERNET_FRAME_SIZE - ETHERNET_FCS_SIZE)
499 #define MINIMUM_ETHERNET_PACKET_SIZE \
500 (MINIMUM_ETHERNET_FRAME_SIZE - ETHERNET_FCS_SIZE)
501 #define CRC_LENGTH ETHERNET_FCS_SIZE
502 #define MAX_JUMBO_FRAME_SIZE 0x3F00
505 /* 802.1q VLAN Packet Sizes */
506 #define VLAN_TAG_SIZE 4 /* 802.3ac tag (not DMAed) */
508 /* Ethertype field values */
509 #define ETHERNET_IEEE_VLAN_TYPE 0x8100 /* 802.3ac packet */
510 #define ETHERNET_IP_TYPE 0x0800 /* IP packets */
511 #define ETHERNET_ARP_TYPE 0x0806 /* Address Resolution Protocol (ARP) */
513 /* Packet Header defines */
514 #define IP_PROTOCOL_TCP 6
515 #define IP_PROTOCOL_UDP 0x11
517 /* This defines the bits that are set in the Interrupt Mask
518 * Set/Read Register. Each bit is documented below:
519 * o RXDMT0 = Receive Descriptor Minimum Threshold hit (ring 0)
520 * o RXSEQ = Receive Sequence Error
522 #define POLL_IMS_ENABLE_MASK ( \
526 /* This defines the bits that are set in the Interrupt Mask
527 * Set/Read Register. Each bit is documented below:
528 * o RXT0 = Receiver Timer Interrupt (ring 0)
529 * o TXDW = Transmit Descriptor Written Back
530 * o RXDMT0 = Receive Descriptor Minimum Threshold hit (ring 0)
531 * o RXSEQ = Receive Sequence Error
532 * o LSC = Link Status Change
534 #define IMS_ENABLE_MASK ( \
542 /* Number of high/low register pairs in the RAR. The RAR (Receive Address
543 * Registers) holds the directed and multicast addresses that we monitor. We
544 * reserve one of these spots for our directed address, allowing us room for
545 * E1000_RAR_ENTRIES - 1 multicast addresses.
547 #define E1000_RAR_ENTRIES 15
549 #define MIN_NUMBER_OF_DESCRIPTORS 8
550 #define MAX_NUMBER_OF_DESCRIPTORS 0xFFF8
552 /* Receive Descriptor */
553 struct e1000_rx_desc {
554 uint64_t buffer_addr; /* Address of the descriptor's data buffer */
555 uint16_t length; /* Length of data DMAed into data buffer */
556 uint16_t csum; /* Packet checksum */
557 uint8_t status; /* Descriptor status */
558 uint8_t errors; /* Descriptor Errors */
562 /* Receive Descriptor - Extended */
563 union e1000_rx_desc_extended {
565 uint64_t buffer_addr;
570 uint32_t mrq; /* Multiple Rx Queues */
572 uint32_t rss; /* RSS Hash */
574 uint16_t ip_id; /* IP id */
575 uint16_t csum; /* Packet Checksum */
580 uint32_t status_error; /* ext status/error */
582 uint16_t vlan; /* VLAN tag */
584 } wb; /* writeback */
587 #define MAX_PS_BUFFERS 4
588 /* Receive Descriptor - Packet Split */
589 union e1000_rx_desc_packet_split {
591 /* one buffer for protocol header(s), three data buffers */
592 uint64_t buffer_addr[MAX_PS_BUFFERS];
596 uint32_t mrq; /* Multiple Rx Queues */
598 uint32_t rss; /* RSS Hash */
600 uint16_t ip_id; /* IP id */
601 uint16_t csum; /* Packet Checksum */
606 uint32_t status_error; /* ext status/error */
607 uint16_t length0; /* length of buffer 0 */
608 uint16_t vlan; /* VLAN tag */
611 uint16_t header_status;
612 uint16_t length[3]; /* length of buffers 1-3 */
615 } wb; /* writeback */
618 /* Receive Decriptor bit definitions */
619 #define E1000_RXD_STAT_DD 0x01 /* Descriptor Done */
620 #define E1000_RXD_STAT_EOP 0x02 /* End of Packet */
621 #define E1000_RXD_STAT_IXSM 0x04 /* Ignore checksum */
622 #define E1000_RXD_STAT_VP 0x08 /* IEEE VLAN Packet */
623 #define E1000_RXD_STAT_UDPCS 0x10 /* UDP xsum caculated */
624 #define E1000_RXD_STAT_TCPCS 0x20 /* TCP xsum calculated */
625 #define E1000_RXD_STAT_IPCS 0x40 /* IP xsum calculated */
626 #define E1000_RXD_STAT_PIF 0x80 /* passed in-exact filter */
627 #define E1000_RXD_STAT_IPIDV 0x200 /* IP identification valid */
628 #define E1000_RXD_STAT_UDPV 0x400 /* Valid UDP checksum */
629 #define E1000_RXD_STAT_ACK 0x8000 /* ACK Packet indication */
630 #define E1000_RXD_ERR_CE 0x01 /* CRC Error */
631 #define E1000_RXD_ERR_SE 0x02 /* Symbol Error */
632 #define E1000_RXD_ERR_SEQ 0x04 /* Sequence Error */
633 #define E1000_RXD_ERR_CXE 0x10 /* Carrier Extension Error */
634 #define E1000_RXD_ERR_TCPE 0x20 /* TCP/UDP Checksum Error */
635 #define E1000_RXD_ERR_IPE 0x40 /* IP Checksum Error */
636 #define E1000_RXD_ERR_RXE 0x80 /* Rx Data Error */
637 #define E1000_RXD_SPC_VLAN_MASK 0x0FFF /* VLAN ID is in lower 12 bits */
638 #define E1000_RXD_SPC_PRI_MASK 0xE000 /* Priority is in upper 3 bits */
639 #define E1000_RXD_SPC_PRI_SHIFT 13
640 #define E1000_RXD_SPC_CFI_MASK 0x1000 /* CFI is bit 12 */
641 #define E1000_RXD_SPC_CFI_SHIFT 12
643 #define E1000_RXDEXT_STATERR_CE 0x01000000
644 #define E1000_RXDEXT_STATERR_SE 0x02000000
645 #define E1000_RXDEXT_STATERR_SEQ 0x04000000
646 #define E1000_RXDEXT_STATERR_CXE 0x10000000
647 #define E1000_RXDEXT_STATERR_TCPE 0x20000000
648 #define E1000_RXDEXT_STATERR_IPE 0x40000000
649 #define E1000_RXDEXT_STATERR_RXE 0x80000000
651 #define E1000_RXDPS_HDRSTAT_HDRSP 0x00008000
652 #define E1000_RXDPS_HDRSTAT_HDRLEN_MASK 0x000003FF
654 /* mask to determine if packets should be dropped due to frame errors */
655 #define E1000_RXD_ERR_FRAME_ERR_MASK ( \
658 E1000_RXD_ERR_SEQ | \
659 E1000_RXD_ERR_CXE | \
663 /* Same mask, but for extended and packet split descriptors */
664 #define E1000_RXDEXT_ERR_FRAME_ERR_MASK ( \
665 E1000_RXDEXT_STATERR_CE | \
666 E1000_RXDEXT_STATERR_SE | \
667 E1000_RXDEXT_STATERR_SEQ | \
668 E1000_RXDEXT_STATERR_CXE | \
669 E1000_RXDEXT_STATERR_RXE)
671 /* Transmit Descriptor */
672 struct e1000_tx_desc {
673 uint64_t buffer_addr; /* Address of the descriptor's data buffer */
677 uint16_t length; /* Data buffer length */
678 uint8_t cso; /* Checksum offset */
679 uint8_t cmd; /* Descriptor control */
685 uint8_t status; /* Descriptor status */
686 uint8_t css; /* Checksum start */
692 /* Transmit Descriptor bit definitions */
693 #define E1000_TXD_DTYP_D 0x00100000 /* Data Descriptor */
694 #define E1000_TXD_DTYP_C 0x00000000 /* Context Descriptor */
695 #define E1000_TXD_POPTS_IXSM 0x01 /* Insert IP checksum */
696 #define E1000_TXD_POPTS_TXSM 0x02 /* Insert TCP/UDP checksum */
697 #define E1000_TXD_CMD_EOP 0x01000000 /* End of Packet */
698 #define E1000_TXD_CMD_IFCS 0x02000000 /* Insert FCS (Ethernet CRC) */
699 #define E1000_TXD_CMD_IC 0x04000000 /* Insert Checksum */
700 #define E1000_TXD_CMD_RS 0x08000000 /* Report Status */
701 #define E1000_TXD_CMD_RPS 0x10000000 /* Report Packet Sent */
702 #define E1000_TXD_CMD_DEXT 0x20000000 /* Descriptor extension (0 = legacy) */
703 #define E1000_TXD_CMD_VLE 0x40000000 /* Add VLAN tag */
704 #define E1000_TXD_CMD_IDE 0x80000000 /* Enable Tidv register */
705 #define E1000_TXD_STAT_DD 0x00000001 /* Descriptor Done */
706 #define E1000_TXD_STAT_EC 0x00000002 /* Excess Collisions */
707 #define E1000_TXD_STAT_LC 0x00000004 /* Late Collisions */
708 #define E1000_TXD_STAT_TU 0x00000008 /* Transmit underrun */
709 #define E1000_TXD_CMD_TCP 0x01000000 /* TCP packet */
710 #define E1000_TXD_CMD_IP 0x02000000 /* IP packet */
711 #define E1000_TXD_CMD_TSE 0x04000000 /* TCP Seg enable */
712 #define E1000_TXD_STAT_TC 0x00000004 /* Tx Underrun */
714 /* Offload Context Descriptor */
715 struct e1000_context_desc {
719 uint8_t ipcss; /* IP checksum start */
720 uint8_t ipcso; /* IP checksum offset */
721 uint16_t ipcse; /* IP checksum end */
727 uint8_t tucss; /* TCP checksum start */
728 uint8_t tucso; /* TCP checksum offset */
729 uint16_t tucse; /* TCP checksum end */
732 uint32_t cmd_and_length; /* */
736 uint8_t status; /* Descriptor status */
737 uint8_t hdr_len; /* Header length */
738 uint16_t mss; /* Maximum segment size */
743 /* Offload data descriptor */
744 struct e1000_data_desc {
745 uint64_t buffer_addr; /* Address of the descriptor's buffer address */
749 uint16_t length; /* Data buffer length */
750 uint8_t typ_len_ext; /* */
757 uint8_t status; /* Descriptor status */
758 uint8_t popts; /* Packet Options */
759 uint16_t special; /* */
765 #define E1000_NUM_UNICAST 16 /* Unicast filter entries */
766 #define E1000_MC_TBL_SIZE 128 /* Multicast Filter Table (4096 bits) */
767 #define E1000_VLAN_FILTER_TBL_SIZE 128 /* VLAN Filter Table (4096 bits) */
770 /* Receive Address Register */
772 volatile uint32_t low; /* receive address low */
773 volatile uint32_t high; /* receive address high */
776 /* Number of entries in the Multicast Table Array (MTA). */
777 #define E1000_NUM_MTA_REGISTERS 128
779 /* IPv4 Address Table Entry */
780 struct e1000_ipv4_at_entry {
781 volatile uint32_t ipv4_addr; /* IP Address (RW) */
782 volatile uint32_t reserved;
785 /* Four wakeup IP addresses are supported */
786 #define E1000_WAKEUP_IP_ADDRESS_COUNT_MAX 4
787 #define E1000_IP4AT_SIZE E1000_WAKEUP_IP_ADDRESS_COUNT_MAX
788 #define E1000_IP6AT_SIZE 1
790 /* IPv6 Address Table Entry */
791 struct e1000_ipv6_at_entry {
792 volatile uint8_t ipv6_addr[16];
795 /* Flexible Filter Length Table Entry */
796 struct e1000_fflt_entry {
797 volatile uint32_t length; /* Flexible Filter Length (RW) */
798 volatile uint32_t reserved;
801 /* Flexible Filter Mask Table Entry */
802 struct e1000_ffmt_entry {
803 volatile uint32_t mask; /* Flexible Filter Mask (RW) */
804 volatile uint32_t reserved;
807 /* Flexible Filter Value Table Entry */
808 struct e1000_ffvt_entry {
809 volatile uint32_t value; /* Flexible Filter Value (RW) */
810 volatile uint32_t reserved;
813 /* Four Flexible Filters are supported */
814 #define E1000_FLEXIBLE_FILTER_COUNT_MAX 4
816 /* Each Flexible Filter is at most 128 (0x80) bytes in length */
817 #define E1000_FLEXIBLE_FILTER_SIZE_MAX 128
819 #define E1000_FFLT_SIZE E1000_FLEXIBLE_FILTER_COUNT_MAX
820 #define E1000_FFMT_SIZE E1000_FLEXIBLE_FILTER_SIZE_MAX
821 #define E1000_FFVT_SIZE E1000_FLEXIBLE_FILTER_SIZE_MAX
823 #define E1000_DISABLE_SERDES_LOOPBACK 0x0400
825 /* Register Set. (82543, 82544)
827 * Registers are defined to be 32 bits and should be accessed as 32 bit values.
828 * These registers are physically located on the NIC, but are mapped into the
829 * host memory address space.
831 * RW - register is both readable and writable
832 * RO - register is read only
833 * WO - register is write only
834 * R/clr - register is read only and is cleared when read
837 #define E1000_CTRL 0x00000 /* Device Control - RW */
838 #define E1000_CTRL_DUP 0x00004 /* Device Control Duplicate (Shadow) - RW */
839 #define E1000_STATUS 0x00008 /* Device Status - RO */
840 #define E1000_EECD 0x00010 /* EEPROM/Flash Control - RW */
841 #define E1000_EERD 0x00014 /* EEPROM Read - RW */
842 #define E1000_CTRL_EXT 0x00018 /* Extended Device Control - RW */
843 #define E1000_FLA 0x0001C /* Flash Access - RW */
844 #define E1000_MDIC 0x00020 /* MDI Control - RW */
845 #define E1000_SCTL 0x00024 /* SerDes Control - RW */
846 #define E1000_FCAL 0x00028 /* Flow Control Address Low - RW */
847 #define E1000_FCAH 0x0002C /* Flow Control Address High -RW */
848 #define E1000_FCT 0x00030 /* Flow Control Type - RW */
849 #define E1000_VET 0x00038 /* VLAN Ether Type - RW */
850 #define E1000_ICR 0x000C0 /* Interrupt Cause Read - R/clr */
851 #define E1000_ITR 0x000C4 /* Interrupt Throttling Rate - RW */
852 #define E1000_ICS 0x000C8 /* Interrupt Cause Set - WO */
853 #define E1000_IMS 0x000D0 /* Interrupt Mask Set - RW */
854 #define E1000_IMC 0x000D8 /* Interrupt Mask Clear - WO */
855 #define E1000_IAM 0x000E0 /* Interrupt Acknowledge Auto Mask */
856 #define E1000_RCTL 0x00100 /* RX Control - RW */
857 #define E1000_RDTR1 0x02820 /* RX Delay Timer (1) - RW */
858 #define E1000_RDBAL1 0x02900 /* RX Descriptor Base Address Low (1) - RW */
859 #define E1000_RDBAH1 0x02904 /* RX Descriptor Base Address High (1) - RW */
860 #define E1000_RDLEN1 0x02908 /* RX Descriptor Length (1) - RW */
861 #define E1000_RDH1 0x02910 /* RX Descriptor Head (1) - RW */
862 #define E1000_RDT1 0x02918 /* RX Descriptor Tail (1) - RW */
863 #define E1000_FCTTV 0x00170 /* Flow Control Transmit Timer Value - RW */
864 #define E1000_TXCW 0x00178 /* TX Configuration Word - RW */
865 #define E1000_RXCW 0x00180 /* RX Configuration Word - RO */
866 #define E1000_TCTL 0x00400 /* TX Control - RW */
867 #define E1000_TCTL_EXT 0x00404 /* Extended TX Control - RW */
868 #define E1000_TIPG 0x00410 /* TX Inter-packet gap -RW */
869 #define E1000_TBT 0x00448 /* TX Burst Timer - RW */
870 #define E1000_AIT 0x00458 /* Adaptive Interframe Spacing Throttle - RW */
871 #define E1000_LEDCTL 0x00E00 /* LED Control - RW */
872 #define E1000_EXTCNF_CTRL 0x00F00 /* Extended Configuration Control */
873 #define E1000_EXTCNF_SIZE 0x00F08 /* Extended Configuration Size */
874 #define E1000_PBA 0x01000 /* Packet Buffer Allocation - RW */
875 #define E1000_PBS 0x01008 /* Packet Buffer Size */
876 #define E1000_EEMNGCTL 0x01010 /* MNG EEprom Control */
877 #define E1000_FLASH_UPDATES 1000
878 #define E1000_EEARBC 0x01024 /* EEPROM Auto Read Bus Control */
879 #define E1000_FLASHT 0x01028 /* FLASH Timer Register */
880 #define E1000_EEWR 0x0102C /* EEPROM Write Register - RW */
881 #define E1000_FLSWCTL 0x01030 /* FLASH control register */
882 #define E1000_FLSWDATA 0x01034 /* FLASH data register */
883 #define E1000_FLSWCNT 0x01038 /* FLASH Access Counter */
884 #define E1000_FLOP 0x0103C /* FLASH Opcode Register */
885 #define E1000_ERT 0x02008 /* Early Rx Threshold - RW */
886 #define E1000_FCRTL 0x02160 /* Flow Control Receive Threshold Low - RW */
887 #define E1000_FCRTH 0x02168 /* Flow Control Receive Threshold High - RW */
888 #define E1000_PSRCTL 0x02170 /* Packet Split Receive Control - RW */
889 #define E1000_RDBAL 0x02800 /* RX Descriptor Base Address Low - RW */
890 #define E1000_RDBAH 0x02804 /* RX Descriptor Base Address High - RW */
891 #define E1000_RDLEN 0x02808 /* RX Descriptor Length - RW */
892 #define E1000_RDH 0x02810 /* RX Descriptor Head - RW */
893 #define E1000_RDT 0x02818 /* RX Descriptor Tail - RW */
894 #define E1000_RDTR 0x02820 /* RX Delay Timer - RW */
895 #define E1000_RDBAL0 E1000_RDBAL /* RX Desc Base Address Low (0) - RW */
896 #define E1000_RDBAH0 E1000_RDBAH /* RX Desc Base Address High (0) - RW */
897 #define E1000_RDLEN0 E1000_RDLEN /* RX Desc Length (0) - RW */
898 #define E1000_RDH0 E1000_RDH /* RX Desc Head (0) - RW */
899 #define E1000_RDT0 E1000_RDT /* RX Desc Tail (0) - RW */
900 #define E1000_RDTR0 E1000_RDTR /* RX Delay Timer (0) - RW */
901 #define E1000_RXDCTL 0x02828 /* RX Descriptor Control - RW */
902 #define E1000_RADV 0x0282C /* RX Interrupt Absolute Delay Timer - RW */
903 #define E1000_RSRPD 0x02C00 /* RX Small Packet Detect - RW */
904 #define E1000_RAID 0x02C08 /* Receive Ack Interrupt Delay - RW */
905 #define E1000_TXDMAC 0x03000 /* TX DMA Control - RW */
906 #define E1000_TDFH 0x03410 /* TX Data FIFO Head - RW */
907 #define E1000_TDFT 0x03418 /* TX Data FIFO Tail - RW */
908 #define E1000_TDFHS 0x03420 /* TX Data FIFO Head Saved - RW */
909 #define E1000_TDFTS 0x03428 /* TX Data FIFO Tail Saved - RW */
910 #define E1000_TDFPC 0x03430 /* TX Data FIFO Packet Count - RW */
911 #define E1000_TDBAL 0x03800 /* TX Descriptor Base Address Low - RW */
912 #define E1000_TDBAH 0x03804 /* TX Descriptor Base Address High - RW */
913 #define E1000_TDLEN 0x03808 /* TX Descriptor Length - RW */
914 #define E1000_TDH 0x03810 /* TX Descriptor Head - RW */
915 #define E1000_TDT 0x03818 /* TX Descripotr Tail - RW */
916 #define E1000_TIDV 0x03820 /* TX Interrupt Delay Value - RW */
917 #define E1000_TXDCTL 0x03828 /* TX Descriptor Control - RW */
918 #define E1000_TADV 0x0382C /* TX Interrupt Absolute Delay Val - RW */
919 #define E1000_TSPMT 0x03830 /* TCP Segmentation PAD & Min Threshold - RW */
920 #define E1000_TARC0 0x03840 /* TX Arbitration Count (0) */
921 #define E1000_TDBAL1 0x03900 /* TX Desc Base Address Low (1) - RW */
922 #define E1000_TDBAH1 0x03904 /* TX Desc Base Address High (1) - RW */
923 #define E1000_TDLEN1 0x03908 /* TX Desc Length (1) - RW */
924 #define E1000_TDH1 0x03910 /* TX Desc Head (1) - RW */
925 #define E1000_TDT1 0x03918 /* TX Desc Tail (1) - RW */
926 #define E1000_TXDCTL1 0x03928 /* TX Descriptor Control (1) - RW */
927 #define E1000_TARC1 0x03940 /* TX Arbitration Count (1) */
928 #define E1000_CRCERRS 0x04000 /* CRC Error Count - R/clr */
929 #define E1000_ALGNERRC 0x04004 /* Alignment Error Count - R/clr */
930 #define E1000_SYMERRS 0x04008 /* Symbol Error Count - R/clr */
931 #define E1000_RXERRC 0x0400C /* Receive Error Count - R/clr */
932 #define E1000_MPC 0x04010 /* Missed Packet Count - R/clr */
933 #define E1000_SCC 0x04014 /* Single Collision Count - R/clr */
934 #define E1000_ECOL 0x04018 /* Excessive Collision Count - R/clr */
935 #define E1000_MCC 0x0401C /* Multiple Collision Count - R/clr */
936 #define E1000_LATECOL 0x04020 /* Late Collision Count - R/clr */
937 #define E1000_COLC 0x04028 /* Collision Count - R/clr */
938 #define E1000_DC 0x04030 /* Defer Count - R/clr */
939 #define E1000_TNCRS 0x04034 /* TX-No CRS - R/clr */
940 #define E1000_SEC 0x04038 /* Sequence Error Count - R/clr */
941 #define E1000_CEXTERR 0x0403C /* Carrier Extension Error Count - R/clr */
942 #define E1000_RLEC 0x04040 /* Receive Length Error Count - R/clr */
943 #define E1000_XONRXC 0x04048 /* XON RX Count - R/clr */
944 #define E1000_XONTXC 0x0404C /* XON TX Count - R/clr */
945 #define E1000_XOFFRXC 0x04050 /* XOFF RX Count - R/clr */
946 #define E1000_XOFFTXC 0x04054 /* XOFF TX Count - R/clr */
947 #define E1000_FCRUC 0x04058 /* Flow Control RX Unsupported Count- R/clr */
948 #define E1000_PRC64 0x0405C /* Packets RX (64 bytes) - R/clr */
949 #define E1000_PRC127 0x04060 /* Packets RX (65-127 bytes) - R/clr */
950 #define E1000_PRC255 0x04064 /* Packets RX (128-255 bytes) - R/clr */
951 #define E1000_PRC511 0x04068 /* Packets RX (255-511 bytes) - R/clr */
952 #define E1000_PRC1023 0x0406C /* Packets RX (512-1023 bytes) - R/clr */
953 #define E1000_PRC1522 0x04070 /* Packets RX (1024-1522 bytes) - R/clr */
954 #define E1000_GPRC 0x04074 /* Good Packets RX Count - R/clr */
955 #define E1000_BPRC 0x04078 /* Broadcast Packets RX Count - R/clr */
956 #define E1000_MPRC 0x0407C /* Multicast Packets RX Count - R/clr */
957 #define E1000_GPTC 0x04080 /* Good Packets TX Count - R/clr */
958 #define E1000_GORCL 0x04088 /* Good Octets RX Count Low - R/clr */
959 #define E1000_GORCH 0x0408C /* Good Octets RX Count High - R/clr */
960 #define E1000_GOTCL 0x04090 /* Good Octets TX Count Low - R/clr */
961 #define E1000_GOTCH 0x04094 /* Good Octets TX Count High - R/clr */
962 #define E1000_RNBC 0x040A0 /* RX No Buffers Count - R/clr */
963 #define E1000_RUC 0x040A4 /* RX Undersize Count - R/clr */
964 #define E1000_RFC 0x040A8 /* RX Fragment Count - R/clr */
965 #define E1000_ROC 0x040AC /* RX Oversize Count - R/clr */
966 #define E1000_RJC 0x040B0 /* RX Jabber Count - R/clr */
967 #define E1000_MGTPRC 0x040B4 /* Management Packets RX Count - R/clr */
968 #define E1000_MGTPDC 0x040B8 /* Management Packets Dropped Count - R/clr */
969 #define E1000_MGTPTC 0x040BC /* Management Packets TX Count - R/clr */
970 #define E1000_TORL 0x040C0 /* Total Octets RX Low - R/clr */
971 #define E1000_TORH 0x040C4 /* Total Octets RX High - R/clr */
972 #define E1000_TOTL 0x040C8 /* Total Octets TX Low - R/clr */
973 #define E1000_TOTH 0x040CC /* Total Octets TX High - R/clr */
974 #define E1000_TPR 0x040D0 /* Total Packets RX - R/clr */
975 #define E1000_TPT 0x040D4 /* Total Packets TX - R/clr */
976 #define E1000_PTC64 0x040D8 /* Packets TX (64 bytes) - R/clr */
977 #define E1000_PTC127 0x040DC /* Packets TX (65-127 bytes) - R/clr */
978 #define E1000_PTC255 0x040E0 /* Packets TX (128-255 bytes) - R/clr */
979 #define E1000_PTC511 0x040E4 /* Packets TX (256-511 bytes) - R/clr */
980 #define E1000_PTC1023 0x040E8 /* Packets TX (512-1023 bytes) - R/clr */
981 #define E1000_PTC1522 0x040EC /* Packets TX (1024-1522 Bytes) - R/clr */
982 #define E1000_MPTC 0x040F0 /* Multicast Packets TX Count - R/clr */
983 #define E1000_BPTC 0x040F4 /* Broadcast Packets TX Count - R/clr */
984 #define E1000_TSCTC 0x040F8 /* TCP Segmentation Context TX - R/clr */
985 #define E1000_TSCTFC 0x040FC /* TCP Segmentation Context TX Fail - R/clr */
986 #define E1000_IAC 0x04100 /* Interrupt Assertion Count */
987 #define E1000_ICRXPTC 0x04104 /* Interrupt Cause Rx Packet Timer Expire Count */
988 #define E1000_ICRXATC 0x04108 /* Interrupt Cause Rx Absolute Timer Expire Count */
989 #define E1000_ICTXPTC 0x0410C /* Interrupt Cause Tx Packet Timer Expire Count */
990 #define E1000_ICTXATC 0x04110 /* Interrupt Cause Tx Absolute Timer Expire Count */
991 #define E1000_ICTXQEC 0x04118 /* Interrupt Cause Tx Queue Empty Count */
992 #define E1000_ICTXQMTC 0x0411C /* Interrupt Cause Tx Queue Minimum Threshold Count */
993 #define E1000_ICRXDMTC 0x04120 /* Interrupt Cause Rx Descriptor Minimum Threshold Count */
994 #define E1000_ICRXOC 0x04124 /* Interrupt Cause Receiver Overrun Count */
995 #define E1000_RXCSUM 0x05000 /* RX Checksum Control - RW */
996 #define E1000_RFCTL 0x05008 /* Receive Filter Control*/
997 #define E1000_MTA 0x05200 /* Multicast Table Array - RW Array */
998 #define E1000_RA 0x05400 /* Receive Address - RW Array */
999 #define E1000_VFTA 0x05600 /* VLAN Filter Table Array - RW Array */
1000 #define E1000_WUC 0x05800 /* Wakeup Control - RW */
1001 #define E1000_WUFC 0x05808 /* Wakeup Filter Control - RW */
1002 #define E1000_WUS 0x05810 /* Wakeup Status - RO */
1003 #define E1000_MANC 0x05820 /* Management Control - RW */
1004 #define E1000_IPAV 0x05838 /* IP Address Valid - RW */
1005 #define E1000_IP4AT 0x05840 /* IPv4 Address Table - RW Array */
1006 #define E1000_IP6AT 0x05880 /* IPv6 Address Table - RW Array */
1007 #define E1000_WUPL 0x05900 /* Wakeup Packet Length - RW */
1008 #define E1000_WUPM 0x05A00 /* Wakeup Packet Memory - RO A */
1009 #define E1000_FFLT 0x05F00 /* Flexible Filter Length Table - RW Array */
1010 #define E1000_HOST_IF 0x08800 /* Host Interface */
1011 #define E1000_FFMT 0x09000 /* Flexible Filter Mask Table - RW Array */
1012 #define E1000_FFVT 0x09800 /* Flexible Filter Value Table - RW Array */
1014 #define E1000_KUMCTRLSTA 0x00034 /* MAC-PHY interface - RW */
1015 #define E1000_MDPHYA 0x0003C /* PHY address - RW */
1016 #define E1000_MANC2H 0x05860 /* Managment Control To Host - RW */
1017 #define E1000_SW_FW_SYNC 0x05B5C /* Software-Firmware Synchronization - RW */
1019 #define E1000_GCR 0x05B00 /* PCI-Ex Control */
1020 #define E1000_GSCL_1 0x05B10 /* PCI-Ex Statistic Control #1 */
1021 #define E1000_GSCL_2 0x05B14 /* PCI-Ex Statistic Control #2 */
1022 #define E1000_GSCL_3 0x05B18 /* PCI-Ex Statistic Control #3 */
1023 #define E1000_GSCL_4 0x05B1C /* PCI-Ex Statistic Control #4 */
1024 #define E1000_FACTPS 0x05B30 /* Function Active and Power State to MNG */
1025 #define E1000_SWSM 0x05B50 /* SW Semaphore */
1026 #define E1000_FWSM 0x05B54 /* FW Semaphore */
1027 #define E1000_FFLT_DBG 0x05F04 /* Debug Register */
1028 #define E1000_HICR 0x08F00 /* Host Inteface Control */
1031 #define E1000_CPUVEC 0x02C10 /* CPU Vector Register - RW */
1032 #define E1000_MRQC 0x05818 /* Multiple Receive Control - RW */
1033 #define E1000_RETA 0x05C00 /* Redirection Table - RW Array */
1034 #define E1000_RSSRK 0x05C80 /* RSS Random Key - RW Array */
1035 #define E1000_RSSIM 0x05864 /* RSS Interrupt Mask */
1036 #define E1000_RSSIR 0x05868 /* RSS Interrupt Request */
1037 /* Register Set (82542)
1039 * Some of the 82542 registers are located at different offsets than they are
1040 * in more current versions of the 8254x. Despite the difference in location,
1041 * the registers function in the same manner.
1043 #define E1000_82542_CTRL E1000_CTRL
1044 #define E1000_82542_CTRL_DUP E1000_CTRL_DUP
1045 #define E1000_82542_STATUS E1000_STATUS
1046 #define E1000_82542_EECD E1000_EECD
1047 #define E1000_82542_EERD E1000_EERD
1048 #define E1000_82542_CTRL_EXT E1000_CTRL_EXT
1049 #define E1000_82542_FLA E1000_FLA
1050 #define E1000_82542_MDIC E1000_MDIC
1051 #define E1000_82542_SCTL E1000_SCTL
1052 #define E1000_82542_FCAL E1000_FCAL
1053 #define E1000_82542_FCAH E1000_FCAH
1054 #define E1000_82542_FCT E1000_FCT
1055 #define E1000_82542_VET E1000_VET
1056 #define E1000_82542_RA 0x00040
1057 #define E1000_82542_ICR E1000_ICR
1058 #define E1000_82542_ITR E1000_ITR
1059 #define E1000_82542_ICS E1000_ICS
1060 #define E1000_82542_IMS E1000_IMS
1061 #define E1000_82542_IMC E1000_IMC
1062 #define E1000_82542_RCTL E1000_RCTL
1063 #define E1000_82542_RDTR 0x00108
1064 #define E1000_82542_RDBAL 0x00110
1065 #define E1000_82542_RDBAH 0x00114
1066 #define E1000_82542_RDLEN 0x00118
1067 #define E1000_82542_RDH 0x00120
1068 #define E1000_82542_RDT 0x00128
1069 #define E1000_82542_RDTR0 E1000_82542_RDTR
1070 #define E1000_82542_RDBAL0 E1000_82542_RDBAL
1071 #define E1000_82542_RDBAH0 E1000_82542_RDBAH
1072 #define E1000_82542_RDLEN0 E1000_82542_RDLEN
1073 #define E1000_82542_RDH0 E1000_82542_RDH
1074 #define E1000_82542_RDT0 E1000_82542_RDT
1075 #define E1000_82542_RDTR1 0x00130
1076 #define E1000_82542_RDBAL1 0x00138
1077 #define E1000_82542_RDBAH1 0x0013C
1078 #define E1000_82542_RDLEN1 0x00140
1079 #define E1000_82542_RDH1 0x00148
1080 #define E1000_82542_RDT1 0x00150
1081 #define E1000_82542_FCRTH 0x00160
1082 #define E1000_82542_FCRTL 0x00168
1083 #define E1000_82542_FCTTV E1000_FCTTV
1084 #define E1000_82542_TXCW E1000_TXCW
1085 #define E1000_82542_RXCW E1000_RXCW
1086 #define E1000_82542_MTA 0x00200
1087 #define E1000_82542_TCTL E1000_TCTL
1088 #define E1000_82542_TCTL_EXT E1000_TCTL_EXT
1089 #define E1000_82542_TIPG E1000_TIPG
1090 #define E1000_82542_TDBAL 0x00420
1091 #define E1000_82542_TDBAH 0x00424
1092 #define E1000_82542_TDLEN 0x00428
1093 #define E1000_82542_TDH 0x00430
1094 #define E1000_82542_TDT 0x00438
1095 #define E1000_82542_TIDV 0x00440
1096 #define E1000_82542_TBT E1000_TBT
1097 #define E1000_82542_AIT E1000_AIT
1098 #define E1000_82542_VFTA 0x00600
1099 #define E1000_82542_LEDCTL E1000_LEDCTL
1100 #define E1000_82542_PBA E1000_PBA
1101 #define E1000_82542_PBS E1000_PBS
1102 #define E1000_82542_EEMNGCTL E1000_EEMNGCTL
1103 #define E1000_82542_EEARBC E1000_EEARBC
1104 #define E1000_82542_FLASHT E1000_FLASHT
1105 #define E1000_82542_EEWR E1000_EEWR
1106 #define E1000_82542_FLSWCTL E1000_FLSWCTL
1107 #define E1000_82542_FLSWDATA E1000_FLSWDATA
1108 #define E1000_82542_FLSWCNT E1000_FLSWCNT
1109 #define E1000_82542_FLOP E1000_FLOP
1110 #define E1000_82542_EXTCNF_CTRL E1000_EXTCNF_CTRL
1111 #define E1000_82542_EXTCNF_SIZE E1000_EXTCNF_SIZE
1112 #define E1000_82542_ERT E1000_ERT
1113 #define E1000_82542_RXDCTL E1000_RXDCTL
1114 #define E1000_82542_RADV E1000_RADV
1115 #define E1000_82542_RSRPD E1000_RSRPD
1116 #define E1000_82542_TXDMAC E1000_TXDMAC
1117 #define E1000_82542_TDFHS E1000_TDFHS
1118 #define E1000_82542_TDFTS E1000_TDFTS
1119 #define E1000_82542_TDFPC E1000_TDFPC
1120 #define E1000_82542_TXDCTL E1000_TXDCTL
1121 #define E1000_82542_TADV E1000_TADV
1122 #define E1000_82542_TSPMT E1000_TSPMT
1123 #define E1000_82542_CRCERRS E1000_CRCERRS
1124 #define E1000_82542_ALGNERRC E1000_ALGNERRC
1125 #define E1000_82542_SYMERRS E1000_SYMERRS
1126 #define E1000_82542_RXERRC E1000_RXERRC
1127 #define E1000_82542_MPC E1000_MPC
1128 #define E1000_82542_SCC E1000_SCC
1129 #define E1000_82542_ECOL E1000_ECOL
1130 #define E1000_82542_MCC E1000_MCC
1131 #define E1000_82542_LATECOL E1000_LATECOL
1132 #define E1000_82542_COLC E1000_COLC
1133 #define E1000_82542_DC E1000_DC
1134 #define E1000_82542_TNCRS E1000_TNCRS
1135 #define E1000_82542_SEC E1000_SEC
1136 #define E1000_82542_CEXTERR E1000_CEXTERR
1137 #define E1000_82542_RLEC E1000_RLEC
1138 #define E1000_82542_XONRXC E1000_XONRXC
1139 #define E1000_82542_XONTXC E1000_XONTXC
1140 #define E1000_82542_XOFFRXC E1000_XOFFRXC
1141 #define E1000_82542_XOFFTXC E1000_XOFFTXC
1142 #define E1000_82542_FCRUC E1000_FCRUC
1143 #define E1000_82542_PRC64 E1000_PRC64
1144 #define E1000_82542_PRC127 E1000_PRC127
1145 #define E1000_82542_PRC255 E1000_PRC255
1146 #define E1000_82542_PRC511 E1000_PRC511
1147 #define E1000_82542_PRC1023 E1000_PRC1023
1148 #define E1000_82542_PRC1522 E1000_PRC1522
1149 #define E1000_82542_GPRC E1000_GPRC
1150 #define E1000_82542_BPRC E1000_BPRC
1151 #define E1000_82542_MPRC E1000_MPRC
1152 #define E1000_82542_GPTC E1000_GPTC
1153 #define E1000_82542_GORCL E1000_GORCL
1154 #define E1000_82542_GORCH E1000_GORCH
1155 #define E1000_82542_GOTCL E1000_GOTCL
1156 #define E1000_82542_GOTCH E1000_GOTCH
1157 #define E1000_82542_RNBC E1000_RNBC
1158 #define E1000_82542_RUC E1000_RUC
1159 #define E1000_82542_RFC E1000_RFC
1160 #define E1000_82542_ROC E1000_ROC
1161 #define E1000_82542_RJC E1000_RJC
1162 #define E1000_82542_MGTPRC E1000_MGTPRC
1163 #define E1000_82542_MGTPDC E1000_MGTPDC
1164 #define E1000_82542_MGTPTC E1000_MGTPTC
1165 #define E1000_82542_TORL E1000_TORL
1166 #define E1000_82542_TORH E1000_TORH
1167 #define E1000_82542_TOTL E1000_TOTL
1168 #define E1000_82542_TOTH E1000_TOTH
1169 #define E1000_82542_TPR E1000_TPR
1170 #define E1000_82542_TPT E1000_TPT
1171 #define E1000_82542_PTC64 E1000_PTC64
1172 #define E1000_82542_PTC127 E1000_PTC127
1173 #define E1000_82542_PTC255 E1000_PTC255
1174 #define E1000_82542_PTC511 E1000_PTC511
1175 #define E1000_82542_PTC1023 E1000_PTC1023
1176 #define E1000_82542_PTC1522 E1000_PTC1522
1177 #define E1000_82542_MPTC E1000_MPTC
1178 #define E1000_82542_BPTC E1000_BPTC
1179 #define E1000_82542_TSCTC E1000_TSCTC
1180 #define E1000_82542_TSCTFC E1000_TSCTFC
1181 #define E1000_82542_RXCSUM E1000_RXCSUM
1182 #define E1000_82542_WUC E1000_WUC
1183 #define E1000_82542_WUFC E1000_WUFC
1184 #define E1000_82542_WUS E1000_WUS
1185 #define E1000_82542_MANC E1000_MANC
1186 #define E1000_82542_IPAV E1000_IPAV
1187 #define E1000_82542_IP4AT E1000_IP4AT
1188 #define E1000_82542_IP6AT E1000_IP6AT
1189 #define E1000_82542_WUPL E1000_WUPL
1190 #define E1000_82542_WUPM E1000_WUPM
1191 #define E1000_82542_FFLT E1000_FFLT
1192 #define E1000_82542_TDFH 0x08010
1193 #define E1000_82542_TDFT 0x08018
1194 #define E1000_82542_FFMT E1000_FFMT
1195 #define E1000_82542_FFVT E1000_FFVT
1196 #define E1000_82542_HOST_IF E1000_HOST_IF
1197 #define E1000_82542_IAM E1000_IAM
1198 #define E1000_82542_EEMNGCTL E1000_EEMNGCTL
1199 #define E1000_82542_PSRCTL E1000_PSRCTL
1200 #define E1000_82542_RAID E1000_RAID
1201 #define E1000_82542_TARC0 E1000_TARC0
1202 #define E1000_82542_TDBAL1 E1000_TDBAL1
1203 #define E1000_82542_TDBAH1 E1000_TDBAH1
1204 #define E1000_82542_TDLEN1 E1000_TDLEN1
1205 #define E1000_82542_TDH1 E1000_TDH1
1206 #define E1000_82542_TDT1 E1000_TDT1
1207 #define E1000_82542_TXDCTL1 E1000_TXDCTL1
1208 #define E1000_82542_TARC1 E1000_TARC1
1209 #define E1000_82542_RFCTL E1000_RFCTL
1210 #define E1000_82542_GCR E1000_GCR
1211 #define E1000_82542_GSCL_1 E1000_GSCL_1
1212 #define E1000_82542_GSCL_2 E1000_GSCL_2
1213 #define E1000_82542_GSCL_3 E1000_GSCL_3
1214 #define E1000_82542_GSCL_4 E1000_GSCL_4
1215 #define E1000_82542_FACTPS E1000_FACTPS
1216 #define E1000_82542_SWSM E1000_SWSM
1217 #define E1000_82542_FWSM E1000_FWSM
1218 #define E1000_82542_FFLT_DBG E1000_FFLT_DBG
1219 #define E1000_82542_IAC E1000_IAC
1220 #define E1000_82542_ICRXPTC E1000_ICRXPTC
1221 #define E1000_82542_ICRXATC E1000_ICRXATC
1222 #define E1000_82542_ICTXPTC E1000_ICTXPTC
1223 #define E1000_82542_ICTXATC E1000_ICTXATC
1224 #define E1000_82542_ICTXQEC E1000_ICTXQEC
1225 #define E1000_82542_ICTXQMTC E1000_ICTXQMTC
1226 #define E1000_82542_ICRXDMTC E1000_ICRXDMTC
1227 #define E1000_82542_ICRXOC E1000_ICRXOC
1228 #define E1000_82542_HICR E1000_HICR
1230 #define E1000_82542_CPUVEC E1000_CPUVEC
1231 #define E1000_82542_MRQC E1000_MRQC
1232 #define E1000_82542_RETA E1000_RETA
1233 #define E1000_82542_RSSRK E1000_RSSRK
1234 #define E1000_82542_RSSIM E1000_RSSIM
1235 #define E1000_82542_RSSIR E1000_RSSIR
1236 #define E1000_82542_KUMCTRLSTA E1000_KUMCTRLSTA
1237 #define E1000_82542_SW_FW_SYNC E1000_SW_FW_SYNC
1239 /* Statistics counters collected by the MAC */
1240 struct e1000_hw_stats {
1310 /* Structure containing variables used by the shared code (e1000_hw.c) */
1312 uint8_t __iomem *hw_addr;
1313 uint8_t *flash_address;
1314 e1000_mac_type mac_type;
1315 e1000_phy_type phy_type;
1316 uint32_t phy_init_script;
1317 e1000_media_type media_type;
1320 e1000_bus_speed bus_speed;
1321 e1000_bus_width bus_width;
1322 e1000_bus_type bus_type;
1323 struct e1000_eeprom_info eeprom;
1324 e1000_ms_type master_slave;
1325 e1000_ms_type original_master_slave;
1326 e1000_ffe_config ffe_config_state;
1327 uint32_t asf_firmware_present;
1328 uint32_t eeprom_semaphore_present;
1329 uint32_t swfw_sync_present;
1330 unsigned long io_base;
1332 uint32_t phy_revision;
1334 uint32_t original_fc;
1336 uint32_t autoneg_failed;
1337 uint32_t max_frame_size;
1338 uint32_t min_frame_size;
1339 uint32_t mc_filter_type;
1340 uint32_t num_mc_addrs;
1341 uint32_t collision_delta;
1342 uint32_t tx_packet_delta;
1343 uint32_t ledctl_default;
1344 uint32_t ledctl_mode1;
1345 uint32_t ledctl_mode2;
1346 boolean_t tx_pkt_filtering;
1347 struct e1000_host_mng_dhcp_cookie mng_cookie;
1348 uint16_t phy_spd_default;
1349 uint16_t autoneg_advertised;
1350 uint16_t pci_cmd_word;
1351 uint16_t fc_high_water;
1352 uint16_t fc_low_water;
1353 uint16_t fc_pause_time;
1354 uint16_t current_ifs_val;
1355 uint16_t ifs_min_val;
1356 uint16_t ifs_max_val;
1357 uint16_t ifs_step_size;
1361 uint16_t subsystem_id;
1362 uint16_t subsystem_vendor_id;
1363 uint8_t revision_id;
1366 uint8_t forced_speed_duplex;
1367 uint8_t wait_autoneg_complete;
1368 uint8_t dma_fairness;
1369 uint8_t mac_addr[NODE_ADDRESS_SIZE];
1370 uint8_t perm_mac_addr[NODE_ADDRESS_SIZE];
1371 boolean_t disable_polarity_correction;
1372 boolean_t speed_downgraded;
1373 e1000_smart_speed smart_speed;
1374 e1000_dsp_config dsp_config_state;
1375 boolean_t get_link_status;
1376 boolean_t serdes_link_down;
1377 boolean_t tbi_compatibility_en;
1378 boolean_t tbi_compatibility_on;
1379 boolean_t laa_is_present;
1380 boolean_t phy_reset_disable;
1381 boolean_t fc_send_xon;
1382 boolean_t fc_strict_ieee;
1383 boolean_t report_tx_early;
1384 boolean_t adaptive_ifs;
1385 boolean_t ifs_params_forced;
1386 boolean_t in_ifs_mode;
1387 boolean_t mng_reg_access_disabled;
1388 boolean_t leave_av_bit_off;
1392 #define E1000_EEPROM_SWDPIN0 0x0001 /* SWDPIN 0 EEPROM Value */
1393 #define E1000_EEPROM_LED_LOGIC 0x0020 /* Led Logic Word */
1394 #define E1000_EEPROM_RW_REG_DATA 16 /* Offset to data in EEPROM read/write registers */
1395 #define E1000_EEPROM_RW_REG_DONE 2 /* Offset to READ/WRITE done bit */
1396 #define E1000_EEPROM_RW_REG_START 1 /* First bit for telling part to start operation */
1397 #define E1000_EEPROM_RW_ADDR_SHIFT 2 /* Shift to the address bits */
1398 #define E1000_EEPROM_POLL_WRITE 1 /* Flag for polling for write complete */
1399 #define E1000_EEPROM_POLL_READ 0 /* Flag for polling for read complete */
1400 /* Register Bit Masks */
1401 /* Device Control */
1402 #define E1000_CTRL_FD 0x00000001 /* Full duplex.0=half; 1=full */
1403 #define E1000_CTRL_BEM 0x00000002 /* Endian Mode.0=little,1=big */
1404 #define E1000_CTRL_PRIOR 0x00000004 /* Priority on PCI. 0=rx,1=fair */
1405 #define E1000_CTRL_GIO_MASTER_DISABLE 0x00000004 /*Blocks new Master requests */
1406 #define E1000_CTRL_LRST 0x00000008 /* Link reset. 0=normal,1=reset */
1407 #define E1000_CTRL_TME 0x00000010 /* Test mode. 0=normal,1=test */
1408 #define E1000_CTRL_SLE 0x00000020 /* Serial Link on 0=dis,1=en */
1409 #define E1000_CTRL_ASDE 0x00000020 /* Auto-speed detect enable */
1410 #define E1000_CTRL_SLU 0x00000040 /* Set link up (Force Link) */
1411 #define E1000_CTRL_ILOS 0x00000080 /* Invert Loss-Of Signal */
1412 #define E1000_CTRL_SPD_SEL 0x00000300 /* Speed Select Mask */
1413 #define E1000_CTRL_SPD_10 0x00000000 /* Force 10Mb */
1414 #define E1000_CTRL_SPD_100 0x00000100 /* Force 100Mb */
1415 #define E1000_CTRL_SPD_1000 0x00000200 /* Force 1Gb */
1416 #define E1000_CTRL_BEM32 0x00000400 /* Big Endian 32 mode */
1417 #define E1000_CTRL_FRCSPD 0x00000800 /* Force Speed */
1418 #define E1000_CTRL_FRCDPX 0x00001000 /* Force Duplex */
1419 #define E1000_CTRL_D_UD_EN 0x00002000 /* Dock/Undock enable */
1420 #define E1000_CTRL_D_UD_POLARITY 0x00004000 /* Defined polarity of Dock/Undock indication in SDP[0] */
1421 #define E1000_CTRL_FORCE_PHY_RESET 0x00008000 /* Reset both PHY ports, through PHYRST_N pin */
1422 #define E1000_CTRL_EXT_LINK_EN 0x00010000 /* enable link status from external LINK_0 and LINK_1 pins */
1423 #define E1000_CTRL_SWDPIN0 0x00040000 /* SWDPIN 0 value */
1424 #define E1000_CTRL_SWDPIN1 0x00080000 /* SWDPIN 1 value */
1425 #define E1000_CTRL_SWDPIN2 0x00100000 /* SWDPIN 2 value */
1426 #define E1000_CTRL_SWDPIN3 0x00200000 /* SWDPIN 3 value */
1427 #define E1000_CTRL_SWDPIO0 0x00400000 /* SWDPIN 0 Input or output */
1428 #define E1000_CTRL_SWDPIO1 0x00800000 /* SWDPIN 1 input or output */
1429 #define E1000_CTRL_SWDPIO2 0x01000000 /* SWDPIN 2 input or output */
1430 #define E1000_CTRL_SWDPIO3 0x02000000 /* SWDPIN 3 input or output */
1431 #define E1000_CTRL_RST 0x04000000 /* Global reset */
1432 #define E1000_CTRL_RFCE 0x08000000 /* Receive Flow Control enable */
1433 #define E1000_CTRL_TFCE 0x10000000 /* Transmit flow control enable */
1434 #define E1000_CTRL_RTE 0x20000000 /* Routing tag enable */
1435 #define E1000_CTRL_VME 0x40000000 /* IEEE VLAN mode enable */
1436 #define E1000_CTRL_PHY_RST 0x80000000 /* PHY Reset */
1439 #define E1000_STATUS_FD 0x00000001 /* Full duplex.0=half,1=full */
1440 #define E1000_STATUS_LU 0x00000002 /* Link up.0=no,1=link */
1441 #define E1000_STATUS_FUNC_MASK 0x0000000C /* PCI Function Mask */
1442 #define E1000_STATUS_FUNC_SHIFT 2
1443 #define E1000_STATUS_FUNC_0 0x00000000 /* Function 0 */
1444 #define E1000_STATUS_FUNC_1 0x00000004 /* Function 1 */
1445 #define E1000_STATUS_TXOFF 0x00000010 /* transmission paused */
1446 #define E1000_STATUS_TBIMODE 0x00000020 /* TBI mode */
1447 #define E1000_STATUS_SPEED_MASK 0x000000C0
1448 #define E1000_STATUS_SPEED_10 0x00000000 /* Speed 10Mb/s */
1449 #define E1000_STATUS_SPEED_100 0x00000040 /* Speed 100Mb/s */
1450 #define E1000_STATUS_SPEED_1000 0x00000080 /* Speed 1000Mb/s */
1451 #define E1000_STATUS_ASDV 0x00000300 /* Auto speed detect value */
1452 #define E1000_STATUS_DOCK_CI 0x00000800 /* Change in Dock/Undock state. Clear on write '0'. */
1453 #define E1000_STATUS_GIO_MASTER_ENABLE 0x00080000 /* Status of Master requests. */
1454 #define E1000_STATUS_MTXCKOK 0x00000400 /* MTX clock running OK */
1455 #define E1000_STATUS_PCI66 0x00000800 /* In 66Mhz slot */
1456 #define E1000_STATUS_BUS64 0x00001000 /* In 64 bit slot */
1457 #define E1000_STATUS_PCIX_MODE 0x00002000 /* PCI-X mode */
1458 #define E1000_STATUS_PCIX_SPEED 0x0000C000 /* PCI-X bus speed */
1459 #define E1000_STATUS_BMC_SKU_0 0x00100000 /* BMC USB redirect disabled */
1460 #define E1000_STATUS_BMC_SKU_1 0x00200000 /* BMC SRAM disabled */
1461 #define E1000_STATUS_BMC_SKU_2 0x00400000 /* BMC SDRAM disabled */
1462 #define E1000_STATUS_BMC_CRYPTO 0x00800000 /* BMC crypto disabled */
1463 #define E1000_STATUS_BMC_LITE 0x01000000 /* BMC external code execution disabled */
1464 #define E1000_STATUS_RGMII_ENABLE 0x02000000 /* RGMII disabled */
1465 #define E1000_STATUS_FUSE_8 0x04000000
1466 #define E1000_STATUS_FUSE_9 0x08000000
1467 #define E1000_STATUS_SERDES0_DIS 0x10000000 /* SERDES disabled on port 0 */
1468 #define E1000_STATUS_SERDES1_DIS 0x20000000 /* SERDES disabled on port 1 */
1470 /* Constants used to intrepret the masked PCI-X bus speed. */
1471 #define E1000_STATUS_PCIX_SPEED_66 0x00000000 /* PCI-X bus speed 50-66 MHz */
1472 #define E1000_STATUS_PCIX_SPEED_100 0x00004000 /* PCI-X bus speed 66-100 MHz */
1473 #define E1000_STATUS_PCIX_SPEED_133 0x00008000 /* PCI-X bus speed 100-133 MHz */
1475 /* EEPROM/Flash Control */
1476 #define E1000_EECD_SK 0x00000001 /* EEPROM Clock */
1477 #define E1000_EECD_CS 0x00000002 /* EEPROM Chip Select */
1478 #define E1000_EECD_DI 0x00000004 /* EEPROM Data In */
1479 #define E1000_EECD_DO 0x00000008 /* EEPROM Data Out */
1480 #define E1000_EECD_FWE_MASK 0x00000030
1481 #define E1000_EECD_FWE_DIS 0x00000010 /* Disable FLASH writes */
1482 #define E1000_EECD_FWE_EN 0x00000020 /* Enable FLASH writes */
1483 #define E1000_EECD_FWE_SHIFT 4
1484 #define E1000_EECD_REQ 0x00000040 /* EEPROM Access Request */
1485 #define E1000_EECD_GNT 0x00000080 /* EEPROM Access Grant */
1486 #define E1000_EECD_PRES 0x00000100 /* EEPROM Present */
1487 #define E1000_EECD_SIZE 0x00000200 /* EEPROM Size (0=64 word 1=256 word) */
1488 #define E1000_EECD_ADDR_BITS 0x00000400 /* EEPROM Addressing bits based on type
1489 * (0-small, 1-large) */
1490 #define E1000_EECD_TYPE 0x00002000 /* EEPROM Type (1-SPI, 0-Microwire) */
1491 #ifndef E1000_EEPROM_GRANT_ATTEMPTS
1492 #define E1000_EEPROM_GRANT_ATTEMPTS 1000 /* EEPROM # attempts to gain grant */
1494 #define E1000_EECD_AUTO_RD 0x00000200 /* EEPROM Auto Read done */
1495 #define E1000_EECD_SIZE_EX_MASK 0x00007800 /* EEprom Size */
1496 #define E1000_EECD_SIZE_EX_SHIFT 11
1497 #define E1000_EECD_NVADDS 0x00018000 /* NVM Address Size */
1498 #define E1000_EECD_SELSHAD 0x00020000 /* Select Shadow RAM */
1499 #define E1000_EECD_INITSRAM 0x00040000 /* Initialize Shadow RAM */
1500 #define E1000_EECD_FLUPD 0x00080000 /* Update FLASH */
1501 #define E1000_EECD_AUPDEN 0x00100000 /* Enable Autonomous FLASH update */
1502 #define E1000_EECD_SHADV 0x00200000 /* Shadow RAM Data Valid */
1503 #define E1000_EECD_SEC1VAL 0x00400000 /* Sector One Valid */
1504 #define E1000_EECD_SECVAL_SHIFT 22
1505 #define E1000_STM_OPCODE 0xDB00
1506 #define E1000_HICR_FW_RESET 0xC0
1509 #define E1000_EERD_START 0x00000001 /* Start Read */
1510 #define E1000_EERD_DONE 0x00000010 /* Read Done */
1511 #define E1000_EERD_ADDR_SHIFT 8
1512 #define E1000_EERD_ADDR_MASK 0x0000FF00 /* Read Address */
1513 #define E1000_EERD_DATA_SHIFT 16
1514 #define E1000_EERD_DATA_MASK 0xFFFF0000 /* Read Data */
1516 /* SPI EEPROM Status Register */
1517 #define EEPROM_STATUS_RDY_SPI 0x01
1518 #define EEPROM_STATUS_WEN_SPI 0x02
1519 #define EEPROM_STATUS_BP0_SPI 0x04
1520 #define EEPROM_STATUS_BP1_SPI 0x08
1521 #define EEPROM_STATUS_WPEN_SPI 0x80
1523 /* Extended Device Control */
1524 #define E1000_CTRL_EXT_GPI0_EN 0x00000001 /* Maps SDP4 to GPI0 */
1525 #define E1000_CTRL_EXT_GPI1_EN 0x00000002 /* Maps SDP5 to GPI1 */
1526 #define E1000_CTRL_EXT_PHYINT_EN E1000_CTRL_EXT_GPI1_EN
1527 #define E1000_CTRL_EXT_GPI2_EN 0x00000004 /* Maps SDP6 to GPI2 */
1528 #define E1000_CTRL_EXT_GPI3_EN 0x00000008 /* Maps SDP7 to GPI3 */
1529 #define E1000_CTRL_EXT_SDP4_DATA 0x00000010 /* Value of SW Defineable Pin 4 */
1530 #define E1000_CTRL_EXT_SDP5_DATA 0x00000020 /* Value of SW Defineable Pin 5 */
1531 #define E1000_CTRL_EXT_PHY_INT E1000_CTRL_EXT_SDP5_DATA
1532 #define E1000_CTRL_EXT_SDP6_DATA 0x00000040 /* Value of SW Defineable Pin 6 */
1533 #define E1000_CTRL_EXT_SDP7_DATA 0x00000080 /* Value of SW Defineable Pin 7 */
1534 #define E1000_CTRL_EXT_SDP4_DIR 0x00000100 /* Direction of SDP4 0=in 1=out */
1535 #define E1000_CTRL_EXT_SDP5_DIR 0x00000200 /* Direction of SDP5 0=in 1=out */
1536 #define E1000_CTRL_EXT_SDP6_DIR 0x00000400 /* Direction of SDP6 0=in 1=out */
1537 #define E1000_CTRL_EXT_SDP7_DIR 0x00000800 /* Direction of SDP7 0=in 1=out */
1538 #define E1000_CTRL_EXT_ASDCHK 0x00001000 /* Initiate an ASD sequence */
1539 #define E1000_CTRL_EXT_EE_RST 0x00002000 /* Reinitialize from EEPROM */
1540 #define E1000_CTRL_EXT_IPS 0x00004000 /* Invert Power State */
1541 #define E1000_CTRL_EXT_SPD_BYPS 0x00008000 /* Speed Select Bypass */
1542 #define E1000_CTRL_EXT_RO_DIS 0x00020000 /* Relaxed Ordering disable */
1543 #define E1000_CTRL_EXT_LINK_MODE_MASK 0x00C00000
1544 #define E1000_CTRL_EXT_LINK_MODE_GMII 0x00000000
1545 #define E1000_CTRL_EXT_LINK_MODE_TBI 0x00C00000
1546 #define E1000_CTRL_EXT_LINK_MODE_KMRN 0x00000000
1547 #define E1000_CTRL_EXT_LINK_MODE_SERDES 0x00C00000
1548 #define E1000_CTRL_EXT_WR_WMARK_MASK 0x03000000
1549 #define E1000_CTRL_EXT_WR_WMARK_256 0x00000000
1550 #define E1000_CTRL_EXT_WR_WMARK_320 0x01000000
1551 #define E1000_CTRL_EXT_WR_WMARK_384 0x02000000
1552 #define E1000_CTRL_EXT_WR_WMARK_448 0x03000000
1553 #define E1000_CTRL_EXT_CANC 0x04000000 /* Interrupt delay cancellation */
1554 #define E1000_CTRL_EXT_DRV_LOAD 0x10000000 /* Driver loaded bit for FW */
1555 #define E1000_CTRL_EXT_IAME 0x08000000 /* Interrupt acknowledge Auto-mask */
1556 #define E1000_CTRL_EXT_INT_TIMER_CLR 0x20000000 /* Clear Interrupt timers after IMS clear */
1557 #define E1000_CRTL_EXT_PB_PAREN 0x01000000 /* packet buffer parity error detection enabled */
1558 #define E1000_CTRL_EXT_DF_PAREN 0x02000000 /* descriptor FIFO parity error detection enable */
1559 #define E1000_CTRL_EXT_GHOST_PAREN 0x40000000
1562 #define E1000_MDIC_DATA_MASK 0x0000FFFF
1563 #define E1000_MDIC_REG_MASK 0x001F0000
1564 #define E1000_MDIC_REG_SHIFT 16
1565 #define E1000_MDIC_PHY_MASK 0x03E00000
1566 #define E1000_MDIC_PHY_SHIFT 21
1567 #define E1000_MDIC_OP_WRITE 0x04000000
1568 #define E1000_MDIC_OP_READ 0x08000000
1569 #define E1000_MDIC_READY 0x10000000
1570 #define E1000_MDIC_INT_EN 0x20000000
1571 #define E1000_MDIC_ERROR 0x40000000
1573 #define E1000_KUMCTRLSTA_MASK 0x0000FFFF
1574 #define E1000_KUMCTRLSTA_OFFSET 0x001F0000
1575 #define E1000_KUMCTRLSTA_OFFSET_SHIFT 16
1576 #define E1000_KUMCTRLSTA_REN 0x00200000
1578 #define E1000_KUMCTRLSTA_OFFSET_FIFO_CTRL 0x00000000
1579 #define E1000_KUMCTRLSTA_OFFSET_CTRL 0x00000001
1580 #define E1000_KUMCTRLSTA_OFFSET_INB_CTRL 0x00000002
1581 #define E1000_KUMCTRLSTA_OFFSET_DIAG 0x00000003
1582 #define E1000_KUMCTRLSTA_OFFSET_TIMEOUTS 0x00000004
1583 #define E1000_KUMCTRLSTA_OFFSET_INB_PARAM 0x00000009
1584 #define E1000_KUMCTRLSTA_OFFSET_HD_CTRL 0x00000010
1585 #define E1000_KUMCTRLSTA_OFFSET_M2P_SERDES 0x0000001E
1586 #define E1000_KUMCTRLSTA_OFFSET_M2P_MODES 0x0000001F
1589 #define E1000_KUMCTRLSTA_FIFO_CTRL_RX_BYPASS 0x00000008
1590 #define E1000_KUMCTRLSTA_FIFO_CTRL_TX_BYPASS 0x00000800
1592 /* In-Band Control */
1593 #define E1000_KUMCTRLSTA_INB_CTRL_DIS_PADDING 0x00000010
1595 /* Half-Duplex Control */
1596 #define E1000_KUMCTRLSTA_HD_CTRL_10_100_DEFAULT 0x00000004
1597 #define E1000_KUMCTRLSTA_HD_CTRL_1000_DEFAULT 0x00000000
1600 #define E1000_LEDCTL_LED0_MODE_MASK 0x0000000F
1601 #define E1000_LEDCTL_LED0_MODE_SHIFT 0
1602 #define E1000_LEDCTL_LED0_BLINK_RATE 0x0000020
1603 #define E1000_LEDCTL_LED0_IVRT 0x00000040
1604 #define E1000_LEDCTL_LED0_BLINK 0x00000080
1605 #define E1000_LEDCTL_LED1_MODE_MASK 0x00000F00
1606 #define E1000_LEDCTL_LED1_MODE_SHIFT 8
1607 #define E1000_LEDCTL_LED1_BLINK_RATE 0x0002000
1608 #define E1000_LEDCTL_LED1_IVRT 0x00004000
1609 #define E1000_LEDCTL_LED1_BLINK 0x00008000
1610 #define E1000_LEDCTL_LED2_MODE_MASK 0x000F0000
1611 #define E1000_LEDCTL_LED2_MODE_SHIFT 16
1612 #define E1000_LEDCTL_LED2_BLINK_RATE 0x00200000
1613 #define E1000_LEDCTL_LED2_IVRT 0x00400000
1614 #define E1000_LEDCTL_LED2_BLINK 0x00800000
1615 #define E1000_LEDCTL_LED3_MODE_MASK 0x0F000000
1616 #define E1000_LEDCTL_LED3_MODE_SHIFT 24
1617 #define E1000_LEDCTL_LED3_BLINK_RATE 0x20000000
1618 #define E1000_LEDCTL_LED3_IVRT 0x40000000
1619 #define E1000_LEDCTL_LED3_BLINK 0x80000000
1621 #define E1000_LEDCTL_MODE_LINK_10_1000 0x0
1622 #define E1000_LEDCTL_MODE_LINK_100_1000 0x1
1623 #define E1000_LEDCTL_MODE_LINK_UP 0x2
1624 #define E1000_LEDCTL_MODE_ACTIVITY 0x3
1625 #define E1000_LEDCTL_MODE_LINK_ACTIVITY 0x4
1626 #define E1000_LEDCTL_MODE_LINK_10 0x5
1627 #define E1000_LEDCTL_MODE_LINK_100 0x6
1628 #define E1000_LEDCTL_MODE_LINK_1000 0x7
1629 #define E1000_LEDCTL_MODE_PCIX_MODE 0x8
1630 #define E1000_LEDCTL_MODE_FULL_DUPLEX 0x9
1631 #define E1000_LEDCTL_MODE_COLLISION 0xA
1632 #define E1000_LEDCTL_MODE_BUS_SPEED 0xB
1633 #define E1000_LEDCTL_MODE_BUS_SIZE 0xC
1634 #define E1000_LEDCTL_MODE_PAUSED 0xD
1635 #define E1000_LEDCTL_MODE_LED_ON 0xE
1636 #define E1000_LEDCTL_MODE_LED_OFF 0xF
1638 /* Receive Address */
1639 #define E1000_RAH_AV 0x80000000 /* Receive descriptor valid */
1641 /* Interrupt Cause Read */
1642 #define E1000_ICR_TXDW 0x00000001 /* Transmit desc written back */
1643 #define E1000_ICR_TXQE 0x00000002 /* Transmit Queue empty */
1644 #define E1000_ICR_LSC 0x00000004 /* Link Status Change */
1645 #define E1000_ICR_RXSEQ 0x00000008 /* rx sequence error */
1646 #define E1000_ICR_RXDMT0 0x00000010 /* rx desc min. threshold (0) */
1647 #define E1000_ICR_RXO 0x00000040 /* rx overrun */
1648 #define E1000_ICR_RXT0 0x00000080 /* rx timer intr (ring 0) */
1649 #define E1000_ICR_MDAC 0x00000200 /* MDIO access complete */
1650 #define E1000_ICR_RXCFG 0x00000400 /* RX /c/ ordered set */
1651 #define E1000_ICR_GPI_EN0 0x00000800 /* GP Int 0 */
1652 #define E1000_ICR_GPI_EN1 0x00001000 /* GP Int 1 */
1653 #define E1000_ICR_GPI_EN2 0x00002000 /* GP Int 2 */
1654 #define E1000_ICR_GPI_EN3 0x00004000 /* GP Int 3 */
1655 #define E1000_ICR_TXD_LOW 0x00008000
1656 #define E1000_ICR_SRPD 0x00010000
1657 #define E1000_ICR_ACK 0x00020000 /* Receive Ack frame */
1658 #define E1000_ICR_MNG 0x00040000 /* Manageability event */
1659 #define E1000_ICR_DOCK 0x00080000 /* Dock/Undock */
1660 #define E1000_ICR_INT_ASSERTED 0x80000000 /* If this bit asserted, the driver should claim the interrupt */
1661 #define E1000_ICR_RXD_FIFO_PAR0 0x00100000 /* queue 0 Rx descriptor FIFO parity error */
1662 #define E1000_ICR_TXD_FIFO_PAR0 0x00200000 /* queue 0 Tx descriptor FIFO parity error */
1663 #define E1000_ICR_HOST_ARB_PAR 0x00400000 /* host arb read buffer parity error */
1664 #define E1000_ICR_PB_PAR 0x00800000 /* packet buffer parity error */
1665 #define E1000_ICR_RXD_FIFO_PAR1 0x01000000 /* queue 1 Rx descriptor FIFO parity error */
1666 #define E1000_ICR_TXD_FIFO_PAR1 0x02000000 /* queue 1 Tx descriptor FIFO parity error */
1667 #define E1000_ICR_ALL_PARITY 0x03F00000 /* all parity error bits */
1669 /* Interrupt Cause Set */
1670 #define E1000_ICS_TXDW E1000_ICR_TXDW /* Transmit desc written back */
1671 #define E1000_ICS_TXQE E1000_ICR_TXQE /* Transmit Queue empty */
1672 #define E1000_ICS_LSC E1000_ICR_LSC /* Link Status Change */
1673 #define E1000_ICS_RXSEQ E1000_ICR_RXSEQ /* rx sequence error */
1674 #define E1000_ICS_RXDMT0 E1000_ICR_RXDMT0 /* rx desc min. threshold */
1675 #define E1000_ICS_RXO E1000_ICR_RXO /* rx overrun */
1676 #define E1000_ICS_RXT0 E1000_ICR_RXT0 /* rx timer intr */
1677 #define E1000_ICS_MDAC E1000_ICR_MDAC /* MDIO access complete */
1678 #define E1000_ICS_RXCFG E1000_ICR_RXCFG /* RX /c/ ordered set */
1679 #define E1000_ICS_GPI_EN0 E1000_ICR_GPI_EN0 /* GP Int 0 */
1680 #define E1000_ICS_GPI_EN1 E1000_ICR_GPI_EN1 /* GP Int 1 */
1681 #define E1000_ICS_GPI_EN2 E1000_ICR_GPI_EN2 /* GP Int 2 */
1682 #define E1000_ICS_GPI_EN3 E1000_ICR_GPI_EN3 /* GP Int 3 */
1683 #define E1000_ICS_TXD_LOW E1000_ICR_TXD_LOW
1684 #define E1000_ICS_SRPD E1000_ICR_SRPD
1685 #define E1000_ICS_ACK E1000_ICR_ACK /* Receive Ack frame */
1686 #define E1000_ICS_MNG E1000_ICR_MNG /* Manageability event */
1687 #define E1000_ICS_DOCK E1000_ICR_DOCK /* Dock/Undock */
1688 #define E1000_ICS_RXD_FIFO_PAR0 E1000_ICR_RXD_FIFO_PAR0 /* queue 0 Rx descriptor FIFO parity error */
1689 #define E1000_ICS_TXD_FIFO_PAR0 E1000_ICR_TXD_FIFO_PAR0 /* queue 0 Tx descriptor FIFO parity error */
1690 #define E1000_ICS_HOST_ARB_PAR E1000_ICR_HOST_ARB_PAR /* host arb read buffer parity error */
1691 #define E1000_ICS_PB_PAR E1000_ICR_PB_PAR /* packet buffer parity error */
1692 #define E1000_ICS_RXD_FIFO_PAR1 E1000_ICR_RXD_FIFO_PAR1 /* queue 1 Rx descriptor FIFO parity error */
1693 #define E1000_ICS_TXD_FIFO_PAR1 E1000_ICR_TXD_FIFO_PAR1 /* queue 1 Tx descriptor FIFO parity error */
1695 /* Interrupt Mask Set */
1696 #define E1000_IMS_TXDW E1000_ICR_TXDW /* Transmit desc written back */
1697 #define E1000_IMS_TXQE E1000_ICR_TXQE /* Transmit Queue empty */
1698 #define E1000_IMS_LSC E1000_ICR_LSC /* Link Status Change */
1699 #define E1000_IMS_RXSEQ E1000_ICR_RXSEQ /* rx sequence error */
1700 #define E1000_IMS_RXDMT0 E1000_ICR_RXDMT0 /* rx desc min. threshold */
1701 #define E1000_IMS_RXO E1000_ICR_RXO /* rx overrun */
1702 #define E1000_IMS_RXT0 E1000_ICR_RXT0 /* rx timer intr */
1703 #define E1000_IMS_MDAC E1000_ICR_MDAC /* MDIO access complete */
1704 #define E1000_IMS_RXCFG E1000_ICR_RXCFG /* RX /c/ ordered set */
1705 #define E1000_IMS_GPI_EN0 E1000_ICR_GPI_EN0 /* GP Int 0 */
1706 #define E1000_IMS_GPI_EN1 E1000_ICR_GPI_EN1 /* GP Int 1 */
1707 #define E1000_IMS_GPI_EN2 E1000_ICR_GPI_EN2 /* GP Int 2 */
1708 #define E1000_IMS_GPI_EN3 E1000_ICR_GPI_EN3 /* GP Int 3 */
1709 #define E1000_IMS_TXD_LOW E1000_ICR_TXD_LOW
1710 #define E1000_IMS_SRPD E1000_ICR_SRPD
1711 #define E1000_IMS_ACK E1000_ICR_ACK /* Receive Ack frame */
1712 #define E1000_IMS_MNG E1000_ICR_MNG /* Manageability event */
1713 #define E1000_IMS_DOCK E1000_ICR_DOCK /* Dock/Undock */
1714 #define E1000_IMS_RXD_FIFO_PAR0 E1000_ICR_RXD_FIFO_PAR0 /* queue 0 Rx descriptor FIFO parity error */
1715 #define E1000_IMS_TXD_FIFO_PAR0 E1000_ICR_TXD_FIFO_PAR0 /* queue 0 Tx descriptor FIFO parity error */
1716 #define E1000_IMS_HOST_ARB_PAR E1000_ICR_HOST_ARB_PAR /* host arb read buffer parity error */
1717 #define E1000_IMS_PB_PAR E1000_ICR_PB_PAR /* packet buffer parity error */
1718 #define E1000_IMS_RXD_FIFO_PAR1 E1000_ICR_RXD_FIFO_PAR1 /* queue 1 Rx descriptor FIFO parity error */
1719 #define E1000_IMS_TXD_FIFO_PAR1 E1000_ICR_TXD_FIFO_PAR1 /* queue 1 Tx descriptor FIFO parity error */
1721 /* Interrupt Mask Clear */
1722 #define E1000_IMC_TXDW E1000_ICR_TXDW /* Transmit desc written back */
1723 #define E1000_IMC_TXQE E1000_ICR_TXQE /* Transmit Queue empty */
1724 #define E1000_IMC_LSC E1000_ICR_LSC /* Link Status Change */
1725 #define E1000_IMC_RXSEQ E1000_ICR_RXSEQ /* rx sequence error */
1726 #define E1000_IMC_RXDMT0 E1000_ICR_RXDMT0 /* rx desc min. threshold */
1727 #define E1000_IMC_RXO E1000_ICR_RXO /* rx overrun */
1728 #define E1000_IMC_RXT0 E1000_ICR_RXT0 /* rx timer intr */
1729 #define E1000_IMC_MDAC E1000_ICR_MDAC /* MDIO access complete */
1730 #define E1000_IMC_RXCFG E1000_ICR_RXCFG /* RX /c/ ordered set */
1731 #define E1000_IMC_GPI_EN0 E1000_ICR_GPI_EN0 /* GP Int 0 */
1732 #define E1000_IMC_GPI_EN1 E1000_ICR_GPI_EN1 /* GP Int 1 */
1733 #define E1000_IMC_GPI_EN2 E1000_ICR_GPI_EN2 /* GP Int 2 */
1734 #define E1000_IMC_GPI_EN3 E1000_ICR_GPI_EN3 /* GP Int 3 */
1735 #define E1000_IMC_TXD_LOW E1000_ICR_TXD_LOW
1736 #define E1000_IMC_SRPD E1000_ICR_SRPD
1737 #define E1000_IMC_ACK E1000_ICR_ACK /* Receive Ack frame */
1738 #define E1000_IMC_MNG E1000_ICR_MNG /* Manageability event */
1739 #define E1000_IMC_DOCK E1000_ICR_DOCK /* Dock/Undock */
1740 #define E1000_IMC_RXD_FIFO_PAR0 E1000_ICR_RXD_FIFO_PAR0 /* queue 0 Rx descriptor FIFO parity error */
1741 #define E1000_IMC_TXD_FIFO_PAR0 E1000_ICR_TXD_FIFO_PAR0 /* queue 0 Tx descriptor FIFO parity error */
1742 #define E1000_IMC_HOST_ARB_PAR E1000_ICR_HOST_ARB_PAR /* host arb read buffer parity error */
1743 #define E1000_IMC_PB_PAR E1000_ICR_PB_PAR /* packet buffer parity error */
1744 #define E1000_IMC_RXD_FIFO_PAR1 E1000_ICR_RXD_FIFO_PAR1 /* queue 1 Rx descriptor FIFO parity error */
1745 #define E1000_IMC_TXD_FIFO_PAR1 E1000_ICR_TXD_FIFO_PAR1 /* queue 1 Tx descriptor FIFO parity error */
1747 /* Receive Control */
1748 #define E1000_RCTL_RST 0x00000001 /* Software reset */
1749 #define E1000_RCTL_EN 0x00000002 /* enable */
1750 #define E1000_RCTL_SBP 0x00000004 /* store bad packet */
1751 #define E1000_RCTL_UPE 0x00000008 /* unicast promiscuous enable */
1752 #define E1000_RCTL_MPE 0x00000010 /* multicast promiscuous enab */
1753 #define E1000_RCTL_LPE 0x00000020 /* long packet enable */
1754 #define E1000_RCTL_LBM_NO 0x00000000 /* no loopback mode */
1755 #define E1000_RCTL_LBM_MAC 0x00000040 /* MAC loopback mode */
1756 #define E1000_RCTL_LBM_SLP 0x00000080 /* serial link loopback mode */
1757 #define E1000_RCTL_LBM_TCVR 0x000000C0 /* tcvr loopback mode */
1758 #define E1000_RCTL_DTYP_MASK 0x00000C00 /* Descriptor type mask */
1759 #define E1000_RCTL_DTYP_PS 0x00000400 /* Packet Split descriptor */
1760 #define E1000_RCTL_RDMTS_HALF 0x00000000 /* rx desc min threshold size */
1761 #define E1000_RCTL_RDMTS_QUAT 0x00000100 /* rx desc min threshold size */
1762 #define E1000_RCTL_RDMTS_EIGTH 0x00000200 /* rx desc min threshold size */
1763 #define E1000_RCTL_MO_SHIFT 12 /* multicast offset shift */
1764 #define E1000_RCTL_MO_0 0x00000000 /* multicast offset 11:0 */
1765 #define E1000_RCTL_MO_1 0x00001000 /* multicast offset 12:1 */
1766 #define E1000_RCTL_MO_2 0x00002000 /* multicast offset 13:2 */
1767 #define E1000_RCTL_MO_3 0x00003000 /* multicast offset 15:4 */
1768 #define E1000_RCTL_MDR 0x00004000 /* multicast desc ring 0 */
1769 #define E1000_RCTL_BAM 0x00008000 /* broadcast enable */
1770 /* these buffer sizes are valid if E1000_RCTL_BSEX is 0 */
1771 #define E1000_RCTL_SZ_2048 0x00000000 /* rx buffer size 2048 */
1772 #define E1000_RCTL_SZ_1024 0x00010000 /* rx buffer size 1024 */
1773 #define E1000_RCTL_SZ_512 0x00020000 /* rx buffer size 512 */
1774 #define E1000_RCTL_SZ_256 0x00030000 /* rx buffer size 256 */
1775 /* these buffer sizes are valid if E1000_RCTL_BSEX is 1 */
1776 #define E1000_RCTL_SZ_16384 0x00010000 /* rx buffer size 16384 */
1777 #define E1000_RCTL_SZ_8192 0x00020000 /* rx buffer size 8192 */
1778 #define E1000_RCTL_SZ_4096 0x00030000 /* rx buffer size 4096 */
1779 #define E1000_RCTL_VFE 0x00040000 /* vlan filter enable */
1780 #define E1000_RCTL_CFIEN 0x00080000 /* canonical form enable */
1781 #define E1000_RCTL_CFI 0x00100000 /* canonical form indicator */
1782 #define E1000_RCTL_DPF 0x00400000 /* discard pause frames */
1783 #define E1000_RCTL_PMCF 0x00800000 /* pass MAC control frames */
1784 #define E1000_RCTL_BSEX 0x02000000 /* Buffer size extension */
1785 #define E1000_RCTL_SECRC 0x04000000 /* Strip Ethernet CRC */
1786 #define E1000_RCTL_FLXBUF_MASK 0x78000000 /* Flexible buffer size */
1787 #define E1000_RCTL_FLXBUF_SHIFT 27 /* Flexible buffer shift */
1789 /* Use byte values for the following shift parameters
1791 * psrctl |= (((ROUNDUP(value0, 128) >> E1000_PSRCTL_BSIZE0_SHIFT) &
1792 * E1000_PSRCTL_BSIZE0_MASK) |
1793 * ((ROUNDUP(value1, 1024) >> E1000_PSRCTL_BSIZE1_SHIFT) &
1794 * E1000_PSRCTL_BSIZE1_MASK) |
1795 * ((ROUNDUP(value2, 1024) << E1000_PSRCTL_BSIZE2_SHIFT) &
1796 * E1000_PSRCTL_BSIZE2_MASK) |
1797 * ((ROUNDUP(value3, 1024) << E1000_PSRCTL_BSIZE3_SHIFT) |;
1798 * E1000_PSRCTL_BSIZE3_MASK))
1799 * where value0 = [128..16256], default=256
1800 * value1 = [1024..64512], default=4096
1801 * value2 = [0..64512], default=4096
1802 * value3 = [0..64512], default=0
1805 #define E1000_PSRCTL_BSIZE0_MASK 0x0000007F
1806 #define E1000_PSRCTL_BSIZE1_MASK 0x00003F00
1807 #define E1000_PSRCTL_BSIZE2_MASK 0x003F0000
1808 #define E1000_PSRCTL_BSIZE3_MASK 0x3F000000
1810 #define E1000_PSRCTL_BSIZE0_SHIFT 7 /* Shift _right_ 7 */
1811 #define E1000_PSRCTL_BSIZE1_SHIFT 2 /* Shift _right_ 2 */
1812 #define E1000_PSRCTL_BSIZE2_SHIFT 6 /* Shift _left_ 6 */
1813 #define E1000_PSRCTL_BSIZE3_SHIFT 14 /* Shift _left_ 14 */
1815 /* SW_W_SYNC definitions */
1816 #define E1000_SWFW_EEP_SM 0x0001
1817 #define E1000_SWFW_PHY0_SM 0x0002
1818 #define E1000_SWFW_PHY1_SM 0x0004
1819 #define E1000_SWFW_MAC_CSR_SM 0x0008
1821 /* Receive Descriptor */
1822 #define E1000_RDT_DELAY 0x0000ffff /* Delay timer (1=1024us) */
1823 #define E1000_RDT_FPDB 0x80000000 /* Flush descriptor block */
1824 #define E1000_RDLEN_LEN 0x0007ff80 /* descriptor length */
1825 #define E1000_RDH_RDH 0x0000ffff /* receive descriptor head */
1826 #define E1000_RDT_RDT 0x0000ffff /* receive descriptor tail */
1829 #define E1000_FCRTH_RTH 0x0000FFF8 /* Mask Bits[15:3] for RTH */
1830 #define E1000_FCRTH_XFCE 0x80000000 /* External Flow Control Enable */
1831 #define E1000_FCRTL_RTL 0x0000FFF8 /* Mask Bits[15:3] for RTL */
1832 #define E1000_FCRTL_XONE 0x80000000 /* Enable XON frame transmission */
1834 /* Header split receive */
1835 #define E1000_RFCTL_ISCSI_DIS 0x00000001
1836 #define E1000_RFCTL_ISCSI_DWC_MASK 0x0000003E
1837 #define E1000_RFCTL_ISCSI_DWC_SHIFT 1
1838 #define E1000_RFCTL_NFSW_DIS 0x00000040
1839 #define E1000_RFCTL_NFSR_DIS 0x00000080
1840 #define E1000_RFCTL_NFS_VER_MASK 0x00000300
1841 #define E1000_RFCTL_NFS_VER_SHIFT 8
1842 #define E1000_RFCTL_IPV6_DIS 0x00000400
1843 #define E1000_RFCTL_IPV6_XSUM_DIS 0x00000800
1844 #define E1000_RFCTL_ACK_DIS 0x00001000
1845 #define E1000_RFCTL_ACKD_DIS 0x00002000
1846 #define E1000_RFCTL_IPFRSP_DIS 0x00004000
1847 #define E1000_RFCTL_EXTEN 0x00008000
1848 #define E1000_RFCTL_IPV6_EX_DIS 0x00010000
1849 #define E1000_RFCTL_NEW_IPV6_EXT_DIS 0x00020000
1851 /* Receive Descriptor Control */
1852 #define E1000_RXDCTL_PTHRESH 0x0000003F /* RXDCTL Prefetch Threshold */
1853 #define E1000_RXDCTL_HTHRESH 0x00003F00 /* RXDCTL Host Threshold */
1854 #define E1000_RXDCTL_WTHRESH 0x003F0000 /* RXDCTL Writeback Threshold */
1855 #define E1000_RXDCTL_GRAN 0x01000000 /* RXDCTL Granularity */
1857 /* Transmit Descriptor Control */
1858 #define E1000_TXDCTL_PTHRESH 0x000000FF /* TXDCTL Prefetch Threshold */
1859 #define E1000_TXDCTL_HTHRESH 0x0000FF00 /* TXDCTL Host Threshold */
1860 #define E1000_TXDCTL_WTHRESH 0x00FF0000 /* TXDCTL Writeback Threshold */
1861 #define E1000_TXDCTL_GRAN 0x01000000 /* TXDCTL Granularity */
1862 #define E1000_TXDCTL_LWTHRESH 0xFE000000 /* TXDCTL Low Threshold */
1863 #define E1000_TXDCTL_FULL_TX_DESC_WB 0x01010000 /* GRAN=1, WTHRESH=1 */
1864 #define E1000_TXDCTL_COUNT_DESC 0x00400000 /* Enable the counting of desc.
1865 still to be processed. */
1866 /* Transmit Configuration Word */
1867 #define E1000_TXCW_FD 0x00000020 /* TXCW full duplex */
1868 #define E1000_TXCW_HD 0x00000040 /* TXCW half duplex */
1869 #define E1000_TXCW_PAUSE 0x00000080 /* TXCW sym pause request */
1870 #define E1000_TXCW_ASM_DIR 0x00000100 /* TXCW astm pause direction */
1871 #define E1000_TXCW_PAUSE_MASK 0x00000180 /* TXCW pause request mask */
1872 #define E1000_TXCW_RF 0x00003000 /* TXCW remote fault */
1873 #define E1000_TXCW_NP 0x00008000 /* TXCW next page */
1874 #define E1000_TXCW_CW 0x0000ffff /* TxConfigWord mask */
1875 #define E1000_TXCW_TXC 0x40000000 /* Transmit Config control */
1876 #define E1000_TXCW_ANE 0x80000000 /* Auto-neg enable */
1878 /* Receive Configuration Word */
1879 #define E1000_RXCW_CW 0x0000ffff /* RxConfigWord mask */
1880 #define E1000_RXCW_NC 0x04000000 /* Receive config no carrier */
1881 #define E1000_RXCW_IV 0x08000000 /* Receive config invalid */
1882 #define E1000_RXCW_CC 0x10000000 /* Receive config change */
1883 #define E1000_RXCW_C 0x20000000 /* Receive config */
1884 #define E1000_RXCW_SYNCH 0x40000000 /* Receive config synch */
1885 #define E1000_RXCW_ANC 0x80000000 /* Auto-neg complete */
1887 /* Transmit Control */
1888 #define E1000_TCTL_RST 0x00000001 /* software reset */
1889 #define E1000_TCTL_EN 0x00000002 /* enable tx */
1890 #define E1000_TCTL_BCE 0x00000004 /* busy check enable */
1891 #define E1000_TCTL_PSP 0x00000008 /* pad short packets */
1892 #define E1000_TCTL_CT 0x00000ff0 /* collision threshold */
1893 #define E1000_TCTL_COLD 0x003ff000 /* collision distance */
1894 #define E1000_TCTL_SWXOFF 0x00400000 /* SW Xoff transmission */
1895 #define E1000_TCTL_PBE 0x00800000 /* Packet Burst Enable */
1896 #define E1000_TCTL_RTLC 0x01000000 /* Re-transmit on late collision */
1897 #define E1000_TCTL_NRTU 0x02000000 /* No Re-transmit on underrun */
1898 #define E1000_TCTL_MULR 0x10000000 /* Multiple request support */
1899 /* Extended Transmit Control */
1900 #define E1000_TCTL_EXT_BST_MASK 0x000003FF /* Backoff Slot Time */
1901 #define E1000_TCTL_EXT_GCEX_MASK 0x000FFC00 /* Gigabit Carry Extend Padding */
1903 #define DEFAULT_80003ES2LAN_TCTL_EXT_GCEX 0x00010000
1905 /* Receive Checksum Control */
1906 #define E1000_RXCSUM_PCSS_MASK 0x000000FF /* Packet Checksum Start */
1907 #define E1000_RXCSUM_IPOFL 0x00000100 /* IPv4 checksum offload */
1908 #define E1000_RXCSUM_TUOFL 0x00000200 /* TCP / UDP checksum offload */
1909 #define E1000_RXCSUM_IPV6OFL 0x00000400 /* IPv6 checksum offload */
1910 #define E1000_RXCSUM_IPPCSE 0x00001000 /* IP payload checksum enable */
1911 #define E1000_RXCSUM_PCSD 0x00002000 /* packet checksum disabled */
1913 /* Multiple Receive Queue Control */
1914 #define E1000_MRQC_ENABLE_MASK 0x00000003
1915 #define E1000_MRQC_ENABLE_RSS_2Q 0x00000001
1916 #define E1000_MRQC_ENABLE_RSS_INT 0x00000004
1917 #define E1000_MRQC_RSS_FIELD_MASK 0xFFFF0000
1918 #define E1000_MRQC_RSS_FIELD_IPV4_TCP 0x00010000
1919 #define E1000_MRQC_RSS_FIELD_IPV4 0x00020000
1920 #define E1000_MRQC_RSS_FIELD_IPV6_TCP 0x00040000
1921 #define E1000_MRQC_RSS_FIELD_IPV6_EX 0x00080000
1922 #define E1000_MRQC_RSS_FIELD_IPV6 0x00100000
1924 /* Definitions for power management and wakeup registers */
1925 /* Wake Up Control */
1926 #define E1000_WUC_APME 0x00000001 /* APM Enable */
1927 #define E1000_WUC_PME_EN 0x00000002 /* PME Enable */
1928 #define E1000_WUC_PME_STATUS 0x00000004 /* PME Status */
1929 #define E1000_WUC_APMPME 0x00000008 /* Assert PME on APM Wakeup */
1930 #define E1000_WUC_SPM 0x80000000 /* Enable SPM */
1932 /* Wake Up Filter Control */
1933 #define E1000_WUFC_LNKC 0x00000001 /* Link Status Change Wakeup Enable */
1934 #define E1000_WUFC_MAG 0x00000002 /* Magic Packet Wakeup Enable */
1935 #define E1000_WUFC_EX 0x00000004 /* Directed Exact Wakeup Enable */
1936 #define E1000_WUFC_MC 0x00000008 /* Directed Multicast Wakeup Enable */
1937 #define E1000_WUFC_BC 0x00000010 /* Broadcast Wakeup Enable */
1938 #define E1000_WUFC_ARP 0x00000020 /* ARP Request Packet Wakeup Enable */
1939 #define E1000_WUFC_IPV4 0x00000040 /* Directed IPv4 Packet Wakeup Enable */
1940 #define E1000_WUFC_IPV6 0x00000080 /* Directed IPv6 Packet Wakeup Enable */
1941 #define E1000_WUFC_IGNORE_TCO 0x00008000 /* Ignore WakeOn TCO packets */
1942 #define E1000_WUFC_FLX0 0x00010000 /* Flexible Filter 0 Enable */
1943 #define E1000_WUFC_FLX1 0x00020000 /* Flexible Filter 1 Enable */
1944 #define E1000_WUFC_FLX2 0x00040000 /* Flexible Filter 2 Enable */
1945 #define E1000_WUFC_FLX3 0x00080000 /* Flexible Filter 3 Enable */
1946 #define E1000_WUFC_ALL_FILTERS 0x000F00FF /* Mask for all wakeup filters */
1947 #define E1000_WUFC_FLX_OFFSET 16 /* Offset to the Flexible Filters bits */
1948 #define E1000_WUFC_FLX_FILTERS 0x000F0000 /* Mask for the 4 flexible filters */
1950 /* Wake Up Status */
1951 #define E1000_WUS_LNKC 0x00000001 /* Link Status Changed */
1952 #define E1000_WUS_MAG 0x00000002 /* Magic Packet Received */
1953 #define E1000_WUS_EX 0x00000004 /* Directed Exact Received */
1954 #define E1000_WUS_MC 0x00000008 /* Directed Multicast Received */
1955 #define E1000_WUS_BC 0x00000010 /* Broadcast Received */
1956 #define E1000_WUS_ARP 0x00000020 /* ARP Request Packet Received */
1957 #define E1000_WUS_IPV4 0x00000040 /* Directed IPv4 Packet Wakeup Received */
1958 #define E1000_WUS_IPV6 0x00000080 /* Directed IPv6 Packet Wakeup Received */
1959 #define E1000_WUS_FLX0 0x00010000 /* Flexible Filter 0 Match */
1960 #define E1000_WUS_FLX1 0x00020000 /* Flexible Filter 1 Match */
1961 #define E1000_WUS_FLX2 0x00040000 /* Flexible Filter 2 Match */
1962 #define E1000_WUS_FLX3 0x00080000 /* Flexible Filter 3 Match */
1963 #define E1000_WUS_FLX_FILTERS 0x000F0000 /* Mask for the 4 flexible filters */
1965 /* Management Control */
1966 #define E1000_MANC_SMBUS_EN 0x00000001 /* SMBus Enabled - RO */
1967 #define E1000_MANC_ASF_EN 0x00000002 /* ASF Enabled - RO */
1968 #define E1000_MANC_R_ON_FORCE 0x00000004 /* Reset on Force TCO - RO */
1969 #define E1000_MANC_RMCP_EN 0x00000100 /* Enable RCMP 026Fh Filtering */
1970 #define E1000_MANC_0298_EN 0x00000200 /* Enable RCMP 0298h Filtering */
1971 #define E1000_MANC_IPV4_EN 0x00000400 /* Enable IPv4 */
1972 #define E1000_MANC_IPV6_EN 0x00000800 /* Enable IPv6 */
1973 #define E1000_MANC_SNAP_EN 0x00001000 /* Accept LLC/SNAP */
1974 #define E1000_MANC_ARP_EN 0x00002000 /* Enable ARP Request Filtering */
1975 #define E1000_MANC_NEIGHBOR_EN 0x00004000 /* Enable Neighbor Discovery
1977 #define E1000_MANC_ARP_RES_EN 0x00008000 /* Enable ARP response Filtering */
1978 #define E1000_MANC_TCO_RESET 0x00010000 /* TCO Reset Occurred */
1979 #define E1000_MANC_RCV_TCO_EN 0x00020000 /* Receive TCO Packets Enabled */
1980 #define E1000_MANC_REPORT_STATUS 0x00040000 /* Status Reporting Enabled */
1981 #define E1000_MANC_RCV_ALL 0x00080000 /* Receive All Enabled */
1982 #define E1000_MANC_BLK_PHY_RST_ON_IDE 0x00040000 /* Block phy resets */
1983 #define E1000_MANC_EN_MAC_ADDR_FILTER 0x00100000 /* Enable MAC address
1985 #define E1000_MANC_EN_MNG2HOST 0x00200000 /* Enable MNG packets to host
1987 #define E1000_MANC_EN_IP_ADDR_FILTER 0x00400000 /* Enable IP address
1989 #define E1000_MANC_EN_XSUM_FILTER 0x00800000 /* Enable checksum filtering */
1990 #define E1000_MANC_BR_EN 0x01000000 /* Enable broadcast filtering */
1991 #define E1000_MANC_SMB_REQ 0x01000000 /* SMBus Request */
1992 #define E1000_MANC_SMB_GNT 0x02000000 /* SMBus Grant */
1993 #define E1000_MANC_SMB_CLK_IN 0x04000000 /* SMBus Clock In */
1994 #define E1000_MANC_SMB_DATA_IN 0x08000000 /* SMBus Data In */
1995 #define E1000_MANC_SMB_DATA_OUT 0x10000000 /* SMBus Data Out */
1996 #define E1000_MANC_SMB_CLK_OUT 0x20000000 /* SMBus Clock Out */
1998 #define E1000_MANC_SMB_DATA_OUT_SHIFT 28 /* SMBus Data Out Shift */
1999 #define E1000_MANC_SMB_CLK_OUT_SHIFT 29 /* SMBus Clock Out Shift */
2001 /* SW Semaphore Register */
2002 #define E1000_SWSM_SMBI 0x00000001 /* Driver Semaphore bit */
2003 #define E1000_SWSM_SWESMBI 0x00000002 /* FW Semaphore bit */
2004 #define E1000_SWSM_WMNG 0x00000004 /* Wake MNG Clock */
2005 #define E1000_SWSM_DRV_LOAD 0x00000008 /* Driver Loaded Bit */
2007 /* FW Semaphore Register */
2008 #define E1000_FWSM_MODE_MASK 0x0000000E /* FW mode */
2009 #define E1000_FWSM_MODE_SHIFT 1
2010 #define E1000_FWSM_FW_VALID 0x00008000 /* FW established a valid mode */
2012 /* FFLT Debug Register */
2013 #define E1000_FFLT_DBG_INVC 0x00100000 /* Invalid /C/ code handling */
2016 e1000_mng_mode_none = 0,
2019 e1000_mng_mode_ipmi,
2020 e1000_mng_mode_host_interface_only
2023 /* Host Inteface Control Register */
2024 #define E1000_HICR_EN 0x00000001 /* Enable Bit - RO */
2025 #define E1000_HICR_C 0x00000002 /* Driver sets this bit when done
2026 * to put command in RAM */
2027 #define E1000_HICR_SV 0x00000004 /* Status Validity */
2028 #define E1000_HICR_FWR 0x00000080 /* FW reset. Set by the Host */
2030 /* Host Interface Command Interface - Address range 0x8800-0x8EFF */
2031 #define E1000_HI_MAX_DATA_LENGTH 252 /* Host Interface data length */
2032 #define E1000_HI_MAX_BLOCK_BYTE_LENGTH 1792 /* Number of bytes in range */
2033 #define E1000_HI_MAX_BLOCK_DWORD_LENGTH 448 /* Number of dwords in range */
2034 #define E1000_HI_COMMAND_TIMEOUT 500 /* Time in ms to process HI command */
2036 struct e1000_host_command_header {
2038 uint8_t command_length;
2039 uint8_t command_options; /* I/F bits for command, status for return */
2042 struct e1000_host_command_info {
2043 struct e1000_host_command_header command_header; /* Command Head/Command Result Head has 4 bytes */
2044 uint8_t command_data[E1000_HI_MAX_DATA_LENGTH]; /* Command data can length 0..252 */
2047 /* Host SMB register #0 */
2048 #define E1000_HSMC0R_CLKIN 0x00000001 /* SMB Clock in */
2049 #define E1000_HSMC0R_DATAIN 0x00000002 /* SMB Data in */
2050 #define E1000_HSMC0R_DATAOUT 0x00000004 /* SMB Data out */
2051 #define E1000_HSMC0R_CLKOUT 0x00000008 /* SMB Clock out */
2053 /* Host SMB register #1 */
2054 #define E1000_HSMC1R_CLKIN E1000_HSMC0R_CLKIN
2055 #define E1000_HSMC1R_DATAIN E1000_HSMC0R_DATAIN
2056 #define E1000_HSMC1R_DATAOUT E1000_HSMC0R_DATAOUT
2057 #define E1000_HSMC1R_CLKOUT E1000_HSMC0R_CLKOUT
2059 /* FW Status Register */
2060 #define E1000_FWSTS_FWS_MASK 0x000000FF /* FW Status */
2062 /* Wake Up Packet Length */
2063 #define E1000_WUPL_LENGTH_MASK 0x0FFF /* Only the lower 12 bits are valid */
2065 #define E1000_MDALIGN 4096
2067 /* PCI-Ex registers */
2069 /* PCI-Ex Control Register */
2070 #define E1000_GCR_RXD_NO_SNOOP 0x00000001
2071 #define E1000_GCR_RXDSCW_NO_SNOOP 0x00000002
2072 #define E1000_GCR_RXDSCR_NO_SNOOP 0x00000004
2073 #define E1000_GCR_TXD_NO_SNOOP 0x00000008
2074 #define E1000_GCR_TXDSCW_NO_SNOOP 0x00000010
2075 #define E1000_GCR_TXDSCR_NO_SNOOP 0x00000020
2077 #define PCI_EX_NO_SNOOP_ALL (E1000_GCR_RXD_NO_SNOOP | \
2078 E1000_GCR_RXDSCW_NO_SNOOP | \
2079 E1000_GCR_RXDSCR_NO_SNOOP | \
2080 E1000_GCR TXD_NO_SNOOP | \
2081 E1000_GCR_TXDSCW_NO_SNOOP | \
2082 E1000_GCR_TXDSCR_NO_SNOOP)
2084 #define E1000_GCR_L1_ACT_WITHOUT_L0S_RX 0x08000000
2085 /* Function Active and Power State to MNG */
2086 #define E1000_FACTPS_FUNC0_POWER_STATE_MASK 0x00000003
2087 #define E1000_FACTPS_LAN0_VALID 0x00000004
2088 #define E1000_FACTPS_FUNC0_AUX_EN 0x00000008
2089 #define E1000_FACTPS_FUNC1_POWER_STATE_MASK 0x000000C0
2090 #define E1000_FACTPS_FUNC1_POWER_STATE_SHIFT 6
2091 #define E1000_FACTPS_LAN1_VALID 0x00000100
2092 #define E1000_FACTPS_FUNC1_AUX_EN 0x00000200
2093 #define E1000_FACTPS_FUNC2_POWER_STATE_MASK 0x00003000
2094 #define E1000_FACTPS_FUNC2_POWER_STATE_SHIFT 12
2095 #define E1000_FACTPS_IDE_ENABLE 0x00004000
2096 #define E1000_FACTPS_FUNC2_AUX_EN 0x00008000
2097 #define E1000_FACTPS_FUNC3_POWER_STATE_MASK 0x000C0000
2098 #define E1000_FACTPS_FUNC3_POWER_STATE_SHIFT 18
2099 #define E1000_FACTPS_SP_ENABLE 0x00100000
2100 #define E1000_FACTPS_FUNC3_AUX_EN 0x00200000
2101 #define E1000_FACTPS_FUNC4_POWER_STATE_MASK 0x03000000
2102 #define E1000_FACTPS_FUNC4_POWER_STATE_SHIFT 24
2103 #define E1000_FACTPS_IPMI_ENABLE 0x04000000
2104 #define E1000_FACTPS_FUNC4_AUX_EN 0x08000000
2105 #define E1000_FACTPS_MNGCG 0x20000000
2106 #define E1000_FACTPS_LAN_FUNC_SEL 0x40000000
2107 #define E1000_FACTPS_PM_STATE_CHANGED 0x80000000
2109 /* EEPROM Commands - Microwire */
2110 #define EEPROM_READ_OPCODE_MICROWIRE 0x6 /* EEPROM read opcode */
2111 #define EEPROM_WRITE_OPCODE_MICROWIRE 0x5 /* EEPROM write opcode */
2112 #define EEPROM_ERASE_OPCODE_MICROWIRE 0x7 /* EEPROM erase opcode */
2113 #define EEPROM_EWEN_OPCODE_MICROWIRE 0x13 /* EEPROM erase/write enable */
2114 #define EEPROM_EWDS_OPCODE_MICROWIRE 0x10 /* EEPROM erast/write disable */
2116 /* EEPROM Commands - SPI */
2117 #define EEPROM_MAX_RETRY_SPI 5000 /* Max wait of 5ms, for RDY signal */
2118 #define EEPROM_READ_OPCODE_SPI 0x03 /* EEPROM read opcode */
2119 #define EEPROM_WRITE_OPCODE_SPI 0x02 /* EEPROM write opcode */
2120 #define EEPROM_A8_OPCODE_SPI 0x08 /* opcode bit-3 = address bit-8 */
2121 #define EEPROM_WREN_OPCODE_SPI 0x06 /* EEPROM set Write Enable latch */
2122 #define EEPROM_WRDI_OPCODE_SPI 0x04 /* EEPROM reset Write Enable latch */
2123 #define EEPROM_RDSR_OPCODE_SPI 0x05 /* EEPROM read Status register */
2124 #define EEPROM_WRSR_OPCODE_SPI 0x01 /* EEPROM write Status register */
2125 #define EEPROM_ERASE4K_OPCODE_SPI 0x20 /* EEPROM ERASE 4KB */
2126 #define EEPROM_ERASE64K_OPCODE_SPI 0xD8 /* EEPROM ERASE 64KB */
2127 #define EEPROM_ERASE256_OPCODE_SPI 0xDB /* EEPROM ERASE 256B */
2129 /* EEPROM Size definitions */
2130 #define EEPROM_WORD_SIZE_SHIFT 6
2131 #define EEPROM_SIZE_SHIFT 10
2132 #define EEPROM_SIZE_MASK 0x1C00
2134 /* EEPROM Word Offsets */
2135 #define EEPROM_COMPAT 0x0003
2136 #define EEPROM_ID_LED_SETTINGS 0x0004
2137 #define EEPROM_VERSION 0x0005
2138 #define EEPROM_SERDES_AMPLITUDE 0x0006 /* For SERDES output amplitude adjustment. */
2139 #define EEPROM_PHY_CLASS_WORD 0x0007
2140 #define EEPROM_INIT_CONTROL1_REG 0x000A
2141 #define EEPROM_INIT_CONTROL2_REG 0x000F
2142 #define EEPROM_INIT_CONTROL3_PORT_B 0x0014
2143 #define EEPROM_INIT_3GIO_3 0x001A
2144 #define EEPROM_INIT_CONTROL3_PORT_A 0x0024
2145 #define EEPROM_CFG 0x0012
2146 #define EEPROM_FLASH_VERSION 0x0032
2147 #define EEPROM_CHECKSUM_REG 0x003F
2149 #define E1000_EEPROM_CFG_DONE 0x00040000 /* MNG config cycle done */
2150 #define E1000_EEPROM_CFG_DONE_PORT_1 0x00080000 /* ...for second port */
2152 /* Word definitions for ID LED Settings */
2153 #define ID_LED_RESERVED_0000 0x0000
2154 #define ID_LED_RESERVED_FFFF 0xFFFF
2155 #define ID_LED_DEFAULT ((ID_LED_OFF1_ON2 << 12) | \
2156 (ID_LED_OFF1_OFF2 << 8) | \
2157 (ID_LED_DEF1_DEF2 << 4) | \
2159 #define ID_LED_DEF1_DEF2 0x1
2160 #define ID_LED_DEF1_ON2 0x2
2161 #define ID_LED_DEF1_OFF2 0x3
2162 #define ID_LED_ON1_DEF2 0x4
2163 #define ID_LED_ON1_ON2 0x5
2164 #define ID_LED_ON1_OFF2 0x6
2165 #define ID_LED_OFF1_DEF2 0x7
2166 #define ID_LED_OFF1_ON2 0x8
2167 #define ID_LED_OFF1_OFF2 0x9
2169 #define IGP_ACTIVITY_LED_MASK 0xFFFFF0FF
2170 #define IGP_ACTIVITY_LED_ENABLE 0x0300
2171 #define IGP_LED3_MODE 0x07000000
2174 /* Mask bits for SERDES amplitude adjustment in Word 6 of the EEPROM */
2175 #define EEPROM_SERDES_AMPLITUDE_MASK 0x000F
2177 /* Mask bit for PHY class in Word 7 of the EEPROM */
2178 #define EEPROM_PHY_CLASS_A 0x8000
2180 /* Mask bits for fields in Word 0x0a of the EEPROM */
2181 #define EEPROM_WORD0A_ILOS 0x0010
2182 #define EEPROM_WORD0A_SWDPIO 0x01E0
2183 #define EEPROM_WORD0A_LRST 0x0200
2184 #define EEPROM_WORD0A_FD 0x0400
2185 #define EEPROM_WORD0A_66MHZ 0x0800
2187 /* Mask bits for fields in Word 0x0f of the EEPROM */
2188 #define EEPROM_WORD0F_PAUSE_MASK 0x3000
2189 #define EEPROM_WORD0F_PAUSE 0x1000
2190 #define EEPROM_WORD0F_ASM_DIR 0x2000
2191 #define EEPROM_WORD0F_ANE 0x0800
2192 #define EEPROM_WORD0F_SWPDIO_EXT 0x00F0
2194 /* Mask bits for fields in Word 0x1a of the EEPROM */
2195 #define EEPROM_WORD1A_ASPM_MASK 0x000C
2197 /* For checksumming, the sum of all words in the EEPROM should equal 0xBABA. */
2198 #define EEPROM_SUM 0xBABA
2200 /* EEPROM Map defines (WORD OFFSETS)*/
2201 #define EEPROM_NODE_ADDRESS_BYTE_0 0
2202 #define EEPROM_PBA_BYTE_1 8
2204 #define EEPROM_RESERVED_WORD 0xFFFF
2206 /* EEPROM Map Sizes (Byte Counts) */
2209 /* Collision related configuration parameters */
2210 #define E1000_COLLISION_THRESHOLD 15
2211 #define E1000_CT_SHIFT 4
2212 /* Collision distance is a 0-based value that applies to
2213 * half-duplex-capable hardware only. */
2214 #define E1000_COLLISION_DISTANCE 63
2215 #define E1000_COLLISION_DISTANCE_82542 64
2216 #define E1000_FDX_COLLISION_DISTANCE E1000_COLLISION_DISTANCE
2217 #define E1000_HDX_COLLISION_DISTANCE E1000_COLLISION_DISTANCE
2218 #define E1000_COLD_SHIFT 12
2220 /* Number of Transmit and Receive Descriptors must be a multiple of 8 */
2221 #define REQ_TX_DESCRIPTOR_MULTIPLE 8
2222 #define REQ_RX_DESCRIPTOR_MULTIPLE 8
2224 /* Default values for the transmit IPG register */
2225 #define DEFAULT_82542_TIPG_IPGT 10
2226 #define DEFAULT_82543_TIPG_IPGT_FIBER 9
2227 #define DEFAULT_82543_TIPG_IPGT_COPPER 8
2229 #define E1000_TIPG_IPGT_MASK 0x000003FF
2230 #define E1000_TIPG_IPGR1_MASK 0x000FFC00
2231 #define E1000_TIPG_IPGR2_MASK 0x3FF00000
2233 #define DEFAULT_82542_TIPG_IPGR1 2
2234 #define DEFAULT_82543_TIPG_IPGR1 8
2235 #define E1000_TIPG_IPGR1_SHIFT 10
2237 #define DEFAULT_82542_TIPG_IPGR2 10
2238 #define DEFAULT_82543_TIPG_IPGR2 6
2239 #define DEFAULT_80003ES2LAN_TIPG_IPGR2 7
2240 #define E1000_TIPG_IPGR2_SHIFT 20
2242 #define DEFAULT_80003ES2LAN_TIPG_IPGT_10_100 0x00000009
2243 #define DEFAULT_80003ES2LAN_TIPG_IPGT_1000 0x00000008
2244 #define E1000_TXDMAC_DPP 0x00000001
2246 /* Adaptive IFS defines */
2247 #define TX_THRESHOLD_START 8
2248 #define TX_THRESHOLD_INCREMENT 10
2249 #define TX_THRESHOLD_DECREMENT 1
2250 #define TX_THRESHOLD_STOP 190
2251 #define TX_THRESHOLD_DISABLE 0
2252 #define TX_THRESHOLD_TIMER_MS 10000
2253 #define MIN_NUM_XMITS 1000
2259 /* Extended Configuration Control and Size */
2260 #define E1000_EXTCNF_CTRL_PCIE_WRITE_ENABLE 0x00000001
2261 #define E1000_EXTCNF_CTRL_PHY_WRITE_ENABLE 0x00000002
2262 #define E1000_EXTCNF_CTRL_D_UD_ENABLE 0x00000004
2263 #define E1000_EXTCNF_CTRL_D_UD_LATENCY 0x00000008
2264 #define E1000_EXTCNF_CTRL_D_UD_OWNER 0x00000010
2265 #define E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP 0x00000020
2266 #define E1000_EXTCNF_CTRL_MDIO_HW_OWNERSHIP 0x00000040
2267 #define E1000_EXTCNF_CTRL_EXT_CNF_POINTER 0x1FFF0000
2269 #define E1000_EXTCNF_SIZE_EXT_PHY_LENGTH 0x000000FF
2270 #define E1000_EXTCNF_SIZE_EXT_DOCK_LENGTH 0x0000FF00
2271 #define E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH 0x00FF0000
2274 #define E1000_PBA_12K 0x000C /* 12KB, default Rx allocation */
2275 #define E1000_PBA_16K 0x0010 /* 16KB, default TX allocation */
2276 #define E1000_PBA_22K 0x0016
2277 #define E1000_PBA_24K 0x0018
2278 #define E1000_PBA_30K 0x001E
2279 #define E1000_PBA_32K 0x0020
2280 #define E1000_PBA_38K 0x0026
2281 #define E1000_PBA_40K 0x0028
2282 #define E1000_PBA_48K 0x0030 /* 48KB, default RX allocation */
2284 /* Flow Control Constants */
2285 #define FLOW_CONTROL_ADDRESS_LOW 0x00C28001
2286 #define FLOW_CONTROL_ADDRESS_HIGH 0x00000100
2287 #define FLOW_CONTROL_TYPE 0x8808
2289 /* The historical defaults for the flow control values are given below. */
2290 #define FC_DEFAULT_HI_THRESH (0x8000) /* 32KB */
2291 #define FC_DEFAULT_LO_THRESH (0x4000) /* 16KB */
2292 #define FC_DEFAULT_TX_TIMER (0x100) /* ~130 us */
2294 /* PCIX Config space */
2295 #define PCIX_COMMAND_REGISTER 0xE6
2296 #define PCIX_STATUS_REGISTER_LO 0xE8
2297 #define PCIX_STATUS_REGISTER_HI 0xEA
2299 #define PCIX_COMMAND_MMRBC_MASK 0x000C
2300 #define PCIX_COMMAND_MMRBC_SHIFT 0x2
2301 #define PCIX_STATUS_HI_MMRBC_MASK 0x0060
2302 #define PCIX_STATUS_HI_MMRBC_SHIFT 0x5
2303 #define PCIX_STATUS_HI_MMRBC_4K 0x3
2304 #define PCIX_STATUS_HI_MMRBC_2K 0x2
2307 /* Number of bits required to shift right the "pause" bits from the
2308 * EEPROM (bits 13:12) to the "pause" (bits 8:7) field in the TXCW register.
2310 #define PAUSE_SHIFT 5
2312 /* Number of bits required to shift left the "SWDPIO" bits from the
2313 * EEPROM (bits 8:5) to the "SWDPIO" (bits 25:22) field in the CTRL register.
2315 #define SWDPIO_SHIFT 17
2317 /* Number of bits required to shift left the "SWDPIO_EXT" bits from the
2318 * EEPROM word F (bits 7:4) to the bits 11:8 of The Extended CTRL register.
2320 #define SWDPIO__EXT_SHIFT 4
2322 /* Number of bits required to shift left the "ILOS" bit from the EEPROM
2323 * (bit 4) to the "ILOS" (bit 7) field in the CTRL register.
2325 #define ILOS_SHIFT 3
2328 #define RECEIVE_BUFFER_ALIGN_SIZE (256)
2330 /* Number of milliseconds we wait for auto-negotiation to complete */
2331 #define LINK_UP_TIMEOUT 500
2333 /* Number of 100 microseconds we wait for PCI Express master disable */
2334 #define MASTER_DISABLE_TIMEOUT 800
2335 /* Number of milliseconds we wait for Eeprom auto read bit done after MAC reset */
2336 #define AUTO_READ_DONE_TIMEOUT 10
2337 /* Number of milliseconds we wait for PHY configuration done after MAC reset */
2338 #define PHY_CFG_TIMEOUT 40
2340 #define E1000_TX_BUFFER_SIZE ((uint32_t)1514)
2342 /* The carrier extension symbol, as received by the NIC. */
2343 #define CARRIER_EXTENSION 0x0F
2345 /* TBI_ACCEPT macro definition:
2347 * This macro requires:
2348 * adapter = a pointer to struct e1000_hw
2349 * status = the 8 bit status field of the RX descriptor with EOP set
2350 * error = the 8 bit error field of the RX descriptor with EOP set
2351 * length = the sum of all the length fields of the RX descriptors that
2352 * make up the current frame
2353 * last_byte = the last byte of the frame DMAed by the hardware
2354 * max_frame_length = the maximum frame length we want to accept.
2355 * min_frame_length = the minimum frame length we want to accept.
2357 * This macro is a conditional that should be used in the interrupt
2358 * handler's Rx processing routine when RxErrors have been detected.
2363 * accept_frame = TRUE;
2364 * e1000_tbi_adjust_stats(adapter, MacAddress);
2367 * accept_frame = FALSE;
2372 #define TBI_ACCEPT(adapter, status, errors, length, last_byte) \
2373 ((adapter)->tbi_compatibility_on && \
2374 (((errors) & E1000_RXD_ERR_FRAME_ERR_MASK) == E1000_RXD_ERR_CE) && \
2375 ((last_byte) == CARRIER_EXTENSION) && \
2376 (((status) & E1000_RXD_STAT_VP) ? \
2377 (((length) > ((adapter)->min_frame_size - VLAN_TAG_SIZE)) && \
2378 ((length) <= ((adapter)->max_frame_size + 1))) : \
2379 (((length) > (adapter)->min_frame_size) && \
2380 ((length) <= ((adapter)->max_frame_size + VLAN_TAG_SIZE + 1)))))
2383 /* Structures, enums, and macros for the PHY */
2385 /* Bit definitions for the Management Data IO (MDIO) and Management Data
2386 * Clock (MDC) pins in the Device Control Register.
2388 #define E1000_CTRL_PHY_RESET_DIR E1000_CTRL_SWDPIO0
2389 #define E1000_CTRL_PHY_RESET E1000_CTRL_SWDPIN0
2390 #define E1000_CTRL_MDIO_DIR E1000_CTRL_SWDPIO2
2391 #define E1000_CTRL_MDIO E1000_CTRL_SWDPIN2
2392 #define E1000_CTRL_MDC_DIR E1000_CTRL_SWDPIO3
2393 #define E1000_CTRL_MDC E1000_CTRL_SWDPIN3
2394 #define E1000_CTRL_PHY_RESET_DIR4 E1000_CTRL_EXT_SDP4_DIR
2395 #define E1000_CTRL_PHY_RESET4 E1000_CTRL_EXT_SDP4_DATA
2397 /* PHY 1000 MII Register/Bit Definitions */
2398 /* PHY Registers defined by IEEE */
2399 #define PHY_CTRL 0x00 /* Control Register */
2400 #define PHY_STATUS 0x01 /* Status Regiser */
2401 #define PHY_ID1 0x02 /* Phy Id Reg (word 1) */
2402 #define PHY_ID2 0x03 /* Phy Id Reg (word 2) */
2403 #define PHY_AUTONEG_ADV 0x04 /* Autoneg Advertisement */
2404 #define PHY_LP_ABILITY 0x05 /* Link Partner Ability (Base Page) */
2405 #define PHY_AUTONEG_EXP 0x06 /* Autoneg Expansion Reg */
2406 #define PHY_NEXT_PAGE_TX 0x07 /* Next Page TX */
2407 #define PHY_LP_NEXT_PAGE 0x08 /* Link Partner Next Page */
2408 #define PHY_1000T_CTRL 0x09 /* 1000Base-T Control Reg */
2409 #define PHY_1000T_STATUS 0x0A /* 1000Base-T Status Reg */
2410 #define PHY_EXT_STATUS 0x0F /* Extended Status Reg */
2412 #define MAX_PHY_REG_ADDRESS 0x1F /* 5 bit address bus (0-0x1F) */
2413 #define MAX_PHY_MULTI_PAGE_REG 0xF /* Registers equal on all pages */
2415 /* M88E1000 Specific Registers */
2416 #define M88E1000_PHY_SPEC_CTRL 0x10 /* PHY Specific Control Register */
2417 #define M88E1000_PHY_SPEC_STATUS 0x11 /* PHY Specific Status Register */
2418 #define M88E1000_INT_ENABLE 0x12 /* Interrupt Enable Register */
2419 #define M88E1000_INT_STATUS 0x13 /* Interrupt Status Register */
2420 #define M88E1000_EXT_PHY_SPEC_CTRL 0x14 /* Extended PHY Specific Control */
2421 #define M88E1000_RX_ERR_CNTR 0x15 /* Receive Error Counter */
2423 #define M88E1000_PHY_EXT_CTRL 0x1A /* PHY extend control register */
2424 #define M88E1000_PHY_PAGE_SELECT 0x1D /* Reg 29 for page number setting */
2425 #define M88E1000_PHY_GEN_CONTROL 0x1E /* Its meaning depends on reg 29 */
2426 #define M88E1000_PHY_VCO_REG_BIT8 0x100 /* Bits 8 & 11 are adjusted for */
2427 #define M88E1000_PHY_VCO_REG_BIT11 0x800 /* improved BER performance */
2429 #define IGP01E1000_IEEE_REGS_PAGE 0x0000
2430 #define IGP01E1000_IEEE_RESTART_AUTONEG 0x3300
2431 #define IGP01E1000_IEEE_FORCE_GIGA 0x0140
2433 /* IGP01E1000 Specific Registers */
2434 #define IGP01E1000_PHY_PORT_CONFIG 0x10 /* PHY Specific Port Config Register */
2435 #define IGP01E1000_PHY_PORT_STATUS 0x11 /* PHY Specific Status Register */
2436 #define IGP01E1000_PHY_PORT_CTRL 0x12 /* PHY Specific Control Register */
2437 #define IGP01E1000_PHY_LINK_HEALTH 0x13 /* PHY Link Health Register */
2438 #define IGP01E1000_GMII_FIFO 0x14 /* GMII FIFO Register */
2439 #define IGP01E1000_PHY_CHANNEL_QUALITY 0x15 /* PHY Channel Quality Register */
2440 #define IGP02E1000_PHY_POWER_MGMT 0x19
2441 #define IGP01E1000_PHY_PAGE_SELECT 0x1F /* PHY Page Select Core Register */
2443 /* IGP01E1000 AGC Registers - stores the cable length values*/
2444 #define IGP01E1000_PHY_AGC_A 0x1172
2445 #define IGP01E1000_PHY_AGC_B 0x1272
2446 #define IGP01E1000_PHY_AGC_C 0x1472
2447 #define IGP01E1000_PHY_AGC_D 0x1872
2449 /* IGP02E1000 AGC Registers for cable length values */
2450 #define IGP02E1000_PHY_AGC_A 0x11B1
2451 #define IGP02E1000_PHY_AGC_B 0x12B1
2452 #define IGP02E1000_PHY_AGC_C 0x14B1
2453 #define IGP02E1000_PHY_AGC_D 0x18B1
2455 /* IGP01E1000 DSP Reset Register */
2456 #define IGP01E1000_PHY_DSP_RESET 0x1F33
2457 #define IGP01E1000_PHY_DSP_SET 0x1F71
2458 #define IGP01E1000_PHY_DSP_FFE 0x1F35
2460 #define IGP01E1000_PHY_CHANNEL_NUM 4
2461 #define IGP02E1000_PHY_CHANNEL_NUM 4
2463 #define IGP01E1000_PHY_AGC_PARAM_A 0x1171
2464 #define IGP01E1000_PHY_AGC_PARAM_B 0x1271
2465 #define IGP01E1000_PHY_AGC_PARAM_C 0x1471
2466 #define IGP01E1000_PHY_AGC_PARAM_D 0x1871
2468 #define IGP01E1000_PHY_EDAC_MU_INDEX 0xC000
2469 #define IGP01E1000_PHY_EDAC_SIGN_EXT_9_BITS 0x8000
2471 #define IGP01E1000_PHY_ANALOG_TX_STATE 0x2890
2472 #define IGP01E1000_PHY_ANALOG_CLASS_A 0x2000
2473 #define IGP01E1000_PHY_FORCE_ANALOG_ENABLE 0x0004
2474 #define IGP01E1000_PHY_DSP_FFE_CM_CP 0x0069
2476 #define IGP01E1000_PHY_DSP_FFE_DEFAULT 0x002A
2477 /* IGP01E1000 PCS Initialization register - stores the polarity status when
2478 * speed = 1000 Mbps. */
2479 #define IGP01E1000_PHY_PCS_INIT_REG 0x00B4
2480 #define IGP01E1000_PHY_PCS_CTRL_REG 0x00B5
2482 #define IGP01E1000_ANALOG_REGS_PAGE 0x20C0
2486 * 4-0: register offset
2488 #define GG82563_PAGE_SHIFT 5
2489 #define GG82563_REG(page, reg) \
2490 (((page) << GG82563_PAGE_SHIFT) | ((reg) & MAX_PHY_REG_ADDRESS))
2491 #define GG82563_MIN_ALT_REG 30
2493 /* GG82563 Specific Registers */
2494 #define GG82563_PHY_SPEC_CTRL \
2495 GG82563_REG(0, 16) /* PHY Specific Control */
2496 #define GG82563_PHY_SPEC_STATUS \
2497 GG82563_REG(0, 17) /* PHY Specific Status */
2498 #define GG82563_PHY_INT_ENABLE \
2499 GG82563_REG(0, 18) /* Interrupt Enable */
2500 #define GG82563_PHY_SPEC_STATUS_2 \
2501 GG82563_REG(0, 19) /* PHY Specific Status 2 */
2502 #define GG82563_PHY_RX_ERR_CNTR \
2503 GG82563_REG(0, 21) /* Receive Error Counter */
2504 #define GG82563_PHY_PAGE_SELECT \
2505 GG82563_REG(0, 22) /* Page Select */
2506 #define GG82563_PHY_SPEC_CTRL_2 \
2507 GG82563_REG(0, 26) /* PHY Specific Control 2 */
2508 #define GG82563_PHY_PAGE_SELECT_ALT \
2509 GG82563_REG(0, 29) /* Alternate Page Select */
2510 #define GG82563_PHY_TEST_CLK_CTRL \
2511 GG82563_REG(0, 30) /* Test Clock Control (use reg. 29 to select) */
2513 #define GG82563_PHY_MAC_SPEC_CTRL \
2514 GG82563_REG(2, 21) /* MAC Specific Control Register */
2515 #define GG82563_PHY_MAC_SPEC_CTRL_2 \
2516 GG82563_REG(2, 26) /* MAC Specific Control 2 */
2518 #define GG82563_PHY_DSP_DISTANCE \
2519 GG82563_REG(5, 26) /* DSP Distance */
2521 /* Page 193 - Port Control Registers */
2522 #define GG82563_PHY_KMRN_MODE_CTRL \
2523 GG82563_REG(193, 16) /* Kumeran Mode Control */
2524 #define GG82563_PHY_PORT_RESET \
2525 GG82563_REG(193, 17) /* Port Reset */
2526 #define GG82563_PHY_REVISION_ID \
2527 GG82563_REG(193, 18) /* Revision ID */
2528 #define GG82563_PHY_DEVICE_ID \
2529 GG82563_REG(193, 19) /* Device ID */
2530 #define GG82563_PHY_PWR_MGMT_CTRL \
2531 GG82563_REG(193, 20) /* Power Management Control */
2532 #define GG82563_PHY_RATE_ADAPT_CTRL \
2533 GG82563_REG(193, 25) /* Rate Adaptation Control */
2535 /* Page 194 - KMRN Registers */
2536 #define GG82563_PHY_KMRN_FIFO_CTRL_STAT \
2537 GG82563_REG(194, 16) /* FIFO's Control/Status */
2538 #define GG82563_PHY_KMRN_CTRL \
2539 GG82563_REG(194, 17) /* Control */
2540 #define GG82563_PHY_INBAND_CTRL \
2541 GG82563_REG(194, 18) /* Inband Control */
2542 #define GG82563_PHY_KMRN_DIAGNOSTIC \
2543 GG82563_REG(194, 19) /* Diagnostic */
2544 #define GG82563_PHY_ACK_TIMEOUTS \
2545 GG82563_REG(194, 20) /* Acknowledge Timeouts */
2546 #define GG82563_PHY_ADV_ABILITY \
2547 GG82563_REG(194, 21) /* Advertised Ability */
2548 #define GG82563_PHY_LINK_PARTNER_ADV_ABILITY \
2549 GG82563_REG(194, 23) /* Link Partner Advertised Ability */
2550 #define GG82563_PHY_ADV_NEXT_PAGE \
2551 GG82563_REG(194, 24) /* Advertised Next Page */
2552 #define GG82563_PHY_LINK_PARTNER_ADV_NEXT_PAGE \
2553 GG82563_REG(194, 25) /* Link Partner Advertised Next page */
2554 #define GG82563_PHY_KMRN_MISC \
2555 GG82563_REG(194, 26) /* Misc. */
2557 /* PHY Control Register */
2558 #define MII_CR_SPEED_SELECT_MSB 0x0040 /* bits 6,13: 10=1000, 01=100, 00=10 */
2559 #define MII_CR_COLL_TEST_ENABLE 0x0080 /* Collision test enable */
2560 #define MII_CR_FULL_DUPLEX 0x0100 /* FDX =1, half duplex =0 */
2561 #define MII_CR_RESTART_AUTO_NEG 0x0200 /* Restart auto negotiation */
2562 #define MII_CR_ISOLATE 0x0400 /* Isolate PHY from MII */
2563 #define MII_CR_POWER_DOWN 0x0800 /* Power down */
2564 #define MII_CR_AUTO_NEG_EN 0x1000 /* Auto Neg Enable */
2565 #define MII_CR_SPEED_SELECT_LSB 0x2000 /* bits 6,13: 10=1000, 01=100, 00=10 */
2566 #define MII_CR_LOOPBACK 0x4000 /* 0 = normal, 1 = loopback */
2567 #define MII_CR_RESET 0x8000 /* 0 = normal, 1 = PHY reset */
2569 /* PHY Status Register */
2570 #define MII_SR_EXTENDED_CAPS 0x0001 /* Extended register capabilities */
2571 #define MII_SR_JABBER_DETECT 0x0002 /* Jabber Detected */
2572 #define MII_SR_LINK_STATUS 0x0004 /* Link Status 1 = link */
2573 #define MII_SR_AUTONEG_CAPS 0x0008 /* Auto Neg Capable */
2574 #define MII_SR_REMOTE_FAULT 0x0010 /* Remote Fault Detect */
2575 #define MII_SR_AUTONEG_COMPLETE 0x0020 /* Auto Neg Complete */
2576 #define MII_SR_PREAMBLE_SUPPRESS 0x0040 /* Preamble may be suppressed */
2577 #define MII_SR_EXTENDED_STATUS 0x0100 /* Ext. status info in Reg 0x0F */
2578 #define MII_SR_100T2_HD_CAPS 0x0200 /* 100T2 Half Duplex Capable */
2579 #define MII_SR_100T2_FD_CAPS 0x0400 /* 100T2 Full Duplex Capable */
2580 #define MII_SR_10T_HD_CAPS 0x0800 /* 10T Half Duplex Capable */
2581 #define MII_SR_10T_FD_CAPS 0x1000 /* 10T Full Duplex Capable */
2582 #define MII_SR_100X_HD_CAPS 0x2000 /* 100X Half Duplex Capable */
2583 #define MII_SR_100X_FD_CAPS 0x4000 /* 100X Full Duplex Capable */
2584 #define MII_SR_100T4_CAPS 0x8000 /* 100T4 Capable */
2586 /* Autoneg Advertisement Register */
2587 #define NWAY_AR_SELECTOR_FIELD 0x0001 /* indicates IEEE 802.3 CSMA/CD */
2588 #define NWAY_AR_10T_HD_CAPS 0x0020 /* 10T Half Duplex Capable */
2589 #define NWAY_AR_10T_FD_CAPS 0x0040 /* 10T Full Duplex Capable */
2590 #define NWAY_AR_100TX_HD_CAPS 0x0080 /* 100TX Half Duplex Capable */
2591 #define NWAY_AR_100TX_FD_CAPS 0x0100 /* 100TX Full Duplex Capable */
2592 #define NWAY_AR_100T4_CAPS 0x0200 /* 100T4 Capable */
2593 #define NWAY_AR_PAUSE 0x0400 /* Pause operation desired */
2594 #define NWAY_AR_ASM_DIR 0x0800 /* Asymmetric Pause Direction bit */
2595 #define NWAY_AR_REMOTE_FAULT 0x2000 /* Remote Fault detected */
2596 #define NWAY_AR_NEXT_PAGE 0x8000 /* Next Page ability supported */
2598 /* Link Partner Ability Register (Base Page) */
2599 #define NWAY_LPAR_SELECTOR_FIELD 0x0000 /* LP protocol selector field */
2600 #define NWAY_LPAR_10T_HD_CAPS 0x0020 /* LP is 10T Half Duplex Capable */
2601 #define NWAY_LPAR_10T_FD_CAPS 0x0040 /* LP is 10T Full Duplex Capable */
2602 #define NWAY_LPAR_100TX_HD_CAPS 0x0080 /* LP is 100TX Half Duplex Capable */
2603 #define NWAY_LPAR_100TX_FD_CAPS 0x0100 /* LP is 100TX Full Duplex Capable */
2604 #define NWAY_LPAR_100T4_CAPS 0x0200 /* LP is 100T4 Capable */
2605 #define NWAY_LPAR_PAUSE 0x0400 /* LP Pause operation desired */
2606 #define NWAY_LPAR_ASM_DIR 0x0800 /* LP Asymmetric Pause Direction bit */
2607 #define NWAY_LPAR_REMOTE_FAULT 0x2000 /* LP has detected Remote Fault */
2608 #define NWAY_LPAR_ACKNOWLEDGE 0x4000 /* LP has rx'd link code word */
2609 #define NWAY_LPAR_NEXT_PAGE 0x8000 /* Next Page ability supported */
2611 /* Autoneg Expansion Register */
2612 #define NWAY_ER_LP_NWAY_CAPS 0x0001 /* LP has Auto Neg Capability */
2613 #define NWAY_ER_PAGE_RXD 0x0002 /* LP is 10T Half Duplex Capable */
2614 #define NWAY_ER_NEXT_PAGE_CAPS 0x0004 /* LP is 10T Full Duplex Capable */
2615 #define NWAY_ER_LP_NEXT_PAGE_CAPS 0x0008 /* LP is 100TX Half Duplex Capable */
2616 #define NWAY_ER_PAR_DETECT_FAULT 0x0010 /* LP is 100TX Full Duplex Capable */
2618 /* Next Page TX Register */
2619 #define NPTX_MSG_CODE_FIELD 0x0001 /* NP msg code or unformatted data */
2620 #define NPTX_TOGGLE 0x0800 /* Toggles between exchanges
2623 #define NPTX_ACKNOWLDGE2 0x1000 /* 1 = will comply with msg
2624 * 0 = cannot comply with msg
2626 #define NPTX_MSG_PAGE 0x2000 /* formatted(1)/unformatted(0) pg */
2627 #define NPTX_NEXT_PAGE 0x8000 /* 1 = addition NP will follow
2628 * 0 = sending last NP
2631 /* Link Partner Next Page Register */
2632 #define LP_RNPR_MSG_CODE_FIELD 0x0001 /* NP msg code or unformatted data */
2633 #define LP_RNPR_TOGGLE 0x0800 /* Toggles between exchanges
2636 #define LP_RNPR_ACKNOWLDGE2 0x1000 /* 1 = will comply with msg
2637 * 0 = cannot comply with msg
2639 #define LP_RNPR_MSG_PAGE 0x2000 /* formatted(1)/unformatted(0) pg */
2640 #define LP_RNPR_ACKNOWLDGE 0x4000 /* 1 = ACK / 0 = NO ACK */
2641 #define LP_RNPR_NEXT_PAGE 0x8000 /* 1 = addition NP will follow
2642 * 0 = sending last NP
2645 /* 1000BASE-T Control Register */
2646 #define CR_1000T_ASYM_PAUSE 0x0080 /* Advertise asymmetric pause bit */
2647 #define CR_1000T_HD_CAPS 0x0100 /* Advertise 1000T HD capability */
2648 #define CR_1000T_FD_CAPS 0x0200 /* Advertise 1000T FD capability */
2649 #define CR_1000T_REPEATER_DTE 0x0400 /* 1=Repeater/switch device port */
2651 #define CR_1000T_MS_VALUE 0x0800 /* 1=Configure PHY as Master */
2652 /* 0=Configure PHY as Slave */
2653 #define CR_1000T_MS_ENABLE 0x1000 /* 1=Master/Slave manual config value */
2654 /* 0=Automatic Master/Slave config */
2655 #define CR_1000T_TEST_MODE_NORMAL 0x0000 /* Normal Operation */
2656 #define CR_1000T_TEST_MODE_1 0x2000 /* Transmit Waveform test */
2657 #define CR_1000T_TEST_MODE_2 0x4000 /* Master Transmit Jitter test */
2658 #define CR_1000T_TEST_MODE_3 0x6000 /* Slave Transmit Jitter test */
2659 #define CR_1000T_TEST_MODE_4 0x8000 /* Transmitter Distortion test */
2661 /* 1000BASE-T Status Register */
2662 #define SR_1000T_IDLE_ERROR_CNT 0x00FF /* Num idle errors since last read */
2663 #define SR_1000T_ASYM_PAUSE_DIR 0x0100 /* LP asymmetric pause direction bit */
2664 #define SR_1000T_LP_HD_CAPS 0x0400 /* LP is 1000T HD capable */
2665 #define SR_1000T_LP_FD_CAPS 0x0800 /* LP is 1000T FD capable */
2666 #define SR_1000T_REMOTE_RX_STATUS 0x1000 /* Remote receiver OK */
2667 #define SR_1000T_LOCAL_RX_STATUS 0x2000 /* Local receiver OK */
2668 #define SR_1000T_MS_CONFIG_RES 0x4000 /* 1=Local TX is Master, 0=Slave */
2669 #define SR_1000T_MS_CONFIG_FAULT 0x8000 /* Master/Slave config fault */
2670 #define SR_1000T_REMOTE_RX_STATUS_SHIFT 12
2671 #define SR_1000T_LOCAL_RX_STATUS_SHIFT 13
2672 #define SR_1000T_PHY_EXCESSIVE_IDLE_ERR_COUNT 5
2673 #define FFE_IDLE_ERR_COUNT_TIMEOUT_20 20
2674 #define FFE_IDLE_ERR_COUNT_TIMEOUT_100 100
2676 /* Extended Status Register */
2677 #define IEEE_ESR_1000T_HD_CAPS 0x1000 /* 1000T HD capable */
2678 #define IEEE_ESR_1000T_FD_CAPS 0x2000 /* 1000T FD capable */
2679 #define IEEE_ESR_1000X_HD_CAPS 0x4000 /* 1000X HD capable */
2680 #define IEEE_ESR_1000X_FD_CAPS 0x8000 /* 1000X FD capable */
2682 #define PHY_TX_POLARITY_MASK 0x0100 /* register 10h bit 8 (polarity bit) */
2683 #define PHY_TX_NORMAL_POLARITY 0 /* register 10h bit 8 (normal polarity) */
2685 #define AUTO_POLARITY_DISABLE 0x0010 /* register 11h bit 4 */
2686 /* (0=enable, 1=disable) */
2688 /* M88E1000 PHY Specific Control Register */
2689 #define M88E1000_PSCR_JABBER_DISABLE 0x0001 /* 1=Jabber Function disabled */
2690 #define M88E1000_PSCR_POLARITY_REVERSAL 0x0002 /* 1=Polarity Reversal enabled */
2691 #define M88E1000_PSCR_SQE_TEST 0x0004 /* 1=SQE Test enabled */
2692 #define M88E1000_PSCR_CLK125_DISABLE 0x0010 /* 1=CLK125 low,
2695 #define M88E1000_PSCR_MDI_MANUAL_MODE 0x0000 /* MDI Crossover Mode bits 6:5 */
2696 /* Manual MDI configuration */
2697 #define M88E1000_PSCR_MDIX_MANUAL_MODE 0x0020 /* Manual MDIX configuration */
2698 #define M88E1000_PSCR_AUTO_X_1000T 0x0040 /* 1000BASE-T: Auto crossover,
2699 * 100BASE-TX/10BASE-T:
2702 #define M88E1000_PSCR_AUTO_X_MODE 0x0060 /* Auto crossover enabled
2705 #define M88E1000_PSCR_10BT_EXT_DIST_ENABLE 0x0080
2706 /* 1=Enable Extended 10BASE-T distance
2707 * (Lower 10BASE-T RX Threshold)
2708 * 0=Normal 10BASE-T RX Threshold */
2709 #define M88E1000_PSCR_MII_5BIT_ENABLE 0x0100
2710 /* 1=5-Bit interface in 100BASE-TX
2711 * 0=MII interface in 100BASE-TX */
2712 #define M88E1000_PSCR_SCRAMBLER_DISABLE 0x0200 /* 1=Scrambler disable */
2713 #define M88E1000_PSCR_FORCE_LINK_GOOD 0x0400 /* 1=Force link good */
2714 #define M88E1000_PSCR_ASSERT_CRS_ON_TX 0x0800 /* 1=Assert CRS on Transmit */
2716 #define M88E1000_PSCR_POLARITY_REVERSAL_SHIFT 1
2717 #define M88E1000_PSCR_AUTO_X_MODE_SHIFT 5
2718 #define M88E1000_PSCR_10BT_EXT_DIST_ENABLE_SHIFT 7
2720 /* M88E1000 PHY Specific Status Register */
2721 #define M88E1000_PSSR_JABBER 0x0001 /* 1=Jabber */
2722 #define M88E1000_PSSR_REV_POLARITY 0x0002 /* 1=Polarity reversed */
2723 #define M88E1000_PSSR_DOWNSHIFT 0x0020 /* 1=Downshifted */
2724 #define M88E1000_PSSR_MDIX 0x0040 /* 1=MDIX; 0=MDI */
2725 #define M88E1000_PSSR_CABLE_LENGTH 0x0380 /* 0=<50M;1=50-80M;2=80-110M;
2726 * 3=110-140M;4=>140M */
2727 #define M88E1000_PSSR_LINK 0x0400 /* 1=Link up, 0=Link down */
2728 #define M88E1000_PSSR_SPD_DPLX_RESOLVED 0x0800 /* 1=Speed & Duplex resolved */
2729 #define M88E1000_PSSR_PAGE_RCVD 0x1000 /* 1=Page received */
2730 #define M88E1000_PSSR_DPLX 0x2000 /* 1=Duplex 0=Half Duplex */
2731 #define M88E1000_PSSR_SPEED 0xC000 /* Speed, bits 14:15 */
2732 #define M88E1000_PSSR_10MBS 0x0000 /* 00=10Mbs */
2733 #define M88E1000_PSSR_100MBS 0x4000 /* 01=100Mbs */
2734 #define M88E1000_PSSR_1000MBS 0x8000 /* 10=1000Mbs */
2736 #define M88E1000_PSSR_REV_POLARITY_SHIFT 1
2737 #define M88E1000_PSSR_DOWNSHIFT_SHIFT 5
2738 #define M88E1000_PSSR_MDIX_SHIFT 6
2739 #define M88E1000_PSSR_CABLE_LENGTH_SHIFT 7
2741 /* M88E1000 Extended PHY Specific Control Register */
2742 #define M88E1000_EPSCR_FIBER_LOOPBACK 0x4000 /* 1=Fiber loopback */
2743 #define M88E1000_EPSCR_DOWN_NO_IDLE 0x8000 /* 1=Lost lock detect enabled.
2744 * Will assert lost lock and bring
2745 * link down if idle not seen
2746 * within 1ms in 1000BASE-T
2748 /* Number of times we will attempt to autonegotiate before downshifting if we
2750 #define M88E1000_EPSCR_MASTER_DOWNSHIFT_MASK 0x0C00
2751 #define M88E1000_EPSCR_MASTER_DOWNSHIFT_1X 0x0000
2752 #define M88E1000_EPSCR_MASTER_DOWNSHIFT_2X 0x0400
2753 #define M88E1000_EPSCR_MASTER_DOWNSHIFT_3X 0x0800
2754 #define M88E1000_EPSCR_MASTER_DOWNSHIFT_4X 0x0C00
2755 /* Number of times we will attempt to autonegotiate before downshifting if we
2757 #define M88E1000_EPSCR_SLAVE_DOWNSHIFT_MASK 0x0300
2758 #define M88E1000_EPSCR_SLAVE_DOWNSHIFT_DIS 0x0000
2759 #define M88E1000_EPSCR_SLAVE_DOWNSHIFT_1X 0x0100
2760 #define M88E1000_EPSCR_SLAVE_DOWNSHIFT_2X 0x0200
2761 #define M88E1000_EPSCR_SLAVE_DOWNSHIFT_3X 0x0300
2762 #define M88E1000_EPSCR_TX_CLK_2_5 0x0060 /* 2.5 MHz TX_CLK */
2763 #define M88E1000_EPSCR_TX_CLK_25 0x0070 /* 25 MHz TX_CLK */
2764 #define M88E1000_EPSCR_TX_CLK_0 0x0000 /* NO TX_CLK */
2766 /* IGP01E1000 Specific Port Config Register - R/W */
2767 #define IGP01E1000_PSCFR_AUTO_MDIX_PAR_DETECT 0x0010
2768 #define IGP01E1000_PSCFR_PRE_EN 0x0020
2769 #define IGP01E1000_PSCFR_SMART_SPEED 0x0080
2770 #define IGP01E1000_PSCFR_DISABLE_TPLOOPBACK 0x0100
2771 #define IGP01E1000_PSCFR_DISABLE_JABBER 0x0400
2772 #define IGP01E1000_PSCFR_DISABLE_TRANSMIT 0x2000
2774 /* IGP01E1000 Specific Port Status Register - R/O */
2775 #define IGP01E1000_PSSR_AUTONEG_FAILED 0x0001 /* RO LH SC */
2776 #define IGP01E1000_PSSR_POLARITY_REVERSED 0x0002
2777 #define IGP01E1000_PSSR_CABLE_LENGTH 0x007C
2778 #define IGP01E1000_PSSR_FULL_DUPLEX 0x0200
2779 #define IGP01E1000_PSSR_LINK_UP 0x0400
2780 #define IGP01E1000_PSSR_MDIX 0x0800
2781 #define IGP01E1000_PSSR_SPEED_MASK 0xC000 /* speed bits mask */
2782 #define IGP01E1000_PSSR_SPEED_10MBPS 0x4000
2783 #define IGP01E1000_PSSR_SPEED_100MBPS 0x8000
2784 #define IGP01E1000_PSSR_SPEED_1000MBPS 0xC000
2785 #define IGP01E1000_PSSR_CABLE_LENGTH_SHIFT 0x0002 /* shift right 2 */
2786 #define IGP01E1000_PSSR_MDIX_SHIFT 0x000B /* shift right 11 */
2788 /* IGP01E1000 Specific Port Control Register - R/W */
2789 #define IGP01E1000_PSCR_TP_LOOPBACK 0x0010
2790 #define IGP01E1000_PSCR_CORRECT_NC_SCMBLR 0x0200
2791 #define IGP01E1000_PSCR_TEN_CRS_SELECT 0x0400
2792 #define IGP01E1000_PSCR_FLIP_CHIP 0x0800
2793 #define IGP01E1000_PSCR_AUTO_MDIX 0x1000
2794 #define IGP01E1000_PSCR_FORCE_MDI_MDIX 0x2000 /* 0-MDI, 1-MDIX */
2796 /* IGP01E1000 Specific Port Link Health Register */
2797 #define IGP01E1000_PLHR_SS_DOWNGRADE 0x8000
2798 #define IGP01E1000_PLHR_GIG_SCRAMBLER_ERROR 0x4000
2799 #define IGP01E1000_PLHR_MASTER_FAULT 0x2000
2800 #define IGP01E1000_PLHR_MASTER_RESOLUTION 0x1000
2801 #define IGP01E1000_PLHR_GIG_REM_RCVR_NOK 0x0800 /* LH */
2802 #define IGP01E1000_PLHR_IDLE_ERROR_CNT_OFLOW 0x0400 /* LH */
2803 #define IGP01E1000_PLHR_DATA_ERR_1 0x0200 /* LH */
2804 #define IGP01E1000_PLHR_DATA_ERR_0 0x0100
2805 #define IGP01E1000_PLHR_AUTONEG_FAULT 0x0040
2806 #define IGP01E1000_PLHR_AUTONEG_ACTIVE 0x0010
2807 #define IGP01E1000_PLHR_VALID_CHANNEL_D 0x0008
2808 #define IGP01E1000_PLHR_VALID_CHANNEL_C 0x0004
2809 #define IGP01E1000_PLHR_VALID_CHANNEL_B 0x0002
2810 #define IGP01E1000_PLHR_VALID_CHANNEL_A 0x0001
2812 /* IGP01E1000 Channel Quality Register */
2813 #define IGP01E1000_MSE_CHANNEL_D 0x000F
2814 #define IGP01E1000_MSE_CHANNEL_C 0x00F0
2815 #define IGP01E1000_MSE_CHANNEL_B 0x0F00
2816 #define IGP01E1000_MSE_CHANNEL_A 0xF000
2818 #define IGP02E1000_PM_SPD 0x0001 /* Smart Power Down */
2819 #define IGP02E1000_PM_D3_LPLU 0x0004 /* Enable LPLU in non-D0a modes */
2820 #define IGP02E1000_PM_D0_LPLU 0x0002 /* Enable LPLU in D0a mode */
2822 /* IGP01E1000 DSP reset macros */
2823 #define DSP_RESET_ENABLE 0x0
2824 #define DSP_RESET_DISABLE 0x2
2825 #define E1000_MAX_DSP_RESETS 10
2827 /* IGP01E1000 & IGP02E1000 AGC Registers */
2829 #define IGP01E1000_AGC_LENGTH_SHIFT 7 /* Coarse - 13:11, Fine - 10:7 */
2830 #define IGP02E1000_AGC_LENGTH_SHIFT 9 /* Coarse - 15:13, Fine - 12:9 */
2832 /* IGP02E1000 AGC Register Length 9-bit mask */
2833 #define IGP02E1000_AGC_LENGTH_MASK 0x7F
2835 /* 7 bits (3 Coarse + 4 Fine) --> 128 optional values */
2836 #define IGP01E1000_AGC_LENGTH_TABLE_SIZE 128
2837 #define IGP02E1000_AGC_LENGTH_TABLE_SIZE 113
2839 /* The precision error of the cable length is +/- 10 meters */
2840 #define IGP01E1000_AGC_RANGE 10
2841 #define IGP02E1000_AGC_RANGE 15
2843 /* IGP01E1000 PCS Initialization register */
2844 /* bits 3:6 in the PCS registers stores the channels polarity */
2845 #define IGP01E1000_PHY_POLARITY_MASK 0x0078
2847 /* IGP01E1000 GMII FIFO Register */
2848 #define IGP01E1000_GMII_FLEX_SPD 0x10 /* Enable flexible speed
2850 #define IGP01E1000_GMII_SPD 0x20 /* Enable SPD */
2852 /* IGP01E1000 Analog Register */
2853 #define IGP01E1000_ANALOG_SPARE_FUSE_STATUS 0x20D1
2854 #define IGP01E1000_ANALOG_FUSE_STATUS 0x20D0
2855 #define IGP01E1000_ANALOG_FUSE_CONTROL 0x20DC
2856 #define IGP01E1000_ANALOG_FUSE_BYPASS 0x20DE
2858 #define IGP01E1000_ANALOG_FUSE_POLY_MASK 0xF000
2859 #define IGP01E1000_ANALOG_FUSE_FINE_MASK 0x0F80
2860 #define IGP01E1000_ANALOG_FUSE_COARSE_MASK 0x0070
2861 #define IGP01E1000_ANALOG_SPARE_FUSE_ENABLED 0x0100
2862 #define IGP01E1000_ANALOG_FUSE_ENABLE_SW_CONTROL 0x0002
2864 #define IGP01E1000_ANALOG_FUSE_COARSE_THRESH 0x0040
2865 #define IGP01E1000_ANALOG_FUSE_COARSE_10 0x0010
2866 #define IGP01E1000_ANALOG_FUSE_FINE_1 0x0080
2867 #define IGP01E1000_ANALOG_FUSE_FINE_10 0x0500
2869 /* GG82563 PHY Specific Status Register (Page 0, Register 16 */
2870 #define GG82563_PSCR_DISABLE_JABBER 0x0001 /* 1=Disable Jabber */
2871 #define GG82563_PSCR_POLARITY_REVERSAL_DISABLE 0x0002 /* 1=Polarity Reversal Disabled */
2872 #define GG82563_PSCR_POWER_DOWN 0x0004 /* 1=Power Down */
2873 #define GG82563_PSCR_COPPER_TRANSMITER_DISABLE 0x0008 /* 1=Transmitter Disabled */
2874 #define GG82563_PSCR_CROSSOVER_MODE_MASK 0x0060
2875 #define GG82563_PSCR_CROSSOVER_MODE_MDI 0x0000 /* 00=Manual MDI configuration */
2876 #define GG82563_PSCR_CROSSOVER_MODE_MDIX 0x0020 /* 01=Manual MDIX configuration */
2877 #define GG82563_PSCR_CROSSOVER_MODE_AUTO 0x0060 /* 11=Automatic crossover */
2878 #define GG82563_PSCR_ENALBE_EXTENDED_DISTANCE 0x0080 /* 1=Enable Extended Distance */
2879 #define GG82563_PSCR_ENERGY_DETECT_MASK 0x0300
2880 #define GG82563_PSCR_ENERGY_DETECT_OFF 0x0000 /* 00,01=Off */
2881 #define GG82563_PSCR_ENERGY_DETECT_RX 0x0200 /* 10=Sense on Rx only (Energy Detect) */
2882 #define GG82563_PSCR_ENERGY_DETECT_RX_TM 0x0300 /* 11=Sense and Tx NLP */
2883 #define GG82563_PSCR_FORCE_LINK_GOOD 0x0400 /* 1=Force Link Good */
2884 #define GG82563_PSCR_DOWNSHIFT_ENABLE 0x0800 /* 1=Enable Downshift */
2885 #define GG82563_PSCR_DOWNSHIFT_COUNTER_MASK 0x7000
2886 #define GG82563_PSCR_DOWNSHIFT_COUNTER_SHIFT 12
2888 /* PHY Specific Status Register (Page 0, Register 17) */
2889 #define GG82563_PSSR_JABBER 0x0001 /* 1=Jabber */
2890 #define GG82563_PSSR_POLARITY 0x0002 /* 1=Polarity Reversed */
2891 #define GG82563_PSSR_LINK 0x0008 /* 1=Link is Up */
2892 #define GG82563_PSSR_ENERGY_DETECT 0x0010 /* 1=Sleep, 0=Active */
2893 #define GG82563_PSSR_DOWNSHIFT 0x0020 /* 1=Downshift */
2894 #define GG82563_PSSR_CROSSOVER_STATUS 0x0040 /* 1=MDIX, 0=MDI */
2895 #define GG82563_PSSR_RX_PAUSE_ENABLED 0x0100 /* 1=Receive Pause Enabled */
2896 #define GG82563_PSSR_TX_PAUSE_ENABLED 0x0200 /* 1=Transmit Pause Enabled */
2897 #define GG82563_PSSR_LINK_UP 0x0400 /* 1=Link Up */
2898 #define GG82563_PSSR_SPEED_DUPLEX_RESOLVED 0x0800 /* 1=Resolved */
2899 #define GG82563_PSSR_PAGE_RECEIVED 0x1000 /* 1=Page Received */
2900 #define GG82563_PSSR_DUPLEX 0x2000 /* 1-Full-Duplex */
2901 #define GG82563_PSSR_SPEED_MASK 0xC000
2902 #define GG82563_PSSR_SPEED_10MBPS 0x0000 /* 00=10Mbps */
2903 #define GG82563_PSSR_SPEED_100MBPS 0x4000 /* 01=100Mbps */
2904 #define GG82563_PSSR_SPEED_1000MBPS 0x8000 /* 10=1000Mbps */
2906 /* PHY Specific Status Register 2 (Page 0, Register 19) */
2907 #define GG82563_PSSR2_JABBER 0x0001 /* 1=Jabber */
2908 #define GG82563_PSSR2_POLARITY_CHANGED 0x0002 /* 1=Polarity Changed */
2909 #define GG82563_PSSR2_ENERGY_DETECT_CHANGED 0x0010 /* 1=Energy Detect Changed */
2910 #define GG82563_PSSR2_DOWNSHIFT_INTERRUPT 0x0020 /* 1=Downshift Detected */
2911 #define GG82563_PSSR2_MDI_CROSSOVER_CHANGE 0x0040 /* 1=Crossover Changed */
2912 #define GG82563_PSSR2_FALSE_CARRIER 0x0100 /* 1=False Carrier */
2913 #define GG82563_PSSR2_SYMBOL_ERROR 0x0200 /* 1=Symbol Error */
2914 #define GG82563_PSSR2_LINK_STATUS_CHANGED 0x0400 /* 1=Link Status Changed */
2915 #define GG82563_PSSR2_AUTO_NEG_COMPLETED 0x0800 /* 1=Auto-Neg Completed */
2916 #define GG82563_PSSR2_PAGE_RECEIVED 0x1000 /* 1=Page Received */
2917 #define GG82563_PSSR2_DUPLEX_CHANGED 0x2000 /* 1=Duplex Changed */
2918 #define GG82563_PSSR2_SPEED_CHANGED 0x4000 /* 1=Speed Changed */
2919 #define GG82563_PSSR2_AUTO_NEG_ERROR 0x8000 /* 1=Auto-Neg Error */
2921 /* PHY Specific Control Register 2 (Page 0, Register 26) */
2922 #define GG82563_PSCR2_10BT_POLARITY_FORCE 0x0002 /* 1=Force Negative Polarity */
2923 #define GG82563_PSCR2_1000MB_TEST_SELECT_MASK 0x000C
2924 #define GG82563_PSCR2_1000MB_TEST_SELECT_NORMAL 0x0000 /* 00,01=Normal Operation */
2925 #define GG82563_PSCR2_1000MB_TEST_SELECT_112NS 0x0008 /* 10=Select 112ns Sequence */
2926 #define GG82563_PSCR2_1000MB_TEST_SELECT_16NS 0x000C /* 11=Select 16ns Sequence */
2927 #define GG82563_PSCR2_REVERSE_AUTO_NEG 0x2000 /* 1=Reverse Auto-Negotiation */
2928 #define GG82563_PSCR2_1000BT_DISABLE 0x4000 /* 1=Disable 1000BASE-T */
2929 #define GG82563_PSCR2_TRANSMITER_TYPE_MASK 0x8000
2930 #define GG82563_PSCR2_TRANSMITTER_TYPE_CLASS_B 0x0000 /* 0=Class B */
2931 #define GG82563_PSCR2_TRANSMITTER_TYPE_CLASS_A 0x8000 /* 1=Class A */
2933 /* MAC Specific Control Register (Page 2, Register 21) */
2934 /* Tx clock speed for Link Down and 1000BASE-T for the following speeds */
2935 #define GG82563_MSCR_TX_CLK_MASK 0x0007
2936 #define GG82563_MSCR_TX_CLK_10MBPS_2_5MHZ 0x0004
2937 #define GG82563_MSCR_TX_CLK_100MBPS_25MHZ 0x0005
2938 #define GG82563_MSCR_TX_CLK_1000MBPS_2_5MHZ 0x0006
2939 #define GG82563_MSCR_TX_CLK_1000MBPS_25MHZ 0x0007
2941 #define GG82563_MSCR_ASSERT_CRS_ON_TX 0x0010 /* 1=Assert */
2943 /* DSP Distance Register (Page 5, Register 26) */
2944 #define GG82563_DSPD_CABLE_LENGTH 0x0007 /* 0 = <50M;
2950 /* Kumeran Mode Control Register (Page 193, Register 16) */
2951 #define GG82563_KMCR_PHY_LEDS_EN 0x0020 /* 1=PHY LEDs, 0=Kumeran Inband LEDs */
2952 #define GG82563_KMCR_FORCE_LINK_UP 0x0040 /* 1=Force Link Up */
2953 #define GG82563_KMCR_SUPPRESS_SGMII_EPD_EXT 0x0080
2954 #define GG82563_KMCR_MDIO_BUS_SPEED_SELECT_MASK 0x0400
2955 #define GG82563_KMCR_MDIO_BUS_SPEED_SELECT 0x0400 /* 1=6.25MHz, 0=0.8MHz */
2956 #define GG82563_KMCR_PASS_FALSE_CARRIER 0x0800
2958 /* Power Management Control Register (Page 193, Register 20) */
2959 #define GG82563_PMCR_ENABLE_ELECTRICAL_IDLE 0x0001 /* 1=Enalbe SERDES Electrical Idle */
2960 #define GG82563_PMCR_DISABLE_PORT 0x0002 /* 1=Disable Port */
2961 #define GG82563_PMCR_DISABLE_SERDES 0x0004 /* 1=Disable SERDES */
2962 #define GG82563_PMCR_REVERSE_AUTO_NEG 0x0008 /* 1=Enable Reverse Auto-Negotiation */
2963 #define GG82563_PMCR_DISABLE_1000_NON_D0 0x0010 /* 1=Disable 1000Mbps Auto-Neg in non D0 */
2964 #define GG82563_PMCR_DISABLE_1000 0x0020 /* 1=Disable 1000Mbps Auto-Neg Always */
2965 #define GG82563_PMCR_REVERSE_AUTO_NEG_D0A 0x0040 /* 1=Enable D0a Reverse Auto-Negotiation */
2966 #define GG82563_PMCR_FORCE_POWER_STATE 0x0080 /* 1=Force Power State */
2967 #define GG82563_PMCR_PROGRAMMED_POWER_STATE_MASK 0x0300
2968 #define GG82563_PMCR_PROGRAMMED_POWER_STATE_DR 0x0000 /* 00=Dr */
2969 #define GG82563_PMCR_PROGRAMMED_POWER_STATE_D0U 0x0100 /* 01=D0u */
2970 #define GG82563_PMCR_PROGRAMMED_POWER_STATE_D0A 0x0200 /* 10=D0a */
2971 #define GG82563_PMCR_PROGRAMMED_POWER_STATE_D3 0x0300 /* 11=D3 */
2973 /* In-Band Control Register (Page 194, Register 18) */
2974 #define GG82563_ICR_DIS_PADDING 0x0010 /* Disable Padding Use */
2977 /* Bit definitions for valid PHY IDs. */
2981 #define M88E1000_E_PHY_ID 0x01410C50
2982 #define M88E1000_I_PHY_ID 0x01410C30
2983 #define M88E1011_I_PHY_ID 0x01410C20
2984 #define IGP01E1000_I_PHY_ID 0x02A80380
2985 #define M88E1000_12_PHY_ID M88E1000_E_PHY_ID
2986 #define M88E1000_14_PHY_ID M88E1000_E_PHY_ID
2987 #define M88E1011_I_REV_4 0x04
2988 #define M88E1111_I_PHY_ID 0x01410CC0
2989 #define L1LXT971A_PHY_ID 0x001378E0
2990 #define GG82563_E_PHY_ID 0x01410CA0
2992 /* Miscellaneous PHY bit definitions. */
2993 #define PHY_PREAMBLE 0xFFFFFFFF
2994 #define PHY_SOF 0x01
2995 #define PHY_OP_READ 0x02
2996 #define PHY_OP_WRITE 0x01
2997 #define PHY_TURNAROUND 0x02
2998 #define PHY_PREAMBLE_SIZE 32
2999 #define MII_CR_SPEED_1000 0x0040
3000 #define MII_CR_SPEED_100 0x2000
3001 #define MII_CR_SPEED_10 0x0000
3002 #define E1000_PHY_ADDRESS 0x01
3003 #define PHY_AUTO_NEG_TIME 45 /* 4.5 Seconds */
3004 #define PHY_FORCE_TIME 20 /* 2.0 Seconds */
3005 #define PHY_REVISION_MASK 0xFFFFFFF0
3006 #define DEVICE_SPEED_MASK 0x00000300 /* Device Ctrl Reg Speed Mask */
3007 #define REG4_SPEED_MASK 0x01E0
3008 #define REG9_SPEED_MASK 0x0300
3009 #define ADVERTISE_10_HALF 0x0001
3010 #define ADVERTISE_10_FULL 0x0002
3011 #define ADVERTISE_100_HALF 0x0004
3012 #define ADVERTISE_100_FULL 0x0008
3013 #define ADVERTISE_1000_HALF 0x0010
3014 #define ADVERTISE_1000_FULL 0x0020
3015 #define AUTONEG_ADVERTISE_SPEED_DEFAULT 0x002F /* Everything but 1000-Half */
3016 #define AUTONEG_ADVERTISE_10_100_ALL 0x000F /* All 10/100 speeds*/
3017 #define AUTONEG_ADVERTISE_10_ALL 0x0003 /* 10Mbps Full & Half speeds*/
3019 #endif /* _E1000_HW_H_ */