1 /*******************************************************************************
4 Copyright(c) 1999 - 2005 Intel Corporation. All rights reserved.
6 This program is free software; you can redistribute it and/or modify it
7 under the terms of the GNU General Public License as published by the Free
8 Software Foundation; either version 2 of the License, or (at your option)
11 This program is distributed in the hope that it will be useful, but WITHOUT
12 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
16 You should have received a copy of the GNU General Public License along with
17 this program; if not, write to the Free Software Foundation, Inc., 59
18 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
20 The full GNU General Public License is included in this distribution in the
24 Linux NICS <linux.nics@intel.com>
25 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
27 *******************************************************************************/
30 * Shared functions for accessing and configuring the MAC
35 static int32_t e1000_set_phy_type(struct e1000_hw *hw);
36 static void e1000_phy_init_script(struct e1000_hw *hw);
37 static int32_t e1000_setup_copper_link(struct e1000_hw *hw);
38 static int32_t e1000_setup_fiber_serdes_link(struct e1000_hw *hw);
39 static int32_t e1000_adjust_serdes_amplitude(struct e1000_hw *hw);
40 static int32_t e1000_phy_force_speed_duplex(struct e1000_hw *hw);
41 static int32_t e1000_config_mac_to_phy(struct e1000_hw *hw);
42 static void e1000_raise_mdi_clk(struct e1000_hw *hw, uint32_t *ctrl);
43 static void e1000_lower_mdi_clk(struct e1000_hw *hw, uint32_t *ctrl);
44 static void e1000_shift_out_mdi_bits(struct e1000_hw *hw, uint32_t data,
46 static uint16_t e1000_shift_in_mdi_bits(struct e1000_hw *hw);
47 static int32_t e1000_phy_reset_dsp(struct e1000_hw *hw);
48 static int32_t e1000_write_eeprom_spi(struct e1000_hw *hw, uint16_t offset,
49 uint16_t words, uint16_t *data);
50 static int32_t e1000_write_eeprom_microwire(struct e1000_hw *hw,
51 uint16_t offset, uint16_t words,
53 static int32_t e1000_spi_eeprom_ready(struct e1000_hw *hw);
54 static void e1000_raise_ee_clk(struct e1000_hw *hw, uint32_t *eecd);
55 static void e1000_lower_ee_clk(struct e1000_hw *hw, uint32_t *eecd);
56 static void e1000_shift_out_ee_bits(struct e1000_hw *hw, uint16_t data,
58 static int32_t e1000_write_phy_reg_ex(struct e1000_hw *hw, uint32_t reg_addr,
60 static int32_t e1000_read_phy_reg_ex(struct e1000_hw *hw,uint32_t reg_addr,
62 static uint16_t e1000_shift_in_ee_bits(struct e1000_hw *hw, uint16_t count);
63 static int32_t e1000_acquire_eeprom(struct e1000_hw *hw);
64 static void e1000_release_eeprom(struct e1000_hw *hw);
65 static void e1000_standby_eeprom(struct e1000_hw *hw);
66 static int32_t e1000_set_vco_speed(struct e1000_hw *hw);
67 static int32_t e1000_polarity_reversal_workaround(struct e1000_hw *hw);
68 static int32_t e1000_set_phy_mode(struct e1000_hw *hw);
69 static int32_t e1000_host_if_read_cookie(struct e1000_hw *hw, uint8_t *buffer);
70 static uint8_t e1000_calculate_mng_checksum(char *buffer, uint32_t length);
71 static uint8_t e1000_arc_subsystem_valid(struct e1000_hw *hw);
72 static int32_t e1000_check_downshift(struct e1000_hw *hw);
73 static int32_t e1000_check_polarity(struct e1000_hw *hw, uint16_t *polarity);
74 static void e1000_clear_hw_cntrs(struct e1000_hw *hw);
75 static void e1000_clear_vfta(struct e1000_hw *hw);
76 static int32_t e1000_commit_shadow_ram(struct e1000_hw *hw);
77 static int32_t e1000_config_dsp_after_link_change(struct e1000_hw *hw,
79 static int32_t e1000_config_fc_after_link_up(struct e1000_hw *hw);
80 static int32_t e1000_detect_gig_phy(struct e1000_hw *hw);
81 static int32_t e1000_get_auto_rd_done(struct e1000_hw *hw);
82 static int32_t e1000_get_cable_length(struct e1000_hw *hw,
84 uint16_t *max_length);
85 static int32_t e1000_get_hw_eeprom_semaphore(struct e1000_hw *hw);
86 static int32_t e1000_get_phy_cfg_done(struct e1000_hw *hw);
87 static int32_t e1000_id_led_init(struct e1000_hw * hw);
88 static void e1000_init_rx_addrs(struct e1000_hw *hw);
89 static boolean_t e1000_is_onboard_nvm_eeprom(struct e1000_hw *hw);
90 static int32_t e1000_poll_eerd_eewr_done(struct e1000_hw *hw, int eerd);
91 static void e1000_put_hw_eeprom_semaphore(struct e1000_hw *hw);
92 static int32_t e1000_read_eeprom_eerd(struct e1000_hw *hw, uint16_t offset,
93 uint16_t words, uint16_t *data);
94 static int32_t e1000_set_d0_lplu_state(struct e1000_hw *hw, boolean_t active);
95 static int32_t e1000_set_d3_lplu_state(struct e1000_hw *hw, boolean_t active);
96 static int32_t e1000_wait_autoneg(struct e1000_hw *hw);
98 static void e1000_write_reg_io(struct e1000_hw *hw, uint32_t offset,
101 #define E1000_WRITE_REG_IO(a, reg, val) \
102 e1000_write_reg_io((a), E1000_##reg, val)
104 /* IGP cable length table */
106 uint16_t e1000_igp_cable_length_table[IGP01E1000_AGC_LENGTH_TABLE_SIZE] =
107 { 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5,
108 5, 10, 10, 10, 10, 10, 10, 10, 20, 20, 20, 20, 20, 25, 25, 25,
109 25, 25, 25, 25, 30, 30, 30, 30, 40, 40, 40, 40, 40, 40, 40, 40,
110 40, 50, 50, 50, 50, 50, 50, 50, 60, 60, 60, 60, 60, 60, 60, 60,
111 60, 70, 70, 70, 70, 70, 70, 80, 80, 80, 80, 80, 80, 90, 90, 90,
112 90, 90, 90, 90, 90, 90, 100, 100, 100, 100, 100, 100, 100, 100, 100, 100,
113 100, 100, 100, 100, 110, 110, 110, 110, 110, 110, 110, 110, 110, 110, 110, 110,
114 110, 110, 110, 110, 110, 110, 120, 120, 120, 120, 120, 120, 120, 120, 120, 120};
117 uint16_t e1000_igp_2_cable_length_table[IGP02E1000_AGC_LENGTH_TABLE_SIZE] =
118 { 0, 0, 0, 0, 0, 0, 0, 0, 3, 5, 8, 11, 13, 16, 18, 21,
119 0, 0, 0, 3, 6, 10, 13, 16, 19, 23, 26, 29, 32, 35, 38, 41,
120 6, 10, 14, 18, 22, 26, 30, 33, 37, 41, 44, 48, 51, 54, 58, 61,
121 21, 26, 31, 35, 40, 44, 49, 53, 57, 61, 65, 68, 72, 75, 79, 82,
122 40, 45, 51, 56, 61, 66, 70, 75, 79, 83, 87, 91, 94, 98, 101, 104,
123 60, 66, 72, 77, 82, 87, 92, 96, 100, 104, 108, 111, 114, 117, 119, 121,
124 83, 89, 95, 100, 105, 109, 113, 116, 119, 122, 124,
125 104, 109, 114, 118, 121, 124};
128 /******************************************************************************
129 * Set the phy type member in the hw struct.
131 * hw - Struct containing variables accessed by shared code
132 *****************************************************************************/
134 e1000_set_phy_type(struct e1000_hw *hw)
136 DEBUGFUNC("e1000_set_phy_type");
138 if(hw->mac_type == e1000_undefined)
139 return -E1000_ERR_PHY_TYPE;
142 case M88E1000_E_PHY_ID:
143 case M88E1000_I_PHY_ID:
144 case M88E1011_I_PHY_ID:
145 case M88E1111_I_PHY_ID:
146 hw->phy_type = e1000_phy_m88;
148 case IGP01E1000_I_PHY_ID:
149 if(hw->mac_type == e1000_82541 ||
150 hw->mac_type == e1000_82541_rev_2 ||
151 hw->mac_type == e1000_82547 ||
152 hw->mac_type == e1000_82547_rev_2) {
153 hw->phy_type = e1000_phy_igp;
158 /* Should never have loaded on this device */
159 hw->phy_type = e1000_phy_undefined;
160 return -E1000_ERR_PHY_TYPE;
163 return E1000_SUCCESS;
166 /******************************************************************************
167 * IGP phy init script - initializes the GbE PHY
169 * hw - Struct containing variables accessed by shared code
170 *****************************************************************************/
172 e1000_phy_init_script(struct e1000_hw *hw)
175 uint16_t phy_saved_data;
177 DEBUGFUNC("e1000_phy_init_script");
179 if(hw->phy_init_script) {
182 /* Save off the current value of register 0x2F5B to be restored at
183 * the end of this routine. */
184 ret_val = e1000_read_phy_reg(hw, 0x2F5B, &phy_saved_data);
186 /* Disabled the PHY transmitter */
187 e1000_write_phy_reg(hw, 0x2F5B, 0x0003);
191 e1000_write_phy_reg(hw,0x0000,0x0140);
195 switch(hw->mac_type) {
198 e1000_write_phy_reg(hw, 0x1F95, 0x0001);
200 e1000_write_phy_reg(hw, 0x1F71, 0xBD21);
202 e1000_write_phy_reg(hw, 0x1F79, 0x0018);
204 e1000_write_phy_reg(hw, 0x1F30, 0x1600);
206 e1000_write_phy_reg(hw, 0x1F31, 0x0014);
208 e1000_write_phy_reg(hw, 0x1F32, 0x161C);
210 e1000_write_phy_reg(hw, 0x1F94, 0x0003);
212 e1000_write_phy_reg(hw, 0x1F96, 0x003F);
214 e1000_write_phy_reg(hw, 0x2010, 0x0008);
217 case e1000_82541_rev_2:
218 case e1000_82547_rev_2:
219 e1000_write_phy_reg(hw, 0x1F73, 0x0099);
225 e1000_write_phy_reg(hw, 0x0000, 0x3300);
229 /* Now enable the transmitter */
230 e1000_write_phy_reg(hw, 0x2F5B, phy_saved_data);
232 if(hw->mac_type == e1000_82547) {
233 uint16_t fused, fine, coarse;
235 /* Move to analog registers page */
236 e1000_read_phy_reg(hw, IGP01E1000_ANALOG_SPARE_FUSE_STATUS, &fused);
238 if(!(fused & IGP01E1000_ANALOG_SPARE_FUSE_ENABLED)) {
239 e1000_read_phy_reg(hw, IGP01E1000_ANALOG_FUSE_STATUS, &fused);
241 fine = fused & IGP01E1000_ANALOG_FUSE_FINE_MASK;
242 coarse = fused & IGP01E1000_ANALOG_FUSE_COARSE_MASK;
244 if(coarse > IGP01E1000_ANALOG_FUSE_COARSE_THRESH) {
245 coarse -= IGP01E1000_ANALOG_FUSE_COARSE_10;
246 fine -= IGP01E1000_ANALOG_FUSE_FINE_1;
247 } else if(coarse == IGP01E1000_ANALOG_FUSE_COARSE_THRESH)
248 fine -= IGP01E1000_ANALOG_FUSE_FINE_10;
250 fused = (fused & IGP01E1000_ANALOG_FUSE_POLY_MASK) |
251 (fine & IGP01E1000_ANALOG_FUSE_FINE_MASK) |
252 (coarse & IGP01E1000_ANALOG_FUSE_COARSE_MASK);
254 e1000_write_phy_reg(hw, IGP01E1000_ANALOG_FUSE_CONTROL, fused);
255 e1000_write_phy_reg(hw, IGP01E1000_ANALOG_FUSE_BYPASS,
256 IGP01E1000_ANALOG_FUSE_ENABLE_SW_CONTROL);
262 /******************************************************************************
263 * Set the mac type member in the hw struct.
265 * hw - Struct containing variables accessed by shared code
266 *****************************************************************************/
268 e1000_set_mac_type(struct e1000_hw *hw)
270 DEBUGFUNC("e1000_set_mac_type");
272 switch (hw->device_id) {
273 case E1000_DEV_ID_82542:
274 switch (hw->revision_id) {
275 case E1000_82542_2_0_REV_ID:
276 hw->mac_type = e1000_82542_rev2_0;
278 case E1000_82542_2_1_REV_ID:
279 hw->mac_type = e1000_82542_rev2_1;
282 /* Invalid 82542 revision ID */
283 return -E1000_ERR_MAC_TYPE;
286 case E1000_DEV_ID_82543GC_FIBER:
287 case E1000_DEV_ID_82543GC_COPPER:
288 hw->mac_type = e1000_82543;
290 case E1000_DEV_ID_82544EI_COPPER:
291 case E1000_DEV_ID_82544EI_FIBER:
292 case E1000_DEV_ID_82544GC_COPPER:
293 case E1000_DEV_ID_82544GC_LOM:
294 hw->mac_type = e1000_82544;
296 case E1000_DEV_ID_82540EM:
297 case E1000_DEV_ID_82540EM_LOM:
298 case E1000_DEV_ID_82540EP:
299 case E1000_DEV_ID_82540EP_LOM:
300 case E1000_DEV_ID_82540EP_LP:
301 hw->mac_type = e1000_82540;
303 case E1000_DEV_ID_82545EM_COPPER:
304 case E1000_DEV_ID_82545EM_FIBER:
305 hw->mac_type = e1000_82545;
307 case E1000_DEV_ID_82545GM_COPPER:
308 case E1000_DEV_ID_82545GM_FIBER:
309 case E1000_DEV_ID_82545GM_SERDES:
310 hw->mac_type = e1000_82545_rev_3;
312 case E1000_DEV_ID_82546EB_COPPER:
313 case E1000_DEV_ID_82546EB_FIBER:
314 case E1000_DEV_ID_82546EB_QUAD_COPPER:
315 hw->mac_type = e1000_82546;
317 case E1000_DEV_ID_82546GB_COPPER:
318 case E1000_DEV_ID_82546GB_FIBER:
319 case E1000_DEV_ID_82546GB_SERDES:
320 case E1000_DEV_ID_82546GB_PCIE:
321 hw->mac_type = e1000_82546_rev_3;
323 case E1000_DEV_ID_82541EI:
324 case E1000_DEV_ID_82541EI_MOBILE:
325 hw->mac_type = e1000_82541;
327 case E1000_DEV_ID_82541ER:
328 case E1000_DEV_ID_82541GI:
329 case E1000_DEV_ID_82541GI_LF:
330 case E1000_DEV_ID_82541GI_MOBILE:
331 hw->mac_type = e1000_82541_rev_2;
333 case E1000_DEV_ID_82547EI:
334 hw->mac_type = e1000_82547;
336 case E1000_DEV_ID_82547GI:
337 hw->mac_type = e1000_82547_rev_2;
339 case E1000_DEV_ID_82571EB_COPPER:
340 case E1000_DEV_ID_82571EB_FIBER:
341 case E1000_DEV_ID_82571EB_SERDES:
342 hw->mac_type = e1000_82571;
344 case E1000_DEV_ID_82572EI_COPPER:
345 case E1000_DEV_ID_82572EI_FIBER:
346 case E1000_DEV_ID_82572EI_SERDES:
347 hw->mac_type = e1000_82572;
349 case E1000_DEV_ID_82573E:
350 case E1000_DEV_ID_82573E_IAMT:
351 case E1000_DEV_ID_82573L:
352 hw->mac_type = e1000_82573;
355 /* Should never have loaded on this device */
356 return -E1000_ERR_MAC_TYPE;
359 switch(hw->mac_type) {
363 hw->eeprom_semaphore_present = TRUE;
367 case e1000_82541_rev_2:
368 case e1000_82547_rev_2:
369 hw->asf_firmware_present = TRUE;
375 return E1000_SUCCESS;
378 /*****************************************************************************
379 * Set media type and TBI compatibility.
381 * hw - Struct containing variables accessed by shared code
382 * **************************************************************************/
384 e1000_set_media_type(struct e1000_hw *hw)
388 DEBUGFUNC("e1000_set_media_type");
390 if(hw->mac_type != e1000_82543) {
391 /* tbi_compatibility is only valid on 82543 */
392 hw->tbi_compatibility_en = FALSE;
395 switch (hw->device_id) {
396 case E1000_DEV_ID_82545GM_SERDES:
397 case E1000_DEV_ID_82546GB_SERDES:
398 case E1000_DEV_ID_82571EB_SERDES:
399 case E1000_DEV_ID_82572EI_SERDES:
400 hw->media_type = e1000_media_type_internal_serdes;
403 switch (hw->mac_type) {
404 case e1000_82542_rev2_0:
405 case e1000_82542_rev2_1:
406 hw->media_type = e1000_media_type_fiber;
409 /* The STATUS_TBIMODE bit is reserved or reused for the this
412 hw->media_type = e1000_media_type_copper;
415 status = E1000_READ_REG(hw, STATUS);
416 if (status & E1000_STATUS_TBIMODE) {
417 hw->media_type = e1000_media_type_fiber;
418 /* tbi_compatibility not valid on fiber */
419 hw->tbi_compatibility_en = FALSE;
421 hw->media_type = e1000_media_type_copper;
428 /******************************************************************************
429 * Reset the transmit and receive units; mask and clear all interrupts.
431 * hw - Struct containing variables accessed by shared code
432 *****************************************************************************/
434 e1000_reset_hw(struct e1000_hw *hw)
442 uint32_t extcnf_ctrl;
445 DEBUGFUNC("e1000_reset_hw");
447 /* For 82542 (rev 2.0), disable MWI before issuing a device reset */
448 if(hw->mac_type == e1000_82542_rev2_0) {
449 DEBUGOUT("Disabling MWI on 82542 rev 2.0\n");
450 e1000_pci_clear_mwi(hw);
453 if(hw->bus_type == e1000_bus_type_pci_express) {
454 /* Prevent the PCI-E bus from sticking if there is no TLP connection
455 * on the last TLP read/write transaction when MAC is reset.
457 if(e1000_disable_pciex_master(hw) != E1000_SUCCESS) {
458 DEBUGOUT("PCI-E Master disable polling has failed.\n");
462 /* Clear interrupt mask to stop board from generating interrupts */
463 DEBUGOUT("Masking off all interrupts\n");
464 E1000_WRITE_REG(hw, IMC, 0xffffffff);
466 /* Disable the Transmit and Receive units. Then delay to allow
467 * any pending transactions to complete before we hit the MAC with
470 E1000_WRITE_REG(hw, RCTL, 0);
471 E1000_WRITE_REG(hw, TCTL, E1000_TCTL_PSP);
472 E1000_WRITE_FLUSH(hw);
474 /* The tbi_compatibility_on Flag must be cleared when Rctl is cleared. */
475 hw->tbi_compatibility_on = FALSE;
477 /* Delay to allow any outstanding PCI transactions to complete before
478 * resetting the device
482 ctrl = E1000_READ_REG(hw, CTRL);
484 /* Must reset the PHY before resetting the MAC */
485 if((hw->mac_type == e1000_82541) || (hw->mac_type == e1000_82547)) {
486 E1000_WRITE_REG(hw, CTRL, (ctrl | E1000_CTRL_PHY_RST));
490 /* Must acquire the MDIO ownership before MAC reset.
491 * Ownership defaults to firmware after a reset. */
492 if(hw->mac_type == e1000_82573) {
495 extcnf_ctrl = E1000_READ_REG(hw, EXTCNF_CTRL);
496 extcnf_ctrl |= E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP;
499 E1000_WRITE_REG(hw, EXTCNF_CTRL, extcnf_ctrl);
500 extcnf_ctrl = E1000_READ_REG(hw, EXTCNF_CTRL);
502 if(extcnf_ctrl & E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP)
505 extcnf_ctrl |= E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP;
512 /* Issue a global reset to the MAC. This will reset the chip's
513 * transmit, receive, DMA, and link units. It will not effect
514 * the current PCI configuration. The global reset bit is self-
515 * clearing, and should clear within a microsecond.
517 DEBUGOUT("Issuing a global reset to MAC\n");
519 switch(hw->mac_type) {
525 case e1000_82541_rev_2:
526 /* These controllers can't ack the 64-bit write when issuing the
527 * reset, so use IO-mapping as a workaround to issue the reset */
528 E1000_WRITE_REG_IO(hw, CTRL, (ctrl | E1000_CTRL_RST));
530 case e1000_82545_rev_3:
531 case e1000_82546_rev_3:
532 /* Reset is performed on a shadow of the control register */
533 E1000_WRITE_REG(hw, CTRL_DUP, (ctrl | E1000_CTRL_RST));
536 E1000_WRITE_REG(hw, CTRL, (ctrl | E1000_CTRL_RST));
540 /* After MAC reset, force reload of EEPROM to restore power-on settings to
541 * device. Later controllers reload the EEPROM automatically, so just wait
542 * for reload to complete.
544 switch(hw->mac_type) {
545 case e1000_82542_rev2_0:
546 case e1000_82542_rev2_1:
549 /* Wait for reset to complete */
551 ctrl_ext = E1000_READ_REG(hw, CTRL_EXT);
552 ctrl_ext |= E1000_CTRL_EXT_EE_RST;
553 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext);
554 E1000_WRITE_FLUSH(hw);
555 /* Wait for EEPROM reload */
559 case e1000_82541_rev_2:
561 case e1000_82547_rev_2:
562 /* Wait for EEPROM reload */
567 ctrl_ext = E1000_READ_REG(hw, CTRL_EXT);
568 ctrl_ext |= E1000_CTRL_EXT_EE_RST;
569 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext);
570 E1000_WRITE_FLUSH(hw);
574 ret_val = e1000_get_auto_rd_done(hw);
576 /* We don't want to continue accessing MAC registers. */
580 /* Wait for EEPROM reload (it happens automatically) */
585 /* Disable HW ARPs on ASF enabled adapters */
586 if(hw->mac_type >= e1000_82540 && hw->mac_type <= e1000_82547_rev_2) {
587 manc = E1000_READ_REG(hw, MANC);
588 manc &= ~(E1000_MANC_ARP_EN);
589 E1000_WRITE_REG(hw, MANC, manc);
592 if((hw->mac_type == e1000_82541) || (hw->mac_type == e1000_82547)) {
593 e1000_phy_init_script(hw);
595 /* Configure activity LED after PHY reset */
596 led_ctrl = E1000_READ_REG(hw, LEDCTL);
597 led_ctrl &= IGP_ACTIVITY_LED_MASK;
598 led_ctrl |= (IGP_ACTIVITY_LED_ENABLE | IGP_LED3_MODE);
599 E1000_WRITE_REG(hw, LEDCTL, led_ctrl);
602 /* Clear interrupt mask to stop board from generating interrupts */
603 DEBUGOUT("Masking off all interrupts\n");
604 E1000_WRITE_REG(hw, IMC, 0xffffffff);
606 /* Clear any pending interrupt events. */
607 icr = E1000_READ_REG(hw, ICR);
609 /* If MWI was previously enabled, reenable it. */
610 if(hw->mac_type == e1000_82542_rev2_0) {
611 if(hw->pci_cmd_word & CMD_MEM_WRT_INVALIDATE)
612 e1000_pci_set_mwi(hw);
615 return E1000_SUCCESS;
618 /******************************************************************************
619 * Performs basic configuration of the adapter.
621 * hw - Struct containing variables accessed by shared code
623 * Assumes that the controller has previously been reset and is in a
624 * post-reset uninitialized state. Initializes the receive address registers,
625 * multicast table, and VLAN filter table. Calls routines to setup link
626 * configuration and flow control settings. Clears all on-chip counters. Leaves
627 * the transmit and receive units disabled and uninitialized.
628 *****************************************************************************/
630 e1000_init_hw(struct e1000_hw *hw)
635 uint16_t pcix_cmd_word;
636 uint16_t pcix_stat_hi_word;
641 DEBUGFUNC("e1000_init_hw");
643 /* Initialize Identification LED */
644 ret_val = e1000_id_led_init(hw);
646 DEBUGOUT("Error Initializing Identification LED\n");
650 /* Set the media type and TBI compatibility */
651 e1000_set_media_type(hw);
653 /* Disabling VLAN filtering. */
654 DEBUGOUT("Initializing the IEEE VLAN\n");
655 if (hw->mac_type < e1000_82545_rev_3)
656 E1000_WRITE_REG(hw, VET, 0);
657 e1000_clear_vfta(hw);
659 /* For 82542 (rev 2.0), disable MWI and put the receiver into reset */
660 if(hw->mac_type == e1000_82542_rev2_0) {
661 DEBUGOUT("Disabling MWI on 82542 rev 2.0\n");
662 e1000_pci_clear_mwi(hw);
663 E1000_WRITE_REG(hw, RCTL, E1000_RCTL_RST);
664 E1000_WRITE_FLUSH(hw);
668 /* Setup the receive address. This involves initializing all of the Receive
669 * Address Registers (RARs 0 - 15).
671 e1000_init_rx_addrs(hw);
673 /* For 82542 (rev 2.0), take the receiver out of reset and enable MWI */
674 if(hw->mac_type == e1000_82542_rev2_0) {
675 E1000_WRITE_REG(hw, RCTL, 0);
676 E1000_WRITE_FLUSH(hw);
678 if(hw->pci_cmd_word & CMD_MEM_WRT_INVALIDATE)
679 e1000_pci_set_mwi(hw);
682 /* Zero out the Multicast HASH table */
683 DEBUGOUT("Zeroing the MTA\n");
684 mta_size = E1000_MC_TBL_SIZE;
685 for(i = 0; i < mta_size; i++)
686 E1000_WRITE_REG_ARRAY(hw, MTA, i, 0);
688 /* Set the PCI priority bit correctly in the CTRL register. This
689 * determines if the adapter gives priority to receives, or if it
690 * gives equal priority to transmits and receives. Valid only on
691 * 82542 and 82543 silicon.
693 if(hw->dma_fairness && hw->mac_type <= e1000_82543) {
694 ctrl = E1000_READ_REG(hw, CTRL);
695 E1000_WRITE_REG(hw, CTRL, ctrl | E1000_CTRL_PRIOR);
698 switch(hw->mac_type) {
699 case e1000_82545_rev_3:
700 case e1000_82546_rev_3:
703 /* Workaround for PCI-X problem when BIOS sets MMRBC incorrectly. */
704 if(hw->bus_type == e1000_bus_type_pcix) {
705 e1000_read_pci_cfg(hw, PCIX_COMMAND_REGISTER, &pcix_cmd_word);
706 e1000_read_pci_cfg(hw, PCIX_STATUS_REGISTER_HI,
708 cmd_mmrbc = (pcix_cmd_word & PCIX_COMMAND_MMRBC_MASK) >>
709 PCIX_COMMAND_MMRBC_SHIFT;
710 stat_mmrbc = (pcix_stat_hi_word & PCIX_STATUS_HI_MMRBC_MASK) >>
711 PCIX_STATUS_HI_MMRBC_SHIFT;
712 if(stat_mmrbc == PCIX_STATUS_HI_MMRBC_4K)
713 stat_mmrbc = PCIX_STATUS_HI_MMRBC_2K;
714 if(cmd_mmrbc > stat_mmrbc) {
715 pcix_cmd_word &= ~PCIX_COMMAND_MMRBC_MASK;
716 pcix_cmd_word |= stat_mmrbc << PCIX_COMMAND_MMRBC_SHIFT;
717 e1000_write_pci_cfg(hw, PCIX_COMMAND_REGISTER,
724 /* Call a subroutine to configure the link and setup flow control. */
725 ret_val = e1000_setup_link(hw);
727 /* Set the transmit descriptor write-back policy */
728 if(hw->mac_type > e1000_82544) {
729 ctrl = E1000_READ_REG(hw, TXDCTL);
730 ctrl = (ctrl & ~E1000_TXDCTL_WTHRESH) | E1000_TXDCTL_FULL_TX_DESC_WB;
731 switch (hw->mac_type) {
738 ctrl |= E1000_TXDCTL_COUNT_DESC;
741 E1000_WRITE_REG(hw, TXDCTL, ctrl);
744 if (hw->mac_type == e1000_82573) {
745 e1000_enable_tx_pkt_filtering(hw);
748 switch (hw->mac_type) {
753 ctrl = E1000_READ_REG(hw, TXDCTL1);
754 ctrl &= ~E1000_TXDCTL_WTHRESH;
755 ctrl |= E1000_TXDCTL_COUNT_DESC | E1000_TXDCTL_FULL_TX_DESC_WB;
757 E1000_WRITE_REG(hw, TXDCTL1, ctrl);
763 if (hw->mac_type == e1000_82573) {
764 uint32_t gcr = E1000_READ_REG(hw, GCR);
765 gcr |= E1000_GCR_L1_ACT_WITHOUT_L0S_RX;
766 E1000_WRITE_REG(hw, GCR, gcr);
769 /* Clear all of the statistics registers (clear on read). It is
770 * important that we do this after we have tried to establish link
771 * because the symbol error count will increment wildly if there
774 e1000_clear_hw_cntrs(hw);
779 /******************************************************************************
780 * Adjust SERDES output amplitude based on EEPROM setting.
782 * hw - Struct containing variables accessed by shared code.
783 *****************************************************************************/
785 e1000_adjust_serdes_amplitude(struct e1000_hw *hw)
787 uint16_t eeprom_data;
790 DEBUGFUNC("e1000_adjust_serdes_amplitude");
792 if(hw->media_type != e1000_media_type_internal_serdes)
793 return E1000_SUCCESS;
795 switch(hw->mac_type) {
796 case e1000_82545_rev_3:
797 case e1000_82546_rev_3:
800 return E1000_SUCCESS;
803 ret_val = e1000_read_eeprom(hw, EEPROM_SERDES_AMPLITUDE, 1, &eeprom_data);
808 if(eeprom_data != EEPROM_RESERVED_WORD) {
809 /* Adjust SERDES output amplitude only. */
810 eeprom_data &= EEPROM_SERDES_AMPLITUDE_MASK;
811 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_EXT_CTRL, eeprom_data);
816 return E1000_SUCCESS;
819 /******************************************************************************
820 * Configures flow control and link settings.
822 * hw - Struct containing variables accessed by shared code
824 * Determines which flow control settings to use. Calls the apropriate media-
825 * specific link configuration function. Configures the flow control settings.
826 * Assuming the adapter has a valid link partner, a valid link should be
827 * established. Assumes the hardware has previously been reset and the
828 * transmitter and receiver are not enabled.
829 *****************************************************************************/
831 e1000_setup_link(struct e1000_hw *hw)
835 uint16_t eeprom_data;
837 DEBUGFUNC("e1000_setup_link");
839 /* Read and store word 0x0F of the EEPROM. This word contains bits
840 * that determine the hardware's default PAUSE (flow control) mode,
841 * a bit that determines whether the HW defaults to enabling or
842 * disabling auto-negotiation, and the direction of the
843 * SW defined pins. If there is no SW over-ride of the flow
844 * control setting, then the variable hw->fc will
845 * be initialized based on a value in the EEPROM.
847 if(e1000_read_eeprom(hw, EEPROM_INIT_CONTROL2_REG, 1, &eeprom_data)) {
848 DEBUGOUT("EEPROM Read Error\n");
849 return -E1000_ERR_EEPROM;
852 if(hw->fc == e1000_fc_default) {
853 if((eeprom_data & EEPROM_WORD0F_PAUSE_MASK) == 0)
854 hw->fc = e1000_fc_none;
855 else if((eeprom_data & EEPROM_WORD0F_PAUSE_MASK) ==
856 EEPROM_WORD0F_ASM_DIR)
857 hw->fc = e1000_fc_tx_pause;
859 hw->fc = e1000_fc_full;
862 /* We want to save off the original Flow Control configuration just
863 * in case we get disconnected and then reconnected into a different
864 * hub or switch with different Flow Control capabilities.
866 if(hw->mac_type == e1000_82542_rev2_0)
867 hw->fc &= (~e1000_fc_tx_pause);
869 if((hw->mac_type < e1000_82543) && (hw->report_tx_early == 1))
870 hw->fc &= (~e1000_fc_rx_pause);
872 hw->original_fc = hw->fc;
874 DEBUGOUT1("After fix-ups FlowControl is now = %x\n", hw->fc);
876 /* Take the 4 bits from EEPROM word 0x0F that determine the initial
877 * polarity value for the SW controlled pins, and setup the
878 * Extended Device Control reg with that info.
879 * This is needed because one of the SW controlled pins is used for
880 * signal detection. So this should be done before e1000_setup_pcs_link()
881 * or e1000_phy_setup() is called.
883 if(hw->mac_type == e1000_82543) {
884 ctrl_ext = ((eeprom_data & EEPROM_WORD0F_SWPDIO_EXT) <<
886 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext);
889 /* Call the necessary subroutine to configure the link. */
890 ret_val = (hw->media_type == e1000_media_type_copper) ?
891 e1000_setup_copper_link(hw) :
892 e1000_setup_fiber_serdes_link(hw);
894 /* Initialize the flow control address, type, and PAUSE timer
895 * registers to their default values. This is done even if flow
896 * control is disabled, because it does not hurt anything to
897 * initialize these registers.
899 DEBUGOUT("Initializing the Flow Control address, type and timer regs\n");
901 E1000_WRITE_REG(hw, FCAL, FLOW_CONTROL_ADDRESS_LOW);
902 E1000_WRITE_REG(hw, FCAH, FLOW_CONTROL_ADDRESS_HIGH);
903 E1000_WRITE_REG(hw, FCT, FLOW_CONTROL_TYPE);
905 E1000_WRITE_REG(hw, FCTTV, hw->fc_pause_time);
907 /* Set the flow control receive threshold registers. Normally,
908 * these registers will be set to a default threshold that may be
909 * adjusted later by the driver's runtime code. However, if the
910 * ability to transmit pause frames in not enabled, then these
911 * registers will be set to 0.
913 if(!(hw->fc & e1000_fc_tx_pause)) {
914 E1000_WRITE_REG(hw, FCRTL, 0);
915 E1000_WRITE_REG(hw, FCRTH, 0);
917 /* We need to set up the Receive Threshold high and low water marks
918 * as well as (optionally) enabling the transmission of XON frames.
920 if(hw->fc_send_xon) {
921 E1000_WRITE_REG(hw, FCRTL, (hw->fc_low_water | E1000_FCRTL_XONE));
922 E1000_WRITE_REG(hw, FCRTH, hw->fc_high_water);
924 E1000_WRITE_REG(hw, FCRTL, hw->fc_low_water);
925 E1000_WRITE_REG(hw, FCRTH, hw->fc_high_water);
931 /******************************************************************************
932 * Sets up link for a fiber based or serdes based adapter
934 * hw - Struct containing variables accessed by shared code
936 * Manipulates Physical Coding Sublayer functions in order to configure
937 * link. Assumes the hardware has been previously reset and the transmitter
938 * and receiver are not enabled.
939 *****************************************************************************/
941 e1000_setup_fiber_serdes_link(struct e1000_hw *hw)
950 DEBUGFUNC("e1000_setup_fiber_serdes_link");
952 /* On 82571 and 82572 Fiber connections, SerDes loopback mode persists
953 * until explicitly turned off or a power cycle is performed. A read to
954 * the register does not indicate its status. Therefore, we ensure
955 * loopback mode is disabled during initialization.
957 if (hw->mac_type == e1000_82571 || hw->mac_type == e1000_82572)
958 E1000_WRITE_REG(hw, SCTL, E1000_DISABLE_SERDES_LOOPBACK);
960 /* On adapters with a MAC newer than 82544, SW Defineable pin 1 will be
961 * set when the optics detect a signal. On older adapters, it will be
962 * cleared when there is a signal. This applies to fiber media only.
963 * If we're on serdes media, adjust the output amplitude to value set in
966 ctrl = E1000_READ_REG(hw, CTRL);
967 if(hw->media_type == e1000_media_type_fiber)
968 signal = (hw->mac_type > e1000_82544) ? E1000_CTRL_SWDPIN1 : 0;
970 ret_val = e1000_adjust_serdes_amplitude(hw);
974 /* Take the link out of reset */
975 ctrl &= ~(E1000_CTRL_LRST);
977 /* Adjust VCO speed to improve BER performance */
978 ret_val = e1000_set_vco_speed(hw);
982 e1000_config_collision_dist(hw);
984 /* Check for a software override of the flow control settings, and setup
985 * the device accordingly. If auto-negotiation is enabled, then software
986 * will have to set the "PAUSE" bits to the correct value in the Tranmsit
987 * Config Word Register (TXCW) and re-start auto-negotiation. However, if
988 * auto-negotiation is disabled, then software will have to manually
989 * configure the two flow control enable bits in the CTRL register.
991 * The possible values of the "fc" parameter are:
992 * 0: Flow control is completely disabled
993 * 1: Rx flow control is enabled (we can receive pause frames, but
994 * not send pause frames).
995 * 2: Tx flow control is enabled (we can send pause frames but we do
996 * not support receiving pause frames).
997 * 3: Both Rx and TX flow control (symmetric) are enabled.
1001 /* Flow control is completely disabled by a software over-ride. */
1002 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD);
1004 case e1000_fc_rx_pause:
1005 /* RX Flow control is enabled and TX Flow control is disabled by a
1006 * software over-ride. Since there really isn't a way to advertise
1007 * that we are capable of RX Pause ONLY, we will advertise that we
1008 * support both symmetric and asymmetric RX PAUSE. Later, we will
1009 * disable the adapter's ability to send PAUSE frames.
1011 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_PAUSE_MASK);
1013 case e1000_fc_tx_pause:
1014 /* TX Flow control is enabled, and RX Flow control is disabled, by a
1015 * software over-ride.
1017 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_ASM_DIR);
1020 /* Flow control (both RX and TX) is enabled by a software over-ride. */
1021 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_PAUSE_MASK);
1024 DEBUGOUT("Flow control param set incorrectly\n");
1025 return -E1000_ERR_CONFIG;
1029 /* Since auto-negotiation is enabled, take the link out of reset (the link
1030 * will be in reset, because we previously reset the chip). This will
1031 * restart auto-negotiation. If auto-neogtiation is successful then the
1032 * link-up status bit will be set and the flow control enable bits (RFCE
1033 * and TFCE) will be set according to their negotiated value.
1035 DEBUGOUT("Auto-negotiation enabled\n");
1037 E1000_WRITE_REG(hw, TXCW, txcw);
1038 E1000_WRITE_REG(hw, CTRL, ctrl);
1039 E1000_WRITE_FLUSH(hw);
1044 /* If we have a signal (the cable is plugged in) then poll for a "Link-Up"
1045 * indication in the Device Status Register. Time-out if a link isn't
1046 * seen in 500 milliseconds seconds (Auto-negotiation should complete in
1047 * less than 500 milliseconds even if the other end is doing it in SW).
1048 * For internal serdes, we just assume a signal is present, then poll.
1050 if(hw->media_type == e1000_media_type_internal_serdes ||
1051 (E1000_READ_REG(hw, CTRL) & E1000_CTRL_SWDPIN1) == signal) {
1052 DEBUGOUT("Looking for Link\n");
1053 for(i = 0; i < (LINK_UP_TIMEOUT / 10); i++) {
1055 status = E1000_READ_REG(hw, STATUS);
1056 if(status & E1000_STATUS_LU) break;
1058 if(i == (LINK_UP_TIMEOUT / 10)) {
1059 DEBUGOUT("Never got a valid link from auto-neg!!!\n");
1060 hw->autoneg_failed = 1;
1061 /* AutoNeg failed to achieve a link, so we'll call
1062 * e1000_check_for_link. This routine will force the link up if
1063 * we detect a signal. This will allow us to communicate with
1064 * non-autonegotiating link partners.
1066 ret_val = e1000_check_for_link(hw);
1068 DEBUGOUT("Error while checking for link\n");
1071 hw->autoneg_failed = 0;
1073 hw->autoneg_failed = 0;
1074 DEBUGOUT("Valid Link Found\n");
1077 DEBUGOUT("No Signal Detected\n");
1079 return E1000_SUCCESS;
1082 /******************************************************************************
1083 * Make sure we have a valid PHY and change PHY mode before link setup.
1085 * hw - Struct containing variables accessed by shared code
1086 ******************************************************************************/
1088 e1000_copper_link_preconfig(struct e1000_hw *hw)
1094 DEBUGFUNC("e1000_copper_link_preconfig");
1096 ctrl = E1000_READ_REG(hw, CTRL);
1097 /* With 82543, we need to force speed and duplex on the MAC equal to what
1098 * the PHY speed and duplex configuration is. In addition, we need to
1099 * perform a hardware reset on the PHY to take it out of reset.
1101 if(hw->mac_type > e1000_82543) {
1102 ctrl |= E1000_CTRL_SLU;
1103 ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
1104 E1000_WRITE_REG(hw, CTRL, ctrl);
1106 ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX | E1000_CTRL_SLU);
1107 E1000_WRITE_REG(hw, CTRL, ctrl);
1108 ret_val = e1000_phy_hw_reset(hw);
1113 /* Make sure we have a valid PHY */
1114 ret_val = e1000_detect_gig_phy(hw);
1116 DEBUGOUT("Error, did not detect valid phy.\n");
1119 DEBUGOUT1("Phy ID = %x \n", hw->phy_id);
1121 /* Set PHY to class A mode (if necessary) */
1122 ret_val = e1000_set_phy_mode(hw);
1126 if((hw->mac_type == e1000_82545_rev_3) ||
1127 (hw->mac_type == e1000_82546_rev_3)) {
1128 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
1129 phy_data |= 0x00000008;
1130 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data);
1133 if(hw->mac_type <= e1000_82543 ||
1134 hw->mac_type == e1000_82541 || hw->mac_type == e1000_82547 ||
1135 hw->mac_type == e1000_82541_rev_2 || hw->mac_type == e1000_82547_rev_2)
1136 hw->phy_reset_disable = FALSE;
1138 return E1000_SUCCESS;
1142 /********************************************************************
1143 * Copper link setup for e1000_phy_igp series.
1145 * hw - Struct containing variables accessed by shared code
1146 *********************************************************************/
1148 e1000_copper_link_igp_setup(struct e1000_hw *hw)
1154 DEBUGFUNC("e1000_copper_link_igp_setup");
1156 if (hw->phy_reset_disable)
1157 return E1000_SUCCESS;
1159 ret_val = e1000_phy_reset(hw);
1161 DEBUGOUT("Error Resetting the PHY\n");
1165 /* Wait 10ms for MAC to configure PHY from eeprom settings */
1168 /* Configure activity LED after PHY reset */
1169 led_ctrl = E1000_READ_REG(hw, LEDCTL);
1170 led_ctrl &= IGP_ACTIVITY_LED_MASK;
1171 led_ctrl |= (IGP_ACTIVITY_LED_ENABLE | IGP_LED3_MODE);
1172 E1000_WRITE_REG(hw, LEDCTL, led_ctrl);
1174 /* disable lplu d3 during driver init */
1175 ret_val = e1000_set_d3_lplu_state(hw, FALSE);
1177 DEBUGOUT("Error Disabling LPLU D3\n");
1181 /* disable lplu d0 during driver init */
1182 ret_val = e1000_set_d0_lplu_state(hw, FALSE);
1184 DEBUGOUT("Error Disabling LPLU D0\n");
1187 /* Configure mdi-mdix settings */
1188 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL, &phy_data);
1192 if ((hw->mac_type == e1000_82541) || (hw->mac_type == e1000_82547)) {
1193 hw->dsp_config_state = e1000_dsp_config_disabled;
1194 /* Force MDI for earlier revs of the IGP PHY */
1195 phy_data &= ~(IGP01E1000_PSCR_AUTO_MDIX | IGP01E1000_PSCR_FORCE_MDI_MDIX);
1199 hw->dsp_config_state = e1000_dsp_config_enabled;
1200 phy_data &= ~IGP01E1000_PSCR_AUTO_MDIX;
1204 phy_data &= ~IGP01E1000_PSCR_FORCE_MDI_MDIX;
1207 phy_data |= IGP01E1000_PSCR_FORCE_MDI_MDIX;
1211 phy_data |= IGP01E1000_PSCR_AUTO_MDIX;
1215 ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL, phy_data);
1219 /* set auto-master slave resolution settings */
1221 e1000_ms_type phy_ms_setting = hw->master_slave;
1223 if(hw->ffe_config_state == e1000_ffe_config_active)
1224 hw->ffe_config_state = e1000_ffe_config_enabled;
1226 if(hw->dsp_config_state == e1000_dsp_config_activated)
1227 hw->dsp_config_state = e1000_dsp_config_enabled;
1229 /* when autonegotiation advertisment is only 1000Mbps then we
1230 * should disable SmartSpeed and enable Auto MasterSlave
1231 * resolution as hardware default. */
1232 if(hw->autoneg_advertised == ADVERTISE_1000_FULL) {
1233 /* Disable SmartSpeed */
1234 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, &phy_data);
1237 phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED;
1238 ret_val = e1000_write_phy_reg(hw,
1239 IGP01E1000_PHY_PORT_CONFIG,
1243 /* Set auto Master/Slave resolution process */
1244 ret_val = e1000_read_phy_reg(hw, PHY_1000T_CTRL, &phy_data);
1247 phy_data &= ~CR_1000T_MS_ENABLE;
1248 ret_val = e1000_write_phy_reg(hw, PHY_1000T_CTRL, phy_data);
1253 ret_val = e1000_read_phy_reg(hw, PHY_1000T_CTRL, &phy_data);
1257 /* load defaults for future use */
1258 hw->original_master_slave = (phy_data & CR_1000T_MS_ENABLE) ?
1259 ((phy_data & CR_1000T_MS_VALUE) ?
1260 e1000_ms_force_master :
1261 e1000_ms_force_slave) :
1264 switch (phy_ms_setting) {
1265 case e1000_ms_force_master:
1266 phy_data |= (CR_1000T_MS_ENABLE | CR_1000T_MS_VALUE);
1268 case e1000_ms_force_slave:
1269 phy_data |= CR_1000T_MS_ENABLE;
1270 phy_data &= ~(CR_1000T_MS_VALUE);
1273 phy_data &= ~CR_1000T_MS_ENABLE;
1277 ret_val = e1000_write_phy_reg(hw, PHY_1000T_CTRL, phy_data);
1282 return E1000_SUCCESS;
1286 /********************************************************************
1287 * Copper link setup for e1000_phy_m88 series.
1289 * hw - Struct containing variables accessed by shared code
1290 *********************************************************************/
1292 e1000_copper_link_mgp_setup(struct e1000_hw *hw)
1297 DEBUGFUNC("e1000_copper_link_mgp_setup");
1299 if(hw->phy_reset_disable)
1300 return E1000_SUCCESS;
1302 /* Enable CRS on TX. This must be set for half-duplex operation. */
1303 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
1307 phy_data |= M88E1000_PSCR_ASSERT_CRS_ON_TX;
1310 * MDI/MDI-X = 0 (default)
1311 * 0 - Auto for all speeds
1314 * 3 - Auto for 1000Base-T only (MDI-X for 10/100Base-T modes)
1316 phy_data &= ~M88E1000_PSCR_AUTO_X_MODE;
1320 phy_data |= M88E1000_PSCR_MDI_MANUAL_MODE;
1323 phy_data |= M88E1000_PSCR_MDIX_MANUAL_MODE;
1326 phy_data |= M88E1000_PSCR_AUTO_X_1000T;
1330 phy_data |= M88E1000_PSCR_AUTO_X_MODE;
1335 * disable_polarity_correction = 0 (default)
1336 * Automatic Correction for Reversed Cable Polarity
1340 phy_data &= ~M88E1000_PSCR_POLARITY_REVERSAL;
1341 if(hw->disable_polarity_correction == 1)
1342 phy_data |= M88E1000_PSCR_POLARITY_REVERSAL;
1343 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data);
1347 /* Force TX_CLK in the Extended PHY Specific Control Register
1350 ret_val = e1000_read_phy_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, &phy_data);
1354 phy_data |= M88E1000_EPSCR_TX_CLK_25;
1356 if (hw->phy_revision < M88E1011_I_REV_4) {
1357 /* Configure Master and Slave downshift values */
1358 phy_data &= ~(M88E1000_EPSCR_MASTER_DOWNSHIFT_MASK |
1359 M88E1000_EPSCR_SLAVE_DOWNSHIFT_MASK);
1360 phy_data |= (M88E1000_EPSCR_MASTER_DOWNSHIFT_1X |
1361 M88E1000_EPSCR_SLAVE_DOWNSHIFT_1X);
1362 ret_val = e1000_write_phy_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, phy_data);
1367 /* SW Reset the PHY so all changes take effect */
1368 ret_val = e1000_phy_reset(hw);
1370 DEBUGOUT("Error Resetting the PHY\n");
1374 return E1000_SUCCESS;
1377 /********************************************************************
1378 * Setup auto-negotiation and flow control advertisements,
1379 * and then perform auto-negotiation.
1381 * hw - Struct containing variables accessed by shared code
1382 *********************************************************************/
1384 e1000_copper_link_autoneg(struct e1000_hw *hw)
1389 DEBUGFUNC("e1000_copper_link_autoneg");
1391 /* Perform some bounds checking on the hw->autoneg_advertised
1392 * parameter. If this variable is zero, then set it to the default.
1394 hw->autoneg_advertised &= AUTONEG_ADVERTISE_SPEED_DEFAULT;
1396 /* If autoneg_advertised is zero, we assume it was not defaulted
1397 * by the calling code so we set to advertise full capability.
1399 if(hw->autoneg_advertised == 0)
1400 hw->autoneg_advertised = AUTONEG_ADVERTISE_SPEED_DEFAULT;
1402 DEBUGOUT("Reconfiguring auto-neg advertisement params\n");
1403 ret_val = e1000_phy_setup_autoneg(hw);
1405 DEBUGOUT("Error Setting up Auto-Negotiation\n");
1408 DEBUGOUT("Restarting Auto-Neg\n");
1410 /* Restart auto-negotiation by setting the Auto Neg Enable bit and
1411 * the Auto Neg Restart bit in the PHY control register.
1413 ret_val = e1000_read_phy_reg(hw, PHY_CTRL, &phy_data);
1417 phy_data |= (MII_CR_AUTO_NEG_EN | MII_CR_RESTART_AUTO_NEG);
1418 ret_val = e1000_write_phy_reg(hw, PHY_CTRL, phy_data);
1422 /* Does the user want to wait for Auto-Neg to complete here, or
1423 * check at a later time (for example, callback routine).
1425 if(hw->wait_autoneg_complete) {
1426 ret_val = e1000_wait_autoneg(hw);
1428 DEBUGOUT("Error while waiting for autoneg to complete\n");
1433 hw->get_link_status = TRUE;
1435 return E1000_SUCCESS;
1439 /******************************************************************************
1440 * Config the MAC and the PHY after link is up.
1441 * 1) Set up the MAC to the current PHY speed/duplex
1442 * if we are on 82543. If we
1443 * are on newer silicon, we only need to configure
1444 * collision distance in the Transmit Control Register.
1445 * 2) Set up flow control on the MAC to that established with
1447 * 3) Config DSP to improve Gigabit link quality for some PHY revisions.
1449 * hw - Struct containing variables accessed by shared code
1450 ******************************************************************************/
1452 e1000_copper_link_postconfig(struct e1000_hw *hw)
1455 DEBUGFUNC("e1000_copper_link_postconfig");
1457 if(hw->mac_type >= e1000_82544) {
1458 e1000_config_collision_dist(hw);
1460 ret_val = e1000_config_mac_to_phy(hw);
1462 DEBUGOUT("Error configuring MAC to PHY settings\n");
1466 ret_val = e1000_config_fc_after_link_up(hw);
1468 DEBUGOUT("Error Configuring Flow Control\n");
1472 /* Config DSP to improve Giga link quality */
1473 if(hw->phy_type == e1000_phy_igp) {
1474 ret_val = e1000_config_dsp_after_link_change(hw, TRUE);
1476 DEBUGOUT("Error Configuring DSP after link up\n");
1481 return E1000_SUCCESS;
1484 /******************************************************************************
1485 * Detects which PHY is present and setup the speed and duplex
1487 * hw - Struct containing variables accessed by shared code
1488 ******************************************************************************/
1490 e1000_setup_copper_link(struct e1000_hw *hw)
1496 DEBUGFUNC("e1000_setup_copper_link");
1498 /* Check if it is a valid PHY and set PHY mode if necessary. */
1499 ret_val = e1000_copper_link_preconfig(hw);
1503 if (hw->phy_type == e1000_phy_igp ||
1504 hw->phy_type == e1000_phy_igp_2) {
1505 ret_val = e1000_copper_link_igp_setup(hw);
1508 } else if (hw->phy_type == e1000_phy_m88) {
1509 ret_val = e1000_copper_link_mgp_setup(hw);
1515 /* Setup autoneg and flow control advertisement
1516 * and perform autonegotiation */
1517 ret_val = e1000_copper_link_autoneg(hw);
1521 /* PHY will be set to 10H, 10F, 100H,or 100F
1522 * depending on value from forced_speed_duplex. */
1523 DEBUGOUT("Forcing speed and duplex\n");
1524 ret_val = e1000_phy_force_speed_duplex(hw);
1526 DEBUGOUT("Error Forcing Speed and Duplex\n");
1531 /* Check link status. Wait up to 100 microseconds for link to become
1534 for(i = 0; i < 10; i++) {
1535 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data);
1538 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data);
1542 if(phy_data & MII_SR_LINK_STATUS) {
1543 /* Config the MAC and PHY after link is up */
1544 ret_val = e1000_copper_link_postconfig(hw);
1548 DEBUGOUT("Valid link established!!!\n");
1549 return E1000_SUCCESS;
1554 DEBUGOUT("Unable to establish link!!!\n");
1555 return E1000_SUCCESS;
1558 /******************************************************************************
1559 * Configures PHY autoneg and flow control advertisement settings
1561 * hw - Struct containing variables accessed by shared code
1562 ******************************************************************************/
1564 e1000_phy_setup_autoneg(struct e1000_hw *hw)
1567 uint16_t mii_autoneg_adv_reg;
1568 uint16_t mii_1000t_ctrl_reg;
1570 DEBUGFUNC("e1000_phy_setup_autoneg");
1572 /* Read the MII Auto-Neg Advertisement Register (Address 4). */
1573 ret_val = e1000_read_phy_reg(hw, PHY_AUTONEG_ADV, &mii_autoneg_adv_reg);
1577 /* Read the MII 1000Base-T Control Register (Address 9). */
1578 ret_val = e1000_read_phy_reg(hw, PHY_1000T_CTRL, &mii_1000t_ctrl_reg);
1582 /* Need to parse both autoneg_advertised and fc and set up
1583 * the appropriate PHY registers. First we will parse for
1584 * autoneg_advertised software override. Since we can advertise
1585 * a plethora of combinations, we need to check each bit
1589 /* First we clear all the 10/100 mb speed bits in the Auto-Neg
1590 * Advertisement Register (Address 4) and the 1000 mb speed bits in
1591 * the 1000Base-T Control Register (Address 9).
1593 mii_autoneg_adv_reg &= ~REG4_SPEED_MASK;
1594 mii_1000t_ctrl_reg &= ~REG9_SPEED_MASK;
1596 DEBUGOUT1("autoneg_advertised %x\n", hw->autoneg_advertised);
1598 /* Do we want to advertise 10 Mb Half Duplex? */
1599 if(hw->autoneg_advertised & ADVERTISE_10_HALF) {
1600 DEBUGOUT("Advertise 10mb Half duplex\n");
1601 mii_autoneg_adv_reg |= NWAY_AR_10T_HD_CAPS;
1604 /* Do we want to advertise 10 Mb Full Duplex? */
1605 if(hw->autoneg_advertised & ADVERTISE_10_FULL) {
1606 DEBUGOUT("Advertise 10mb Full duplex\n");
1607 mii_autoneg_adv_reg |= NWAY_AR_10T_FD_CAPS;
1610 /* Do we want to advertise 100 Mb Half Duplex? */
1611 if(hw->autoneg_advertised & ADVERTISE_100_HALF) {
1612 DEBUGOUT("Advertise 100mb Half duplex\n");
1613 mii_autoneg_adv_reg |= NWAY_AR_100TX_HD_CAPS;
1616 /* Do we want to advertise 100 Mb Full Duplex? */
1617 if(hw->autoneg_advertised & ADVERTISE_100_FULL) {
1618 DEBUGOUT("Advertise 100mb Full duplex\n");
1619 mii_autoneg_adv_reg |= NWAY_AR_100TX_FD_CAPS;
1622 /* We do not allow the Phy to advertise 1000 Mb Half Duplex */
1623 if(hw->autoneg_advertised & ADVERTISE_1000_HALF) {
1624 DEBUGOUT("Advertise 1000mb Half duplex requested, request denied!\n");
1627 /* Do we want to advertise 1000 Mb Full Duplex? */
1628 if(hw->autoneg_advertised & ADVERTISE_1000_FULL) {
1629 DEBUGOUT("Advertise 1000mb Full duplex\n");
1630 mii_1000t_ctrl_reg |= CR_1000T_FD_CAPS;
1633 /* Check for a software override of the flow control settings, and
1634 * setup the PHY advertisement registers accordingly. If
1635 * auto-negotiation is enabled, then software will have to set the
1636 * "PAUSE" bits to the correct value in the Auto-Negotiation
1637 * Advertisement Register (PHY_AUTONEG_ADV) and re-start auto-negotiation.
1639 * The possible values of the "fc" parameter are:
1640 * 0: Flow control is completely disabled
1641 * 1: Rx flow control is enabled (we can receive pause frames
1642 * but not send pause frames).
1643 * 2: Tx flow control is enabled (we can send pause frames
1644 * but we do not support receiving pause frames).
1645 * 3: Both Rx and TX flow control (symmetric) are enabled.
1646 * other: No software override. The flow control configuration
1647 * in the EEPROM is used.
1650 case e1000_fc_none: /* 0 */
1651 /* Flow control (RX & TX) is completely disabled by a
1652 * software over-ride.
1654 mii_autoneg_adv_reg &= ~(NWAY_AR_ASM_DIR | NWAY_AR_PAUSE);
1656 case e1000_fc_rx_pause: /* 1 */
1657 /* RX Flow control is enabled, and TX Flow control is
1658 * disabled, by a software over-ride.
1660 /* Since there really isn't a way to advertise that we are
1661 * capable of RX Pause ONLY, we will advertise that we
1662 * support both symmetric and asymmetric RX PAUSE. Later
1663 * (in e1000_config_fc_after_link_up) we will disable the
1664 *hw's ability to send PAUSE frames.
1666 mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE);
1668 case e1000_fc_tx_pause: /* 2 */
1669 /* TX Flow control is enabled, and RX Flow control is
1670 * disabled, by a software over-ride.
1672 mii_autoneg_adv_reg |= NWAY_AR_ASM_DIR;
1673 mii_autoneg_adv_reg &= ~NWAY_AR_PAUSE;
1675 case e1000_fc_full: /* 3 */
1676 /* Flow control (both RX and TX) is enabled by a software
1679 mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE);
1682 DEBUGOUT("Flow control param set incorrectly\n");
1683 return -E1000_ERR_CONFIG;
1686 ret_val = e1000_write_phy_reg(hw, PHY_AUTONEG_ADV, mii_autoneg_adv_reg);
1690 DEBUGOUT1("Auto-Neg Advertising %x\n", mii_autoneg_adv_reg);
1692 ret_val = e1000_write_phy_reg(hw, PHY_1000T_CTRL, mii_1000t_ctrl_reg);
1696 return E1000_SUCCESS;
1699 /******************************************************************************
1700 * Force PHY speed and duplex settings to hw->forced_speed_duplex
1702 * hw - Struct containing variables accessed by shared code
1703 ******************************************************************************/
1705 e1000_phy_force_speed_duplex(struct e1000_hw *hw)
1709 uint16_t mii_ctrl_reg;
1710 uint16_t mii_status_reg;
1714 DEBUGFUNC("e1000_phy_force_speed_duplex");
1716 /* Turn off Flow control if we are forcing speed and duplex. */
1717 hw->fc = e1000_fc_none;
1719 DEBUGOUT1("hw->fc = %d\n", hw->fc);
1721 /* Read the Device Control Register. */
1722 ctrl = E1000_READ_REG(hw, CTRL);
1724 /* Set the bits to Force Speed and Duplex in the Device Ctrl Reg. */
1725 ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
1726 ctrl &= ~(DEVICE_SPEED_MASK);
1728 /* Clear the Auto Speed Detect Enable bit. */
1729 ctrl &= ~E1000_CTRL_ASDE;
1731 /* Read the MII Control Register. */
1732 ret_val = e1000_read_phy_reg(hw, PHY_CTRL, &mii_ctrl_reg);
1736 /* We need to disable autoneg in order to force link and duplex. */
1738 mii_ctrl_reg &= ~MII_CR_AUTO_NEG_EN;
1740 /* Are we forcing Full or Half Duplex? */
1741 if(hw->forced_speed_duplex == e1000_100_full ||
1742 hw->forced_speed_duplex == e1000_10_full) {
1743 /* We want to force full duplex so we SET the full duplex bits in the
1744 * Device and MII Control Registers.
1746 ctrl |= E1000_CTRL_FD;
1747 mii_ctrl_reg |= MII_CR_FULL_DUPLEX;
1748 DEBUGOUT("Full Duplex\n");
1750 /* We want to force half duplex so we CLEAR the full duplex bits in
1751 * the Device and MII Control Registers.
1753 ctrl &= ~E1000_CTRL_FD;
1754 mii_ctrl_reg &= ~MII_CR_FULL_DUPLEX;
1755 DEBUGOUT("Half Duplex\n");
1758 /* Are we forcing 100Mbps??? */
1759 if(hw->forced_speed_duplex == e1000_100_full ||
1760 hw->forced_speed_duplex == e1000_100_half) {
1761 /* Set the 100Mb bit and turn off the 1000Mb and 10Mb bits. */
1762 ctrl |= E1000_CTRL_SPD_100;
1763 mii_ctrl_reg |= MII_CR_SPEED_100;
1764 mii_ctrl_reg &= ~(MII_CR_SPEED_1000 | MII_CR_SPEED_10);
1765 DEBUGOUT("Forcing 100mb ");
1767 /* Set the 10Mb bit and turn off the 1000Mb and 100Mb bits. */
1768 ctrl &= ~(E1000_CTRL_SPD_1000 | E1000_CTRL_SPD_100);
1769 mii_ctrl_reg |= MII_CR_SPEED_10;
1770 mii_ctrl_reg &= ~(MII_CR_SPEED_1000 | MII_CR_SPEED_100);
1771 DEBUGOUT("Forcing 10mb ");
1774 e1000_config_collision_dist(hw);
1776 /* Write the configured values back to the Device Control Reg. */
1777 E1000_WRITE_REG(hw, CTRL, ctrl);
1779 if (hw->phy_type == e1000_phy_m88) {
1780 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
1784 /* Clear Auto-Crossover to force MDI manually. M88E1000 requires MDI
1785 * forced whenever speed are duplex are forced.
1787 phy_data &= ~M88E1000_PSCR_AUTO_X_MODE;
1788 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data);
1792 DEBUGOUT1("M88E1000 PSCR: %x \n", phy_data);
1794 /* Need to reset the PHY or these changes will be ignored */
1795 mii_ctrl_reg |= MII_CR_RESET;
1797 /* Clear Auto-Crossover to force MDI manually. IGP requires MDI
1798 * forced whenever speed or duplex are forced.
1800 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL, &phy_data);
1804 phy_data &= ~IGP01E1000_PSCR_AUTO_MDIX;
1805 phy_data &= ~IGP01E1000_PSCR_FORCE_MDI_MDIX;
1807 ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL, phy_data);
1812 /* Write back the modified PHY MII control register. */
1813 ret_val = e1000_write_phy_reg(hw, PHY_CTRL, mii_ctrl_reg);
1819 /* The wait_autoneg_complete flag may be a little misleading here.
1820 * Since we are forcing speed and duplex, Auto-Neg is not enabled.
1821 * But we do want to delay for a period while forcing only so we
1822 * don't generate false No Link messages. So we will wait here
1823 * only if the user has set wait_autoneg_complete to 1, which is
1826 if(hw->wait_autoneg_complete) {
1827 /* We will wait for autoneg to complete. */
1828 DEBUGOUT("Waiting for forced speed/duplex link.\n");
1831 /* We will wait for autoneg to complete or 4.5 seconds to expire. */
1832 for(i = PHY_FORCE_TIME; i > 0; i--) {
1833 /* Read the MII Status Register and wait for Auto-Neg Complete bit
1836 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg);
1840 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg);
1844 if(mii_status_reg & MII_SR_LINK_STATUS) break;
1848 (hw->phy_type == e1000_phy_m88)) {
1849 /* We didn't get link. Reset the DSP and wait again for link. */
1850 ret_val = e1000_phy_reset_dsp(hw);
1852 DEBUGOUT("Error Resetting PHY DSP\n");
1856 /* This loop will early-out if the link condition has been met. */
1857 for(i = PHY_FORCE_TIME; i > 0; i--) {
1858 if(mii_status_reg & MII_SR_LINK_STATUS) break;
1860 /* Read the MII Status Register and wait for Auto-Neg Complete bit
1863 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg);
1867 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg);
1873 if (hw->phy_type == e1000_phy_m88) {
1874 /* Because we reset the PHY above, we need to re-force TX_CLK in the
1875 * Extended PHY Specific Control Register to 25MHz clock. This value
1876 * defaults back to a 2.5MHz clock when the PHY is reset.
1878 ret_val = e1000_read_phy_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, &phy_data);
1882 phy_data |= M88E1000_EPSCR_TX_CLK_25;
1883 ret_val = e1000_write_phy_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, phy_data);
1887 /* In addition, because of the s/w reset above, we need to enable CRS on
1888 * TX. This must be set for both full and half duplex operation.
1890 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
1894 phy_data |= M88E1000_PSCR_ASSERT_CRS_ON_TX;
1895 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data);
1899 if((hw->mac_type == e1000_82544 || hw->mac_type == e1000_82543) &&
1901 (hw->forced_speed_duplex == e1000_10_full ||
1902 hw->forced_speed_duplex == e1000_10_half)) {
1903 ret_val = e1000_polarity_reversal_workaround(hw);
1908 return E1000_SUCCESS;
1911 /******************************************************************************
1912 * Sets the collision distance in the Transmit Control register
1914 * hw - Struct containing variables accessed by shared code
1916 * Link should have been established previously. Reads the speed and duplex
1917 * information from the Device Status register.
1918 ******************************************************************************/
1920 e1000_config_collision_dist(struct e1000_hw *hw)
1924 DEBUGFUNC("e1000_config_collision_dist");
1926 tctl = E1000_READ_REG(hw, TCTL);
1928 tctl &= ~E1000_TCTL_COLD;
1929 tctl |= E1000_COLLISION_DISTANCE << E1000_COLD_SHIFT;
1931 E1000_WRITE_REG(hw, TCTL, tctl);
1932 E1000_WRITE_FLUSH(hw);
1935 /******************************************************************************
1936 * Sets MAC speed and duplex settings to reflect the those in the PHY
1938 * hw - Struct containing variables accessed by shared code
1939 * mii_reg - data to write to the MII control register
1941 * The contents of the PHY register containing the needed information need to
1943 ******************************************************************************/
1945 e1000_config_mac_to_phy(struct e1000_hw *hw)
1951 DEBUGFUNC("e1000_config_mac_to_phy");
1953 /* 82544 or newer MAC, Auto Speed Detection takes care of
1954 * MAC speed/duplex configuration.*/
1955 if (hw->mac_type >= e1000_82544)
1956 return E1000_SUCCESS;
1958 /* Read the Device Control Register and set the bits to Force Speed
1961 ctrl = E1000_READ_REG(hw, CTRL);
1962 ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
1963 ctrl &= ~(E1000_CTRL_SPD_SEL | E1000_CTRL_ILOS);
1965 /* Set up duplex in the Device Control and Transmit Control
1966 * registers depending on negotiated values.
1968 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS, &phy_data);
1972 if(phy_data & M88E1000_PSSR_DPLX)
1973 ctrl |= E1000_CTRL_FD;
1975 ctrl &= ~E1000_CTRL_FD;
1977 e1000_config_collision_dist(hw);
1979 /* Set up speed in the Device Control register depending on
1980 * negotiated values.
1982 if((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_1000MBS)
1983 ctrl |= E1000_CTRL_SPD_1000;
1984 else if((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_100MBS)
1985 ctrl |= E1000_CTRL_SPD_100;
1987 /* Write the configured values back to the Device Control Reg. */
1988 E1000_WRITE_REG(hw, CTRL, ctrl);
1989 return E1000_SUCCESS;
1992 /******************************************************************************
1993 * Forces the MAC's flow control settings.
1995 * hw - Struct containing variables accessed by shared code
1997 * Sets the TFCE and RFCE bits in the device control register to reflect
1998 * the adapter settings. TFCE and RFCE need to be explicitly set by
1999 * software when a Copper PHY is used because autonegotiation is managed
2000 * by the PHY rather than the MAC. Software must also configure these
2001 * bits when link is forced on a fiber connection.
2002 *****************************************************************************/
2004 e1000_force_mac_fc(struct e1000_hw *hw)
2008 DEBUGFUNC("e1000_force_mac_fc");
2010 /* Get the current configuration of the Device Control Register */
2011 ctrl = E1000_READ_REG(hw, CTRL);
2013 /* Because we didn't get link via the internal auto-negotiation
2014 * mechanism (we either forced link or we got link via PHY
2015 * auto-neg), we have to manually enable/disable transmit an
2016 * receive flow control.
2018 * The "Case" statement below enables/disable flow control
2019 * according to the "hw->fc" parameter.
2021 * The possible values of the "fc" parameter are:
2022 * 0: Flow control is completely disabled
2023 * 1: Rx flow control is enabled (we can receive pause
2024 * frames but not send pause frames).
2025 * 2: Tx flow control is enabled (we can send pause frames
2026 * frames but we do not receive pause frames).
2027 * 3: Both Rx and TX flow control (symmetric) is enabled.
2028 * other: No other values should be possible at this point.
2033 ctrl &= (~(E1000_CTRL_TFCE | E1000_CTRL_RFCE));
2035 case e1000_fc_rx_pause:
2036 ctrl &= (~E1000_CTRL_TFCE);
2037 ctrl |= E1000_CTRL_RFCE;
2039 case e1000_fc_tx_pause:
2040 ctrl &= (~E1000_CTRL_RFCE);
2041 ctrl |= E1000_CTRL_TFCE;
2044 ctrl |= (E1000_CTRL_TFCE | E1000_CTRL_RFCE);
2047 DEBUGOUT("Flow control param set incorrectly\n");
2048 return -E1000_ERR_CONFIG;
2051 /* Disable TX Flow Control for 82542 (rev 2.0) */
2052 if(hw->mac_type == e1000_82542_rev2_0)
2053 ctrl &= (~E1000_CTRL_TFCE);
2055 E1000_WRITE_REG(hw, CTRL, ctrl);
2056 return E1000_SUCCESS;
2059 /******************************************************************************
2060 * Configures flow control settings after link is established
2062 * hw - Struct containing variables accessed by shared code
2064 * Should be called immediately after a valid link has been established.
2065 * Forces MAC flow control settings if link was forced. When in MII/GMII mode
2066 * and autonegotiation is enabled, the MAC flow control settings will be set
2067 * based on the flow control negotiated by the PHY. In TBI mode, the TFCE
2068 * and RFCE bits will be automaticaly set to the negotiated flow control mode.
2069 *****************************************************************************/
2071 e1000_config_fc_after_link_up(struct e1000_hw *hw)
2074 uint16_t mii_status_reg;
2075 uint16_t mii_nway_adv_reg;
2076 uint16_t mii_nway_lp_ability_reg;
2080 DEBUGFUNC("e1000_config_fc_after_link_up");
2082 /* Check for the case where we have fiber media and auto-neg failed
2083 * so we had to force link. In this case, we need to force the
2084 * configuration of the MAC to match the "fc" parameter.
2086 if(((hw->media_type == e1000_media_type_fiber) && (hw->autoneg_failed)) ||
2087 ((hw->media_type == e1000_media_type_internal_serdes) && (hw->autoneg_failed)) ||
2088 ((hw->media_type == e1000_media_type_copper) && (!hw->autoneg))) {
2089 ret_val = e1000_force_mac_fc(hw);
2091 DEBUGOUT("Error forcing flow control settings\n");
2096 /* Check for the case where we have copper media and auto-neg is
2097 * enabled. In this case, we need to check and see if Auto-Neg
2098 * has completed, and if so, how the PHY and link partner has
2099 * flow control configured.
2101 if((hw->media_type == e1000_media_type_copper) && hw->autoneg) {
2102 /* Read the MII Status Register and check to see if AutoNeg
2103 * has completed. We read this twice because this reg has
2104 * some "sticky" (latched) bits.
2106 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg);
2109 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg);
2113 if(mii_status_reg & MII_SR_AUTONEG_COMPLETE) {
2114 /* The AutoNeg process has completed, so we now need to
2115 * read both the Auto Negotiation Advertisement Register
2116 * (Address 4) and the Auto_Negotiation Base Page Ability
2117 * Register (Address 5) to determine how flow control was
2120 ret_val = e1000_read_phy_reg(hw, PHY_AUTONEG_ADV,
2124 ret_val = e1000_read_phy_reg(hw, PHY_LP_ABILITY,
2125 &mii_nway_lp_ability_reg);
2129 /* Two bits in the Auto Negotiation Advertisement Register
2130 * (Address 4) and two bits in the Auto Negotiation Base
2131 * Page Ability Register (Address 5) determine flow control
2132 * for both the PHY and the link partner. The following
2133 * table, taken out of the IEEE 802.3ab/D6.0 dated March 25,
2134 * 1999, describes these PAUSE resolution bits and how flow
2135 * control is determined based upon these settings.
2136 * NOTE: DC = Don't Care
2138 * LOCAL DEVICE | LINK PARTNER
2139 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | NIC Resolution
2140 *-------|---------|-------|---------|--------------------
2141 * 0 | 0 | DC | DC | e1000_fc_none
2142 * 0 | 1 | 0 | DC | e1000_fc_none
2143 * 0 | 1 | 1 | 0 | e1000_fc_none
2144 * 0 | 1 | 1 | 1 | e1000_fc_tx_pause
2145 * 1 | 0 | 0 | DC | e1000_fc_none
2146 * 1 | DC | 1 | DC | e1000_fc_full
2147 * 1 | 1 | 0 | 0 | e1000_fc_none
2148 * 1 | 1 | 0 | 1 | e1000_fc_rx_pause
2151 /* Are both PAUSE bits set to 1? If so, this implies
2152 * Symmetric Flow Control is enabled at both ends. The
2153 * ASM_DIR bits are irrelevant per the spec.
2155 * For Symmetric Flow Control:
2157 * LOCAL DEVICE | LINK PARTNER
2158 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
2159 *-------|---------|-------|---------|--------------------
2160 * 1 | DC | 1 | DC | e1000_fc_full
2163 if((mii_nway_adv_reg & NWAY_AR_PAUSE) &&
2164 (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE)) {
2165 /* Now we need to check if the user selected RX ONLY
2166 * of pause frames. In this case, we had to advertise
2167 * FULL flow control because we could not advertise RX
2168 * ONLY. Hence, we must now check to see if we need to
2169 * turn OFF the TRANSMISSION of PAUSE frames.
2171 if(hw->original_fc == e1000_fc_full) {
2172 hw->fc = e1000_fc_full;
2173 DEBUGOUT("Flow Control = FULL.\r\n");
2175 hw->fc = e1000_fc_rx_pause;
2176 DEBUGOUT("Flow Control = RX PAUSE frames only.\r\n");
2179 /* For receiving PAUSE frames ONLY.
2181 * LOCAL DEVICE | LINK PARTNER
2182 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
2183 *-------|---------|-------|---------|--------------------
2184 * 0 | 1 | 1 | 1 | e1000_fc_tx_pause
2187 else if(!(mii_nway_adv_reg & NWAY_AR_PAUSE) &&
2188 (mii_nway_adv_reg & NWAY_AR_ASM_DIR) &&
2189 (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) &&
2190 (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR)) {
2191 hw->fc = e1000_fc_tx_pause;
2192 DEBUGOUT("Flow Control = TX PAUSE frames only.\r\n");
2194 /* For transmitting PAUSE frames ONLY.
2196 * LOCAL DEVICE | LINK PARTNER
2197 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
2198 *-------|---------|-------|---------|--------------------
2199 * 1 | 1 | 0 | 1 | e1000_fc_rx_pause
2202 else if((mii_nway_adv_reg & NWAY_AR_PAUSE) &&
2203 (mii_nway_adv_reg & NWAY_AR_ASM_DIR) &&
2204 !(mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) &&
2205 (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR)) {
2206 hw->fc = e1000_fc_rx_pause;
2207 DEBUGOUT("Flow Control = RX PAUSE frames only.\r\n");
2209 /* Per the IEEE spec, at this point flow control should be
2210 * disabled. However, we want to consider that we could
2211 * be connected to a legacy switch that doesn't advertise
2212 * desired flow control, but can be forced on the link
2213 * partner. So if we advertised no flow control, that is
2214 * what we will resolve to. If we advertised some kind of
2215 * receive capability (Rx Pause Only or Full Flow Control)
2216 * and the link partner advertised none, we will configure
2217 * ourselves to enable Rx Flow Control only. We can do
2218 * this safely for two reasons: If the link partner really
2219 * didn't want flow control enabled, and we enable Rx, no
2220 * harm done since we won't be receiving any PAUSE frames
2221 * anyway. If the intent on the link partner was to have
2222 * flow control enabled, then by us enabling RX only, we
2223 * can at least receive pause frames and process them.
2224 * This is a good idea because in most cases, since we are
2225 * predominantly a server NIC, more times than not we will
2226 * be asked to delay transmission of packets than asking
2227 * our link partner to pause transmission of frames.
2229 else if((hw->original_fc == e1000_fc_none ||
2230 hw->original_fc == e1000_fc_tx_pause) ||
2231 hw->fc_strict_ieee) {
2232 hw->fc = e1000_fc_none;
2233 DEBUGOUT("Flow Control = NONE.\r\n");
2235 hw->fc = e1000_fc_rx_pause;
2236 DEBUGOUT("Flow Control = RX PAUSE frames only.\r\n");
2239 /* Now we need to do one last check... If we auto-
2240 * negotiated to HALF DUPLEX, flow control should not be
2241 * enabled per IEEE 802.3 spec.
2243 ret_val = e1000_get_speed_and_duplex(hw, &speed, &duplex);
2245 DEBUGOUT("Error getting link speed and duplex\n");
2249 if(duplex == HALF_DUPLEX)
2250 hw->fc = e1000_fc_none;
2252 /* Now we call a subroutine to actually force the MAC
2253 * controller to use the correct flow control settings.
2255 ret_val = e1000_force_mac_fc(hw);
2257 DEBUGOUT("Error forcing flow control settings\n");
2261 DEBUGOUT("Copper PHY and Auto Neg has not completed.\r\n");
2264 return E1000_SUCCESS;
2267 /******************************************************************************
2268 * Checks to see if the link status of the hardware has changed.
2270 * hw - Struct containing variables accessed by shared code
2272 * Called by any function that needs to check the link status of the adapter.
2273 *****************************************************************************/
2275 e1000_check_for_link(struct e1000_hw *hw)
2282 uint32_t signal = 0;
2286 DEBUGFUNC("e1000_check_for_link");
2288 ctrl = E1000_READ_REG(hw, CTRL);
2289 status = E1000_READ_REG(hw, STATUS);
2291 /* On adapters with a MAC newer than 82544, SW Defineable pin 1 will be
2292 * set when the optics detect a signal. On older adapters, it will be
2293 * cleared when there is a signal. This applies to fiber media only.
2295 if((hw->media_type == e1000_media_type_fiber) ||
2296 (hw->media_type == e1000_media_type_internal_serdes)) {
2297 rxcw = E1000_READ_REG(hw, RXCW);
2299 if(hw->media_type == e1000_media_type_fiber) {
2300 signal = (hw->mac_type > e1000_82544) ? E1000_CTRL_SWDPIN1 : 0;
2301 if(status & E1000_STATUS_LU)
2302 hw->get_link_status = FALSE;
2306 /* If we have a copper PHY then we only want to go out to the PHY
2307 * registers to see if Auto-Neg has completed and/or if our link
2308 * status has changed. The get_link_status flag will be set if we
2309 * receive a Link Status Change interrupt or we have Rx Sequence
2312 if((hw->media_type == e1000_media_type_copper) && hw->get_link_status) {
2313 /* First we want to see if the MII Status Register reports
2314 * link. If so, then we want to get the current speed/duplex
2316 * Read the register twice since the link bit is sticky.
2318 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data);
2321 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data);
2325 if(phy_data & MII_SR_LINK_STATUS) {
2326 hw->get_link_status = FALSE;
2327 /* Check if there was DownShift, must be checked immediately after
2329 e1000_check_downshift(hw);
2331 /* If we are on 82544 or 82543 silicon and speed/duplex
2332 * are forced to 10H or 10F, then we will implement the polarity
2333 * reversal workaround. We disable interrupts first, and upon
2334 * returning, place the devices interrupt state to its previous
2335 * value except for the link status change interrupt which will
2336 * happen due to the execution of this workaround.
2339 if((hw->mac_type == e1000_82544 || hw->mac_type == e1000_82543) &&
2341 (hw->forced_speed_duplex == e1000_10_full ||
2342 hw->forced_speed_duplex == e1000_10_half)) {
2343 E1000_WRITE_REG(hw, IMC, 0xffffffff);
2344 ret_val = e1000_polarity_reversal_workaround(hw);
2345 icr = E1000_READ_REG(hw, ICR);
2346 E1000_WRITE_REG(hw, ICS, (icr & ~E1000_ICS_LSC));
2347 E1000_WRITE_REG(hw, IMS, IMS_ENABLE_MASK);
2351 /* No link detected */
2352 e1000_config_dsp_after_link_change(hw, FALSE);
2356 /* If we are forcing speed/duplex, then we simply return since
2357 * we have already determined whether we have link or not.
2359 if(!hw->autoneg) return -E1000_ERR_CONFIG;
2361 /* optimize the dsp settings for the igp phy */
2362 e1000_config_dsp_after_link_change(hw, TRUE);
2364 /* We have a M88E1000 PHY and Auto-Neg is enabled. If we
2365 * have Si on board that is 82544 or newer, Auto
2366 * Speed Detection takes care of MAC speed/duplex
2367 * configuration. So we only need to configure Collision
2368 * Distance in the MAC. Otherwise, we need to force
2369 * speed/duplex on the MAC to the current PHY speed/duplex
2372 if(hw->mac_type >= e1000_82544)
2373 e1000_config_collision_dist(hw);
2375 ret_val = e1000_config_mac_to_phy(hw);
2377 DEBUGOUT("Error configuring MAC to PHY settings\n");
2382 /* Configure Flow Control now that Auto-Neg has completed. First, we
2383 * need to restore the desired flow control settings because we may
2384 * have had to re-autoneg with a different link partner.
2386 ret_val = e1000_config_fc_after_link_up(hw);
2388 DEBUGOUT("Error configuring flow control\n");
2392 /* At this point we know that we are on copper and we have
2393 * auto-negotiated link. These are conditions for checking the link
2394 * partner capability register. We use the link speed to determine if
2395 * TBI compatibility needs to be turned on or off. If the link is not
2396 * at gigabit speed, then TBI compatibility is not needed. If we are
2397 * at gigabit speed, we turn on TBI compatibility.
2399 if(hw->tbi_compatibility_en) {
2400 uint16_t speed, duplex;
2401 e1000_get_speed_and_duplex(hw, &speed, &duplex);
2402 if(speed != SPEED_1000) {
2403 /* If link speed is not set to gigabit speed, we do not need
2404 * to enable TBI compatibility.
2406 if(hw->tbi_compatibility_on) {
2407 /* If we previously were in the mode, turn it off. */
2408 rctl = E1000_READ_REG(hw, RCTL);
2409 rctl &= ~E1000_RCTL_SBP;
2410 E1000_WRITE_REG(hw, RCTL, rctl);
2411 hw->tbi_compatibility_on = FALSE;
2414 /* If TBI compatibility is was previously off, turn it on. For
2415 * compatibility with a TBI link partner, we will store bad
2416 * packets. Some frames have an additional byte on the end and
2417 * will look like CRC errors to to the hardware.
2419 if(!hw->tbi_compatibility_on) {
2420 hw->tbi_compatibility_on = TRUE;
2421 rctl = E1000_READ_REG(hw, RCTL);
2422 rctl |= E1000_RCTL_SBP;
2423 E1000_WRITE_REG(hw, RCTL, rctl);
2428 /* If we don't have link (auto-negotiation failed or link partner cannot
2429 * auto-negotiate), the cable is plugged in (we have signal), and our
2430 * link partner is not trying to auto-negotiate with us (we are receiving
2431 * idles or data), we need to force link up. We also need to give
2432 * auto-negotiation time to complete, in case the cable was just plugged
2433 * in. The autoneg_failed flag does this.
2435 else if((((hw->media_type == e1000_media_type_fiber) &&
2436 ((ctrl & E1000_CTRL_SWDPIN1) == signal)) ||
2437 (hw->media_type == e1000_media_type_internal_serdes)) &&
2438 (!(status & E1000_STATUS_LU)) &&
2439 (!(rxcw & E1000_RXCW_C))) {
2440 if(hw->autoneg_failed == 0) {
2441 hw->autoneg_failed = 1;
2444 DEBUGOUT("NOT RXing /C/, disable AutoNeg and force link.\r\n");
2446 /* Disable auto-negotiation in the TXCW register */
2447 E1000_WRITE_REG(hw, TXCW, (hw->txcw & ~E1000_TXCW_ANE));
2449 /* Force link-up and also force full-duplex. */
2450 ctrl = E1000_READ_REG(hw, CTRL);
2451 ctrl |= (E1000_CTRL_SLU | E1000_CTRL_FD);
2452 E1000_WRITE_REG(hw, CTRL, ctrl);
2454 /* Configure Flow Control after forcing link up. */
2455 ret_val = e1000_config_fc_after_link_up(hw);
2457 DEBUGOUT("Error configuring flow control\n");
2461 /* If we are forcing link and we are receiving /C/ ordered sets, re-enable
2462 * auto-negotiation in the TXCW register and disable forced link in the
2463 * Device Control register in an attempt to auto-negotiate with our link
2466 else if(((hw->media_type == e1000_media_type_fiber) ||
2467 (hw->media_type == e1000_media_type_internal_serdes)) &&
2468 (ctrl & E1000_CTRL_SLU) && (rxcw & E1000_RXCW_C)) {
2469 DEBUGOUT("RXing /C/, enable AutoNeg and stop forcing link.\r\n");
2470 E1000_WRITE_REG(hw, TXCW, hw->txcw);
2471 E1000_WRITE_REG(hw, CTRL, (ctrl & ~E1000_CTRL_SLU));
2473 hw->serdes_link_down = FALSE;
2475 /* If we force link for non-auto-negotiation switch, check link status
2476 * based on MAC synchronization for internal serdes media type.
2478 else if((hw->media_type == e1000_media_type_internal_serdes) &&
2479 !(E1000_TXCW_ANE & E1000_READ_REG(hw, TXCW))) {
2480 /* SYNCH bit and IV bit are sticky. */
2482 if(E1000_RXCW_SYNCH & E1000_READ_REG(hw, RXCW)) {
2483 if(!(rxcw & E1000_RXCW_IV)) {
2484 hw->serdes_link_down = FALSE;
2485 DEBUGOUT("SERDES: Link is up.\n");
2488 hw->serdes_link_down = TRUE;
2489 DEBUGOUT("SERDES: Link is down.\n");
2492 if((hw->media_type == e1000_media_type_internal_serdes) &&
2493 (E1000_TXCW_ANE & E1000_READ_REG(hw, TXCW))) {
2494 hw->serdes_link_down = !(E1000_STATUS_LU & E1000_READ_REG(hw, STATUS));
2496 return E1000_SUCCESS;
2499 /******************************************************************************
2500 * Detects the current speed and duplex settings of the hardware.
2502 * hw - Struct containing variables accessed by shared code
2503 * speed - Speed of the connection
2504 * duplex - Duplex setting of the connection
2505 *****************************************************************************/
2507 e1000_get_speed_and_duplex(struct e1000_hw *hw,
2515 DEBUGFUNC("e1000_get_speed_and_duplex");
2517 if(hw->mac_type >= e1000_82543) {
2518 status = E1000_READ_REG(hw, STATUS);
2519 if(status & E1000_STATUS_SPEED_1000) {
2520 *speed = SPEED_1000;
2521 DEBUGOUT("1000 Mbs, ");
2522 } else if(status & E1000_STATUS_SPEED_100) {
2524 DEBUGOUT("100 Mbs, ");
2527 DEBUGOUT("10 Mbs, ");
2530 if(status & E1000_STATUS_FD) {
2531 *duplex = FULL_DUPLEX;
2532 DEBUGOUT("Full Duplex\r\n");
2534 *duplex = HALF_DUPLEX;
2535 DEBUGOUT(" Half Duplex\r\n");
2538 DEBUGOUT("1000 Mbs, Full Duplex\r\n");
2539 *speed = SPEED_1000;
2540 *duplex = FULL_DUPLEX;
2543 /* IGP01 PHY may advertise full duplex operation after speed downgrade even
2544 * if it is operating at half duplex. Here we set the duplex settings to
2545 * match the duplex in the link partner's capabilities.
2547 if(hw->phy_type == e1000_phy_igp && hw->speed_downgraded) {
2548 ret_val = e1000_read_phy_reg(hw, PHY_AUTONEG_EXP, &phy_data);
2552 if(!(phy_data & NWAY_ER_LP_NWAY_CAPS))
2553 *duplex = HALF_DUPLEX;
2555 ret_val = e1000_read_phy_reg(hw, PHY_LP_ABILITY, &phy_data);
2558 if((*speed == SPEED_100 && !(phy_data & NWAY_LPAR_100TX_FD_CAPS)) ||
2559 (*speed == SPEED_10 && !(phy_data & NWAY_LPAR_10T_FD_CAPS)))
2560 *duplex = HALF_DUPLEX;
2564 return E1000_SUCCESS;
2567 /******************************************************************************
2568 * Blocks until autoneg completes or times out (~4.5 seconds)
2570 * hw - Struct containing variables accessed by shared code
2571 ******************************************************************************/
2573 e1000_wait_autoneg(struct e1000_hw *hw)
2579 DEBUGFUNC("e1000_wait_autoneg");
2580 DEBUGOUT("Waiting for Auto-Neg to complete.\n");
2582 /* We will wait for autoneg to complete or 4.5 seconds to expire. */
2583 for(i = PHY_AUTO_NEG_TIME; i > 0; i--) {
2584 /* Read the MII Status Register and wait for Auto-Neg
2585 * Complete bit to be set.
2587 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data);
2590 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data);
2593 if(phy_data & MII_SR_AUTONEG_COMPLETE) {
2594 return E1000_SUCCESS;
2598 return E1000_SUCCESS;
2601 /******************************************************************************
2602 * Raises the Management Data Clock
2604 * hw - Struct containing variables accessed by shared code
2605 * ctrl - Device control register's current value
2606 ******************************************************************************/
2608 e1000_raise_mdi_clk(struct e1000_hw *hw,
2611 /* Raise the clock input to the Management Data Clock (by setting the MDC
2612 * bit), and then delay 10 microseconds.
2614 E1000_WRITE_REG(hw, CTRL, (*ctrl | E1000_CTRL_MDC));
2615 E1000_WRITE_FLUSH(hw);
2619 /******************************************************************************
2620 * Lowers the Management Data Clock
2622 * hw - Struct containing variables accessed by shared code
2623 * ctrl - Device control register's current value
2624 ******************************************************************************/
2626 e1000_lower_mdi_clk(struct e1000_hw *hw,
2629 /* Lower the clock input to the Management Data Clock (by clearing the MDC
2630 * bit), and then delay 10 microseconds.
2632 E1000_WRITE_REG(hw, CTRL, (*ctrl & ~E1000_CTRL_MDC));
2633 E1000_WRITE_FLUSH(hw);
2637 /******************************************************************************
2638 * Shifts data bits out to the PHY
2640 * hw - Struct containing variables accessed by shared code
2641 * data - Data to send out to the PHY
2642 * count - Number of bits to shift out
2644 * Bits are shifted out in MSB to LSB order.
2645 ******************************************************************************/
2647 e1000_shift_out_mdi_bits(struct e1000_hw *hw,
2654 /* We need to shift "count" number of bits out to the PHY. So, the value
2655 * in the "data" parameter will be shifted out to the PHY one bit at a
2656 * time. In order to do this, "data" must be broken down into bits.
2659 mask <<= (count - 1);
2661 ctrl = E1000_READ_REG(hw, CTRL);
2663 /* Set MDIO_DIR and MDC_DIR direction bits to be used as output pins. */
2664 ctrl |= (E1000_CTRL_MDIO_DIR | E1000_CTRL_MDC_DIR);
2667 /* A "1" is shifted out to the PHY by setting the MDIO bit to "1" and
2668 * then raising and lowering the Management Data Clock. A "0" is
2669 * shifted out to the PHY by setting the MDIO bit to "0" and then
2670 * raising and lowering the clock.
2672 if(data & mask) ctrl |= E1000_CTRL_MDIO;
2673 else ctrl &= ~E1000_CTRL_MDIO;
2675 E1000_WRITE_REG(hw, CTRL, ctrl);
2676 E1000_WRITE_FLUSH(hw);
2680 e1000_raise_mdi_clk(hw, &ctrl);
2681 e1000_lower_mdi_clk(hw, &ctrl);
2687 /******************************************************************************
2688 * Shifts data bits in from the PHY
2690 * hw - Struct containing variables accessed by shared code
2692 * Bits are shifted in in MSB to LSB order.
2693 ******************************************************************************/
2695 e1000_shift_in_mdi_bits(struct e1000_hw *hw)
2701 /* In order to read a register from the PHY, we need to shift in a total
2702 * of 18 bits from the PHY. The first two bit (turnaround) times are used
2703 * to avoid contention on the MDIO pin when a read operation is performed.
2704 * These two bits are ignored by us and thrown away. Bits are "shifted in"
2705 * by raising the input to the Management Data Clock (setting the MDC bit),
2706 * and then reading the value of the MDIO bit.
2708 ctrl = E1000_READ_REG(hw, CTRL);
2710 /* Clear MDIO_DIR (SWDPIO1) to indicate this bit is to be used as input. */
2711 ctrl &= ~E1000_CTRL_MDIO_DIR;
2712 ctrl &= ~E1000_CTRL_MDIO;
2714 E1000_WRITE_REG(hw, CTRL, ctrl);
2715 E1000_WRITE_FLUSH(hw);
2717 /* Raise and Lower the clock before reading in the data. This accounts for
2718 * the turnaround bits. The first clock occurred when we clocked out the
2719 * last bit of the Register Address.
2721 e1000_raise_mdi_clk(hw, &ctrl);
2722 e1000_lower_mdi_clk(hw, &ctrl);
2724 for(data = 0, i = 0; i < 16; i++) {
2726 e1000_raise_mdi_clk(hw, &ctrl);
2727 ctrl = E1000_READ_REG(hw, CTRL);
2728 /* Check to see if we shifted in a "1". */
2729 if(ctrl & E1000_CTRL_MDIO) data |= 1;
2730 e1000_lower_mdi_clk(hw, &ctrl);
2733 e1000_raise_mdi_clk(hw, &ctrl);
2734 e1000_lower_mdi_clk(hw, &ctrl);
2739 /*****************************************************************************
2740 * Reads the value from a PHY register, if the value is on a specific non zero
2741 * page, sets the page first.
2742 * hw - Struct containing variables accessed by shared code
2743 * reg_addr - address of the PHY register to read
2744 ******************************************************************************/
2746 e1000_read_phy_reg(struct e1000_hw *hw,
2752 DEBUGFUNC("e1000_read_phy_reg");
2754 if((hw->phy_type == e1000_phy_igp ||
2755 hw->phy_type == e1000_phy_igp_2) &&
2756 (reg_addr > MAX_PHY_MULTI_PAGE_REG)) {
2757 ret_val = e1000_write_phy_reg_ex(hw, IGP01E1000_PHY_PAGE_SELECT,
2758 (uint16_t)reg_addr);
2764 ret_val = e1000_read_phy_reg_ex(hw, MAX_PHY_REG_ADDRESS & reg_addr,
2771 e1000_read_phy_reg_ex(struct e1000_hw *hw,
2777 const uint32_t phy_addr = 1;
2779 DEBUGFUNC("e1000_read_phy_reg_ex");
2781 if(reg_addr > MAX_PHY_REG_ADDRESS) {
2782 DEBUGOUT1("PHY Address %d is out of range\n", reg_addr);
2783 return -E1000_ERR_PARAM;
2786 if(hw->mac_type > e1000_82543) {
2787 /* Set up Op-code, Phy Address, and register address in the MDI
2788 * Control register. The MAC will take care of interfacing with the
2789 * PHY to retrieve the desired data.
2791 mdic = ((reg_addr << E1000_MDIC_REG_SHIFT) |
2792 (phy_addr << E1000_MDIC_PHY_SHIFT) |
2793 (E1000_MDIC_OP_READ));
2795 E1000_WRITE_REG(hw, MDIC, mdic);
2797 /* Poll the ready bit to see if the MDI read completed */
2798 for(i = 0; i < 64; i++) {
2800 mdic = E1000_READ_REG(hw, MDIC);
2801 if(mdic & E1000_MDIC_READY) break;
2803 if(!(mdic & E1000_MDIC_READY)) {
2804 DEBUGOUT("MDI Read did not complete\n");
2805 return -E1000_ERR_PHY;
2807 if(mdic & E1000_MDIC_ERROR) {
2808 DEBUGOUT("MDI Error\n");
2809 return -E1000_ERR_PHY;
2811 *phy_data = (uint16_t) mdic;
2813 /* We must first send a preamble through the MDIO pin to signal the
2814 * beginning of an MII instruction. This is done by sending 32
2815 * consecutive "1" bits.
2817 e1000_shift_out_mdi_bits(hw, PHY_PREAMBLE, PHY_PREAMBLE_SIZE);
2819 /* Now combine the next few fields that are required for a read
2820 * operation. We use this method instead of calling the
2821 * e1000_shift_out_mdi_bits routine five different times. The format of
2822 * a MII read instruction consists of a shift out of 14 bits and is
2823 * defined as follows:
2824 * <Preamble><SOF><Op Code><Phy Addr><Reg Addr>
2825 * followed by a shift in of 18 bits. This first two bits shifted in
2826 * are TurnAround bits used to avoid contention on the MDIO pin when a
2827 * READ operation is performed. These two bits are thrown away
2828 * followed by a shift in of 16 bits which contains the desired data.
2830 mdic = ((reg_addr) | (phy_addr << 5) |
2831 (PHY_OP_READ << 10) | (PHY_SOF << 12));
2833 e1000_shift_out_mdi_bits(hw, mdic, 14);
2835 /* Now that we've shifted out the read command to the MII, we need to
2836 * "shift in" the 16-bit value (18 total bits) of the requested PHY
2839 *phy_data = e1000_shift_in_mdi_bits(hw);
2841 return E1000_SUCCESS;
2844 /******************************************************************************
2845 * Writes a value to a PHY register
2847 * hw - Struct containing variables accessed by shared code
2848 * reg_addr - address of the PHY register to write
2849 * data - data to write to the PHY
2850 ******************************************************************************/
2852 e1000_write_phy_reg(struct e1000_hw *hw,
2858 DEBUGFUNC("e1000_write_phy_reg");
2860 if((hw->phy_type == e1000_phy_igp ||
2861 hw->phy_type == e1000_phy_igp_2) &&
2862 (reg_addr > MAX_PHY_MULTI_PAGE_REG)) {
2863 ret_val = e1000_write_phy_reg_ex(hw, IGP01E1000_PHY_PAGE_SELECT,
2864 (uint16_t)reg_addr);
2870 ret_val = e1000_write_phy_reg_ex(hw, MAX_PHY_REG_ADDRESS & reg_addr,
2877 e1000_write_phy_reg_ex(struct e1000_hw *hw,
2883 const uint32_t phy_addr = 1;
2885 DEBUGFUNC("e1000_write_phy_reg_ex");
2887 if(reg_addr > MAX_PHY_REG_ADDRESS) {
2888 DEBUGOUT1("PHY Address %d is out of range\n", reg_addr);
2889 return -E1000_ERR_PARAM;
2892 if(hw->mac_type > e1000_82543) {
2893 /* Set up Op-code, Phy Address, register address, and data intended
2894 * for the PHY register in the MDI Control register. The MAC will take
2895 * care of interfacing with the PHY to send the desired data.
2897 mdic = (((uint32_t) phy_data) |
2898 (reg_addr << E1000_MDIC_REG_SHIFT) |
2899 (phy_addr << E1000_MDIC_PHY_SHIFT) |
2900 (E1000_MDIC_OP_WRITE));
2902 E1000_WRITE_REG(hw, MDIC, mdic);
2904 /* Poll the ready bit to see if the MDI read completed */
2905 for(i = 0; i < 640; i++) {
2907 mdic = E1000_READ_REG(hw, MDIC);
2908 if(mdic & E1000_MDIC_READY) break;
2910 if(!(mdic & E1000_MDIC_READY)) {
2911 DEBUGOUT("MDI Write did not complete\n");
2912 return -E1000_ERR_PHY;
2915 /* We'll need to use the SW defined pins to shift the write command
2916 * out to the PHY. We first send a preamble to the PHY to signal the
2917 * beginning of the MII instruction. This is done by sending 32
2918 * consecutive "1" bits.
2920 e1000_shift_out_mdi_bits(hw, PHY_PREAMBLE, PHY_PREAMBLE_SIZE);
2922 /* Now combine the remaining required fields that will indicate a
2923 * write operation. We use this method instead of calling the
2924 * e1000_shift_out_mdi_bits routine for each field in the command. The
2925 * format of a MII write instruction is as follows:
2926 * <Preamble><SOF><Op Code><Phy Addr><Reg Addr><Turnaround><Data>.
2928 mdic = ((PHY_TURNAROUND) | (reg_addr << 2) | (phy_addr << 7) |
2929 (PHY_OP_WRITE << 12) | (PHY_SOF << 14));
2931 mdic |= (uint32_t) phy_data;
2933 e1000_shift_out_mdi_bits(hw, mdic, 32);
2936 return E1000_SUCCESS;
2940 /******************************************************************************
2941 * Returns the PHY to the power-on reset state
2943 * hw - Struct containing variables accessed by shared code
2944 ******************************************************************************/
2946 e1000_phy_hw_reset(struct e1000_hw *hw)
2948 uint32_t ctrl, ctrl_ext;
2952 DEBUGFUNC("e1000_phy_hw_reset");
2954 /* In the case of the phy reset being blocked, it's not an error, we
2955 * simply return success without performing the reset. */
2956 ret_val = e1000_check_phy_reset_block(hw);
2958 return E1000_SUCCESS;
2960 DEBUGOUT("Resetting Phy...\n");
2962 if(hw->mac_type > e1000_82543) {
2963 /* Read the device control register and assert the E1000_CTRL_PHY_RST
2964 * bit. Then, take it out of reset.
2966 ctrl = E1000_READ_REG(hw, CTRL);
2967 E1000_WRITE_REG(hw, CTRL, ctrl | E1000_CTRL_PHY_RST);
2968 E1000_WRITE_FLUSH(hw);
2970 E1000_WRITE_REG(hw, CTRL, ctrl);
2971 E1000_WRITE_FLUSH(hw);
2973 /* Read the Extended Device Control Register, assert the PHY_RESET_DIR
2974 * bit to put the PHY into reset. Then, take it out of reset.
2976 ctrl_ext = E1000_READ_REG(hw, CTRL_EXT);
2977 ctrl_ext |= E1000_CTRL_EXT_SDP4_DIR;
2978 ctrl_ext &= ~E1000_CTRL_EXT_SDP4_DATA;
2979 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext);
2980 E1000_WRITE_FLUSH(hw);
2982 ctrl_ext |= E1000_CTRL_EXT_SDP4_DATA;
2983 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext);
2984 E1000_WRITE_FLUSH(hw);
2988 if((hw->mac_type == e1000_82541) || (hw->mac_type == e1000_82547)) {
2989 /* Configure activity LED after PHY reset */
2990 led_ctrl = E1000_READ_REG(hw, LEDCTL);
2991 led_ctrl &= IGP_ACTIVITY_LED_MASK;
2992 led_ctrl |= (IGP_ACTIVITY_LED_ENABLE | IGP_LED3_MODE);
2993 E1000_WRITE_REG(hw, LEDCTL, led_ctrl);
2996 /* Wait for FW to finish PHY configuration. */
2997 ret_val = e1000_get_phy_cfg_done(hw);
3002 /******************************************************************************
3005 * hw - Struct containing variables accessed by shared code
3007 * Sets bit 15 of the MII Control regiser
3008 ******************************************************************************/
3010 e1000_phy_reset(struct e1000_hw *hw)
3015 DEBUGFUNC("e1000_phy_reset");
3017 /* In the case of the phy reset being blocked, it's not an error, we
3018 * simply return success without performing the reset. */
3019 ret_val = e1000_check_phy_reset_block(hw);
3021 return E1000_SUCCESS;
3023 switch (hw->mac_type) {
3024 case e1000_82541_rev_2:
3027 ret_val = e1000_phy_hw_reset(hw);
3032 ret_val = e1000_read_phy_reg(hw, PHY_CTRL, &phy_data);
3036 phy_data |= MII_CR_RESET;
3037 ret_val = e1000_write_phy_reg(hw, PHY_CTRL, phy_data);
3045 if(hw->phy_type == e1000_phy_igp || hw->phy_type == e1000_phy_igp_2)
3046 e1000_phy_init_script(hw);
3048 return E1000_SUCCESS;
3051 /******************************************************************************
3052 * Probes the expected PHY address for known PHY IDs
3054 * hw - Struct containing variables accessed by shared code
3055 ******************************************************************************/
3057 e1000_detect_gig_phy(struct e1000_hw *hw)
3059 int32_t phy_init_status, ret_val;
3060 uint16_t phy_id_high, phy_id_low;
3061 boolean_t match = FALSE;
3063 DEBUGFUNC("e1000_detect_gig_phy");
3065 /* The 82571 firmware may still be configuring the PHY. In this
3066 * case, we cannot access the PHY until the configuration is done. So
3067 * we explicitly set the PHY values. */
3068 if(hw->mac_type == e1000_82571 ||
3069 hw->mac_type == e1000_82572) {
3070 hw->phy_id = IGP01E1000_I_PHY_ID;
3071 hw->phy_type = e1000_phy_igp_2;
3072 return E1000_SUCCESS;
3075 /* Read the PHY ID Registers to identify which PHY is onboard. */
3076 ret_val = e1000_read_phy_reg(hw, PHY_ID1, &phy_id_high);
3080 hw->phy_id = (uint32_t) (phy_id_high << 16);
3082 ret_val = e1000_read_phy_reg(hw, PHY_ID2, &phy_id_low);
3086 hw->phy_id |= (uint32_t) (phy_id_low & PHY_REVISION_MASK);
3087 hw->phy_revision = (uint32_t) phy_id_low & ~PHY_REVISION_MASK;
3089 switch(hw->mac_type) {
3091 if(hw->phy_id == M88E1000_E_PHY_ID) match = TRUE;
3094 if(hw->phy_id == M88E1000_I_PHY_ID) match = TRUE;
3098 case e1000_82545_rev_3:
3100 case e1000_82546_rev_3:
3101 if(hw->phy_id == M88E1011_I_PHY_ID) match = TRUE;
3104 case e1000_82541_rev_2:
3106 case e1000_82547_rev_2:
3107 if(hw->phy_id == IGP01E1000_I_PHY_ID) match = TRUE;
3110 if(hw->phy_id == M88E1111_I_PHY_ID) match = TRUE;
3113 DEBUGOUT1("Invalid MAC type %d\n", hw->mac_type);
3114 return -E1000_ERR_CONFIG;
3116 phy_init_status = e1000_set_phy_type(hw);
3118 if ((match) && (phy_init_status == E1000_SUCCESS)) {
3119 DEBUGOUT1("PHY ID 0x%X detected\n", hw->phy_id);
3120 return E1000_SUCCESS;
3122 DEBUGOUT1("Invalid PHY ID 0x%X\n", hw->phy_id);
3123 return -E1000_ERR_PHY;
3126 /******************************************************************************
3127 * Resets the PHY's DSP
3129 * hw - Struct containing variables accessed by shared code
3130 ******************************************************************************/
3132 e1000_phy_reset_dsp(struct e1000_hw *hw)
3135 DEBUGFUNC("e1000_phy_reset_dsp");
3138 ret_val = e1000_write_phy_reg(hw, 29, 0x001d);
3140 ret_val = e1000_write_phy_reg(hw, 30, 0x00c1);
3142 ret_val = e1000_write_phy_reg(hw, 30, 0x0000);
3144 ret_val = E1000_SUCCESS;
3150 /******************************************************************************
3151 * Get PHY information from various PHY registers for igp PHY only.
3153 * hw - Struct containing variables accessed by shared code
3154 * phy_info - PHY information structure
3155 ******************************************************************************/
3157 e1000_phy_igp_get_info(struct e1000_hw *hw,
3158 struct e1000_phy_info *phy_info)
3161 uint16_t phy_data, polarity, min_length, max_length, average;
3163 DEBUGFUNC("e1000_phy_igp_get_info");
3165 /* The downshift status is checked only once, after link is established,
3166 * and it stored in the hw->speed_downgraded parameter. */
3167 phy_info->downshift = (e1000_downshift)hw->speed_downgraded;
3169 /* IGP01E1000 does not need to support it. */
3170 phy_info->extended_10bt_distance = e1000_10bt_ext_dist_enable_normal;
3172 /* IGP01E1000 always correct polarity reversal */
3173 phy_info->polarity_correction = e1000_polarity_reversal_enabled;
3175 /* Check polarity status */
3176 ret_val = e1000_check_polarity(hw, &polarity);
3180 phy_info->cable_polarity = polarity;
3182 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_STATUS, &phy_data);
3186 phy_info->mdix_mode = (phy_data & IGP01E1000_PSSR_MDIX) >>
3187 IGP01E1000_PSSR_MDIX_SHIFT;
3189 if((phy_data & IGP01E1000_PSSR_SPEED_MASK) ==
3190 IGP01E1000_PSSR_SPEED_1000MBPS) {
3191 /* Local/Remote Receiver Information are only valid at 1000 Mbps */
3192 ret_val = e1000_read_phy_reg(hw, PHY_1000T_STATUS, &phy_data);
3196 phy_info->local_rx = (phy_data & SR_1000T_LOCAL_RX_STATUS) >>
3197 SR_1000T_LOCAL_RX_STATUS_SHIFT;
3198 phy_info->remote_rx = (phy_data & SR_1000T_REMOTE_RX_STATUS) >>
3199 SR_1000T_REMOTE_RX_STATUS_SHIFT;
3201 /* Get cable length */
3202 ret_val = e1000_get_cable_length(hw, &min_length, &max_length);
3206 /* Translate to old method */
3207 average = (max_length + min_length) / 2;
3209 if(average <= e1000_igp_cable_length_50)
3210 phy_info->cable_length = e1000_cable_length_50;
3211 else if(average <= e1000_igp_cable_length_80)
3212 phy_info->cable_length = e1000_cable_length_50_80;
3213 else if(average <= e1000_igp_cable_length_110)
3214 phy_info->cable_length = e1000_cable_length_80_110;
3215 else if(average <= e1000_igp_cable_length_140)
3216 phy_info->cable_length = e1000_cable_length_110_140;
3218 phy_info->cable_length = e1000_cable_length_140;
3221 return E1000_SUCCESS;
3224 /******************************************************************************
3225 * Get PHY information from various PHY registers fot m88 PHY only.
3227 * hw - Struct containing variables accessed by shared code
3228 * phy_info - PHY information structure
3229 ******************************************************************************/
3231 e1000_phy_m88_get_info(struct e1000_hw *hw,
3232 struct e1000_phy_info *phy_info)
3235 uint16_t phy_data, polarity;
3237 DEBUGFUNC("e1000_phy_m88_get_info");
3239 /* The downshift status is checked only once, after link is established,
3240 * and it stored in the hw->speed_downgraded parameter. */
3241 phy_info->downshift = (e1000_downshift)hw->speed_downgraded;
3243 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
3247 phy_info->extended_10bt_distance =
3248 (phy_data & M88E1000_PSCR_10BT_EXT_DIST_ENABLE) >>
3249 M88E1000_PSCR_10BT_EXT_DIST_ENABLE_SHIFT;
3250 phy_info->polarity_correction =
3251 (phy_data & M88E1000_PSCR_POLARITY_REVERSAL) >>
3252 M88E1000_PSCR_POLARITY_REVERSAL_SHIFT;
3254 /* Check polarity status */
3255 ret_val = e1000_check_polarity(hw, &polarity);
3258 phy_info->cable_polarity = polarity;
3260 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS, &phy_data);
3264 phy_info->mdix_mode = (phy_data & M88E1000_PSSR_MDIX) >>
3265 M88E1000_PSSR_MDIX_SHIFT;
3267 if ((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_1000MBS) {
3268 /* Cable Length Estimation and Local/Remote Receiver Information
3269 * are only valid at 1000 Mbps.
3271 phy_info->cable_length = ((phy_data & M88E1000_PSSR_CABLE_LENGTH) >>
3272 M88E1000_PSSR_CABLE_LENGTH_SHIFT);
3274 ret_val = e1000_read_phy_reg(hw, PHY_1000T_STATUS, &phy_data);
3278 phy_info->local_rx = (phy_data & SR_1000T_LOCAL_RX_STATUS) >>
3279 SR_1000T_LOCAL_RX_STATUS_SHIFT;
3281 phy_info->remote_rx = (phy_data & SR_1000T_REMOTE_RX_STATUS) >>
3282 SR_1000T_REMOTE_RX_STATUS_SHIFT;
3285 return E1000_SUCCESS;
3288 /******************************************************************************
3289 * Get PHY information from various PHY registers
3291 * hw - Struct containing variables accessed by shared code
3292 * phy_info - PHY information structure
3293 ******************************************************************************/
3295 e1000_phy_get_info(struct e1000_hw *hw,
3296 struct e1000_phy_info *phy_info)
3301 DEBUGFUNC("e1000_phy_get_info");
3303 phy_info->cable_length = e1000_cable_length_undefined;
3304 phy_info->extended_10bt_distance = e1000_10bt_ext_dist_enable_undefined;
3305 phy_info->cable_polarity = e1000_rev_polarity_undefined;
3306 phy_info->downshift = e1000_downshift_undefined;
3307 phy_info->polarity_correction = e1000_polarity_reversal_undefined;
3308 phy_info->mdix_mode = e1000_auto_x_mode_undefined;
3309 phy_info->local_rx = e1000_1000t_rx_status_undefined;
3310 phy_info->remote_rx = e1000_1000t_rx_status_undefined;
3312 if(hw->media_type != e1000_media_type_copper) {
3313 DEBUGOUT("PHY info is only valid for copper media\n");
3314 return -E1000_ERR_CONFIG;
3317 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data);
3321 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data);
3325 if((phy_data & MII_SR_LINK_STATUS) != MII_SR_LINK_STATUS) {
3326 DEBUGOUT("PHY info is only valid if link is up\n");
3327 return -E1000_ERR_CONFIG;
3330 if(hw->phy_type == e1000_phy_igp ||
3331 hw->phy_type == e1000_phy_igp_2)
3332 return e1000_phy_igp_get_info(hw, phy_info);
3334 return e1000_phy_m88_get_info(hw, phy_info);
3338 e1000_validate_mdi_setting(struct e1000_hw *hw)
3340 DEBUGFUNC("e1000_validate_mdi_settings");
3342 if(!hw->autoneg && (hw->mdix == 0 || hw->mdix == 3)) {
3343 DEBUGOUT("Invalid MDI setting detected\n");
3345 return -E1000_ERR_CONFIG;
3347 return E1000_SUCCESS;
3351 /******************************************************************************
3352 * Sets up eeprom variables in the hw struct. Must be called after mac_type
3355 * hw - Struct containing variables accessed by shared code
3356 *****************************************************************************/
3358 e1000_init_eeprom_params(struct e1000_hw *hw)
3360 struct e1000_eeprom_info *eeprom = &hw->eeprom;
3361 uint32_t eecd = E1000_READ_REG(hw, EECD);
3362 int32_t ret_val = E1000_SUCCESS;
3363 uint16_t eeprom_size;
3365 DEBUGFUNC("e1000_init_eeprom_params");
3367 switch (hw->mac_type) {
3368 case e1000_82542_rev2_0:
3369 case e1000_82542_rev2_1:
3372 eeprom->type = e1000_eeprom_microwire;
3373 eeprom->word_size = 64;
3374 eeprom->opcode_bits = 3;
3375 eeprom->address_bits = 6;
3376 eeprom->delay_usec = 50;
3377 eeprom->use_eerd = FALSE;
3378 eeprom->use_eewr = FALSE;
3382 case e1000_82545_rev_3:
3384 case e1000_82546_rev_3:
3385 eeprom->type = e1000_eeprom_microwire;
3386 eeprom->opcode_bits = 3;
3387 eeprom->delay_usec = 50;
3388 if(eecd & E1000_EECD_SIZE) {
3389 eeprom->word_size = 256;
3390 eeprom->address_bits = 8;
3392 eeprom->word_size = 64;
3393 eeprom->address_bits = 6;
3395 eeprom->use_eerd = FALSE;
3396 eeprom->use_eewr = FALSE;
3399 case e1000_82541_rev_2:
3401 case e1000_82547_rev_2:
3402 if (eecd & E1000_EECD_TYPE) {
3403 eeprom->type = e1000_eeprom_spi;
3404 eeprom->opcode_bits = 8;
3405 eeprom->delay_usec = 1;
3406 if (eecd & E1000_EECD_ADDR_BITS) {
3407 eeprom->page_size = 32;
3408 eeprom->address_bits = 16;
3410 eeprom->page_size = 8;
3411 eeprom->address_bits = 8;
3414 eeprom->type = e1000_eeprom_microwire;
3415 eeprom->opcode_bits = 3;
3416 eeprom->delay_usec = 50;
3417 if (eecd & E1000_EECD_ADDR_BITS) {
3418 eeprom->word_size = 256;
3419 eeprom->address_bits = 8;
3421 eeprom->word_size = 64;
3422 eeprom->address_bits = 6;
3425 eeprom->use_eerd = FALSE;
3426 eeprom->use_eewr = FALSE;
3430 eeprom->type = e1000_eeprom_spi;
3431 eeprom->opcode_bits = 8;
3432 eeprom->delay_usec = 1;
3433 if (eecd & E1000_EECD_ADDR_BITS) {
3434 eeprom->page_size = 32;
3435 eeprom->address_bits = 16;
3437 eeprom->page_size = 8;
3438 eeprom->address_bits = 8;
3440 eeprom->use_eerd = FALSE;
3441 eeprom->use_eewr = FALSE;
3444 eeprom->type = e1000_eeprom_spi;
3445 eeprom->opcode_bits = 8;
3446 eeprom->delay_usec = 1;
3447 if (eecd & E1000_EECD_ADDR_BITS) {
3448 eeprom->page_size = 32;
3449 eeprom->address_bits = 16;
3451 eeprom->page_size = 8;
3452 eeprom->address_bits = 8;
3454 eeprom->use_eerd = TRUE;
3455 eeprom->use_eewr = TRUE;
3456 if(e1000_is_onboard_nvm_eeprom(hw) == FALSE) {
3457 eeprom->type = e1000_eeprom_flash;
3458 eeprom->word_size = 2048;
3460 /* Ensure that the Autonomous FLASH update bit is cleared due to
3461 * Flash update issue on parts which use a FLASH for NVM. */
3462 eecd &= ~E1000_EECD_AUPDEN;
3463 E1000_WRITE_REG(hw, EECD, eecd);
3470 if (eeprom->type == e1000_eeprom_spi) {
3471 /* eeprom_size will be an enum [0..8] that maps to eeprom sizes 128B to
3472 * 32KB (incremented by powers of 2).
3474 if(hw->mac_type <= e1000_82547_rev_2) {
3475 /* Set to default value for initial eeprom read. */
3476 eeprom->word_size = 64;
3477 ret_val = e1000_read_eeprom(hw, EEPROM_CFG, 1, &eeprom_size);
3480 eeprom_size = (eeprom_size & EEPROM_SIZE_MASK) >> EEPROM_SIZE_SHIFT;
3481 /* 256B eeprom size was not supported in earlier hardware, so we
3482 * bump eeprom_size up one to ensure that "1" (which maps to 256B)
3483 * is never the result used in the shifting logic below. */
3487 eeprom_size = (uint16_t)((eecd & E1000_EECD_SIZE_EX_MASK) >>
3488 E1000_EECD_SIZE_EX_SHIFT);
3491 eeprom->word_size = 1 << (eeprom_size + EEPROM_WORD_SIZE_SHIFT);
3496 /******************************************************************************
3497 * Raises the EEPROM's clock input.
3499 * hw - Struct containing variables accessed by shared code
3500 * eecd - EECD's current value
3501 *****************************************************************************/
3503 e1000_raise_ee_clk(struct e1000_hw *hw,
3506 /* Raise the clock input to the EEPROM (by setting the SK bit), and then
3507 * wait <delay> microseconds.
3509 *eecd = *eecd | E1000_EECD_SK;
3510 E1000_WRITE_REG(hw, EECD, *eecd);
3511 E1000_WRITE_FLUSH(hw);
3512 udelay(hw->eeprom.delay_usec);
3515 /******************************************************************************
3516 * Lowers the EEPROM's clock input.
3518 * hw - Struct containing variables accessed by shared code
3519 * eecd - EECD's current value
3520 *****************************************************************************/
3522 e1000_lower_ee_clk(struct e1000_hw *hw,
3525 /* Lower the clock input to the EEPROM (by clearing the SK bit), and then
3526 * wait 50 microseconds.
3528 *eecd = *eecd & ~E1000_EECD_SK;
3529 E1000_WRITE_REG(hw, EECD, *eecd);
3530 E1000_WRITE_FLUSH(hw);
3531 udelay(hw->eeprom.delay_usec);
3534 /******************************************************************************
3535 * Shift data bits out to the EEPROM.
3537 * hw - Struct containing variables accessed by shared code
3538 * data - data to send to the EEPROM
3539 * count - number of bits to shift out
3540 *****************************************************************************/
3542 e1000_shift_out_ee_bits(struct e1000_hw *hw,
3546 struct e1000_eeprom_info *eeprom = &hw->eeprom;
3550 /* We need to shift "count" bits out to the EEPROM. So, value in the
3551 * "data" parameter will be shifted out to the EEPROM one bit at a time.
3552 * In order to do this, "data" must be broken down into bits.
3554 mask = 0x01 << (count - 1);
3555 eecd = E1000_READ_REG(hw, EECD);
3556 if (eeprom->type == e1000_eeprom_microwire) {
3557 eecd &= ~E1000_EECD_DO;
3558 } else if (eeprom->type == e1000_eeprom_spi) {
3559 eecd |= E1000_EECD_DO;
3562 /* A "1" is shifted out to the EEPROM by setting bit "DI" to a "1",
3563 * and then raising and then lowering the clock (the SK bit controls
3564 * the clock input to the EEPROM). A "0" is shifted out to the EEPROM
3565 * by setting "DI" to "0" and then raising and then lowering the clock.
3567 eecd &= ~E1000_EECD_DI;
3570 eecd |= E1000_EECD_DI;
3572 E1000_WRITE_REG(hw, EECD, eecd);
3573 E1000_WRITE_FLUSH(hw);
3575 udelay(eeprom->delay_usec);
3577 e1000_raise_ee_clk(hw, &eecd);
3578 e1000_lower_ee_clk(hw, &eecd);
3584 /* We leave the "DI" bit set to "0" when we leave this routine. */
3585 eecd &= ~E1000_EECD_DI;
3586 E1000_WRITE_REG(hw, EECD, eecd);
3589 /******************************************************************************
3590 * Shift data bits in from the EEPROM
3592 * hw - Struct containing variables accessed by shared code
3593 *****************************************************************************/
3595 e1000_shift_in_ee_bits(struct e1000_hw *hw,
3602 /* In order to read a register from the EEPROM, we need to shift 'count'
3603 * bits in from the EEPROM. Bits are "shifted in" by raising the clock
3604 * input to the EEPROM (setting the SK bit), and then reading the value of
3605 * the "DO" bit. During this "shifting in" process the "DI" bit should
3609 eecd = E1000_READ_REG(hw, EECD);
3611 eecd &= ~(E1000_EECD_DO | E1000_EECD_DI);
3614 for(i = 0; i < count; i++) {
3616 e1000_raise_ee_clk(hw, &eecd);
3618 eecd = E1000_READ_REG(hw, EECD);
3620 eecd &= ~(E1000_EECD_DI);
3621 if(eecd & E1000_EECD_DO)
3624 e1000_lower_ee_clk(hw, &eecd);
3630 /******************************************************************************
3631 * Prepares EEPROM for access
3633 * hw - Struct containing variables accessed by shared code
3635 * Lowers EEPROM clock. Clears input pin. Sets the chip select pin. This
3636 * function should be called before issuing a command to the EEPROM.
3637 *****************************************************************************/
3639 e1000_acquire_eeprom(struct e1000_hw *hw)
3641 struct e1000_eeprom_info *eeprom = &hw->eeprom;
3644 DEBUGFUNC("e1000_acquire_eeprom");
3646 if(e1000_get_hw_eeprom_semaphore(hw))
3647 return -E1000_ERR_EEPROM;
3649 eecd = E1000_READ_REG(hw, EECD);
3651 if (hw->mac_type != e1000_82573) {
3652 /* Request EEPROM Access */
3653 if(hw->mac_type > e1000_82544) {
3654 eecd |= E1000_EECD_REQ;
3655 E1000_WRITE_REG(hw, EECD, eecd);
3656 eecd = E1000_READ_REG(hw, EECD);
3657 while((!(eecd & E1000_EECD_GNT)) &&
3658 (i < E1000_EEPROM_GRANT_ATTEMPTS)) {
3661 eecd = E1000_READ_REG(hw, EECD);
3663 if(!(eecd & E1000_EECD_GNT)) {
3664 eecd &= ~E1000_EECD_REQ;
3665 E1000_WRITE_REG(hw, EECD, eecd);
3666 DEBUGOUT("Could not acquire EEPROM grant\n");
3667 e1000_put_hw_eeprom_semaphore(hw);
3668 return -E1000_ERR_EEPROM;
3673 /* Setup EEPROM for Read/Write */
3675 if (eeprom->type == e1000_eeprom_microwire) {
3676 /* Clear SK and DI */
3677 eecd &= ~(E1000_EECD_DI | E1000_EECD_SK);
3678 E1000_WRITE_REG(hw, EECD, eecd);
3681 eecd |= E1000_EECD_CS;
3682 E1000_WRITE_REG(hw, EECD, eecd);
3683 } else if (eeprom->type == e1000_eeprom_spi) {
3684 /* Clear SK and CS */
3685 eecd &= ~(E1000_EECD_CS | E1000_EECD_SK);
3686 E1000_WRITE_REG(hw, EECD, eecd);
3690 return E1000_SUCCESS;
3693 /******************************************************************************
3694 * Returns EEPROM to a "standby" state
3696 * hw - Struct containing variables accessed by shared code
3697 *****************************************************************************/
3699 e1000_standby_eeprom(struct e1000_hw *hw)
3701 struct e1000_eeprom_info *eeprom = &hw->eeprom;
3704 eecd = E1000_READ_REG(hw, EECD);
3706 if(eeprom->type == e1000_eeprom_microwire) {
3707 eecd &= ~(E1000_EECD_CS | E1000_EECD_SK);
3708 E1000_WRITE_REG(hw, EECD, eecd);
3709 E1000_WRITE_FLUSH(hw);
3710 udelay(eeprom->delay_usec);
3713 eecd |= E1000_EECD_SK;
3714 E1000_WRITE_REG(hw, EECD, eecd);
3715 E1000_WRITE_FLUSH(hw);
3716 udelay(eeprom->delay_usec);
3719 eecd |= E1000_EECD_CS;
3720 E1000_WRITE_REG(hw, EECD, eecd);
3721 E1000_WRITE_FLUSH(hw);
3722 udelay(eeprom->delay_usec);
3725 eecd &= ~E1000_EECD_SK;
3726 E1000_WRITE_REG(hw, EECD, eecd);
3727 E1000_WRITE_FLUSH(hw);
3728 udelay(eeprom->delay_usec);
3729 } else if(eeprom->type == e1000_eeprom_spi) {
3730 /* Toggle CS to flush commands */
3731 eecd |= E1000_EECD_CS;
3732 E1000_WRITE_REG(hw, EECD, eecd);
3733 E1000_WRITE_FLUSH(hw);
3734 udelay(eeprom->delay_usec);
3735 eecd &= ~E1000_EECD_CS;
3736 E1000_WRITE_REG(hw, EECD, eecd);
3737 E1000_WRITE_FLUSH(hw);
3738 udelay(eeprom->delay_usec);
3742 /******************************************************************************
3743 * Terminates a command by inverting the EEPROM's chip select pin
3745 * hw - Struct containing variables accessed by shared code
3746 *****************************************************************************/
3748 e1000_release_eeprom(struct e1000_hw *hw)
3752 DEBUGFUNC("e1000_release_eeprom");
3754 eecd = E1000_READ_REG(hw, EECD);
3756 if (hw->eeprom.type == e1000_eeprom_spi) {
3757 eecd |= E1000_EECD_CS; /* Pull CS high */
3758 eecd &= ~E1000_EECD_SK; /* Lower SCK */
3760 E1000_WRITE_REG(hw, EECD, eecd);
3762 udelay(hw->eeprom.delay_usec);
3763 } else if(hw->eeprom.type == e1000_eeprom_microwire) {
3764 /* cleanup eeprom */
3766 /* CS on Microwire is active-high */
3767 eecd &= ~(E1000_EECD_CS | E1000_EECD_DI);
3769 E1000_WRITE_REG(hw, EECD, eecd);
3771 /* Rising edge of clock */
3772 eecd |= E1000_EECD_SK;
3773 E1000_WRITE_REG(hw, EECD, eecd);
3774 E1000_WRITE_FLUSH(hw);
3775 udelay(hw->eeprom.delay_usec);
3777 /* Falling edge of clock */
3778 eecd &= ~E1000_EECD_SK;
3779 E1000_WRITE_REG(hw, EECD, eecd);
3780 E1000_WRITE_FLUSH(hw);
3781 udelay(hw->eeprom.delay_usec);
3784 /* Stop requesting EEPROM access */
3785 if(hw->mac_type > e1000_82544) {
3786 eecd &= ~E1000_EECD_REQ;
3787 E1000_WRITE_REG(hw, EECD, eecd);
3790 e1000_put_hw_eeprom_semaphore(hw);
3793 /******************************************************************************
3794 * Reads a 16 bit word from the EEPROM.
3796 * hw - Struct containing variables accessed by shared code
3797 *****************************************************************************/
3799 e1000_spi_eeprom_ready(struct e1000_hw *hw)
3801 uint16_t retry_count = 0;
3802 uint8_t spi_stat_reg;
3804 DEBUGFUNC("e1000_spi_eeprom_ready");
3806 /* Read "Status Register" repeatedly until the LSB is cleared. The
3807 * EEPROM will signal that the command has been completed by clearing
3808 * bit 0 of the internal status register. If it's not cleared within
3809 * 5 milliseconds, then error out.
3813 e1000_shift_out_ee_bits(hw, EEPROM_RDSR_OPCODE_SPI,
3814 hw->eeprom.opcode_bits);
3815 spi_stat_reg = (uint8_t)e1000_shift_in_ee_bits(hw, 8);
3816 if (!(spi_stat_reg & EEPROM_STATUS_RDY_SPI))
3822 e1000_standby_eeprom(hw);
3823 } while(retry_count < EEPROM_MAX_RETRY_SPI);
3825 /* ATMEL SPI write time could vary from 0-20mSec on 3.3V devices (and
3826 * only 0-5mSec on 5V devices)
3828 if(retry_count >= EEPROM_MAX_RETRY_SPI) {
3829 DEBUGOUT("SPI EEPROM Status error\n");
3830 return -E1000_ERR_EEPROM;
3833 return E1000_SUCCESS;
3836 /******************************************************************************
3837 * Reads a 16 bit word from the EEPROM.
3839 * hw - Struct containing variables accessed by shared code
3840 * offset - offset of word in the EEPROM to read
3841 * data - word read from the EEPROM
3842 * words - number of words to read
3843 *****************************************************************************/
3845 e1000_read_eeprom(struct e1000_hw *hw,
3850 struct e1000_eeprom_info *eeprom = &hw->eeprom;
3854 DEBUGFUNC("e1000_read_eeprom");
3856 /* A check for invalid values: offset too large, too many words, and not
3859 if((offset >= eeprom->word_size) || (words > eeprom->word_size - offset) ||
3861 DEBUGOUT("\"words\" parameter out of bounds\n");
3862 return -E1000_ERR_EEPROM;
3865 /* FLASH reads without acquiring the semaphore are safe in 82573-based
3868 if ((e1000_is_onboard_nvm_eeprom(hw) == TRUE) ||
3869 (hw->mac_type != e1000_82573)) {
3870 /* Prepare the EEPROM for reading */
3871 if(e1000_acquire_eeprom(hw) != E1000_SUCCESS)
3872 return -E1000_ERR_EEPROM;
3875 if(eeprom->use_eerd == TRUE) {
3876 ret_val = e1000_read_eeprom_eerd(hw, offset, words, data);
3877 if ((e1000_is_onboard_nvm_eeprom(hw) == TRUE) ||
3878 (hw->mac_type != e1000_82573))
3879 e1000_release_eeprom(hw);
3883 if(eeprom->type == e1000_eeprom_spi) {
3885 uint8_t read_opcode = EEPROM_READ_OPCODE_SPI;
3887 if(e1000_spi_eeprom_ready(hw)) {
3888 e1000_release_eeprom(hw);
3889 return -E1000_ERR_EEPROM;
3892 e1000_standby_eeprom(hw);
3894 /* Some SPI eeproms use the 8th address bit embedded in the opcode */
3895 if((eeprom->address_bits == 8) && (offset >= 128))
3896 read_opcode |= EEPROM_A8_OPCODE_SPI;
3898 /* Send the READ command (opcode + addr) */
3899 e1000_shift_out_ee_bits(hw, read_opcode, eeprom->opcode_bits);
3900 e1000_shift_out_ee_bits(hw, (uint16_t)(offset*2), eeprom->address_bits);
3902 /* Read the data. The address of the eeprom internally increments with
3903 * each byte (spi) being read, saving on the overhead of eeprom setup
3904 * and tear-down. The address counter will roll over if reading beyond
3905 * the size of the eeprom, thus allowing the entire memory to be read
3906 * starting from any offset. */
3907 for (i = 0; i < words; i++) {
3908 word_in = e1000_shift_in_ee_bits(hw, 16);
3909 data[i] = (word_in >> 8) | (word_in << 8);
3911 } else if(eeprom->type == e1000_eeprom_microwire) {
3912 for (i = 0; i < words; i++) {
3913 /* Send the READ command (opcode + addr) */
3914 e1000_shift_out_ee_bits(hw, EEPROM_READ_OPCODE_MICROWIRE,
3915 eeprom->opcode_bits);
3916 e1000_shift_out_ee_bits(hw, (uint16_t)(offset + i),
3917 eeprom->address_bits);
3919 /* Read the data. For microwire, each word requires the overhead
3920 * of eeprom setup and tear-down. */
3921 data[i] = e1000_shift_in_ee_bits(hw, 16);
3922 e1000_standby_eeprom(hw);
3926 /* End this read operation */
3927 e1000_release_eeprom(hw);
3929 return E1000_SUCCESS;
3932 /******************************************************************************
3933 * Reads a 16 bit word from the EEPROM using the EERD register.
3935 * hw - Struct containing variables accessed by shared code
3936 * offset - offset of word in the EEPROM to read
3937 * data - word read from the EEPROM
3938 * words - number of words to read
3939 *****************************************************************************/
3941 e1000_read_eeprom_eerd(struct e1000_hw *hw,
3946 uint32_t i, eerd = 0;
3949 for (i = 0; i < words; i++) {
3950 eerd = ((offset+i) << E1000_EEPROM_RW_ADDR_SHIFT) +
3951 E1000_EEPROM_RW_REG_START;
3953 E1000_WRITE_REG(hw, EERD, eerd);
3954 error = e1000_poll_eerd_eewr_done(hw, E1000_EEPROM_POLL_READ);
3959 data[i] = (E1000_READ_REG(hw, EERD) >> E1000_EEPROM_RW_REG_DATA);
3966 /******************************************************************************
3967 * Writes a 16 bit word from the EEPROM using the EEWR register.
3969 * hw - Struct containing variables accessed by shared code
3970 * offset - offset of word in the EEPROM to read
3971 * data - word read from the EEPROM
3972 * words - number of words to read
3973 *****************************************************************************/
3975 e1000_write_eeprom_eewr(struct e1000_hw *hw,
3980 uint32_t register_value = 0;
3984 for (i = 0; i < words; i++) {
3985 register_value = (data[i] << E1000_EEPROM_RW_REG_DATA) |
3986 ((offset+i) << E1000_EEPROM_RW_ADDR_SHIFT) |
3987 E1000_EEPROM_RW_REG_START;
3989 error = e1000_poll_eerd_eewr_done(hw, E1000_EEPROM_POLL_WRITE);
3994 E1000_WRITE_REG(hw, EEWR, register_value);
3996 error = e1000_poll_eerd_eewr_done(hw, E1000_EEPROM_POLL_WRITE);
4006 /******************************************************************************
4007 * Polls the status bit (bit 1) of the EERD to determine when the read is done.
4009 * hw - Struct containing variables accessed by shared code
4010 *****************************************************************************/
4012 e1000_poll_eerd_eewr_done(struct e1000_hw *hw, int eerd)
4014 uint32_t attempts = 100000;
4015 uint32_t i, reg = 0;
4016 int32_t done = E1000_ERR_EEPROM;
4018 for(i = 0; i < attempts; i++) {
4019 if(eerd == E1000_EEPROM_POLL_READ)
4020 reg = E1000_READ_REG(hw, EERD);
4022 reg = E1000_READ_REG(hw, EEWR);
4024 if(reg & E1000_EEPROM_RW_REG_DONE) {
4025 done = E1000_SUCCESS;
4034 /***************************************************************************
4035 * Description: Determines if the onboard NVM is FLASH or EEPROM.
4037 * hw - Struct containing variables accessed by shared code
4038 ****************************************************************************/
4040 e1000_is_onboard_nvm_eeprom(struct e1000_hw *hw)
4044 if(hw->mac_type == e1000_82573) {
4045 eecd = E1000_READ_REG(hw, EECD);
4047 /* Isolate bits 15 & 16 */
4048 eecd = ((eecd >> 15) & 0x03);
4050 /* If both bits are set, device is Flash type */
4058 /******************************************************************************
4059 * Verifies that the EEPROM has a valid checksum
4061 * hw - Struct containing variables accessed by shared code
4063 * Reads the first 64 16 bit words of the EEPROM and sums the values read.
4064 * If the the sum of the 64 16 bit words is 0xBABA, the EEPROM's checksum is
4066 *****************************************************************************/
4068 e1000_validate_eeprom_checksum(struct e1000_hw *hw)
4070 uint16_t checksum = 0;
4071 uint16_t i, eeprom_data;
4073 DEBUGFUNC("e1000_validate_eeprom_checksum");
4075 if ((hw->mac_type == e1000_82573) &&
4076 (e1000_is_onboard_nvm_eeprom(hw) == FALSE)) {
4077 /* Check bit 4 of word 10h. If it is 0, firmware is done updating
4078 * 10h-12h. Checksum may need to be fixed. */
4079 e1000_read_eeprom(hw, 0x10, 1, &eeprom_data);
4080 if ((eeprom_data & 0x10) == 0) {
4081 /* Read 0x23 and check bit 15. This bit is a 1 when the checksum
4082 * has already been fixed. If the checksum is still wrong and this
4083 * bit is a 1, we need to return bad checksum. Otherwise, we need
4084 * to set this bit to a 1 and update the checksum. */
4085 e1000_read_eeprom(hw, 0x23, 1, &eeprom_data);
4086 if ((eeprom_data & 0x8000) == 0) {
4087 eeprom_data |= 0x8000;
4088 e1000_write_eeprom(hw, 0x23, 1, &eeprom_data);
4089 e1000_update_eeprom_checksum(hw);
4094 for(i = 0; i < (EEPROM_CHECKSUM_REG + 1); i++) {
4095 if(e1000_read_eeprom(hw, i, 1, &eeprom_data) < 0) {
4096 DEBUGOUT("EEPROM Read Error\n");
4097 return -E1000_ERR_EEPROM;
4099 checksum += eeprom_data;
4102 if(checksum == (uint16_t) EEPROM_SUM)
4103 return E1000_SUCCESS;
4105 DEBUGOUT("EEPROM Checksum Invalid\n");
4106 return -E1000_ERR_EEPROM;
4110 /******************************************************************************
4111 * Calculates the EEPROM checksum and writes it to the EEPROM
4113 * hw - Struct containing variables accessed by shared code
4115 * Sums the first 63 16 bit words of the EEPROM. Subtracts the sum from 0xBABA.
4116 * Writes the difference to word offset 63 of the EEPROM.
4117 *****************************************************************************/
4119 e1000_update_eeprom_checksum(struct e1000_hw *hw)
4121 uint16_t checksum = 0;
4122 uint16_t i, eeprom_data;
4124 DEBUGFUNC("e1000_update_eeprom_checksum");
4126 for(i = 0; i < EEPROM_CHECKSUM_REG; i++) {
4127 if(e1000_read_eeprom(hw, i, 1, &eeprom_data) < 0) {
4128 DEBUGOUT("EEPROM Read Error\n");
4129 return -E1000_ERR_EEPROM;
4131 checksum += eeprom_data;
4133 checksum = (uint16_t) EEPROM_SUM - checksum;
4134 if(e1000_write_eeprom(hw, EEPROM_CHECKSUM_REG, 1, &checksum) < 0) {
4135 DEBUGOUT("EEPROM Write Error\n");
4136 return -E1000_ERR_EEPROM;
4137 } else if (hw->eeprom.type == e1000_eeprom_flash) {
4138 e1000_commit_shadow_ram(hw);
4140 return E1000_SUCCESS;
4143 /******************************************************************************
4144 * Parent function for writing words to the different EEPROM types.
4146 * hw - Struct containing variables accessed by shared code
4147 * offset - offset within the EEPROM to be written to
4148 * words - number of words to write
4149 * data - 16 bit word to be written to the EEPROM
4151 * If e1000_update_eeprom_checksum is not called after this function, the
4152 * EEPROM will most likely contain an invalid checksum.
4153 *****************************************************************************/
4155 e1000_write_eeprom(struct e1000_hw *hw,
4160 struct e1000_eeprom_info *eeprom = &hw->eeprom;
4163 DEBUGFUNC("e1000_write_eeprom");
4165 /* A check for invalid values: offset too large, too many words, and not
4168 if((offset >= eeprom->word_size) || (words > eeprom->word_size - offset) ||
4170 DEBUGOUT("\"words\" parameter out of bounds\n");
4171 return -E1000_ERR_EEPROM;
4174 /* 82573 writes only through eewr */
4175 if(eeprom->use_eewr == TRUE)
4176 return e1000_write_eeprom_eewr(hw, offset, words, data);
4178 /* Prepare the EEPROM for writing */
4179 if (e1000_acquire_eeprom(hw) != E1000_SUCCESS)
4180 return -E1000_ERR_EEPROM;
4182 if(eeprom->type == e1000_eeprom_microwire) {
4183 status = e1000_write_eeprom_microwire(hw, offset, words, data);
4185 status = e1000_write_eeprom_spi(hw, offset, words, data);
4189 /* Done with writing */
4190 e1000_release_eeprom(hw);
4195 /******************************************************************************
4196 * Writes a 16 bit word to a given offset in an SPI EEPROM.
4198 * hw - Struct containing variables accessed by shared code
4199 * offset - offset within the EEPROM to be written to
4200 * words - number of words to write
4201 * data - pointer to array of 8 bit words to be written to the EEPROM
4203 *****************************************************************************/
4205 e1000_write_eeprom_spi(struct e1000_hw *hw,
4210 struct e1000_eeprom_info *eeprom = &hw->eeprom;
4213 DEBUGFUNC("e1000_write_eeprom_spi");
4215 while (widx < words) {
4216 uint8_t write_opcode = EEPROM_WRITE_OPCODE_SPI;
4218 if(e1000_spi_eeprom_ready(hw)) return -E1000_ERR_EEPROM;
4220 e1000_standby_eeprom(hw);
4222 /* Send the WRITE ENABLE command (8 bit opcode ) */
4223 e1000_shift_out_ee_bits(hw, EEPROM_WREN_OPCODE_SPI,
4224 eeprom->opcode_bits);
4226 e1000_standby_eeprom(hw);
4228 /* Some SPI eeproms use the 8th address bit embedded in the opcode */
4229 if((eeprom->address_bits == 8) && (offset >= 128))
4230 write_opcode |= EEPROM_A8_OPCODE_SPI;
4232 /* Send the Write command (8-bit opcode + addr) */
4233 e1000_shift_out_ee_bits(hw, write_opcode, eeprom->opcode_bits);
4235 e1000_shift_out_ee_bits(hw, (uint16_t)((offset + widx)*2),
4236 eeprom->address_bits);
4240 /* Loop to allow for up to whole page write (32 bytes) of eeprom */
4241 while (widx < words) {
4242 uint16_t word_out = data[widx];
4243 word_out = (word_out >> 8) | (word_out << 8);
4244 e1000_shift_out_ee_bits(hw, word_out, 16);
4247 /* Some larger eeprom sizes are capable of a 32-byte PAGE WRITE
4248 * operation, while the smaller eeproms are capable of an 8-byte
4249 * PAGE WRITE operation. Break the inner loop to pass new address
4251 if((((offset + widx)*2) % eeprom->page_size) == 0) {
4252 e1000_standby_eeprom(hw);
4258 return E1000_SUCCESS;
4261 /******************************************************************************
4262 * Writes a 16 bit word to a given offset in a Microwire EEPROM.
4264 * hw - Struct containing variables accessed by shared code
4265 * offset - offset within the EEPROM to be written to
4266 * words - number of words to write
4267 * data - pointer to array of 16 bit words to be written to the EEPROM
4269 *****************************************************************************/
4271 e1000_write_eeprom_microwire(struct e1000_hw *hw,
4276 struct e1000_eeprom_info *eeprom = &hw->eeprom;
4278 uint16_t words_written = 0;
4281 DEBUGFUNC("e1000_write_eeprom_microwire");
4283 /* Send the write enable command to the EEPROM (3-bit opcode plus
4284 * 6/8-bit dummy address beginning with 11). It's less work to include
4285 * the 11 of the dummy address as part of the opcode than it is to shift
4286 * it over the correct number of bits for the address. This puts the
4287 * EEPROM into write/erase mode.
4289 e1000_shift_out_ee_bits(hw, EEPROM_EWEN_OPCODE_MICROWIRE,
4290 (uint16_t)(eeprom->opcode_bits + 2));
4292 e1000_shift_out_ee_bits(hw, 0, (uint16_t)(eeprom->address_bits - 2));
4294 /* Prepare the EEPROM */
4295 e1000_standby_eeprom(hw);
4297 while (words_written < words) {
4298 /* Send the Write command (3-bit opcode + addr) */
4299 e1000_shift_out_ee_bits(hw, EEPROM_WRITE_OPCODE_MICROWIRE,
4300 eeprom->opcode_bits);
4302 e1000_shift_out_ee_bits(hw, (uint16_t)(offset + words_written),
4303 eeprom->address_bits);
4306 e1000_shift_out_ee_bits(hw, data[words_written], 16);
4308 /* Toggle the CS line. This in effect tells the EEPROM to execute
4309 * the previous command.
4311 e1000_standby_eeprom(hw);
4313 /* Read DO repeatedly until it is high (equal to '1'). The EEPROM will
4314 * signal that the command has been completed by raising the DO signal.
4315 * If DO does not go high in 10 milliseconds, then error out.
4317 for(i = 0; i < 200; i++) {
4318 eecd = E1000_READ_REG(hw, EECD);
4319 if(eecd & E1000_EECD_DO) break;
4323 DEBUGOUT("EEPROM Write did not complete\n");
4324 return -E1000_ERR_EEPROM;
4327 /* Recover from write */
4328 e1000_standby_eeprom(hw);
4333 /* Send the write disable command to the EEPROM (3-bit opcode plus
4334 * 6/8-bit dummy address beginning with 10). It's less work to include
4335 * the 10 of the dummy address as part of the opcode than it is to shift
4336 * it over the correct number of bits for the address. This takes the
4337 * EEPROM out of write/erase mode.
4339 e1000_shift_out_ee_bits(hw, EEPROM_EWDS_OPCODE_MICROWIRE,
4340 (uint16_t)(eeprom->opcode_bits + 2));
4342 e1000_shift_out_ee_bits(hw, 0, (uint16_t)(eeprom->address_bits - 2));
4344 return E1000_SUCCESS;
4347 /******************************************************************************
4348 * Flushes the cached eeprom to NVM. This is done by saving the modified values
4349 * in the eeprom cache and the non modified values in the currently active bank
4352 * hw - Struct containing variables accessed by shared code
4353 * offset - offset of word in the EEPROM to read
4354 * data - word read from the EEPROM
4355 * words - number of words to read
4356 *****************************************************************************/
4358 e1000_commit_shadow_ram(struct e1000_hw *hw)
4360 uint32_t attempts = 100000;
4364 int32_t error = E1000_SUCCESS;
4366 /* The flop register will be used to determine if flash type is STM */
4367 flop = E1000_READ_REG(hw, FLOP);
4369 if (hw->mac_type == e1000_82573) {
4370 for (i=0; i < attempts; i++) {
4371 eecd = E1000_READ_REG(hw, EECD);
4372 if ((eecd & E1000_EECD_FLUPD) == 0) {
4378 if (i == attempts) {
4379 return -E1000_ERR_EEPROM;
4382 /* If STM opcode located in bits 15:8 of flop, reset firmware */
4383 if ((flop & 0xFF00) == E1000_STM_OPCODE) {
4384 E1000_WRITE_REG(hw, HICR, E1000_HICR_FW_RESET);
4387 /* Perform the flash update */
4388 E1000_WRITE_REG(hw, EECD, eecd | E1000_EECD_FLUPD);
4390 for (i=0; i < attempts; i++) {
4391 eecd = E1000_READ_REG(hw, EECD);
4392 if ((eecd & E1000_EECD_FLUPD) == 0) {
4398 if (i == attempts) {
4399 return -E1000_ERR_EEPROM;
4406 /******************************************************************************
4407 * Reads the adapter's part number from the EEPROM
4409 * hw - Struct containing variables accessed by shared code
4410 * part_num - Adapter's part number
4411 *****************************************************************************/
4413 e1000_read_part_num(struct e1000_hw *hw,
4416 uint16_t offset = EEPROM_PBA_BYTE_1;
4417 uint16_t eeprom_data;
4419 DEBUGFUNC("e1000_read_part_num");
4421 /* Get word 0 from EEPROM */
4422 if(e1000_read_eeprom(hw, offset, 1, &eeprom_data) < 0) {
4423 DEBUGOUT("EEPROM Read Error\n");
4424 return -E1000_ERR_EEPROM;
4426 /* Save word 0 in upper half of part_num */
4427 *part_num = (uint32_t) (eeprom_data << 16);
4429 /* Get word 1 from EEPROM */
4430 if(e1000_read_eeprom(hw, ++offset, 1, &eeprom_data) < 0) {
4431 DEBUGOUT("EEPROM Read Error\n");
4432 return -E1000_ERR_EEPROM;
4434 /* Save word 1 in lower half of part_num */
4435 *part_num |= eeprom_data;
4437 return E1000_SUCCESS;
4440 /******************************************************************************
4441 * Reads the adapter's MAC address from the EEPROM and inverts the LSB for the
4442 * second function of dual function devices
4444 * hw - Struct containing variables accessed by shared code
4445 *****************************************************************************/
4447 e1000_read_mac_addr(struct e1000_hw * hw)
4450 uint16_t eeprom_data, i;
4452 DEBUGFUNC("e1000_read_mac_addr");
4454 for(i = 0; i < NODE_ADDRESS_SIZE; i += 2) {
4456 if(e1000_read_eeprom(hw, offset, 1, &eeprom_data) < 0) {
4457 DEBUGOUT("EEPROM Read Error\n");
4458 return -E1000_ERR_EEPROM;
4460 hw->perm_mac_addr[i] = (uint8_t) (eeprom_data & 0x00FF);
4461 hw->perm_mac_addr[i+1] = (uint8_t) (eeprom_data >> 8);
4463 switch (hw->mac_type) {
4467 case e1000_82546_rev_3:
4469 if(E1000_READ_REG(hw, STATUS) & E1000_STATUS_FUNC_1)
4470 hw->perm_mac_addr[5] ^= 0x01;
4474 for(i = 0; i < NODE_ADDRESS_SIZE; i++)
4475 hw->mac_addr[i] = hw->perm_mac_addr[i];
4476 return E1000_SUCCESS;
4479 /******************************************************************************
4480 * Initializes receive address filters.
4482 * hw - Struct containing variables accessed by shared code
4484 * Places the MAC address in receive address register 0 and clears the rest
4485 * of the receive addresss registers. Clears the multicast table. Assumes
4486 * the receiver is in reset when the routine is called.
4487 *****************************************************************************/
4489 e1000_init_rx_addrs(struct e1000_hw *hw)
4494 DEBUGFUNC("e1000_init_rx_addrs");
4496 /* Setup the receive address. */
4497 DEBUGOUT("Programming MAC Address into RAR[0]\n");
4499 e1000_rar_set(hw, hw->mac_addr, 0);
4501 rar_num = E1000_RAR_ENTRIES;
4503 /* Reserve a spot for the Locally Administered Address to work around
4504 * an 82571 issue in which a reset on one port will reload the MAC on
4505 * the other port. */
4506 if ((hw->mac_type == e1000_82571) && (hw->laa_is_present == TRUE))
4508 /* Zero out the other 15 receive addresses. */
4509 DEBUGOUT("Clearing RAR[1-15]\n");
4510 for(i = 1; i < rar_num; i++) {
4511 E1000_WRITE_REG_ARRAY(hw, RA, (i << 1), 0);
4512 E1000_WRITE_REG_ARRAY(hw, RA, ((i << 1) + 1), 0);
4517 /******************************************************************************
4518 * Updates the MAC's list of multicast addresses.
4520 * hw - Struct containing variables accessed by shared code
4521 * mc_addr_list - the list of new multicast addresses
4522 * mc_addr_count - number of addresses
4523 * pad - number of bytes between addresses in the list
4524 * rar_used_count - offset where to start adding mc addresses into the RAR's
4526 * The given list replaces any existing list. Clears the last 15 receive
4527 * address registers and the multicast table. Uses receive address registers
4528 * for the first 15 multicast addresses, and hashes the rest into the
4530 *****************************************************************************/
4532 e1000_mc_addr_list_update(struct e1000_hw *hw,
4533 uint8_t *mc_addr_list,
4534 uint32_t mc_addr_count,
4536 uint32_t rar_used_count)
4538 uint32_t hash_value;
4540 uint32_t num_rar_entry;
4541 uint32_t num_mta_entry;
4543 DEBUGFUNC("e1000_mc_addr_list_update");
4545 /* Set the new number of MC addresses that we are being requested to use. */
4546 hw->num_mc_addrs = mc_addr_count;
4548 /* Clear RAR[1-15] */
4549 DEBUGOUT(" Clearing RAR[1-15]\n");
4550 num_rar_entry = E1000_RAR_ENTRIES;
4551 /* Reserve a spot for the Locally Administered Address to work around
4552 * an 82571 issue in which a reset on one port will reload the MAC on
4553 * the other port. */
4554 if ((hw->mac_type == e1000_82571) && (hw->laa_is_present == TRUE))
4557 for(i = rar_used_count; i < num_rar_entry; i++) {
4558 E1000_WRITE_REG_ARRAY(hw, RA, (i << 1), 0);
4559 E1000_WRITE_REG_ARRAY(hw, RA, ((i << 1) + 1), 0);
4563 DEBUGOUT(" Clearing MTA\n");
4564 num_mta_entry = E1000_NUM_MTA_REGISTERS;
4565 for(i = 0; i < num_mta_entry; i++) {
4566 E1000_WRITE_REG_ARRAY(hw, MTA, i, 0);
4569 /* Add the new addresses */
4570 for(i = 0; i < mc_addr_count; i++) {
4571 DEBUGOUT(" Adding the multicast addresses:\n");
4572 DEBUGOUT7(" MC Addr #%d =%.2X %.2X %.2X %.2X %.2X %.2X\n", i,
4573 mc_addr_list[i * (ETH_LENGTH_OF_ADDRESS + pad)],
4574 mc_addr_list[i * (ETH_LENGTH_OF_ADDRESS + pad) + 1],
4575 mc_addr_list[i * (ETH_LENGTH_OF_ADDRESS + pad) + 2],
4576 mc_addr_list[i * (ETH_LENGTH_OF_ADDRESS + pad) + 3],
4577 mc_addr_list[i * (ETH_LENGTH_OF_ADDRESS + pad) + 4],
4578 mc_addr_list[i * (ETH_LENGTH_OF_ADDRESS + pad) + 5]);
4580 hash_value = e1000_hash_mc_addr(hw,
4582 (i * (ETH_LENGTH_OF_ADDRESS + pad)));
4584 DEBUGOUT1(" Hash value = 0x%03X\n", hash_value);
4586 /* Place this multicast address in the RAR if there is room, *
4587 * else put it in the MTA
4589 if (rar_used_count < num_rar_entry) {
4591 mc_addr_list + (i * (ETH_LENGTH_OF_ADDRESS + pad)),
4595 e1000_mta_set(hw, hash_value);
4598 DEBUGOUT("MC Update Complete\n");
4602 /******************************************************************************
4603 * Hashes an address to determine its location in the multicast table
4605 * hw - Struct containing variables accessed by shared code
4606 * mc_addr - the multicast address to hash
4607 *****************************************************************************/
4609 e1000_hash_mc_addr(struct e1000_hw *hw,
4612 uint32_t hash_value = 0;
4614 /* The portion of the address that is used for the hash table is
4615 * determined by the mc_filter_type setting.
4617 switch (hw->mc_filter_type) {
4618 /* [0] [1] [2] [3] [4] [5]
4623 /* [47:36] i.e. 0x563 for above example address */
4624 hash_value = ((mc_addr[4] >> 4) | (((uint16_t) mc_addr[5]) << 4));
4627 /* [46:35] i.e. 0xAC6 for above example address */
4628 hash_value = ((mc_addr[4] >> 3) | (((uint16_t) mc_addr[5]) << 5));
4631 /* [45:34] i.e. 0x5D8 for above example address */
4632 hash_value = ((mc_addr[4] >> 2) | (((uint16_t) mc_addr[5]) << 6));
4635 /* [43:32] i.e. 0x634 for above example address */
4636 hash_value = ((mc_addr[4]) | (((uint16_t) mc_addr[5]) << 8));
4640 hash_value &= 0xFFF;
4645 /******************************************************************************
4646 * Sets the bit in the multicast table corresponding to the hash value.
4648 * hw - Struct containing variables accessed by shared code
4649 * hash_value - Multicast address hash value
4650 *****************************************************************************/
4652 e1000_mta_set(struct e1000_hw *hw,
4653 uint32_t hash_value)
4655 uint32_t hash_bit, hash_reg;
4659 /* The MTA is a register array of 128 32-bit registers.
4660 * It is treated like an array of 4096 bits. We want to set
4661 * bit BitArray[hash_value]. So we figure out what register
4662 * the bit is in, read it, OR in the new bit, then write
4663 * back the new value. The register is determined by the
4664 * upper 7 bits of the hash value and the bit within that
4665 * register are determined by the lower 5 bits of the value.
4667 hash_reg = (hash_value >> 5) & 0x7F;
4668 hash_bit = hash_value & 0x1F;
4670 mta = E1000_READ_REG_ARRAY(hw, MTA, hash_reg);
4672 mta |= (1 << hash_bit);
4674 /* If we are on an 82544 and we are trying to write an odd offset
4675 * in the MTA, save off the previous entry before writing and
4676 * restore the old value after writing.
4678 if((hw->mac_type == e1000_82544) && ((hash_reg & 0x1) == 1)) {
4679 temp = E1000_READ_REG_ARRAY(hw, MTA, (hash_reg - 1));
4680 E1000_WRITE_REG_ARRAY(hw, MTA, hash_reg, mta);
4681 E1000_WRITE_REG_ARRAY(hw, MTA, (hash_reg - 1), temp);
4683 E1000_WRITE_REG_ARRAY(hw, MTA, hash_reg, mta);
4687 /******************************************************************************
4688 * Puts an ethernet address into a receive address register.
4690 * hw - Struct containing variables accessed by shared code
4691 * addr - Address to put into receive address register
4692 * index - Receive address register to write
4693 *****************************************************************************/
4695 e1000_rar_set(struct e1000_hw *hw,
4699 uint32_t rar_low, rar_high;
4701 /* HW expects these in little endian so we reverse the byte order
4702 * from network order (big endian) to little endian
4704 rar_low = ((uint32_t) addr[0] |
4705 ((uint32_t) addr[1] << 8) |
4706 ((uint32_t) addr[2] << 16) | ((uint32_t) addr[3] << 24));
4708 rar_high = ((uint32_t) addr[4] | ((uint32_t) addr[5] << 8) | E1000_RAH_AV);
4710 E1000_WRITE_REG_ARRAY(hw, RA, (index << 1), rar_low);
4711 E1000_WRITE_REG_ARRAY(hw, RA, ((index << 1) + 1), rar_high);
4714 /******************************************************************************
4715 * Writes a value to the specified offset in the VLAN filter table.
4717 * hw - Struct containing variables accessed by shared code
4718 * offset - Offset in VLAN filer table to write
4719 * value - Value to write into VLAN filter table
4720 *****************************************************************************/
4722 e1000_write_vfta(struct e1000_hw *hw,
4728 if((hw->mac_type == e1000_82544) && ((offset & 0x1) == 1)) {
4729 temp = E1000_READ_REG_ARRAY(hw, VFTA, (offset - 1));
4730 E1000_WRITE_REG_ARRAY(hw, VFTA, offset, value);
4731 E1000_WRITE_REG_ARRAY(hw, VFTA, (offset - 1), temp);
4733 E1000_WRITE_REG_ARRAY(hw, VFTA, offset, value);
4737 /******************************************************************************
4738 * Clears the VLAN filer table
4740 * hw - Struct containing variables accessed by shared code
4741 *****************************************************************************/
4743 e1000_clear_vfta(struct e1000_hw *hw)
4746 uint32_t vfta_value = 0;
4747 uint32_t vfta_offset = 0;
4748 uint32_t vfta_bit_in_reg = 0;
4750 if (hw->mac_type == e1000_82573) {
4751 if (hw->mng_cookie.vlan_id != 0) {
4752 /* The VFTA is a 4096b bit-field, each identifying a single VLAN
4753 * ID. The following operations determine which 32b entry
4754 * (i.e. offset) into the array we want to set the VLAN ID
4755 * (i.e. bit) of the manageability unit. */
4756 vfta_offset = (hw->mng_cookie.vlan_id >>
4757 E1000_VFTA_ENTRY_SHIFT) &
4758 E1000_VFTA_ENTRY_MASK;
4759 vfta_bit_in_reg = 1 << (hw->mng_cookie.vlan_id &
4760 E1000_VFTA_ENTRY_BIT_SHIFT_MASK);
4763 for (offset = 0; offset < E1000_VLAN_FILTER_TBL_SIZE; offset++) {
4764 /* If the offset we want to clear is the same offset of the
4765 * manageability VLAN ID, then clear all bits except that of the
4766 * manageability unit */
4767 vfta_value = (offset == vfta_offset) ? vfta_bit_in_reg : 0;
4768 E1000_WRITE_REG_ARRAY(hw, VFTA, offset, vfta_value);
4773 e1000_id_led_init(struct e1000_hw * hw)
4776 const uint32_t ledctl_mask = 0x000000FF;
4777 const uint32_t ledctl_on = E1000_LEDCTL_MODE_LED_ON;
4778 const uint32_t ledctl_off = E1000_LEDCTL_MODE_LED_OFF;
4779 uint16_t eeprom_data, i, temp;
4780 const uint16_t led_mask = 0x0F;
4782 DEBUGFUNC("e1000_id_led_init");
4784 if(hw->mac_type < e1000_82540) {
4786 return E1000_SUCCESS;
4789 ledctl = E1000_READ_REG(hw, LEDCTL);
4790 hw->ledctl_default = ledctl;
4791 hw->ledctl_mode1 = hw->ledctl_default;
4792 hw->ledctl_mode2 = hw->ledctl_default;
4794 if(e1000_read_eeprom(hw, EEPROM_ID_LED_SETTINGS, 1, &eeprom_data) < 0) {
4795 DEBUGOUT("EEPROM Read Error\n");
4796 return -E1000_ERR_EEPROM;
4798 if((eeprom_data== ID_LED_RESERVED_0000) ||
4799 (eeprom_data == ID_LED_RESERVED_FFFF)) eeprom_data = ID_LED_DEFAULT;
4800 for(i = 0; i < 4; i++) {
4801 temp = (eeprom_data >> (i << 2)) & led_mask;
4803 case ID_LED_ON1_DEF2:
4804 case ID_LED_ON1_ON2:
4805 case ID_LED_ON1_OFF2:
4806 hw->ledctl_mode1 &= ~(ledctl_mask << (i << 3));
4807 hw->ledctl_mode1 |= ledctl_on << (i << 3);
4809 case ID_LED_OFF1_DEF2:
4810 case ID_LED_OFF1_ON2:
4811 case ID_LED_OFF1_OFF2:
4812 hw->ledctl_mode1 &= ~(ledctl_mask << (i << 3));
4813 hw->ledctl_mode1 |= ledctl_off << (i << 3);
4820 case ID_LED_DEF1_ON2:
4821 case ID_LED_ON1_ON2:
4822 case ID_LED_OFF1_ON2:
4823 hw->ledctl_mode2 &= ~(ledctl_mask << (i << 3));
4824 hw->ledctl_mode2 |= ledctl_on << (i << 3);
4826 case ID_LED_DEF1_OFF2:
4827 case ID_LED_ON1_OFF2:
4828 case ID_LED_OFF1_OFF2:
4829 hw->ledctl_mode2 &= ~(ledctl_mask << (i << 3));
4830 hw->ledctl_mode2 |= ledctl_off << (i << 3);
4837 return E1000_SUCCESS;
4840 /******************************************************************************
4841 * Prepares SW controlable LED for use and saves the current state of the LED.
4843 * hw - Struct containing variables accessed by shared code
4844 *****************************************************************************/
4846 e1000_setup_led(struct e1000_hw *hw)
4849 int32_t ret_val = E1000_SUCCESS;
4851 DEBUGFUNC("e1000_setup_led");
4853 switch(hw->mac_type) {
4854 case e1000_82542_rev2_0:
4855 case e1000_82542_rev2_1:
4858 /* No setup necessary */
4862 case e1000_82541_rev_2:
4863 case e1000_82547_rev_2:
4864 /* Turn off PHY Smart Power Down (if enabled) */
4865 ret_val = e1000_read_phy_reg(hw, IGP01E1000_GMII_FIFO,
4866 &hw->phy_spd_default);
4869 ret_val = e1000_write_phy_reg(hw, IGP01E1000_GMII_FIFO,
4870 (uint16_t)(hw->phy_spd_default &
4871 ~IGP01E1000_GMII_SPD));
4876 if(hw->media_type == e1000_media_type_fiber) {
4877 ledctl = E1000_READ_REG(hw, LEDCTL);
4878 /* Save current LEDCTL settings */
4879 hw->ledctl_default = ledctl;
4881 ledctl &= ~(E1000_LEDCTL_LED0_IVRT |
4882 E1000_LEDCTL_LED0_BLINK |
4883 E1000_LEDCTL_LED0_MODE_MASK);
4884 ledctl |= (E1000_LEDCTL_MODE_LED_OFF <<
4885 E1000_LEDCTL_LED0_MODE_SHIFT);
4886 E1000_WRITE_REG(hw, LEDCTL, ledctl);
4887 } else if(hw->media_type == e1000_media_type_copper)
4888 E1000_WRITE_REG(hw, LEDCTL, hw->ledctl_mode1);
4892 return E1000_SUCCESS;
4895 /******************************************************************************
4896 * Restores the saved state of the SW controlable LED.
4898 * hw - Struct containing variables accessed by shared code
4899 *****************************************************************************/
4901 e1000_cleanup_led(struct e1000_hw *hw)
4903 int32_t ret_val = E1000_SUCCESS;
4905 DEBUGFUNC("e1000_cleanup_led");
4907 switch(hw->mac_type) {
4908 case e1000_82542_rev2_0:
4909 case e1000_82542_rev2_1:
4912 /* No cleanup necessary */
4916 case e1000_82541_rev_2:
4917 case e1000_82547_rev_2:
4918 /* Turn on PHY Smart Power Down (if previously enabled) */
4919 ret_val = e1000_write_phy_reg(hw, IGP01E1000_GMII_FIFO,
4920 hw->phy_spd_default);
4925 /* Restore LEDCTL settings */
4926 E1000_WRITE_REG(hw, LEDCTL, hw->ledctl_default);
4930 return E1000_SUCCESS;
4933 /******************************************************************************
4934 * Turns on the software controllable LED
4936 * hw - Struct containing variables accessed by shared code
4937 *****************************************************************************/
4939 e1000_led_on(struct e1000_hw *hw)
4941 uint32_t ctrl = E1000_READ_REG(hw, CTRL);
4943 DEBUGFUNC("e1000_led_on");
4945 switch(hw->mac_type) {
4946 case e1000_82542_rev2_0:
4947 case e1000_82542_rev2_1:
4949 /* Set SW Defineable Pin 0 to turn on the LED */
4950 ctrl |= E1000_CTRL_SWDPIN0;
4951 ctrl |= E1000_CTRL_SWDPIO0;
4954 if(hw->media_type == e1000_media_type_fiber) {
4955 /* Set SW Defineable Pin 0 to turn on the LED */
4956 ctrl |= E1000_CTRL_SWDPIN0;
4957 ctrl |= E1000_CTRL_SWDPIO0;
4959 /* Clear SW Defineable Pin 0 to turn on the LED */
4960 ctrl &= ~E1000_CTRL_SWDPIN0;
4961 ctrl |= E1000_CTRL_SWDPIO0;
4965 if(hw->media_type == e1000_media_type_fiber) {
4966 /* Clear SW Defineable Pin 0 to turn on the LED */
4967 ctrl &= ~E1000_CTRL_SWDPIN0;
4968 ctrl |= E1000_CTRL_SWDPIO0;
4969 } else if(hw->media_type == e1000_media_type_copper) {
4970 E1000_WRITE_REG(hw, LEDCTL, hw->ledctl_mode2);
4971 return E1000_SUCCESS;
4976 E1000_WRITE_REG(hw, CTRL, ctrl);
4978 return E1000_SUCCESS;
4981 /******************************************************************************
4982 * Turns off the software controllable LED
4984 * hw - Struct containing variables accessed by shared code
4985 *****************************************************************************/
4987 e1000_led_off(struct e1000_hw *hw)
4989 uint32_t ctrl = E1000_READ_REG(hw, CTRL);
4991 DEBUGFUNC("e1000_led_off");
4993 switch(hw->mac_type) {
4994 case e1000_82542_rev2_0:
4995 case e1000_82542_rev2_1:
4997 /* Clear SW Defineable Pin 0 to turn off the LED */
4998 ctrl &= ~E1000_CTRL_SWDPIN0;
4999 ctrl |= E1000_CTRL_SWDPIO0;
5002 if(hw->media_type == e1000_media_type_fiber) {
5003 /* Clear SW Defineable Pin 0 to turn off the LED */
5004 ctrl &= ~E1000_CTRL_SWDPIN0;
5005 ctrl |= E1000_CTRL_SWDPIO0;
5007 /* Set SW Defineable Pin 0 to turn off the LED */
5008 ctrl |= E1000_CTRL_SWDPIN0;
5009 ctrl |= E1000_CTRL_SWDPIO0;
5013 if(hw->media_type == e1000_media_type_fiber) {
5014 /* Set SW Defineable Pin 0 to turn off the LED */
5015 ctrl |= E1000_CTRL_SWDPIN0;
5016 ctrl |= E1000_CTRL_SWDPIO0;
5017 } else if(hw->media_type == e1000_media_type_copper) {
5018 E1000_WRITE_REG(hw, LEDCTL, hw->ledctl_mode1);
5019 return E1000_SUCCESS;
5024 E1000_WRITE_REG(hw, CTRL, ctrl);
5026 return E1000_SUCCESS;
5029 /******************************************************************************
5030 * Clears all hardware statistics counters.
5032 * hw - Struct containing variables accessed by shared code
5033 *****************************************************************************/
5035 e1000_clear_hw_cntrs(struct e1000_hw *hw)
5037 volatile uint32_t temp;
5039 temp = E1000_READ_REG(hw, CRCERRS);
5040 temp = E1000_READ_REG(hw, SYMERRS);
5041 temp = E1000_READ_REG(hw, MPC);
5042 temp = E1000_READ_REG(hw, SCC);
5043 temp = E1000_READ_REG(hw, ECOL);
5044 temp = E1000_READ_REG(hw, MCC);
5045 temp = E1000_READ_REG(hw, LATECOL);
5046 temp = E1000_READ_REG(hw, COLC);
5047 temp = E1000_READ_REG(hw, DC);
5048 temp = E1000_READ_REG(hw, SEC);
5049 temp = E1000_READ_REG(hw, RLEC);
5050 temp = E1000_READ_REG(hw, XONRXC);
5051 temp = E1000_READ_REG(hw, XONTXC);
5052 temp = E1000_READ_REG(hw, XOFFRXC);
5053 temp = E1000_READ_REG(hw, XOFFTXC);
5054 temp = E1000_READ_REG(hw, FCRUC);
5055 temp = E1000_READ_REG(hw, PRC64);
5056 temp = E1000_READ_REG(hw, PRC127);
5057 temp = E1000_READ_REG(hw, PRC255);
5058 temp = E1000_READ_REG(hw, PRC511);
5059 temp = E1000_READ_REG(hw, PRC1023);
5060 temp = E1000_READ_REG(hw, PRC1522);
5061 temp = E1000_READ_REG(hw, GPRC);
5062 temp = E1000_READ_REG(hw, BPRC);
5063 temp = E1000_READ_REG(hw, MPRC);
5064 temp = E1000_READ_REG(hw, GPTC);
5065 temp = E1000_READ_REG(hw, GORCL);
5066 temp = E1000_READ_REG(hw, GORCH);
5067 temp = E1000_READ_REG(hw, GOTCL);
5068 temp = E1000_READ_REG(hw, GOTCH);
5069 temp = E1000_READ_REG(hw, RNBC);
5070 temp = E1000_READ_REG(hw, RUC);
5071 temp = E1000_READ_REG(hw, RFC);
5072 temp = E1000_READ_REG(hw, ROC);
5073 temp = E1000_READ_REG(hw, RJC);
5074 temp = E1000_READ_REG(hw, TORL);
5075 temp = E1000_READ_REG(hw, TORH);
5076 temp = E1000_READ_REG(hw, TOTL);
5077 temp = E1000_READ_REG(hw, TOTH);
5078 temp = E1000_READ_REG(hw, TPR);
5079 temp = E1000_READ_REG(hw, TPT);
5080 temp = E1000_READ_REG(hw, PTC64);
5081 temp = E1000_READ_REG(hw, PTC127);
5082 temp = E1000_READ_REG(hw, PTC255);
5083 temp = E1000_READ_REG(hw, PTC511);
5084 temp = E1000_READ_REG(hw, PTC1023);
5085 temp = E1000_READ_REG(hw, PTC1522);
5086 temp = E1000_READ_REG(hw, MPTC);
5087 temp = E1000_READ_REG(hw, BPTC);
5089 if(hw->mac_type < e1000_82543) return;
5091 temp = E1000_READ_REG(hw, ALGNERRC);
5092 temp = E1000_READ_REG(hw, RXERRC);
5093 temp = E1000_READ_REG(hw, TNCRS);
5094 temp = E1000_READ_REG(hw, CEXTERR);
5095 temp = E1000_READ_REG(hw, TSCTC);
5096 temp = E1000_READ_REG(hw, TSCTFC);
5098 if(hw->mac_type <= e1000_82544) return;
5100 temp = E1000_READ_REG(hw, MGTPRC);
5101 temp = E1000_READ_REG(hw, MGTPDC);
5102 temp = E1000_READ_REG(hw, MGTPTC);
5104 if(hw->mac_type <= e1000_82547_rev_2) return;
5106 temp = E1000_READ_REG(hw, IAC);
5107 temp = E1000_READ_REG(hw, ICRXOC);
5108 temp = E1000_READ_REG(hw, ICRXPTC);
5109 temp = E1000_READ_REG(hw, ICRXATC);
5110 temp = E1000_READ_REG(hw, ICTXPTC);
5111 temp = E1000_READ_REG(hw, ICTXATC);
5112 temp = E1000_READ_REG(hw, ICTXQEC);
5113 temp = E1000_READ_REG(hw, ICTXQMTC);
5114 temp = E1000_READ_REG(hw, ICRXDMTC);
5117 /******************************************************************************
5118 * Resets Adaptive IFS to its default state.
5120 * hw - Struct containing variables accessed by shared code
5122 * Call this after e1000_init_hw. You may override the IFS defaults by setting
5123 * hw->ifs_params_forced to TRUE. However, you must initialize hw->
5124 * current_ifs_val, ifs_min_val, ifs_max_val, ifs_step_size, and ifs_ratio
5125 * before calling this function.
5126 *****************************************************************************/
5128 e1000_reset_adaptive(struct e1000_hw *hw)
5130 DEBUGFUNC("e1000_reset_adaptive");
5132 if(hw->adaptive_ifs) {
5133 if(!hw->ifs_params_forced) {
5134 hw->current_ifs_val = 0;
5135 hw->ifs_min_val = IFS_MIN;
5136 hw->ifs_max_val = IFS_MAX;
5137 hw->ifs_step_size = IFS_STEP;
5138 hw->ifs_ratio = IFS_RATIO;
5140 hw->in_ifs_mode = FALSE;
5141 E1000_WRITE_REG(hw, AIT, 0);
5143 DEBUGOUT("Not in Adaptive IFS mode!\n");
5147 /******************************************************************************
5148 * Called during the callback/watchdog routine to update IFS value based on
5149 * the ratio of transmits to collisions.
5151 * hw - Struct containing variables accessed by shared code
5152 * tx_packets - Number of transmits since last callback
5153 * total_collisions - Number of collisions since last callback
5154 *****************************************************************************/
5156 e1000_update_adaptive(struct e1000_hw *hw)
5158 DEBUGFUNC("e1000_update_adaptive");
5160 if(hw->adaptive_ifs) {
5161 if((hw->collision_delta * hw->ifs_ratio) > hw->tx_packet_delta) {
5162 if(hw->tx_packet_delta > MIN_NUM_XMITS) {
5163 hw->in_ifs_mode = TRUE;
5164 if(hw->current_ifs_val < hw->ifs_max_val) {
5165 if(hw->current_ifs_val == 0)
5166 hw->current_ifs_val = hw->ifs_min_val;
5168 hw->current_ifs_val += hw->ifs_step_size;
5169 E1000_WRITE_REG(hw, AIT, hw->current_ifs_val);
5173 if(hw->in_ifs_mode && (hw->tx_packet_delta <= MIN_NUM_XMITS)) {
5174 hw->current_ifs_val = 0;
5175 hw->in_ifs_mode = FALSE;
5176 E1000_WRITE_REG(hw, AIT, 0);
5180 DEBUGOUT("Not in Adaptive IFS mode!\n");
5184 /******************************************************************************
5185 * Adjusts the statistic counters when a frame is accepted by TBI_ACCEPT
5187 * hw - Struct containing variables accessed by shared code
5188 * frame_len - The length of the frame in question
5189 * mac_addr - The Ethernet destination address of the frame in question
5190 *****************************************************************************/
5192 e1000_tbi_adjust_stats(struct e1000_hw *hw,
5193 struct e1000_hw_stats *stats,
5199 /* First adjust the frame length. */
5201 /* We need to adjust the statistics counters, since the hardware
5202 * counters overcount this packet as a CRC error and undercount
5203 * the packet as a good packet
5205 /* This packet should not be counted as a CRC error. */
5207 /* This packet does count as a Good Packet Received. */
5210 /* Adjust the Good Octets received counters */
5211 carry_bit = 0x80000000 & stats->gorcl;
5212 stats->gorcl += frame_len;
5213 /* If the high bit of Gorcl (the low 32 bits of the Good Octets
5214 * Received Count) was one before the addition,
5215 * AND it is zero after, then we lost the carry out,
5216 * need to add one to Gorch (Good Octets Received Count High).
5217 * This could be simplified if all environments supported
5220 if(carry_bit && ((stats->gorcl & 0x80000000) == 0))
5222 /* Is this a broadcast or multicast? Check broadcast first,
5223 * since the test for a multicast frame will test positive on
5224 * a broadcast frame.
5226 if((mac_addr[0] == (uint8_t) 0xff) && (mac_addr[1] == (uint8_t) 0xff))
5227 /* Broadcast packet */
5229 else if(*mac_addr & 0x01)
5230 /* Multicast packet */
5233 if(frame_len == hw->max_frame_size) {
5234 /* In this case, the hardware has overcounted the number of
5241 /* Adjust the bin counters when the extra byte put the frame in the
5242 * wrong bin. Remember that the frame_len was adjusted above.
5244 if(frame_len == 64) {
5247 } else if(frame_len == 127) {
5250 } else if(frame_len == 255) {
5253 } else if(frame_len == 511) {
5256 } else if(frame_len == 1023) {
5259 } else if(frame_len == 1522) {
5264 /******************************************************************************
5265 * Gets the current PCI bus type, speed, and width of the hardware
5267 * hw - Struct containing variables accessed by shared code
5268 *****************************************************************************/
5270 e1000_get_bus_info(struct e1000_hw *hw)
5274 switch (hw->mac_type) {
5275 case e1000_82542_rev2_0:
5276 case e1000_82542_rev2_1:
5277 hw->bus_type = e1000_bus_type_unknown;
5278 hw->bus_speed = e1000_bus_speed_unknown;
5279 hw->bus_width = e1000_bus_width_unknown;
5284 hw->bus_type = e1000_bus_type_pci_express;
5285 hw->bus_speed = e1000_bus_speed_2500;
5286 hw->bus_width = e1000_bus_width_pciex_4;
5289 status = E1000_READ_REG(hw, STATUS);
5290 hw->bus_type = (status & E1000_STATUS_PCIX_MODE) ?
5291 e1000_bus_type_pcix : e1000_bus_type_pci;
5293 if(hw->device_id == E1000_DEV_ID_82546EB_QUAD_COPPER) {
5294 hw->bus_speed = (hw->bus_type == e1000_bus_type_pci) ?
5295 e1000_bus_speed_66 : e1000_bus_speed_120;
5296 } else if(hw->bus_type == e1000_bus_type_pci) {
5297 hw->bus_speed = (status & E1000_STATUS_PCI66) ?
5298 e1000_bus_speed_66 : e1000_bus_speed_33;
5300 switch (status & E1000_STATUS_PCIX_SPEED) {
5301 case E1000_STATUS_PCIX_SPEED_66:
5302 hw->bus_speed = e1000_bus_speed_66;
5304 case E1000_STATUS_PCIX_SPEED_100:
5305 hw->bus_speed = e1000_bus_speed_100;
5307 case E1000_STATUS_PCIX_SPEED_133:
5308 hw->bus_speed = e1000_bus_speed_133;
5311 hw->bus_speed = e1000_bus_speed_reserved;
5315 hw->bus_width = (status & E1000_STATUS_BUS64) ?
5316 e1000_bus_width_64 : e1000_bus_width_32;
5322 /******************************************************************************
5323 * Reads a value from one of the devices registers using port I/O (as opposed
5324 * memory mapped I/O). Only 82544 and newer devices support port I/O.
5326 * hw - Struct containing variables accessed by shared code
5327 * offset - offset to read from
5328 *****************************************************************************/
5330 e1000_read_reg_io(struct e1000_hw *hw,
5333 unsigned long io_addr = hw->io_base;
5334 unsigned long io_data = hw->io_base + 4;
5336 e1000_io_write(hw, io_addr, offset);
5337 return e1000_io_read(hw, io_data);
5341 /******************************************************************************
5342 * Writes a value to one of the devices registers using port I/O (as opposed to
5343 * memory mapped I/O). Only 82544 and newer devices support port I/O.
5345 * hw - Struct containing variables accessed by shared code
5346 * offset - offset to write to
5347 * value - value to write
5348 *****************************************************************************/
5350 e1000_write_reg_io(struct e1000_hw *hw,
5354 unsigned long io_addr = hw->io_base;
5355 unsigned long io_data = hw->io_base + 4;
5357 e1000_io_write(hw, io_addr, offset);
5358 e1000_io_write(hw, io_data, value);
5362 /******************************************************************************
5363 * Estimates the cable length.
5365 * hw - Struct containing variables accessed by shared code
5366 * min_length - The estimated minimum length
5367 * max_length - The estimated maximum length
5369 * returns: - E1000_ERR_XXX
5372 * This function always returns a ranged length (minimum & maximum).
5373 * So for M88 phy's, this function interprets the one value returned from the
5374 * register to the minimum and maximum range.
5375 * For IGP phy's, the function calculates the range by the AGC registers.
5376 *****************************************************************************/
5378 e1000_get_cable_length(struct e1000_hw *hw,
5379 uint16_t *min_length,
5380 uint16_t *max_length)
5383 uint16_t agc_value = 0;
5384 uint16_t cur_agc, min_agc = IGP01E1000_AGC_LENGTH_TABLE_SIZE;
5385 uint16_t max_agc = 0;
5386 uint16_t i, phy_data;
5387 uint16_t cable_length;
5389 DEBUGFUNC("e1000_get_cable_length");
5391 *min_length = *max_length = 0;
5393 /* Use old method for Phy older than IGP */
5394 if(hw->phy_type == e1000_phy_m88) {
5396 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS,
5400 cable_length = (phy_data & M88E1000_PSSR_CABLE_LENGTH) >>
5401 M88E1000_PSSR_CABLE_LENGTH_SHIFT;
5403 /* Convert the enum value to ranged values */
5404 switch (cable_length) {
5405 case e1000_cable_length_50:
5407 *max_length = e1000_igp_cable_length_50;
5409 case e1000_cable_length_50_80:
5410 *min_length = e1000_igp_cable_length_50;
5411 *max_length = e1000_igp_cable_length_80;
5413 case e1000_cable_length_80_110:
5414 *min_length = e1000_igp_cable_length_80;
5415 *max_length = e1000_igp_cable_length_110;
5417 case e1000_cable_length_110_140:
5418 *min_length = e1000_igp_cable_length_110;
5419 *max_length = e1000_igp_cable_length_140;
5421 case e1000_cable_length_140:
5422 *min_length = e1000_igp_cable_length_140;
5423 *max_length = e1000_igp_cable_length_170;
5426 return -E1000_ERR_PHY;
5429 } else if(hw->phy_type == e1000_phy_igp) { /* For IGP PHY */
5430 uint16_t agc_reg_array[IGP01E1000_PHY_CHANNEL_NUM] =
5431 {IGP01E1000_PHY_AGC_A,
5432 IGP01E1000_PHY_AGC_B,
5433 IGP01E1000_PHY_AGC_C,
5434 IGP01E1000_PHY_AGC_D};
5435 /* Read the AGC registers for all channels */
5436 for(i = 0; i < IGP01E1000_PHY_CHANNEL_NUM; i++) {
5438 ret_val = e1000_read_phy_reg(hw, agc_reg_array[i], &phy_data);
5442 cur_agc = phy_data >> IGP01E1000_AGC_LENGTH_SHIFT;
5444 /* Array bound check. */
5445 if((cur_agc >= IGP01E1000_AGC_LENGTH_TABLE_SIZE - 1) ||
5447 return -E1000_ERR_PHY;
5449 agc_value += cur_agc;
5451 /* Update minimal AGC value. */
5452 if(min_agc > cur_agc)
5456 /* Remove the minimal AGC result for length < 50m */
5457 if(agc_value < IGP01E1000_PHY_CHANNEL_NUM * e1000_igp_cable_length_50) {
5458 agc_value -= min_agc;
5460 /* Get the average length of the remaining 3 channels */
5461 agc_value /= (IGP01E1000_PHY_CHANNEL_NUM - 1);
5463 /* Get the average length of all the 4 channels. */
5464 agc_value /= IGP01E1000_PHY_CHANNEL_NUM;
5467 /* Set the range of the calculated length. */
5468 *min_length = ((e1000_igp_cable_length_table[agc_value] -
5469 IGP01E1000_AGC_RANGE) > 0) ?
5470 (e1000_igp_cable_length_table[agc_value] -
5471 IGP01E1000_AGC_RANGE) : 0;
5472 *max_length = e1000_igp_cable_length_table[agc_value] +
5473 IGP01E1000_AGC_RANGE;
5474 } else if (hw->phy_type == e1000_phy_igp_2) {
5475 uint16_t agc_reg_array[IGP02E1000_PHY_CHANNEL_NUM] =
5476 {IGP02E1000_PHY_AGC_A,
5477 IGP02E1000_PHY_AGC_B,
5478 IGP02E1000_PHY_AGC_C,
5479 IGP02E1000_PHY_AGC_D};
5480 /* Read the AGC registers for all channels */
5481 for (i = 0; i < IGP02E1000_PHY_CHANNEL_NUM; i++) {
5482 ret_val = e1000_read_phy_reg(hw, agc_reg_array[i], &phy_data);
5486 /* Getting bits 15:9, which represent the combination of course and
5487 * fine gain values. The result is a number that can be put into
5488 * the lookup table to obtain the approximate cable length. */
5489 cur_agc = (phy_data >> IGP02E1000_AGC_LENGTH_SHIFT) &
5490 IGP02E1000_AGC_LENGTH_MASK;
5492 /* Remove min & max AGC values from calculation. */
5493 if (e1000_igp_2_cable_length_table[min_agc] > e1000_igp_2_cable_length_table[cur_agc])
5495 if (e1000_igp_2_cable_length_table[max_agc] < e1000_igp_2_cable_length_table[cur_agc])
5498 agc_value += e1000_igp_2_cable_length_table[cur_agc];
5501 agc_value -= (e1000_igp_2_cable_length_table[min_agc] + e1000_igp_2_cable_length_table[max_agc]);
5502 agc_value /= (IGP02E1000_PHY_CHANNEL_NUM - 2);
5504 /* Calculate cable length with the error range of +/- 10 meters. */
5505 *min_length = ((agc_value - IGP02E1000_AGC_RANGE) > 0) ?
5506 (agc_value - IGP02E1000_AGC_RANGE) : 0;
5507 *max_length = agc_value + IGP02E1000_AGC_RANGE;
5510 return E1000_SUCCESS;
5513 /******************************************************************************
5514 * Check the cable polarity
5516 * hw - Struct containing variables accessed by shared code
5517 * polarity - output parameter : 0 - Polarity is not reversed
5518 * 1 - Polarity is reversed.
5520 * returns: - E1000_ERR_XXX
5523 * For phy's older then IGP, this function simply reads the polarity bit in the
5524 * Phy Status register. For IGP phy's, this bit is valid only if link speed is
5525 * 10 Mbps. If the link speed is 100 Mbps there is no polarity so this bit will
5526 * return 0. If the link speed is 1000 Mbps the polarity status is in the
5527 * IGP01E1000_PHY_PCS_INIT_REG.
5528 *****************************************************************************/
5530 e1000_check_polarity(struct e1000_hw *hw,
5536 DEBUGFUNC("e1000_check_polarity");
5538 if(hw->phy_type == e1000_phy_m88) {
5539 /* return the Polarity bit in the Status register. */
5540 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS,
5544 *polarity = (phy_data & M88E1000_PSSR_REV_POLARITY) >>
5545 M88E1000_PSSR_REV_POLARITY_SHIFT;
5546 } else if(hw->phy_type == e1000_phy_igp ||
5547 hw->phy_type == e1000_phy_igp_2) {
5548 /* Read the Status register to check the speed */
5549 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_STATUS,
5554 /* If speed is 1000 Mbps, must read the IGP01E1000_PHY_PCS_INIT_REG to
5555 * find the polarity status */
5556 if((phy_data & IGP01E1000_PSSR_SPEED_MASK) ==
5557 IGP01E1000_PSSR_SPEED_1000MBPS) {
5559 /* Read the GIG initialization PCS register (0x00B4) */
5560 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PCS_INIT_REG,
5565 /* Check the polarity bits */
5566 *polarity = (phy_data & IGP01E1000_PHY_POLARITY_MASK) ? 1 : 0;
5568 /* For 10 Mbps, read the polarity bit in the status register. (for
5569 * 100 Mbps this bit is always 0) */
5570 *polarity = phy_data & IGP01E1000_PSSR_POLARITY_REVERSED;
5573 return E1000_SUCCESS;
5576 /******************************************************************************
5577 * Check if Downshift occured
5579 * hw - Struct containing variables accessed by shared code
5580 * downshift - output parameter : 0 - No Downshift ocured.
5581 * 1 - Downshift ocured.
5583 * returns: - E1000_ERR_XXX
5586 * For phy's older then IGP, this function reads the Downshift bit in the Phy
5587 * Specific Status register. For IGP phy's, it reads the Downgrade bit in the
5588 * Link Health register. In IGP this bit is latched high, so the driver must
5589 * read it immediately after link is established.
5590 *****************************************************************************/
5592 e1000_check_downshift(struct e1000_hw *hw)
5597 DEBUGFUNC("e1000_check_downshift");
5599 if(hw->phy_type == e1000_phy_igp ||
5600 hw->phy_type == e1000_phy_igp_2) {
5601 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_LINK_HEALTH,
5606 hw->speed_downgraded = (phy_data & IGP01E1000_PLHR_SS_DOWNGRADE) ? 1 : 0;
5607 } else if(hw->phy_type == e1000_phy_m88) {
5608 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS,
5613 hw->speed_downgraded = (phy_data & M88E1000_PSSR_DOWNSHIFT) >>
5614 M88E1000_PSSR_DOWNSHIFT_SHIFT;
5617 return E1000_SUCCESS;
5620 /*****************************************************************************
5622 * 82541_rev_2 & 82547_rev_2 have the capability to configure the DSP when a
5623 * gigabit link is achieved to improve link quality.
5625 * hw: Struct containing variables accessed by shared code
5627 * returns: - E1000_ERR_PHY if fail to read/write the PHY
5628 * E1000_SUCCESS at any other case.
5630 ****************************************************************************/
5633 e1000_config_dsp_after_link_change(struct e1000_hw *hw,
5637 uint16_t phy_data, phy_saved_data, speed, duplex, i;
5638 uint16_t dsp_reg_array[IGP01E1000_PHY_CHANNEL_NUM] =
5639 {IGP01E1000_PHY_AGC_PARAM_A,
5640 IGP01E1000_PHY_AGC_PARAM_B,
5641 IGP01E1000_PHY_AGC_PARAM_C,
5642 IGP01E1000_PHY_AGC_PARAM_D};
5643 uint16_t min_length, max_length;
5645 DEBUGFUNC("e1000_config_dsp_after_link_change");
5647 if(hw->phy_type != e1000_phy_igp)
5648 return E1000_SUCCESS;
5651 ret_val = e1000_get_speed_and_duplex(hw, &speed, &duplex);
5653 DEBUGOUT("Error getting link speed and duplex\n");
5657 if(speed == SPEED_1000) {
5659 e1000_get_cable_length(hw, &min_length, &max_length);
5661 if((hw->dsp_config_state == e1000_dsp_config_enabled) &&
5662 min_length >= e1000_igp_cable_length_50) {
5664 for(i = 0; i < IGP01E1000_PHY_CHANNEL_NUM; i++) {
5665 ret_val = e1000_read_phy_reg(hw, dsp_reg_array[i],
5670 phy_data &= ~IGP01E1000_PHY_EDAC_MU_INDEX;
5672 ret_val = e1000_write_phy_reg(hw, dsp_reg_array[i],
5677 hw->dsp_config_state = e1000_dsp_config_activated;
5680 if((hw->ffe_config_state == e1000_ffe_config_enabled) &&
5681 (min_length < e1000_igp_cable_length_50)) {
5683 uint16_t ffe_idle_err_timeout = FFE_IDLE_ERR_COUNT_TIMEOUT_20;
5684 uint32_t idle_errs = 0;
5686 /* clear previous idle error counts */
5687 ret_val = e1000_read_phy_reg(hw, PHY_1000T_STATUS,
5692 for(i = 0; i < ffe_idle_err_timeout; i++) {
5694 ret_val = e1000_read_phy_reg(hw, PHY_1000T_STATUS,
5699 idle_errs += (phy_data & SR_1000T_IDLE_ERROR_CNT);
5700 if(idle_errs > SR_1000T_PHY_EXCESSIVE_IDLE_ERR_COUNT) {
5701 hw->ffe_config_state = e1000_ffe_config_active;
5703 ret_val = e1000_write_phy_reg(hw,
5704 IGP01E1000_PHY_DSP_FFE,
5705 IGP01E1000_PHY_DSP_FFE_CM_CP);
5712 ffe_idle_err_timeout = FFE_IDLE_ERR_COUNT_TIMEOUT_100;
5717 if(hw->dsp_config_state == e1000_dsp_config_activated) {
5718 /* Save off the current value of register 0x2F5B to be restored at
5719 * the end of the routines. */
5720 ret_val = e1000_read_phy_reg(hw, 0x2F5B, &phy_saved_data);
5725 /* Disable the PHY transmitter */
5726 ret_val = e1000_write_phy_reg(hw, 0x2F5B, 0x0003);
5733 ret_val = e1000_write_phy_reg(hw, 0x0000,
5734 IGP01E1000_IEEE_FORCE_GIGA);
5737 for(i = 0; i < IGP01E1000_PHY_CHANNEL_NUM; i++) {
5738 ret_val = e1000_read_phy_reg(hw, dsp_reg_array[i], &phy_data);
5742 phy_data &= ~IGP01E1000_PHY_EDAC_MU_INDEX;
5743 phy_data |= IGP01E1000_PHY_EDAC_SIGN_EXT_9_BITS;
5745 ret_val = e1000_write_phy_reg(hw,dsp_reg_array[i], phy_data);
5750 ret_val = e1000_write_phy_reg(hw, 0x0000,
5751 IGP01E1000_IEEE_RESTART_AUTONEG);
5757 /* Now enable the transmitter */
5758 ret_val = e1000_write_phy_reg(hw, 0x2F5B, phy_saved_data);
5763 hw->dsp_config_state = e1000_dsp_config_enabled;
5766 if(hw->ffe_config_state == e1000_ffe_config_active) {
5767 /* Save off the current value of register 0x2F5B to be restored at
5768 * the end of the routines. */
5769 ret_val = e1000_read_phy_reg(hw, 0x2F5B, &phy_saved_data);
5774 /* Disable the PHY transmitter */
5775 ret_val = e1000_write_phy_reg(hw, 0x2F5B, 0x0003);
5782 ret_val = e1000_write_phy_reg(hw, 0x0000,
5783 IGP01E1000_IEEE_FORCE_GIGA);
5786 ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_DSP_FFE,
5787 IGP01E1000_PHY_DSP_FFE_DEFAULT);
5791 ret_val = e1000_write_phy_reg(hw, 0x0000,
5792 IGP01E1000_IEEE_RESTART_AUTONEG);
5798 /* Now enable the transmitter */
5799 ret_val = e1000_write_phy_reg(hw, 0x2F5B, phy_saved_data);
5804 hw->ffe_config_state = e1000_ffe_config_enabled;
5807 return E1000_SUCCESS;
5810 /*****************************************************************************
5811 * Set PHY to class A mode
5812 * Assumes the following operations will follow to enable the new class mode.
5813 * 1. Do a PHY soft reset
5814 * 2. Restart auto-negotiation or force link.
5816 * hw - Struct containing variables accessed by shared code
5817 ****************************************************************************/
5819 e1000_set_phy_mode(struct e1000_hw *hw)
5822 uint16_t eeprom_data;
5824 DEBUGFUNC("e1000_set_phy_mode");
5826 if((hw->mac_type == e1000_82545_rev_3) &&
5827 (hw->media_type == e1000_media_type_copper)) {
5828 ret_val = e1000_read_eeprom(hw, EEPROM_PHY_CLASS_WORD, 1, &eeprom_data);
5833 if((eeprom_data != EEPROM_RESERVED_WORD) &&
5834 (eeprom_data & EEPROM_PHY_CLASS_A)) {
5835 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x000B);
5838 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, 0x8104);
5842 hw->phy_reset_disable = FALSE;
5846 return E1000_SUCCESS;
5849 /*****************************************************************************
5851 * This function sets the lplu state according to the active flag. When
5852 * activating lplu this function also disables smart speed and vise versa.
5853 * lplu will not be activated unless the device autonegotiation advertisment
5854 * meets standards of either 10 or 10/100 or 10/100/1000 at all duplexes.
5855 * hw: Struct containing variables accessed by shared code
5856 * active - true to enable lplu false to disable lplu.
5858 * returns: - E1000_ERR_PHY if fail to read/write the PHY
5859 * E1000_SUCCESS at any other case.
5861 ****************************************************************************/
5864 e1000_set_d3_lplu_state(struct e1000_hw *hw,
5869 DEBUGFUNC("e1000_set_d3_lplu_state");
5871 if(hw->phy_type != e1000_phy_igp && hw->phy_type != e1000_phy_igp_2)
5872 return E1000_SUCCESS;
5874 /* During driver activity LPLU should not be used or it will attain link
5875 * from the lowest speeds starting from 10Mbps. The capability is used for
5876 * Dx transitions and states */
5877 if(hw->mac_type == e1000_82541_rev_2 || hw->mac_type == e1000_82547_rev_2) {
5878 ret_val = e1000_read_phy_reg(hw, IGP01E1000_GMII_FIFO, &phy_data);
5882 ret_val = e1000_read_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT, &phy_data);
5888 if(hw->mac_type == e1000_82541_rev_2 ||
5889 hw->mac_type == e1000_82547_rev_2) {
5890 phy_data &= ~IGP01E1000_GMII_FLEX_SPD;
5891 ret_val = e1000_write_phy_reg(hw, IGP01E1000_GMII_FIFO, phy_data);
5895 phy_data &= ~IGP02E1000_PM_D3_LPLU;
5896 ret_val = e1000_write_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT,
5902 /* LPLU and SmartSpeed are mutually exclusive. LPLU is used during
5903 * Dx states where the power conservation is most important. During
5904 * driver activity we should enable SmartSpeed, so performance is
5906 if (hw->smart_speed == e1000_smart_speed_on) {
5907 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
5912 phy_data |= IGP01E1000_PSCFR_SMART_SPEED;
5913 ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
5917 } else if (hw->smart_speed == e1000_smart_speed_off) {
5918 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
5923 phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED;
5924 ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
5930 } else if((hw->autoneg_advertised == AUTONEG_ADVERTISE_SPEED_DEFAULT) ||
5931 (hw->autoneg_advertised == AUTONEG_ADVERTISE_10_ALL ) ||
5932 (hw->autoneg_advertised == AUTONEG_ADVERTISE_10_100_ALL)) {
5934 if(hw->mac_type == e1000_82541_rev_2 ||
5935 hw->mac_type == e1000_82547_rev_2) {
5936 phy_data |= IGP01E1000_GMII_FLEX_SPD;
5937 ret_val = e1000_write_phy_reg(hw, IGP01E1000_GMII_FIFO, phy_data);
5941 phy_data |= IGP02E1000_PM_D3_LPLU;
5942 ret_val = e1000_write_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT,
5948 /* When LPLU is enabled we should disable SmartSpeed */
5949 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, &phy_data);
5953 phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED;
5954 ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, phy_data);
5959 return E1000_SUCCESS;
5962 /*****************************************************************************
5964 * This function sets the lplu d0 state according to the active flag. When
5965 * activating lplu this function also disables smart speed and vise versa.
5966 * lplu will not be activated unless the device autonegotiation advertisment
5967 * meets standards of either 10 or 10/100 or 10/100/1000 at all duplexes.
5968 * hw: Struct containing variables accessed by shared code
5969 * active - true to enable lplu false to disable lplu.
5971 * returns: - E1000_ERR_PHY if fail to read/write the PHY
5972 * E1000_SUCCESS at any other case.
5974 ****************************************************************************/
5977 e1000_set_d0_lplu_state(struct e1000_hw *hw,
5982 DEBUGFUNC("e1000_set_d0_lplu_state");
5984 if(hw->mac_type <= e1000_82547_rev_2)
5985 return E1000_SUCCESS;
5987 ret_val = e1000_read_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT, &phy_data);
5992 phy_data &= ~IGP02E1000_PM_D0_LPLU;
5993 ret_val = e1000_write_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT, phy_data);
5997 /* LPLU and SmartSpeed are mutually exclusive. LPLU is used during
5998 * Dx states where the power conservation is most important. During
5999 * driver activity we should enable SmartSpeed, so performance is
6001 if (hw->smart_speed == e1000_smart_speed_on) {
6002 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
6007 phy_data |= IGP01E1000_PSCFR_SMART_SPEED;
6008 ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
6012 } else if (hw->smart_speed == e1000_smart_speed_off) {
6013 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
6018 phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED;
6019 ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
6028 phy_data |= IGP02E1000_PM_D0_LPLU;
6029 ret_val = e1000_write_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT, phy_data);
6033 /* When LPLU is enabled we should disable SmartSpeed */
6034 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, &phy_data);
6038 phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED;
6039 ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, phy_data);
6044 return E1000_SUCCESS;
6047 /******************************************************************************
6048 * Change VCO speed register to improve Bit Error Rate performance of SERDES.
6050 * hw - Struct containing variables accessed by shared code
6051 *****************************************************************************/
6053 e1000_set_vco_speed(struct e1000_hw *hw)
6056 uint16_t default_page = 0;
6059 DEBUGFUNC("e1000_set_vco_speed");
6061 switch(hw->mac_type) {
6062 case e1000_82545_rev_3:
6063 case e1000_82546_rev_3:
6066 return E1000_SUCCESS;
6069 /* Set PHY register 30, page 5, bit 8 to 0 */
6071 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, &default_page);
6075 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0005);
6079 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, &phy_data);
6083 phy_data &= ~M88E1000_PHY_VCO_REG_BIT8;
6084 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, phy_data);
6088 /* Set PHY register 30, page 4, bit 11 to 1 */
6090 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0004);
6094 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, &phy_data);
6098 phy_data |= M88E1000_PHY_VCO_REG_BIT11;
6099 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, phy_data);
6103 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, default_page);
6107 return E1000_SUCCESS;
6111 /*****************************************************************************
6112 * This function reads the cookie from ARC ram.
6114 * returns: - E1000_SUCCESS .
6115 ****************************************************************************/
6117 e1000_host_if_read_cookie(struct e1000_hw * hw, uint8_t *buffer)
6120 uint32_t offset = E1000_MNG_DHCP_COOKIE_OFFSET;
6121 uint8_t length = E1000_MNG_DHCP_COOKIE_LENGTH;
6123 length = (length >> 2);
6124 offset = (offset >> 2);
6126 for (i = 0; i < length; i++) {
6127 *((uint32_t *) buffer + i) =
6128 E1000_READ_REG_ARRAY_DWORD(hw, HOST_IF, offset + i);
6130 return E1000_SUCCESS;
6134 /*****************************************************************************
6135 * This function checks whether the HOST IF is enabled for command operaton
6136 * and also checks whether the previous command is completed.
6137 * It busy waits in case of previous command is not completed.
6139 * returns: - E1000_ERR_HOST_INTERFACE_COMMAND in case if is not ready or
6141 * - E1000_SUCCESS for success.
6142 ****************************************************************************/
6144 e1000_mng_enable_host_if(struct e1000_hw * hw)
6149 /* Check that the host interface is enabled. */
6150 hicr = E1000_READ_REG(hw, HICR);
6151 if ((hicr & E1000_HICR_EN) == 0) {
6152 DEBUGOUT("E1000_HOST_EN bit disabled.\n");
6153 return -E1000_ERR_HOST_INTERFACE_COMMAND;
6155 /* check the previous command is completed */
6156 for (i = 0; i < E1000_MNG_DHCP_COMMAND_TIMEOUT; i++) {
6157 hicr = E1000_READ_REG(hw, HICR);
6158 if (!(hicr & E1000_HICR_C))
6163 if (i == E1000_MNG_DHCP_COMMAND_TIMEOUT) {
6164 DEBUGOUT("Previous command timeout failed .\n");
6165 return -E1000_ERR_HOST_INTERFACE_COMMAND;
6167 return E1000_SUCCESS;
6170 /*****************************************************************************
6171 * This function writes the buffer content at the offset given on the host if.
6172 * It also does alignment considerations to do the writes in most efficient way.
6173 * Also fills up the sum of the buffer in *buffer parameter.
6175 * returns - E1000_SUCCESS for success.
6176 ****************************************************************************/
6178 e1000_mng_host_if_write(struct e1000_hw * hw, uint8_t *buffer,
6179 uint16_t length, uint16_t offset, uint8_t *sum)
6182 uint8_t *bufptr = buffer;
6184 uint16_t remaining, i, j, prev_bytes;
6186 /* sum = only sum of the data and it is not checksum */
6188 if (length == 0 || offset + length > E1000_HI_MAX_MNG_DATA_LENGTH) {
6189 return -E1000_ERR_PARAM;
6192 tmp = (uint8_t *)&data;
6193 prev_bytes = offset & 0x3;
6198 data = E1000_READ_REG_ARRAY_DWORD(hw, HOST_IF, offset);
6199 for (j = prev_bytes; j < sizeof(uint32_t); j++) {
6200 *(tmp + j) = *bufptr++;
6203 E1000_WRITE_REG_ARRAY_DWORD(hw, HOST_IF, offset, data);
6204 length -= j - prev_bytes;
6208 remaining = length & 0x3;
6209 length -= remaining;
6211 /* Calculate length in DWORDs */
6214 /* The device driver writes the relevant command block into the
6216 for (i = 0; i < length; i++) {
6217 for (j = 0; j < sizeof(uint32_t); j++) {
6218 *(tmp + j) = *bufptr++;
6222 E1000_WRITE_REG_ARRAY_DWORD(hw, HOST_IF, offset + i, data);
6225 for (j = 0; j < sizeof(uint32_t); j++) {
6227 *(tmp + j) = *bufptr++;
6233 E1000_WRITE_REG_ARRAY_DWORD(hw, HOST_IF, offset + i, data);
6236 return E1000_SUCCESS;
6240 /*****************************************************************************
6241 * This function writes the command header after does the checksum calculation.
6243 * returns - E1000_SUCCESS for success.
6244 ****************************************************************************/
6246 e1000_mng_write_cmd_header(struct e1000_hw * hw,
6247 struct e1000_host_mng_command_header * hdr)
6253 /* Write the whole command header structure which includes sum of
6256 uint16_t length = sizeof(struct e1000_host_mng_command_header);
6258 sum = hdr->checksum;
6261 buffer = (uint8_t *) hdr;
6266 hdr->checksum = 0 - sum;
6269 /* The device driver writes the relevant command block into the ram area. */
6270 for (i = 0; i < length; i++)
6271 E1000_WRITE_REG_ARRAY_DWORD(hw, HOST_IF, i, *((uint32_t *) hdr + i));
6273 return E1000_SUCCESS;
6277 /*****************************************************************************
6278 * This function indicates to ARC that a new command is pending which completes
6279 * one write operation by the driver.
6281 * returns - E1000_SUCCESS for success.
6282 ****************************************************************************/
6284 e1000_mng_write_commit(
6285 struct e1000_hw * hw)
6289 hicr = E1000_READ_REG(hw, HICR);
6290 /* Setting this bit tells the ARC that a new command is pending. */
6291 E1000_WRITE_REG(hw, HICR, hicr | E1000_HICR_C);
6293 return E1000_SUCCESS;
6297 /*****************************************************************************
6298 * This function checks the mode of the firmware.
6300 * returns - TRUE when the mode is IAMT or FALSE.
6301 ****************************************************************************/
6303 e1000_check_mng_mode(
6304 struct e1000_hw *hw)
6308 fwsm = E1000_READ_REG(hw, FWSM);
6310 if((fwsm & E1000_FWSM_MODE_MASK) ==
6311 (E1000_MNG_IAMT_MODE << E1000_FWSM_MODE_SHIFT))
6318 /*****************************************************************************
6319 * This function writes the dhcp info .
6320 ****************************************************************************/
6322 e1000_mng_write_dhcp_info(struct e1000_hw * hw, uint8_t *buffer,
6326 struct e1000_host_mng_command_header hdr;
6328 hdr.command_id = E1000_MNG_DHCP_TX_PAYLOAD_CMD;
6329 hdr.command_length = length;
6334 ret_val = e1000_mng_enable_host_if(hw);
6335 if (ret_val == E1000_SUCCESS) {
6336 ret_val = e1000_mng_host_if_write(hw, buffer, length, sizeof(hdr),
6338 if (ret_val == E1000_SUCCESS) {
6339 ret_val = e1000_mng_write_cmd_header(hw, &hdr);
6340 if (ret_val == E1000_SUCCESS)
6341 ret_val = e1000_mng_write_commit(hw);
6348 /*****************************************************************************
6349 * This function calculates the checksum.
6351 * returns - checksum of buffer contents.
6352 ****************************************************************************/
6354 e1000_calculate_mng_checksum(char *buffer, uint32_t length)
6362 for (i=0; i < length; i++)
6365 return (uint8_t) (0 - sum);
6368 /*****************************************************************************
6369 * This function checks whether tx pkt filtering needs to be enabled or not.
6371 * returns - TRUE for packet filtering or FALSE.
6372 ****************************************************************************/
6374 e1000_enable_tx_pkt_filtering(struct e1000_hw *hw)
6376 /* called in init as well as watchdog timer functions */
6378 int32_t ret_val, checksum;
6379 boolean_t tx_filter = FALSE;
6380 struct e1000_host_mng_dhcp_cookie *hdr = &(hw->mng_cookie);
6381 uint8_t *buffer = (uint8_t *) &(hw->mng_cookie);
6383 if (e1000_check_mng_mode(hw)) {
6384 ret_val = e1000_mng_enable_host_if(hw);
6385 if (ret_val == E1000_SUCCESS) {
6386 ret_val = e1000_host_if_read_cookie(hw, buffer);
6387 if (ret_val == E1000_SUCCESS) {
6388 checksum = hdr->checksum;
6390 if ((hdr->signature == E1000_IAMT_SIGNATURE) &&
6391 checksum == e1000_calculate_mng_checksum((char *)buffer,
6392 E1000_MNG_DHCP_COOKIE_LENGTH)) {
6394 E1000_MNG_DHCP_COOKIE_STATUS_PARSING_SUPPORT)
6403 hw->tx_pkt_filtering = tx_filter;
6407 /******************************************************************************
6408 * Verifies the hardware needs to allow ARPs to be processed by the host
6410 * hw - Struct containing variables accessed by shared code
6412 * returns: - TRUE/FALSE
6414 *****************************************************************************/
6416 e1000_enable_mng_pass_thru(struct e1000_hw *hw)
6419 uint32_t fwsm, factps;
6421 if (hw->asf_firmware_present) {
6422 manc = E1000_READ_REG(hw, MANC);
6424 if (!(manc & E1000_MANC_RCV_TCO_EN) ||
6425 !(manc & E1000_MANC_EN_MAC_ADDR_FILTER))
6427 if (e1000_arc_subsystem_valid(hw) == TRUE) {
6428 fwsm = E1000_READ_REG(hw, FWSM);
6429 factps = E1000_READ_REG(hw, FACTPS);
6431 if (((fwsm & E1000_FWSM_MODE_MASK) ==
6432 (e1000_mng_mode_pt << E1000_FWSM_MODE_SHIFT)) &&
6433 (factps & E1000_FACTPS_MNGCG))
6436 if ((manc & E1000_MANC_SMBUS_EN) && !(manc & E1000_MANC_ASF_EN))
6443 e1000_polarity_reversal_workaround(struct e1000_hw *hw)
6446 uint16_t mii_status_reg;
6449 /* Polarity reversal workaround for forced 10F/10H links. */
6451 /* Disable the transmitter on the PHY */
6453 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0019);
6456 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, 0xFFFF);
6460 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0000);
6464 /* This loop will early-out if the NO link condition has been met. */
6465 for(i = PHY_FORCE_TIME; i > 0; i--) {
6466 /* Read the MII Status Register and wait for Link Status bit
6470 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg);
6474 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg);
6478 if((mii_status_reg & ~MII_SR_LINK_STATUS) == 0) break;
6479 msec_delay_irq(100);
6482 /* Recommended delay time after link has been lost */
6483 msec_delay_irq(1000);
6485 /* Now we will re-enable th transmitter on the PHY */
6487 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0019);
6491 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, 0xFFF0);
6495 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, 0xFF00);
6499 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, 0x0000);
6503 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0000);
6507 /* This loop will early-out if the link condition has been met. */
6508 for(i = PHY_FORCE_TIME; i > 0; i--) {
6509 /* Read the MII Status Register and wait for Link Status bit
6513 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg);
6517 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg);
6521 if(mii_status_reg & MII_SR_LINK_STATUS) break;
6522 msec_delay_irq(100);
6524 return E1000_SUCCESS;
6527 /***************************************************************************
6529 * Disables PCI-Express master access.
6531 * hw: Struct containing variables accessed by shared code
6535 ***************************************************************************/
6537 e1000_set_pci_express_master_disable(struct e1000_hw *hw)
6541 DEBUGFUNC("e1000_set_pci_express_master_disable");
6543 if (hw->bus_type != e1000_bus_type_pci_express)
6546 ctrl = E1000_READ_REG(hw, CTRL);
6547 ctrl |= E1000_CTRL_GIO_MASTER_DISABLE;
6548 E1000_WRITE_REG(hw, CTRL, ctrl);
6552 /***************************************************************************
6554 * Enables PCI-Express master access.
6556 * hw: Struct containing variables accessed by shared code
6560 ***************************************************************************/
6562 e1000_enable_pciex_master(struct e1000_hw *hw)
6566 DEBUGFUNC("e1000_enable_pciex_master");
6568 if (hw->bus_type != e1000_bus_type_pci_express)
6571 ctrl = E1000_READ_REG(hw, CTRL);
6572 ctrl &= ~E1000_CTRL_GIO_MASTER_DISABLE;
6573 E1000_WRITE_REG(hw, CTRL, ctrl);
6577 /*******************************************************************************
6579 * Disables PCI-Express master access and verifies there are no pending requests
6581 * hw: Struct containing variables accessed by shared code
6583 * returns: - E1000_ERR_MASTER_REQUESTS_PENDING if master disable bit hasn't
6584 * caused the master requests to be disabled.
6585 * E1000_SUCCESS master requests disabled.
6587 ******************************************************************************/
6589 e1000_disable_pciex_master(struct e1000_hw *hw)
6591 int32_t timeout = MASTER_DISABLE_TIMEOUT; /* 80ms */
6593 DEBUGFUNC("e1000_disable_pciex_master");
6595 if (hw->bus_type != e1000_bus_type_pci_express)
6596 return E1000_SUCCESS;
6598 e1000_set_pci_express_master_disable(hw);
6601 if(!(E1000_READ_REG(hw, STATUS) & E1000_STATUS_GIO_MASTER_ENABLE))
6609 DEBUGOUT("Master requests are pending.\n");
6610 return -E1000_ERR_MASTER_REQUESTS_PENDING;
6613 return E1000_SUCCESS;
6616 /*******************************************************************************
6618 * Check for EEPROM Auto Read bit done.
6620 * hw: Struct containing variables accessed by shared code
6622 * returns: - E1000_ERR_RESET if fail to reset MAC
6623 * E1000_SUCCESS at any other case.
6625 ******************************************************************************/
6627 e1000_get_auto_rd_done(struct e1000_hw *hw)
6629 int32_t timeout = AUTO_READ_DONE_TIMEOUT;
6631 DEBUGFUNC("e1000_get_auto_rd_done");
6633 switch (hw->mac_type) {
6641 if (E1000_READ_REG(hw, EECD) & E1000_EECD_AUTO_RD) break;
6647 DEBUGOUT("Auto read by HW from EEPROM has not completed.\n");
6648 return -E1000_ERR_RESET;
6653 return E1000_SUCCESS;
6656 /***************************************************************************
6657 * Checks if the PHY configuration is done
6659 * hw: Struct containing variables accessed by shared code
6661 * returns: - E1000_ERR_RESET if fail to reset MAC
6662 * E1000_SUCCESS at any other case.
6664 ***************************************************************************/
6666 e1000_get_phy_cfg_done(struct e1000_hw *hw)
6668 int32_t timeout = PHY_CFG_TIMEOUT;
6669 uint32_t cfg_mask = E1000_EEPROM_CFG_DONE;
6671 DEBUGFUNC("e1000_get_phy_cfg_done");
6673 switch (hw->mac_type) {
6680 if (E1000_READ_REG(hw, EEMNGCTL) & cfg_mask)
6688 DEBUGOUT("MNG configuration cycle has not completed.\n");
6689 return -E1000_ERR_RESET;
6694 return E1000_SUCCESS;
6697 /***************************************************************************
6699 * Using the combination of SMBI and SWESMBI semaphore bits when resetting
6700 * adapter or Eeprom access.
6702 * hw: Struct containing variables accessed by shared code
6704 * returns: - E1000_ERR_EEPROM if fail to access EEPROM.
6705 * E1000_SUCCESS at any other case.
6707 ***************************************************************************/
6709 e1000_get_hw_eeprom_semaphore(struct e1000_hw *hw)
6714 DEBUGFUNC("e1000_get_hw_eeprom_semaphore");
6716 if(!hw->eeprom_semaphore_present)
6717 return E1000_SUCCESS;
6720 /* Get the FW semaphore. */
6721 timeout = hw->eeprom.word_size + 1;
6723 swsm = E1000_READ_REG(hw, SWSM);
6724 swsm |= E1000_SWSM_SWESMBI;
6725 E1000_WRITE_REG(hw, SWSM, swsm);
6726 /* if we managed to set the bit we got the semaphore. */
6727 swsm = E1000_READ_REG(hw, SWSM);
6728 if(swsm & E1000_SWSM_SWESMBI)
6736 /* Release semaphores */
6737 e1000_put_hw_eeprom_semaphore(hw);
6738 DEBUGOUT("Driver can't access the Eeprom - SWESMBI bit is set.\n");
6739 return -E1000_ERR_EEPROM;
6742 return E1000_SUCCESS;
6745 /***************************************************************************
6746 * This function clears HW semaphore bits.
6748 * hw: Struct containing variables accessed by shared code
6752 ***************************************************************************/
6754 e1000_put_hw_eeprom_semaphore(struct e1000_hw *hw)
6758 DEBUGFUNC("e1000_put_hw_eeprom_semaphore");
6760 if(!hw->eeprom_semaphore_present)
6763 swsm = E1000_READ_REG(hw, SWSM);
6764 swsm &= ~(E1000_SWSM_SWESMBI);
6765 E1000_WRITE_REG(hw, SWSM, swsm);
6768 /******************************************************************************
6769 * Checks if PHY reset is blocked due to SOL/IDER session, for example.
6770 * Returning E1000_BLK_PHY_RESET isn't necessarily an error. But it's up to
6771 * the caller to figure out how to deal with it.
6773 * hw - Struct containing variables accessed by shared code
6775 * returns: - E1000_BLK_PHY_RESET
6778 *****************************************************************************/
6780 e1000_check_phy_reset_block(struct e1000_hw *hw)
6783 if(hw->mac_type > e1000_82547_rev_2)
6784 manc = E1000_READ_REG(hw, MANC);
6785 return (manc & E1000_MANC_BLK_PHY_RST_ON_IDE) ?
6786 E1000_BLK_PHY_RESET : E1000_SUCCESS;
6790 e1000_arc_subsystem_valid(struct e1000_hw *hw)
6794 /* On 8257x silicon, registers in the range of 0x8800 - 0x8FFC
6795 * may not be provided a DMA clock when no manageability features are
6796 * enabled. We do not want to perform any reads/writes to these registers
6797 * if this is the case. We read FWSM to determine the manageability mode.
6799 switch (hw->mac_type) {
6803 fwsm = E1000_READ_REG(hw, FWSM);
6804 if((fwsm & E1000_FWSM_MODE_MASK) != 0)