1 /* bnx2x_main.c: Broadcom Everest network driver.
3 * Copyright (c) 2007-2008 Broadcom Corporation
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation.
9 * Maintained by: Eilon Greenstein <eilong@broadcom.com>
10 * Written by: Eliezer Tamir
11 * Based on code from Michael Chan's bnx2 driver
12 * UDP CSUM errata workaround by Arik Gendelman
13 * Slowpath rework by Vladislav Zolotarov
14 * Statistics and Link management by Yitchak Gertner
18 #include <linux/module.h>
19 #include <linux/moduleparam.h>
20 #include <linux/kernel.h>
21 #include <linux/device.h> /* for dev_info() */
22 #include <linux/timer.h>
23 #include <linux/errno.h>
24 #include <linux/ioport.h>
25 #include <linux/slab.h>
26 #include <linux/vmalloc.h>
27 #include <linux/interrupt.h>
28 #include <linux/pci.h>
29 #include <linux/init.h>
30 #include <linux/netdevice.h>
31 #include <linux/etherdevice.h>
32 #include <linux/skbuff.h>
33 #include <linux/dma-mapping.h>
34 #include <linux/bitops.h>
35 #include <linux/irq.h>
36 #include <linux/delay.h>
37 #include <asm/byteorder.h>
38 #include <linux/time.h>
39 #include <linux/ethtool.h>
40 #include <linux/mii.h>
41 #ifdef NETIF_F_HW_VLAN_TX
42 #include <linux/if_vlan.h>
46 #include <net/checksum.h>
47 #include <linux/version.h>
48 #include <net/ip6_checksum.h>
49 #include <linux/workqueue.h>
50 #include <linux/crc32.h>
51 #include <linux/crc32c.h>
52 #include <linux/prefetch.h>
53 #include <linux/zlib.h>
56 #include "bnx2x_reg.h"
57 #include "bnx2x_fw_defs.h"
58 #include "bnx2x_hsi.h"
59 #include "bnx2x_link.h"
61 #include "bnx2x_init.h"
63 #define DRV_MODULE_VERSION "1.45.6"
64 #define DRV_MODULE_RELDATE "2008/06/23"
65 #define BNX2X_BC_VER 0x040200
67 /* Time in jiffies before concluding the transmitter is hung */
68 #define TX_TIMEOUT (5*HZ)
70 static char version[] __devinitdata =
71 "Broadcom NetXtreme II 5771x 10Gigabit Ethernet Driver "
72 DRV_MODULE_NAME " " DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")\n";
74 MODULE_AUTHOR("Eliezer Tamir");
75 MODULE_DESCRIPTION("Broadcom NetXtreme II BCM57710 Driver");
76 MODULE_LICENSE("GPL");
77 MODULE_VERSION(DRV_MODULE_VERSION);
79 static int disable_tpa;
83 static int load_count[3]; /* 0-common, 1-port0, 2-port1 */
86 module_param(disable_tpa, int, 0);
87 module_param(use_inta, int, 0);
88 module_param(poll, int, 0);
89 module_param(debug, int, 0);
90 MODULE_PARM_DESC(disable_tpa, "disable the TPA (LRO) feature");
91 MODULE_PARM_DESC(use_inta, "use INT#A instead of MSI-X");
92 MODULE_PARM_DESC(poll, "use polling (for debug)");
93 MODULE_PARM_DESC(debug, "default debug msglevel");
96 module_param(use_multi, int, 0);
97 MODULE_PARM_DESC(use_multi, "use per-CPU queues");
100 enum bnx2x_board_type {
106 /* indexed by board_type, above */
109 } board_info[] __devinitdata = {
110 { "Broadcom NetXtreme II BCM57710 XGb" },
111 { "Broadcom NetXtreme II BCM57711 XGb" },
112 { "Broadcom NetXtreme II BCM57711E XGb" }
116 static const struct pci_device_id bnx2x_pci_tbl[] = {
117 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_57710,
118 PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM57710 },
119 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_57711,
120 PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM57711 },
121 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_57711E,
122 PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM57711E },
126 MODULE_DEVICE_TABLE(pci, bnx2x_pci_tbl);
128 /****************************************************************************
129 * General service functions
130 ****************************************************************************/
133 * locking is done by mcp
135 static void bnx2x_reg_wr_ind(struct bnx2x *bp, u32 addr, u32 val)
137 pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS, addr);
138 pci_write_config_dword(bp->pdev, PCICFG_GRC_DATA, val);
139 pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS,
140 PCICFG_VENDOR_ID_OFFSET);
143 static u32 bnx2x_reg_rd_ind(struct bnx2x *bp, u32 addr)
147 pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS, addr);
148 pci_read_config_dword(bp->pdev, PCICFG_GRC_DATA, &val);
149 pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS,
150 PCICFG_VENDOR_ID_OFFSET);
155 static const u32 dmae_reg_go_c[] = {
156 DMAE_REG_GO_C0, DMAE_REG_GO_C1, DMAE_REG_GO_C2, DMAE_REG_GO_C3,
157 DMAE_REG_GO_C4, DMAE_REG_GO_C5, DMAE_REG_GO_C6, DMAE_REG_GO_C7,
158 DMAE_REG_GO_C8, DMAE_REG_GO_C9, DMAE_REG_GO_C10, DMAE_REG_GO_C11,
159 DMAE_REG_GO_C12, DMAE_REG_GO_C13, DMAE_REG_GO_C14, DMAE_REG_GO_C15
162 /* copy command into DMAE command memory and set DMAE command go */
163 static void bnx2x_post_dmae(struct bnx2x *bp, struct dmae_command *dmae,
169 cmd_offset = (DMAE_REG_CMD_MEM + sizeof(struct dmae_command) * idx);
170 for (i = 0; i < (sizeof(struct dmae_command)/4); i++) {
171 REG_WR(bp, cmd_offset + i*4, *(((u32 *)dmae) + i));
173 DP(BNX2X_MSG_OFF, "DMAE cmd[%d].%d (0x%08x) : 0x%08x\n",
174 idx, i, cmd_offset + i*4, *(((u32 *)dmae) + i));
176 REG_WR(bp, dmae_reg_go_c[idx], 1);
179 void bnx2x_write_dmae(struct bnx2x *bp, dma_addr_t dma_addr, u32 dst_addr,
182 struct dmae_command *dmae = &bp->init_dmae;
183 u32 *wb_comp = bnx2x_sp(bp, wb_comp);
186 if (!bp->dmae_ready) {
187 u32 *data = bnx2x_sp(bp, wb_data[0]);
189 DP(BNX2X_MSG_OFF, "DMAE is not ready (dst_addr %08x len32 %d)"
190 " using indirect\n", dst_addr, len32);
191 bnx2x_init_ind_wr(bp, dst_addr, data, len32);
195 mutex_lock(&bp->dmae_mutex);
197 memset(dmae, 0, sizeof(struct dmae_command));
199 dmae->opcode = (DMAE_CMD_SRC_PCI | DMAE_CMD_DST_GRC |
200 DMAE_CMD_C_DST_PCI | DMAE_CMD_C_ENABLE |
201 DMAE_CMD_SRC_RESET | DMAE_CMD_DST_RESET |
203 DMAE_CMD_ENDIANITY_B_DW_SWAP |
205 DMAE_CMD_ENDIANITY_DW_SWAP |
207 (BP_PORT(bp) ? DMAE_CMD_PORT_1 : DMAE_CMD_PORT_0) |
208 (BP_E1HVN(bp) << DMAE_CMD_E1HVN_SHIFT));
209 dmae->src_addr_lo = U64_LO(dma_addr);
210 dmae->src_addr_hi = U64_HI(dma_addr);
211 dmae->dst_addr_lo = dst_addr >> 2;
212 dmae->dst_addr_hi = 0;
214 dmae->comp_addr_lo = U64_LO(bnx2x_sp_mapping(bp, wb_comp));
215 dmae->comp_addr_hi = U64_HI(bnx2x_sp_mapping(bp, wb_comp));
216 dmae->comp_val = DMAE_COMP_VAL;
218 DP(BNX2X_MSG_OFF, "dmae: opcode 0x%08x\n"
219 DP_LEVEL "src_addr [%x:%08x] len [%d *4] "
220 "dst_addr [%x:%08x (%08x)]\n"
221 DP_LEVEL "comp_addr [%x:%08x] comp_val 0x%08x\n",
222 dmae->opcode, dmae->src_addr_hi, dmae->src_addr_lo,
223 dmae->len, dmae->dst_addr_hi, dmae->dst_addr_lo, dst_addr,
224 dmae->comp_addr_hi, dmae->comp_addr_lo, dmae->comp_val);
225 DP(BNX2X_MSG_OFF, "data [0x%08x 0x%08x 0x%08x 0x%08x]\n",
226 bp->slowpath->wb_data[0], bp->slowpath->wb_data[1],
227 bp->slowpath->wb_data[2], bp->slowpath->wb_data[3]);
231 bnx2x_post_dmae(bp, dmae, INIT_DMAE_C(bp));
235 while (*wb_comp != DMAE_COMP_VAL) {
236 DP(BNX2X_MSG_OFF, "wb_comp 0x%08x\n", *wb_comp);
238 /* adjust delay for emulation/FPGA */
239 if (CHIP_REV_IS_SLOW(bp))
245 BNX2X_ERR("dmae timeout!\n");
251 mutex_unlock(&bp->dmae_mutex);
254 void bnx2x_read_dmae(struct bnx2x *bp, u32 src_addr, u32 len32)
256 struct dmae_command *dmae = &bp->init_dmae;
257 u32 *wb_comp = bnx2x_sp(bp, wb_comp);
260 if (!bp->dmae_ready) {
261 u32 *data = bnx2x_sp(bp, wb_data[0]);
264 DP(BNX2X_MSG_OFF, "DMAE is not ready (src_addr %08x len32 %d)"
265 " using indirect\n", src_addr, len32);
266 for (i = 0; i < len32; i++)
267 data[i] = bnx2x_reg_rd_ind(bp, src_addr + i*4);
271 mutex_lock(&bp->dmae_mutex);
273 memset(bnx2x_sp(bp, wb_data[0]), 0, sizeof(u32) * 4);
274 memset(dmae, 0, sizeof(struct dmae_command));
276 dmae->opcode = (DMAE_CMD_SRC_GRC | DMAE_CMD_DST_PCI |
277 DMAE_CMD_C_DST_PCI | DMAE_CMD_C_ENABLE |
278 DMAE_CMD_SRC_RESET | DMAE_CMD_DST_RESET |
280 DMAE_CMD_ENDIANITY_B_DW_SWAP |
282 DMAE_CMD_ENDIANITY_DW_SWAP |
284 (BP_PORT(bp) ? DMAE_CMD_PORT_1 : DMAE_CMD_PORT_0) |
285 (BP_E1HVN(bp) << DMAE_CMD_E1HVN_SHIFT));
286 dmae->src_addr_lo = src_addr >> 2;
287 dmae->src_addr_hi = 0;
288 dmae->dst_addr_lo = U64_LO(bnx2x_sp_mapping(bp, wb_data));
289 dmae->dst_addr_hi = U64_HI(bnx2x_sp_mapping(bp, wb_data));
291 dmae->comp_addr_lo = U64_LO(bnx2x_sp_mapping(bp, wb_comp));
292 dmae->comp_addr_hi = U64_HI(bnx2x_sp_mapping(bp, wb_comp));
293 dmae->comp_val = DMAE_COMP_VAL;
295 DP(BNX2X_MSG_OFF, "dmae: opcode 0x%08x\n"
296 DP_LEVEL "src_addr [%x:%08x] len [%d *4] "
297 "dst_addr [%x:%08x (%08x)]\n"
298 DP_LEVEL "comp_addr [%x:%08x] comp_val 0x%08x\n",
299 dmae->opcode, dmae->src_addr_hi, dmae->src_addr_lo,
300 dmae->len, dmae->dst_addr_hi, dmae->dst_addr_lo, src_addr,
301 dmae->comp_addr_hi, dmae->comp_addr_lo, dmae->comp_val);
305 bnx2x_post_dmae(bp, dmae, INIT_DMAE_C(bp));
309 while (*wb_comp != DMAE_COMP_VAL) {
311 /* adjust delay for emulation/FPGA */
312 if (CHIP_REV_IS_SLOW(bp))
318 BNX2X_ERR("dmae timeout!\n");
323 DP(BNX2X_MSG_OFF, "data [0x%08x 0x%08x 0x%08x 0x%08x]\n",
324 bp->slowpath->wb_data[0], bp->slowpath->wb_data[1],
325 bp->slowpath->wb_data[2], bp->slowpath->wb_data[3]);
327 mutex_unlock(&bp->dmae_mutex);
330 /* used only for slowpath so not inlined */
331 static void bnx2x_wb_wr(struct bnx2x *bp, int reg, u32 val_hi, u32 val_lo)
335 wb_write[0] = val_hi;
336 wb_write[1] = val_lo;
337 REG_WR_DMAE(bp, reg, wb_write, 2);
341 static u64 bnx2x_wb_rd(struct bnx2x *bp, int reg)
345 REG_RD_DMAE(bp, reg, wb_data, 2);
347 return HILO_U64(wb_data[0], wb_data[1]);
351 static int bnx2x_mc_assert(struct bnx2x *bp)
355 u32 row0, row1, row2, row3;
358 last_idx = REG_RD8(bp, BAR_XSTRORM_INTMEM +
359 XSTORM_ASSERT_LIST_INDEX_OFFSET);
361 BNX2X_ERR("XSTORM_ASSERT_LIST_INDEX 0x%x\n", last_idx);
363 /* print the asserts */
364 for (i = 0; i < STROM_ASSERT_ARRAY_SIZE; i++) {
366 row0 = REG_RD(bp, BAR_XSTRORM_INTMEM +
367 XSTORM_ASSERT_LIST_OFFSET(i));
368 row1 = REG_RD(bp, BAR_XSTRORM_INTMEM +
369 XSTORM_ASSERT_LIST_OFFSET(i) + 4);
370 row2 = REG_RD(bp, BAR_XSTRORM_INTMEM +
371 XSTORM_ASSERT_LIST_OFFSET(i) + 8);
372 row3 = REG_RD(bp, BAR_XSTRORM_INTMEM +
373 XSTORM_ASSERT_LIST_OFFSET(i) + 12);
375 if (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) {
376 BNX2X_ERR("XSTORM_ASSERT_INDEX 0x%x = 0x%08x"
377 " 0x%08x 0x%08x 0x%08x\n",
378 i, row3, row2, row1, row0);
386 last_idx = REG_RD8(bp, BAR_TSTRORM_INTMEM +
387 TSTORM_ASSERT_LIST_INDEX_OFFSET);
389 BNX2X_ERR("TSTORM_ASSERT_LIST_INDEX 0x%x\n", last_idx);
391 /* print the asserts */
392 for (i = 0; i < STROM_ASSERT_ARRAY_SIZE; i++) {
394 row0 = REG_RD(bp, BAR_TSTRORM_INTMEM +
395 TSTORM_ASSERT_LIST_OFFSET(i));
396 row1 = REG_RD(bp, BAR_TSTRORM_INTMEM +
397 TSTORM_ASSERT_LIST_OFFSET(i) + 4);
398 row2 = REG_RD(bp, BAR_TSTRORM_INTMEM +
399 TSTORM_ASSERT_LIST_OFFSET(i) + 8);
400 row3 = REG_RD(bp, BAR_TSTRORM_INTMEM +
401 TSTORM_ASSERT_LIST_OFFSET(i) + 12);
403 if (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) {
404 BNX2X_ERR("TSTORM_ASSERT_INDEX 0x%x = 0x%08x"
405 " 0x%08x 0x%08x 0x%08x\n",
406 i, row3, row2, row1, row0);
414 last_idx = REG_RD8(bp, BAR_CSTRORM_INTMEM +
415 CSTORM_ASSERT_LIST_INDEX_OFFSET);
417 BNX2X_ERR("CSTORM_ASSERT_LIST_INDEX 0x%x\n", last_idx);
419 /* print the asserts */
420 for (i = 0; i < STROM_ASSERT_ARRAY_SIZE; i++) {
422 row0 = REG_RD(bp, BAR_CSTRORM_INTMEM +
423 CSTORM_ASSERT_LIST_OFFSET(i));
424 row1 = REG_RD(bp, BAR_CSTRORM_INTMEM +
425 CSTORM_ASSERT_LIST_OFFSET(i) + 4);
426 row2 = REG_RD(bp, BAR_CSTRORM_INTMEM +
427 CSTORM_ASSERT_LIST_OFFSET(i) + 8);
428 row3 = REG_RD(bp, BAR_CSTRORM_INTMEM +
429 CSTORM_ASSERT_LIST_OFFSET(i) + 12);
431 if (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) {
432 BNX2X_ERR("CSTORM_ASSERT_INDEX 0x%x = 0x%08x"
433 " 0x%08x 0x%08x 0x%08x\n",
434 i, row3, row2, row1, row0);
442 last_idx = REG_RD8(bp, BAR_USTRORM_INTMEM +
443 USTORM_ASSERT_LIST_INDEX_OFFSET);
445 BNX2X_ERR("USTORM_ASSERT_LIST_INDEX 0x%x\n", last_idx);
447 /* print the asserts */
448 for (i = 0; i < STROM_ASSERT_ARRAY_SIZE; i++) {
450 row0 = REG_RD(bp, BAR_USTRORM_INTMEM +
451 USTORM_ASSERT_LIST_OFFSET(i));
452 row1 = REG_RD(bp, BAR_USTRORM_INTMEM +
453 USTORM_ASSERT_LIST_OFFSET(i) + 4);
454 row2 = REG_RD(bp, BAR_USTRORM_INTMEM +
455 USTORM_ASSERT_LIST_OFFSET(i) + 8);
456 row3 = REG_RD(bp, BAR_USTRORM_INTMEM +
457 USTORM_ASSERT_LIST_OFFSET(i) + 12);
459 if (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) {
460 BNX2X_ERR("USTORM_ASSERT_INDEX 0x%x = 0x%08x"
461 " 0x%08x 0x%08x 0x%08x\n",
462 i, row3, row2, row1, row0);
472 static void bnx2x_fw_dump(struct bnx2x *bp)
478 mark = REG_RD(bp, MCP_REG_MCPR_SCRATCH + 0xf104);
479 mark = ((mark + 0x3) & ~0x3);
480 printk(KERN_ERR PFX "begin fw dump (mark 0x%x)\n" KERN_ERR, mark);
482 for (offset = mark - 0x08000000; offset <= 0xF900; offset += 0x8*4) {
483 for (word = 0; word < 8; word++)
484 data[word] = htonl(REG_RD(bp, MCP_REG_MCPR_SCRATCH +
487 printk(KERN_CONT "%s", (char *)data);
489 for (offset = 0xF108; offset <= mark - 0x08000000; offset += 0x8*4) {
490 for (word = 0; word < 8; word++)
491 data[word] = htonl(REG_RD(bp, MCP_REG_MCPR_SCRATCH +
494 printk(KERN_CONT "%s", (char *)data);
496 printk("\n" KERN_ERR PFX "end of fw dump\n");
499 static void bnx2x_panic_dump(struct bnx2x *bp)
504 bp->stats_state = STATS_STATE_DISABLED;
505 DP(BNX2X_MSG_STATS, "stats_state - DISABLED\n");
507 BNX2X_ERR("begin crash dump -----------------\n");
509 for_each_queue(bp, i) {
510 struct bnx2x_fastpath *fp = &bp->fp[i];
511 struct eth_tx_db_data *hw_prods = fp->hw_tx_prods;
513 BNX2X_ERR("queue[%d]: tx_pkt_prod(%x) tx_pkt_cons(%x)"
514 " tx_bd_prod(%x) tx_bd_cons(%x) *tx_cons_sb(%x)\n",
515 i, fp->tx_pkt_prod, fp->tx_pkt_cons, fp->tx_bd_prod,
516 fp->tx_bd_cons, le16_to_cpu(*fp->tx_cons_sb));
517 BNX2X_ERR(" rx_bd_prod(%x) rx_bd_cons(%x)"
518 " *rx_bd_cons_sb(%x) rx_comp_prod(%x)"
519 " rx_comp_cons(%x) *rx_cons_sb(%x)\n",
520 fp->rx_bd_prod, fp->rx_bd_cons,
521 le16_to_cpu(*fp->rx_bd_cons_sb), fp->rx_comp_prod,
522 fp->rx_comp_cons, le16_to_cpu(*fp->rx_cons_sb));
523 BNX2X_ERR(" rx_sge_prod(%x) last_max_sge(%x)"
524 " fp_c_idx(%x) *sb_c_idx(%x) fp_u_idx(%x)"
525 " *sb_u_idx(%x) bd data(%x,%x)\n",
526 fp->rx_sge_prod, fp->last_max_sge, fp->fp_c_idx,
527 fp->status_blk->c_status_block.status_block_index,
529 fp->status_blk->u_status_block.status_block_index,
530 hw_prods->packets_prod, hw_prods->bds_prod);
532 start = TX_BD(le16_to_cpu(*fp->tx_cons_sb) - 10);
533 end = TX_BD(le16_to_cpu(*fp->tx_cons_sb) + 245);
534 for (j = start; j < end; j++) {
535 struct sw_tx_bd *sw_bd = &fp->tx_buf_ring[j];
537 BNX2X_ERR("packet[%x]=[%p,%x]\n", j,
538 sw_bd->skb, sw_bd->first_bd);
541 start = TX_BD(fp->tx_bd_cons - 10);
542 end = TX_BD(fp->tx_bd_cons + 254);
543 for (j = start; j < end; j++) {
544 u32 *tx_bd = (u32 *)&fp->tx_desc_ring[j];
546 BNX2X_ERR("tx_bd[%x]=[%x:%x:%x:%x]\n",
547 j, tx_bd[0], tx_bd[1], tx_bd[2], tx_bd[3]);
550 start = RX_BD(le16_to_cpu(*fp->rx_cons_sb) - 10);
551 end = RX_BD(le16_to_cpu(*fp->rx_cons_sb) + 503);
552 for (j = start; j < end; j++) {
553 u32 *rx_bd = (u32 *)&fp->rx_desc_ring[j];
554 struct sw_rx_bd *sw_bd = &fp->rx_buf_ring[j];
556 BNX2X_ERR("rx_bd[%x]=[%x:%x] sw_bd=[%p]\n",
557 j, rx_bd[1], rx_bd[0], sw_bd->skb);
561 end = RX_SGE_CNT*NUM_RX_SGE_PAGES;
562 for (j = start; j < end; j++) {
563 u32 *rx_sge = (u32 *)&fp->rx_sge_ring[j];
564 struct sw_rx_page *sw_page = &fp->rx_page_ring[j];
566 BNX2X_ERR("rx_sge[%x]=[%x:%x] sw_page=[%p]\n",
567 j, rx_sge[1], rx_sge[0], sw_page->page);
570 start = RCQ_BD(fp->rx_comp_cons - 10);
571 end = RCQ_BD(fp->rx_comp_cons + 503);
572 for (j = start; j < end; j++) {
573 u32 *cqe = (u32 *)&fp->rx_comp_ring[j];
575 BNX2X_ERR("cqe[%x]=[%x:%x:%x:%x]\n",
576 j, cqe[0], cqe[1], cqe[2], cqe[3]);
580 BNX2X_ERR("def_c_idx(%u) def_u_idx(%u) def_x_idx(%u)"
581 " def_t_idx(%u) def_att_idx(%u) attn_state(%u)"
582 " spq_prod_idx(%u)\n",
583 bp->def_c_idx, bp->def_u_idx, bp->def_x_idx, bp->def_t_idx,
584 bp->def_att_idx, bp->attn_state, bp->spq_prod_idx);
588 BNX2X_ERR("end crash dump -----------------\n");
591 static void bnx2x_int_enable(struct bnx2x *bp)
593 int port = BP_PORT(bp);
594 u32 addr = port ? HC_REG_CONFIG_1 : HC_REG_CONFIG_0;
595 u32 val = REG_RD(bp, addr);
596 int msix = (bp->flags & USING_MSIX_FLAG) ? 1 : 0;
599 val &= ~HC_CONFIG_0_REG_SINGLE_ISR_EN_0;
600 val |= (HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |
601 HC_CONFIG_0_REG_ATTN_BIT_EN_0);
603 val |= (HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
604 HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |
605 HC_CONFIG_0_REG_INT_LINE_EN_0 |
606 HC_CONFIG_0_REG_ATTN_BIT_EN_0);
608 DP(NETIF_MSG_INTR, "write %x to HC %d (addr 0x%x) MSI-X %d\n",
609 val, port, addr, msix);
611 REG_WR(bp, addr, val);
613 val &= ~HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0;
616 DP(NETIF_MSG_INTR, "write %x to HC %d (addr 0x%x) MSI-X %d\n",
617 val, port, addr, msix);
619 REG_WR(bp, addr, val);
621 if (CHIP_IS_E1H(bp)) {
622 /* init leading/trailing edge */
624 val = (0xfe0f | (1 << (BP_E1HVN(bp) + 4)));
626 /* enable nig attention */
631 REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, val);
632 REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, val);
636 static void bnx2x_int_disable(struct bnx2x *bp)
638 int port = BP_PORT(bp);
639 u32 addr = port ? HC_REG_CONFIG_1 : HC_REG_CONFIG_0;
640 u32 val = REG_RD(bp, addr);
642 val &= ~(HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
643 HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |
644 HC_CONFIG_0_REG_INT_LINE_EN_0 |
645 HC_CONFIG_0_REG_ATTN_BIT_EN_0);
647 DP(NETIF_MSG_INTR, "write %x to HC %d (addr 0x%x)\n",
650 REG_WR(bp, addr, val);
651 if (REG_RD(bp, addr) != val)
652 BNX2X_ERR("BUG! proper val not read from IGU!\n");
655 static void bnx2x_int_disable_sync(struct bnx2x *bp)
657 int msix = (bp->flags & USING_MSIX_FLAG) ? 1 : 0;
660 /* disable interrupt handling */
661 atomic_inc(&bp->intr_sem);
662 /* prevent the HW from sending interrupts */
663 bnx2x_int_disable(bp);
665 /* make sure all ISRs are done */
667 for_each_queue(bp, i)
668 synchronize_irq(bp->msix_table[i].vector);
670 /* one more for the Slow Path IRQ */
671 synchronize_irq(bp->msix_table[i].vector);
673 synchronize_irq(bp->pdev->irq);
675 /* make sure sp_task is not running */
676 cancel_work_sync(&bp->sp_task);
682 * General service functions
685 static inline void bnx2x_ack_sb(struct bnx2x *bp, u8 sb_id,
686 u8 storm, u16 index, u8 op, u8 update)
688 u32 igu_addr = (IGU_ADDR_INT_ACK + IGU_FUNC_BASE * BP_FUNC(bp)) * 8;
689 struct igu_ack_register igu_ack;
691 igu_ack.status_block_index = index;
692 igu_ack.sb_id_and_flags =
693 ((sb_id << IGU_ACK_REGISTER_STATUS_BLOCK_ID_SHIFT) |
694 (storm << IGU_ACK_REGISTER_STORM_ID_SHIFT) |
695 (update << IGU_ACK_REGISTER_UPDATE_INDEX_SHIFT) |
696 (op << IGU_ACK_REGISTER_INTERRUPT_MODE_SHIFT));
698 DP(BNX2X_MSG_OFF, "write 0x%08x to IGU addr 0x%x\n",
699 (*(u32 *)&igu_ack), BAR_IGU_INTMEM + igu_addr);
700 REG_WR(bp, BAR_IGU_INTMEM + igu_addr, (*(u32 *)&igu_ack));
703 static inline u16 bnx2x_update_fpsb_idx(struct bnx2x_fastpath *fp)
705 struct host_status_block *fpsb = fp->status_blk;
708 barrier(); /* status block is written to by the chip */
709 if (fp->fp_c_idx != fpsb->c_status_block.status_block_index) {
710 fp->fp_c_idx = fpsb->c_status_block.status_block_index;
713 if (fp->fp_u_idx != fpsb->u_status_block.status_block_index) {
714 fp->fp_u_idx = fpsb->u_status_block.status_block_index;
720 static u16 bnx2x_ack_int(struct bnx2x *bp)
722 u32 igu_addr = (IGU_ADDR_SIMD_MASK + IGU_FUNC_BASE * BP_FUNC(bp)) * 8;
723 u32 result = REG_RD(bp, BAR_IGU_INTMEM + igu_addr);
725 DP(BNX2X_MSG_OFF, "read 0x%08x from IGU addr 0x%x\n",
726 result, BAR_IGU_INTMEM + igu_addr);
729 #warning IGU_DEBUG active
731 BNX2X_ERR("read %x from IGU\n", result);
732 REG_WR(bp, TM_REG_TIMER_SOFT_RST, 0);
740 * fast path service functions
743 /* free skb in the packet ring at pos idx
744 * return idx of last bd freed
746 static u16 bnx2x_free_tx_pkt(struct bnx2x *bp, struct bnx2x_fastpath *fp,
749 struct sw_tx_bd *tx_buf = &fp->tx_buf_ring[idx];
750 struct eth_tx_bd *tx_bd;
751 struct sk_buff *skb = tx_buf->skb;
752 u16 bd_idx = TX_BD(tx_buf->first_bd), new_cons;
755 DP(BNX2X_MSG_OFF, "pkt_idx %d buff @(%p)->skb %p\n",
759 DP(BNX2X_MSG_OFF, "free bd_idx %d\n", bd_idx);
760 tx_bd = &fp->tx_desc_ring[bd_idx];
761 pci_unmap_single(bp->pdev, BD_UNMAP_ADDR(tx_bd),
762 BD_UNMAP_LEN(tx_bd), PCI_DMA_TODEVICE);
764 nbd = le16_to_cpu(tx_bd->nbd) - 1;
765 new_cons = nbd + tx_buf->first_bd;
766 #ifdef BNX2X_STOP_ON_ERROR
767 if (nbd > (MAX_SKB_FRAGS + 2)) {
768 BNX2X_ERR("BAD nbd!\n");
773 /* Skip a parse bd and the TSO split header bd
774 since they have no mapping */
776 bd_idx = TX_BD(NEXT_TX_IDX(bd_idx));
778 if (tx_bd->bd_flags.as_bitfield & (ETH_TX_BD_FLAGS_IP_CSUM |
779 ETH_TX_BD_FLAGS_TCP_CSUM |
780 ETH_TX_BD_FLAGS_SW_LSO)) {
782 bd_idx = TX_BD(NEXT_TX_IDX(bd_idx));
783 tx_bd = &fp->tx_desc_ring[bd_idx];
784 /* is this a TSO split header bd? */
785 if (tx_bd->bd_flags.as_bitfield & ETH_TX_BD_FLAGS_SW_LSO) {
787 bd_idx = TX_BD(NEXT_TX_IDX(bd_idx));
794 DP(BNX2X_MSG_OFF, "free frag bd_idx %d\n", bd_idx);
795 tx_bd = &fp->tx_desc_ring[bd_idx];
796 pci_unmap_page(bp->pdev, BD_UNMAP_ADDR(tx_bd),
797 BD_UNMAP_LEN(tx_bd), PCI_DMA_TODEVICE);
799 bd_idx = TX_BD(NEXT_TX_IDX(bd_idx));
805 tx_buf->first_bd = 0;
811 static inline u16 bnx2x_tx_avail(struct bnx2x_fastpath *fp)
817 barrier(); /* Tell compiler that prod and cons can change */
818 prod = fp->tx_bd_prod;
819 cons = fp->tx_bd_cons;
821 /* NUM_TX_RINGS = number of "next-page" entries
822 It will be used as a threshold */
823 used = SUB_S16(prod, cons) + (s16)NUM_TX_RINGS;
825 #ifdef BNX2X_STOP_ON_ERROR
827 WARN_ON(used > fp->bp->tx_ring_size);
828 WARN_ON((fp->bp->tx_ring_size - used) > MAX_TX_AVAIL);
831 return (s16)(fp->bp->tx_ring_size) - used;
834 static void bnx2x_tx_int(struct bnx2x_fastpath *fp, int work)
836 struct bnx2x *bp = fp->bp;
837 u16 hw_cons, sw_cons, bd_cons = fp->tx_bd_cons;
840 #ifdef BNX2X_STOP_ON_ERROR
841 if (unlikely(bp->panic))
845 hw_cons = le16_to_cpu(*fp->tx_cons_sb);
846 sw_cons = fp->tx_pkt_cons;
848 while (sw_cons != hw_cons) {
851 pkt_cons = TX_BD(sw_cons);
853 /* prefetch(bp->tx_buf_ring[pkt_cons].skb); */
855 DP(NETIF_MSG_TX_DONE, "hw_cons %u sw_cons %u pkt_cons %u\n",
856 hw_cons, sw_cons, pkt_cons);
858 /* if (NEXT_TX_IDX(sw_cons) != hw_cons) {
860 prefetch(fp->tx_buf_ring[NEXT_TX_IDX(sw_cons)].skb);
863 bd_cons = bnx2x_free_tx_pkt(bp, fp, pkt_cons);
871 fp->tx_pkt_cons = sw_cons;
872 fp->tx_bd_cons = bd_cons;
874 /* Need to make the tx_cons update visible to start_xmit()
875 * before checking for netif_queue_stopped(). Without the
876 * memory barrier, there is a small possibility that start_xmit()
877 * will miss it and cause the queue to be stopped forever.
881 /* TBD need a thresh? */
882 if (unlikely(netif_queue_stopped(bp->dev))) {
884 netif_tx_lock(bp->dev);
886 if (netif_queue_stopped(bp->dev) &&
887 (bp->state == BNX2X_STATE_OPEN) &&
888 (bnx2x_tx_avail(fp) >= MAX_SKB_FRAGS + 3))
889 netif_wake_queue(bp->dev);
891 netif_tx_unlock(bp->dev);
895 static void bnx2x_sp_event(struct bnx2x_fastpath *fp,
896 union eth_rx_cqe *rr_cqe)
898 struct bnx2x *bp = fp->bp;
899 int cid = SW_CID(rr_cqe->ramrod_cqe.conn_and_cmd_data);
900 int command = CQE_CMD(rr_cqe->ramrod_cqe.conn_and_cmd_data);
903 "fp %d cid %d got ramrod #%d state is %x type is %d\n",
904 FP_IDX(fp), cid, command, bp->state,
905 rr_cqe->ramrod_cqe.ramrod_type);
910 switch (command | fp->state) {
911 case (RAMROD_CMD_ID_ETH_CLIENT_SETUP |
912 BNX2X_FP_STATE_OPENING):
913 DP(NETIF_MSG_IFUP, "got MULTI[%d] setup ramrod\n",
915 fp->state = BNX2X_FP_STATE_OPEN;
918 case (RAMROD_CMD_ID_ETH_HALT | BNX2X_FP_STATE_HALTING):
919 DP(NETIF_MSG_IFDOWN, "got MULTI[%d] halt ramrod\n",
921 fp->state = BNX2X_FP_STATE_HALTED;
925 BNX2X_ERR("unexpected MC reply (%d) "
926 "fp->state is %x\n", command, fp->state);
929 mb(); /* force bnx2x_wait_ramrod() to see the change */
933 switch (command | bp->state) {
934 case (RAMROD_CMD_ID_ETH_PORT_SETUP | BNX2X_STATE_OPENING_WAIT4_PORT):
935 DP(NETIF_MSG_IFUP, "got setup ramrod\n");
936 bp->state = BNX2X_STATE_OPEN;
939 case (RAMROD_CMD_ID_ETH_HALT | BNX2X_STATE_CLOSING_WAIT4_HALT):
940 DP(NETIF_MSG_IFDOWN, "got halt ramrod\n");
941 bp->state = BNX2X_STATE_CLOSING_WAIT4_DELETE;
942 fp->state = BNX2X_FP_STATE_HALTED;
945 case (RAMROD_CMD_ID_ETH_CFC_DEL | BNX2X_STATE_CLOSING_WAIT4_HALT):
946 DP(NETIF_MSG_IFDOWN, "got delete ramrod for MULTI[%d]\n", cid);
947 bnx2x_fp(bp, cid, state) = BNX2X_FP_STATE_CLOSED;
950 case (RAMROD_CMD_ID_ETH_SET_MAC | BNX2X_STATE_OPEN):
951 case (RAMROD_CMD_ID_ETH_SET_MAC | BNX2X_STATE_DIAG):
952 DP(NETIF_MSG_IFUP, "got set mac ramrod\n");
953 bp->set_mac_pending = 0;
956 case (RAMROD_CMD_ID_ETH_SET_MAC | BNX2X_STATE_CLOSING_WAIT4_HALT):
957 DP(NETIF_MSG_IFDOWN, "got (un)set mac ramrod\n");
961 BNX2X_ERR("unexpected MC reply (%d) bp->state is %x\n",
965 mb(); /* force bnx2x_wait_ramrod() to see the change */
968 static inline void bnx2x_free_rx_sge(struct bnx2x *bp,
969 struct bnx2x_fastpath *fp, u16 index)
971 struct sw_rx_page *sw_buf = &fp->rx_page_ring[index];
972 struct page *page = sw_buf->page;
973 struct eth_rx_sge *sge = &fp->rx_sge_ring[index];
975 /* Skip "next page" elements */
979 pci_unmap_page(bp->pdev, pci_unmap_addr(sw_buf, mapping),
980 BCM_PAGE_SIZE*PAGES_PER_SGE, PCI_DMA_FROMDEVICE);
981 __free_pages(page, PAGES_PER_SGE_SHIFT);
988 static inline void bnx2x_free_rx_sge_range(struct bnx2x *bp,
989 struct bnx2x_fastpath *fp, int last)
993 for (i = 0; i < last; i++)
994 bnx2x_free_rx_sge(bp, fp, i);
997 static inline int bnx2x_alloc_rx_sge(struct bnx2x *bp,
998 struct bnx2x_fastpath *fp, u16 index)
1000 struct page *page = alloc_pages(GFP_ATOMIC, PAGES_PER_SGE_SHIFT);
1001 struct sw_rx_page *sw_buf = &fp->rx_page_ring[index];
1002 struct eth_rx_sge *sge = &fp->rx_sge_ring[index];
1005 if (unlikely(page == NULL))
1008 mapping = pci_map_page(bp->pdev, page, 0, BCM_PAGE_SIZE*PAGES_PER_SGE,
1009 PCI_DMA_FROMDEVICE);
1010 if (unlikely(dma_mapping_error(&bp->pdev->dev, mapping))) {
1011 __free_pages(page, PAGES_PER_SGE_SHIFT);
1015 sw_buf->page = page;
1016 pci_unmap_addr_set(sw_buf, mapping, mapping);
1018 sge->addr_hi = cpu_to_le32(U64_HI(mapping));
1019 sge->addr_lo = cpu_to_le32(U64_LO(mapping));
1024 static inline int bnx2x_alloc_rx_skb(struct bnx2x *bp,
1025 struct bnx2x_fastpath *fp, u16 index)
1027 struct sk_buff *skb;
1028 struct sw_rx_bd *rx_buf = &fp->rx_buf_ring[index];
1029 struct eth_rx_bd *rx_bd = &fp->rx_desc_ring[index];
1032 skb = netdev_alloc_skb(bp->dev, bp->rx_buf_size);
1033 if (unlikely(skb == NULL))
1036 mapping = pci_map_single(bp->pdev, skb->data, bp->rx_buf_use_size,
1037 PCI_DMA_FROMDEVICE);
1038 if (unlikely(dma_mapping_error(&bp->pdev->dev, mapping))) {
1044 pci_unmap_addr_set(rx_buf, mapping, mapping);
1046 rx_bd->addr_hi = cpu_to_le32(U64_HI(mapping));
1047 rx_bd->addr_lo = cpu_to_le32(U64_LO(mapping));
1052 /* note that we are not allocating a new skb,
1053 * we are just moving one from cons to prod
1054 * we are not creating a new mapping,
1055 * so there is no need to check for dma_mapping_error().
1057 static void bnx2x_reuse_rx_skb(struct bnx2x_fastpath *fp,
1058 struct sk_buff *skb, u16 cons, u16 prod)
1060 struct bnx2x *bp = fp->bp;
1061 struct sw_rx_bd *cons_rx_buf = &fp->rx_buf_ring[cons];
1062 struct sw_rx_bd *prod_rx_buf = &fp->rx_buf_ring[prod];
1063 struct eth_rx_bd *cons_bd = &fp->rx_desc_ring[cons];
1064 struct eth_rx_bd *prod_bd = &fp->rx_desc_ring[prod];
1066 pci_dma_sync_single_for_device(bp->pdev,
1067 pci_unmap_addr(cons_rx_buf, mapping),
1068 bp->rx_offset + RX_COPY_THRESH,
1069 PCI_DMA_FROMDEVICE);
1071 prod_rx_buf->skb = cons_rx_buf->skb;
1072 pci_unmap_addr_set(prod_rx_buf, mapping,
1073 pci_unmap_addr(cons_rx_buf, mapping));
1074 *prod_bd = *cons_bd;
1077 static inline void bnx2x_update_last_max_sge(struct bnx2x_fastpath *fp,
1080 u16 last_max = fp->last_max_sge;
1082 if (SUB_S16(idx, last_max) > 0)
1083 fp->last_max_sge = idx;
1086 static void bnx2x_clear_sge_mask_next_elems(struct bnx2x_fastpath *fp)
1090 for (i = 1; i <= NUM_RX_SGE_PAGES; i++) {
1091 int idx = RX_SGE_CNT * i - 1;
1093 for (j = 0; j < 2; j++) {
1094 SGE_MASK_CLEAR_BIT(fp, idx);
1100 static void bnx2x_update_sge_prod(struct bnx2x_fastpath *fp,
1101 struct eth_fast_path_rx_cqe *fp_cqe)
1103 struct bnx2x *bp = fp->bp;
1104 u16 sge_len = BCM_PAGE_ALIGN(le16_to_cpu(fp_cqe->pkt_len) -
1105 le16_to_cpu(fp_cqe->len_on_bd)) >>
1107 u16 last_max, last_elem, first_elem;
1114 /* First mark all used pages */
1115 for (i = 0; i < sge_len; i++)
1116 SGE_MASK_CLEAR_BIT(fp, RX_SGE(le16_to_cpu(fp_cqe->sgl[i])));
1118 DP(NETIF_MSG_RX_STATUS, "fp_cqe->sgl[%d] = %d\n",
1119 sge_len - 1, le16_to_cpu(fp_cqe->sgl[sge_len - 1]));
1121 /* Here we assume that the last SGE index is the biggest */
1122 prefetch((void *)(fp->sge_mask));
1123 bnx2x_update_last_max_sge(fp, le16_to_cpu(fp_cqe->sgl[sge_len - 1]));
1125 last_max = RX_SGE(fp->last_max_sge);
1126 last_elem = last_max >> RX_SGE_MASK_ELEM_SHIFT;
1127 first_elem = RX_SGE(fp->rx_sge_prod) >> RX_SGE_MASK_ELEM_SHIFT;
1129 /* If ring is not full */
1130 if (last_elem + 1 != first_elem)
1133 /* Now update the prod */
1134 for (i = first_elem; i != last_elem; i = NEXT_SGE_MASK_ELEM(i)) {
1135 if (likely(fp->sge_mask[i]))
1138 fp->sge_mask[i] = RX_SGE_MASK_ELEM_ONE_MASK;
1139 delta += RX_SGE_MASK_ELEM_SZ;
1143 fp->rx_sge_prod += delta;
1144 /* clear page-end entries */
1145 bnx2x_clear_sge_mask_next_elems(fp);
1148 DP(NETIF_MSG_RX_STATUS,
1149 "fp->last_max_sge = %d fp->rx_sge_prod = %d\n",
1150 fp->last_max_sge, fp->rx_sge_prod);
1153 static inline void bnx2x_init_sge_ring_bit_mask(struct bnx2x_fastpath *fp)
1155 /* Set the mask to all 1-s: it's faster to compare to 0 than to 0xf-s */
1156 memset(fp->sge_mask, 0xff,
1157 (NUM_RX_SGE >> RX_SGE_MASK_ELEM_SHIFT)*sizeof(u64));
1159 /* Clear the two last indeces in the page to 1:
1160 these are the indeces that correspond to the "next" element,
1161 hence will never be indicated and should be removed from
1162 the calculations. */
1163 bnx2x_clear_sge_mask_next_elems(fp);
1166 static void bnx2x_tpa_start(struct bnx2x_fastpath *fp, u16 queue,
1167 struct sk_buff *skb, u16 cons, u16 prod)
1169 struct bnx2x *bp = fp->bp;
1170 struct sw_rx_bd *cons_rx_buf = &fp->rx_buf_ring[cons];
1171 struct sw_rx_bd *prod_rx_buf = &fp->rx_buf_ring[prod];
1172 struct eth_rx_bd *prod_bd = &fp->rx_desc_ring[prod];
1175 /* move empty skb from pool to prod and map it */
1176 prod_rx_buf->skb = fp->tpa_pool[queue].skb;
1177 mapping = pci_map_single(bp->pdev, fp->tpa_pool[queue].skb->data,
1178 bp->rx_buf_use_size, PCI_DMA_FROMDEVICE);
1179 pci_unmap_addr_set(prod_rx_buf, mapping, mapping);
1181 /* move partial skb from cons to pool (don't unmap yet) */
1182 fp->tpa_pool[queue] = *cons_rx_buf;
1184 /* mark bin state as start - print error if current state != stop */
1185 if (fp->tpa_state[queue] != BNX2X_TPA_STOP)
1186 BNX2X_ERR("start of bin not in stop [%d]\n", queue);
1188 fp->tpa_state[queue] = BNX2X_TPA_START;
1190 /* point prod_bd to new skb */
1191 prod_bd->addr_hi = cpu_to_le32(U64_HI(mapping));
1192 prod_bd->addr_lo = cpu_to_le32(U64_LO(mapping));
1194 #ifdef BNX2X_STOP_ON_ERROR
1195 fp->tpa_queue_used |= (1 << queue);
1196 #ifdef __powerpc64__
1197 DP(NETIF_MSG_RX_STATUS, "fp->tpa_queue_used = 0x%lx\n",
1199 DP(NETIF_MSG_RX_STATUS, "fp->tpa_queue_used = 0x%llx\n",
1201 fp->tpa_queue_used);
1205 static int bnx2x_fill_frag_skb(struct bnx2x *bp, struct bnx2x_fastpath *fp,
1206 struct sk_buff *skb,
1207 struct eth_fast_path_rx_cqe *fp_cqe,
1210 struct sw_rx_page *rx_pg, old_rx_pg;
1212 u16 len_on_bd = le16_to_cpu(fp_cqe->len_on_bd);
1213 u32 i, frag_len, frag_size, pages;
1217 frag_size = le16_to_cpu(fp_cqe->pkt_len) - len_on_bd;
1218 pages = BCM_PAGE_ALIGN(frag_size) >> BCM_PAGE_SHIFT;
1220 /* This is needed in order to enable forwarding support */
1222 skb_shinfo(skb)->gso_size = min((u32)BCM_PAGE_SIZE,
1223 max(frag_size, (u32)len_on_bd));
1225 #ifdef BNX2X_STOP_ON_ERROR
1226 if (pages > 8*PAGES_PER_SGE) {
1227 BNX2X_ERR("SGL length is too long: %d. CQE index is %d\n",
1229 BNX2X_ERR("fp_cqe->pkt_len = %d fp_cqe->len_on_bd = %d\n",
1230 fp_cqe->pkt_len, len_on_bd);
1236 /* Run through the SGL and compose the fragmented skb */
1237 for (i = 0, j = 0; i < pages; i += PAGES_PER_SGE, j++) {
1238 u16 sge_idx = RX_SGE(le16_to_cpu(fp_cqe->sgl[j]));
1240 /* FW gives the indices of the SGE as if the ring is an array
1241 (meaning that "next" element will consume 2 indices) */
1242 frag_len = min(frag_size, (u32)(BCM_PAGE_SIZE*PAGES_PER_SGE));
1243 rx_pg = &fp->rx_page_ring[sge_idx];
1247 /* If we fail to allocate a substitute page, we simply stop
1248 where we are and drop the whole packet */
1249 err = bnx2x_alloc_rx_sge(bp, fp, sge_idx);
1250 if (unlikely(err)) {
1251 bp->eth_stats.rx_skb_alloc_failed++;
1255 /* Unmap the page as we r going to pass it to the stack */
1256 pci_unmap_page(bp->pdev, pci_unmap_addr(&old_rx_pg, mapping),
1257 BCM_PAGE_SIZE*PAGES_PER_SGE, PCI_DMA_FROMDEVICE);
1259 /* Add one frag and update the appropriate fields in the skb */
1260 skb_fill_page_desc(skb, j, old_rx_pg.page, 0, frag_len);
1262 skb->data_len += frag_len;
1263 skb->truesize += frag_len;
1264 skb->len += frag_len;
1266 frag_size -= frag_len;
1272 static void bnx2x_tpa_stop(struct bnx2x *bp, struct bnx2x_fastpath *fp,
1273 u16 queue, int pad, int len, union eth_rx_cqe *cqe,
1276 struct sw_rx_bd *rx_buf = &fp->tpa_pool[queue];
1277 struct sk_buff *skb = rx_buf->skb;
1279 struct sk_buff *new_skb = netdev_alloc_skb(bp->dev, bp->rx_buf_size);
1281 /* Unmap skb in the pool anyway, as we are going to change
1282 pool entry status to BNX2X_TPA_STOP even if new skb allocation
1284 pci_unmap_single(bp->pdev, pci_unmap_addr(rx_buf, mapping),
1285 bp->rx_buf_use_size, PCI_DMA_FROMDEVICE);
1287 if (likely(new_skb)) {
1288 /* fix ip xsum and give it to the stack */
1289 /* (no need to map the new skb) */
1292 prefetch(((char *)(skb)) + 128);
1294 #ifdef BNX2X_STOP_ON_ERROR
1295 if (pad + len > bp->rx_buf_size) {
1296 BNX2X_ERR("skb_put is about to fail... "
1297 "pad %d len %d rx_buf_size %d\n",
1298 pad, len, bp->rx_buf_size);
1304 skb_reserve(skb, pad);
1307 skb->protocol = eth_type_trans(skb, bp->dev);
1308 skb->ip_summed = CHECKSUM_UNNECESSARY;
1313 iph = (struct iphdr *)skb->data;
1315 iph->check = ip_fast_csum((u8 *)iph, iph->ihl);
1318 if (!bnx2x_fill_frag_skb(bp, fp, skb,
1319 &cqe->fast_path_cqe, cqe_idx)) {
1321 if ((bp->vlgrp != NULL) &&
1322 (le16_to_cpu(cqe->fast_path_cqe.pars_flags.flags) &
1323 PARSING_FLAGS_VLAN))
1324 vlan_hwaccel_receive_skb(skb, bp->vlgrp,
1325 le16_to_cpu(cqe->fast_path_cqe.
1329 netif_receive_skb(skb);
1331 DP(NETIF_MSG_RX_STATUS, "Failed to allocate new pages"
1332 " - dropping packet!\n");
1336 bp->dev->last_rx = jiffies;
1338 /* put new skb in bin */
1339 fp->tpa_pool[queue].skb = new_skb;
1342 /* else drop the packet and keep the buffer in the bin */
1343 DP(NETIF_MSG_RX_STATUS,
1344 "Failed to allocate new skb - dropping packet!\n");
1345 bp->eth_stats.rx_skb_alloc_failed++;
1348 fp->tpa_state[queue] = BNX2X_TPA_STOP;
1351 static inline void bnx2x_update_rx_prod(struct bnx2x *bp,
1352 struct bnx2x_fastpath *fp,
1353 u16 bd_prod, u16 rx_comp_prod,
1356 struct tstorm_eth_rx_producers rx_prods = {0};
1359 /* Update producers */
1360 rx_prods.bd_prod = bd_prod;
1361 rx_prods.cqe_prod = rx_comp_prod;
1362 rx_prods.sge_prod = rx_sge_prod;
1364 for (i = 0; i < sizeof(struct tstorm_eth_rx_producers)/4; i++)
1365 REG_WR(bp, BAR_TSTRORM_INTMEM +
1366 TSTORM_RX_PRODS_OFFSET(BP_PORT(bp), FP_CL_ID(fp)) + i*4,
1367 ((u32 *)&rx_prods)[i]);
1369 DP(NETIF_MSG_RX_STATUS,
1370 "Wrote: bd_prod %u cqe_prod %u sge_prod %u\n",
1371 bd_prod, rx_comp_prod, rx_sge_prod);
1374 static int bnx2x_rx_int(struct bnx2x_fastpath *fp, int budget)
1376 struct bnx2x *bp = fp->bp;
1377 u16 bd_cons, bd_prod, bd_prod_fw, comp_ring_cons;
1378 u16 hw_comp_cons, sw_comp_cons, sw_comp_prod;
1382 #ifdef BNX2X_STOP_ON_ERROR
1383 if (unlikely(bp->panic))
1387 /* CQ "next element" is of the size of the regular element,
1388 that's why it's ok here */
1389 hw_comp_cons = le16_to_cpu(*fp->rx_cons_sb);
1390 if ((hw_comp_cons & MAX_RCQ_DESC_CNT) == MAX_RCQ_DESC_CNT)
1393 bd_cons = fp->rx_bd_cons;
1394 bd_prod = fp->rx_bd_prod;
1395 bd_prod_fw = bd_prod;
1396 sw_comp_cons = fp->rx_comp_cons;
1397 sw_comp_prod = fp->rx_comp_prod;
1399 /* Memory barrier necessary as speculative reads of the rx
1400 * buffer can be ahead of the index in the status block
1404 DP(NETIF_MSG_RX_STATUS,
1405 "queue[%d]: hw_comp_cons %u sw_comp_cons %u\n",
1406 FP_IDX(fp), hw_comp_cons, sw_comp_cons);
1408 while (sw_comp_cons != hw_comp_cons) {
1409 struct sw_rx_bd *rx_buf = NULL;
1410 struct sk_buff *skb;
1411 union eth_rx_cqe *cqe;
1415 comp_ring_cons = RCQ_BD(sw_comp_cons);
1416 bd_prod = RX_BD(bd_prod);
1417 bd_cons = RX_BD(bd_cons);
1419 cqe = &fp->rx_comp_ring[comp_ring_cons];
1420 cqe_fp_flags = cqe->fast_path_cqe.type_error_flags;
1422 DP(NETIF_MSG_RX_STATUS, "CQE type %x err %x status %x"
1423 " queue %x vlan %x len %u\n", CQE_TYPE(cqe_fp_flags),
1424 cqe_fp_flags, cqe->fast_path_cqe.status_flags,
1425 cqe->fast_path_cqe.rss_hash_result,
1426 le16_to_cpu(cqe->fast_path_cqe.vlan_tag),
1427 le16_to_cpu(cqe->fast_path_cqe.pkt_len));
1429 /* is this a slowpath msg? */
1430 if (unlikely(CQE_TYPE(cqe_fp_flags))) {
1431 bnx2x_sp_event(fp, cqe);
1434 /* this is an rx packet */
1436 rx_buf = &fp->rx_buf_ring[bd_cons];
1438 len = le16_to_cpu(cqe->fast_path_cqe.pkt_len);
1439 pad = cqe->fast_path_cqe.placement_offset;
1441 /* If CQE is marked both TPA_START and TPA_END
1442 it is a non-TPA CQE */
1443 if ((!fp->disable_tpa) &&
1444 (TPA_TYPE(cqe_fp_flags) !=
1445 (TPA_TYPE_START | TPA_TYPE_END))) {
1446 queue = cqe->fast_path_cqe.queue_index;
1448 if (TPA_TYPE(cqe_fp_flags) == TPA_TYPE_START) {
1449 DP(NETIF_MSG_RX_STATUS,
1450 "calling tpa_start on queue %d\n",
1453 bnx2x_tpa_start(fp, queue, skb,
1458 if (TPA_TYPE(cqe_fp_flags) == TPA_TYPE_END) {
1459 DP(NETIF_MSG_RX_STATUS,
1460 "calling tpa_stop on queue %d\n",
1463 if (!BNX2X_RX_SUM_FIX(cqe))
1464 BNX2X_ERR("STOP on none TCP "
1467 /* This is a size of the linear data
1469 len = le16_to_cpu(cqe->fast_path_cqe.
1471 bnx2x_tpa_stop(bp, fp, queue, pad,
1472 len, cqe, comp_ring_cons);
1473 #ifdef BNX2X_STOP_ON_ERROR
1478 bnx2x_update_sge_prod(fp,
1479 &cqe->fast_path_cqe);
1484 pci_dma_sync_single_for_device(bp->pdev,
1485 pci_unmap_addr(rx_buf, mapping),
1486 pad + RX_COPY_THRESH,
1487 PCI_DMA_FROMDEVICE);
1489 prefetch(((char *)(skb)) + 128);
1491 /* is this an error packet? */
1492 if (unlikely(cqe_fp_flags & ETH_RX_ERROR_FALGS)) {
1493 DP(NETIF_MSG_RX_ERR,
1494 "ERROR flags %x rx packet %u\n",
1495 cqe_fp_flags, sw_comp_cons);
1496 bp->eth_stats.rx_err_discard_pkt++;
1500 /* Since we don't have a jumbo ring
1501 * copy small packets if mtu > 1500
1503 if ((bp->dev->mtu > ETH_MAX_PACKET_SIZE) &&
1504 (len <= RX_COPY_THRESH)) {
1505 struct sk_buff *new_skb;
1507 new_skb = netdev_alloc_skb(bp->dev,
1509 if (new_skb == NULL) {
1510 DP(NETIF_MSG_RX_ERR,
1511 "ERROR packet dropped "
1512 "because of alloc failure\n");
1513 bp->eth_stats.rx_skb_alloc_failed++;
1518 skb_copy_from_linear_data_offset(skb, pad,
1519 new_skb->data + pad, len);
1520 skb_reserve(new_skb, pad);
1521 skb_put(new_skb, len);
1523 bnx2x_reuse_rx_skb(fp, skb, bd_cons, bd_prod);
1527 } else if (bnx2x_alloc_rx_skb(bp, fp, bd_prod) == 0) {
1528 pci_unmap_single(bp->pdev,
1529 pci_unmap_addr(rx_buf, mapping),
1530 bp->rx_buf_use_size,
1531 PCI_DMA_FROMDEVICE);
1532 skb_reserve(skb, pad);
1536 DP(NETIF_MSG_RX_ERR,
1537 "ERROR packet dropped because "
1538 "of alloc failure\n");
1539 bp->eth_stats.rx_skb_alloc_failed++;
1541 bnx2x_reuse_rx_skb(fp, skb, bd_cons, bd_prod);
1545 skb->protocol = eth_type_trans(skb, bp->dev);
1547 skb->ip_summed = CHECKSUM_NONE;
1549 if (likely(BNX2X_RX_CSUM_OK(cqe)))
1550 skb->ip_summed = CHECKSUM_UNNECESSARY;
1552 bp->eth_stats.hw_csum_err++;
1557 if ((bp->vlgrp != NULL) &&
1558 (le16_to_cpu(cqe->fast_path_cqe.pars_flags.flags) &
1559 PARSING_FLAGS_VLAN))
1560 vlan_hwaccel_receive_skb(skb, bp->vlgrp,
1561 le16_to_cpu(cqe->fast_path_cqe.vlan_tag));
1564 netif_receive_skb(skb);
1566 bp->dev->last_rx = jiffies;
1571 bd_cons = NEXT_RX_IDX(bd_cons);
1572 bd_prod = NEXT_RX_IDX(bd_prod);
1573 bd_prod_fw = NEXT_RX_IDX(bd_prod_fw);
1576 sw_comp_prod = NEXT_RCQ_IDX(sw_comp_prod);
1577 sw_comp_cons = NEXT_RCQ_IDX(sw_comp_cons);
1579 if (rx_pkt == budget)
1583 fp->rx_bd_cons = bd_cons;
1584 fp->rx_bd_prod = bd_prod_fw;
1585 fp->rx_comp_cons = sw_comp_cons;
1586 fp->rx_comp_prod = sw_comp_prod;
1588 /* Update producers */
1589 bnx2x_update_rx_prod(bp, fp, bd_prod_fw, sw_comp_prod,
1591 mmiowb(); /* keep prod updates ordered */
1593 fp->rx_pkt += rx_pkt;
1599 static irqreturn_t bnx2x_msix_fp_int(int irq, void *fp_cookie)
1601 struct bnx2x_fastpath *fp = fp_cookie;
1602 struct bnx2x *bp = fp->bp;
1603 struct net_device *dev = bp->dev;
1604 int index = FP_IDX(fp);
1606 /* Return here if interrupt is disabled */
1607 if (unlikely(atomic_read(&bp->intr_sem) != 0)) {
1608 DP(NETIF_MSG_INTR, "called but intr_sem not 0, returning\n");
1612 DP(BNX2X_MSG_FP, "got an MSI-X interrupt on IDX:SB [%d:%d]\n",
1613 index, FP_SB_ID(fp));
1614 bnx2x_ack_sb(bp, FP_SB_ID(fp), USTORM_ID, 0, IGU_INT_DISABLE, 0);
1616 #ifdef BNX2X_STOP_ON_ERROR
1617 if (unlikely(bp->panic))
1621 prefetch(fp->rx_cons_sb);
1622 prefetch(fp->tx_cons_sb);
1623 prefetch(&fp->status_blk->c_status_block.status_block_index);
1624 prefetch(&fp->status_blk->u_status_block.status_block_index);
1626 netif_rx_schedule(dev, &bnx2x_fp(bp, index, napi));
1631 static irqreturn_t bnx2x_interrupt(int irq, void *dev_instance)
1633 struct net_device *dev = dev_instance;
1634 struct bnx2x *bp = netdev_priv(dev);
1635 u16 status = bnx2x_ack_int(bp);
1638 /* Return here if interrupt is shared and it's not for us */
1639 if (unlikely(status == 0)) {
1640 DP(NETIF_MSG_INTR, "not our interrupt!\n");
1643 DP(NETIF_MSG_INTR, "got an interrupt status %u\n", status);
1645 #ifdef BNX2X_STOP_ON_ERROR
1646 if (unlikely(bp->panic))
1650 /* Return here if interrupt is disabled */
1651 if (unlikely(atomic_read(&bp->intr_sem) != 0)) {
1652 DP(NETIF_MSG_INTR, "called but intr_sem not 0, returning\n");
1656 mask = 0x2 << bp->fp[0].sb_id;
1657 if (status & mask) {
1658 struct bnx2x_fastpath *fp = &bp->fp[0];
1660 prefetch(fp->rx_cons_sb);
1661 prefetch(fp->tx_cons_sb);
1662 prefetch(&fp->status_blk->c_status_block.status_block_index);
1663 prefetch(&fp->status_blk->u_status_block.status_block_index);
1665 netif_rx_schedule(dev, &bnx2x_fp(bp, 0, napi));
1671 if (unlikely(status & 0x1)) {
1672 schedule_work(&bp->sp_task);
1680 DP(NETIF_MSG_INTR, "got an unknown interrupt! (status %u)\n",
1686 /* end of fast path */
1688 static void bnx2x_stats_handle(struct bnx2x *bp, enum bnx2x_stats_event event);
1693 * General service functions
1696 static int bnx2x_acquire_hw_lock(struct bnx2x *bp, u32 resource)
1699 u32 resource_bit = (1 << resource);
1700 int func = BP_FUNC(bp);
1701 u32 hw_lock_control_reg;
1704 /* Validating that the resource is within range */
1705 if (resource > HW_LOCK_MAX_RESOURCE_VALUE) {
1707 "resource(0x%x) > HW_LOCK_MAX_RESOURCE_VALUE(0x%x)\n",
1708 resource, HW_LOCK_MAX_RESOURCE_VALUE);
1713 hw_lock_control_reg = (MISC_REG_DRIVER_CONTROL_1 + func*8);
1715 hw_lock_control_reg =
1716 (MISC_REG_DRIVER_CONTROL_7 + (func - 6)*8);
1719 /* Validating that the resource is not already taken */
1720 lock_status = REG_RD(bp, hw_lock_control_reg);
1721 if (lock_status & resource_bit) {
1722 DP(NETIF_MSG_HW, "lock_status 0x%x resource_bit 0x%x\n",
1723 lock_status, resource_bit);
1727 /* Try for 1 second every 5ms */
1728 for (cnt = 0; cnt < 200; cnt++) {
1729 /* Try to acquire the lock */
1730 REG_WR(bp, hw_lock_control_reg + 4, resource_bit);
1731 lock_status = REG_RD(bp, hw_lock_control_reg);
1732 if (lock_status & resource_bit)
1737 DP(NETIF_MSG_HW, "Timeout\n");
1741 static int bnx2x_release_hw_lock(struct bnx2x *bp, u32 resource)
1744 u32 resource_bit = (1 << resource);
1745 int func = BP_FUNC(bp);
1746 u32 hw_lock_control_reg;
1748 /* Validating that the resource is within range */
1749 if (resource > HW_LOCK_MAX_RESOURCE_VALUE) {
1751 "resource(0x%x) > HW_LOCK_MAX_RESOURCE_VALUE(0x%x)\n",
1752 resource, HW_LOCK_MAX_RESOURCE_VALUE);
1757 hw_lock_control_reg = (MISC_REG_DRIVER_CONTROL_1 + func*8);
1759 hw_lock_control_reg =
1760 (MISC_REG_DRIVER_CONTROL_7 + (func - 6)*8);
1763 /* Validating that the resource is currently taken */
1764 lock_status = REG_RD(bp, hw_lock_control_reg);
1765 if (!(lock_status & resource_bit)) {
1766 DP(NETIF_MSG_HW, "lock_status 0x%x resource_bit 0x%x\n",
1767 lock_status, resource_bit);
1771 REG_WR(bp, hw_lock_control_reg, resource_bit);
1775 /* HW Lock for shared dual port PHYs */
1776 static void bnx2x_acquire_phy_lock(struct bnx2x *bp)
1778 u32 ext_phy_type = XGXS_EXT_PHY_TYPE(bp->link_params.ext_phy_config);
1780 mutex_lock(&bp->port.phy_mutex);
1782 if ((ext_phy_type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8072) ||
1783 (ext_phy_type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073))
1784 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_8072_MDIO);
1787 static void bnx2x_release_phy_lock(struct bnx2x *bp)
1789 u32 ext_phy_type = XGXS_EXT_PHY_TYPE(bp->link_params.ext_phy_config);
1791 if ((ext_phy_type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8072) ||
1792 (ext_phy_type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073))
1793 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_8072_MDIO);
1795 mutex_unlock(&bp->port.phy_mutex);
1798 int bnx2x_set_gpio(struct bnx2x *bp, int gpio_num, u32 mode)
1800 /* The GPIO should be swapped if swap register is set and active */
1801 int gpio_port = (REG_RD(bp, NIG_REG_PORT_SWAP) &&
1802 REG_RD(bp, NIG_REG_STRAP_OVERRIDE)) ^ BP_PORT(bp);
1803 int gpio_shift = gpio_num +
1804 (gpio_port ? MISC_REGISTERS_GPIO_PORT_SHIFT : 0);
1805 u32 gpio_mask = (1 << gpio_shift);
1808 if (gpio_num > MISC_REGISTERS_GPIO_3) {
1809 BNX2X_ERR("Invalid GPIO %d\n", gpio_num);
1813 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_GPIO);
1814 /* read GPIO and mask except the float bits */
1815 gpio_reg = (REG_RD(bp, MISC_REG_GPIO) & MISC_REGISTERS_GPIO_FLOAT);
1818 case MISC_REGISTERS_GPIO_OUTPUT_LOW:
1819 DP(NETIF_MSG_LINK, "Set GPIO %d (shift %d) -> output low\n",
1820 gpio_num, gpio_shift);
1821 /* clear FLOAT and set CLR */
1822 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_FLOAT_POS);
1823 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_CLR_POS);
1826 case MISC_REGISTERS_GPIO_OUTPUT_HIGH:
1827 DP(NETIF_MSG_LINK, "Set GPIO %d (shift %d) -> output high\n",
1828 gpio_num, gpio_shift);
1829 /* clear FLOAT and set SET */
1830 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_FLOAT_POS);
1831 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_SET_POS);
1834 case MISC_REGISTERS_GPIO_INPUT_HI_Z :
1835 DP(NETIF_MSG_LINK, "Set GPIO %d (shift %d) -> input\n",
1836 gpio_num, gpio_shift);
1838 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_FLOAT_POS);
1845 REG_WR(bp, MISC_REG_GPIO, gpio_reg);
1846 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_GPIO);
1851 static int bnx2x_set_spio(struct bnx2x *bp, int spio_num, u32 mode)
1853 u32 spio_mask = (1 << spio_num);
1856 if ((spio_num < MISC_REGISTERS_SPIO_4) ||
1857 (spio_num > MISC_REGISTERS_SPIO_7)) {
1858 BNX2X_ERR("Invalid SPIO %d\n", spio_num);
1862 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_SPIO);
1863 /* read SPIO and mask except the float bits */
1864 spio_reg = (REG_RD(bp, MISC_REG_SPIO) & MISC_REGISTERS_SPIO_FLOAT);
1867 case MISC_REGISTERS_SPIO_OUTPUT_LOW :
1868 DP(NETIF_MSG_LINK, "Set SPIO %d -> output low\n", spio_num);
1869 /* clear FLOAT and set CLR */
1870 spio_reg &= ~(spio_mask << MISC_REGISTERS_SPIO_FLOAT_POS);
1871 spio_reg |= (spio_mask << MISC_REGISTERS_SPIO_CLR_POS);
1874 case MISC_REGISTERS_SPIO_OUTPUT_HIGH :
1875 DP(NETIF_MSG_LINK, "Set SPIO %d -> output high\n", spio_num);
1876 /* clear FLOAT and set SET */
1877 spio_reg &= ~(spio_mask << MISC_REGISTERS_SPIO_FLOAT_POS);
1878 spio_reg |= (spio_mask << MISC_REGISTERS_SPIO_SET_POS);
1881 case MISC_REGISTERS_SPIO_INPUT_HI_Z:
1882 DP(NETIF_MSG_LINK, "Set SPIO %d -> input\n", spio_num);
1884 spio_reg |= (spio_mask << MISC_REGISTERS_SPIO_FLOAT_POS);
1891 REG_WR(bp, MISC_REG_SPIO, spio_reg);
1892 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_SPIO);
1897 static void bnx2x_calc_fc_adv(struct bnx2x *bp)
1899 switch (bp->link_vars.ieee_fc) {
1900 case MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_NONE:
1901 bp->port.advertising &= ~(ADVERTISED_Asym_Pause |
1904 case MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH:
1905 bp->port.advertising |= (ADVERTISED_Asym_Pause |
1908 case MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC:
1909 bp->port.advertising |= ADVERTISED_Asym_Pause;
1912 bp->port.advertising &= ~(ADVERTISED_Asym_Pause |
1918 static void bnx2x_link_report(struct bnx2x *bp)
1920 if (bp->link_vars.link_up) {
1921 if (bp->state == BNX2X_STATE_OPEN)
1922 netif_carrier_on(bp->dev);
1923 printk(KERN_INFO PFX "%s NIC Link is Up, ", bp->dev->name);
1925 printk("%d Mbps ", bp->link_vars.line_speed);
1927 if (bp->link_vars.duplex == DUPLEX_FULL)
1928 printk("full duplex");
1930 printk("half duplex");
1932 if (bp->link_vars.flow_ctrl != FLOW_CTRL_NONE) {
1933 if (bp->link_vars.flow_ctrl & FLOW_CTRL_RX) {
1934 printk(", receive ");
1935 if (bp->link_vars.flow_ctrl & FLOW_CTRL_TX)
1936 printk("& transmit ");
1938 printk(", transmit ");
1940 printk("flow control ON");
1944 } else { /* link_down */
1945 netif_carrier_off(bp->dev);
1946 printk(KERN_ERR PFX "%s NIC Link is Down\n", bp->dev->name);
1950 static u8 bnx2x_initial_phy_init(struct bnx2x *bp)
1952 if (!BP_NOMCP(bp)) {
1955 /* Initialize link parameters structure variables */
1956 bp->link_params.mtu = bp->dev->mtu;
1958 bnx2x_acquire_phy_lock(bp);
1959 rc = bnx2x_phy_init(&bp->link_params, &bp->link_vars);
1960 bnx2x_release_phy_lock(bp);
1962 if (bp->link_vars.link_up)
1963 bnx2x_link_report(bp);
1965 bnx2x_calc_fc_adv(bp);
1969 BNX2X_ERR("Bootcode is missing -not initializing link\n");
1973 static void bnx2x_link_set(struct bnx2x *bp)
1975 if (!BP_NOMCP(bp)) {
1976 bnx2x_acquire_phy_lock(bp);
1977 bnx2x_phy_init(&bp->link_params, &bp->link_vars);
1978 bnx2x_release_phy_lock(bp);
1980 bnx2x_calc_fc_adv(bp);
1982 BNX2X_ERR("Bootcode is missing -not setting link\n");
1985 static void bnx2x__link_reset(struct bnx2x *bp)
1987 if (!BP_NOMCP(bp)) {
1988 bnx2x_acquire_phy_lock(bp);
1989 bnx2x_link_reset(&bp->link_params, &bp->link_vars);
1990 bnx2x_release_phy_lock(bp);
1992 BNX2X_ERR("Bootcode is missing -not resetting link\n");
1995 static u8 bnx2x_link_test(struct bnx2x *bp)
1999 bnx2x_acquire_phy_lock(bp);
2000 rc = bnx2x_test_link(&bp->link_params, &bp->link_vars);
2001 bnx2x_release_phy_lock(bp);
2006 /* Calculates the sum of vn_min_rates.
2007 It's needed for further normalizing of the min_rates.
2012 0 - if all the min_rates are 0.
2013 In the later case fainess algorithm should be deactivated.
2014 If not all min_rates are zero then those that are zeroes will
2017 static u32 bnx2x_calc_vn_wsum(struct bnx2x *bp)
2019 int i, port = BP_PORT(bp);
2023 for (i = 0; i < E1HVN_MAX; i++) {
2025 SHMEM_RD(bp, mf_cfg.func_mf_config[2*i + port].config);
2026 u32 vn_min_rate = ((vn_cfg & FUNC_MF_CFG_MIN_BW_MASK) >>
2027 FUNC_MF_CFG_MIN_BW_SHIFT) * 100;
2028 if (!(vn_cfg & FUNC_MF_CFG_FUNC_HIDE)) {
2029 /* If min rate is zero - set it to 1 */
2031 vn_min_rate = DEF_MIN_RATE;
2035 wsum += vn_min_rate;
2039 /* ... only if all min rates are zeros - disable FAIRNESS */
2046 static void bnx2x_init_port_minmax(struct bnx2x *bp,
2049 struct cmng_struct_per_port *m_cmng_port)
2051 u32 r_param = port_rate / 8;
2052 int port = BP_PORT(bp);
2055 memset(m_cmng_port, 0, sizeof(struct cmng_struct_per_port));
2057 /* Enable minmax only if we are in e1hmf mode */
2059 u32 fair_periodic_timeout_usec;
2062 /* Enable rate shaping and fairness */
2063 m_cmng_port->flags.cmng_vn_enable = 1;
2064 m_cmng_port->flags.fairness_enable = en_fness ? 1 : 0;
2065 m_cmng_port->flags.rate_shaping_enable = 1;
2068 DP(NETIF_MSG_IFUP, "All MIN values are zeroes"
2069 " fairness will be disabled\n");
2071 /* 100 usec in SDM ticks = 25 since each tick is 4 usec */
2072 m_cmng_port->rs_vars.rs_periodic_timeout =
2073 RS_PERIODIC_TIMEOUT_USEC / 4;
2075 /* this is the threshold below which no timer arming will occur
2076 1.25 coefficient is for the threshold to be a little bigger
2077 than the real time, to compensate for timer in-accuracy */
2078 m_cmng_port->rs_vars.rs_threshold =
2079 (RS_PERIODIC_TIMEOUT_USEC * r_param * 5) / 4;
2081 /* resolution of fairness timer */
2082 fair_periodic_timeout_usec = QM_ARB_BYTES / r_param;
2083 /* for 10G it is 1000usec. for 1G it is 10000usec. */
2084 t_fair = T_FAIR_COEF / port_rate;
2086 /* this is the threshold below which we won't arm
2087 the timer anymore */
2088 m_cmng_port->fair_vars.fair_threshold = QM_ARB_BYTES;
2090 /* we multiply by 1e3/8 to get bytes/msec.
2091 We don't want the credits to pass a credit
2092 of the T_FAIR*FAIR_MEM (algorithm resolution) */
2093 m_cmng_port->fair_vars.upper_bound =
2094 r_param * t_fair * FAIR_MEM;
2095 /* since each tick is 4 usec */
2096 m_cmng_port->fair_vars.fairness_timeout =
2097 fair_periodic_timeout_usec / 4;
2100 /* Disable rate shaping and fairness */
2101 m_cmng_port->flags.cmng_vn_enable = 0;
2102 m_cmng_port->flags.fairness_enable = 0;
2103 m_cmng_port->flags.rate_shaping_enable = 0;
2106 "Single function mode minmax will be disabled\n");
2109 /* Store it to internal memory */
2110 for (i = 0; i < sizeof(struct cmng_struct_per_port) / 4; i++)
2111 REG_WR(bp, BAR_XSTRORM_INTMEM +
2112 XSTORM_CMNG_PER_PORT_VARS_OFFSET(port) + i * 4,
2113 ((u32 *)(m_cmng_port))[i]);
2116 static void bnx2x_init_vn_minmax(struct bnx2x *bp, int func,
2117 u32 wsum, u16 port_rate,
2118 struct cmng_struct_per_port *m_cmng_port)
2120 struct rate_shaping_vars_per_vn m_rs_vn;
2121 struct fairness_vars_per_vn m_fair_vn;
2122 u32 vn_cfg = SHMEM_RD(bp, mf_cfg.func_mf_config[func].config);
2123 u16 vn_min_rate, vn_max_rate;
2126 /* If function is hidden - set min and max to zeroes */
2127 if (vn_cfg & FUNC_MF_CFG_FUNC_HIDE) {
2132 vn_min_rate = ((vn_cfg & FUNC_MF_CFG_MIN_BW_MASK) >>
2133 FUNC_MF_CFG_MIN_BW_SHIFT) * 100;
2134 /* If FAIRNESS is enabled (not all min rates are zeroes) and
2135 if current min rate is zero - set it to 1.
2136 This is a requirment of the algorithm. */
2137 if ((vn_min_rate == 0) && wsum)
2138 vn_min_rate = DEF_MIN_RATE;
2139 vn_max_rate = ((vn_cfg & FUNC_MF_CFG_MAX_BW_MASK) >>
2140 FUNC_MF_CFG_MAX_BW_SHIFT) * 100;
2143 DP(NETIF_MSG_IFUP, "func %d: vn_min_rate=%d vn_max_rate=%d "
2144 "wsum=%d\n", func, vn_min_rate, vn_max_rate, wsum);
2146 memset(&m_rs_vn, 0, sizeof(struct rate_shaping_vars_per_vn));
2147 memset(&m_fair_vn, 0, sizeof(struct fairness_vars_per_vn));
2149 /* global vn counter - maximal Mbps for this vn */
2150 m_rs_vn.vn_counter.rate = vn_max_rate;
2152 /* quota - number of bytes transmitted in this period */
2153 m_rs_vn.vn_counter.quota =
2154 (vn_max_rate * RS_PERIODIC_TIMEOUT_USEC) / 8;
2156 #ifdef BNX2X_PER_PROT_QOS
2157 /* per protocol counter */
2158 for (protocol = 0; protocol < NUM_OF_PROTOCOLS; protocol++) {
2159 /* maximal Mbps for this protocol */
2160 m_rs_vn.protocol_counters[protocol].rate =
2161 protocol_max_rate[protocol];
2162 /* the quota in each timer period -
2163 number of bytes transmitted in this period */
2164 m_rs_vn.protocol_counters[protocol].quota =
2165 (u32)(rs_periodic_timeout_usec *
2167 protocol_counters[protocol].rate/8));
2172 /* credit for each period of the fairness algorithm:
2173 number of bytes in T_FAIR (the vn share the port rate).
2174 wsum should not be larger than 10000, thus
2175 T_FAIR_COEF / (8 * wsum) will always be grater than zero */
2176 m_fair_vn.vn_credit_delta =
2177 max((u64)(vn_min_rate * (T_FAIR_COEF / (8 * wsum))),
2178 (u64)(m_cmng_port->fair_vars.fair_threshold * 2));
2179 DP(NETIF_MSG_IFUP, "m_fair_vn.vn_credit_delta=%d\n",
2180 m_fair_vn.vn_credit_delta);
2183 #ifdef BNX2X_PER_PROT_QOS
2185 u32 protocolWeightSum = 0;
2187 for (protocol = 0; protocol < NUM_OF_PROTOCOLS; protocol++)
2188 protocolWeightSum +=
2189 drvInit.protocol_min_rate[protocol];
2190 /* per protocol counter -
2191 NOT NEEDED IF NO PER-PROTOCOL CONGESTION MANAGEMENT */
2192 if (protocolWeightSum > 0) {
2194 protocol < NUM_OF_PROTOCOLS; protocol++)
2195 /* credit for each period of the
2196 fairness algorithm - number of bytes in
2197 T_FAIR (the protocol share the vn rate) */
2198 m_fair_vn.protocol_credit_delta[protocol] =
2199 (u32)((vn_min_rate / 8) * t_fair *
2200 protocol_min_rate / protocolWeightSum);
2205 /* Store it to internal memory */
2206 for (i = 0; i < sizeof(struct rate_shaping_vars_per_vn)/4; i++)
2207 REG_WR(bp, BAR_XSTRORM_INTMEM +
2208 XSTORM_RATE_SHAPING_PER_VN_VARS_OFFSET(func) + i * 4,
2209 ((u32 *)(&m_rs_vn))[i]);
2211 for (i = 0; i < sizeof(struct fairness_vars_per_vn)/4; i++)
2212 REG_WR(bp, BAR_XSTRORM_INTMEM +
2213 XSTORM_FAIRNESS_PER_VN_VARS_OFFSET(func) + i * 4,
2214 ((u32 *)(&m_fair_vn))[i]);
2217 /* This function is called upon link interrupt */
2218 static void bnx2x_link_attn(struct bnx2x *bp)
2222 /* Make sure that we are synced with the current statistics */
2223 bnx2x_stats_handle(bp, STATS_EVENT_STOP);
2225 bnx2x_acquire_phy_lock(bp);
2226 bnx2x_link_update(&bp->link_params, &bp->link_vars);
2227 bnx2x_release_phy_lock(bp);
2229 if (bp->link_vars.link_up) {
2231 if (bp->link_vars.mac_type == MAC_TYPE_BMAC) {
2232 struct host_port_stats *pstats;
2234 pstats = bnx2x_sp(bp, port_stats);
2235 /* reset old bmac stats */
2236 memset(&(pstats->mac_stx[0]), 0,
2237 sizeof(struct mac_stx));
2239 if ((bp->state == BNX2X_STATE_OPEN) ||
2240 (bp->state == BNX2X_STATE_DISABLED))
2241 bnx2x_stats_handle(bp, STATS_EVENT_LINK_UP);
2244 /* indicate link status */
2245 bnx2x_link_report(bp);
2250 for (vn = VN_0; vn < E1HVN_MAX; vn++) {
2251 if (vn == BP_E1HVN(bp))
2254 func = ((vn << 1) | BP_PORT(bp));
2256 /* Set the attention towards other drivers
2258 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_0 +
2259 (LINK_SYNC_ATTENTION_BIT_FUNC_0 + func)*4, 1);
2263 if (CHIP_IS_E1H(bp) && (bp->link_vars.line_speed > 0)) {
2264 struct cmng_struct_per_port m_cmng_port;
2266 int port = BP_PORT(bp);
2268 /* Init RATE SHAPING and FAIRNESS contexts */
2269 wsum = bnx2x_calc_vn_wsum(bp);
2270 bnx2x_init_port_minmax(bp, (int)wsum,
2271 bp->link_vars.line_speed,
2274 for (vn = VN_0; vn < E1HVN_MAX; vn++)
2275 bnx2x_init_vn_minmax(bp, 2*vn + port,
2276 wsum, bp->link_vars.line_speed,
2281 static void bnx2x__link_status_update(struct bnx2x *bp)
2283 if (bp->state != BNX2X_STATE_OPEN)
2286 bnx2x_link_status_update(&bp->link_params, &bp->link_vars);
2288 if (bp->link_vars.link_up)
2289 bnx2x_stats_handle(bp, STATS_EVENT_LINK_UP);
2291 bnx2x_stats_handle(bp, STATS_EVENT_STOP);
2293 /* indicate link status */
2294 bnx2x_link_report(bp);
2297 static void bnx2x_pmf_update(struct bnx2x *bp)
2299 int port = BP_PORT(bp);
2303 DP(NETIF_MSG_LINK, "pmf %d\n", bp->port.pmf);
2305 /* enable nig attention */
2306 val = (0xff0f | (1 << (BP_E1HVN(bp) + 4)));
2307 REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, val);
2308 REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, val);
2310 bnx2x_stats_handle(bp, STATS_EVENT_PMF);
2318 * General service functions
2321 /* the slow path queue is odd since completions arrive on the fastpath ring */
2322 static int bnx2x_sp_post(struct bnx2x *bp, int command, int cid,
2323 u32 data_hi, u32 data_lo, int common)
2325 int func = BP_FUNC(bp);
2327 DP(BNX2X_MSG_SP/*NETIF_MSG_TIMER*/,
2328 "SPQE (%x:%x) command %d hw_cid %x data (%x:%x) left %x\n",
2329 (u32)U64_HI(bp->spq_mapping), (u32)(U64_LO(bp->spq_mapping) +
2330 (void *)bp->spq_prod_bd - (void *)bp->spq), command,
2331 HW_CID(bp, cid), data_hi, data_lo, bp->spq_left);
2333 #ifdef BNX2X_STOP_ON_ERROR
2334 if (unlikely(bp->panic))
2338 spin_lock_bh(&bp->spq_lock);
2340 if (!bp->spq_left) {
2341 BNX2X_ERR("BUG! SPQ ring full!\n");
2342 spin_unlock_bh(&bp->spq_lock);
2347 /* CID needs port number to be encoded int it */
2348 bp->spq_prod_bd->hdr.conn_and_cmd_data =
2349 cpu_to_le32(((command << SPE_HDR_CMD_ID_SHIFT) |
2351 bp->spq_prod_bd->hdr.type = cpu_to_le16(ETH_CONNECTION_TYPE);
2353 bp->spq_prod_bd->hdr.type |=
2354 cpu_to_le16((1 << SPE_HDR_COMMON_RAMROD_SHIFT));
2356 bp->spq_prod_bd->data.mac_config_addr.hi = cpu_to_le32(data_hi);
2357 bp->spq_prod_bd->data.mac_config_addr.lo = cpu_to_le32(data_lo);
2361 if (bp->spq_prod_bd == bp->spq_last_bd) {
2362 bp->spq_prod_bd = bp->spq;
2363 bp->spq_prod_idx = 0;
2364 DP(NETIF_MSG_TIMER, "end of spq\n");
2371 REG_WR(bp, BAR_XSTRORM_INTMEM + XSTORM_SPQ_PROD_OFFSET(func),
2374 spin_unlock_bh(&bp->spq_lock);
2378 /* acquire split MCP access lock register */
2379 static int bnx2x_acquire_alr(struct bnx2x *bp)
2386 for (j = 0; j < i*10; j++) {
2388 REG_WR(bp, GRCBASE_MCP + 0x9c, val);
2389 val = REG_RD(bp, GRCBASE_MCP + 0x9c);
2390 if (val & (1L << 31))
2395 if (!(val & (1L << 31))) {
2396 BNX2X_ERR("Cannot acquire MCP access lock register\n");
2403 /* release split MCP access lock register */
2404 static void bnx2x_release_alr(struct bnx2x *bp)
2408 REG_WR(bp, GRCBASE_MCP + 0x9c, val);
2411 static inline u16 bnx2x_update_dsb_idx(struct bnx2x *bp)
2413 struct host_def_status_block *def_sb = bp->def_status_blk;
2416 barrier(); /* status block is written to by the chip */
2417 if (bp->def_att_idx != def_sb->atten_status_block.attn_bits_index) {
2418 bp->def_att_idx = def_sb->atten_status_block.attn_bits_index;
2421 if (bp->def_c_idx != def_sb->c_def_status_block.status_block_index) {
2422 bp->def_c_idx = def_sb->c_def_status_block.status_block_index;
2425 if (bp->def_u_idx != def_sb->u_def_status_block.status_block_index) {
2426 bp->def_u_idx = def_sb->u_def_status_block.status_block_index;
2429 if (bp->def_x_idx != def_sb->x_def_status_block.status_block_index) {
2430 bp->def_x_idx = def_sb->x_def_status_block.status_block_index;
2433 if (bp->def_t_idx != def_sb->t_def_status_block.status_block_index) {
2434 bp->def_t_idx = def_sb->t_def_status_block.status_block_index;
2441 * slow path service functions
2444 static void bnx2x_attn_int_asserted(struct bnx2x *bp, u32 asserted)
2446 int port = BP_PORT(bp);
2447 int func = BP_FUNC(bp);
2448 u32 igu_addr = (IGU_ADDR_ATTN_BITS_SET + IGU_FUNC_BASE * func) * 8;
2449 u32 aeu_addr = port ? MISC_REG_AEU_MASK_ATTN_FUNC_1 :
2450 MISC_REG_AEU_MASK_ATTN_FUNC_0;
2451 u32 nig_int_mask_addr = port ? NIG_REG_MASK_INTERRUPT_PORT1 :
2452 NIG_REG_MASK_INTERRUPT_PORT0;
2455 if (bp->attn_state & asserted)
2456 BNX2X_ERR("IGU ERROR\n");
2458 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port);
2459 aeu_mask = REG_RD(bp, aeu_addr);
2461 DP(NETIF_MSG_HW, "aeu_mask %x newly asserted %x\n",
2462 aeu_mask, asserted);
2463 aeu_mask &= ~(asserted & 0xff);
2464 DP(NETIF_MSG_HW, "new mask %x\n", aeu_mask);
2466 REG_WR(bp, aeu_addr, aeu_mask);
2467 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port);
2469 DP(NETIF_MSG_HW, "attn_state %x\n", bp->attn_state);
2470 bp->attn_state |= asserted;
2471 DP(NETIF_MSG_HW, "new state %x\n", bp->attn_state);
2473 if (asserted & ATTN_HARD_WIRED_MASK) {
2474 if (asserted & ATTN_NIG_FOR_FUNC) {
2476 /* save nig interrupt mask */
2477 bp->nig_mask = REG_RD(bp, nig_int_mask_addr);
2478 REG_WR(bp, nig_int_mask_addr, 0);
2480 bnx2x_link_attn(bp);
2482 /* handle unicore attn? */
2484 if (asserted & ATTN_SW_TIMER_4_FUNC)
2485 DP(NETIF_MSG_HW, "ATTN_SW_TIMER_4_FUNC!\n");
2487 if (asserted & GPIO_2_FUNC)
2488 DP(NETIF_MSG_HW, "GPIO_2_FUNC!\n");
2490 if (asserted & GPIO_3_FUNC)
2491 DP(NETIF_MSG_HW, "GPIO_3_FUNC!\n");
2493 if (asserted & GPIO_4_FUNC)
2494 DP(NETIF_MSG_HW, "GPIO_4_FUNC!\n");
2497 if (asserted & ATTN_GENERAL_ATTN_1) {
2498 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_1!\n");
2499 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_1, 0x0);
2501 if (asserted & ATTN_GENERAL_ATTN_2) {
2502 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_2!\n");
2503 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_2, 0x0);
2505 if (asserted & ATTN_GENERAL_ATTN_3) {
2506 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_3!\n");
2507 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_3, 0x0);
2510 if (asserted & ATTN_GENERAL_ATTN_4) {
2511 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_4!\n");
2512 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_4, 0x0);
2514 if (asserted & ATTN_GENERAL_ATTN_5) {
2515 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_5!\n");
2516 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_5, 0x0);
2518 if (asserted & ATTN_GENERAL_ATTN_6) {
2519 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_6!\n");
2520 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_6, 0x0);
2524 } /* if hardwired */
2526 DP(NETIF_MSG_HW, "about to mask 0x%08x at IGU addr 0x%x\n",
2527 asserted, BAR_IGU_INTMEM + igu_addr);
2528 REG_WR(bp, BAR_IGU_INTMEM + igu_addr, asserted);
2530 /* now set back the mask */
2531 if (asserted & ATTN_NIG_FOR_FUNC)
2532 REG_WR(bp, nig_int_mask_addr, bp->nig_mask);
2535 static inline void bnx2x_attn_int_deasserted0(struct bnx2x *bp, u32 attn)
2537 int port = BP_PORT(bp);
2541 reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 :
2542 MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0);
2544 if (attn & AEU_INPUTS_ATTN_BITS_SPIO5) {
2546 val = REG_RD(bp, reg_offset);
2547 val &= ~AEU_INPUTS_ATTN_BITS_SPIO5;
2548 REG_WR(bp, reg_offset, val);
2550 BNX2X_ERR("SPIO5 hw attention\n");
2552 switch (bp->common.board & SHARED_HW_CFG_BOARD_TYPE_MASK) {
2553 case SHARED_HW_CFG_BOARD_TYPE_BCM957710A1022G:
2554 /* Fan failure attention */
2556 /* The PHY reset is controled by GPIO 1 */
2557 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_1,
2558 MISC_REGISTERS_GPIO_OUTPUT_LOW);
2559 /* Low power mode is controled by GPIO 2 */
2560 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2,
2561 MISC_REGISTERS_GPIO_OUTPUT_LOW);
2562 /* mark the failure */
2563 bp->link_params.ext_phy_config &=
2564 ~PORT_HW_CFG_XGXS_EXT_PHY_TYPE_MASK;
2565 bp->link_params.ext_phy_config |=
2566 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE;
2568 dev_info.port_hw_config[port].
2569 external_phy_config,
2570 bp->link_params.ext_phy_config);
2571 /* log the failure */
2572 printk(KERN_ERR PFX "Fan Failure on Network"
2573 " Controller %s has caused the driver to"
2574 " shutdown the card to prevent permanent"
2575 " damage. Please contact Dell Support for"
2576 " assistance\n", bp->dev->name);
2584 if (attn & HW_INTERRUT_ASSERT_SET_0) {
2586 val = REG_RD(bp, reg_offset);
2587 val &= ~(attn & HW_INTERRUT_ASSERT_SET_0);
2588 REG_WR(bp, reg_offset, val);
2590 BNX2X_ERR("FATAL HW block attention set0 0x%x\n",
2591 (attn & HW_INTERRUT_ASSERT_SET_0));
2596 static inline void bnx2x_attn_int_deasserted1(struct bnx2x *bp, u32 attn)
2600 if (attn & BNX2X_DOORQ_ASSERT) {
2602 val = REG_RD(bp, DORQ_REG_DORQ_INT_STS_CLR);
2603 BNX2X_ERR("DB hw attention 0x%x\n", val);
2604 /* DORQ discard attention */
2606 BNX2X_ERR("FATAL error from DORQ\n");
2609 if (attn & HW_INTERRUT_ASSERT_SET_1) {
2611 int port = BP_PORT(bp);
2614 reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_1 :
2615 MISC_REG_AEU_ENABLE1_FUNC_0_OUT_1);
2617 val = REG_RD(bp, reg_offset);
2618 val &= ~(attn & HW_INTERRUT_ASSERT_SET_1);
2619 REG_WR(bp, reg_offset, val);
2621 BNX2X_ERR("FATAL HW block attention set1 0x%x\n",
2622 (attn & HW_INTERRUT_ASSERT_SET_1));
2627 static inline void bnx2x_attn_int_deasserted2(struct bnx2x *bp, u32 attn)
2631 if (attn & AEU_INPUTS_ATTN_BITS_CFC_HW_INTERRUPT) {
2633 val = REG_RD(bp, CFC_REG_CFC_INT_STS_CLR);
2634 BNX2X_ERR("CFC hw attention 0x%x\n", val);
2635 /* CFC error attention */
2637 BNX2X_ERR("FATAL error from CFC\n");
2640 if (attn & AEU_INPUTS_ATTN_BITS_PXP_HW_INTERRUPT) {
2642 val = REG_RD(bp, PXP_REG_PXP_INT_STS_CLR_0);
2643 BNX2X_ERR("PXP hw attention 0x%x\n", val);
2644 /* RQ_USDMDP_FIFO_OVERFLOW */
2646 BNX2X_ERR("FATAL error from PXP\n");
2649 if (attn & HW_INTERRUT_ASSERT_SET_2) {
2651 int port = BP_PORT(bp);
2654 reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_2 :
2655 MISC_REG_AEU_ENABLE1_FUNC_0_OUT_2);
2657 val = REG_RD(bp, reg_offset);
2658 val &= ~(attn & HW_INTERRUT_ASSERT_SET_2);
2659 REG_WR(bp, reg_offset, val);
2661 BNX2X_ERR("FATAL HW block attention set2 0x%x\n",
2662 (attn & HW_INTERRUT_ASSERT_SET_2));
2667 static inline void bnx2x_attn_int_deasserted3(struct bnx2x *bp, u32 attn)
2671 if (attn & EVEREST_GEN_ATTN_IN_USE_MASK) {
2673 if (attn & BNX2X_PMF_LINK_ASSERT) {
2674 int func = BP_FUNC(bp);
2676 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_12 + func*4, 0);
2677 bnx2x__link_status_update(bp);
2678 if (SHMEM_RD(bp, func_mb[func].drv_status) &
2680 bnx2x_pmf_update(bp);
2682 } else if (attn & BNX2X_MC_ASSERT_BITS) {
2684 BNX2X_ERR("MC assert!\n");
2685 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_10, 0);
2686 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_9, 0);
2687 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_8, 0);
2688 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_7, 0);
2691 } else if (attn & BNX2X_MCP_ASSERT) {
2693 BNX2X_ERR("MCP assert!\n");
2694 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_11, 0);
2698 BNX2X_ERR("Unknown HW assert! (attn 0x%x)\n", attn);
2701 if (attn & EVEREST_LATCHED_ATTN_IN_USE_MASK) {
2702 BNX2X_ERR("LATCHED attention 0x%08x (masked)\n", attn);
2703 if (attn & BNX2X_GRC_TIMEOUT) {
2704 val = CHIP_IS_E1H(bp) ?
2705 REG_RD(bp, MISC_REG_GRC_TIMEOUT_ATTN) : 0;
2706 BNX2X_ERR("GRC time-out 0x%08x\n", val);
2708 if (attn & BNX2X_GRC_RSV) {
2709 val = CHIP_IS_E1H(bp) ?
2710 REG_RD(bp, MISC_REG_GRC_RSV_ATTN) : 0;
2711 BNX2X_ERR("GRC reserved 0x%08x\n", val);
2713 REG_WR(bp, MISC_REG_AEU_CLR_LATCH_SIGNAL, 0x7ff);
2717 static void bnx2x_attn_int_deasserted(struct bnx2x *bp, u32 deasserted)
2719 struct attn_route attn;
2720 struct attn_route group_mask;
2721 int port = BP_PORT(bp);
2727 /* need to take HW lock because MCP or other port might also
2728 try to handle this event */
2729 bnx2x_acquire_alr(bp);
2731 attn.sig[0] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_1_FUNC_0 + port*4);
2732 attn.sig[1] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_2_FUNC_0 + port*4);
2733 attn.sig[2] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_3_FUNC_0 + port*4);
2734 attn.sig[3] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_4_FUNC_0 + port*4);
2735 DP(NETIF_MSG_HW, "attn: %08x %08x %08x %08x\n",
2736 attn.sig[0], attn.sig[1], attn.sig[2], attn.sig[3]);
2738 for (index = 0; index < MAX_DYNAMIC_ATTN_GRPS; index++) {
2739 if (deasserted & (1 << index)) {
2740 group_mask = bp->attn_group[index];
2742 DP(NETIF_MSG_HW, "group[%d]: %08x %08x %08x %08x\n",
2743 index, group_mask.sig[0], group_mask.sig[1],
2744 group_mask.sig[2], group_mask.sig[3]);
2746 bnx2x_attn_int_deasserted3(bp,
2747 attn.sig[3] & group_mask.sig[3]);
2748 bnx2x_attn_int_deasserted1(bp,
2749 attn.sig[1] & group_mask.sig[1]);
2750 bnx2x_attn_int_deasserted2(bp,
2751 attn.sig[2] & group_mask.sig[2]);
2752 bnx2x_attn_int_deasserted0(bp,
2753 attn.sig[0] & group_mask.sig[0]);
2755 if ((attn.sig[0] & group_mask.sig[0] &
2756 HW_PRTY_ASSERT_SET_0) ||
2757 (attn.sig[1] & group_mask.sig[1] &
2758 HW_PRTY_ASSERT_SET_1) ||
2759 (attn.sig[2] & group_mask.sig[2] &
2760 HW_PRTY_ASSERT_SET_2))
2761 BNX2X_ERR("FATAL HW block parity attention\n");
2765 bnx2x_release_alr(bp);
2767 reg_addr = (IGU_ADDR_ATTN_BITS_CLR + IGU_FUNC_BASE * BP_FUNC(bp)) * 8;
2770 DP(NETIF_MSG_HW, "about to mask 0x%08x at HC addr 0x%x\n",
2772 REG_WR(bp, BAR_IGU_INTMEM + reg_addr, val);
2774 if (~bp->attn_state & deasserted)
2775 BNX2X_ERR("IGU ERROR\n");
2777 reg_addr = port ? MISC_REG_AEU_MASK_ATTN_FUNC_1 :
2778 MISC_REG_AEU_MASK_ATTN_FUNC_0;
2780 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port);
2781 aeu_mask = REG_RD(bp, reg_addr);
2783 DP(NETIF_MSG_HW, "aeu_mask %x newly deasserted %x\n",
2784 aeu_mask, deasserted);
2785 aeu_mask |= (deasserted & 0xff);
2786 DP(NETIF_MSG_HW, "new mask %x\n", aeu_mask);
2788 REG_WR(bp, reg_addr, aeu_mask);
2789 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port);
2791 DP(NETIF_MSG_HW, "attn_state %x\n", bp->attn_state);
2792 bp->attn_state &= ~deasserted;
2793 DP(NETIF_MSG_HW, "new state %x\n", bp->attn_state);
2796 static void bnx2x_attn_int(struct bnx2x *bp)
2798 /* read local copy of bits */
2799 u32 attn_bits = bp->def_status_blk->atten_status_block.attn_bits;
2800 u32 attn_ack = bp->def_status_blk->atten_status_block.attn_bits_ack;
2801 u32 attn_state = bp->attn_state;
2803 /* look for changed bits */
2804 u32 asserted = attn_bits & ~attn_ack & ~attn_state;
2805 u32 deasserted = ~attn_bits & attn_ack & attn_state;
2808 "attn_bits %x attn_ack %x asserted %x deasserted %x\n",
2809 attn_bits, attn_ack, asserted, deasserted);
2811 if (~(attn_bits ^ attn_ack) & (attn_bits ^ attn_state))
2812 BNX2X_ERR("BAD attention state\n");
2814 /* handle bits that were raised */
2816 bnx2x_attn_int_asserted(bp, asserted);
2819 bnx2x_attn_int_deasserted(bp, deasserted);
2822 static void bnx2x_sp_task(struct work_struct *work)
2824 struct bnx2x *bp = container_of(work, struct bnx2x, sp_task);
2828 /* Return here if interrupt is disabled */
2829 if (unlikely(atomic_read(&bp->intr_sem) != 0)) {
2830 DP(BNX2X_MSG_SP, "called but intr_sem not 0, returning\n");
2834 status = bnx2x_update_dsb_idx(bp);
2835 /* if (status == 0) */
2836 /* BNX2X_ERR("spurious slowpath interrupt!\n"); */
2838 DP(BNX2X_MSG_SP, "got a slowpath interrupt (updated %x)\n", status);
2844 /* CStorm events: query_stats, port delete ramrod */
2846 bp->stats_pending = 0;
2848 bnx2x_ack_sb(bp, DEF_SB_ID, ATTENTION_ID, bp->def_att_idx,
2850 bnx2x_ack_sb(bp, DEF_SB_ID, USTORM_ID, le16_to_cpu(bp->def_u_idx),
2852 bnx2x_ack_sb(bp, DEF_SB_ID, CSTORM_ID, le16_to_cpu(bp->def_c_idx),
2854 bnx2x_ack_sb(bp, DEF_SB_ID, XSTORM_ID, le16_to_cpu(bp->def_x_idx),
2856 bnx2x_ack_sb(bp, DEF_SB_ID, TSTORM_ID, le16_to_cpu(bp->def_t_idx),
2861 static irqreturn_t bnx2x_msix_sp_int(int irq, void *dev_instance)
2863 struct net_device *dev = dev_instance;
2864 struct bnx2x *bp = netdev_priv(dev);
2866 /* Return here if interrupt is disabled */
2867 if (unlikely(atomic_read(&bp->intr_sem) != 0)) {
2868 DP(BNX2X_MSG_SP, "called but intr_sem not 0, returning\n");
2872 bnx2x_ack_sb(bp, DEF_SB_ID, XSTORM_ID, 0, IGU_INT_DISABLE, 0);
2874 #ifdef BNX2X_STOP_ON_ERROR
2875 if (unlikely(bp->panic))
2879 schedule_work(&bp->sp_task);
2884 /* end of slow path */
2888 /****************************************************************************
2890 ****************************************************************************/
2892 /* sum[hi:lo] += add[hi:lo] */
2893 #define ADD_64(s_hi, a_hi, s_lo, a_lo) \
2896 s_hi += a_hi + (s_lo < a_lo) ? 1 : 0; \
2899 /* difference = minuend - subtrahend */
2900 #define DIFF_64(d_hi, m_hi, s_hi, d_lo, m_lo, s_lo) \
2902 if (m_lo < s_lo) { \
2904 d_hi = m_hi - s_hi; \
2906 /* we can 'loan' 1 */ \
2908 d_lo = m_lo + (UINT_MAX - s_lo) + 1; \
2910 /* m_hi <= s_hi */ \
2915 /* m_lo >= s_lo */ \
2916 if (m_hi < s_hi) { \
2920 /* m_hi >= s_hi */ \
2921 d_hi = m_hi - s_hi; \
2922 d_lo = m_lo - s_lo; \
2927 #define UPDATE_STAT64(s, t) \
2929 DIFF_64(diff.hi, new->s##_hi, pstats->mac_stx[0].t##_hi, \
2930 diff.lo, new->s##_lo, pstats->mac_stx[0].t##_lo); \
2931 pstats->mac_stx[0].t##_hi = new->s##_hi; \
2932 pstats->mac_stx[0].t##_lo = new->s##_lo; \
2933 ADD_64(pstats->mac_stx[1].t##_hi, diff.hi, \
2934 pstats->mac_stx[1].t##_lo, diff.lo); \
2937 #define UPDATE_STAT64_NIG(s, t) \
2939 DIFF_64(diff.hi, new->s##_hi, old->s##_hi, \
2940 diff.lo, new->s##_lo, old->s##_lo); \
2941 ADD_64(estats->t##_hi, diff.hi, \
2942 estats->t##_lo, diff.lo); \
2945 /* sum[hi:lo] += add */
2946 #define ADD_EXTEND_64(s_hi, s_lo, a) \
2949 s_hi += (s_lo < a) ? 1 : 0; \
2952 #define UPDATE_EXTEND_STAT(s) \
2954 ADD_EXTEND_64(pstats->mac_stx[1].s##_hi, \
2955 pstats->mac_stx[1].s##_lo, \
2959 #define UPDATE_EXTEND_TSTAT(s, t) \
2961 diff = le32_to_cpu(tclient->s) - old_tclient->s; \
2962 old_tclient->s = le32_to_cpu(tclient->s); \
2963 ADD_EXTEND_64(fstats->t##_hi, fstats->t##_lo, diff); \
2966 #define UPDATE_EXTEND_XSTAT(s, t) \
2968 diff = le32_to_cpu(xclient->s) - old_xclient->s; \
2969 old_xclient->s = le32_to_cpu(xclient->s); \
2970 ADD_EXTEND_64(fstats->t##_hi, fstats->t##_lo, diff); \
2974 * General service functions
2977 static inline long bnx2x_hilo(u32 *hiref)
2979 u32 lo = *(hiref + 1);
2980 #if (BITS_PER_LONG == 64)
2983 return HILO_U64(hi, lo);
2990 * Init service functions
2993 static void bnx2x_storm_stats_post(struct bnx2x *bp)
2995 if (!bp->stats_pending) {
2996 struct eth_query_ramrod_data ramrod_data = {0};
2999 ramrod_data.drv_counter = bp->stats_counter++;
3000 ramrod_data.collect_port_1b = bp->port.pmf ? 1 : 0;
3001 ramrod_data.ctr_id_vector = (1 << BP_CL_ID(bp));
3003 rc = bnx2x_sp_post(bp, RAMROD_CMD_ID_ETH_STAT_QUERY, 0,
3004 ((u32 *)&ramrod_data)[1],
3005 ((u32 *)&ramrod_data)[0], 0);
3007 /* stats ramrod has it's own slot on the spq */
3009 bp->stats_pending = 1;
3014 static void bnx2x_stats_init(struct bnx2x *bp)
3016 int port = BP_PORT(bp);
3018 bp->executer_idx = 0;
3019 bp->stats_counter = 0;
3023 bp->port.port_stx = SHMEM_RD(bp, port_mb[port].port_stx);
3025 bp->port.port_stx = 0;
3026 DP(BNX2X_MSG_STATS, "port_stx 0x%x\n", bp->port.port_stx);
3028 memset(&(bp->port.old_nig_stats), 0, sizeof(struct nig_stats));
3029 bp->port.old_nig_stats.brb_discard =
3030 REG_RD(bp, NIG_REG_STAT0_BRB_DISCARD + port*0x38);
3031 bp->port.old_nig_stats.brb_truncate =
3032 REG_RD(bp, NIG_REG_STAT0_BRB_TRUNCATE + port*0x38);
3033 REG_RD_DMAE(bp, NIG_REG_STAT0_EGRESS_MAC_PKT0 + port*0x50,
3034 &(bp->port.old_nig_stats.egress_mac_pkt0_lo), 2);
3035 REG_RD_DMAE(bp, NIG_REG_STAT0_EGRESS_MAC_PKT1 + port*0x50,
3036 &(bp->port.old_nig_stats.egress_mac_pkt1_lo), 2);
3038 /* function stats */
3039 memset(&bp->dev->stats, 0, sizeof(struct net_device_stats));
3040 memset(&bp->old_tclient, 0, sizeof(struct tstorm_per_client_stats));
3041 memset(&bp->old_xclient, 0, sizeof(struct xstorm_per_client_stats));
3042 memset(&bp->eth_stats, 0, sizeof(struct bnx2x_eth_stats));
3044 bp->stats_state = STATS_STATE_DISABLED;
3045 if (IS_E1HMF(bp) && bp->port.pmf && bp->port.port_stx)
3046 bnx2x_stats_handle(bp, STATS_EVENT_PMF);
3049 static void bnx2x_hw_stats_post(struct bnx2x *bp)
3051 struct dmae_command *dmae = &bp->stats_dmae;
3052 u32 *stats_comp = bnx2x_sp(bp, stats_comp);
3054 *stats_comp = DMAE_COMP_VAL;
3057 if (bp->executer_idx) {
3058 int loader_idx = PMF_DMAE_C(bp);
3060 memset(dmae, 0, sizeof(struct dmae_command));
3062 dmae->opcode = (DMAE_CMD_SRC_PCI | DMAE_CMD_DST_GRC |
3063 DMAE_CMD_C_DST_GRC | DMAE_CMD_C_ENABLE |
3064 DMAE_CMD_DST_RESET |
3066 DMAE_CMD_ENDIANITY_B_DW_SWAP |
3068 DMAE_CMD_ENDIANITY_DW_SWAP |
3070 (BP_PORT(bp) ? DMAE_CMD_PORT_1 :
3072 (BP_E1HVN(bp) << DMAE_CMD_E1HVN_SHIFT));
3073 dmae->src_addr_lo = U64_LO(bnx2x_sp_mapping(bp, dmae[0]));
3074 dmae->src_addr_hi = U64_HI(bnx2x_sp_mapping(bp, dmae[0]));
3075 dmae->dst_addr_lo = (DMAE_REG_CMD_MEM +
3076 sizeof(struct dmae_command) *
3077 (loader_idx + 1)) >> 2;
3078 dmae->dst_addr_hi = 0;
3079 dmae->len = sizeof(struct dmae_command) >> 2;
3082 dmae->comp_addr_lo = dmae_reg_go_c[loader_idx + 1] >> 2;
3083 dmae->comp_addr_hi = 0;
3087 bnx2x_post_dmae(bp, dmae, loader_idx);
3089 } else if (bp->func_stx) {
3091 bnx2x_post_dmae(bp, dmae, INIT_DMAE_C(bp));
3095 static int bnx2x_stats_comp(struct bnx2x *bp)
3097 u32 *stats_comp = bnx2x_sp(bp, stats_comp);
3101 while (*stats_comp != DMAE_COMP_VAL) {
3104 BNX2X_ERR("timeout waiting for stats finished\n");
3113 * Statistics service functions
3116 static void bnx2x_stats_pmf_update(struct bnx2x *bp)
3118 struct dmae_command *dmae;
3120 int loader_idx = PMF_DMAE_C(bp);
3121 u32 *stats_comp = bnx2x_sp(bp, stats_comp);
3124 if (!IS_E1HMF(bp) || !bp->port.pmf || !bp->port.port_stx) {
3125 BNX2X_ERR("BUG!\n");
3129 bp->executer_idx = 0;
3131 opcode = (DMAE_CMD_SRC_GRC | DMAE_CMD_DST_PCI |
3133 DMAE_CMD_SRC_RESET | DMAE_CMD_DST_RESET |
3135 DMAE_CMD_ENDIANITY_B_DW_SWAP |
3137 DMAE_CMD_ENDIANITY_DW_SWAP |
3139 (BP_PORT(bp) ? DMAE_CMD_PORT_1 : DMAE_CMD_PORT_0) |
3140 (BP_E1HVN(bp) << DMAE_CMD_E1HVN_SHIFT));
3142 dmae = bnx2x_sp(bp, dmae[bp->executer_idx++]);
3143 dmae->opcode = (opcode | DMAE_CMD_C_DST_GRC);
3144 dmae->src_addr_lo = bp->port.port_stx >> 2;
3145 dmae->src_addr_hi = 0;
3146 dmae->dst_addr_lo = U64_LO(bnx2x_sp_mapping(bp, port_stats));
3147 dmae->dst_addr_hi = U64_HI(bnx2x_sp_mapping(bp, port_stats));
3148 dmae->len = DMAE_LEN32_RD_MAX;
3149 dmae->comp_addr_lo = dmae_reg_go_c[loader_idx] >> 2;
3150 dmae->comp_addr_hi = 0;
3153 dmae = bnx2x_sp(bp, dmae[bp->executer_idx++]);
3154 dmae->opcode = (opcode | DMAE_CMD_C_DST_PCI);
3155 dmae->src_addr_lo = (bp->port.port_stx >> 2) + DMAE_LEN32_RD_MAX;
3156 dmae->src_addr_hi = 0;
3157 dmae->dst_addr_lo = U64_LO(bnx2x_sp_mapping(bp, port_stats) +
3158 DMAE_LEN32_RD_MAX * 4);
3159 dmae->dst_addr_hi = U64_HI(bnx2x_sp_mapping(bp, port_stats) +
3160 DMAE_LEN32_RD_MAX * 4);
3161 dmae->len = (sizeof(struct host_port_stats) >> 2) - DMAE_LEN32_RD_MAX;
3162 dmae->comp_addr_lo = U64_LO(bnx2x_sp_mapping(bp, stats_comp));
3163 dmae->comp_addr_hi = U64_HI(bnx2x_sp_mapping(bp, stats_comp));
3164 dmae->comp_val = DMAE_COMP_VAL;
3167 bnx2x_hw_stats_post(bp);
3168 bnx2x_stats_comp(bp);
3171 static void bnx2x_port_stats_init(struct bnx2x *bp)
3173 struct dmae_command *dmae;
3174 int port = BP_PORT(bp);
3175 int vn = BP_E1HVN(bp);
3177 int loader_idx = PMF_DMAE_C(bp);
3179 u32 *stats_comp = bnx2x_sp(bp, stats_comp);
3182 if (!bp->link_vars.link_up || !bp->port.pmf) {
3183 BNX2X_ERR("BUG!\n");
3187 bp->executer_idx = 0;
3190 opcode = (DMAE_CMD_SRC_PCI | DMAE_CMD_DST_GRC |
3191 DMAE_CMD_C_DST_GRC | DMAE_CMD_C_ENABLE |
3192 DMAE_CMD_SRC_RESET | DMAE_CMD_DST_RESET |
3194 DMAE_CMD_ENDIANITY_B_DW_SWAP |
3196 DMAE_CMD_ENDIANITY_DW_SWAP |
3198 (port ? DMAE_CMD_PORT_1 : DMAE_CMD_PORT_0) |
3199 (vn << DMAE_CMD_E1HVN_SHIFT));
3201 if (bp->port.port_stx) {
3203 dmae = bnx2x_sp(bp, dmae[bp->executer_idx++]);
3204 dmae->opcode = opcode;
3205 dmae->src_addr_lo = U64_LO(bnx2x_sp_mapping(bp, port_stats));
3206 dmae->src_addr_hi = U64_HI(bnx2x_sp_mapping(bp, port_stats));
3207 dmae->dst_addr_lo = bp->port.port_stx >> 2;
3208 dmae->dst_addr_hi = 0;
3209 dmae->len = sizeof(struct host_port_stats) >> 2;
3210 dmae->comp_addr_lo = dmae_reg_go_c[loader_idx] >> 2;
3211 dmae->comp_addr_hi = 0;
3217 dmae = bnx2x_sp(bp, dmae[bp->executer_idx++]);
3218 dmae->opcode = opcode;
3219 dmae->src_addr_lo = U64_LO(bnx2x_sp_mapping(bp, func_stats));
3220 dmae->src_addr_hi = U64_HI(bnx2x_sp_mapping(bp, func_stats));
3221 dmae->dst_addr_lo = bp->func_stx >> 2;
3222 dmae->dst_addr_hi = 0;
3223 dmae->len = sizeof(struct host_func_stats) >> 2;
3224 dmae->comp_addr_lo = dmae_reg_go_c[loader_idx] >> 2;
3225 dmae->comp_addr_hi = 0;
3230 opcode = (DMAE_CMD_SRC_GRC | DMAE_CMD_DST_PCI |
3231 DMAE_CMD_C_DST_GRC | DMAE_CMD_C_ENABLE |
3232 DMAE_CMD_SRC_RESET | DMAE_CMD_DST_RESET |
3234 DMAE_CMD_ENDIANITY_B_DW_SWAP |
3236 DMAE_CMD_ENDIANITY_DW_SWAP |
3238 (port ? DMAE_CMD_PORT_1 : DMAE_CMD_PORT_0) |
3239 (vn << DMAE_CMD_E1HVN_SHIFT));
3241 if (bp->link_vars.mac_type == MAC_TYPE_BMAC) {
3243 mac_addr = (port ? NIG_REG_INGRESS_BMAC1_MEM :
3244 NIG_REG_INGRESS_BMAC0_MEM);
3246 /* BIGMAC_REGISTER_TX_STAT_GTPKT ..
3247 BIGMAC_REGISTER_TX_STAT_GTBYT */
3248 dmae = bnx2x_sp(bp, dmae[bp->executer_idx++]);
3249 dmae->opcode = opcode;
3250 dmae->src_addr_lo = (mac_addr +
3251 BIGMAC_REGISTER_TX_STAT_GTPKT) >> 2;
3252 dmae->src_addr_hi = 0;
3253 dmae->dst_addr_lo = U64_LO(bnx2x_sp_mapping(bp, mac_stats));
3254 dmae->dst_addr_hi = U64_HI(bnx2x_sp_mapping(bp, mac_stats));
3255 dmae->len = (8 + BIGMAC_REGISTER_TX_STAT_GTBYT -
3256 BIGMAC_REGISTER_TX_STAT_GTPKT) >> 2;
3257 dmae->comp_addr_lo = dmae_reg_go_c[loader_idx] >> 2;
3258 dmae->comp_addr_hi = 0;
3261 /* BIGMAC_REGISTER_RX_STAT_GR64 ..
3262 BIGMAC_REGISTER_RX_STAT_GRIPJ */
3263 dmae = bnx2x_sp(bp, dmae[bp->executer_idx++]);
3264 dmae->opcode = opcode;
3265 dmae->src_addr_lo = (mac_addr +
3266 BIGMAC_REGISTER_RX_STAT_GR64) >> 2;
3267 dmae->src_addr_hi = 0;
3268 dmae->dst_addr_lo = U64_LO(bnx2x_sp_mapping(bp, mac_stats) +
3269 offsetof(struct bmac_stats, rx_stat_gr64_lo));
3270 dmae->dst_addr_hi = U64_HI(bnx2x_sp_mapping(bp, mac_stats) +
3271 offsetof(struct bmac_stats, rx_stat_gr64_lo));
3272 dmae->len = (8 + BIGMAC_REGISTER_RX_STAT_GRIPJ -
3273 BIGMAC_REGISTER_RX_STAT_GR64) >> 2;
3274 dmae->comp_addr_lo = dmae_reg_go_c[loader_idx] >> 2;
3275 dmae->comp_addr_hi = 0;
3278 } else if (bp->link_vars.mac_type == MAC_TYPE_EMAC) {
3280 mac_addr = (port ? GRCBASE_EMAC1 : GRCBASE_EMAC0);
3282 /* EMAC_REG_EMAC_RX_STAT_AC (EMAC_REG_EMAC_RX_STAT_AC_COUNT)*/
3283 dmae = bnx2x_sp(bp, dmae[bp->executer_idx++]);
3284 dmae->opcode = opcode;
3285 dmae->src_addr_lo = (mac_addr +
3286 EMAC_REG_EMAC_RX_STAT_AC) >> 2;
3287 dmae->src_addr_hi = 0;
3288 dmae->dst_addr_lo = U64_LO(bnx2x_sp_mapping(bp, mac_stats));
3289 dmae->dst_addr_hi = U64_HI(bnx2x_sp_mapping(bp, mac_stats));
3290 dmae->len = EMAC_REG_EMAC_RX_STAT_AC_COUNT;
3291 dmae->comp_addr_lo = dmae_reg_go_c[loader_idx] >> 2;
3292 dmae->comp_addr_hi = 0;
3295 /* EMAC_REG_EMAC_RX_STAT_AC_28 */
3296 dmae = bnx2x_sp(bp, dmae[bp->executer_idx++]);
3297 dmae->opcode = opcode;
3298 dmae->src_addr_lo = (mac_addr +
3299 EMAC_REG_EMAC_RX_STAT_AC_28) >> 2;
3300 dmae->src_addr_hi = 0;
3301 dmae->dst_addr_lo = U64_LO(bnx2x_sp_mapping(bp, mac_stats) +
3302 offsetof(struct emac_stats, rx_stat_falsecarriererrors));
3303 dmae->dst_addr_hi = U64_HI(bnx2x_sp_mapping(bp, mac_stats) +
3304 offsetof(struct emac_stats, rx_stat_falsecarriererrors));
3306 dmae->comp_addr_lo = dmae_reg_go_c[loader_idx] >> 2;
3307 dmae->comp_addr_hi = 0;
3310 /* EMAC_REG_EMAC_TX_STAT_AC (EMAC_REG_EMAC_TX_STAT_AC_COUNT)*/
3311 dmae = bnx2x_sp(bp, dmae[bp->executer_idx++]);
3312 dmae->opcode = opcode;
3313 dmae->src_addr_lo = (mac_addr +
3314 EMAC_REG_EMAC_TX_STAT_AC) >> 2;
3315 dmae->src_addr_hi = 0;
3316 dmae->dst_addr_lo = U64_LO(bnx2x_sp_mapping(bp, mac_stats) +
3317 offsetof(struct emac_stats, tx_stat_ifhcoutoctets));
3318 dmae->dst_addr_hi = U64_HI(bnx2x_sp_mapping(bp, mac_stats) +
3319 offsetof(struct emac_stats, tx_stat_ifhcoutoctets));
3320 dmae->len = EMAC_REG_EMAC_TX_STAT_AC_COUNT;
3321 dmae->comp_addr_lo = dmae_reg_go_c[loader_idx] >> 2;
3322 dmae->comp_addr_hi = 0;
3327 dmae = bnx2x_sp(bp, dmae[bp->executer_idx++]);
3328 dmae->opcode = opcode;
3329 dmae->src_addr_lo = (port ? NIG_REG_STAT1_BRB_DISCARD :
3330 NIG_REG_STAT0_BRB_DISCARD) >> 2;
3331 dmae->src_addr_hi = 0;
3332 dmae->dst_addr_lo = U64_LO(bnx2x_sp_mapping(bp, nig_stats));
3333 dmae->dst_addr_hi = U64_HI(bnx2x_sp_mapping(bp, nig_stats));
3334 dmae->len = (sizeof(struct nig_stats) - 4*sizeof(u32)) >> 2;
3335 dmae->comp_addr_lo = dmae_reg_go_c[loader_idx] >> 2;
3336 dmae->comp_addr_hi = 0;
3339 dmae = bnx2x_sp(bp, dmae[bp->executer_idx++]);
3340 dmae->opcode = opcode;
3341 dmae->src_addr_lo = (port ? NIG_REG_STAT1_EGRESS_MAC_PKT0 :
3342 NIG_REG_STAT0_EGRESS_MAC_PKT0) >> 2;
3343 dmae->src_addr_hi = 0;
3344 dmae->dst_addr_lo = U64_LO(bnx2x_sp_mapping(bp, nig_stats) +
3345 offsetof(struct nig_stats, egress_mac_pkt0_lo));
3346 dmae->dst_addr_hi = U64_HI(bnx2x_sp_mapping(bp, nig_stats) +
3347 offsetof(struct nig_stats, egress_mac_pkt0_lo));
3348 dmae->len = (2*sizeof(u32)) >> 2;
3349 dmae->comp_addr_lo = dmae_reg_go_c[loader_idx] >> 2;
3350 dmae->comp_addr_hi = 0;
3353 dmae = bnx2x_sp(bp, dmae[bp->executer_idx++]);
3354 dmae->opcode = (DMAE_CMD_SRC_GRC | DMAE_CMD_DST_PCI |
3355 DMAE_CMD_C_DST_PCI | DMAE_CMD_C_ENABLE |
3356 DMAE_CMD_SRC_RESET | DMAE_CMD_DST_RESET |
3358 DMAE_CMD_ENDIANITY_B_DW_SWAP |
3360 DMAE_CMD_ENDIANITY_DW_SWAP |
3362 (port ? DMAE_CMD_PORT_1 : DMAE_CMD_PORT_0) |
3363 (vn << DMAE_CMD_E1HVN_SHIFT));
3364 dmae->src_addr_lo = (port ? NIG_REG_STAT1_EGRESS_MAC_PKT1 :
3365 NIG_REG_STAT0_EGRESS_MAC_PKT1) >> 2;
3366 dmae->src_addr_hi = 0;
3367 dmae->dst_addr_lo = U64_LO(bnx2x_sp_mapping(bp, nig_stats) +
3368 offsetof(struct nig_stats, egress_mac_pkt1_lo));
3369 dmae->dst_addr_hi = U64_HI(bnx2x_sp_mapping(bp, nig_stats) +
3370 offsetof(struct nig_stats, egress_mac_pkt1_lo));
3371 dmae->len = (2*sizeof(u32)) >> 2;
3372 dmae->comp_addr_lo = U64_LO(bnx2x_sp_mapping(bp, stats_comp));
3373 dmae->comp_addr_hi = U64_HI(bnx2x_sp_mapping(bp, stats_comp));
3374 dmae->comp_val = DMAE_COMP_VAL;
3379 static void bnx2x_func_stats_init(struct bnx2x *bp)
3381 struct dmae_command *dmae = &bp->stats_dmae;
3382 u32 *stats_comp = bnx2x_sp(bp, stats_comp);
3385 if (!bp->func_stx) {
3386 BNX2X_ERR("BUG!\n");
3390 bp->executer_idx = 0;
3391 memset(dmae, 0, sizeof(struct dmae_command));
3393 dmae->opcode = (DMAE_CMD_SRC_PCI | DMAE_CMD_DST_GRC |
3394 DMAE_CMD_C_DST_PCI | DMAE_CMD_C_ENABLE |
3395 DMAE_CMD_SRC_RESET | DMAE_CMD_DST_RESET |
3397 DMAE_CMD_ENDIANITY_B_DW_SWAP |
3399 DMAE_CMD_ENDIANITY_DW_SWAP |
3401 (BP_PORT(bp) ? DMAE_CMD_PORT_1 : DMAE_CMD_PORT_0) |
3402 (BP_E1HVN(bp) << DMAE_CMD_E1HVN_SHIFT));
3403 dmae->src_addr_lo = U64_LO(bnx2x_sp_mapping(bp, func_stats));
3404 dmae->src_addr_hi = U64_HI(bnx2x_sp_mapping(bp, func_stats));
3405 dmae->dst_addr_lo = bp->func_stx >> 2;
3406 dmae->dst_addr_hi = 0;
3407 dmae->len = sizeof(struct host_func_stats) >> 2;
3408 dmae->comp_addr_lo = U64_LO(bnx2x_sp_mapping(bp, stats_comp));
3409 dmae->comp_addr_hi = U64_HI(bnx2x_sp_mapping(bp, stats_comp));
3410 dmae->comp_val = DMAE_COMP_VAL;
3415 static void bnx2x_stats_start(struct bnx2x *bp)
3418 bnx2x_port_stats_init(bp);
3420 else if (bp->func_stx)
3421 bnx2x_func_stats_init(bp);
3423 bnx2x_hw_stats_post(bp);
3424 bnx2x_storm_stats_post(bp);
3427 static void bnx2x_stats_pmf_start(struct bnx2x *bp)
3429 bnx2x_stats_comp(bp);
3430 bnx2x_stats_pmf_update(bp);
3431 bnx2x_stats_start(bp);
3434 static void bnx2x_stats_restart(struct bnx2x *bp)
3436 bnx2x_stats_comp(bp);
3437 bnx2x_stats_start(bp);
3440 static void bnx2x_bmac_stats_update(struct bnx2x *bp)
3442 struct bmac_stats *new = bnx2x_sp(bp, mac_stats.bmac_stats);
3443 struct host_port_stats *pstats = bnx2x_sp(bp, port_stats);
3444 struct regpair diff;
3446 UPDATE_STAT64(rx_stat_grerb, rx_stat_ifhcinbadoctets);
3447 UPDATE_STAT64(rx_stat_grfcs, rx_stat_dot3statsfcserrors);
3448 UPDATE_STAT64(rx_stat_grund, rx_stat_etherstatsundersizepkts);
3449 UPDATE_STAT64(rx_stat_grovr, rx_stat_dot3statsframestoolong);
3450 UPDATE_STAT64(rx_stat_grfrg, rx_stat_etherstatsfragments);
3451 UPDATE_STAT64(rx_stat_grjbr, rx_stat_etherstatsjabbers);
3452 UPDATE_STAT64(rx_stat_grxcf, rx_stat_maccontrolframesreceived);
3453 UPDATE_STAT64(rx_stat_grxpf, rx_stat_xoffstateentered);
3454 UPDATE_STAT64(rx_stat_grxpf, rx_stat_xoffpauseframesreceived);
3455 UPDATE_STAT64(tx_stat_gtxpf, tx_stat_outxoffsent);
3456 UPDATE_STAT64(tx_stat_gtxpf, tx_stat_flowcontroldone);
3457 UPDATE_STAT64(tx_stat_gt64, tx_stat_etherstatspkts64octets);
3458 UPDATE_STAT64(tx_stat_gt127,
3459 tx_stat_etherstatspkts65octetsto127octets);
3460 UPDATE_STAT64(tx_stat_gt255,
3461 tx_stat_etherstatspkts128octetsto255octets);
3462 UPDATE_STAT64(tx_stat_gt511,
3463 tx_stat_etherstatspkts256octetsto511octets);
3464 UPDATE_STAT64(tx_stat_gt1023,
3465 tx_stat_etherstatspkts512octetsto1023octets);
3466 UPDATE_STAT64(tx_stat_gt1518,
3467 tx_stat_etherstatspkts1024octetsto1522octets);
3468 UPDATE_STAT64(tx_stat_gt2047, tx_stat_bmac_2047);
3469 UPDATE_STAT64(tx_stat_gt4095, tx_stat_bmac_4095);
3470 UPDATE_STAT64(tx_stat_gt9216, tx_stat_bmac_9216);
3471 UPDATE_STAT64(tx_stat_gt16383, tx_stat_bmac_16383);
3472 UPDATE_STAT64(tx_stat_gterr,
3473 tx_stat_dot3statsinternalmactransmiterrors);
3474 UPDATE_STAT64(tx_stat_gtufl, tx_stat_bmac_ufl);
3477 static void bnx2x_emac_stats_update(struct bnx2x *bp)
3479 struct emac_stats *new = bnx2x_sp(bp, mac_stats.emac_stats);
3480 struct host_port_stats *pstats = bnx2x_sp(bp, port_stats);
3482 UPDATE_EXTEND_STAT(rx_stat_ifhcinbadoctets);
3483 UPDATE_EXTEND_STAT(tx_stat_ifhcoutbadoctets);
3484 UPDATE_EXTEND_STAT(rx_stat_dot3statsfcserrors);
3485 UPDATE_EXTEND_STAT(rx_stat_dot3statsalignmenterrors);
3486 UPDATE_EXTEND_STAT(rx_stat_dot3statscarriersenseerrors);
3487 UPDATE_EXTEND_STAT(rx_stat_falsecarriererrors);
3488 UPDATE_EXTEND_STAT(rx_stat_etherstatsundersizepkts);
3489 UPDATE_EXTEND_STAT(rx_stat_dot3statsframestoolong);
3490 UPDATE_EXTEND_STAT(rx_stat_etherstatsfragments);
3491 UPDATE_EXTEND_STAT(rx_stat_etherstatsjabbers);
3492 UPDATE_EXTEND_STAT(rx_stat_maccontrolframesreceived);
3493 UPDATE_EXTEND_STAT(rx_stat_xoffstateentered);
3494 UPDATE_EXTEND_STAT(rx_stat_xonpauseframesreceived);
3495 UPDATE_EXTEND_STAT(rx_stat_xoffpauseframesreceived);
3496 UPDATE_EXTEND_STAT(tx_stat_outxonsent);
3497 UPDATE_EXTEND_STAT(tx_stat_outxoffsent);
3498 UPDATE_EXTEND_STAT(tx_stat_flowcontroldone);
3499 UPDATE_EXTEND_STAT(tx_stat_etherstatscollisions);
3500 UPDATE_EXTEND_STAT(tx_stat_dot3statssinglecollisionframes);
3501 UPDATE_EXTEND_STAT(tx_stat_dot3statsmultiplecollisionframes);
3502 UPDATE_EXTEND_STAT(tx_stat_dot3statsdeferredtransmissions);
3503 UPDATE_EXTEND_STAT(tx_stat_dot3statsexcessivecollisions);
3504 UPDATE_EXTEND_STAT(tx_stat_dot3statslatecollisions);
3505 UPDATE_EXTEND_STAT(tx_stat_etherstatspkts64octets);
3506 UPDATE_EXTEND_STAT(tx_stat_etherstatspkts65octetsto127octets);
3507 UPDATE_EXTEND_STAT(tx_stat_etherstatspkts128octetsto255octets);
3508 UPDATE_EXTEND_STAT(tx_stat_etherstatspkts256octetsto511octets);
3509 UPDATE_EXTEND_STAT(tx_stat_etherstatspkts512octetsto1023octets);
3510 UPDATE_EXTEND_STAT(tx_stat_etherstatspkts1024octetsto1522octets);
3511 UPDATE_EXTEND_STAT(tx_stat_etherstatspktsover1522octets);
3512 UPDATE_EXTEND_STAT(tx_stat_dot3statsinternalmactransmiterrors);
3515 static int bnx2x_hw_stats_update(struct bnx2x *bp)
3517 struct nig_stats *new = bnx2x_sp(bp, nig_stats);
3518 struct nig_stats *old = &(bp->port.old_nig_stats);
3519 struct host_port_stats *pstats = bnx2x_sp(bp, port_stats);
3520 struct bnx2x_eth_stats *estats = &bp->eth_stats;
3521 struct regpair diff;
3523 if (bp->link_vars.mac_type == MAC_TYPE_BMAC)
3524 bnx2x_bmac_stats_update(bp);
3526 else if (bp->link_vars.mac_type == MAC_TYPE_EMAC)
3527 bnx2x_emac_stats_update(bp);
3529 else { /* unreached */
3530 BNX2X_ERR("stats updated by dmae but no MAC active\n");
3534 ADD_EXTEND_64(pstats->brb_drop_hi, pstats->brb_drop_lo,
3535 new->brb_discard - old->brb_discard);
3536 ADD_EXTEND_64(estats->brb_truncate_hi, estats->brb_truncate_lo,
3537 new->brb_truncate - old->brb_truncate);
3539 UPDATE_STAT64_NIG(egress_mac_pkt0,
3540 etherstatspkts1024octetsto1522octets);
3541 UPDATE_STAT64_NIG(egress_mac_pkt1, etherstatspktsover1522octets);
3543 memcpy(old, new, sizeof(struct nig_stats));
3545 memcpy(&(estats->rx_stat_ifhcinbadoctets_hi), &(pstats->mac_stx[1]),
3546 sizeof(struct mac_stx));
3547 estats->brb_drop_hi = pstats->brb_drop_hi;
3548 estats->brb_drop_lo = pstats->brb_drop_lo;
3550 pstats->host_port_stats_start = ++pstats->host_port_stats_end;
3555 static int bnx2x_storm_stats_update(struct bnx2x *bp)
3557 struct eth_stats_query *stats = bnx2x_sp(bp, fw_stats);
3558 int cl_id = BP_CL_ID(bp);
3559 struct tstorm_per_port_stats *tport =
3560 &stats->tstorm_common.port_statistics;
3561 struct tstorm_per_client_stats *tclient =
3562 &stats->tstorm_common.client_statistics[cl_id];
3563 struct tstorm_per_client_stats *old_tclient = &bp->old_tclient;
3564 struct xstorm_per_client_stats *xclient =
3565 &stats->xstorm_common.client_statistics[cl_id];
3566 struct xstorm_per_client_stats *old_xclient = &bp->old_xclient;
3567 struct host_func_stats *fstats = bnx2x_sp(bp, func_stats);
3568 struct bnx2x_eth_stats *estats = &bp->eth_stats;
3571 /* are storm stats valid? */
3572 if ((u16)(le16_to_cpu(tclient->stats_counter) + 1) !=
3573 bp->stats_counter) {
3574 DP(BNX2X_MSG_STATS, "stats not updated by tstorm"
3575 " tstorm counter (%d) != stats_counter (%d)\n",
3576 tclient->stats_counter, bp->stats_counter);
3579 if ((u16)(le16_to_cpu(xclient->stats_counter) + 1) !=
3580 bp->stats_counter) {
3581 DP(BNX2X_MSG_STATS, "stats not updated by xstorm"
3582 " xstorm counter (%d) != stats_counter (%d)\n",
3583 xclient->stats_counter, bp->stats_counter);
3587 fstats->total_bytes_received_hi =
3588 fstats->valid_bytes_received_hi =
3589 le32_to_cpu(tclient->total_rcv_bytes.hi);
3590 fstats->total_bytes_received_lo =
3591 fstats->valid_bytes_received_lo =
3592 le32_to_cpu(tclient->total_rcv_bytes.lo);
3594 estats->error_bytes_received_hi =
3595 le32_to_cpu(tclient->rcv_error_bytes.hi);
3596 estats->error_bytes_received_lo =
3597 le32_to_cpu(tclient->rcv_error_bytes.lo);
3598 ADD_64(estats->error_bytes_received_hi,
3599 estats->rx_stat_ifhcinbadoctets_hi,
3600 estats->error_bytes_received_lo,
3601 estats->rx_stat_ifhcinbadoctets_lo);
3603 ADD_64(fstats->total_bytes_received_hi,
3604 estats->error_bytes_received_hi,
3605 fstats->total_bytes_received_lo,
3606 estats->error_bytes_received_lo);
3608 UPDATE_EXTEND_TSTAT(rcv_unicast_pkts, total_unicast_packets_received);
3609 UPDATE_EXTEND_TSTAT(rcv_multicast_pkts,
3610 total_multicast_packets_received);
3611 UPDATE_EXTEND_TSTAT(rcv_broadcast_pkts,
3612 total_broadcast_packets_received);
3614 fstats->total_bytes_transmitted_hi =
3615 le32_to_cpu(xclient->total_sent_bytes.hi);
3616 fstats->total_bytes_transmitted_lo =
3617 le32_to_cpu(xclient->total_sent_bytes.lo);
3619 UPDATE_EXTEND_XSTAT(unicast_pkts_sent,
3620 total_unicast_packets_transmitted);
3621 UPDATE_EXTEND_XSTAT(multicast_pkts_sent,
3622 total_multicast_packets_transmitted);
3623 UPDATE_EXTEND_XSTAT(broadcast_pkts_sent,
3624 total_broadcast_packets_transmitted);
3626 memcpy(estats, &(fstats->total_bytes_received_hi),
3627 sizeof(struct host_func_stats) - 2*sizeof(u32));
3629 estats->mac_filter_discard = le32_to_cpu(tport->mac_filter_discard);
3630 estats->xxoverflow_discard = le32_to_cpu(tport->xxoverflow_discard);
3631 estats->brb_truncate_discard =
3632 le32_to_cpu(tport->brb_truncate_discard);
3633 estats->mac_discard = le32_to_cpu(tport->mac_discard);
3635 old_tclient->rcv_unicast_bytes.hi =
3636 le32_to_cpu(tclient->rcv_unicast_bytes.hi);
3637 old_tclient->rcv_unicast_bytes.lo =
3638 le32_to_cpu(tclient->rcv_unicast_bytes.lo);
3639 old_tclient->rcv_broadcast_bytes.hi =
3640 le32_to_cpu(tclient->rcv_broadcast_bytes.hi);
3641 old_tclient->rcv_broadcast_bytes.lo =
3642 le32_to_cpu(tclient->rcv_broadcast_bytes.lo);
3643 old_tclient->rcv_multicast_bytes.hi =
3644 le32_to_cpu(tclient->rcv_multicast_bytes.hi);
3645 old_tclient->rcv_multicast_bytes.lo =
3646 le32_to_cpu(tclient->rcv_multicast_bytes.lo);
3647 old_tclient->total_rcv_pkts = le32_to_cpu(tclient->total_rcv_pkts);
3649 old_tclient->checksum_discard = le32_to_cpu(tclient->checksum_discard);
3650 old_tclient->packets_too_big_discard =
3651 le32_to_cpu(tclient->packets_too_big_discard);
3652 estats->no_buff_discard =
3653 old_tclient->no_buff_discard = le32_to_cpu(tclient->no_buff_discard);
3654 old_tclient->ttl0_discard = le32_to_cpu(tclient->ttl0_discard);
3656 old_xclient->total_sent_pkts = le32_to_cpu(xclient->total_sent_pkts);
3657 old_xclient->unicast_bytes_sent.hi =
3658 le32_to_cpu(xclient->unicast_bytes_sent.hi);
3659 old_xclient->unicast_bytes_sent.lo =
3660 le32_to_cpu(xclient->unicast_bytes_sent.lo);
3661 old_xclient->multicast_bytes_sent.hi =
3662 le32_to_cpu(xclient->multicast_bytes_sent.hi);
3663 old_xclient->multicast_bytes_sent.lo =
3664 le32_to_cpu(xclient->multicast_bytes_sent.lo);
3665 old_xclient->broadcast_bytes_sent.hi =
3666 le32_to_cpu(xclient->broadcast_bytes_sent.hi);
3667 old_xclient->broadcast_bytes_sent.lo =
3668 le32_to_cpu(xclient->broadcast_bytes_sent.lo);
3670 fstats->host_func_stats_start = ++fstats->host_func_stats_end;
3675 static void bnx2x_net_stats_update(struct bnx2x *bp)
3677 struct tstorm_per_client_stats *old_tclient = &bp->old_tclient;
3678 struct bnx2x_eth_stats *estats = &bp->eth_stats;
3679 struct net_device_stats *nstats = &bp->dev->stats;
3681 nstats->rx_packets =
3682 bnx2x_hilo(&estats->total_unicast_packets_received_hi) +
3683 bnx2x_hilo(&estats->total_multicast_packets_received_hi) +
3684 bnx2x_hilo(&estats->total_broadcast_packets_received_hi);
3686 nstats->tx_packets =
3687 bnx2x_hilo(&estats->total_unicast_packets_transmitted_hi) +
3688 bnx2x_hilo(&estats->total_multicast_packets_transmitted_hi) +
3689 bnx2x_hilo(&estats->total_broadcast_packets_transmitted_hi);
3691 nstats->rx_bytes = bnx2x_hilo(&estats->valid_bytes_received_hi);
3693 nstats->tx_bytes = bnx2x_hilo(&estats->total_bytes_transmitted_hi);
3695 nstats->rx_dropped = old_tclient->checksum_discard +
3696 estats->mac_discard;
3697 nstats->tx_dropped = 0;
3700 bnx2x_hilo(&estats->total_multicast_packets_transmitted_hi);
3702 nstats->collisions =
3703 estats->tx_stat_dot3statssinglecollisionframes_lo +
3704 estats->tx_stat_dot3statsmultiplecollisionframes_lo +
3705 estats->tx_stat_dot3statslatecollisions_lo +
3706 estats->tx_stat_dot3statsexcessivecollisions_lo;
3708 estats->jabber_packets_received =
3709 old_tclient->packets_too_big_discard +
3710 estats->rx_stat_dot3statsframestoolong_lo;
3712 nstats->rx_length_errors =
3713 estats->rx_stat_etherstatsundersizepkts_lo +
3714 estats->jabber_packets_received;
3715 nstats->rx_over_errors = estats->brb_drop_lo + estats->brb_truncate_lo;
3716 nstats->rx_crc_errors = estats->rx_stat_dot3statsfcserrors_lo;
3717 nstats->rx_frame_errors = estats->rx_stat_dot3statsalignmenterrors_lo;
3718 nstats->rx_fifo_errors = old_tclient->no_buff_discard;
3719 nstats->rx_missed_errors = estats->xxoverflow_discard;
3721 nstats->rx_errors = nstats->rx_length_errors +
3722 nstats->rx_over_errors +
3723 nstats->rx_crc_errors +
3724 nstats->rx_frame_errors +
3725 nstats->rx_fifo_errors +
3726 nstats->rx_missed_errors;
3728 nstats->tx_aborted_errors =
3729 estats->tx_stat_dot3statslatecollisions_lo +
3730 estats->tx_stat_dot3statsexcessivecollisions_lo;
3731 nstats->tx_carrier_errors = estats->rx_stat_falsecarriererrors_lo;
3732 nstats->tx_fifo_errors = 0;
3733 nstats->tx_heartbeat_errors = 0;
3734 nstats->tx_window_errors = 0;
3736 nstats->tx_errors = nstats->tx_aborted_errors +
3737 nstats->tx_carrier_errors;
3740 static void bnx2x_stats_update(struct bnx2x *bp)
3742 u32 *stats_comp = bnx2x_sp(bp, stats_comp);
3745 if (*stats_comp != DMAE_COMP_VAL)
3749 update = (bnx2x_hw_stats_update(bp) == 0);
3751 update |= (bnx2x_storm_stats_update(bp) == 0);
3754 bnx2x_net_stats_update(bp);
3757 if (bp->stats_pending) {
3758 bp->stats_pending++;
3759 if (bp->stats_pending == 3) {
3760 BNX2X_ERR("stats not updated for 3 times\n");
3767 if (bp->msglevel & NETIF_MSG_TIMER) {
3768 struct tstorm_per_client_stats *old_tclient = &bp->old_tclient;
3769 struct bnx2x_eth_stats *estats = &bp->eth_stats;
3770 struct net_device_stats *nstats = &bp->dev->stats;
3773 printk(KERN_DEBUG "%s:\n", bp->dev->name);
3774 printk(KERN_DEBUG " tx avail (%4x) tx hc idx (%x)"
3776 bnx2x_tx_avail(bp->fp),
3777 le16_to_cpu(*bp->fp->tx_cons_sb), nstats->tx_packets);
3778 printk(KERN_DEBUG " rx usage (%4x) rx hc idx (%x)"
3780 (u16)(le16_to_cpu(*bp->fp->rx_cons_sb) -
3781 bp->fp->rx_comp_cons),
3782 le16_to_cpu(*bp->fp->rx_cons_sb), nstats->rx_packets);
3783 printk(KERN_DEBUG " %s (Xoff events %u) brb drops %u\n",
3784 netif_queue_stopped(bp->dev)? "Xoff" : "Xon",
3785 estats->driver_xoff, estats->brb_drop_lo);
3786 printk(KERN_DEBUG "tstats: checksum_discard %u "
3787 "packets_too_big_discard %u no_buff_discard %u "
3788 "mac_discard %u mac_filter_discard %u "
3789 "xxovrflow_discard %u brb_truncate_discard %u "
3790 "ttl0_discard %u\n",
3791 old_tclient->checksum_discard,
3792 old_tclient->packets_too_big_discard,
3793 old_tclient->no_buff_discard, estats->mac_discard,
3794 estats->mac_filter_discard, estats->xxoverflow_discard,
3795 estats->brb_truncate_discard,
3796 old_tclient->ttl0_discard);
3798 for_each_queue(bp, i) {
3799 printk(KERN_DEBUG "[%d]: %lu\t%lu\t%lu\n", i,
3800 bnx2x_fp(bp, i, tx_pkt),
3801 bnx2x_fp(bp, i, rx_pkt),
3802 bnx2x_fp(bp, i, rx_calls));
3806 bnx2x_hw_stats_post(bp);
3807 bnx2x_storm_stats_post(bp);
3810 static void bnx2x_port_stats_stop(struct bnx2x *bp)
3812 struct dmae_command *dmae;
3814 int loader_idx = PMF_DMAE_C(bp);
3815 u32 *stats_comp = bnx2x_sp(bp, stats_comp);
3817 bp->executer_idx = 0;
3819 opcode = (DMAE_CMD_SRC_PCI | DMAE_CMD_DST_GRC |
3821 DMAE_CMD_SRC_RESET | DMAE_CMD_DST_RESET |
3823 DMAE_CMD_ENDIANITY_B_DW_SWAP |
3825 DMAE_CMD_ENDIANITY_DW_SWAP |
3827 (BP_PORT(bp) ? DMAE_CMD_PORT_1 : DMAE_CMD_PORT_0) |
3828 (BP_E1HVN(bp) << DMAE_CMD_E1HVN_SHIFT));
3830 if (bp->port.port_stx) {
3832 dmae = bnx2x_sp(bp, dmae[bp->executer_idx++]);
3834 dmae->opcode = (opcode | DMAE_CMD_C_DST_GRC);
3836 dmae->opcode = (opcode | DMAE_CMD_C_DST_PCI);
3837 dmae->src_addr_lo = U64_LO(bnx2x_sp_mapping(bp, port_stats));
3838 dmae->src_addr_hi = U64_HI(bnx2x_sp_mapping(bp, port_stats));
3839 dmae->dst_addr_lo = bp->port.port_stx >> 2;
3840 dmae->dst_addr_hi = 0;
3841 dmae->len = sizeof(struct host_port_stats) >> 2;
3843 dmae->comp_addr_lo = dmae_reg_go_c[loader_idx] >> 2;
3844 dmae->comp_addr_hi = 0;
3847 dmae->comp_addr_lo =
3848 U64_LO(bnx2x_sp_mapping(bp, stats_comp));
3849 dmae->comp_addr_hi =
3850 U64_HI(bnx2x_sp_mapping(bp, stats_comp));
3851 dmae->comp_val = DMAE_COMP_VAL;
3859 dmae = bnx2x_sp(bp, dmae[bp->executer_idx++]);
3860 dmae->opcode = (opcode | DMAE_CMD_C_DST_PCI);
3861 dmae->src_addr_lo = U64_LO(bnx2x_sp_mapping(bp, func_stats));
3862 dmae->src_addr_hi = U64_HI(bnx2x_sp_mapping(bp, func_stats));
3863 dmae->dst_addr_lo = bp->func_stx >> 2;
3864 dmae->dst_addr_hi = 0;
3865 dmae->len = sizeof(struct host_func_stats) >> 2;
3866 dmae->comp_addr_lo = U64_LO(bnx2x_sp_mapping(bp, stats_comp));
3867 dmae->comp_addr_hi = U64_HI(bnx2x_sp_mapping(bp, stats_comp));
3868 dmae->comp_val = DMAE_COMP_VAL;
3874 static void bnx2x_stats_stop(struct bnx2x *bp)
3878 bnx2x_stats_comp(bp);
3881 update = (bnx2x_hw_stats_update(bp) == 0);
3883 update |= (bnx2x_storm_stats_update(bp) == 0);
3886 bnx2x_net_stats_update(bp);
3889 bnx2x_port_stats_stop(bp);
3891 bnx2x_hw_stats_post(bp);
3892 bnx2x_stats_comp(bp);
3896 static void bnx2x_stats_do_nothing(struct bnx2x *bp)
3900 static const struct {
3901 void (*action)(struct bnx2x *bp);
3902 enum bnx2x_stats_state next_state;
3903 } bnx2x_stats_stm[STATS_STATE_MAX][STATS_EVENT_MAX] = {
3906 /* DISABLED PMF */ {bnx2x_stats_pmf_update, STATS_STATE_DISABLED},
3907 /* LINK_UP */ {bnx2x_stats_start, STATS_STATE_ENABLED},
3908 /* UPDATE */ {bnx2x_stats_do_nothing, STATS_STATE_DISABLED},
3909 /* STOP */ {bnx2x_stats_do_nothing, STATS_STATE_DISABLED}
3912 /* ENABLED PMF */ {bnx2x_stats_pmf_start, STATS_STATE_ENABLED},
3913 /* LINK_UP */ {bnx2x_stats_restart, STATS_STATE_ENABLED},
3914 /* UPDATE */ {bnx2x_stats_update, STATS_STATE_ENABLED},
3915 /* STOP */ {bnx2x_stats_stop, STATS_STATE_DISABLED}
3919 static void bnx2x_stats_handle(struct bnx2x *bp, enum bnx2x_stats_event event)
3921 enum bnx2x_stats_state state = bp->stats_state;
3923 bnx2x_stats_stm[state][event].action(bp);
3924 bp->stats_state = bnx2x_stats_stm[state][event].next_state;
3926 if ((event != STATS_EVENT_UPDATE) || (bp->msglevel & NETIF_MSG_TIMER))
3927 DP(BNX2X_MSG_STATS, "state %d -> event %d -> state %d\n",
3928 state, event, bp->stats_state);
3931 static void bnx2x_timer(unsigned long data)
3933 struct bnx2x *bp = (struct bnx2x *) data;
3935 if (!netif_running(bp->dev))
3938 if (atomic_read(&bp->intr_sem) != 0)
3942 struct bnx2x_fastpath *fp = &bp->fp[0];
3945 bnx2x_tx_int(fp, 1000);
3946 rc = bnx2x_rx_int(fp, 1000);
3949 if (!BP_NOMCP(bp)) {
3950 int func = BP_FUNC(bp);
3954 ++bp->fw_drv_pulse_wr_seq;
3955 bp->fw_drv_pulse_wr_seq &= DRV_PULSE_SEQ_MASK;
3956 /* TBD - add SYSTEM_TIME */
3957 drv_pulse = bp->fw_drv_pulse_wr_seq;
3958 SHMEM_WR(bp, func_mb[func].drv_pulse_mb, drv_pulse);
3960 mcp_pulse = (SHMEM_RD(bp, func_mb[func].mcp_pulse_mb) &
3961 MCP_PULSE_SEQ_MASK);
3962 /* The delta between driver pulse and mcp response
3963 * should be 1 (before mcp response) or 0 (after mcp response)
3965 if ((drv_pulse != mcp_pulse) &&
3966 (drv_pulse != ((mcp_pulse + 1) & MCP_PULSE_SEQ_MASK))) {
3967 /* someone lost a heartbeat... */
3968 BNX2X_ERR("drv_pulse (0x%x) != mcp_pulse (0x%x)\n",
3969 drv_pulse, mcp_pulse);
3973 if ((bp->state == BNX2X_STATE_OPEN) ||
3974 (bp->state == BNX2X_STATE_DISABLED))
3975 bnx2x_stats_handle(bp, STATS_EVENT_UPDATE);
3978 mod_timer(&bp->timer, jiffies + bp->current_interval);
3981 /* end of Statistics */
3986 * nic init service functions
3989 static void bnx2x_zero_sb(struct bnx2x *bp, int sb_id)
3991 int port = BP_PORT(bp);
3993 bnx2x_init_fill(bp, BAR_USTRORM_INTMEM +
3994 USTORM_SB_HOST_STATUS_BLOCK_OFFSET(port, sb_id), 0,
3995 sizeof(struct ustorm_def_status_block)/4);
3996 bnx2x_init_fill(bp, BAR_CSTRORM_INTMEM +
3997 CSTORM_SB_HOST_STATUS_BLOCK_OFFSET(port, sb_id), 0,
3998 sizeof(struct cstorm_def_status_block)/4);
4001 static void bnx2x_init_sb(struct bnx2x *bp, int sb_id,
4002 struct host_status_block *sb, dma_addr_t mapping)
4004 int port = BP_PORT(bp);
4005 int func = BP_FUNC(bp);
4010 section = ((u64)mapping) + offsetof(struct host_status_block,
4012 sb->u_status_block.status_block_id = sb_id;
4014 REG_WR(bp, BAR_USTRORM_INTMEM +
4015 USTORM_SB_HOST_SB_ADDR_OFFSET(port, sb_id), U64_LO(section));
4016 REG_WR(bp, BAR_USTRORM_INTMEM +
4017 ((USTORM_SB_HOST_SB_ADDR_OFFSET(port, sb_id)) + 4),
4019 REG_WR8(bp, BAR_USTRORM_INTMEM + FP_USB_FUNC_OFF +
4020 USTORM_SB_HOST_STATUS_BLOCK_OFFSET(port, sb_id), func);
4022 for (index = 0; index < HC_USTORM_SB_NUM_INDICES; index++)
4023 REG_WR16(bp, BAR_USTRORM_INTMEM +
4024 USTORM_SB_HC_DISABLE_OFFSET(port, sb_id, index), 1);
4027 section = ((u64)mapping) + offsetof(struct host_status_block,
4029 sb->c_status_block.status_block_id = sb_id;
4031 REG_WR(bp, BAR_CSTRORM_INTMEM +
4032 CSTORM_SB_HOST_SB_ADDR_OFFSET(port, sb_id), U64_LO(section));
4033 REG_WR(bp, BAR_CSTRORM_INTMEM +
4034 ((CSTORM_SB_HOST_SB_ADDR_OFFSET(port, sb_id)) + 4),
4036 REG_WR8(bp, BAR_CSTRORM_INTMEM + FP_CSB_FUNC_OFF +
4037 CSTORM_SB_HOST_STATUS_BLOCK_OFFSET(port, sb_id), func);
4039 for (index = 0; index < HC_CSTORM_SB_NUM_INDICES; index++)
4040 REG_WR16(bp, BAR_CSTRORM_INTMEM +
4041 CSTORM_SB_HC_DISABLE_OFFSET(port, sb_id, index), 1);
4043 bnx2x_ack_sb(bp, sb_id, CSTORM_ID, 0, IGU_INT_ENABLE, 0);
4046 static void bnx2x_zero_def_sb(struct bnx2x *bp)
4048 int func = BP_FUNC(bp);
4050 bnx2x_init_fill(bp, BAR_USTRORM_INTMEM +
4051 USTORM_DEF_SB_HOST_STATUS_BLOCK_OFFSET(func), 0,
4052 sizeof(struct ustorm_def_status_block)/4);
4053 bnx2x_init_fill(bp, BAR_CSTRORM_INTMEM +
4054 CSTORM_DEF_SB_HOST_STATUS_BLOCK_OFFSET(func), 0,
4055 sizeof(struct cstorm_def_status_block)/4);
4056 bnx2x_init_fill(bp, BAR_XSTRORM_INTMEM +
4057 XSTORM_DEF_SB_HOST_STATUS_BLOCK_OFFSET(func), 0,
4058 sizeof(struct xstorm_def_status_block)/4);
4059 bnx2x_init_fill(bp, BAR_TSTRORM_INTMEM +
4060 TSTORM_DEF_SB_HOST_STATUS_BLOCK_OFFSET(func), 0,
4061 sizeof(struct tstorm_def_status_block)/4);
4064 static void bnx2x_init_def_sb(struct bnx2x *bp,
4065 struct host_def_status_block *def_sb,
4066 dma_addr_t mapping, int sb_id)
4068 int port = BP_PORT(bp);
4069 int func = BP_FUNC(bp);
4070 int index, val, reg_offset;
4074 section = ((u64)mapping) + offsetof(struct host_def_status_block,
4075 atten_status_block);
4076 def_sb->atten_status_block.status_block_id = sb_id;
4078 bp->def_att_idx = 0;
4081 reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 :
4082 MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0);
4084 for (index = 0; index < MAX_DYNAMIC_ATTN_GRPS; index++) {
4085 bp->attn_group[index].sig[0] = REG_RD(bp,
4086 reg_offset + 0x10*index);
4087 bp->attn_group[index].sig[1] = REG_RD(bp,
4088 reg_offset + 0x4 + 0x10*index);
4089 bp->attn_group[index].sig[2] = REG_RD(bp,
4090 reg_offset + 0x8 + 0x10*index);
4091 bp->attn_group[index].sig[3] = REG_RD(bp,
4092 reg_offset + 0xc + 0x10*index);
4095 reg_offset = (port ? HC_REG_ATTN_MSG1_ADDR_L :
4096 HC_REG_ATTN_MSG0_ADDR_L);
4098 REG_WR(bp, reg_offset, U64_LO(section));
4099 REG_WR(bp, reg_offset + 4, U64_HI(section));
4101 reg_offset = (port ? HC_REG_ATTN_NUM_P1 : HC_REG_ATTN_NUM_P0);
4103 val = REG_RD(bp, reg_offset);
4105 REG_WR(bp, reg_offset, val);
4108 section = ((u64)mapping) + offsetof(struct host_def_status_block,
4109 u_def_status_block);
4110 def_sb->u_def_status_block.status_block_id = sb_id;
4114 REG_WR(bp, BAR_USTRORM_INTMEM +
4115 USTORM_DEF_SB_HOST_SB_ADDR_OFFSET(func), U64_LO(section));
4116 REG_WR(bp, BAR_USTRORM_INTMEM +
4117 ((USTORM_DEF_SB_HOST_SB_ADDR_OFFSET(func)) + 4),
4119 REG_WR8(bp, BAR_USTRORM_INTMEM + DEF_USB_FUNC_OFF +
4120 USTORM_DEF_SB_HOST_STATUS_BLOCK_OFFSET(func), func);
4121 REG_WR(bp, BAR_USTRORM_INTMEM + USTORM_HC_BTR_OFFSET(func),
4124 for (index = 0; index < HC_USTORM_DEF_SB_NUM_INDICES; index++)
4125 REG_WR16(bp, BAR_USTRORM_INTMEM +
4126 USTORM_DEF_SB_HC_DISABLE_OFFSET(func, index), 1);
4129 section = ((u64)mapping) + offsetof(struct host_def_status_block,
4130 c_def_status_block);
4131 def_sb->c_def_status_block.status_block_id = sb_id;
4135 REG_WR(bp, BAR_CSTRORM_INTMEM +
4136 CSTORM_DEF_SB_HOST_SB_ADDR_OFFSET(func), U64_LO(section));
4137 REG_WR(bp, BAR_CSTRORM_INTMEM +
4138 ((CSTORM_DEF_SB_HOST_SB_ADDR_OFFSET(func)) + 4),
4140 REG_WR8(bp, BAR_CSTRORM_INTMEM + DEF_CSB_FUNC_OFF +
4141 CSTORM_DEF_SB_HOST_STATUS_BLOCK_OFFSET(func), func);
4142 REG_WR(bp, BAR_CSTRORM_INTMEM + CSTORM_HC_BTR_OFFSET(func),
4145 for (index = 0; index < HC_CSTORM_DEF_SB_NUM_INDICES; index++)
4146 REG_WR16(bp, BAR_CSTRORM_INTMEM +
4147 CSTORM_DEF_SB_HC_DISABLE_OFFSET(func, index), 1);
4150 section = ((u64)mapping) + offsetof(struct host_def_status_block,
4151 t_def_status_block);
4152 def_sb->t_def_status_block.status_block_id = sb_id;
4156 REG_WR(bp, BAR_TSTRORM_INTMEM +
4157 TSTORM_DEF_SB_HOST_SB_ADDR_OFFSET(func), U64_LO(section));
4158 REG_WR(bp, BAR_TSTRORM_INTMEM +
4159 ((TSTORM_DEF_SB_HOST_SB_ADDR_OFFSET(func)) + 4),
4161 REG_WR8(bp, BAR_TSTRORM_INTMEM + DEF_TSB_FUNC_OFF +
4162 TSTORM_DEF_SB_HOST_STATUS_BLOCK_OFFSET(func), func);
4163 REG_WR(bp, BAR_TSTRORM_INTMEM + TSTORM_HC_BTR_OFFSET(func),
4166 for (index = 0; index < HC_TSTORM_DEF_SB_NUM_INDICES; index++)
4167 REG_WR16(bp, BAR_TSTRORM_INTMEM +
4168 TSTORM_DEF_SB_HC_DISABLE_OFFSET(func, index), 1);
4171 section = ((u64)mapping) + offsetof(struct host_def_status_block,
4172 x_def_status_block);
4173 def_sb->x_def_status_block.status_block_id = sb_id;
4177 REG_WR(bp, BAR_XSTRORM_INTMEM +
4178 XSTORM_DEF_SB_HOST_SB_ADDR_OFFSET(func), U64_LO(section));
4179 REG_WR(bp, BAR_XSTRORM_INTMEM +
4180 ((XSTORM_DEF_SB_HOST_SB_ADDR_OFFSET(func)) + 4),
4182 REG_WR8(bp, BAR_XSTRORM_INTMEM + DEF_XSB_FUNC_OFF +
4183 XSTORM_DEF_SB_HOST_STATUS_BLOCK_OFFSET(func), func);
4184 REG_WR(bp, BAR_XSTRORM_INTMEM + XSTORM_HC_BTR_OFFSET(func),
4187 for (index = 0; index < HC_XSTORM_DEF_SB_NUM_INDICES; index++)
4188 REG_WR16(bp, BAR_XSTRORM_INTMEM +
4189 XSTORM_DEF_SB_HC_DISABLE_OFFSET(func, index), 1);
4191 bp->stats_pending = 0;
4192 bp->set_mac_pending = 0;
4194 bnx2x_ack_sb(bp, sb_id, CSTORM_ID, 0, IGU_INT_ENABLE, 0);
4197 static void bnx2x_update_coalesce(struct bnx2x *bp)
4199 int port = BP_PORT(bp);
4202 for_each_queue(bp, i) {
4203 int sb_id = bp->fp[i].sb_id;
4205 /* HC_INDEX_U_ETH_RX_CQ_CONS */
4206 REG_WR8(bp, BAR_USTRORM_INTMEM +
4207 USTORM_SB_HC_TIMEOUT_OFFSET(port, sb_id,
4208 HC_INDEX_U_ETH_RX_CQ_CONS),
4210 REG_WR16(bp, BAR_USTRORM_INTMEM +
4211 USTORM_SB_HC_DISABLE_OFFSET(port, sb_id,
4212 HC_INDEX_U_ETH_RX_CQ_CONS),
4213 bp->rx_ticks ? 0 : 1);
4215 /* HC_INDEX_C_ETH_TX_CQ_CONS */
4216 REG_WR8(bp, BAR_CSTRORM_INTMEM +
4217 CSTORM_SB_HC_TIMEOUT_OFFSET(port, sb_id,
4218 HC_INDEX_C_ETH_TX_CQ_CONS),
4220 REG_WR16(bp, BAR_CSTRORM_INTMEM +
4221 CSTORM_SB_HC_DISABLE_OFFSET(port, sb_id,
4222 HC_INDEX_C_ETH_TX_CQ_CONS),
4223 bp->tx_ticks ? 0 : 1);
4227 static inline void bnx2x_free_tpa_pool(struct bnx2x *bp,
4228 struct bnx2x_fastpath *fp, int last)
4232 for (i = 0; i < last; i++) {
4233 struct sw_rx_bd *rx_buf = &(fp->tpa_pool[i]);
4234 struct sk_buff *skb = rx_buf->skb;
4237 DP(NETIF_MSG_IFDOWN, "tpa bin %d empty on free\n", i);
4241 if (fp->tpa_state[i] == BNX2X_TPA_START)
4242 pci_unmap_single(bp->pdev,
4243 pci_unmap_addr(rx_buf, mapping),
4244 bp->rx_buf_use_size,
4245 PCI_DMA_FROMDEVICE);
4252 static void bnx2x_init_rx_rings(struct bnx2x *bp)
4254 int func = BP_FUNC(bp);
4255 int max_agg_queues = CHIP_IS_E1(bp) ? ETH_MAX_AGGREGATION_QUEUES_E1 :
4256 ETH_MAX_AGGREGATION_QUEUES_E1H;
4257 u16 ring_prod, cqe_ring_prod;
4260 bp->rx_buf_use_size = bp->dev->mtu;
4261 bp->rx_buf_use_size += bp->rx_offset + ETH_OVREHEAD;
4262 bp->rx_buf_size = bp->rx_buf_use_size + 64;
4264 if (bp->flags & TPA_ENABLE_FLAG) {
4266 "rx_buf_use_size %d rx_buf_size %d effective_mtu %d\n",
4267 bp->rx_buf_use_size, bp->rx_buf_size,
4268 bp->dev->mtu + ETH_OVREHEAD);
4270 for_each_queue(bp, j) {
4271 struct bnx2x_fastpath *fp = &bp->fp[j];
4273 for (i = 0; i < max_agg_queues; i++) {
4274 fp->tpa_pool[i].skb =
4275 netdev_alloc_skb(bp->dev, bp->rx_buf_size);
4276 if (!fp->tpa_pool[i].skb) {
4277 BNX2X_ERR("Failed to allocate TPA "
4278 "skb pool for queue[%d] - "
4279 "disabling TPA on this "
4281 bnx2x_free_tpa_pool(bp, fp, i);
4282 fp->disable_tpa = 1;
4285 pci_unmap_addr_set((struct sw_rx_bd *)
4286 &bp->fp->tpa_pool[i],
4288 fp->tpa_state[i] = BNX2X_TPA_STOP;
4293 for_each_queue(bp, j) {
4294 struct bnx2x_fastpath *fp = &bp->fp[j];
4297 fp->rx_cons_sb = BNX2X_RX_SB_INDEX;
4298 fp->rx_bd_cons_sb = BNX2X_RX_SB_BD_INDEX;
4300 /* "next page" elements initialization */
4302 for (i = 1; i <= NUM_RX_SGE_PAGES; i++) {
4303 struct eth_rx_sge *sge;
4305 sge = &fp->rx_sge_ring[RX_SGE_CNT * i - 2];
4307 cpu_to_le32(U64_HI(fp->rx_sge_mapping +
4308 BCM_PAGE_SIZE*(i % NUM_RX_SGE_PAGES)));
4310 cpu_to_le32(U64_LO(fp->rx_sge_mapping +
4311 BCM_PAGE_SIZE*(i % NUM_RX_SGE_PAGES)));
4314 bnx2x_init_sge_ring_bit_mask(fp);
4317 for (i = 1; i <= NUM_RX_RINGS; i++) {
4318 struct eth_rx_bd *rx_bd;
4320 rx_bd = &fp->rx_desc_ring[RX_DESC_CNT * i - 2];
4322 cpu_to_le32(U64_HI(fp->rx_desc_mapping +
4323 BCM_PAGE_SIZE*(i % NUM_RX_RINGS)));
4325 cpu_to_le32(U64_LO(fp->rx_desc_mapping +
4326 BCM_PAGE_SIZE*(i % NUM_RX_RINGS)));
4330 for (i = 1; i <= NUM_RCQ_RINGS; i++) {
4331 struct eth_rx_cqe_next_page *nextpg;
4333 nextpg = (struct eth_rx_cqe_next_page *)
4334 &fp->rx_comp_ring[RCQ_DESC_CNT * i - 1];
4336 cpu_to_le32(U64_HI(fp->rx_comp_mapping +
4337 BCM_PAGE_SIZE*(i % NUM_RCQ_RINGS)));
4339 cpu_to_le32(U64_LO(fp->rx_comp_mapping +
4340 BCM_PAGE_SIZE*(i % NUM_RCQ_RINGS)));
4343 /* Allocate SGEs and initialize the ring elements */
4344 for (i = 0, ring_prod = 0;
4345 i < MAX_RX_SGE_CNT*NUM_RX_SGE_PAGES; i++) {
4347 if (bnx2x_alloc_rx_sge(bp, fp, ring_prod) < 0) {
4348 BNX2X_ERR("was only able to allocate "
4350 BNX2X_ERR("disabling TPA for queue[%d]\n", j);
4351 /* Cleanup already allocated elements */
4352 bnx2x_free_rx_sge_range(bp, fp, ring_prod);
4353 bnx2x_free_tpa_pool(bp, fp, max_agg_queues);
4354 fp->disable_tpa = 1;
4358 ring_prod = NEXT_SGE_IDX(ring_prod);
4360 fp->rx_sge_prod = ring_prod;
4362 /* Allocate BDs and initialize BD ring */
4363 fp->rx_comp_cons = 0;
4364 cqe_ring_prod = ring_prod = 0;
4365 for (i = 0; i < bp->rx_ring_size; i++) {
4366 if (bnx2x_alloc_rx_skb(bp, fp, ring_prod) < 0) {
4367 BNX2X_ERR("was only able to allocate "
4369 bp->eth_stats.rx_skb_alloc_failed++;
4372 ring_prod = NEXT_RX_IDX(ring_prod);
4373 cqe_ring_prod = NEXT_RCQ_IDX(cqe_ring_prod);
4374 WARN_ON(ring_prod <= i);
4377 fp->rx_bd_prod = ring_prod;
4378 /* must not have more available CQEs than BDs */
4379 fp->rx_comp_prod = min((u16)(NUM_RCQ_RINGS*RCQ_DESC_CNT),
4381 fp->rx_pkt = fp->rx_calls = 0;
4384 * this will generate an interrupt (to the TSTORM)
4385 * must only be done after chip is initialized
4387 bnx2x_update_rx_prod(bp, fp, ring_prod, fp->rx_comp_prod,
4392 REG_WR(bp, BAR_USTRORM_INTMEM +
4393 USTORM_MEM_WORKAROUND_ADDRESS_OFFSET(func),
4394 U64_LO(fp->rx_comp_mapping));
4395 REG_WR(bp, BAR_USTRORM_INTMEM +
4396 USTORM_MEM_WORKAROUND_ADDRESS_OFFSET(func) + 4,
4397 U64_HI(fp->rx_comp_mapping));
4401 static void bnx2x_init_tx_ring(struct bnx2x *bp)
4405 for_each_queue(bp, j) {
4406 struct bnx2x_fastpath *fp = &bp->fp[j];
4408 for (i = 1; i <= NUM_TX_RINGS; i++) {
4409 struct eth_tx_bd *tx_bd =
4410 &fp->tx_desc_ring[TX_DESC_CNT * i - 1];
4413 cpu_to_le32(U64_HI(fp->tx_desc_mapping +
4414 BCM_PAGE_SIZE*(i % NUM_TX_RINGS)));
4416 cpu_to_le32(U64_LO(fp->tx_desc_mapping +
4417 BCM_PAGE_SIZE*(i % NUM_TX_RINGS)));
4420 fp->tx_pkt_prod = 0;
4421 fp->tx_pkt_cons = 0;
4424 fp->tx_cons_sb = BNX2X_TX_SB_INDEX;
4429 static void bnx2x_init_sp_ring(struct bnx2x *bp)
4431 int func = BP_FUNC(bp);
4433 spin_lock_init(&bp->spq_lock);
4435 bp->spq_left = MAX_SPQ_PENDING;
4436 bp->spq_prod_idx = 0;
4437 bp->dsb_sp_prod = BNX2X_SP_DSB_INDEX;
4438 bp->spq_prod_bd = bp->spq;
4439 bp->spq_last_bd = bp->spq_prod_bd + MAX_SP_DESC_CNT;
4441 REG_WR(bp, XSEM_REG_FAST_MEMORY + XSTORM_SPQ_PAGE_BASE_OFFSET(func),
4442 U64_LO(bp->spq_mapping));
4444 XSEM_REG_FAST_MEMORY + XSTORM_SPQ_PAGE_BASE_OFFSET(func) + 4,
4445 U64_HI(bp->spq_mapping));
4447 REG_WR(bp, XSEM_REG_FAST_MEMORY + XSTORM_SPQ_PROD_OFFSET(func),
4451 static void bnx2x_init_context(struct bnx2x *bp)
4455 for_each_queue(bp, i) {
4456 struct eth_context *context = bnx2x_sp(bp, context[i].eth);
4457 struct bnx2x_fastpath *fp = &bp->fp[i];
4458 u8 sb_id = FP_SB_ID(fp);
4460 context->xstorm_st_context.tx_bd_page_base_hi =
4461 U64_HI(fp->tx_desc_mapping);
4462 context->xstorm_st_context.tx_bd_page_base_lo =
4463 U64_LO(fp->tx_desc_mapping);
4464 context->xstorm_st_context.db_data_addr_hi =
4465 U64_HI(fp->tx_prods_mapping);
4466 context->xstorm_st_context.db_data_addr_lo =
4467 U64_LO(fp->tx_prods_mapping);
4468 context->xstorm_st_context.statistics_data = (BP_CL_ID(bp) |
4469 XSTORM_ETH_ST_CONTEXT_STATISTICS_ENABLE);
4471 context->ustorm_st_context.common.sb_index_numbers =
4472 BNX2X_RX_SB_INDEX_NUM;
4473 context->ustorm_st_context.common.clientId = FP_CL_ID(fp);
4474 context->ustorm_st_context.common.status_block_id = sb_id;
4475 context->ustorm_st_context.common.flags =
4476 USTORM_ETH_ST_CONTEXT_CONFIG_ENABLE_MC_ALIGNMENT;
4477 context->ustorm_st_context.common.mc_alignment_size = 64;
4478 context->ustorm_st_context.common.bd_buff_size =
4479 bp->rx_buf_use_size;
4480 context->ustorm_st_context.common.bd_page_base_hi =
4481 U64_HI(fp->rx_desc_mapping);
4482 context->ustorm_st_context.common.bd_page_base_lo =
4483 U64_LO(fp->rx_desc_mapping);
4484 if (!fp->disable_tpa) {
4485 context->ustorm_st_context.common.flags |=
4486 (USTORM_ETH_ST_CONTEXT_CONFIG_ENABLE_TPA |
4487 USTORM_ETH_ST_CONTEXT_CONFIG_ENABLE_SGE_RING);
4488 context->ustorm_st_context.common.sge_buff_size =
4489 (u16)(BCM_PAGE_SIZE*PAGES_PER_SGE);
4490 context->ustorm_st_context.common.sge_page_base_hi =
4491 U64_HI(fp->rx_sge_mapping);
4492 context->ustorm_st_context.common.sge_page_base_lo =
4493 U64_LO(fp->rx_sge_mapping);
4496 context->cstorm_st_context.sb_index_number =
4497 HC_INDEX_C_ETH_TX_CQ_CONS;
4498 context->cstorm_st_context.status_block_id = sb_id;
4500 context->xstorm_ag_context.cdu_reserved =
4501 CDU_RSRVD_VALUE_TYPE_A(HW_CID(bp, i),
4502 CDU_REGION_NUMBER_XCM_AG,
4503 ETH_CONNECTION_TYPE);
4504 context->ustorm_ag_context.cdu_usage =
4505 CDU_RSRVD_VALUE_TYPE_A(HW_CID(bp, i),
4506 CDU_REGION_NUMBER_UCM_AG,
4507 ETH_CONNECTION_TYPE);
4511 static void bnx2x_init_ind_table(struct bnx2x *bp)
4513 int port = BP_PORT(bp);
4519 DP(NETIF_MSG_IFUP, "Initializing indirection table\n");
4520 for (i = 0; i < TSTORM_INDIRECTION_TABLE_SIZE; i++)
4521 REG_WR8(bp, BAR_TSTRORM_INTMEM +
4522 TSTORM_INDIRECTION_TABLE_OFFSET(port) + i,
4523 i % bp->num_queues);
4525 REG_WR(bp, PRS_REG_A_PRSU_20, 0xf);
4528 static void bnx2x_set_client_config(struct bnx2x *bp)
4530 struct tstorm_eth_client_config tstorm_client = {0};
4531 int port = BP_PORT(bp);
4534 tstorm_client.mtu = bp->dev->mtu + ETH_OVREHEAD;
4535 tstorm_client.statistics_counter_id = BP_CL_ID(bp);
4536 tstorm_client.config_flags =
4537 TSTORM_ETH_CLIENT_CONFIG_STATSITICS_ENABLE;
4539 if (bp->rx_mode && bp->vlgrp) {
4540 tstorm_client.config_flags |=
4541 TSTORM_ETH_CLIENT_CONFIG_VLAN_REMOVAL_ENABLE;
4542 DP(NETIF_MSG_IFUP, "vlan removal enabled\n");
4546 if (bp->flags & TPA_ENABLE_FLAG) {
4547 tstorm_client.max_sges_for_packet =
4548 BCM_PAGE_ALIGN(tstorm_client.mtu) >> BCM_PAGE_SHIFT;
4549 tstorm_client.max_sges_for_packet =
4550 ((tstorm_client.max_sges_for_packet +
4551 PAGES_PER_SGE - 1) & (~(PAGES_PER_SGE - 1))) >>
4552 PAGES_PER_SGE_SHIFT;
4554 tstorm_client.config_flags |=
4555 TSTORM_ETH_CLIENT_CONFIG_ENABLE_SGE_RING;
4558 for_each_queue(bp, i) {
4559 REG_WR(bp, BAR_TSTRORM_INTMEM +
4560 TSTORM_CLIENT_CONFIG_OFFSET(port, bp->fp[i].cl_id),
4561 ((u32 *)&tstorm_client)[0]);
4562 REG_WR(bp, BAR_TSTRORM_INTMEM +
4563 TSTORM_CLIENT_CONFIG_OFFSET(port, bp->fp[i].cl_id) + 4,
4564 ((u32 *)&tstorm_client)[1]);
4567 DP(BNX2X_MSG_OFF, "tstorm_client: 0x%08x 0x%08x\n",
4568 ((u32 *)&tstorm_client)[0], ((u32 *)&tstorm_client)[1]);
4571 static void bnx2x_set_storm_rx_mode(struct bnx2x *bp)
4573 struct tstorm_eth_mac_filter_config tstorm_mac_filter = {0};
4574 int mode = bp->rx_mode;
4575 int mask = (1 << BP_L_ID(bp));
4576 int func = BP_FUNC(bp);
4579 DP(NETIF_MSG_RX_STATUS, "rx mode is %d\n", mode);
4582 case BNX2X_RX_MODE_NONE: /* no Rx */
4583 tstorm_mac_filter.ucast_drop_all = mask;
4584 tstorm_mac_filter.mcast_drop_all = mask;
4585 tstorm_mac_filter.bcast_drop_all = mask;
4587 case BNX2X_RX_MODE_NORMAL:
4588 tstorm_mac_filter.bcast_accept_all = mask;
4590 case BNX2X_RX_MODE_ALLMULTI:
4591 tstorm_mac_filter.mcast_accept_all = mask;
4592 tstorm_mac_filter.bcast_accept_all = mask;
4594 case BNX2X_RX_MODE_PROMISC:
4595 tstorm_mac_filter.ucast_accept_all = mask;
4596 tstorm_mac_filter.mcast_accept_all = mask;
4597 tstorm_mac_filter.bcast_accept_all = mask;
4600 BNX2X_ERR("BAD rx mode (%d)\n", mode);
4604 for (i = 0; i < sizeof(struct tstorm_eth_mac_filter_config)/4; i++) {
4605 REG_WR(bp, BAR_TSTRORM_INTMEM +
4606 TSTORM_MAC_FILTER_CONFIG_OFFSET(func) + i * 4,
4607 ((u32 *)&tstorm_mac_filter)[i]);
4609 /* DP(NETIF_MSG_IFUP, "tstorm_mac_filter[%d]: 0x%08x\n", i,
4610 ((u32 *)&tstorm_mac_filter)[i]); */
4613 if (mode != BNX2X_RX_MODE_NONE)
4614 bnx2x_set_client_config(bp);
4617 static void bnx2x_init_internal_common(struct bnx2x *bp)
4621 /* Zero this manually as its initialization is
4622 currently missing in the initTool */
4623 for (i = 0; i < (USTORM_AGG_DATA_SIZE >> 2); i++)
4624 REG_WR(bp, BAR_USTRORM_INTMEM +
4625 USTORM_AGG_DATA_OFFSET + i * 4, 0);
4628 static void bnx2x_init_internal_port(struct bnx2x *bp)
4630 int port = BP_PORT(bp);
4632 REG_WR(bp, BAR_USTRORM_INTMEM + USTORM_HC_BTR_OFFSET(port), BNX2X_BTR);
4633 REG_WR(bp, BAR_CSTRORM_INTMEM + CSTORM_HC_BTR_OFFSET(port), BNX2X_BTR);
4634 REG_WR(bp, BAR_TSTRORM_INTMEM + TSTORM_HC_BTR_OFFSET(port), BNX2X_BTR);
4635 REG_WR(bp, BAR_XSTRORM_INTMEM + XSTORM_HC_BTR_OFFSET(port), BNX2X_BTR);
4638 static void bnx2x_init_internal_func(struct bnx2x *bp)
4640 struct tstorm_eth_function_common_config tstorm_config = {0};
4641 struct stats_indication_flags stats_flags = {0};
4642 int port = BP_PORT(bp);
4643 int func = BP_FUNC(bp);
4648 tstorm_config.config_flags = MULTI_FLAGS;
4649 tstorm_config.rss_result_mask = MULTI_MASK;
4652 tstorm_config.leading_client_id = BP_L_ID(bp);
4654 REG_WR(bp, BAR_TSTRORM_INTMEM +
4655 TSTORM_FUNCTION_COMMON_CONFIG_OFFSET(func),
4656 (*(u32 *)&tstorm_config));
4658 bp->rx_mode = BNX2X_RX_MODE_NONE; /* no rx until link is up */
4659 bnx2x_set_storm_rx_mode(bp);
4661 /* reset xstorm per client statistics */
4662 for (i = 0; i < sizeof(struct xstorm_per_client_stats) / 4; i++) {
4663 REG_WR(bp, BAR_XSTRORM_INTMEM +
4664 XSTORM_PER_COUNTER_ID_STATS_OFFSET(port, BP_CL_ID(bp)) +
4667 /* reset tstorm per client statistics */
4668 for (i = 0; i < sizeof(struct tstorm_per_client_stats) / 4; i++) {
4669 REG_WR(bp, BAR_TSTRORM_INTMEM +
4670 TSTORM_PER_COUNTER_ID_STATS_OFFSET(port, BP_CL_ID(bp)) +
4674 /* Init statistics related context */
4675 stats_flags.collect_eth = 1;
4677 REG_WR(bp, BAR_XSTRORM_INTMEM + XSTORM_STATS_FLAGS_OFFSET(func),
4678 ((u32 *)&stats_flags)[0]);
4679 REG_WR(bp, BAR_XSTRORM_INTMEM + XSTORM_STATS_FLAGS_OFFSET(func) + 4,
4680 ((u32 *)&stats_flags)[1]);
4682 REG_WR(bp, BAR_TSTRORM_INTMEM + TSTORM_STATS_FLAGS_OFFSET(func),
4683 ((u32 *)&stats_flags)[0]);
4684 REG_WR(bp, BAR_TSTRORM_INTMEM + TSTORM_STATS_FLAGS_OFFSET(func) + 4,
4685 ((u32 *)&stats_flags)[1]);
4687 REG_WR(bp, BAR_CSTRORM_INTMEM + CSTORM_STATS_FLAGS_OFFSET(func),
4688 ((u32 *)&stats_flags)[0]);
4689 REG_WR(bp, BAR_CSTRORM_INTMEM + CSTORM_STATS_FLAGS_OFFSET(func) + 4,
4690 ((u32 *)&stats_flags)[1]);
4692 REG_WR(bp, BAR_XSTRORM_INTMEM +
4693 XSTORM_ETH_STATS_QUERY_ADDR_OFFSET(func),
4694 U64_LO(bnx2x_sp_mapping(bp, fw_stats)));
4695 REG_WR(bp, BAR_XSTRORM_INTMEM +
4696 XSTORM_ETH_STATS_QUERY_ADDR_OFFSET(func) + 4,
4697 U64_HI(bnx2x_sp_mapping(bp, fw_stats)));
4699 REG_WR(bp, BAR_TSTRORM_INTMEM +
4700 TSTORM_ETH_STATS_QUERY_ADDR_OFFSET(func),
4701 U64_LO(bnx2x_sp_mapping(bp, fw_stats)));
4702 REG_WR(bp, BAR_TSTRORM_INTMEM +
4703 TSTORM_ETH_STATS_QUERY_ADDR_OFFSET(func) + 4,
4704 U64_HI(bnx2x_sp_mapping(bp, fw_stats)));
4706 if (CHIP_IS_E1H(bp)) {
4707 REG_WR8(bp, BAR_XSTRORM_INTMEM + XSTORM_FUNCTION_MODE_OFFSET,
4709 REG_WR8(bp, BAR_TSTRORM_INTMEM + TSTORM_FUNCTION_MODE_OFFSET,
4711 REG_WR8(bp, BAR_CSTRORM_INTMEM + CSTORM_FUNCTION_MODE_OFFSET,
4713 REG_WR8(bp, BAR_USTRORM_INTMEM + USTORM_FUNCTION_MODE_OFFSET,
4716 REG_WR16(bp, BAR_XSTRORM_INTMEM + XSTORM_E1HOV_OFFSET(func),
4720 /* Init CQ ring mapping and aggregation size */
4721 max_agg_size = min((u32)(bp->rx_buf_use_size +
4722 8*BCM_PAGE_SIZE*PAGES_PER_SGE),
4724 for_each_queue(bp, i) {
4725 struct bnx2x_fastpath *fp = &bp->fp[i];
4727 REG_WR(bp, BAR_USTRORM_INTMEM +
4728 USTORM_CQE_PAGE_BASE_OFFSET(port, FP_CL_ID(fp)),
4729 U64_LO(fp->rx_comp_mapping));
4730 REG_WR(bp, BAR_USTRORM_INTMEM +
4731 USTORM_CQE_PAGE_BASE_OFFSET(port, FP_CL_ID(fp)) + 4,
4732 U64_HI(fp->rx_comp_mapping));
4734 REG_WR16(bp, BAR_USTRORM_INTMEM +
4735 USTORM_MAX_AGG_SIZE_OFFSET(port, FP_CL_ID(fp)),
4740 static void bnx2x_init_internal(struct bnx2x *bp, u32 load_code)
4742 switch (load_code) {
4743 case FW_MSG_CODE_DRV_LOAD_COMMON:
4744 bnx2x_init_internal_common(bp);
4747 case FW_MSG_CODE_DRV_LOAD_PORT:
4748 bnx2x_init_internal_port(bp);
4751 case FW_MSG_CODE_DRV_LOAD_FUNCTION:
4752 bnx2x_init_internal_func(bp);
4756 BNX2X_ERR("Unknown load_code (0x%x) from MCP\n", load_code);
4761 static void bnx2x_nic_init(struct bnx2x *bp, u32 load_code)
4765 for_each_queue(bp, i) {
4766 struct bnx2x_fastpath *fp = &bp->fp[i];
4769 fp->state = BNX2X_FP_STATE_CLOSED;
4771 fp->cl_id = BP_L_ID(bp) + i;
4772 fp->sb_id = fp->cl_id;
4774 "bnx2x_init_sb(%p,%p) index %d cl_id %d sb %d\n",
4775 bp, fp->status_blk, i, FP_CL_ID(fp), FP_SB_ID(fp));
4776 bnx2x_init_sb(bp, FP_SB_ID(fp), fp->status_blk,
4777 fp->status_blk_mapping);
4780 bnx2x_init_def_sb(bp, bp->def_status_blk,
4781 bp->def_status_blk_mapping, DEF_SB_ID);
4782 bnx2x_update_coalesce(bp);
4783 bnx2x_init_rx_rings(bp);
4784 bnx2x_init_tx_ring(bp);
4785 bnx2x_init_sp_ring(bp);
4786 bnx2x_init_context(bp);
4787 bnx2x_init_internal(bp, load_code);
4788 bnx2x_init_ind_table(bp);
4789 bnx2x_int_enable(bp);
4792 /* end of nic init */
4795 * gzip service functions
4798 static int bnx2x_gunzip_init(struct bnx2x *bp)
4800 bp->gunzip_buf = pci_alloc_consistent(bp->pdev, FW_BUF_SIZE,
4801 &bp->gunzip_mapping);
4802 if (bp->gunzip_buf == NULL)
4805 bp->strm = kmalloc(sizeof(*bp->strm), GFP_KERNEL);
4806 if (bp->strm == NULL)
4809 bp->strm->workspace = kmalloc(zlib_inflate_workspacesize(),
4811 if (bp->strm->workspace == NULL)
4821 pci_free_consistent(bp->pdev, FW_BUF_SIZE, bp->gunzip_buf,
4822 bp->gunzip_mapping);
4823 bp->gunzip_buf = NULL;
4826 printk(KERN_ERR PFX "%s: Cannot allocate firmware buffer for"
4827 " un-compression\n", bp->dev->name);
4831 static void bnx2x_gunzip_end(struct bnx2x *bp)
4833 kfree(bp->strm->workspace);
4838 if (bp->gunzip_buf) {
4839 pci_free_consistent(bp->pdev, FW_BUF_SIZE, bp->gunzip_buf,
4840 bp->gunzip_mapping);
4841 bp->gunzip_buf = NULL;
4845 static int bnx2x_gunzip(struct bnx2x *bp, u8 *zbuf, int len)
4849 /* check gzip header */
4850 if ((zbuf[0] != 0x1f) || (zbuf[1] != 0x8b) || (zbuf[2] != Z_DEFLATED))
4857 if (zbuf[3] & FNAME)
4858 while ((zbuf[n++] != 0) && (n < len));
4860 bp->strm->next_in = zbuf + n;
4861 bp->strm->avail_in = len - n;
4862 bp->strm->next_out = bp->gunzip_buf;
4863 bp->strm->avail_out = FW_BUF_SIZE;
4865 rc = zlib_inflateInit2(bp->strm, -MAX_WBITS);
4869 rc = zlib_inflate(bp->strm, Z_FINISH);
4870 if ((rc != Z_OK) && (rc != Z_STREAM_END))
4871 printk(KERN_ERR PFX "%s: Firmware decompression error: %s\n",
4872 bp->dev->name, bp->strm->msg);
4874 bp->gunzip_outlen = (FW_BUF_SIZE - bp->strm->avail_out);
4875 if (bp->gunzip_outlen & 0x3)
4876 printk(KERN_ERR PFX "%s: Firmware decompression error:"
4877 " gunzip_outlen (%d) not aligned\n",
4878 bp->dev->name, bp->gunzip_outlen);
4879 bp->gunzip_outlen >>= 2;
4881 zlib_inflateEnd(bp->strm);
4883 if (rc == Z_STREAM_END)
4889 /* nic load/unload */
4892 * General service functions
4895 /* send a NIG loopback debug packet */
4896 static void bnx2x_lb_pckt(struct bnx2x *bp)
4900 /* Ethernet source and destination addresses */
4901 wb_write[0] = 0x55555555;
4902 wb_write[1] = 0x55555555;
4903 wb_write[2] = 0x20; /* SOP */
4904 REG_WR_DMAE(bp, NIG_REG_DEBUG_PACKET_LB, wb_write, 3);
4906 /* NON-IP protocol */
4907 wb_write[0] = 0x09000000;
4908 wb_write[1] = 0x55555555;
4909 wb_write[2] = 0x10; /* EOP, eop_bvalid = 0 */
4910 REG_WR_DMAE(bp, NIG_REG_DEBUG_PACKET_LB, wb_write, 3);
4913 /* some of the internal memories
4914 * are not directly readable from the driver
4915 * to test them we send debug packets
4917 static int bnx2x_int_mem_test(struct bnx2x *bp)
4923 if (CHIP_REV_IS_FPGA(bp))
4925 else if (CHIP_REV_IS_EMUL(bp))
4930 DP(NETIF_MSG_HW, "start part1\n");
4932 /* Disable inputs of parser neighbor blocks */
4933 REG_WR(bp, TSDM_REG_ENABLE_IN1, 0x0);
4934 REG_WR(bp, TCM_REG_PRS_IFEN, 0x0);
4935 REG_WR(bp, CFC_REG_DEBUG0, 0x1);
4936 NIG_WR(NIG_REG_PRS_REQ_IN_EN, 0x0);
4938 /* Write 0 to parser credits for CFC search request */
4939 REG_WR(bp, PRS_REG_CFC_SEARCH_INITIAL_CREDIT, 0x0);
4941 /* send Ethernet packet */
4944 /* TODO do i reset NIG statistic? */
4945 /* Wait until NIG register shows 1 packet of size 0x10 */
4946 count = 1000 * factor;
4949 bnx2x_read_dmae(bp, NIG_REG_STAT2_BRB_OCTET, 2);
4950 val = *bnx2x_sp(bp, wb_data[0]);
4958 BNX2X_ERR("NIG timeout val = 0x%x\n", val);
4962 /* Wait until PRS register shows 1 packet */
4963 count = 1000 * factor;
4965 val = REG_RD(bp, PRS_REG_NUM_OF_PACKETS);
4973 BNX2X_ERR("PRS timeout val = 0x%x\n", val);
4977 /* Reset and init BRB, PRS */
4978 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR, 0x03);
4980 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, 0x03);
4982 bnx2x_init_block(bp, BRB1_COMMON_START, BRB1_COMMON_END);
4983 bnx2x_init_block(bp, PRS_COMMON_START, PRS_COMMON_END);
4985 DP(NETIF_MSG_HW, "part2\n");
4987 /* Disable inputs of parser neighbor blocks */
4988 REG_WR(bp, TSDM_REG_ENABLE_IN1, 0x0);
4989 REG_WR(bp, TCM_REG_PRS_IFEN, 0x0);
4990 REG_WR(bp, CFC_REG_DEBUG0, 0x1);
4991 NIG_WR(NIG_REG_PRS_REQ_IN_EN, 0x0);
4993 /* Write 0 to parser credits for CFC search request */
4994 REG_WR(bp, PRS_REG_CFC_SEARCH_INITIAL_CREDIT, 0x0);
4996 /* send 10 Ethernet packets */
4997 for (i = 0; i < 10; i++)
5000 /* Wait until NIG register shows 10 + 1
5001 packets of size 11*0x10 = 0xb0 */
5002 count = 1000 * factor;
5005 bnx2x_read_dmae(bp, NIG_REG_STAT2_BRB_OCTET, 2);
5006 val = *bnx2x_sp(bp, wb_data[0]);
5014 BNX2X_ERR("NIG timeout val = 0x%x\n", val);
5018 /* Wait until PRS register shows 2 packets */
5019 val = REG_RD(bp, PRS_REG_NUM_OF_PACKETS);
5021 BNX2X_ERR("PRS timeout val = 0x%x\n", val);
5023 /* Write 1 to parser credits for CFC search request */
5024 REG_WR(bp, PRS_REG_CFC_SEARCH_INITIAL_CREDIT, 0x1);
5026 /* Wait until PRS register shows 3 packets */
5027 msleep(10 * factor);
5028 /* Wait until NIG register shows 1 packet of size 0x10 */
5029 val = REG_RD(bp, PRS_REG_NUM_OF_PACKETS);
5031 BNX2X_ERR("PRS timeout val = 0x%x\n", val);
5033 /* clear NIG EOP FIFO */
5034 for (i = 0; i < 11; i++)
5035 REG_RD(bp, NIG_REG_INGRESS_EOP_LB_FIFO);
5036 val = REG_RD(bp, NIG_REG_INGRESS_EOP_LB_EMPTY);
5038 BNX2X_ERR("clear of NIG failed\n");
5042 /* Reset and init BRB, PRS, NIG */
5043 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR, 0x03);
5045 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, 0x03);
5047 bnx2x_init_block(bp, BRB1_COMMON_START, BRB1_COMMON_END);
5048 bnx2x_init_block(bp, PRS_COMMON_START, PRS_COMMON_END);
5051 REG_WR(bp, PRS_REG_NIC_MODE, 1);
5054 /* Enable inputs of parser neighbor blocks */
5055 REG_WR(bp, TSDM_REG_ENABLE_IN1, 0x7fffffff);
5056 REG_WR(bp, TCM_REG_PRS_IFEN, 0x1);
5057 REG_WR(bp, CFC_REG_DEBUG0, 0x0);
5058 NIG_WR(NIG_REG_PRS_REQ_IN_EN, 0x1);
5060 DP(NETIF_MSG_HW, "done\n");
5065 static void enable_blocks_attention(struct bnx2x *bp)
5067 REG_WR(bp, PXP_REG_PXP_INT_MASK_0, 0);
5068 REG_WR(bp, PXP_REG_PXP_INT_MASK_1, 0);
5069 REG_WR(bp, DORQ_REG_DORQ_INT_MASK, 0);
5070 REG_WR(bp, CFC_REG_CFC_INT_MASK, 0);
5071 REG_WR(bp, QM_REG_QM_INT_MASK, 0);
5072 REG_WR(bp, TM_REG_TM_INT_MASK, 0);
5073 REG_WR(bp, XSDM_REG_XSDM_INT_MASK_0, 0);
5074 REG_WR(bp, XSDM_REG_XSDM_INT_MASK_1, 0);
5075 REG_WR(bp, XCM_REG_XCM_INT_MASK, 0);
5076 /* REG_WR(bp, XSEM_REG_XSEM_INT_MASK_0, 0); */
5077 /* REG_WR(bp, XSEM_REG_XSEM_INT_MASK_1, 0); */
5078 REG_WR(bp, USDM_REG_USDM_INT_MASK_0, 0);
5079 REG_WR(bp, USDM_REG_USDM_INT_MASK_1, 0);
5080 REG_WR(bp, UCM_REG_UCM_INT_MASK, 0);
5081 /* REG_WR(bp, USEM_REG_USEM_INT_MASK_0, 0); */
5082 /* REG_WR(bp, USEM_REG_USEM_INT_MASK_1, 0); */
5083 REG_WR(bp, GRCBASE_UPB + PB_REG_PB_INT_MASK, 0);
5084 REG_WR(bp, CSDM_REG_CSDM_INT_MASK_0, 0);
5085 REG_WR(bp, CSDM_REG_CSDM_INT_MASK_1, 0);
5086 REG_WR(bp, CCM_REG_CCM_INT_MASK, 0);
5087 /* REG_WR(bp, CSEM_REG_CSEM_INT_MASK_0, 0); */
5088 /* REG_WR(bp, CSEM_REG_CSEM_INT_MASK_1, 0); */
5089 if (CHIP_REV_IS_FPGA(bp))
5090 REG_WR(bp, PXP2_REG_PXP2_INT_MASK_0, 0x580000);
5092 REG_WR(bp, PXP2_REG_PXP2_INT_MASK_0, 0x480000);
5093 REG_WR(bp, TSDM_REG_TSDM_INT_MASK_0, 0);
5094 REG_WR(bp, TSDM_REG_TSDM_INT_MASK_1, 0);
5095 REG_WR(bp, TCM_REG_TCM_INT_MASK, 0);
5096 /* REG_WR(bp, TSEM_REG_TSEM_INT_MASK_0, 0); */
5097 /* REG_WR(bp, TSEM_REG_TSEM_INT_MASK_1, 0); */
5098 REG_WR(bp, CDU_REG_CDU_INT_MASK, 0);
5099 REG_WR(bp, DMAE_REG_DMAE_INT_MASK, 0);
5100 /* REG_WR(bp, MISC_REG_MISC_INT_MASK, 0); */
5101 REG_WR(bp, PBF_REG_PBF_INT_MASK, 0X18); /* bit 3,4 masked */
5105 static int bnx2x_init_common(struct bnx2x *bp)
5109 DP(BNX2X_MSG_MCP, "starting common init func %d\n", BP_FUNC(bp));
5111 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, 0xffffffff);
5112 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET, 0xfffc);
5114 bnx2x_init_block(bp, MISC_COMMON_START, MISC_COMMON_END);
5115 if (CHIP_IS_E1H(bp))
5116 REG_WR(bp, MISC_REG_E1HMF_MODE, IS_E1HMF(bp));
5118 REG_WR(bp, MISC_REG_LCPLL_CTRL_REG_2, 0x100);
5120 REG_WR(bp, MISC_REG_LCPLL_CTRL_REG_2, 0x0);
5122 bnx2x_init_block(bp, PXP_COMMON_START, PXP_COMMON_END);
5123 if (CHIP_IS_E1(bp)) {
5124 /* enable HW interrupt from PXP on USDM overflow
5125 bit 16 on INT_MASK_0 */
5126 REG_WR(bp, PXP_REG_PXP_INT_MASK_0, 0);
5129 bnx2x_init_block(bp, PXP2_COMMON_START, PXP2_COMMON_END);
5133 REG_WR(bp, PXP2_REG_RQ_QM_ENDIAN_M, 1);
5134 REG_WR(bp, PXP2_REG_RQ_TM_ENDIAN_M, 1);
5135 REG_WR(bp, PXP2_REG_RQ_SRC_ENDIAN_M, 1);
5136 REG_WR(bp, PXP2_REG_RQ_CDU_ENDIAN_M, 1);
5137 REG_WR(bp, PXP2_REG_RQ_DBG_ENDIAN_M, 1);
5138 REG_WR(bp, PXP2_REG_RQ_HC_ENDIAN_M, 1);
5140 /* REG_WR(bp, PXP2_REG_RD_PBF_SWAP_MODE, 1); */
5141 REG_WR(bp, PXP2_REG_RD_QM_SWAP_MODE, 1);
5142 REG_WR(bp, PXP2_REG_RD_TM_SWAP_MODE, 1);
5143 REG_WR(bp, PXP2_REG_RD_SRC_SWAP_MODE, 1);
5144 REG_WR(bp, PXP2_REG_RD_CDURD_SWAP_MODE, 1);
5149 REG_WR(bp, PRS_REG_NIC_MODE, 1);
5152 REG_WR(bp, PXP2_REG_RQ_CDU_P_SIZE, 2);
5154 REG_WR(bp, PXP2_REG_RQ_TM_P_SIZE, 5);
5155 REG_WR(bp, PXP2_REG_RQ_QM_P_SIZE, 5);
5156 REG_WR(bp, PXP2_REG_RQ_SRC_P_SIZE, 5);
5159 if (CHIP_REV_IS_FPGA(bp) && CHIP_IS_E1H(bp))
5160 REG_WR(bp, PXP2_REG_PGL_TAGS_LIMIT, 0x1);
5162 /* let the HW do it's magic ... */
5164 /* finish PXP init */
5165 val = REG_RD(bp, PXP2_REG_RQ_CFG_DONE);
5167 BNX2X_ERR("PXP2 CFG failed\n");
5170 val = REG_RD(bp, PXP2_REG_RD_INIT_DONE);
5172 BNX2X_ERR("PXP2 RD_INIT failed\n");
5176 REG_WR(bp, PXP2_REG_RQ_DISABLE_INPUTS, 0);
5177 REG_WR(bp, PXP2_REG_RD_DISABLE_INPUTS, 0);
5179 bnx2x_init_block(bp, DMAE_COMMON_START, DMAE_COMMON_END);
5181 /* clean the DMAE memory */
5183 bnx2x_init_fill(bp, TSEM_REG_PRAM, 0, 8);
5185 bnx2x_init_block(bp, TCM_COMMON_START, TCM_COMMON_END);
5186 bnx2x_init_block(bp, UCM_COMMON_START, UCM_COMMON_END);
5187 bnx2x_init_block(bp, CCM_COMMON_START, CCM_COMMON_END);
5188 bnx2x_init_block(bp, XCM_COMMON_START, XCM_COMMON_END);
5190 bnx2x_read_dmae(bp, XSEM_REG_PASSIVE_BUFFER, 3);
5191 bnx2x_read_dmae(bp, CSEM_REG_PASSIVE_BUFFER, 3);
5192 bnx2x_read_dmae(bp, TSEM_REG_PASSIVE_BUFFER, 3);
5193 bnx2x_read_dmae(bp, USEM_REG_PASSIVE_BUFFER, 3);
5195 bnx2x_init_block(bp, QM_COMMON_START, QM_COMMON_END);
5196 /* soft reset pulse */
5197 REG_WR(bp, QM_REG_SOFT_RESET, 1);
5198 REG_WR(bp, QM_REG_SOFT_RESET, 0);
5201 bnx2x_init_block(bp, TIMERS_COMMON_START, TIMERS_COMMON_END);
5204 bnx2x_init_block(bp, DQ_COMMON_START, DQ_COMMON_END);
5205 REG_WR(bp, DORQ_REG_DPM_CID_OFST, BCM_PAGE_SHIFT);
5206 if (!CHIP_REV_IS_SLOW(bp)) {
5207 /* enable hw interrupt from doorbell Q */
5208 REG_WR(bp, DORQ_REG_DORQ_INT_MASK, 0);
5211 bnx2x_init_block(bp, BRB1_COMMON_START, BRB1_COMMON_END);
5212 if (CHIP_REV_IS_SLOW(bp)) {
5213 /* fix for emulation and FPGA for no pause */
5214 REG_WR(bp, BRB1_REG_PAUSE_HIGH_THRESHOLD_0, 513);
5215 REG_WR(bp, BRB1_REG_PAUSE_HIGH_THRESHOLD_1, 513);
5216 REG_WR(bp, BRB1_REG_PAUSE_LOW_THRESHOLD_0, 0);
5217 REG_WR(bp, BRB1_REG_PAUSE_LOW_THRESHOLD_1, 0);
5220 bnx2x_init_block(bp, PRS_COMMON_START, PRS_COMMON_END);
5221 if (CHIP_IS_E1H(bp))
5222 REG_WR(bp, PRS_REG_E1HOV_MODE, IS_E1HMF(bp));
5224 bnx2x_init_block(bp, TSDM_COMMON_START, TSDM_COMMON_END);
5225 bnx2x_init_block(bp, CSDM_COMMON_START, CSDM_COMMON_END);
5226 bnx2x_init_block(bp, USDM_COMMON_START, USDM_COMMON_END);
5227 bnx2x_init_block(bp, XSDM_COMMON_START, XSDM_COMMON_END);
5229 if (CHIP_IS_E1H(bp)) {
5230 bnx2x_init_fill(bp, TSTORM_INTMEM_ADDR, 0,
5231 STORM_INTMEM_SIZE_E1H/2);
5233 TSTORM_INTMEM_ADDR + STORM_INTMEM_SIZE_E1H/2,
5234 0, STORM_INTMEM_SIZE_E1H/2);
5235 bnx2x_init_fill(bp, CSTORM_INTMEM_ADDR, 0,
5236 STORM_INTMEM_SIZE_E1H/2);
5238 CSTORM_INTMEM_ADDR + STORM_INTMEM_SIZE_E1H/2,
5239 0, STORM_INTMEM_SIZE_E1H/2);
5240 bnx2x_init_fill(bp, XSTORM_INTMEM_ADDR, 0,
5241 STORM_INTMEM_SIZE_E1H/2);
5243 XSTORM_INTMEM_ADDR + STORM_INTMEM_SIZE_E1H/2,
5244 0, STORM_INTMEM_SIZE_E1H/2);
5245 bnx2x_init_fill(bp, USTORM_INTMEM_ADDR, 0,
5246 STORM_INTMEM_SIZE_E1H/2);
5248 USTORM_INTMEM_ADDR + STORM_INTMEM_SIZE_E1H/2,
5249 0, STORM_INTMEM_SIZE_E1H/2);
5251 bnx2x_init_fill(bp, TSTORM_INTMEM_ADDR, 0,
5252 STORM_INTMEM_SIZE_E1);
5253 bnx2x_init_fill(bp, CSTORM_INTMEM_ADDR, 0,
5254 STORM_INTMEM_SIZE_E1);
5255 bnx2x_init_fill(bp, XSTORM_INTMEM_ADDR, 0,
5256 STORM_INTMEM_SIZE_E1);
5257 bnx2x_init_fill(bp, USTORM_INTMEM_ADDR, 0,
5258 STORM_INTMEM_SIZE_E1);
5261 bnx2x_init_block(bp, TSEM_COMMON_START, TSEM_COMMON_END);
5262 bnx2x_init_block(bp, USEM_COMMON_START, USEM_COMMON_END);
5263 bnx2x_init_block(bp, CSEM_COMMON_START, CSEM_COMMON_END);
5264 bnx2x_init_block(bp, XSEM_COMMON_START, XSEM_COMMON_END);
5267 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR,
5269 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET,
5272 bnx2x_init_block(bp, UPB_COMMON_START, UPB_COMMON_END);
5273 bnx2x_init_block(bp, XPB_COMMON_START, XPB_COMMON_END);
5274 bnx2x_init_block(bp, PBF_COMMON_START, PBF_COMMON_END);
5276 REG_WR(bp, SRC_REG_SOFT_RST, 1);
5277 for (i = SRC_REG_KEYRSS0_0; i <= SRC_REG_KEYRSS1_9; i += 4) {
5278 REG_WR(bp, i, 0xc0cac01a);
5279 /* TODO: replace with something meaningful */
5281 if (CHIP_IS_E1H(bp))
5282 bnx2x_init_block(bp, SRCH_COMMON_START, SRCH_COMMON_END);
5283 REG_WR(bp, SRC_REG_SOFT_RST, 0);
5285 if (sizeof(union cdu_context) != 1024)
5286 /* we currently assume that a context is 1024 bytes */
5287 printk(KERN_ALERT PFX "please adjust the size of"
5288 " cdu_context(%ld)\n", (long)sizeof(union cdu_context));
5290 bnx2x_init_block(bp, CDU_COMMON_START, CDU_COMMON_END);
5291 val = (4 << 24) + (0 << 12) + 1024;
5292 REG_WR(bp, CDU_REG_CDU_GLOBAL_PARAMS, val);
5293 if (CHIP_IS_E1(bp)) {
5294 /* !!! fix pxp client crdit until excel update */
5295 REG_WR(bp, CDU_REG_CDU_DEBUG, 0x264);
5296 REG_WR(bp, CDU_REG_CDU_DEBUG, 0);
5299 bnx2x_init_block(bp, CFC_COMMON_START, CFC_COMMON_END);
5300 REG_WR(bp, CFC_REG_INIT_REG, 0x7FF);
5302 bnx2x_init_block(bp, HC_COMMON_START, HC_COMMON_END);
5303 bnx2x_init_block(bp, MISC_AEU_COMMON_START, MISC_AEU_COMMON_END);
5305 /* PXPCS COMMON comes here */
5306 /* Reset PCIE errors for debug */
5307 REG_WR(bp, 0x2814, 0xffffffff);
5308 REG_WR(bp, 0x3820, 0xffffffff);
5310 /* EMAC0 COMMON comes here */
5311 /* EMAC1 COMMON comes here */
5312 /* DBU COMMON comes here */
5313 /* DBG COMMON comes here */
5315 bnx2x_init_block(bp, NIG_COMMON_START, NIG_COMMON_END);
5316 if (CHIP_IS_E1H(bp)) {
5317 REG_WR(bp, NIG_REG_LLH_MF_MODE, IS_E1HMF(bp));
5318 REG_WR(bp, NIG_REG_LLH_E1HOV_MODE, IS_E1HMF(bp));
5321 if (CHIP_REV_IS_SLOW(bp))
5324 /* finish CFC init */
5325 val = reg_poll(bp, CFC_REG_LL_INIT_DONE, 1, 100, 10);
5327 BNX2X_ERR("CFC LL_INIT failed\n");
5330 val = reg_poll(bp, CFC_REG_AC_INIT_DONE, 1, 100, 10);
5332 BNX2X_ERR("CFC AC_INIT failed\n");
5335 val = reg_poll(bp, CFC_REG_CAM_INIT_DONE, 1, 100, 10);
5337 BNX2X_ERR("CFC CAM_INIT failed\n");
5340 REG_WR(bp, CFC_REG_DEBUG0, 0);
5342 /* read NIG statistic
5343 to see if this is our first up since powerup */
5344 bnx2x_read_dmae(bp, NIG_REG_STAT2_BRB_OCTET, 2);
5345 val = *bnx2x_sp(bp, wb_data[0]);
5347 /* do internal memory self test */
5348 if ((CHIP_IS_E1(bp)) && (val == 0) && bnx2x_int_mem_test(bp)) {
5349 BNX2X_ERR("internal mem self test failed\n");
5353 switch (bp->common.board & SHARED_HW_CFG_BOARD_TYPE_MASK) {
5354 case SHARED_HW_CFG_BOARD_TYPE_BCM957710A1022G:
5355 /* Fan failure is indicated by SPIO 5 */
5356 bnx2x_set_spio(bp, MISC_REGISTERS_SPIO_5,
5357 MISC_REGISTERS_SPIO_INPUT_HI_Z);
5359 /* set to active low mode */
5360 val = REG_RD(bp, MISC_REG_SPIO_INT);
5361 val |= ((1 << MISC_REGISTERS_SPIO_5) <<
5362 MISC_REGISTERS_SPIO_INT_OLD_SET_POS);
5363 REG_WR(bp, MISC_REG_SPIO_INT, val);
5365 /* enable interrupt to signal the IGU */
5366 val = REG_RD(bp, MISC_REG_SPIO_EVENT_EN);
5367 val |= (1 << MISC_REGISTERS_SPIO_5);
5368 REG_WR(bp, MISC_REG_SPIO_EVENT_EN, val);
5375 /* clear PXP2 attentions */
5376 REG_RD(bp, PXP2_REG_PXP2_INT_STS_CLR_0);
5378 enable_blocks_attention(bp);
5380 if (bp->flags & TPA_ENABLE_FLAG) {
5381 struct tstorm_eth_tpa_exist tmp = {0};
5385 REG_WR(bp, BAR_TSTRORM_INTMEM + TSTORM_TPA_EXIST_OFFSET,
5387 REG_WR(bp, BAR_TSTRORM_INTMEM + TSTORM_TPA_EXIST_OFFSET + 4,
5394 static int bnx2x_init_port(struct bnx2x *bp)
5396 int port = BP_PORT(bp);
5399 DP(BNX2X_MSG_MCP, "starting port init port %x\n", port);
5401 REG_WR(bp, NIG_REG_MASK_INTERRUPT_PORT0 + port*4, 0);
5403 /* Port PXP comes here */
5404 /* Port PXP2 comes here */
5409 wb_write[0] = ONCHIP_ADDR1(bp->timers_mapping);
5410 wb_write[1] = ONCHIP_ADDR2(bp->timers_mapping);
5411 REG_WR_DMAE(bp, PXP2_REG_RQ_ONCHIP_AT + i*8, wb_write, 2);
5412 REG_WR(bp, PXP2_REG_PSWRQ_TM0_L2P + func*4, PXP_ONE_ILT(i));
5417 wb_write[0] = ONCHIP_ADDR1(bp->qm_mapping);
5418 wb_write[1] = ONCHIP_ADDR2(bp->qm_mapping);
5419 REG_WR_DMAE(bp, PXP2_REG_RQ_ONCHIP_AT + i*8, wb_write, 2);
5420 REG_WR(bp, PXP2_REG_PSWRQ_QM0_L2P + func*4, PXP_ONE_ILT(i));
5425 wb_write[0] = ONCHIP_ADDR1(bp->t1_mapping);
5426 wb_write[1] = ONCHIP_ADDR2(bp->t1_mapping);
5427 REG_WR_DMAE(bp, PXP2_REG_RQ_ONCHIP_AT + i*8, wb_write, 2);
5428 REG_WR(bp, PXP2_REG_PSWRQ_SRC0_L2P + func*4, PXP_ONE_ILT(i));
5430 /* Port CMs come here */
5432 /* Port QM comes here */
5434 REG_WR(bp, TM_REG_LIN0_SCAN_TIME + func*4, 1024/64*20);
5435 REG_WR(bp, TM_REG_LIN0_MAX_ACTIVE_CID + func*4, 31);
5437 bnx2x_init_block(bp, func ? TIMERS_PORT1_START : TIMERS_PORT0_START,
5438 func ? TIMERS_PORT1_END : TIMERS_PORT0_END);
5440 /* Port DQ comes here */
5441 /* Port BRB1 comes here */
5442 /* Port PRS comes here */
5443 /* Port TSDM comes here */
5444 /* Port CSDM comes here */
5445 /* Port USDM comes here */
5446 /* Port XSDM comes here */
5447 bnx2x_init_block(bp, port ? TSEM_PORT1_START : TSEM_PORT0_START,
5448 port ? TSEM_PORT1_END : TSEM_PORT0_END);
5449 bnx2x_init_block(bp, port ? USEM_PORT1_START : USEM_PORT0_START,
5450 port ? USEM_PORT1_END : USEM_PORT0_END);
5451 bnx2x_init_block(bp, port ? CSEM_PORT1_START : CSEM_PORT0_START,
5452 port ? CSEM_PORT1_END : CSEM_PORT0_END);
5453 bnx2x_init_block(bp, port ? XSEM_PORT1_START : XSEM_PORT0_START,
5454 port ? XSEM_PORT1_END : XSEM_PORT0_END);
5455 /* Port UPB comes here */
5456 /* Port XPB comes here */
5458 bnx2x_init_block(bp, port ? PBF_PORT1_START : PBF_PORT0_START,
5459 port ? PBF_PORT1_END : PBF_PORT0_END);
5461 /* configure PBF to work without PAUSE mtu 9000 */
5462 REG_WR(bp, PBF_REG_P0_PAUSE_ENABLE + port*4, 0);
5464 /* update threshold */
5465 REG_WR(bp, PBF_REG_P0_ARB_THRSH + port*4, (9040/16));
5466 /* update init credit */
5467 REG_WR(bp, PBF_REG_P0_INIT_CRD + port*4, (9040/16) + 553 - 22);
5470 REG_WR(bp, PBF_REG_INIT_P0 + port*4, 1);
5472 REG_WR(bp, PBF_REG_INIT_P0 + port*4, 0);
5475 /* tell the searcher where the T2 table is */
5476 REG_WR(bp, SRC_REG_COUNTFREE0 + func*4, 16*1024/64);
5478 wb_write[0] = U64_LO(bp->t2_mapping);
5479 wb_write[1] = U64_HI(bp->t2_mapping);
5480 REG_WR_DMAE(bp, SRC_REG_FIRSTFREE0 + func*4, wb_write, 2);
5481 wb_write[0] = U64_LO((u64)bp->t2_mapping + 16*1024 - 64);
5482 wb_write[1] = U64_HI((u64)bp->t2_mapping + 16*1024 - 64);
5483 REG_WR_DMAE(bp, SRC_REG_LASTFREE0 + func*4, wb_write, 2);
5485 REG_WR(bp, SRC_REG_NUMBER_HASH_BITS0 + func*4, 10);
5486 /* Port SRCH comes here */
5488 /* Port CDU comes here */
5489 /* Port CFC comes here */
5491 if (CHIP_IS_E1(bp)) {
5492 REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, 0);
5493 REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, 0);
5495 bnx2x_init_block(bp, port ? HC_PORT1_START : HC_PORT0_START,
5496 port ? HC_PORT1_END : HC_PORT0_END);
5498 bnx2x_init_block(bp, port ? MISC_AEU_PORT1_START :
5499 MISC_AEU_PORT0_START,
5500 port ? MISC_AEU_PORT1_END : MISC_AEU_PORT0_END);
5501 /* init aeu_mask_attn_func_0/1:
5502 * - SF mode: bits 3-7 are masked. only bits 0-2 are in use
5503 * - MF mode: bit 3 is masked. bits 0-2 are in use as in SF
5504 * bits 4-7 are used for "per vn group attention" */
5505 REG_WR(bp, MISC_REG_AEU_MASK_ATTN_FUNC_0 + port*4,
5506 (IS_E1HMF(bp) ? 0xF7 : 0x7));
5508 /* Port PXPCS comes here */
5509 /* Port EMAC0 comes here */
5510 /* Port EMAC1 comes here */
5511 /* Port DBU comes here */
5512 /* Port DBG comes here */
5513 bnx2x_init_block(bp, port ? NIG_PORT1_START : NIG_PORT0_START,
5514 port ? NIG_PORT1_END : NIG_PORT0_END);
5516 REG_WR(bp, NIG_REG_XGXS_SERDES0_MODE_SEL + port*4, 1);
5518 if (CHIP_IS_E1H(bp)) {
5520 struct cmng_struct_per_port m_cmng_port;
5523 /* 0x2 disable e1hov, 0x1 enable */
5524 REG_WR(bp, NIG_REG_LLH0_BRB1_DRV_MASK_MF + port*4,
5525 (IS_E1HMF(bp) ? 0x1 : 0x2));
5527 /* Init RATE SHAPING and FAIRNESS contexts.
5528 Initialize as if there is 10G link. */
5529 wsum = bnx2x_calc_vn_wsum(bp);
5530 bnx2x_init_port_minmax(bp, (int)wsum, 10000, &m_cmng_port);
5532 for (vn = VN_0; vn < E1HVN_MAX; vn++)
5533 bnx2x_init_vn_minmax(bp, 2*vn + port,
5534 wsum, 10000, &m_cmng_port);
5537 /* Port MCP comes here */
5538 /* Port DMAE comes here */
5540 switch (bp->common.board & SHARED_HW_CFG_BOARD_TYPE_MASK) {
5541 case SHARED_HW_CFG_BOARD_TYPE_BCM957710A1022G:
5542 /* add SPIO 5 to group 0 */
5543 val = REG_RD(bp, MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0);
5544 val |= AEU_INPUTS_ATTN_BITS_SPIO5;
5545 REG_WR(bp, MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0, val);
5552 bnx2x__link_reset(bp);
5557 #define ILT_PER_FUNC (768/2)
5558 #define FUNC_ILT_BASE(func) (func * ILT_PER_FUNC)
5559 /* the phys address is shifted right 12 bits and has an added
5560 1=valid bit added to the 53rd bit
5561 then since this is a wide register(TM)
5562 we split it into two 32 bit writes
5564 #define ONCHIP_ADDR1(x) ((u32)(((u64)x >> 12) & 0xFFFFFFFF))
5565 #define ONCHIP_ADDR2(x) ((u32)((1 << 20) | ((u64)x >> 44)))
5566 #define PXP_ONE_ILT(x) (((x) << 10) | x)
5567 #define PXP_ILT_RANGE(f, l) (((l) << 10) | f)
5569 #define CNIC_ILT_LINES 0
5571 static void bnx2x_ilt_wr(struct bnx2x *bp, u32 index, dma_addr_t addr)
5575 if (CHIP_IS_E1H(bp))
5576 reg = PXP2_REG_RQ_ONCHIP_AT_B0 + index*8;
5578 reg = PXP2_REG_RQ_ONCHIP_AT + index*8;
5580 bnx2x_wb_wr(bp, reg, ONCHIP_ADDR1(addr), ONCHIP_ADDR2(addr));
5583 static int bnx2x_init_func(struct bnx2x *bp)
5585 int port = BP_PORT(bp);
5586 int func = BP_FUNC(bp);
5589 DP(BNX2X_MSG_MCP, "starting func init func %x\n", func);
5591 i = FUNC_ILT_BASE(func);
5593 bnx2x_ilt_wr(bp, i, bnx2x_sp_mapping(bp, context));
5594 if (CHIP_IS_E1H(bp)) {
5595 REG_WR(bp, PXP2_REG_RQ_CDU_FIRST_ILT, i);
5596 REG_WR(bp, PXP2_REG_RQ_CDU_LAST_ILT, i + CNIC_ILT_LINES);
5598 REG_WR(bp, PXP2_REG_PSWRQ_CDU0_L2P + func*4,
5599 PXP_ILT_RANGE(i, i + CNIC_ILT_LINES));
5602 if (CHIP_IS_E1H(bp)) {
5603 for (i = 0; i < 9; i++)
5604 bnx2x_init_block(bp,
5605 cm_start[func][i], cm_end[func][i]);
5607 REG_WR(bp, NIG_REG_LLH0_FUNC_EN + port*8, 1);
5608 REG_WR(bp, NIG_REG_LLH0_FUNC_VLAN_ID + port*8, bp->e1hov);
5611 /* HC init per function */
5612 if (CHIP_IS_E1H(bp)) {
5613 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_12 + func*4, 0);
5615 REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, 0);
5616 REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, 0);
5618 bnx2x_init_block(bp, hc_limits[func][0], hc_limits[func][1]);
5620 if (CHIP_IS_E1H(bp))
5621 REG_WR(bp, HC_REG_FUNC_NUM_P0 + port*4, func);
5623 /* Reset PCIE errors for debug */
5624 REG_WR(bp, 0x2114, 0xffffffff);
5625 REG_WR(bp, 0x2120, 0xffffffff);
5630 static int bnx2x_init_hw(struct bnx2x *bp, u32 load_code)
5634 DP(BNX2X_MSG_MCP, "function %d load_code %x\n",
5635 BP_FUNC(bp), load_code);
5638 mutex_init(&bp->dmae_mutex);
5639 bnx2x_gunzip_init(bp);
5641 switch (load_code) {
5642 case FW_MSG_CODE_DRV_LOAD_COMMON:
5643 rc = bnx2x_init_common(bp);
5648 case FW_MSG_CODE_DRV_LOAD_PORT:
5650 rc = bnx2x_init_port(bp);
5655 case FW_MSG_CODE_DRV_LOAD_FUNCTION:
5657 rc = bnx2x_init_func(bp);
5663 BNX2X_ERR("Unknown load_code (0x%x) from MCP\n", load_code);
5667 if (!BP_NOMCP(bp)) {
5668 int func = BP_FUNC(bp);
5670 bp->fw_drv_pulse_wr_seq =
5671 (SHMEM_RD(bp, func_mb[func].drv_pulse_mb) &
5672 DRV_PULSE_SEQ_MASK);
5673 bp->func_stx = SHMEM_RD(bp, func_mb[func].fw_mb_param);
5674 DP(BNX2X_MSG_MCP, "drv_pulse 0x%x func_stx 0x%x\n",
5675 bp->fw_drv_pulse_wr_seq, bp->func_stx);
5679 /* this needs to be done before gunzip end */
5680 bnx2x_zero_def_sb(bp);
5681 for_each_queue(bp, i)
5682 bnx2x_zero_sb(bp, BP_L_ID(bp) + i);
5685 bnx2x_gunzip_end(bp);
5690 /* send the MCP a request, block until there is a reply */
5691 static u32 bnx2x_fw_command(struct bnx2x *bp, u32 command)
5693 int func = BP_FUNC(bp);
5694 u32 seq = ++bp->fw_seq;
5697 u8 delay = CHIP_REV_IS_SLOW(bp) ? 100 : 10;
5699 SHMEM_WR(bp, func_mb[func].drv_mb_header, (command | seq));
5700 DP(BNX2X_MSG_MCP, "wrote command (%x) to FW MB\n", (command | seq));
5703 /* let the FW do it's magic ... */
5706 rc = SHMEM_RD(bp, func_mb[func].fw_mb_header);
5708 /* Give the FW up to 2 second (200*10ms) */
5709 } while ((seq != (rc & FW_MSG_SEQ_NUMBER_MASK)) && (cnt++ < 200));
5711 DP(BNX2X_MSG_MCP, "[after %d ms] read (%x) seq is (%x) from FW MB\n",
5712 cnt*delay, rc, seq);
5714 /* is this a reply to our command? */
5715 if (seq == (rc & FW_MSG_SEQ_NUMBER_MASK)) {
5716 rc &= FW_MSG_CODE_MASK;
5720 BNX2X_ERR("FW failed to respond!\n");
5728 static void bnx2x_free_mem(struct bnx2x *bp)
5731 #define BNX2X_PCI_FREE(x, y, size) \
5734 pci_free_consistent(bp->pdev, size, x, y); \
5740 #define BNX2X_FREE(x) \
5751 for_each_queue(bp, i) {
5754 BNX2X_PCI_FREE(bnx2x_fp(bp, i, status_blk),
5755 bnx2x_fp(bp, i, status_blk_mapping),
5756 sizeof(struct host_status_block) +
5757 sizeof(struct eth_tx_db_data));
5759 /* fast path rings: tx_buf tx_desc rx_buf rx_desc rx_comp */
5760 BNX2X_FREE(bnx2x_fp(bp, i, tx_buf_ring));
5761 BNX2X_PCI_FREE(bnx2x_fp(bp, i, tx_desc_ring),
5762 bnx2x_fp(bp, i, tx_desc_mapping),
5763 sizeof(struct eth_tx_bd) * NUM_TX_BD);
5765 BNX2X_FREE(bnx2x_fp(bp, i, rx_buf_ring));
5766 BNX2X_PCI_FREE(bnx2x_fp(bp, i, rx_desc_ring),
5767 bnx2x_fp(bp, i, rx_desc_mapping),
5768 sizeof(struct eth_rx_bd) * NUM_RX_BD);
5770 BNX2X_PCI_FREE(bnx2x_fp(bp, i, rx_comp_ring),
5771 bnx2x_fp(bp, i, rx_comp_mapping),
5772 sizeof(struct eth_fast_path_rx_cqe) *
5776 BNX2X_FREE(bnx2x_fp(bp, i, rx_page_ring));
5777 BNX2X_PCI_FREE(bnx2x_fp(bp, i, rx_sge_ring),
5778 bnx2x_fp(bp, i, rx_sge_mapping),
5779 BCM_PAGE_SIZE * NUM_RX_SGE_PAGES);
5781 /* end of fastpath */
5783 BNX2X_PCI_FREE(bp->def_status_blk, bp->def_status_blk_mapping,
5784 sizeof(struct host_def_status_block));
5786 BNX2X_PCI_FREE(bp->slowpath, bp->slowpath_mapping,
5787 sizeof(struct bnx2x_slowpath));
5790 BNX2X_PCI_FREE(bp->t1, bp->t1_mapping, 64*1024);
5791 BNX2X_PCI_FREE(bp->t2, bp->t2_mapping, 16*1024);
5792 BNX2X_PCI_FREE(bp->timers, bp->timers_mapping, 8*1024);
5793 BNX2X_PCI_FREE(bp->qm, bp->qm_mapping, 128*1024);
5795 BNX2X_PCI_FREE(bp->spq, bp->spq_mapping, BCM_PAGE_SIZE);
5797 #undef BNX2X_PCI_FREE
5801 static int bnx2x_alloc_mem(struct bnx2x *bp)
5804 #define BNX2X_PCI_ALLOC(x, y, size) \
5806 x = pci_alloc_consistent(bp->pdev, size, y); \
5808 goto alloc_mem_err; \
5809 memset(x, 0, size); \
5812 #define BNX2X_ALLOC(x, size) \
5814 x = vmalloc(size); \
5816 goto alloc_mem_err; \
5817 memset(x, 0, size); \
5823 for_each_queue(bp, i) {
5824 bnx2x_fp(bp, i, bp) = bp;
5827 BNX2X_PCI_ALLOC(bnx2x_fp(bp, i, status_blk),
5828 &bnx2x_fp(bp, i, status_blk_mapping),
5829 sizeof(struct host_status_block) +
5830 sizeof(struct eth_tx_db_data));
5832 bnx2x_fp(bp, i, hw_tx_prods) =
5833 (void *)(bnx2x_fp(bp, i, status_blk) + 1);
5835 bnx2x_fp(bp, i, tx_prods_mapping) =
5836 bnx2x_fp(bp, i, status_blk_mapping) +
5837 sizeof(struct host_status_block);
5839 /* fast path rings: tx_buf tx_desc rx_buf rx_desc rx_comp */
5840 BNX2X_ALLOC(bnx2x_fp(bp, i, tx_buf_ring),
5841 sizeof(struct sw_tx_bd) * NUM_TX_BD);
5842 BNX2X_PCI_ALLOC(bnx2x_fp(bp, i, tx_desc_ring),
5843 &bnx2x_fp(bp, i, tx_desc_mapping),
5844 sizeof(struct eth_tx_bd) * NUM_TX_BD);
5846 BNX2X_ALLOC(bnx2x_fp(bp, i, rx_buf_ring),
5847 sizeof(struct sw_rx_bd) * NUM_RX_BD);
5848 BNX2X_PCI_ALLOC(bnx2x_fp(bp, i, rx_desc_ring),
5849 &bnx2x_fp(bp, i, rx_desc_mapping),
5850 sizeof(struct eth_rx_bd) * NUM_RX_BD);
5852 BNX2X_PCI_ALLOC(bnx2x_fp(bp, i, rx_comp_ring),
5853 &bnx2x_fp(bp, i, rx_comp_mapping),
5854 sizeof(struct eth_fast_path_rx_cqe) *
5858 BNX2X_ALLOC(bnx2x_fp(bp, i, rx_page_ring),
5859 sizeof(struct sw_rx_page) * NUM_RX_SGE);
5860 BNX2X_PCI_ALLOC(bnx2x_fp(bp, i, rx_sge_ring),
5861 &bnx2x_fp(bp, i, rx_sge_mapping),
5862 BCM_PAGE_SIZE * NUM_RX_SGE_PAGES);
5864 /* end of fastpath */
5866 BNX2X_PCI_ALLOC(bp->def_status_blk, &bp->def_status_blk_mapping,
5867 sizeof(struct host_def_status_block));
5869 BNX2X_PCI_ALLOC(bp->slowpath, &bp->slowpath_mapping,
5870 sizeof(struct bnx2x_slowpath));
5873 BNX2X_PCI_ALLOC(bp->t1, &bp->t1_mapping, 64*1024);
5876 for (i = 0; i < 64*1024; i += 64) {
5877 *(u64 *)((char *)bp->t1 + i + 56) = 0x0UL;
5878 *(u64 *)((char *)bp->t1 + i + 3) = 0x0UL;
5881 /* allocate searcher T2 table
5882 we allocate 1/4 of alloc num for T2
5883 (which is not entered into the ILT) */
5884 BNX2X_PCI_ALLOC(bp->t2, &bp->t2_mapping, 16*1024);
5887 for (i = 0; i < 16*1024; i += 64)
5888 * (u64 *)((char *)bp->t2 + i + 56) = bp->t2_mapping + i + 64;
5890 /* now fixup the last line in the block to point to the next block */
5891 *(u64 *)((char *)bp->t2 + 1024*16-8) = bp->t2_mapping;
5893 /* Timer block array (MAX_CONN*8) phys uncached for now 1024 conns */
5894 BNX2X_PCI_ALLOC(bp->timers, &bp->timers_mapping, 8*1024);
5896 /* QM queues (128*MAX_CONN) */
5897 BNX2X_PCI_ALLOC(bp->qm, &bp->qm_mapping, 128*1024);
5900 /* Slow path ring */
5901 BNX2X_PCI_ALLOC(bp->spq, &bp->spq_mapping, BCM_PAGE_SIZE);
5909 #undef BNX2X_PCI_ALLOC
5913 static void bnx2x_free_tx_skbs(struct bnx2x *bp)
5917 for_each_queue(bp, i) {
5918 struct bnx2x_fastpath *fp = &bp->fp[i];
5920 u16 bd_cons = fp->tx_bd_cons;
5921 u16 sw_prod = fp->tx_pkt_prod;
5922 u16 sw_cons = fp->tx_pkt_cons;
5924 while (sw_cons != sw_prod) {
5925 bd_cons = bnx2x_free_tx_pkt(bp, fp, TX_BD(sw_cons));
5931 static void bnx2x_free_rx_skbs(struct bnx2x *bp)
5935 for_each_queue(bp, j) {
5936 struct bnx2x_fastpath *fp = &bp->fp[j];
5938 for (i = 0; i < NUM_RX_BD; i++) {
5939 struct sw_rx_bd *rx_buf = &fp->rx_buf_ring[i];
5940 struct sk_buff *skb = rx_buf->skb;
5945 pci_unmap_single(bp->pdev,
5946 pci_unmap_addr(rx_buf, mapping),
5947 bp->rx_buf_use_size,
5948 PCI_DMA_FROMDEVICE);
5953 if (!fp->disable_tpa)
5954 bnx2x_free_tpa_pool(bp, fp, CHIP_IS_E1(bp) ?
5955 ETH_MAX_AGGREGATION_QUEUES_E1 :
5956 ETH_MAX_AGGREGATION_QUEUES_E1H);
5960 static void bnx2x_free_skbs(struct bnx2x *bp)
5962 bnx2x_free_tx_skbs(bp);
5963 bnx2x_free_rx_skbs(bp);
5966 static void bnx2x_free_msix_irqs(struct bnx2x *bp)
5970 free_irq(bp->msix_table[0].vector, bp->dev);
5971 DP(NETIF_MSG_IFDOWN, "released sp irq (%d)\n",
5972 bp->msix_table[0].vector);
5974 for_each_queue(bp, i) {
5975 DP(NETIF_MSG_IFDOWN, "about to release fp #%d->%d irq "
5976 "state %x\n", i, bp->msix_table[i + offset].vector,
5977 bnx2x_fp(bp, i, state));
5979 if (bnx2x_fp(bp, i, state) != BNX2X_FP_STATE_CLOSED)
5980 BNX2X_ERR("IRQ of fp #%d being freed while "
5981 "state != closed\n", i);
5983 free_irq(bp->msix_table[i + offset].vector, &bp->fp[i]);
5987 static void bnx2x_free_irq(struct bnx2x *bp)
5989 if (bp->flags & USING_MSIX_FLAG) {
5990 bnx2x_free_msix_irqs(bp);
5991 pci_disable_msix(bp->pdev);
5992 bp->flags &= ~USING_MSIX_FLAG;
5995 free_irq(bp->pdev->irq, bp->dev);
5998 static int bnx2x_enable_msix(struct bnx2x *bp)
6002 bp->msix_table[0].entry = 0;
6004 DP(NETIF_MSG_IFUP, "msix_table[0].entry = 0 (slowpath)\n");
6006 for_each_queue(bp, i) {
6007 int igu_vec = offset + i + BP_L_ID(bp);
6009 bp->msix_table[i + offset].entry = igu_vec;
6010 DP(NETIF_MSG_IFUP, "msix_table[%d].entry = %d "
6011 "(fastpath #%u)\n", i + offset, igu_vec, i);
6014 rc = pci_enable_msix(bp->pdev, &bp->msix_table[0],
6015 bp->num_queues + offset);
6017 DP(NETIF_MSG_IFUP, "MSI-X is not attainable\n");
6020 bp->flags |= USING_MSIX_FLAG;
6025 static int bnx2x_req_msix_irqs(struct bnx2x *bp)
6027 int i, rc, offset = 1;
6029 rc = request_irq(bp->msix_table[0].vector, bnx2x_msix_sp_int, 0,
6030 bp->dev->name, bp->dev);
6032 BNX2X_ERR("request sp irq failed\n");
6036 for_each_queue(bp, i) {
6037 rc = request_irq(bp->msix_table[i + offset].vector,
6038 bnx2x_msix_fp_int, 0,
6039 bp->dev->name, &bp->fp[i]);
6041 BNX2X_ERR("request fp #%d irq failed rc %d\n",
6043 bnx2x_free_msix_irqs(bp);
6047 bnx2x_fp(bp, i, state) = BNX2X_FP_STATE_IRQ;
6053 static int bnx2x_req_irq(struct bnx2x *bp)
6057 rc = request_irq(bp->pdev->irq, bnx2x_interrupt, IRQF_SHARED,
6058 bp->dev->name, bp->dev);
6060 bnx2x_fp(bp, 0, state) = BNX2X_FP_STATE_IRQ;
6066 * Init service functions
6069 static void bnx2x_set_mac_addr_e1(struct bnx2x *bp)
6071 struct mac_configuration_cmd *config = bnx2x_sp(bp, mac_config);
6072 int port = BP_PORT(bp);
6075 * unicasts 0-31:port0 32-63:port1
6076 * multicast 64-127:port0 128-191:port1
6078 config->hdr.length_6b = 2;
6079 config->hdr.offset = port ? 31 : 0;
6080 config->hdr.client_id = BP_CL_ID(bp);
6081 config->hdr.reserved1 = 0;
6084 config->config_table[0].cam_entry.msb_mac_addr =
6085 swab16(*(u16 *)&bp->dev->dev_addr[0]);
6086 config->config_table[0].cam_entry.middle_mac_addr =
6087 swab16(*(u16 *)&bp->dev->dev_addr[2]);
6088 config->config_table[0].cam_entry.lsb_mac_addr =
6089 swab16(*(u16 *)&bp->dev->dev_addr[4]);
6090 config->config_table[0].cam_entry.flags = cpu_to_le16(port);
6091 config->config_table[0].target_table_entry.flags = 0;
6092 config->config_table[0].target_table_entry.client_id = 0;
6093 config->config_table[0].target_table_entry.vlan_id = 0;
6095 DP(NETIF_MSG_IFUP, "setting MAC (%04x:%04x:%04x)\n",
6096 config->config_table[0].cam_entry.msb_mac_addr,
6097 config->config_table[0].cam_entry.middle_mac_addr,
6098 config->config_table[0].cam_entry.lsb_mac_addr);
6101 config->config_table[1].cam_entry.msb_mac_addr = 0xffff;
6102 config->config_table[1].cam_entry.middle_mac_addr = 0xffff;
6103 config->config_table[1].cam_entry.lsb_mac_addr = 0xffff;
6104 config->config_table[1].cam_entry.flags = cpu_to_le16(port);
6105 config->config_table[1].target_table_entry.flags =
6106 TSTORM_CAM_TARGET_TABLE_ENTRY_BROADCAST;
6107 config->config_table[1].target_table_entry.client_id = 0;
6108 config->config_table[1].target_table_entry.vlan_id = 0;
6110 bnx2x_sp_post(bp, RAMROD_CMD_ID_ETH_SET_MAC, 0,
6111 U64_HI(bnx2x_sp_mapping(bp, mac_config)),
6112 U64_LO(bnx2x_sp_mapping(bp, mac_config)), 0);
6115 static void bnx2x_set_mac_addr_e1h(struct bnx2x *bp)
6117 struct mac_configuration_cmd_e1h *config =
6118 (struct mac_configuration_cmd_e1h *)bnx2x_sp(bp, mac_config);
6120 if (bp->state != BNX2X_STATE_OPEN) {
6121 DP(NETIF_MSG_IFUP, "state is %x, returning\n", bp->state);
6125 /* CAM allocation for E1H
6126 * unicasts: by func number
6127 * multicast: 20+FUNC*20, 20 each
6129 config->hdr.length_6b = 1;
6130 config->hdr.offset = BP_FUNC(bp);
6131 config->hdr.client_id = BP_CL_ID(bp);
6132 config->hdr.reserved1 = 0;
6135 config->config_table[0].msb_mac_addr =
6136 swab16(*(u16 *)&bp->dev->dev_addr[0]);
6137 config->config_table[0].middle_mac_addr =
6138 swab16(*(u16 *)&bp->dev->dev_addr[2]);
6139 config->config_table[0].lsb_mac_addr =
6140 swab16(*(u16 *)&bp->dev->dev_addr[4]);
6141 config->config_table[0].client_id = BP_L_ID(bp);
6142 config->config_table[0].vlan_id = 0;
6143 config->config_table[0].e1hov_id = cpu_to_le16(bp->e1hov);
6144 config->config_table[0].flags = BP_PORT(bp);
6146 DP(NETIF_MSG_IFUP, "setting MAC (%04x:%04x:%04x) E1HOV %d CLID %d\n",
6147 config->config_table[0].msb_mac_addr,
6148 config->config_table[0].middle_mac_addr,
6149 config->config_table[0].lsb_mac_addr, bp->e1hov, BP_L_ID(bp));
6151 bnx2x_sp_post(bp, RAMROD_CMD_ID_ETH_SET_MAC, 0,
6152 U64_HI(bnx2x_sp_mapping(bp, mac_config)),
6153 U64_LO(bnx2x_sp_mapping(bp, mac_config)), 0);
6156 static int bnx2x_wait_ramrod(struct bnx2x *bp, int state, int idx,
6157 int *state_p, int poll)
6159 /* can take a while if any port is running */
6162 DP(NETIF_MSG_IFUP, "%s for state to become %x on IDX [%d]\n",
6163 poll ? "polling" : "waiting", state, idx);
6168 bnx2x_rx_int(bp->fp, 10);
6169 /* if index is different from 0
6170 * the reply for some commands will
6171 * be on the none default queue
6174 bnx2x_rx_int(&bp->fp[idx], 10);
6176 mb(); /* state is changed by bnx2x_sp_event() */
6178 if (*state_p == state)
6185 BNX2X_ERR("timeout %s for state %x on IDX [%d]\n",
6186 poll ? "polling" : "waiting", state, idx);
6187 #ifdef BNX2X_STOP_ON_ERROR
6194 static int bnx2x_setup_leading(struct bnx2x *bp)
6198 /* reset IGU state */
6199 bnx2x_ack_sb(bp, bp->fp[0].sb_id, CSTORM_ID, 0, IGU_INT_ENABLE, 0);
6202 bnx2x_sp_post(bp, RAMROD_CMD_ID_ETH_PORT_SETUP, 0, 0, 0, 0);
6204 /* Wait for completion */
6205 rc = bnx2x_wait_ramrod(bp, BNX2X_STATE_OPEN, 0, &(bp->state), 0);
6210 static int bnx2x_setup_multi(struct bnx2x *bp, int index)
6212 /* reset IGU state */
6213 bnx2x_ack_sb(bp, bp->fp[index].sb_id, CSTORM_ID, 0, IGU_INT_ENABLE, 0);
6216 bp->fp[index].state = BNX2X_FP_STATE_OPENING;
6217 bnx2x_sp_post(bp, RAMROD_CMD_ID_ETH_CLIENT_SETUP, index, 0, index, 0);
6219 /* Wait for completion */
6220 return bnx2x_wait_ramrod(bp, BNX2X_FP_STATE_OPEN, index,
6221 &(bp->fp[index].state), 0);
6224 static int bnx2x_poll(struct napi_struct *napi, int budget);
6225 static void bnx2x_set_rx_mode(struct net_device *dev);
6227 /* must be called with rtnl_lock */
6228 static int bnx2x_nic_load(struct bnx2x *bp, int load_mode)
6233 #ifdef BNX2X_STOP_ON_ERROR
6234 if (unlikely(bp->panic))
6238 bp->state = BNX2X_STATE_OPENING_WAIT4_LOAD;
6240 /* Send LOAD_REQUEST command to MCP
6241 Returns the type of LOAD command:
6242 if it is the first port to be initialized
6243 common blocks should be initialized, otherwise - not
6245 if (!BP_NOMCP(bp)) {
6246 load_code = bnx2x_fw_command(bp, DRV_MSG_CODE_LOAD_REQ);
6248 BNX2X_ERR("MCP response failure, aborting\n");
6251 if (load_code == FW_MSG_CODE_DRV_LOAD_REFUSED)
6252 return -EBUSY; /* other port in diagnostic mode */
6255 int port = BP_PORT(bp);
6257 DP(NETIF_MSG_IFUP, "NO MCP load counts before us %d, %d, %d\n",
6258 load_count[0], load_count[1], load_count[2]);
6260 load_count[1 + port]++;
6261 DP(NETIF_MSG_IFUP, "NO MCP new load counts %d, %d, %d\n",
6262 load_count[0], load_count[1], load_count[2]);
6263 if (load_count[0] == 1)
6264 load_code = FW_MSG_CODE_DRV_LOAD_COMMON;
6265 else if (load_count[1 + port] == 1)
6266 load_code = FW_MSG_CODE_DRV_LOAD_PORT;
6268 load_code = FW_MSG_CODE_DRV_LOAD_FUNCTION;
6271 if ((load_code == FW_MSG_CODE_DRV_LOAD_COMMON) ||
6272 (load_code == FW_MSG_CODE_DRV_LOAD_PORT))
6276 DP(NETIF_MSG_LINK, "pmf %d\n", bp->port.pmf);
6278 /* if we can't use MSI-X we only need one fp,
6279 * so try to enable MSI-X with the requested number of fp's
6280 * and fallback to inta with one fp
6286 if ((use_multi > 1) && (use_multi <= BP_MAX_QUEUES(bp)))
6287 /* user requested number */
6288 bp->num_queues = use_multi;
6291 bp->num_queues = min_t(u32, num_online_cpus(),
6296 if (bnx2x_enable_msix(bp)) {
6297 /* failed to enable MSI-X */
6300 BNX2X_ERR("Multi requested but failed"
6301 " to enable MSI-X\n");
6305 "set number of queues to %d\n", bp->num_queues);
6307 if (bnx2x_alloc_mem(bp))
6310 for_each_queue(bp, i)
6311 bnx2x_fp(bp, i, disable_tpa) =
6312 ((bp->flags & TPA_ENABLE_FLAG) == 0);
6314 if (bp->flags & USING_MSIX_FLAG) {
6315 rc = bnx2x_req_msix_irqs(bp);
6317 pci_disable_msix(bp->pdev);
6322 rc = bnx2x_req_irq(bp);
6324 BNX2X_ERR("IRQ request failed, aborting\n");
6329 for_each_queue(bp, i)
6330 netif_napi_add(bp->dev, &bnx2x_fp(bp, i, napi),
6334 rc = bnx2x_init_hw(bp, load_code);
6336 BNX2X_ERR("HW init failed, aborting\n");
6340 /* Setup NIC internals and enable interrupts */
6341 bnx2x_nic_init(bp, load_code);
6343 /* Send LOAD_DONE command to MCP */
6344 if (!BP_NOMCP(bp)) {
6345 load_code = bnx2x_fw_command(bp, DRV_MSG_CODE_LOAD_DONE);
6347 BNX2X_ERR("MCP response failure, aborting\n");
6349 goto load_int_disable;
6353 bnx2x_stats_init(bp);
6355 bp->state = BNX2X_STATE_OPENING_WAIT4_PORT;
6357 /* Enable Rx interrupt handling before sending the ramrod
6358 as it's completed on Rx FP queue */
6359 for_each_queue(bp, i)
6360 napi_enable(&bnx2x_fp(bp, i, napi));
6362 /* Enable interrupt handling */
6363 atomic_set(&bp->intr_sem, 0);
6365 rc = bnx2x_setup_leading(bp);
6367 BNX2X_ERR("Setup leading failed!\n");
6368 goto load_stop_netif;
6371 if (CHIP_IS_E1H(bp))
6372 if (bp->mf_config & FUNC_MF_CFG_FUNC_DISABLED) {
6373 BNX2X_ERR("!!! mf_cfg function disabled\n");
6374 bp->state = BNX2X_STATE_DISABLED;
6377 if (bp->state == BNX2X_STATE_OPEN)
6378 for_each_nondefault_queue(bp, i) {
6379 rc = bnx2x_setup_multi(bp, i);
6381 goto load_stop_netif;
6385 bnx2x_set_mac_addr_e1(bp);
6387 bnx2x_set_mac_addr_e1h(bp);
6390 bnx2x_initial_phy_init(bp);
6392 /* Start fast path */
6393 switch (load_mode) {
6395 /* Tx queue should be only reenabled */
6396 netif_wake_queue(bp->dev);
6397 bnx2x_set_rx_mode(bp->dev);
6401 netif_start_queue(bp->dev);
6402 bnx2x_set_rx_mode(bp->dev);
6403 if (bp->flags & USING_MSIX_FLAG)
6404 printk(KERN_INFO PFX "%s: using MSI-X\n",
6409 bnx2x_set_rx_mode(bp->dev);
6410 bp->state = BNX2X_STATE_DIAG;
6418 bnx2x__link_status_update(bp);
6420 /* start the timer */
6421 mod_timer(&bp->timer, jiffies + bp->current_interval);
6427 for_each_queue(bp, i)
6428 napi_disable(&bnx2x_fp(bp, i, napi));
6431 bnx2x_int_disable_sync(bp);
6436 /* Free SKBs, SGEs, TPA pool and driver internals */
6437 bnx2x_free_skbs(bp);
6438 for_each_queue(bp, i)
6439 bnx2x_free_rx_sge_range(bp, bp->fp + i,
6440 RX_SGE_CNT*NUM_RX_SGE_PAGES);
6444 /* TBD we really need to reset the chip
6445 if we want to recover from this */
6449 static int bnx2x_stop_multi(struct bnx2x *bp, int index)
6453 /* halt the connection */
6454 bp->fp[index].state = BNX2X_FP_STATE_HALTING;
6455 bnx2x_sp_post(bp, RAMROD_CMD_ID_ETH_HALT, index, 0, 0, 0);
6457 /* Wait for completion */
6458 rc = bnx2x_wait_ramrod(bp, BNX2X_FP_STATE_HALTED, index,
6459 &(bp->fp[index].state), 1);
6460 if (rc) /* timeout */
6463 /* delete cfc entry */
6464 bnx2x_sp_post(bp, RAMROD_CMD_ID_ETH_CFC_DEL, index, 0, 0, 1);
6466 /* Wait for completion */
6467 rc = bnx2x_wait_ramrod(bp, BNX2X_FP_STATE_CLOSED, index,
6468 &(bp->fp[index].state), 1);
6472 static int bnx2x_stop_leading(struct bnx2x *bp)
6474 u16 dsb_sp_prod_idx;
6475 /* if the other port is handling traffic,
6476 this can take a lot of time */
6482 /* Send HALT ramrod */
6483 bp->fp[0].state = BNX2X_FP_STATE_HALTING;
6484 bnx2x_sp_post(bp, RAMROD_CMD_ID_ETH_HALT, 0, 0, BP_CL_ID(bp), 0);
6486 /* Wait for completion */
6487 rc = bnx2x_wait_ramrod(bp, BNX2X_FP_STATE_HALTED, 0,
6488 &(bp->fp[0].state), 1);
6489 if (rc) /* timeout */
6492 dsb_sp_prod_idx = *bp->dsb_sp_prod;
6494 /* Send PORT_DELETE ramrod */
6495 bnx2x_sp_post(bp, RAMROD_CMD_ID_ETH_PORT_DEL, 0, 0, 0, 1);
6497 /* Wait for completion to arrive on default status block
6498 we are going to reset the chip anyway
6499 so there is not much to do if this times out
6501 while (dsb_sp_prod_idx == *bp->dsb_sp_prod) {
6504 DP(NETIF_MSG_IFDOWN, "timeout waiting for port del "
6505 "dsb_sp_prod 0x%x != dsb_sp_prod_idx 0x%x\n",
6506 *bp->dsb_sp_prod, dsb_sp_prod_idx);
6507 #ifdef BNX2X_STOP_ON_ERROR
6517 bp->state = BNX2X_STATE_CLOSING_WAIT4_UNLOAD;
6518 bp->fp[0].state = BNX2X_FP_STATE_CLOSED;
6523 static void bnx2x_reset_func(struct bnx2x *bp)
6525 int port = BP_PORT(bp);
6526 int func = BP_FUNC(bp);
6530 REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, 0);
6531 REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, 0);
6533 REG_WR(bp, HC_REG_CONFIG_0 + port*4, 0x1000);
6536 base = FUNC_ILT_BASE(func);
6537 for (i = base; i < base + ILT_PER_FUNC; i++)
6538 bnx2x_ilt_wr(bp, i, 0);
6541 static void bnx2x_reset_port(struct bnx2x *bp)
6543 int port = BP_PORT(bp);
6546 REG_WR(bp, NIG_REG_MASK_INTERRUPT_PORT0 + port*4, 0);
6548 /* Do not rcv packets to BRB */
6549 REG_WR(bp, NIG_REG_LLH0_BRB1_DRV_MASK + port*4, 0x0);
6550 /* Do not direct rcv packets that are not for MCP to the BRB */
6551 REG_WR(bp, (port ? NIG_REG_LLH1_BRB1_NOT_MCP :
6552 NIG_REG_LLH0_BRB1_NOT_MCP), 0x0);
6555 REG_WR(bp, MISC_REG_AEU_MASK_ATTN_FUNC_0 + port*4, 0);
6558 /* Check for BRB port occupancy */
6559 val = REG_RD(bp, BRB1_REG_PORT_NUM_OCC_BLOCKS_0 + port*4);
6561 DP(NETIF_MSG_IFDOWN,
6562 "BRB1 is not empty %d blooks are occupied\n", val);
6564 /* TODO: Close Doorbell port? */
6567 static void bnx2x_reset_common(struct bnx2x *bp)
6570 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR,
6572 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR, 0x1403);
6575 static void bnx2x_reset_chip(struct bnx2x *bp, u32 reset_code)
6577 DP(BNX2X_MSG_MCP, "function %d reset_code %x\n",
6578 BP_FUNC(bp), reset_code);
6580 switch (reset_code) {
6581 case FW_MSG_CODE_DRV_UNLOAD_COMMON:
6582 bnx2x_reset_port(bp);
6583 bnx2x_reset_func(bp);
6584 bnx2x_reset_common(bp);
6587 case FW_MSG_CODE_DRV_UNLOAD_PORT:
6588 bnx2x_reset_port(bp);
6589 bnx2x_reset_func(bp);
6592 case FW_MSG_CODE_DRV_UNLOAD_FUNCTION:
6593 bnx2x_reset_func(bp);
6597 BNX2X_ERR("Unknown reset_code (0x%x) from MCP\n", reset_code);
6602 /* msut be called with rtnl_lock */
6603 static int bnx2x_nic_unload(struct bnx2x *bp, int unload_mode)
6605 int port = BP_PORT(bp);
6609 bp->state = BNX2X_STATE_CLOSING_WAIT4_HALT;
6611 bp->rx_mode = BNX2X_RX_MODE_NONE;
6612 bnx2x_set_storm_rx_mode(bp);
6614 if (netif_running(bp->dev)) {
6615 netif_tx_disable(bp->dev);
6616 bp->dev->trans_start = jiffies; /* prevent tx timeout */
6619 del_timer_sync(&bp->timer);
6620 SHMEM_WR(bp, func_mb[BP_FUNC(bp)].drv_pulse_mb,
6621 (DRV_PULSE_ALWAYS_ALIVE | bp->fw_drv_pulse_wr_seq));
6622 bnx2x_stats_handle(bp, STATS_EVENT_STOP);
6624 /* Wait until tx fast path tasks complete */
6625 for_each_queue(bp, i) {
6626 struct bnx2x_fastpath *fp = &bp->fp[i];
6630 while (BNX2X_HAS_TX_WORK(fp)) {
6632 if (!netif_running(bp->dev))
6633 bnx2x_tx_int(fp, 1000);
6636 BNX2X_ERR("timeout waiting for queue[%d]\n",
6638 #ifdef BNX2X_STOP_ON_ERROR
6651 /* Give HW time to discard old tx messages */
6654 for_each_queue(bp, i)
6655 napi_disable(&bnx2x_fp(bp, i, napi));
6656 /* Disable interrupts after Tx and Rx are disabled on stack level */
6657 bnx2x_int_disable_sync(bp);
6662 if (unload_mode == UNLOAD_NORMAL)
6663 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS;
6665 else if (bp->flags & NO_WOL_FLAG) {
6666 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_MCP;
6667 if (CHIP_IS_E1H(bp))
6668 REG_WR(bp, MISC_REG_E1HMF_MODE, 0);
6670 } else if (bp->wol) {
6671 u32 emac_base = port ? GRCBASE_EMAC1 : GRCBASE_EMAC0;
6672 u8 *mac_addr = bp->dev->dev_addr;
6674 /* The mac address is written to entries 1-4 to
6675 preserve entry 0 which is used by the PMF */
6676 u8 entry = (BP_E1HVN(bp) + 1)*8;
6678 val = (mac_addr[0] << 8) | mac_addr[1];
6679 EMAC_WR(EMAC_REG_EMAC_MAC_MATCH + entry, val);
6681 val = (mac_addr[2] << 24) | (mac_addr[3] << 16) |
6682 (mac_addr[4] << 8) | mac_addr[5];
6683 EMAC_WR(EMAC_REG_EMAC_MAC_MATCH + entry + 4, val);
6685 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_EN;
6688 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS;
6690 if (CHIP_IS_E1H(bp))
6691 REG_WR(bp, NIG_REG_LLH0_FUNC_EN + port*8, 0);
6693 /* Close multi and leading connections
6694 Completions for ramrods are collected in a synchronous way */
6695 for_each_nondefault_queue(bp, i)
6696 if (bnx2x_stop_multi(bp, i))
6699 rc = bnx2x_stop_leading(bp);
6701 BNX2X_ERR("Stop leading failed!\n");
6702 #ifdef BNX2X_STOP_ON_ERROR
6711 reset_code = bnx2x_fw_command(bp, reset_code);
6713 DP(NETIF_MSG_IFDOWN, "NO MCP load counts %d, %d, %d\n",
6714 load_count[0], load_count[1], load_count[2]);
6716 load_count[1 + port]--;
6717 DP(NETIF_MSG_IFDOWN, "NO MCP new load counts %d, %d, %d\n",
6718 load_count[0], load_count[1], load_count[2]);
6719 if (load_count[0] == 0)
6720 reset_code = FW_MSG_CODE_DRV_UNLOAD_COMMON;
6721 else if (load_count[1 + port] == 0)
6722 reset_code = FW_MSG_CODE_DRV_UNLOAD_PORT;
6724 reset_code = FW_MSG_CODE_DRV_UNLOAD_FUNCTION;
6727 if ((reset_code == FW_MSG_CODE_DRV_UNLOAD_COMMON) ||
6728 (reset_code == FW_MSG_CODE_DRV_UNLOAD_PORT))
6729 bnx2x__link_reset(bp);
6731 /* Reset the chip */
6732 bnx2x_reset_chip(bp, reset_code);
6734 /* Report UNLOAD_DONE to MCP */
6736 bnx2x_fw_command(bp, DRV_MSG_CODE_UNLOAD_DONE);
6738 /* Free SKBs, SGEs, TPA pool and driver internals */
6739 bnx2x_free_skbs(bp);
6740 for_each_queue(bp, i)
6741 bnx2x_free_rx_sge_range(bp, bp->fp + i,
6742 RX_SGE_CNT*NUM_RX_SGE_PAGES);
6745 bp->state = BNX2X_STATE_CLOSED;
6747 netif_carrier_off(bp->dev);
6752 static void bnx2x_reset_task(struct work_struct *work)
6754 struct bnx2x *bp = container_of(work, struct bnx2x, reset_task);
6756 #ifdef BNX2X_STOP_ON_ERROR
6757 BNX2X_ERR("reset task called but STOP_ON_ERROR defined"
6758 " so reset not done to allow debug dump,\n"
6759 KERN_ERR " you will need to reboot when done\n");
6765 if (!netif_running(bp->dev))
6766 goto reset_task_exit;
6768 bnx2x_nic_unload(bp, UNLOAD_NORMAL);
6769 bnx2x_nic_load(bp, LOAD_NORMAL);
6775 /* end of nic load/unload */
6780 * Init service functions
6783 static void __devinit bnx2x_undi_unload(struct bnx2x *bp)
6787 /* Check if there is any driver already loaded */
6788 val = REG_RD(bp, MISC_REG_UNPREPARED);
6790 /* Check if it is the UNDI driver
6791 * UNDI driver initializes CID offset for normal bell to 0x7
6793 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_UNDI);
6794 val = REG_RD(bp, DORQ_REG_NORM_CID_OFST);
6796 u32 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS;
6798 int func = BP_FUNC(bp);
6802 BNX2X_DEV_INFO("UNDI is active! reset device\n");
6804 /* try unload UNDI on port 0 */
6807 (SHMEM_RD(bp, func_mb[bp->func].drv_mb_header) &
6808 DRV_MSG_SEQ_NUMBER_MASK);
6809 reset_code = bnx2x_fw_command(bp, reset_code);
6811 /* if UNDI is loaded on the other port */
6812 if (reset_code != FW_MSG_CODE_DRV_UNLOAD_COMMON) {
6814 /* send "DONE" for previous unload */
6815 bnx2x_fw_command(bp, DRV_MSG_CODE_UNLOAD_DONE);
6817 /* unload UNDI on port 1 */
6820 (SHMEM_RD(bp, func_mb[bp->func].drv_mb_header) &
6821 DRV_MSG_SEQ_NUMBER_MASK);
6822 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS;
6824 bnx2x_fw_command(bp, reset_code);
6827 REG_WR(bp, (BP_PORT(bp) ? HC_REG_CONFIG_1 :
6828 HC_REG_CONFIG_0), 0x1000);
6830 /* close input traffic and wait for it */
6831 /* Do not rcv packets to BRB */
6833 (BP_PORT(bp) ? NIG_REG_LLH1_BRB1_DRV_MASK :
6834 NIG_REG_LLH0_BRB1_DRV_MASK), 0x0);
6835 /* Do not direct rcv packets that are not for MCP to
6838 (BP_PORT(bp) ? NIG_REG_LLH1_BRB1_NOT_MCP :
6839 NIG_REG_LLH0_BRB1_NOT_MCP), 0x0);
6842 (BP_PORT(bp) ? MISC_REG_AEU_MASK_ATTN_FUNC_1 :
6843 MISC_REG_AEU_MASK_ATTN_FUNC_0), 0);
6846 /* save NIG port swap info */
6847 swap_val = REG_RD(bp, NIG_REG_PORT_SWAP);
6848 swap_en = REG_RD(bp, NIG_REG_STRAP_OVERRIDE);
6851 GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR,
6854 GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
6856 /* take the NIG out of reset and restore swap values */
6858 GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET,
6859 MISC_REGISTERS_RESET_REG_1_RST_NIG);
6860 REG_WR(bp, NIG_REG_PORT_SWAP, swap_val);
6861 REG_WR(bp, NIG_REG_STRAP_OVERRIDE, swap_en);
6863 /* send unload done to the MCP */
6864 bnx2x_fw_command(bp, DRV_MSG_CODE_UNLOAD_DONE);
6866 /* restore our func and fw_seq */
6869 (SHMEM_RD(bp, func_mb[bp->func].drv_mb_header) &
6870 DRV_MSG_SEQ_NUMBER_MASK);
6872 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_UNDI);
6876 static void __devinit bnx2x_get_common_hwinfo(struct bnx2x *bp)
6878 u32 val, val2, val3, val4, id;
6880 /* Get the chip revision id and number. */
6881 /* chip num:16-31, rev:12-15, metal:4-11, bond_id:0-3 */
6882 val = REG_RD(bp, MISC_REG_CHIP_NUM);
6883 id = ((val & 0xffff) << 16);
6884 val = REG_RD(bp, MISC_REG_CHIP_REV);
6885 id |= ((val & 0xf) << 12);
6886 val = REG_RD(bp, MISC_REG_CHIP_METAL);
6887 id |= ((val & 0xff) << 4);
6888 REG_RD(bp, MISC_REG_BOND_ID);
6890 bp->common.chip_id = id;
6891 bp->link_params.chip_id = bp->common.chip_id;
6892 BNX2X_DEV_INFO("chip ID is 0x%x\n", id);
6894 val = REG_RD(bp, MCP_REG_MCPR_NVM_CFG4);
6895 bp->common.flash_size = (NVRAM_1MB_SIZE <<
6896 (val & MCPR_NVM_CFG4_FLASH_SIZE));
6897 BNX2X_DEV_INFO("flash_size 0x%x (%d)\n",
6898 bp->common.flash_size, bp->common.flash_size);
6900 bp->common.shmem_base = REG_RD(bp, MISC_REG_SHARED_MEM_ADDR);
6901 bp->link_params.shmem_base = bp->common.shmem_base;
6902 BNX2X_DEV_INFO("shmem offset is 0x%x\n", bp->common.shmem_base);
6904 if (!bp->common.shmem_base ||
6905 (bp->common.shmem_base < 0xA0000) ||
6906 (bp->common.shmem_base >= 0xC0000)) {
6907 BNX2X_DEV_INFO("MCP not active\n");
6908 bp->flags |= NO_MCP_FLAG;
6912 val = SHMEM_RD(bp, validity_map[BP_PORT(bp)]);
6913 if ((val & (SHR_MEM_VALIDITY_DEV_INFO | SHR_MEM_VALIDITY_MB))
6914 != (SHR_MEM_VALIDITY_DEV_INFO | SHR_MEM_VALIDITY_MB))
6915 BNX2X_ERR("BAD MCP validity signature\n");
6917 bp->common.hw_config = SHMEM_RD(bp, dev_info.shared_hw_config.config);
6918 bp->common.board = SHMEM_RD(bp, dev_info.shared_hw_config.board);
6920 BNX2X_DEV_INFO("hw_config 0x%08x board 0x%08x\n",
6921 bp->common.hw_config, bp->common.board);
6923 bp->link_params.hw_led_mode = ((bp->common.hw_config &
6924 SHARED_HW_CFG_LED_MODE_MASK) >>
6925 SHARED_HW_CFG_LED_MODE_SHIFT);
6927 val = SHMEM_RD(bp, dev_info.bc_rev) >> 8;
6928 bp->common.bc_ver = val;
6929 BNX2X_DEV_INFO("bc_ver %X\n", val);
6930 if (val < BNX2X_BC_VER) {
6931 /* for now only warn
6932 * later we might need to enforce this */
6933 BNX2X_ERR("This driver needs bc_ver %X but found %X,"
6934 " please upgrade BC\n", BNX2X_BC_VER, val);
6936 BNX2X_DEV_INFO("%sWoL Capable\n",
6937 (bp->flags & NO_WOL_FLAG)? "Not " : "");
6939 val = SHMEM_RD(bp, dev_info.shared_hw_config.part_num);
6940 val2 = SHMEM_RD(bp, dev_info.shared_hw_config.part_num[4]);
6941 val3 = SHMEM_RD(bp, dev_info.shared_hw_config.part_num[8]);
6942 val4 = SHMEM_RD(bp, dev_info.shared_hw_config.part_num[12]);
6944 printk(KERN_INFO PFX "part number %X-%X-%X-%X\n",
6945 val, val2, val3, val4);
6948 static void __devinit bnx2x_link_settings_supported(struct bnx2x *bp,
6951 int port = BP_PORT(bp);
6954 switch (switch_cfg) {
6956 BNX2X_DEV_INFO("switch_cfg 0x%x (1G)\n", switch_cfg);
6959 SERDES_EXT_PHY_TYPE(bp->link_params.ext_phy_config);
6960 switch (ext_phy_type) {
6961 case PORT_HW_CFG_SERDES_EXT_PHY_TYPE_DIRECT:
6962 BNX2X_DEV_INFO("ext_phy_type 0x%x (Direct)\n",
6965 bp->port.supported |= (SUPPORTED_10baseT_Half |
6966 SUPPORTED_10baseT_Full |
6967 SUPPORTED_100baseT_Half |
6968 SUPPORTED_100baseT_Full |
6969 SUPPORTED_1000baseT_Full |
6970 SUPPORTED_2500baseX_Full |
6975 SUPPORTED_Asym_Pause);
6978 case PORT_HW_CFG_SERDES_EXT_PHY_TYPE_BCM5482:
6979 BNX2X_DEV_INFO("ext_phy_type 0x%x (5482)\n",
6982 bp->port.supported |= (SUPPORTED_10baseT_Half |
6983 SUPPORTED_10baseT_Full |
6984 SUPPORTED_100baseT_Half |
6985 SUPPORTED_100baseT_Full |
6986 SUPPORTED_1000baseT_Full |
6991 SUPPORTED_Asym_Pause);
6995 BNX2X_ERR("NVRAM config error. "
6996 "BAD SerDes ext_phy_config 0x%x\n",
6997 bp->link_params.ext_phy_config);
7001 bp->port.phy_addr = REG_RD(bp, NIG_REG_SERDES0_CTRL_PHY_ADDR +
7003 BNX2X_DEV_INFO("phy_addr 0x%x\n", bp->port.phy_addr);
7006 case SWITCH_CFG_10G:
7007 BNX2X_DEV_INFO("switch_cfg 0x%x (10G)\n", switch_cfg);
7010 XGXS_EXT_PHY_TYPE(bp->link_params.ext_phy_config);
7011 switch (ext_phy_type) {
7012 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT:
7013 BNX2X_DEV_INFO("ext_phy_type 0x%x (Direct)\n",
7016 bp->port.supported |= (SUPPORTED_10baseT_Half |
7017 SUPPORTED_10baseT_Full |
7018 SUPPORTED_100baseT_Half |
7019 SUPPORTED_100baseT_Full |
7020 SUPPORTED_1000baseT_Full |
7021 SUPPORTED_2500baseX_Full |
7022 SUPPORTED_10000baseT_Full |
7027 SUPPORTED_Asym_Pause);
7030 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8705:
7031 BNX2X_DEV_INFO("ext_phy_type 0x%x (8705)\n",
7034 bp->port.supported |= (SUPPORTED_10000baseT_Full |
7037 SUPPORTED_Asym_Pause);
7040 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8706:
7041 BNX2X_DEV_INFO("ext_phy_type 0x%x (8706)\n",
7044 bp->port.supported |= (SUPPORTED_10000baseT_Full |
7045 SUPPORTED_1000baseT_Full |
7048 SUPPORTED_Asym_Pause);
7051 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8072:
7052 BNX2X_DEV_INFO("ext_phy_type 0x%x (8072)\n",
7055 bp->port.supported |= (SUPPORTED_10000baseT_Full |
7056 SUPPORTED_1000baseT_Full |
7060 SUPPORTED_Asym_Pause);
7063 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073:
7064 BNX2X_DEV_INFO("ext_phy_type 0x%x (8073)\n",
7067 bp->port.supported |= (SUPPORTED_10000baseT_Full |
7068 SUPPORTED_2500baseX_Full |
7069 SUPPORTED_1000baseT_Full |
7073 SUPPORTED_Asym_Pause);
7076 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101:
7077 BNX2X_DEV_INFO("ext_phy_type 0x%x (SFX7101)\n",
7080 bp->port.supported |= (SUPPORTED_10000baseT_Full |
7084 SUPPORTED_Asym_Pause);
7087 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE:
7088 BNX2X_ERR("XGXS PHY Failure detected 0x%x\n",
7089 bp->link_params.ext_phy_config);
7093 BNX2X_ERR("NVRAM config error. "
7094 "BAD XGXS ext_phy_config 0x%x\n",
7095 bp->link_params.ext_phy_config);
7099 bp->port.phy_addr = REG_RD(bp, NIG_REG_XGXS0_CTRL_PHY_ADDR +
7101 BNX2X_DEV_INFO("phy_addr 0x%x\n", bp->port.phy_addr);
7106 BNX2X_ERR("BAD switch_cfg link_config 0x%x\n",
7107 bp->port.link_config);
7110 bp->link_params.phy_addr = bp->port.phy_addr;
7112 /* mask what we support according to speed_cap_mask */
7113 if (!(bp->link_params.speed_cap_mask &
7114 PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_HALF))
7115 bp->port.supported &= ~SUPPORTED_10baseT_Half;
7117 if (!(bp->link_params.speed_cap_mask &
7118 PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_FULL))
7119 bp->port.supported &= ~SUPPORTED_10baseT_Full;
7121 if (!(bp->link_params.speed_cap_mask &
7122 PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_HALF))
7123 bp->port.supported &= ~SUPPORTED_100baseT_Half;
7125 if (!(bp->link_params.speed_cap_mask &
7126 PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_FULL))
7127 bp->port.supported &= ~SUPPORTED_100baseT_Full;
7129 if (!(bp->link_params.speed_cap_mask &
7130 PORT_HW_CFG_SPEED_CAPABILITY_D0_1G))
7131 bp->port.supported &= ~(SUPPORTED_1000baseT_Half |
7132 SUPPORTED_1000baseT_Full);
7134 if (!(bp->link_params.speed_cap_mask &
7135 PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G))
7136 bp->port.supported &= ~SUPPORTED_2500baseX_Full;
7138 if (!(bp->link_params.speed_cap_mask &
7139 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G))
7140 bp->port.supported &= ~SUPPORTED_10000baseT_Full;
7142 BNX2X_DEV_INFO("supported 0x%x\n", bp->port.supported);
7145 static void __devinit bnx2x_link_settings_requested(struct bnx2x *bp)
7147 bp->link_params.req_duplex = DUPLEX_FULL;
7149 switch (bp->port.link_config & PORT_FEATURE_LINK_SPEED_MASK) {
7150 case PORT_FEATURE_LINK_SPEED_AUTO:
7151 if (bp->port.supported & SUPPORTED_Autoneg) {
7152 bp->link_params.req_line_speed = SPEED_AUTO_NEG;
7153 bp->port.advertising = bp->port.supported;
7156 XGXS_EXT_PHY_TYPE(bp->link_params.ext_phy_config);
7158 if ((ext_phy_type ==
7159 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8705) ||
7161 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8706)) {
7162 /* force 10G, no AN */
7163 bp->link_params.req_line_speed = SPEED_10000;
7164 bp->port.advertising =
7165 (ADVERTISED_10000baseT_Full |
7169 BNX2X_ERR("NVRAM config error. "
7170 "Invalid link_config 0x%x"
7171 " Autoneg not supported\n",
7172 bp->port.link_config);
7177 case PORT_FEATURE_LINK_SPEED_10M_FULL:
7178 if (bp->port.supported & SUPPORTED_10baseT_Full) {
7179 bp->link_params.req_line_speed = SPEED_10;
7180 bp->port.advertising = (ADVERTISED_10baseT_Full |
7183 BNX2X_ERR("NVRAM config error. "
7184 "Invalid link_config 0x%x"
7185 " speed_cap_mask 0x%x\n",
7186 bp->port.link_config,
7187 bp->link_params.speed_cap_mask);
7192 case PORT_FEATURE_LINK_SPEED_10M_HALF:
7193 if (bp->port.supported & SUPPORTED_10baseT_Half) {
7194 bp->link_params.req_line_speed = SPEED_10;
7195 bp->link_params.req_duplex = DUPLEX_HALF;
7196 bp->port.advertising = (ADVERTISED_10baseT_Half |
7199 BNX2X_ERR("NVRAM config error. "
7200 "Invalid link_config 0x%x"
7201 " speed_cap_mask 0x%x\n",
7202 bp->port.link_config,
7203 bp->link_params.speed_cap_mask);
7208 case PORT_FEATURE_LINK_SPEED_100M_FULL:
7209 if (bp->port.supported & SUPPORTED_100baseT_Full) {
7210 bp->link_params.req_line_speed = SPEED_100;
7211 bp->port.advertising = (ADVERTISED_100baseT_Full |
7214 BNX2X_ERR("NVRAM config error. "
7215 "Invalid link_config 0x%x"
7216 " speed_cap_mask 0x%x\n",
7217 bp->port.link_config,
7218 bp->link_params.speed_cap_mask);
7223 case PORT_FEATURE_LINK_SPEED_100M_HALF:
7224 if (bp->port.supported & SUPPORTED_100baseT_Half) {
7225 bp->link_params.req_line_speed = SPEED_100;
7226 bp->link_params.req_duplex = DUPLEX_HALF;
7227 bp->port.advertising = (ADVERTISED_100baseT_Half |
7230 BNX2X_ERR("NVRAM config error. "
7231 "Invalid link_config 0x%x"
7232 " speed_cap_mask 0x%x\n",
7233 bp->port.link_config,
7234 bp->link_params.speed_cap_mask);
7239 case PORT_FEATURE_LINK_SPEED_1G:
7240 if (bp->port.supported & SUPPORTED_1000baseT_Full) {
7241 bp->link_params.req_line_speed = SPEED_1000;
7242 bp->port.advertising = (ADVERTISED_1000baseT_Full |
7245 BNX2X_ERR("NVRAM config error. "
7246 "Invalid link_config 0x%x"
7247 " speed_cap_mask 0x%x\n",
7248 bp->port.link_config,
7249 bp->link_params.speed_cap_mask);
7254 case PORT_FEATURE_LINK_SPEED_2_5G:
7255 if (bp->port.supported & SUPPORTED_2500baseX_Full) {
7256 bp->link_params.req_line_speed = SPEED_2500;
7257 bp->port.advertising = (ADVERTISED_2500baseX_Full |
7260 BNX2X_ERR("NVRAM config error. "
7261 "Invalid link_config 0x%x"
7262 " speed_cap_mask 0x%x\n",
7263 bp->port.link_config,
7264 bp->link_params.speed_cap_mask);
7269 case PORT_FEATURE_LINK_SPEED_10G_CX4:
7270 case PORT_FEATURE_LINK_SPEED_10G_KX4:
7271 case PORT_FEATURE_LINK_SPEED_10G_KR:
7272 if (bp->port.supported & SUPPORTED_10000baseT_Full) {
7273 bp->link_params.req_line_speed = SPEED_10000;
7274 bp->port.advertising = (ADVERTISED_10000baseT_Full |
7277 BNX2X_ERR("NVRAM config error. "
7278 "Invalid link_config 0x%x"
7279 " speed_cap_mask 0x%x\n",
7280 bp->port.link_config,
7281 bp->link_params.speed_cap_mask);
7287 BNX2X_ERR("NVRAM config error. "
7288 "BAD link speed link_config 0x%x\n",
7289 bp->port.link_config);
7290 bp->link_params.req_line_speed = SPEED_AUTO_NEG;
7291 bp->port.advertising = bp->port.supported;
7295 bp->link_params.req_flow_ctrl = (bp->port.link_config &
7296 PORT_FEATURE_FLOW_CONTROL_MASK);
7297 if ((bp->link_params.req_flow_ctrl == FLOW_CTRL_AUTO) &&
7298 !(bp->port.supported & SUPPORTED_Autoneg))
7299 bp->link_params.req_flow_ctrl = FLOW_CTRL_NONE;
7301 BNX2X_DEV_INFO("req_line_speed %d req_duplex %d req_flow_ctrl 0x%x"
7302 " advertising 0x%x\n",
7303 bp->link_params.req_line_speed,
7304 bp->link_params.req_duplex,
7305 bp->link_params.req_flow_ctrl, bp->port.advertising);
7308 static void __devinit bnx2x_get_port_hwinfo(struct bnx2x *bp)
7310 int port = BP_PORT(bp);
7313 bp->link_params.bp = bp;
7314 bp->link_params.port = port;
7316 bp->link_params.serdes_config =
7317 SHMEM_RD(bp, dev_info.port_hw_config[port].serdes_config);
7318 bp->link_params.lane_config =
7319 SHMEM_RD(bp, dev_info.port_hw_config[port].lane_config);
7320 bp->link_params.ext_phy_config =
7322 dev_info.port_hw_config[port].external_phy_config);
7323 bp->link_params.speed_cap_mask =
7325 dev_info.port_hw_config[port].speed_capability_mask);
7327 bp->port.link_config =
7328 SHMEM_RD(bp, dev_info.port_feature_config[port].link_config);
7330 BNX2X_DEV_INFO("serdes_config 0x%08x lane_config 0x%08x\n"
7331 KERN_INFO " ext_phy_config 0x%08x speed_cap_mask 0x%08x"
7332 " link_config 0x%08x\n",
7333 bp->link_params.serdes_config,
7334 bp->link_params.lane_config,
7335 bp->link_params.ext_phy_config,
7336 bp->link_params.speed_cap_mask, bp->port.link_config);
7338 bp->link_params.switch_cfg = (bp->port.link_config &
7339 PORT_FEATURE_CONNECTED_SWITCH_MASK);
7340 bnx2x_link_settings_supported(bp, bp->link_params.switch_cfg);
7342 bnx2x_link_settings_requested(bp);
7344 val2 = SHMEM_RD(bp, dev_info.port_hw_config[port].mac_upper);
7345 val = SHMEM_RD(bp, dev_info.port_hw_config[port].mac_lower);
7346 bp->dev->dev_addr[0] = (u8)(val2 >> 8 & 0xff);
7347 bp->dev->dev_addr[1] = (u8)(val2 & 0xff);
7348 bp->dev->dev_addr[2] = (u8)(val >> 24 & 0xff);
7349 bp->dev->dev_addr[3] = (u8)(val >> 16 & 0xff);
7350 bp->dev->dev_addr[4] = (u8)(val >> 8 & 0xff);
7351 bp->dev->dev_addr[5] = (u8)(val & 0xff);
7352 memcpy(bp->link_params.mac_addr, bp->dev->dev_addr, ETH_ALEN);
7353 memcpy(bp->dev->perm_addr, bp->dev->dev_addr, ETH_ALEN);
7356 static int __devinit bnx2x_get_hwinfo(struct bnx2x *bp)
7358 int func = BP_FUNC(bp);
7362 bnx2x_get_common_hwinfo(bp);
7366 if (CHIP_IS_E1H(bp)) {
7368 SHMEM_RD(bp, mf_cfg.func_mf_config[func].config);
7371 (SHMEM_RD(bp, mf_cfg.func_mf_config[func].e1hov_tag) &
7372 FUNC_MF_CFG_E1HOV_TAG_MASK);
7373 if (val != FUNC_MF_CFG_E1HOV_TAG_DEFAULT) {
7377 BNX2X_DEV_INFO("MF mode E1HOV for func %d is %d "
7379 func, bp->e1hov, bp->e1hov);
7381 BNX2X_DEV_INFO("Single function mode\n");
7383 BNX2X_ERR("!!! No valid E1HOV for func %d,"
7384 " aborting\n", func);
7390 if (!BP_NOMCP(bp)) {
7391 bnx2x_get_port_hwinfo(bp);
7393 bp->fw_seq = (SHMEM_RD(bp, func_mb[func].drv_mb_header) &
7394 DRV_MSG_SEQ_NUMBER_MASK);
7395 BNX2X_DEV_INFO("fw_seq 0x%08x\n", bp->fw_seq);
7399 val2 = SHMEM_RD(bp, mf_cfg.func_mf_config[func].mac_upper);
7400 val = SHMEM_RD(bp, mf_cfg.func_mf_config[func].mac_lower);
7401 if ((val2 != FUNC_MF_CFG_UPPERMAC_DEFAULT) &&
7402 (val != FUNC_MF_CFG_LOWERMAC_DEFAULT)) {
7403 bp->dev->dev_addr[0] = (u8)(val2 >> 8 & 0xff);
7404 bp->dev->dev_addr[1] = (u8)(val2 & 0xff);
7405 bp->dev->dev_addr[2] = (u8)(val >> 24 & 0xff);
7406 bp->dev->dev_addr[3] = (u8)(val >> 16 & 0xff);
7407 bp->dev->dev_addr[4] = (u8)(val >> 8 & 0xff);
7408 bp->dev->dev_addr[5] = (u8)(val & 0xff);
7409 memcpy(bp->link_params.mac_addr, bp->dev->dev_addr,
7411 memcpy(bp->dev->perm_addr, bp->dev->dev_addr,
7419 /* only supposed to happen on emulation/FPGA */
7420 BNX2X_ERR("warning rendom MAC workaround active\n");
7421 random_ether_addr(bp->dev->dev_addr);
7422 memcpy(bp->dev->perm_addr, bp->dev->dev_addr, ETH_ALEN);
7428 static int __devinit bnx2x_init_bp(struct bnx2x *bp)
7430 int func = BP_FUNC(bp);
7433 /* Disable interrupt handling until HW is initialized */
7434 atomic_set(&bp->intr_sem, 1);
7436 mutex_init(&bp->port.phy_mutex);
7438 INIT_WORK(&bp->sp_task, bnx2x_sp_task);
7439 INIT_WORK(&bp->reset_task, bnx2x_reset_task);
7441 rc = bnx2x_get_hwinfo(bp);
7443 /* need to reset chip if undi was active */
7445 bnx2x_undi_unload(bp);
7447 if (CHIP_REV_IS_FPGA(bp))
7448 printk(KERN_ERR PFX "FPGA detected\n");
7450 if (BP_NOMCP(bp) && (func == 0))
7452 "MCP disabled, must load devices in order!\n");
7456 bp->flags &= ~TPA_ENABLE_FLAG;
7457 bp->dev->features &= ~NETIF_F_LRO;
7459 bp->flags |= TPA_ENABLE_FLAG;
7460 bp->dev->features |= NETIF_F_LRO;
7464 bp->tx_ring_size = MAX_TX_AVAIL;
7465 bp->rx_ring_size = MAX_RX_AVAIL;
7473 bp->timer_interval = (CHIP_REV_IS_SLOW(bp) ? 5*HZ : HZ);
7474 bp->current_interval = (poll ? poll : bp->timer_interval);
7476 init_timer(&bp->timer);
7477 bp->timer.expires = jiffies + bp->current_interval;
7478 bp->timer.data = (unsigned long) bp;
7479 bp->timer.function = bnx2x_timer;
7485 * ethtool service functions
7488 /* All ethtool functions called with rtnl_lock */
7490 static int bnx2x_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
7492 struct bnx2x *bp = netdev_priv(dev);
7494 cmd->supported = bp->port.supported;
7495 cmd->advertising = bp->port.advertising;
7497 if (netif_carrier_ok(dev)) {
7498 cmd->speed = bp->link_vars.line_speed;
7499 cmd->duplex = bp->link_vars.duplex;
7501 cmd->speed = bp->link_params.req_line_speed;
7502 cmd->duplex = bp->link_params.req_duplex;
7507 vn_max_rate = ((bp->mf_config & FUNC_MF_CFG_MAX_BW_MASK) >>
7508 FUNC_MF_CFG_MAX_BW_SHIFT) * 100;
7509 if (vn_max_rate < cmd->speed)
7510 cmd->speed = vn_max_rate;
7513 if (bp->link_params.switch_cfg == SWITCH_CFG_10G) {
7515 XGXS_EXT_PHY_TYPE(bp->link_params.ext_phy_config);
7517 switch (ext_phy_type) {
7518 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT:
7519 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8705:
7520 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8706:
7521 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8072:
7522 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073:
7523 cmd->port = PORT_FIBRE;
7526 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101:
7527 cmd->port = PORT_TP;
7530 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE:
7531 BNX2X_ERR("XGXS PHY Failure detected 0x%x\n",
7532 bp->link_params.ext_phy_config);
7536 DP(NETIF_MSG_LINK, "BAD XGXS ext_phy_config 0x%x\n",
7537 bp->link_params.ext_phy_config);
7541 cmd->port = PORT_TP;
7543 cmd->phy_address = bp->port.phy_addr;
7544 cmd->transceiver = XCVR_INTERNAL;
7546 if (bp->link_params.req_line_speed == SPEED_AUTO_NEG)
7547 cmd->autoneg = AUTONEG_ENABLE;
7549 cmd->autoneg = AUTONEG_DISABLE;
7554 DP(NETIF_MSG_LINK, "ethtool_cmd: cmd %d\n"
7555 DP_LEVEL " supported 0x%x advertising 0x%x speed %d\n"
7556 DP_LEVEL " duplex %d port %d phy_address %d transceiver %d\n"
7557 DP_LEVEL " autoneg %d maxtxpkt %d maxrxpkt %d\n",
7558 cmd->cmd, cmd->supported, cmd->advertising, cmd->speed,
7559 cmd->duplex, cmd->port, cmd->phy_address, cmd->transceiver,
7560 cmd->autoneg, cmd->maxtxpkt, cmd->maxrxpkt);
7565 static int bnx2x_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
7567 struct bnx2x *bp = netdev_priv(dev);
7573 DP(NETIF_MSG_LINK, "ethtool_cmd: cmd %d\n"
7574 DP_LEVEL " supported 0x%x advertising 0x%x speed %d\n"
7575 DP_LEVEL " duplex %d port %d phy_address %d transceiver %d\n"
7576 DP_LEVEL " autoneg %d maxtxpkt %d maxrxpkt %d\n",
7577 cmd->cmd, cmd->supported, cmd->advertising, cmd->speed,
7578 cmd->duplex, cmd->port, cmd->phy_address, cmd->transceiver,
7579 cmd->autoneg, cmd->maxtxpkt, cmd->maxrxpkt);
7581 if (cmd->autoneg == AUTONEG_ENABLE) {
7582 if (!(bp->port.supported & SUPPORTED_Autoneg)) {
7583 DP(NETIF_MSG_LINK, "Autoneg not supported\n");
7587 /* advertise the requested speed and duplex if supported */
7588 cmd->advertising &= bp->port.supported;
7590 bp->link_params.req_line_speed = SPEED_AUTO_NEG;
7591 bp->link_params.req_duplex = DUPLEX_FULL;
7592 bp->port.advertising |= (ADVERTISED_Autoneg |
7595 } else { /* forced speed */
7596 /* advertise the requested speed and duplex if supported */
7597 switch (cmd->speed) {
7599 if (cmd->duplex == DUPLEX_FULL) {
7600 if (!(bp->port.supported &
7601 SUPPORTED_10baseT_Full)) {
7603 "10M full not supported\n");
7607 advertising = (ADVERTISED_10baseT_Full |
7610 if (!(bp->port.supported &
7611 SUPPORTED_10baseT_Half)) {
7613 "10M half not supported\n");
7617 advertising = (ADVERTISED_10baseT_Half |
7623 if (cmd->duplex == DUPLEX_FULL) {
7624 if (!(bp->port.supported &
7625 SUPPORTED_100baseT_Full)) {
7627 "100M full not supported\n");
7631 advertising = (ADVERTISED_100baseT_Full |
7634 if (!(bp->port.supported &
7635 SUPPORTED_100baseT_Half)) {
7637 "100M half not supported\n");
7641 advertising = (ADVERTISED_100baseT_Half |
7647 if (cmd->duplex != DUPLEX_FULL) {
7648 DP(NETIF_MSG_LINK, "1G half not supported\n");
7652 if (!(bp->port.supported & SUPPORTED_1000baseT_Full)) {
7653 DP(NETIF_MSG_LINK, "1G full not supported\n");
7657 advertising = (ADVERTISED_1000baseT_Full |
7662 if (cmd->duplex != DUPLEX_FULL) {
7664 "2.5G half not supported\n");
7668 if (!(bp->port.supported & SUPPORTED_2500baseX_Full)) {
7670 "2.5G full not supported\n");
7674 advertising = (ADVERTISED_2500baseX_Full |
7679 if (cmd->duplex != DUPLEX_FULL) {
7680 DP(NETIF_MSG_LINK, "10G half not supported\n");
7684 if (!(bp->port.supported & SUPPORTED_10000baseT_Full)) {
7685 DP(NETIF_MSG_LINK, "10G full not supported\n");
7689 advertising = (ADVERTISED_10000baseT_Full |
7694 DP(NETIF_MSG_LINK, "Unsupported speed\n");
7698 bp->link_params.req_line_speed = cmd->speed;
7699 bp->link_params.req_duplex = cmd->duplex;
7700 bp->port.advertising = advertising;
7703 DP(NETIF_MSG_LINK, "req_line_speed %d\n"
7704 DP_LEVEL " req_duplex %d advertising 0x%x\n",
7705 bp->link_params.req_line_speed, bp->link_params.req_duplex,
7706 bp->port.advertising);
7708 if (netif_running(dev)) {
7709 bnx2x_stats_handle(bp, STATS_EVENT_STOP);
7716 #define PHY_FW_VER_LEN 10
7718 static void bnx2x_get_drvinfo(struct net_device *dev,
7719 struct ethtool_drvinfo *info)
7721 struct bnx2x *bp = netdev_priv(dev);
7722 char phy_fw_ver[PHY_FW_VER_LEN];
7724 strcpy(info->driver, DRV_MODULE_NAME);
7725 strcpy(info->version, DRV_MODULE_VERSION);
7727 phy_fw_ver[0] = '\0';
7729 bnx2x_acquire_phy_lock(bp);
7730 bnx2x_get_ext_phy_fw_version(&bp->link_params,
7731 (bp->state != BNX2X_STATE_CLOSED),
7732 phy_fw_ver, PHY_FW_VER_LEN);
7733 bnx2x_release_phy_lock(bp);
7736 snprintf(info->fw_version, 32, "%d.%d.%d:%d BC:%x%s%s",
7737 BCM_5710_FW_MAJOR_VERSION, BCM_5710_FW_MINOR_VERSION,
7738 BCM_5710_FW_REVISION_VERSION,
7739 BCM_5710_FW_COMPILE_FLAGS, bp->common.bc_ver,
7740 ((phy_fw_ver[0] != '\0')? " PHY:":""), phy_fw_ver);
7741 strcpy(info->bus_info, pci_name(bp->pdev));
7742 info->n_stats = BNX2X_NUM_STATS;
7743 info->testinfo_len = BNX2X_NUM_TESTS;
7744 info->eedump_len = bp->common.flash_size;
7745 info->regdump_len = 0;
7748 static void bnx2x_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
7750 struct bnx2x *bp = netdev_priv(dev);
7752 if (bp->flags & NO_WOL_FLAG) {
7756 wol->supported = WAKE_MAGIC;
7758 wol->wolopts = WAKE_MAGIC;
7762 memset(&wol->sopass, 0, sizeof(wol->sopass));
7765 static int bnx2x_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
7767 struct bnx2x *bp = netdev_priv(dev);
7769 if (wol->wolopts & ~WAKE_MAGIC)
7772 if (wol->wolopts & WAKE_MAGIC) {
7773 if (bp->flags & NO_WOL_FLAG)
7783 static u32 bnx2x_get_msglevel(struct net_device *dev)
7785 struct bnx2x *bp = netdev_priv(dev);
7787 return bp->msglevel;
7790 static void bnx2x_set_msglevel(struct net_device *dev, u32 level)
7792 struct bnx2x *bp = netdev_priv(dev);
7794 if (capable(CAP_NET_ADMIN))
7795 bp->msglevel = level;
7798 static int bnx2x_nway_reset(struct net_device *dev)
7800 struct bnx2x *bp = netdev_priv(dev);
7805 if (netif_running(dev)) {
7806 bnx2x_stats_handle(bp, STATS_EVENT_STOP);
7813 static int bnx2x_get_eeprom_len(struct net_device *dev)
7815 struct bnx2x *bp = netdev_priv(dev);
7817 return bp->common.flash_size;
7820 static int bnx2x_acquire_nvram_lock(struct bnx2x *bp)
7822 int port = BP_PORT(bp);
7826 /* adjust timeout for emulation/FPGA */
7827 count = NVRAM_TIMEOUT_COUNT;
7828 if (CHIP_REV_IS_SLOW(bp))
7831 /* request access to nvram interface */
7832 REG_WR(bp, MCP_REG_MCPR_NVM_SW_ARB,
7833 (MCPR_NVM_SW_ARB_ARB_REQ_SET1 << port));
7835 for (i = 0; i < count*10; i++) {
7836 val = REG_RD(bp, MCP_REG_MCPR_NVM_SW_ARB);
7837 if (val & (MCPR_NVM_SW_ARB_ARB_ARB1 << port))
7843 if (!(val & (MCPR_NVM_SW_ARB_ARB_ARB1 << port))) {
7844 DP(BNX2X_MSG_NVM, "cannot get access to nvram interface\n");
7851 static int bnx2x_release_nvram_lock(struct bnx2x *bp)
7853 int port = BP_PORT(bp);
7857 /* adjust timeout for emulation/FPGA */
7858 count = NVRAM_TIMEOUT_COUNT;
7859 if (CHIP_REV_IS_SLOW(bp))
7862 /* relinquish nvram interface */
7863 REG_WR(bp, MCP_REG_MCPR_NVM_SW_ARB,
7864 (MCPR_NVM_SW_ARB_ARB_REQ_CLR1 << port));
7866 for (i = 0; i < count*10; i++) {
7867 val = REG_RD(bp, MCP_REG_MCPR_NVM_SW_ARB);
7868 if (!(val & (MCPR_NVM_SW_ARB_ARB_ARB1 << port)))
7874 if (val & (MCPR_NVM_SW_ARB_ARB_ARB1 << port)) {
7875 DP(BNX2X_MSG_NVM, "cannot free access to nvram interface\n");
7882 static void bnx2x_enable_nvram_access(struct bnx2x *bp)
7886 val = REG_RD(bp, MCP_REG_MCPR_NVM_ACCESS_ENABLE);
7888 /* enable both bits, even on read */
7889 REG_WR(bp, MCP_REG_MCPR_NVM_ACCESS_ENABLE,
7890 (val | MCPR_NVM_ACCESS_ENABLE_EN |
7891 MCPR_NVM_ACCESS_ENABLE_WR_EN));
7894 static void bnx2x_disable_nvram_access(struct bnx2x *bp)
7898 val = REG_RD(bp, MCP_REG_MCPR_NVM_ACCESS_ENABLE);
7900 /* disable both bits, even after read */
7901 REG_WR(bp, MCP_REG_MCPR_NVM_ACCESS_ENABLE,
7902 (val & ~(MCPR_NVM_ACCESS_ENABLE_EN |
7903 MCPR_NVM_ACCESS_ENABLE_WR_EN)));
7906 static int bnx2x_nvram_read_dword(struct bnx2x *bp, u32 offset, u32 *ret_val,
7912 /* build the command word */
7913 cmd_flags |= MCPR_NVM_COMMAND_DOIT;
7915 /* need to clear DONE bit separately */
7916 REG_WR(bp, MCP_REG_MCPR_NVM_COMMAND, MCPR_NVM_COMMAND_DONE);
7918 /* address of the NVRAM to read from */
7919 REG_WR(bp, MCP_REG_MCPR_NVM_ADDR,
7920 (offset & MCPR_NVM_ADDR_NVM_ADDR_VALUE));
7922 /* issue a read command */
7923 REG_WR(bp, MCP_REG_MCPR_NVM_COMMAND, cmd_flags);
7925 /* adjust timeout for emulation/FPGA */
7926 count = NVRAM_TIMEOUT_COUNT;
7927 if (CHIP_REV_IS_SLOW(bp))
7930 /* wait for completion */
7933 for (i = 0; i < count; i++) {
7935 val = REG_RD(bp, MCP_REG_MCPR_NVM_COMMAND);
7937 if (val & MCPR_NVM_COMMAND_DONE) {
7938 val = REG_RD(bp, MCP_REG_MCPR_NVM_READ);
7939 /* we read nvram data in cpu order
7940 * but ethtool sees it as an array of bytes
7941 * converting to big-endian will do the work */
7942 val = cpu_to_be32(val);
7952 static int bnx2x_nvram_read(struct bnx2x *bp, u32 offset, u8 *ret_buf,
7959 if ((offset & 0x03) || (buf_size & 0x03) || (buf_size == 0)) {
7961 "Invalid parameter: offset 0x%x buf_size 0x%x\n",
7966 if (offset + buf_size > bp->common.flash_size) {
7967 DP(BNX2X_MSG_NVM, "Invalid parameter: offset (0x%x) +"
7968 " buf_size (0x%x) > flash_size (0x%x)\n",
7969 offset, buf_size, bp->common.flash_size);
7973 /* request access to nvram interface */
7974 rc = bnx2x_acquire_nvram_lock(bp);
7978 /* enable access to nvram interface */
7979 bnx2x_enable_nvram_access(bp);
7981 /* read the first word(s) */
7982 cmd_flags = MCPR_NVM_COMMAND_FIRST;
7983 while ((buf_size > sizeof(u32)) && (rc == 0)) {
7984 rc = bnx2x_nvram_read_dword(bp, offset, &val, cmd_flags);
7985 memcpy(ret_buf, &val, 4);
7987 /* advance to the next dword */
7988 offset += sizeof(u32);
7989 ret_buf += sizeof(u32);
7990 buf_size -= sizeof(u32);
7995 cmd_flags |= MCPR_NVM_COMMAND_LAST;
7996 rc = bnx2x_nvram_read_dword(bp, offset, &val, cmd_flags);
7997 memcpy(ret_buf, &val, 4);
8000 /* disable access to nvram interface */
8001 bnx2x_disable_nvram_access(bp);
8002 bnx2x_release_nvram_lock(bp);
8007 static int bnx2x_get_eeprom(struct net_device *dev,
8008 struct ethtool_eeprom *eeprom, u8 *eebuf)
8010 struct bnx2x *bp = netdev_priv(dev);
8013 DP(BNX2X_MSG_NVM, "ethtool_eeprom: cmd %d\n"
8014 DP_LEVEL " magic 0x%x offset 0x%x (%d) len 0x%x (%d)\n",
8015 eeprom->cmd, eeprom->magic, eeprom->offset, eeprom->offset,
8016 eeprom->len, eeprom->len);
8018 /* parameters already validated in ethtool_get_eeprom */
8020 rc = bnx2x_nvram_read(bp, eeprom->offset, eebuf, eeprom->len);
8025 static int bnx2x_nvram_write_dword(struct bnx2x *bp, u32 offset, u32 val,
8030 /* build the command word */
8031 cmd_flags |= MCPR_NVM_COMMAND_DOIT | MCPR_NVM_COMMAND_WR;
8033 /* need to clear DONE bit separately */
8034 REG_WR(bp, MCP_REG_MCPR_NVM_COMMAND, MCPR_NVM_COMMAND_DONE);
8036 /* write the data */
8037 REG_WR(bp, MCP_REG_MCPR_NVM_WRITE, val);
8039 /* address of the NVRAM to write to */
8040 REG_WR(bp, MCP_REG_MCPR_NVM_ADDR,
8041 (offset & MCPR_NVM_ADDR_NVM_ADDR_VALUE));
8043 /* issue the write command */
8044 REG_WR(bp, MCP_REG_MCPR_NVM_COMMAND, cmd_flags);
8046 /* adjust timeout for emulation/FPGA */
8047 count = NVRAM_TIMEOUT_COUNT;
8048 if (CHIP_REV_IS_SLOW(bp))
8051 /* wait for completion */
8053 for (i = 0; i < count; i++) {
8055 val = REG_RD(bp, MCP_REG_MCPR_NVM_COMMAND);
8056 if (val & MCPR_NVM_COMMAND_DONE) {
8065 #define BYTE_OFFSET(offset) (8 * (offset & 0x03))
8067 static int bnx2x_nvram_write1(struct bnx2x *bp, u32 offset, u8 *data_buf,
8075 if (offset + buf_size > bp->common.flash_size) {
8076 DP(BNX2X_MSG_NVM, "Invalid parameter: offset (0x%x) +"
8077 " buf_size (0x%x) > flash_size (0x%x)\n",
8078 offset, buf_size, bp->common.flash_size);
8082 /* request access to nvram interface */
8083 rc = bnx2x_acquire_nvram_lock(bp);
8087 /* enable access to nvram interface */
8088 bnx2x_enable_nvram_access(bp);
8090 cmd_flags = (MCPR_NVM_COMMAND_FIRST | MCPR_NVM_COMMAND_LAST);
8091 align_offset = (offset & ~0x03);
8092 rc = bnx2x_nvram_read_dword(bp, align_offset, &val, cmd_flags);
8095 val &= ~(0xff << BYTE_OFFSET(offset));
8096 val |= (*data_buf << BYTE_OFFSET(offset));
8098 /* nvram data is returned as an array of bytes
8099 * convert it back to cpu order */
8100 val = be32_to_cpu(val);
8102 rc = bnx2x_nvram_write_dword(bp, align_offset, val,
8106 /* disable access to nvram interface */
8107 bnx2x_disable_nvram_access(bp);
8108 bnx2x_release_nvram_lock(bp);
8113 static int bnx2x_nvram_write(struct bnx2x *bp, u32 offset, u8 *data_buf,
8121 if (buf_size == 1) /* ethtool */
8122 return bnx2x_nvram_write1(bp, offset, data_buf, buf_size);
8124 if ((offset & 0x03) || (buf_size & 0x03) || (buf_size == 0)) {
8126 "Invalid parameter: offset 0x%x buf_size 0x%x\n",
8131 if (offset + buf_size > bp->common.flash_size) {
8132 DP(BNX2X_MSG_NVM, "Invalid parameter: offset (0x%x) +"
8133 " buf_size (0x%x) > flash_size (0x%x)\n",
8134 offset, buf_size, bp->common.flash_size);
8138 /* request access to nvram interface */
8139 rc = bnx2x_acquire_nvram_lock(bp);
8143 /* enable access to nvram interface */
8144 bnx2x_enable_nvram_access(bp);
8147 cmd_flags = MCPR_NVM_COMMAND_FIRST;
8148 while ((written_so_far < buf_size) && (rc == 0)) {
8149 if (written_so_far == (buf_size - sizeof(u32)))
8150 cmd_flags |= MCPR_NVM_COMMAND_LAST;
8151 else if (((offset + 4) % NVRAM_PAGE_SIZE) == 0)
8152 cmd_flags |= MCPR_NVM_COMMAND_LAST;
8153 else if ((offset % NVRAM_PAGE_SIZE) == 0)
8154 cmd_flags |= MCPR_NVM_COMMAND_FIRST;
8156 memcpy(&val, data_buf, 4);
8158 rc = bnx2x_nvram_write_dword(bp, offset, val, cmd_flags);
8160 /* advance to the next dword */
8161 offset += sizeof(u32);
8162 data_buf += sizeof(u32);
8163 written_so_far += sizeof(u32);
8167 /* disable access to nvram interface */
8168 bnx2x_disable_nvram_access(bp);
8169 bnx2x_release_nvram_lock(bp);
8174 static int bnx2x_set_eeprom(struct net_device *dev,
8175 struct ethtool_eeprom *eeprom, u8 *eebuf)
8177 struct bnx2x *bp = netdev_priv(dev);
8180 DP(BNX2X_MSG_NVM, "ethtool_eeprom: cmd %d\n"
8181 DP_LEVEL " magic 0x%x offset 0x%x (%d) len 0x%x (%d)\n",
8182 eeprom->cmd, eeprom->magic, eeprom->offset, eeprom->offset,
8183 eeprom->len, eeprom->len);
8185 /* parameters already validated in ethtool_set_eeprom */
8187 /* If the magic number is PHY (0x00504859) upgrade the PHY FW */
8188 if (eeprom->magic == 0x00504859)
8191 bnx2x_acquire_phy_lock(bp);
8192 rc = bnx2x_flash_download(bp, BP_PORT(bp),
8193 bp->link_params.ext_phy_config,
8194 (bp->state != BNX2X_STATE_CLOSED),
8195 eebuf, eeprom->len);
8196 if ((bp->state == BNX2X_STATE_OPEN) ||
8197 (bp->state == BNX2X_STATE_DISABLED)) {
8198 rc |= bnx2x_link_reset(&bp->link_params,
8200 rc |= bnx2x_phy_init(&bp->link_params,
8203 bnx2x_release_phy_lock(bp);
8205 } else /* Only the PMF can access the PHY */
8208 rc = bnx2x_nvram_write(bp, eeprom->offset, eebuf, eeprom->len);
8213 static int bnx2x_get_coalesce(struct net_device *dev,
8214 struct ethtool_coalesce *coal)
8216 struct bnx2x *bp = netdev_priv(dev);
8218 memset(coal, 0, sizeof(struct ethtool_coalesce));
8220 coal->rx_coalesce_usecs = bp->rx_ticks;
8221 coal->tx_coalesce_usecs = bp->tx_ticks;
8226 static int bnx2x_set_coalesce(struct net_device *dev,
8227 struct ethtool_coalesce *coal)
8229 struct bnx2x *bp = netdev_priv(dev);
8231 bp->rx_ticks = (u16) coal->rx_coalesce_usecs;
8232 if (bp->rx_ticks > 3000)
8233 bp->rx_ticks = 3000;
8235 bp->tx_ticks = (u16) coal->tx_coalesce_usecs;
8236 if (bp->tx_ticks > 0x3000)
8237 bp->tx_ticks = 0x3000;
8239 if (netif_running(dev))
8240 bnx2x_update_coalesce(bp);
8245 static int bnx2x_set_flags(struct net_device *dev, u32 data)
8247 struct bnx2x *bp = netdev_priv(dev);
8251 if (data & ETH_FLAG_LRO) {
8252 if (!(dev->features & NETIF_F_LRO)) {
8253 dev->features |= NETIF_F_LRO;
8254 bp->flags |= TPA_ENABLE_FLAG;
8258 } else if (dev->features & NETIF_F_LRO) {
8259 dev->features &= ~NETIF_F_LRO;
8260 bp->flags &= ~TPA_ENABLE_FLAG;
8264 if (changed && netif_running(dev)) {
8265 bnx2x_nic_unload(bp, UNLOAD_NORMAL);
8266 rc = bnx2x_nic_load(bp, LOAD_NORMAL);
8272 static void bnx2x_get_ringparam(struct net_device *dev,
8273 struct ethtool_ringparam *ering)
8275 struct bnx2x *bp = netdev_priv(dev);
8277 ering->rx_max_pending = MAX_RX_AVAIL;
8278 ering->rx_mini_max_pending = 0;
8279 ering->rx_jumbo_max_pending = 0;
8281 ering->rx_pending = bp->rx_ring_size;
8282 ering->rx_mini_pending = 0;
8283 ering->rx_jumbo_pending = 0;
8285 ering->tx_max_pending = MAX_TX_AVAIL;
8286 ering->tx_pending = bp->tx_ring_size;
8289 static int bnx2x_set_ringparam(struct net_device *dev,
8290 struct ethtool_ringparam *ering)
8292 struct bnx2x *bp = netdev_priv(dev);
8295 if ((ering->rx_pending > MAX_RX_AVAIL) ||
8296 (ering->tx_pending > MAX_TX_AVAIL) ||
8297 (ering->tx_pending <= MAX_SKB_FRAGS + 4))
8300 bp->rx_ring_size = ering->rx_pending;
8301 bp->tx_ring_size = ering->tx_pending;
8303 if (netif_running(dev)) {
8304 bnx2x_nic_unload(bp, UNLOAD_NORMAL);
8305 rc = bnx2x_nic_load(bp, LOAD_NORMAL);
8311 static void bnx2x_get_pauseparam(struct net_device *dev,
8312 struct ethtool_pauseparam *epause)
8314 struct bnx2x *bp = netdev_priv(dev);
8316 epause->autoneg = (bp->link_params.req_flow_ctrl == FLOW_CTRL_AUTO) &&
8317 (bp->link_params.req_line_speed == SPEED_AUTO_NEG);
8319 epause->rx_pause = ((bp->link_vars.flow_ctrl & FLOW_CTRL_RX) ==
8321 epause->tx_pause = ((bp->link_vars.flow_ctrl & FLOW_CTRL_TX) ==
8324 DP(NETIF_MSG_LINK, "ethtool_pauseparam: cmd %d\n"
8325 DP_LEVEL " autoneg %d rx_pause %d tx_pause %d\n",
8326 epause->cmd, epause->autoneg, epause->rx_pause, epause->tx_pause);
8329 static int bnx2x_set_pauseparam(struct net_device *dev,
8330 struct ethtool_pauseparam *epause)
8332 struct bnx2x *bp = netdev_priv(dev);
8337 DP(NETIF_MSG_LINK, "ethtool_pauseparam: cmd %d\n"
8338 DP_LEVEL " autoneg %d rx_pause %d tx_pause %d\n",
8339 epause->cmd, epause->autoneg, epause->rx_pause, epause->tx_pause);
8341 bp->link_params.req_flow_ctrl = FLOW_CTRL_AUTO;
8343 if (epause->rx_pause)
8344 bp->link_params.req_flow_ctrl |= FLOW_CTRL_RX;
8346 if (epause->tx_pause)
8347 bp->link_params.req_flow_ctrl |= FLOW_CTRL_TX;
8349 if (bp->link_params.req_flow_ctrl == FLOW_CTRL_AUTO)
8350 bp->link_params.req_flow_ctrl = FLOW_CTRL_NONE;
8352 if (epause->autoneg) {
8353 if (!(bp->port.supported & SUPPORTED_Autoneg)) {
8354 DP(NETIF_MSG_LINK, "Autoneg not supported\n");
8358 if (bp->link_params.req_line_speed == SPEED_AUTO_NEG)
8359 bp->link_params.req_flow_ctrl = FLOW_CTRL_AUTO;
8363 "req_flow_ctrl 0x%x\n", bp->link_params.req_flow_ctrl);
8365 if (netif_running(dev)) {
8366 bnx2x_stats_handle(bp, STATS_EVENT_STOP);
8373 static u32 bnx2x_get_rx_csum(struct net_device *dev)
8375 struct bnx2x *bp = netdev_priv(dev);
8380 static int bnx2x_set_rx_csum(struct net_device *dev, u32 data)
8382 struct bnx2x *bp = netdev_priv(dev);
8388 static int bnx2x_set_tso(struct net_device *dev, u32 data)
8391 dev->features |= (NETIF_F_TSO | NETIF_F_TSO_ECN);
8392 dev->features |= NETIF_F_TSO6;
8394 dev->features &= ~(NETIF_F_TSO | NETIF_F_TSO_ECN);
8395 dev->features &= ~NETIF_F_TSO6;
8401 static const struct {
8402 char string[ETH_GSTRING_LEN];
8403 } bnx2x_tests_str_arr[BNX2X_NUM_TESTS] = {
8404 { "register_test (offline)" },
8405 { "memory_test (offline)" },
8406 { "loopback_test (offline)" },
8407 { "nvram_test (online)" },
8408 { "interrupt_test (online)" },
8409 { "link_test (online)" },
8410 { "idle check (online)" },
8411 { "MC errors (online)" }
8414 static int bnx2x_self_test_count(struct net_device *dev)
8416 return BNX2X_NUM_TESTS;
8419 static int bnx2x_test_registers(struct bnx2x *bp)
8421 int idx, i, rc = -ENODEV;
8423 int port = BP_PORT(bp);
8424 static const struct {
8429 /* 0 */ { BRB1_REG_PAUSE_LOW_THRESHOLD_0, 4, 0x000003ff },
8430 { DORQ_REG_DB_ADDR0, 4, 0xffffffff },
8431 { HC_REG_AGG_INT_0, 4, 0x000003ff },
8432 { PBF_REG_MAC_IF0_ENABLE, 4, 0x00000001 },
8433 { PBF_REG_P0_INIT_CRD, 4, 0x000007ff },
8434 { PRS_REG_CID_PORT_0, 4, 0x00ffffff },
8435 { PXP2_REG_PSWRQ_CDU0_L2P, 4, 0x000fffff },
8436 { PXP2_REG_RQ_CDU0_EFIRST_MEM_ADDR, 8, 0x0003ffff },
8437 { PXP2_REG_PSWRQ_TM0_L2P, 4, 0x000fffff },
8438 { PXP2_REG_RQ_USDM0_EFIRST_MEM_ADDR, 8, 0x0003ffff },
8439 /* 10 */ { PXP2_REG_PSWRQ_TSDM0_L2P, 4, 0x000fffff },
8440 { QM_REG_CONNNUM_0, 4, 0x000fffff },
8441 { TM_REG_LIN0_MAX_ACTIVE_CID, 4, 0x0003ffff },
8442 { SRC_REG_KEYRSS0_0, 40, 0xffffffff },
8443 { SRC_REG_KEYRSS0_7, 40, 0xffffffff },
8444 { XCM_REG_WU_DA_SET_TMR_CNT_FLG_CMD00, 4, 0x00000001 },
8445 { XCM_REG_WU_DA_CNT_CMD00, 4, 0x00000003 },
8446 { XCM_REG_GLB_DEL_ACK_MAX_CNT_0, 4, 0x000000ff },
8447 { NIG_REG_EGRESS_MNG0_FIFO, 20, 0xffffffff },
8448 { NIG_REG_LLH0_T_BIT, 4, 0x00000001 },
8449 /* 20 */ { NIG_REG_EMAC0_IN_EN, 4, 0x00000001 },
8450 { NIG_REG_BMAC0_IN_EN, 4, 0x00000001 },
8451 { NIG_REG_XCM0_OUT_EN, 4, 0x00000001 },
8452 { NIG_REG_BRB0_OUT_EN, 4, 0x00000001 },
8453 { NIG_REG_LLH0_XCM_MASK, 4, 0x00000007 },
8454 { NIG_REG_LLH0_ACPI_PAT_6_LEN, 68, 0x000000ff },
8455 { NIG_REG_LLH0_ACPI_PAT_0_CRC, 68, 0xffffffff },
8456 { NIG_REG_LLH0_DEST_MAC_0_0, 160, 0xffffffff },
8457 { NIG_REG_LLH0_DEST_IP_0_1, 160, 0xffffffff },
8458 { NIG_REG_LLH0_IPV4_IPV6_0, 160, 0x00000001 },
8459 /* 30 */ { NIG_REG_LLH0_DEST_UDP_0, 160, 0x0000ffff },
8460 { NIG_REG_LLH0_DEST_TCP_0, 160, 0x0000ffff },
8461 { NIG_REG_LLH0_VLAN_ID_0, 160, 0x00000fff },
8462 { NIG_REG_XGXS_SERDES0_MODE_SEL, 4, 0x00000001 },
8463 { NIG_REG_LED_CONTROL_OVERRIDE_TRAFFIC_P0, 4, 0x00000001 },
8464 { NIG_REG_STATUS_INTERRUPT_PORT0, 4, 0x07ffffff },
8465 { NIG_REG_XGXS0_CTRL_EXTREMOTEMDIOST, 24, 0x00000001 },
8466 { NIG_REG_SERDES0_CTRL_PHY_ADDR, 16, 0x0000001f },
8468 { 0xffffffff, 0, 0x00000000 }
8471 if (!netif_running(bp->dev))
8474 /* Repeat the test twice:
8475 First by writing 0x00000000, second by writing 0xffffffff */
8476 for (idx = 0; idx < 2; idx++) {
8483 wr_val = 0xffffffff;
8487 for (i = 0; reg_tbl[i].offset0 != 0xffffffff; i++) {
8488 u32 offset, mask, save_val, val;
8490 offset = reg_tbl[i].offset0 + port*reg_tbl[i].offset1;
8491 mask = reg_tbl[i].mask;
8493 save_val = REG_RD(bp, offset);
8495 REG_WR(bp, offset, wr_val);
8496 val = REG_RD(bp, offset);
8498 /* Restore the original register's value */
8499 REG_WR(bp, offset, save_val);
8501 /* verify that value is as expected value */
8502 if ((val & mask) != (wr_val & mask))
8513 static int bnx2x_test_memory(struct bnx2x *bp)
8515 int i, j, rc = -ENODEV;
8517 static const struct {
8521 { CCM_REG_XX_DESCR_TABLE, CCM_REG_XX_DESCR_TABLE_SIZE },
8522 { CFC_REG_ACTIVITY_COUNTER, CFC_REG_ACTIVITY_COUNTER_SIZE },
8523 { CFC_REG_LINK_LIST, CFC_REG_LINK_LIST_SIZE },
8524 { DMAE_REG_CMD_MEM, DMAE_REG_CMD_MEM_SIZE },
8525 { TCM_REG_XX_DESCR_TABLE, TCM_REG_XX_DESCR_TABLE_SIZE },
8526 { UCM_REG_XX_DESCR_TABLE, UCM_REG_XX_DESCR_TABLE_SIZE },
8527 { XCM_REG_XX_DESCR_TABLE, XCM_REG_XX_DESCR_TABLE_SIZE },
8531 static const struct {
8537 { "CCM_PRTY_STS", CCM_REG_CCM_PRTY_STS, 0x3ffc0, 0 },
8538 { "CFC_PRTY_STS", CFC_REG_CFC_PRTY_STS, 0x2, 0x2 },
8539 { "DMAE_PRTY_STS", DMAE_REG_DMAE_PRTY_STS, 0, 0 },
8540 { "TCM_PRTY_STS", TCM_REG_TCM_PRTY_STS, 0x3ffc0, 0 },
8541 { "UCM_PRTY_STS", UCM_REG_UCM_PRTY_STS, 0x3ffc0, 0 },
8542 { "XCM_PRTY_STS", XCM_REG_XCM_PRTY_STS, 0x3ffc1, 0 },
8544 { NULL, 0xffffffff, 0, 0 }
8547 if (!netif_running(bp->dev))
8550 /* Go through all the memories */
8551 for (i = 0; mem_tbl[i].offset != 0xffffffff; i++)
8552 for (j = 0; j < mem_tbl[i].size; j++)
8553 REG_RD(bp, mem_tbl[i].offset + j*4);
8555 /* Check the parity status */
8556 for (i = 0; prty_tbl[i].offset != 0xffffffff; i++) {
8557 val = REG_RD(bp, prty_tbl[i].offset);
8558 if ((CHIP_IS_E1(bp) && (val & ~(prty_tbl[i].e1_mask))) ||
8559 (CHIP_IS_E1H(bp) && (val & ~(prty_tbl[i].e1h_mask)))) {
8561 "%s is 0x%x\n", prty_tbl[i].name, val);
8572 static void bnx2x_netif_start(struct bnx2x *bp)
8576 if (atomic_dec_and_test(&bp->intr_sem)) {
8577 if (netif_running(bp->dev)) {
8578 bnx2x_int_enable(bp);
8579 for_each_queue(bp, i)
8580 napi_enable(&bnx2x_fp(bp, i, napi));
8581 if (bp->state == BNX2X_STATE_OPEN)
8582 netif_wake_queue(bp->dev);
8587 static void bnx2x_netif_stop(struct bnx2x *bp)
8591 if (netif_running(bp->dev)) {
8592 netif_tx_disable(bp->dev);
8593 bp->dev->trans_start = jiffies; /* prevent tx timeout */
8594 for_each_queue(bp, i)
8595 napi_disable(&bnx2x_fp(bp, i, napi));
8597 bnx2x_int_disable_sync(bp);
8600 static void bnx2x_wait_for_link(struct bnx2x *bp, u8 link_up)
8605 while (bnx2x_link_test(bp) && cnt--)
8609 static int bnx2x_run_loopback(struct bnx2x *bp, int loopback_mode, u8 link_up)
8611 unsigned int pkt_size, num_pkts, i;
8612 struct sk_buff *skb;
8613 unsigned char *packet;
8614 struct bnx2x_fastpath *fp = &bp->fp[0];
8615 u16 tx_start_idx, tx_idx;
8616 u16 rx_start_idx, rx_idx;
8618 struct sw_tx_bd *tx_buf;
8619 struct eth_tx_bd *tx_bd;
8621 union eth_rx_cqe *cqe;
8623 struct sw_rx_bd *rx_buf;
8627 if (loopback_mode == BNX2X_MAC_LOOPBACK) {
8628 bp->link_params.loopback_mode = LOOPBACK_BMAC;
8629 bnx2x_acquire_phy_lock(bp);
8630 bnx2x_phy_init(&bp->link_params, &bp->link_vars);
8631 bnx2x_release_phy_lock(bp);
8633 } else if (loopback_mode == BNX2X_PHY_LOOPBACK) {
8634 bp->link_params.loopback_mode = LOOPBACK_XGXS_10;
8635 bnx2x_acquire_phy_lock(bp);
8636 bnx2x_phy_init(&bp->link_params, &bp->link_vars);
8637 bnx2x_release_phy_lock(bp);
8638 /* wait until link state is restored */
8639 bnx2x_wait_for_link(bp, link_up);
8645 skb = netdev_alloc_skb(bp->dev, bp->rx_buf_size);
8648 goto test_loopback_exit;
8650 packet = skb_put(skb, pkt_size);
8651 memcpy(packet, bp->dev->dev_addr, ETH_ALEN);
8652 memset(packet + ETH_ALEN, 0, (ETH_HLEN - ETH_ALEN));
8653 for (i = ETH_HLEN; i < pkt_size; i++)
8654 packet[i] = (unsigned char) (i & 0xff);
8657 tx_start_idx = le16_to_cpu(*fp->tx_cons_sb);
8658 rx_start_idx = le16_to_cpu(*fp->rx_cons_sb);
8660 pkt_prod = fp->tx_pkt_prod++;
8661 tx_buf = &fp->tx_buf_ring[TX_BD(pkt_prod)];
8662 tx_buf->first_bd = fp->tx_bd_prod;
8665 tx_bd = &fp->tx_desc_ring[TX_BD(fp->tx_bd_prod)];
8666 mapping = pci_map_single(bp->pdev, skb->data,
8667 skb_headlen(skb), PCI_DMA_TODEVICE);
8668 tx_bd->addr_hi = cpu_to_le32(U64_HI(mapping));
8669 tx_bd->addr_lo = cpu_to_le32(U64_LO(mapping));
8670 tx_bd->nbd = cpu_to_le16(1);
8671 tx_bd->nbytes = cpu_to_le16(skb_headlen(skb));
8672 tx_bd->vlan = cpu_to_le16(pkt_prod);
8673 tx_bd->bd_flags.as_bitfield = (ETH_TX_BD_FLAGS_START_BD |
8674 ETH_TX_BD_FLAGS_END_BD);
8675 tx_bd->general_data = ((UNICAST_ADDRESS <<
8676 ETH_TX_BD_ETH_ADDR_TYPE_SHIFT) | 1);
8678 fp->hw_tx_prods->bds_prod =
8679 cpu_to_le16(le16_to_cpu(fp->hw_tx_prods->bds_prod) + 1);
8680 mb(); /* FW restriction: must not reorder writing nbd and packets */
8681 fp->hw_tx_prods->packets_prod =
8682 cpu_to_le32(le32_to_cpu(fp->hw_tx_prods->packets_prod) + 1);
8683 DOORBELL(bp, FP_IDX(fp), 0);
8689 bp->dev->trans_start = jiffies;
8693 tx_idx = le16_to_cpu(*fp->tx_cons_sb);
8694 if (tx_idx != tx_start_idx + num_pkts)
8695 goto test_loopback_exit;
8697 rx_idx = le16_to_cpu(*fp->rx_cons_sb);
8698 if (rx_idx != rx_start_idx + num_pkts)
8699 goto test_loopback_exit;
8701 cqe = &fp->rx_comp_ring[RCQ_BD(fp->rx_comp_cons)];
8702 cqe_fp_flags = cqe->fast_path_cqe.type_error_flags;
8703 if (CQE_TYPE(cqe_fp_flags) || (cqe_fp_flags & ETH_RX_ERROR_FALGS))
8704 goto test_loopback_rx_exit;
8706 len = le16_to_cpu(cqe->fast_path_cqe.pkt_len);
8707 if (len != pkt_size)
8708 goto test_loopback_rx_exit;
8710 rx_buf = &fp->rx_buf_ring[RX_BD(fp->rx_bd_cons)];
8712 skb_reserve(skb, cqe->fast_path_cqe.placement_offset);
8713 for (i = ETH_HLEN; i < pkt_size; i++)
8714 if (*(skb->data + i) != (unsigned char) (i & 0xff))
8715 goto test_loopback_rx_exit;
8719 test_loopback_rx_exit:
8720 bp->dev->last_rx = jiffies;
8722 fp->rx_bd_cons = NEXT_RX_IDX(fp->rx_bd_cons);
8723 fp->rx_bd_prod = NEXT_RX_IDX(fp->rx_bd_prod);
8724 fp->rx_comp_cons = NEXT_RCQ_IDX(fp->rx_comp_cons);
8725 fp->rx_comp_prod = NEXT_RCQ_IDX(fp->rx_comp_prod);
8727 /* Update producers */
8728 bnx2x_update_rx_prod(bp, fp, fp->rx_bd_prod, fp->rx_comp_prod,
8730 mmiowb(); /* keep prod updates ordered */
8733 bp->link_params.loopback_mode = LOOPBACK_NONE;
8738 static int bnx2x_test_loopback(struct bnx2x *bp, u8 link_up)
8742 if (!netif_running(bp->dev))
8743 return BNX2X_LOOPBACK_FAILED;
8745 bnx2x_netif_stop(bp);
8747 if (bnx2x_run_loopback(bp, BNX2X_MAC_LOOPBACK, link_up)) {
8748 DP(NETIF_MSG_PROBE, "MAC loopback failed\n");
8749 rc |= BNX2X_MAC_LOOPBACK_FAILED;
8752 if (bnx2x_run_loopback(bp, BNX2X_PHY_LOOPBACK, link_up)) {
8753 DP(NETIF_MSG_PROBE, "PHY loopback failed\n");
8754 rc |= BNX2X_PHY_LOOPBACK_FAILED;
8757 bnx2x_netif_start(bp);
8762 #define CRC32_RESIDUAL 0xdebb20e3
8764 static int bnx2x_test_nvram(struct bnx2x *bp)
8766 static const struct {
8770 { 0, 0x14 }, /* bootstrap */
8771 { 0x14, 0xec }, /* dir */
8772 { 0x100, 0x350 }, /* manuf_info */
8773 { 0x450, 0xf0 }, /* feature_info */
8774 { 0x640, 0x64 }, /* upgrade_key_info */
8776 { 0x708, 0x70 }, /* manuf_key_info */
8781 u8 *data = (u8 *)buf;
8785 rc = bnx2x_nvram_read(bp, 0, data, 4);
8787 DP(NETIF_MSG_PROBE, "magic value read (rc -%d)\n", -rc);
8788 goto test_nvram_exit;
8791 magic = be32_to_cpu(buf[0]);
8792 if (magic != 0x669955aa) {
8793 DP(NETIF_MSG_PROBE, "magic value (0x%08x)\n", magic);
8795 goto test_nvram_exit;
8798 for (i = 0; nvram_tbl[i].size; i++) {
8800 rc = bnx2x_nvram_read(bp, nvram_tbl[i].offset, data,
8804 "nvram_tbl[%d] read data (rc -%d)\n", i, -rc);
8805 goto test_nvram_exit;
8808 csum = ether_crc_le(nvram_tbl[i].size, data);
8809 if (csum != CRC32_RESIDUAL) {
8811 "nvram_tbl[%d] csum value (0x%08x)\n", i, csum);
8813 goto test_nvram_exit;
8821 static int bnx2x_test_intr(struct bnx2x *bp)
8823 struct mac_configuration_cmd *config = bnx2x_sp(bp, mac_config);
8826 if (!netif_running(bp->dev))
8829 config->hdr.length_6b = 0;
8830 config->hdr.offset = 0;
8831 config->hdr.client_id = BP_CL_ID(bp);
8832 config->hdr.reserved1 = 0;
8834 rc = bnx2x_sp_post(bp, RAMROD_CMD_ID_ETH_SET_MAC, 0,
8835 U64_HI(bnx2x_sp_mapping(bp, mac_config)),
8836 U64_LO(bnx2x_sp_mapping(bp, mac_config)), 0);
8838 bp->set_mac_pending++;
8839 for (i = 0; i < 10; i++) {
8840 if (!bp->set_mac_pending)
8842 msleep_interruptible(10);
8851 static void bnx2x_self_test(struct net_device *dev,
8852 struct ethtool_test *etest, u64 *buf)
8854 struct bnx2x *bp = netdev_priv(dev);
8856 memset(buf, 0, sizeof(u64) * BNX2X_NUM_TESTS);
8858 if (!netif_running(dev))
8861 /* offline tests are not suppoerted in MF mode */
8863 etest->flags &= ~ETH_TEST_FL_OFFLINE;
8865 if (etest->flags & ETH_TEST_FL_OFFLINE) {
8868 link_up = bp->link_vars.link_up;
8869 bnx2x_nic_unload(bp, UNLOAD_NORMAL);
8870 bnx2x_nic_load(bp, LOAD_DIAG);
8871 /* wait until link state is restored */
8872 bnx2x_wait_for_link(bp, link_up);
8874 if (bnx2x_test_registers(bp) != 0) {
8876 etest->flags |= ETH_TEST_FL_FAILED;
8878 if (bnx2x_test_memory(bp) != 0) {
8880 etest->flags |= ETH_TEST_FL_FAILED;
8882 buf[2] = bnx2x_test_loopback(bp, link_up);
8884 etest->flags |= ETH_TEST_FL_FAILED;
8886 bnx2x_nic_unload(bp, UNLOAD_NORMAL);
8887 bnx2x_nic_load(bp, LOAD_NORMAL);
8888 /* wait until link state is restored */
8889 bnx2x_wait_for_link(bp, link_up);
8891 if (bnx2x_test_nvram(bp) != 0) {
8893 etest->flags |= ETH_TEST_FL_FAILED;
8895 if (bnx2x_test_intr(bp) != 0) {
8897 etest->flags |= ETH_TEST_FL_FAILED;
8900 if (bnx2x_link_test(bp) != 0) {
8902 etest->flags |= ETH_TEST_FL_FAILED;
8904 buf[7] = bnx2x_mc_assert(bp);
8906 etest->flags |= ETH_TEST_FL_FAILED;
8908 #ifdef BNX2X_EXTRA_DEBUG
8909 bnx2x_panic_dump(bp);
8913 static const struct {
8917 #define STATS_FLAGS_PORT 1
8918 #define STATS_FLAGS_FUNC 2
8919 u8 string[ETH_GSTRING_LEN];
8920 } bnx2x_stats_arr[BNX2X_NUM_STATS] = {
8921 /* 1 */ { STATS_OFFSET32(valid_bytes_received_hi),
8922 8, STATS_FLAGS_FUNC, "rx_bytes" },
8923 { STATS_OFFSET32(error_bytes_received_hi),
8924 8, STATS_FLAGS_FUNC, "rx_error_bytes" },
8925 { STATS_OFFSET32(total_bytes_transmitted_hi),
8926 8, STATS_FLAGS_FUNC, "tx_bytes" },
8927 { STATS_OFFSET32(tx_stat_ifhcoutbadoctets_hi),
8928 8, STATS_FLAGS_PORT, "tx_error_bytes" },
8929 { STATS_OFFSET32(total_unicast_packets_received_hi),
8930 8, STATS_FLAGS_FUNC, "rx_ucast_packets" },
8931 { STATS_OFFSET32(total_multicast_packets_received_hi),
8932 8, STATS_FLAGS_FUNC, "rx_mcast_packets" },
8933 { STATS_OFFSET32(total_broadcast_packets_received_hi),
8934 8, STATS_FLAGS_FUNC, "rx_bcast_packets" },
8935 { STATS_OFFSET32(total_unicast_packets_transmitted_hi),
8936 8, STATS_FLAGS_FUNC, "tx_packets" },
8937 { STATS_OFFSET32(tx_stat_dot3statsinternalmactransmiterrors_hi),
8938 8, STATS_FLAGS_PORT, "tx_mac_errors" },
8939 /* 10 */{ STATS_OFFSET32(rx_stat_dot3statscarriersenseerrors_hi),
8940 8, STATS_FLAGS_PORT, "tx_carrier_errors" },
8941 { STATS_OFFSET32(rx_stat_dot3statsfcserrors_hi),
8942 8, STATS_FLAGS_PORT, "rx_crc_errors" },
8943 { STATS_OFFSET32(rx_stat_dot3statsalignmenterrors_hi),
8944 8, STATS_FLAGS_PORT, "rx_align_errors" },
8945 { STATS_OFFSET32(tx_stat_dot3statssinglecollisionframes_hi),
8946 8, STATS_FLAGS_PORT, "tx_single_collisions" },
8947 { STATS_OFFSET32(tx_stat_dot3statsmultiplecollisionframes_hi),
8948 8, STATS_FLAGS_PORT, "tx_multi_collisions" },
8949 { STATS_OFFSET32(tx_stat_dot3statsdeferredtransmissions_hi),
8950 8, STATS_FLAGS_PORT, "tx_deferred" },
8951 { STATS_OFFSET32(tx_stat_dot3statsexcessivecollisions_hi),
8952 8, STATS_FLAGS_PORT, "tx_excess_collisions" },
8953 { STATS_OFFSET32(tx_stat_dot3statslatecollisions_hi),
8954 8, STATS_FLAGS_PORT, "tx_late_collisions" },
8955 { STATS_OFFSET32(tx_stat_etherstatscollisions_hi),
8956 8, STATS_FLAGS_PORT, "tx_total_collisions" },
8957 { STATS_OFFSET32(rx_stat_etherstatsfragments_hi),
8958 8, STATS_FLAGS_PORT, "rx_fragments" },
8959 /* 20 */{ STATS_OFFSET32(rx_stat_etherstatsjabbers_hi),
8960 8, STATS_FLAGS_PORT, "rx_jabbers" },
8961 { STATS_OFFSET32(rx_stat_etherstatsundersizepkts_hi),
8962 8, STATS_FLAGS_PORT, "rx_undersize_packets" },
8963 { STATS_OFFSET32(jabber_packets_received),
8964 4, STATS_FLAGS_FUNC, "rx_oversize_packets" },
8965 { STATS_OFFSET32(tx_stat_etherstatspkts64octets_hi),
8966 8, STATS_FLAGS_PORT, "tx_64_byte_packets" },
8967 { STATS_OFFSET32(tx_stat_etherstatspkts65octetsto127octets_hi),
8968 8, STATS_FLAGS_PORT, "tx_65_to_127_byte_packets" },
8969 { STATS_OFFSET32(tx_stat_etherstatspkts128octetsto255octets_hi),
8970 8, STATS_FLAGS_PORT, "tx_128_to_255_byte_packets" },
8971 { STATS_OFFSET32(tx_stat_etherstatspkts256octetsto511octets_hi),
8972 8, STATS_FLAGS_PORT, "tx_256_to_511_byte_packets" },
8973 { STATS_OFFSET32(tx_stat_etherstatspkts512octetsto1023octets_hi),
8974 8, STATS_FLAGS_PORT, "tx_512_to_1023_byte_packets" },
8975 { STATS_OFFSET32(etherstatspkts1024octetsto1522octets_hi),
8976 8, STATS_FLAGS_PORT, "tx_1024_to_1522_byte_packets" },
8977 { STATS_OFFSET32(etherstatspktsover1522octets_hi),
8978 8, STATS_FLAGS_PORT, "tx_1523_to_9022_byte_packets" },
8979 /* 30 */{ STATS_OFFSET32(rx_stat_xonpauseframesreceived_hi),
8980 8, STATS_FLAGS_PORT, "rx_xon_frames" },
8981 { STATS_OFFSET32(rx_stat_xoffpauseframesreceived_hi),
8982 8, STATS_FLAGS_PORT, "rx_xoff_frames" },
8983 { STATS_OFFSET32(tx_stat_outxonsent_hi),
8984 8, STATS_FLAGS_PORT, "tx_xon_frames" },
8985 { STATS_OFFSET32(tx_stat_outxoffsent_hi),
8986 8, STATS_FLAGS_PORT, "tx_xoff_frames" },
8987 { STATS_OFFSET32(rx_stat_maccontrolframesreceived_hi),
8988 8, STATS_FLAGS_PORT, "rx_mac_ctrl_frames" },
8989 { STATS_OFFSET32(mac_filter_discard),
8990 4, STATS_FLAGS_PORT, "rx_filtered_packets" },
8991 { STATS_OFFSET32(no_buff_discard),
8992 4, STATS_FLAGS_FUNC, "rx_discards" },
8993 { STATS_OFFSET32(xxoverflow_discard),
8994 4, STATS_FLAGS_PORT, "rx_fw_discards" },
8995 { STATS_OFFSET32(brb_drop_hi),
8996 8, STATS_FLAGS_PORT, "brb_discard" },
8997 { STATS_OFFSET32(brb_truncate_hi),
8998 8, STATS_FLAGS_PORT, "brb_truncate" },
8999 /* 40 */{ STATS_OFFSET32(rx_err_discard_pkt),
9000 4, STATS_FLAGS_FUNC, "rx_phy_ip_err_discards"},
9001 { STATS_OFFSET32(rx_skb_alloc_failed),
9002 4, STATS_FLAGS_FUNC, "rx_skb_alloc_discard" },
9003 /* 42 */{ STATS_OFFSET32(hw_csum_err),
9004 4, STATS_FLAGS_FUNC, "rx_csum_offload_errors" }
9007 #define IS_NOT_E1HMF_STAT(bp, i) \
9008 (IS_E1HMF(bp) && (bnx2x_stats_arr[i].flags & STATS_FLAGS_PORT))
9010 static void bnx2x_get_strings(struct net_device *dev, u32 stringset, u8 *buf)
9012 struct bnx2x *bp = netdev_priv(dev);
9015 switch (stringset) {
9017 for (i = 0, j = 0; i < BNX2X_NUM_STATS; i++) {
9018 if (IS_NOT_E1HMF_STAT(bp, i))
9020 strcpy(buf + j*ETH_GSTRING_LEN,
9021 bnx2x_stats_arr[i].string);
9027 memcpy(buf, bnx2x_tests_str_arr, sizeof(bnx2x_tests_str_arr));
9032 static int bnx2x_get_stats_count(struct net_device *dev)
9034 struct bnx2x *bp = netdev_priv(dev);
9035 int i, num_stats = 0;
9037 for (i = 0; i < BNX2X_NUM_STATS; i++) {
9038 if (IS_NOT_E1HMF_STAT(bp, i))
9045 static void bnx2x_get_ethtool_stats(struct net_device *dev,
9046 struct ethtool_stats *stats, u64 *buf)
9048 struct bnx2x *bp = netdev_priv(dev);
9049 u32 *hw_stats = (u32 *)&bp->eth_stats;
9052 for (i = 0, j = 0; i < BNX2X_NUM_STATS; i++) {
9053 if (IS_NOT_E1HMF_STAT(bp, i))
9056 if (bnx2x_stats_arr[i].size == 0) {
9057 /* skip this counter */
9062 if (bnx2x_stats_arr[i].size == 4) {
9063 /* 4-byte counter */
9064 buf[j] = (u64) *(hw_stats + bnx2x_stats_arr[i].offset);
9068 /* 8-byte counter */
9069 buf[j] = HILO_U64(*(hw_stats + bnx2x_stats_arr[i].offset),
9070 *(hw_stats + bnx2x_stats_arr[i].offset + 1));
9075 static int bnx2x_phys_id(struct net_device *dev, u32 data)
9077 struct bnx2x *bp = netdev_priv(dev);
9078 int port = BP_PORT(bp);
9081 if (!netif_running(dev))
9090 for (i = 0; i < (data * 2); i++) {
9092 bnx2x_set_led(bp, port, LED_MODE_OPER, SPEED_1000,
9093 bp->link_params.hw_led_mode,
9094 bp->link_params.chip_id);
9096 bnx2x_set_led(bp, port, LED_MODE_OFF, 0,
9097 bp->link_params.hw_led_mode,
9098 bp->link_params.chip_id);
9100 msleep_interruptible(500);
9101 if (signal_pending(current))
9105 if (bp->link_vars.link_up)
9106 bnx2x_set_led(bp, port, LED_MODE_OPER,
9107 bp->link_vars.line_speed,
9108 bp->link_params.hw_led_mode,
9109 bp->link_params.chip_id);
9114 static struct ethtool_ops bnx2x_ethtool_ops = {
9115 .get_settings = bnx2x_get_settings,
9116 .set_settings = bnx2x_set_settings,
9117 .get_drvinfo = bnx2x_get_drvinfo,
9118 .get_wol = bnx2x_get_wol,
9119 .set_wol = bnx2x_set_wol,
9120 .get_msglevel = bnx2x_get_msglevel,
9121 .set_msglevel = bnx2x_set_msglevel,
9122 .nway_reset = bnx2x_nway_reset,
9123 .get_link = ethtool_op_get_link,
9124 .get_eeprom_len = bnx2x_get_eeprom_len,
9125 .get_eeprom = bnx2x_get_eeprom,
9126 .set_eeprom = bnx2x_set_eeprom,
9127 .get_coalesce = bnx2x_get_coalesce,
9128 .set_coalesce = bnx2x_set_coalesce,
9129 .get_ringparam = bnx2x_get_ringparam,
9130 .set_ringparam = bnx2x_set_ringparam,
9131 .get_pauseparam = bnx2x_get_pauseparam,
9132 .set_pauseparam = bnx2x_set_pauseparam,
9133 .get_rx_csum = bnx2x_get_rx_csum,
9134 .set_rx_csum = bnx2x_set_rx_csum,
9135 .get_tx_csum = ethtool_op_get_tx_csum,
9136 .set_tx_csum = ethtool_op_set_tx_hw_csum,
9137 .set_flags = bnx2x_set_flags,
9138 .get_flags = ethtool_op_get_flags,
9139 .get_sg = ethtool_op_get_sg,
9140 .set_sg = ethtool_op_set_sg,
9141 .get_tso = ethtool_op_get_tso,
9142 .set_tso = bnx2x_set_tso,
9143 .self_test_count = bnx2x_self_test_count,
9144 .self_test = bnx2x_self_test,
9145 .get_strings = bnx2x_get_strings,
9146 .phys_id = bnx2x_phys_id,
9147 .get_stats_count = bnx2x_get_stats_count,
9148 .get_ethtool_stats = bnx2x_get_ethtool_stats,
9151 /* end of ethtool_ops */
9153 /****************************************************************************
9154 * General service functions
9155 ****************************************************************************/
9157 static int bnx2x_set_power_state(struct bnx2x *bp, pci_power_t state)
9161 pci_read_config_word(bp->pdev, bp->pm_cap + PCI_PM_CTRL, &pmcsr);
9165 pci_write_config_word(bp->pdev, bp->pm_cap + PCI_PM_CTRL,
9166 ((pmcsr & ~PCI_PM_CTRL_STATE_MASK) |
9167 PCI_PM_CTRL_PME_STATUS));
9169 if (pmcsr & PCI_PM_CTRL_STATE_MASK)
9170 /* delay required during transition out of D3hot */
9175 pmcsr &= ~PCI_PM_CTRL_STATE_MASK;
9179 pmcsr |= PCI_PM_CTRL_PME_ENABLE;
9181 pci_write_config_word(bp->pdev, bp->pm_cap + PCI_PM_CTRL,
9184 /* No more memory access after this point until
9185 * device is brought back to D0.
9196 * net_device service functions
9199 static int bnx2x_poll(struct napi_struct *napi, int budget)
9201 struct bnx2x_fastpath *fp = container_of(napi, struct bnx2x_fastpath,
9203 struct bnx2x *bp = fp->bp;
9206 #ifdef BNX2X_STOP_ON_ERROR
9207 if (unlikely(bp->panic))
9211 prefetch(fp->tx_buf_ring[TX_BD(fp->tx_pkt_cons)].skb);
9212 prefetch(fp->rx_buf_ring[RX_BD(fp->rx_bd_cons)].skb);
9213 prefetch((char *)(fp->rx_buf_ring[RX_BD(fp->rx_bd_cons)].skb) + 256);
9215 bnx2x_update_fpsb_idx(fp);
9217 if (BNX2X_HAS_TX_WORK(fp))
9218 bnx2x_tx_int(fp, budget);
9220 if (BNX2X_HAS_RX_WORK(fp))
9221 work_done = bnx2x_rx_int(fp, budget);
9223 rmb(); /* BNX2X_HAS_WORK() reads the status block */
9225 /* must not complete if we consumed full budget */
9226 if ((work_done < budget) && !BNX2X_HAS_WORK(fp)) {
9228 #ifdef BNX2X_STOP_ON_ERROR
9231 netif_rx_complete(bp->dev, napi);
9233 bnx2x_ack_sb(bp, FP_SB_ID(fp), USTORM_ID,
9234 le16_to_cpu(fp->fp_u_idx), IGU_INT_NOP, 1);
9235 bnx2x_ack_sb(bp, FP_SB_ID(fp), CSTORM_ID,
9236 le16_to_cpu(fp->fp_c_idx), IGU_INT_ENABLE, 1);
9242 /* we split the first BD into headers and data BDs
9243 * to ease the pain of our fellow micocode engineers
9244 * we use one mapping for both BDs
9245 * So far this has only been observed to happen
9246 * in Other Operating Systems(TM)
9248 static noinline u16 bnx2x_tx_split(struct bnx2x *bp,
9249 struct bnx2x_fastpath *fp,
9250 struct eth_tx_bd **tx_bd, u16 hlen,
9251 u16 bd_prod, int nbd)
9253 struct eth_tx_bd *h_tx_bd = *tx_bd;
9254 struct eth_tx_bd *d_tx_bd;
9256 int old_len = le16_to_cpu(h_tx_bd->nbytes);
9258 /* first fix first BD */
9259 h_tx_bd->nbd = cpu_to_le16(nbd);
9260 h_tx_bd->nbytes = cpu_to_le16(hlen);
9262 DP(NETIF_MSG_TX_QUEUED, "TSO split header size is %d "
9263 "(%x:%x) nbd %d\n", h_tx_bd->nbytes, h_tx_bd->addr_hi,
9264 h_tx_bd->addr_lo, h_tx_bd->nbd);
9266 /* now get a new data BD
9267 * (after the pbd) and fill it */
9268 bd_prod = TX_BD(NEXT_TX_IDX(bd_prod));
9269 d_tx_bd = &fp->tx_desc_ring[bd_prod];
9271 mapping = HILO_U64(le32_to_cpu(h_tx_bd->addr_hi),
9272 le32_to_cpu(h_tx_bd->addr_lo)) + hlen;
9274 d_tx_bd->addr_hi = cpu_to_le32(U64_HI(mapping));
9275 d_tx_bd->addr_lo = cpu_to_le32(U64_LO(mapping));
9276 d_tx_bd->nbytes = cpu_to_le16(old_len - hlen);
9278 /* this marks the BD as one that has no individual mapping
9279 * the FW ignores this flag in a BD not marked start
9281 d_tx_bd->bd_flags.as_bitfield = ETH_TX_BD_FLAGS_SW_LSO;
9282 DP(NETIF_MSG_TX_QUEUED,
9283 "TSO split data size is %d (%x:%x)\n",
9284 d_tx_bd->nbytes, d_tx_bd->addr_hi, d_tx_bd->addr_lo);
9286 /* update tx_bd for marking the last BD flag */
9292 static inline u16 bnx2x_csum_fix(unsigned char *t_header, u16 csum, s8 fix)
9295 csum = (u16) ~csum_fold(csum_sub(csum,
9296 csum_partial(t_header - fix, fix, 0)));
9299 csum = (u16) ~csum_fold(csum_add(csum,
9300 csum_partial(t_header, -fix, 0)));
9302 return swab16(csum);
9305 static inline u32 bnx2x_xmit_type(struct bnx2x *bp, struct sk_buff *skb)
9309 if (skb->ip_summed != CHECKSUM_PARTIAL)
9313 if (skb->protocol == ntohs(ETH_P_IPV6)) {
9315 if (ipv6_hdr(skb)->nexthdr == IPPROTO_TCP)
9316 rc |= XMIT_CSUM_TCP;
9320 if (ip_hdr(skb)->protocol == IPPROTO_TCP)
9321 rc |= XMIT_CSUM_TCP;
9325 if (skb_shinfo(skb)->gso_type & SKB_GSO_TCPV4)
9328 else if (skb_shinfo(skb)->gso_type & SKB_GSO_TCPV6)
9334 /* check if packet requires linearization (packet is too fragmented) */
9335 static int bnx2x_pkt_req_lin(struct bnx2x *bp, struct sk_buff *skb,
9340 int first_bd_sz = 0;
9342 /* 3 = 1 (for linear data BD) + 2 (for PBD and last BD) */
9343 if (skb_shinfo(skb)->nr_frags >= (MAX_FETCH_BD - 3)) {
9345 if (xmit_type & XMIT_GSO) {
9346 unsigned short lso_mss = skb_shinfo(skb)->gso_size;
9347 /* Check if LSO packet needs to be copied:
9348 3 = 1 (for headers BD) + 2 (for PBD and last BD) */
9349 int wnd_size = MAX_FETCH_BD - 3;
9350 /* Number of widnows to check */
9351 int num_wnds = skb_shinfo(skb)->nr_frags - wnd_size;
9356 /* Headers length */
9357 hlen = (int)(skb_transport_header(skb) - skb->data) +
9360 /* Amount of data (w/o headers) on linear part of SKB*/
9361 first_bd_sz = skb_headlen(skb) - hlen;
9363 wnd_sum = first_bd_sz;
9365 /* Calculate the first sum - it's special */
9366 for (frag_idx = 0; frag_idx < wnd_size - 1; frag_idx++)
9368 skb_shinfo(skb)->frags[frag_idx].size;
9370 /* If there was data on linear skb data - check it */
9371 if (first_bd_sz > 0) {
9372 if (unlikely(wnd_sum < lso_mss)) {
9377 wnd_sum -= first_bd_sz;
9380 /* Others are easier: run through the frag list and
9381 check all windows */
9382 for (wnd_idx = 0; wnd_idx <= num_wnds; wnd_idx++) {
9384 skb_shinfo(skb)->frags[wnd_idx + wnd_size - 1].size;
9386 if (unlikely(wnd_sum < lso_mss)) {
9391 skb_shinfo(skb)->frags[wnd_idx].size;
9395 /* in non-LSO too fragmented packet should always
9402 if (unlikely(to_copy))
9403 DP(NETIF_MSG_TX_QUEUED,
9404 "Linearization IS REQUIRED for %s packet. "
9405 "num_frags %d hlen %d first_bd_sz %d\n",
9406 (xmit_type & XMIT_GSO) ? "LSO" : "non-LSO",
9407 skb_shinfo(skb)->nr_frags, hlen, first_bd_sz);
9412 /* called with netif_tx_lock
9413 * bnx2x_tx_int() runs without netif_tx_lock unless it needs to call
9414 * netif_wake_queue()
9416 static int bnx2x_start_xmit(struct sk_buff *skb, struct net_device *dev)
9418 struct bnx2x *bp = netdev_priv(dev);
9419 struct bnx2x_fastpath *fp;
9420 struct sw_tx_bd *tx_buf;
9421 struct eth_tx_bd *tx_bd;
9422 struct eth_tx_parse_bd *pbd = NULL;
9423 u16 pkt_prod, bd_prod;
9426 u32 xmit_type = bnx2x_xmit_type(bp, skb);
9427 int vlan_off = (bp->e1hov ? 4 : 0);
9431 #ifdef BNX2X_STOP_ON_ERROR
9432 if (unlikely(bp->panic))
9433 return NETDEV_TX_BUSY;
9436 fp_index = (smp_processor_id() % bp->num_queues);
9437 fp = &bp->fp[fp_index];
9439 if (unlikely(bnx2x_tx_avail(bp->fp) <
9440 (skb_shinfo(skb)->nr_frags + 3))) {
9441 bp->eth_stats.driver_xoff++,
9442 netif_stop_queue(dev);
9443 BNX2X_ERR("BUG! Tx ring full when queue awake!\n");
9444 return NETDEV_TX_BUSY;
9447 DP(NETIF_MSG_TX_QUEUED, "SKB: summed %x protocol %x protocol(%x,%x)"
9448 " gso type %x xmit_type %x\n",
9449 skb->ip_summed, skb->protocol, ipv6_hdr(skb)->nexthdr,
9450 ip_hdr(skb)->protocol, skb_shinfo(skb)->gso_type, xmit_type);
9452 /* First, check if we need to linearaize the skb
9453 (due to FW restrictions) */
9454 if (bnx2x_pkt_req_lin(bp, skb, xmit_type)) {
9455 /* Statistics of linearization */
9457 if (skb_linearize(skb) != 0) {
9458 DP(NETIF_MSG_TX_QUEUED, "SKB linearization failed - "
9459 "silently dropping this SKB\n");
9460 dev_kfree_skb_any(skb);
9461 return NETDEV_TX_OK;
9466 Please read carefully. First we use one BD which we mark as start,
9467 then for TSO or xsum we have a parsing info BD,
9468 and only then we have the rest of the TSO BDs.
9469 (don't forget to mark the last one as last,
9470 and to unmap only AFTER you write to the BD ...)
9471 And above all, all pdb sizes are in words - NOT DWORDS!
9474 pkt_prod = fp->tx_pkt_prod++;
9475 bd_prod = TX_BD(fp->tx_bd_prod);
9477 /* get a tx_buf and first BD */
9478 tx_buf = &fp->tx_buf_ring[TX_BD(pkt_prod)];
9479 tx_bd = &fp->tx_desc_ring[bd_prod];
9481 tx_bd->bd_flags.as_bitfield = ETH_TX_BD_FLAGS_START_BD;
9482 tx_bd->general_data = (UNICAST_ADDRESS <<
9483 ETH_TX_BD_ETH_ADDR_TYPE_SHIFT);
9484 tx_bd->general_data |= 1; /* header nbd */
9486 /* remember the first BD of the packet */
9487 tx_buf->first_bd = fp->tx_bd_prod;
9490 DP(NETIF_MSG_TX_QUEUED,
9491 "sending pkt %u @%p next_idx %u bd %u @%p\n",
9492 pkt_prod, tx_buf, fp->tx_pkt_prod, bd_prod, tx_bd);
9494 if ((bp->vlgrp != NULL) && vlan_tx_tag_present(skb)) {
9495 tx_bd->vlan = cpu_to_le16(vlan_tx_tag_get(skb));
9496 tx_bd->bd_flags.as_bitfield |= ETH_TX_BD_FLAGS_VLAN_TAG;
9499 tx_bd->vlan = cpu_to_le16(pkt_prod);
9503 /* turn on parsing and get a BD */
9504 bd_prod = TX_BD(NEXT_TX_IDX(bd_prod));
9505 pbd = (void *)&fp->tx_desc_ring[bd_prod];
9507 memset(pbd, 0, sizeof(struct eth_tx_parse_bd));
9510 if (xmit_type & XMIT_CSUM) {
9511 hlen = (skb_network_header(skb) - skb->data + vlan_off) / 2;
9513 /* for now NS flag is not used in Linux */
9514 pbd->global_data = (hlen |
9515 ((skb->protocol == ntohs(ETH_P_8021Q)) <<
9516 ETH_TX_PARSE_BD_LLC_SNAP_EN_SHIFT));
9518 pbd->ip_hlen = (skb_transport_header(skb) -
9519 skb_network_header(skb)) / 2;
9521 hlen += pbd->ip_hlen + tcp_hdrlen(skb) / 2;
9523 pbd->total_hlen = cpu_to_le16(hlen);
9524 hlen = hlen*2 - vlan_off;
9526 tx_bd->bd_flags.as_bitfield |= ETH_TX_BD_FLAGS_TCP_CSUM;
9528 if (xmit_type & XMIT_CSUM_V4)
9529 tx_bd->bd_flags.as_bitfield |=
9530 ETH_TX_BD_FLAGS_IP_CSUM;
9532 tx_bd->bd_flags.as_bitfield |= ETH_TX_BD_FLAGS_IPV6;
9534 if (xmit_type & XMIT_CSUM_TCP) {
9535 pbd->tcp_pseudo_csum = swab16(tcp_hdr(skb)->check);
9538 s8 fix = SKB_CS_OFF(skb); /* signed! */
9540 pbd->global_data |= ETH_TX_PARSE_BD_CS_ANY_FLG;
9541 pbd->cs_offset = fix / 2;
9543 DP(NETIF_MSG_TX_QUEUED,
9544 "hlen %d offset %d fix %d csum before fix %x\n",
9545 le16_to_cpu(pbd->total_hlen), pbd->cs_offset, fix,
9548 /* HW bug: fixup the CSUM */
9549 pbd->tcp_pseudo_csum =
9550 bnx2x_csum_fix(skb_transport_header(skb),
9553 DP(NETIF_MSG_TX_QUEUED, "csum after fix %x\n",
9554 pbd->tcp_pseudo_csum);
9558 mapping = pci_map_single(bp->pdev, skb->data,
9559 skb_headlen(skb), PCI_DMA_TODEVICE);
9561 tx_bd->addr_hi = cpu_to_le32(U64_HI(mapping));
9562 tx_bd->addr_lo = cpu_to_le32(U64_LO(mapping));
9563 nbd = skb_shinfo(skb)->nr_frags + ((pbd == NULL)? 1 : 2);
9564 tx_bd->nbd = cpu_to_le16(nbd);
9565 tx_bd->nbytes = cpu_to_le16(skb_headlen(skb));
9567 DP(NETIF_MSG_TX_QUEUED, "first bd @%p addr (%x:%x) nbd %d"
9568 " nbytes %d flags %x vlan %x\n",
9569 tx_bd, tx_bd->addr_hi, tx_bd->addr_lo, le16_to_cpu(tx_bd->nbd),
9570 le16_to_cpu(tx_bd->nbytes), tx_bd->bd_flags.as_bitfield,
9571 le16_to_cpu(tx_bd->vlan));
9573 if (xmit_type & XMIT_GSO) {
9575 DP(NETIF_MSG_TX_QUEUED,
9576 "TSO packet len %d hlen %d total len %d tso size %d\n",
9577 skb->len, hlen, skb_headlen(skb),
9578 skb_shinfo(skb)->gso_size);
9580 tx_bd->bd_flags.as_bitfield |= ETH_TX_BD_FLAGS_SW_LSO;
9582 if (unlikely(skb_headlen(skb) > hlen))
9583 bd_prod = bnx2x_tx_split(bp, fp, &tx_bd, hlen,
9586 pbd->lso_mss = cpu_to_le16(skb_shinfo(skb)->gso_size);
9587 pbd->tcp_send_seq = swab32(tcp_hdr(skb)->seq);
9588 pbd->tcp_flags = pbd_tcp_flags(skb);
9590 if (xmit_type & XMIT_GSO_V4) {
9591 pbd->ip_id = swab16(ip_hdr(skb)->id);
9592 pbd->tcp_pseudo_csum =
9593 swab16(~csum_tcpudp_magic(ip_hdr(skb)->saddr,
9595 0, IPPROTO_TCP, 0));
9598 pbd->tcp_pseudo_csum =
9599 swab16(~csum_ipv6_magic(&ipv6_hdr(skb)->saddr,
9600 &ipv6_hdr(skb)->daddr,
9601 0, IPPROTO_TCP, 0));
9603 pbd->global_data |= ETH_TX_PARSE_BD_PSEUDO_CS_WITHOUT_LEN;
9606 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
9607 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
9609 bd_prod = TX_BD(NEXT_TX_IDX(bd_prod));
9610 tx_bd = &fp->tx_desc_ring[bd_prod];
9612 mapping = pci_map_page(bp->pdev, frag->page, frag->page_offset,
9613 frag->size, PCI_DMA_TODEVICE);
9615 tx_bd->addr_hi = cpu_to_le32(U64_HI(mapping));
9616 tx_bd->addr_lo = cpu_to_le32(U64_LO(mapping));
9617 tx_bd->nbytes = cpu_to_le16(frag->size);
9618 tx_bd->vlan = cpu_to_le16(pkt_prod);
9619 tx_bd->bd_flags.as_bitfield = 0;
9621 DP(NETIF_MSG_TX_QUEUED,
9622 "frag %d bd @%p addr (%x:%x) nbytes %d flags %x\n",
9623 i, tx_bd, tx_bd->addr_hi, tx_bd->addr_lo,
9624 le16_to_cpu(tx_bd->nbytes), tx_bd->bd_flags.as_bitfield);
9627 /* now at last mark the BD as the last BD */
9628 tx_bd->bd_flags.as_bitfield |= ETH_TX_BD_FLAGS_END_BD;
9630 DP(NETIF_MSG_TX_QUEUED, "last bd @%p flags %x\n",
9631 tx_bd, tx_bd->bd_flags.as_bitfield);
9633 bd_prod = TX_BD(NEXT_TX_IDX(bd_prod));
9635 /* now send a tx doorbell, counting the next BD
9636 * if the packet contains or ends with it
9638 if (TX_BD_POFF(bd_prod) < nbd)
9642 DP(NETIF_MSG_TX_QUEUED,
9643 "PBD @%p ip_data %x ip_hlen %u ip_id %u lso_mss %u"
9644 " tcp_flags %x xsum %x seq %u hlen %u\n",
9645 pbd, pbd->global_data, pbd->ip_hlen, pbd->ip_id,
9646 pbd->lso_mss, pbd->tcp_flags, pbd->tcp_pseudo_csum,
9647 pbd->tcp_send_seq, le16_to_cpu(pbd->total_hlen));
9649 DP(NETIF_MSG_TX_QUEUED, "doorbell: nbd %d bd %u\n", nbd, bd_prod);
9651 fp->hw_tx_prods->bds_prod =
9652 cpu_to_le16(le16_to_cpu(fp->hw_tx_prods->bds_prod) + nbd);
9653 mb(); /* FW restriction: must not reorder writing nbd and packets */
9654 fp->hw_tx_prods->packets_prod =
9655 cpu_to_le32(le32_to_cpu(fp->hw_tx_prods->packets_prod) + 1);
9656 DOORBELL(bp, FP_IDX(fp), 0);
9660 fp->tx_bd_prod += nbd;
9661 dev->trans_start = jiffies;
9663 if (unlikely(bnx2x_tx_avail(fp) < MAX_SKB_FRAGS + 3)) {
9664 netif_stop_queue(dev);
9665 bp->eth_stats.driver_xoff++;
9666 if (bnx2x_tx_avail(fp) >= MAX_SKB_FRAGS + 3)
9667 netif_wake_queue(dev);
9671 return NETDEV_TX_OK;
9674 /* called with rtnl_lock */
9675 static int bnx2x_open(struct net_device *dev)
9677 struct bnx2x *bp = netdev_priv(dev);
9679 bnx2x_set_power_state(bp, PCI_D0);
9681 return bnx2x_nic_load(bp, LOAD_OPEN);
9684 /* called with rtnl_lock */
9685 static int bnx2x_close(struct net_device *dev)
9687 struct bnx2x *bp = netdev_priv(dev);
9689 /* Unload the driver, release IRQs */
9690 bnx2x_nic_unload(bp, UNLOAD_CLOSE);
9691 if (atomic_read(&bp->pdev->enable_cnt) == 1)
9692 if (!CHIP_REV_IS_SLOW(bp))
9693 bnx2x_set_power_state(bp, PCI_D3hot);
9698 /* called with netif_tx_lock from set_multicast */
9699 static void bnx2x_set_rx_mode(struct net_device *dev)
9701 struct bnx2x *bp = netdev_priv(dev);
9702 u32 rx_mode = BNX2X_RX_MODE_NORMAL;
9703 int port = BP_PORT(bp);
9705 if (bp->state != BNX2X_STATE_OPEN) {
9706 DP(NETIF_MSG_IFUP, "state is %x, returning\n", bp->state);
9710 DP(NETIF_MSG_IFUP, "dev->flags = %x\n", dev->flags);
9712 if (dev->flags & IFF_PROMISC)
9713 rx_mode = BNX2X_RX_MODE_PROMISC;
9715 else if ((dev->flags & IFF_ALLMULTI) ||
9716 ((dev->mc_count > BNX2X_MAX_MULTICAST) && CHIP_IS_E1(bp)))
9717 rx_mode = BNX2X_RX_MODE_ALLMULTI;
9719 else { /* some multicasts */
9720 if (CHIP_IS_E1(bp)) {
9722 struct dev_mc_list *mclist;
9723 struct mac_configuration_cmd *config =
9724 bnx2x_sp(bp, mcast_config);
9726 for (i = 0, mclist = dev->mc_list;
9727 mclist && (i < dev->mc_count);
9728 i++, mclist = mclist->next) {
9730 config->config_table[i].
9731 cam_entry.msb_mac_addr =
9732 swab16(*(u16 *)&mclist->dmi_addr[0]);
9733 config->config_table[i].
9734 cam_entry.middle_mac_addr =
9735 swab16(*(u16 *)&mclist->dmi_addr[2]);
9736 config->config_table[i].
9737 cam_entry.lsb_mac_addr =
9738 swab16(*(u16 *)&mclist->dmi_addr[4]);
9739 config->config_table[i].cam_entry.flags =
9741 config->config_table[i].
9742 target_table_entry.flags = 0;
9743 config->config_table[i].
9744 target_table_entry.client_id = 0;
9745 config->config_table[i].
9746 target_table_entry.vlan_id = 0;
9749 "setting MCAST[%d] (%04x:%04x:%04x)\n", i,
9750 config->config_table[i].
9751 cam_entry.msb_mac_addr,
9752 config->config_table[i].
9753 cam_entry.middle_mac_addr,
9754 config->config_table[i].
9755 cam_entry.lsb_mac_addr);
9757 old = config->hdr.length_6b;
9759 for (; i < old; i++) {
9760 if (CAM_IS_INVALID(config->
9762 i--; /* already invalidated */
9766 CAM_INVALIDATE(config->
9771 if (CHIP_REV_IS_SLOW(bp))
9772 offset = BNX2X_MAX_EMUL_MULTI*(1 + port);
9774 offset = BNX2X_MAX_MULTICAST*(1 + port);
9776 config->hdr.length_6b = i;
9777 config->hdr.offset = offset;
9778 config->hdr.client_id = BP_CL_ID(bp);
9779 config->hdr.reserved1 = 0;
9781 bnx2x_sp_post(bp, RAMROD_CMD_ID_ETH_SET_MAC, 0,
9782 U64_HI(bnx2x_sp_mapping(bp, mcast_config)),
9783 U64_LO(bnx2x_sp_mapping(bp, mcast_config)),
9786 /* Accept one or more multicasts */
9787 struct dev_mc_list *mclist;
9788 u32 mc_filter[MC_HASH_SIZE];
9789 u32 crc, bit, regidx;
9792 memset(mc_filter, 0, 4 * MC_HASH_SIZE);
9794 for (i = 0, mclist = dev->mc_list;
9795 mclist && (i < dev->mc_count);
9796 i++, mclist = mclist->next) {
9798 DP(NETIF_MSG_IFUP, "Adding mcast MAC: "
9799 "%02x:%02x:%02x:%02x:%02x:%02x\n",
9800 mclist->dmi_addr[0], mclist->dmi_addr[1],
9801 mclist->dmi_addr[2], mclist->dmi_addr[3],
9802 mclist->dmi_addr[4], mclist->dmi_addr[5]);
9804 crc = crc32c_le(0, mclist->dmi_addr, ETH_ALEN);
9805 bit = (crc >> 24) & 0xff;
9808 mc_filter[regidx] |= (1 << bit);
9811 for (i = 0; i < MC_HASH_SIZE; i++)
9812 REG_WR(bp, MC_HASH_OFFSET(bp, i),
9817 bp->rx_mode = rx_mode;
9818 bnx2x_set_storm_rx_mode(bp);
9821 /* called with rtnl_lock */
9822 static int bnx2x_change_mac_addr(struct net_device *dev, void *p)
9824 struct sockaddr *addr = p;
9825 struct bnx2x *bp = netdev_priv(dev);
9827 if (!is_valid_ether_addr((u8 *)(addr->sa_data)))
9830 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
9831 if (netif_running(dev)) {
9833 bnx2x_set_mac_addr_e1(bp);
9835 bnx2x_set_mac_addr_e1h(bp);
9841 /* called with rtnl_lock */
9842 static int bnx2x_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
9844 struct mii_ioctl_data *data = if_mii(ifr);
9845 struct bnx2x *bp = netdev_priv(dev);
9850 data->phy_id = bp->port.phy_addr;
9857 if (!netif_running(dev))
9860 mutex_lock(&bp->port.phy_mutex);
9861 err = bnx2x_cl45_read(bp, BP_PORT(bp), 0, bp->port.phy_addr,
9862 DEFAULT_PHY_DEV_ADDR,
9863 (data->reg_num & 0x1f), &mii_regval);
9864 data->val_out = mii_regval;
9865 mutex_unlock(&bp->port.phy_mutex);
9870 if (!capable(CAP_NET_ADMIN))
9873 if (!netif_running(dev))
9876 mutex_lock(&bp->port.phy_mutex);
9877 err = bnx2x_cl45_write(bp, BP_PORT(bp), 0, bp->port.phy_addr,
9878 DEFAULT_PHY_DEV_ADDR,
9879 (data->reg_num & 0x1f), data->val_in);
9880 mutex_unlock(&bp->port.phy_mutex);
9891 /* called with rtnl_lock */
9892 static int bnx2x_change_mtu(struct net_device *dev, int new_mtu)
9894 struct bnx2x *bp = netdev_priv(dev);
9897 if ((new_mtu > ETH_MAX_JUMBO_PACKET_SIZE) ||
9898 ((new_mtu + ETH_HLEN) < ETH_MIN_PACKET_SIZE))
9901 /* This does not race with packet allocation
9902 * because the actual alloc size is
9903 * only updated as part of load
9907 if (netif_running(dev)) {
9908 bnx2x_nic_unload(bp, UNLOAD_NORMAL);
9909 rc = bnx2x_nic_load(bp, LOAD_NORMAL);
9915 static void bnx2x_tx_timeout(struct net_device *dev)
9917 struct bnx2x *bp = netdev_priv(dev);
9919 #ifdef BNX2X_STOP_ON_ERROR
9923 /* This allows the netif to be shutdown gracefully before resetting */
9924 schedule_work(&bp->reset_task);
9928 /* called with rtnl_lock */
9929 static void bnx2x_vlan_rx_register(struct net_device *dev,
9930 struct vlan_group *vlgrp)
9932 struct bnx2x *bp = netdev_priv(dev);
9935 if (netif_running(dev))
9936 bnx2x_set_client_config(bp);
9941 #if defined(HAVE_POLL_CONTROLLER) || defined(CONFIG_NET_POLL_CONTROLLER)
9942 static void poll_bnx2x(struct net_device *dev)
9944 struct bnx2x *bp = netdev_priv(dev);
9946 disable_irq(bp->pdev->irq);
9947 bnx2x_interrupt(bp->pdev->irq, dev);
9948 enable_irq(bp->pdev->irq);
9952 static int __devinit bnx2x_init_dev(struct pci_dev *pdev,
9953 struct net_device *dev)
9958 SET_NETDEV_DEV(dev, &pdev->dev);
9959 bp = netdev_priv(dev);
9964 bp->func = PCI_FUNC(pdev->devfn);
9966 rc = pci_enable_device(pdev);
9968 printk(KERN_ERR PFX "Cannot enable PCI device, aborting\n");
9972 if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
9973 printk(KERN_ERR PFX "Cannot find PCI device base address,"
9976 goto err_out_disable;
9979 if (!(pci_resource_flags(pdev, 2) & IORESOURCE_MEM)) {
9980 printk(KERN_ERR PFX "Cannot find second PCI device"
9981 " base address, aborting\n");
9983 goto err_out_disable;
9986 if (atomic_read(&pdev->enable_cnt) == 1) {
9987 rc = pci_request_regions(pdev, DRV_MODULE_NAME);
9989 printk(KERN_ERR PFX "Cannot obtain PCI resources,"
9991 goto err_out_disable;
9994 pci_set_master(pdev);
9995 pci_save_state(pdev);
9998 bp->pm_cap = pci_find_capability(pdev, PCI_CAP_ID_PM);
9999 if (bp->pm_cap == 0) {
10000 printk(KERN_ERR PFX "Cannot find power management"
10001 " capability, aborting\n");
10003 goto err_out_release;
10006 bp->pcie_cap = pci_find_capability(pdev, PCI_CAP_ID_EXP);
10007 if (bp->pcie_cap == 0) {
10008 printk(KERN_ERR PFX "Cannot find PCI Express capability,"
10011 goto err_out_release;
10014 if (pci_set_dma_mask(pdev, DMA_64BIT_MASK) == 0) {
10015 bp->flags |= USING_DAC_FLAG;
10016 if (pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK) != 0) {
10017 printk(KERN_ERR PFX "pci_set_consistent_dma_mask"
10018 " failed, aborting\n");
10020 goto err_out_release;
10023 } else if (pci_set_dma_mask(pdev, DMA_32BIT_MASK) != 0) {
10024 printk(KERN_ERR PFX "System does not support DMA,"
10027 goto err_out_release;
10030 dev->mem_start = pci_resource_start(pdev, 0);
10031 dev->base_addr = dev->mem_start;
10032 dev->mem_end = pci_resource_end(pdev, 0);
10034 dev->irq = pdev->irq;
10036 bp->regview = ioremap_nocache(dev->base_addr,
10037 pci_resource_len(pdev, 0));
10038 if (!bp->regview) {
10039 printk(KERN_ERR PFX "Cannot map register space, aborting\n");
10041 goto err_out_release;
10044 bp->doorbells = ioremap_nocache(pci_resource_start(pdev, 2),
10045 min_t(u64, BNX2X_DB_SIZE,
10046 pci_resource_len(pdev, 2)));
10047 if (!bp->doorbells) {
10048 printk(KERN_ERR PFX "Cannot map doorbell space, aborting\n");
10050 goto err_out_unmap;
10053 bnx2x_set_power_state(bp, PCI_D0);
10055 /* clean indirect addresses */
10056 pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS,
10057 PCICFG_VENDOR_ID_OFFSET);
10058 REG_WR(bp, PXP2_REG_PGL_ADDR_88_F0 + BP_PORT(bp)*16, 0);
10059 REG_WR(bp, PXP2_REG_PGL_ADDR_8C_F0 + BP_PORT(bp)*16, 0);
10060 REG_WR(bp, PXP2_REG_PGL_ADDR_90_F0 + BP_PORT(bp)*16, 0);
10061 REG_WR(bp, PXP2_REG_PGL_ADDR_94_F0 + BP_PORT(bp)*16, 0);
10063 dev->hard_start_xmit = bnx2x_start_xmit;
10064 dev->watchdog_timeo = TX_TIMEOUT;
10066 dev->ethtool_ops = &bnx2x_ethtool_ops;
10067 dev->open = bnx2x_open;
10068 dev->stop = bnx2x_close;
10069 dev->set_multicast_list = bnx2x_set_rx_mode;
10070 dev->set_mac_address = bnx2x_change_mac_addr;
10071 dev->do_ioctl = bnx2x_ioctl;
10072 dev->change_mtu = bnx2x_change_mtu;
10073 dev->tx_timeout = bnx2x_tx_timeout;
10075 dev->vlan_rx_register = bnx2x_vlan_rx_register;
10077 #if defined(HAVE_POLL_CONTROLLER) || defined(CONFIG_NET_POLL_CONTROLLER)
10078 dev->poll_controller = poll_bnx2x;
10080 dev->features |= NETIF_F_SG;
10081 dev->features |= NETIF_F_HW_CSUM;
10082 if (bp->flags & USING_DAC_FLAG)
10083 dev->features |= NETIF_F_HIGHDMA;
10085 dev->features |= (NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX);
10087 dev->features |= (NETIF_F_TSO | NETIF_F_TSO_ECN);
10088 dev->features |= NETIF_F_TSO6;
10094 iounmap(bp->regview);
10095 bp->regview = NULL;
10097 if (bp->doorbells) {
10098 iounmap(bp->doorbells);
10099 bp->doorbells = NULL;
10103 if (atomic_read(&pdev->enable_cnt) == 1)
10104 pci_release_regions(pdev);
10107 pci_disable_device(pdev);
10108 pci_set_drvdata(pdev, NULL);
10114 static int __devinit bnx2x_get_pcie_width(struct bnx2x *bp)
10116 u32 val = REG_RD(bp, PCICFG_OFFSET + PCICFG_LINK_CONTROL);
10118 val = (val & PCICFG_LINK_WIDTH) >> PCICFG_LINK_WIDTH_SHIFT;
10122 /* return value of 1=2.5GHz 2=5GHz */
10123 static int __devinit bnx2x_get_pcie_speed(struct bnx2x *bp)
10125 u32 val = REG_RD(bp, PCICFG_OFFSET + PCICFG_LINK_CONTROL);
10127 val = (val & PCICFG_LINK_SPEED) >> PCICFG_LINK_SPEED_SHIFT;
10131 static int __devinit bnx2x_init_one(struct pci_dev *pdev,
10132 const struct pci_device_id *ent)
10134 static int version_printed;
10135 struct net_device *dev = NULL;
10138 DECLARE_MAC_BUF(mac);
10140 if (version_printed++ == 0)
10141 printk(KERN_INFO "%s", version);
10143 /* dev zeroed in init_etherdev */
10144 dev = alloc_etherdev(sizeof(*bp));
10146 printk(KERN_ERR PFX "Cannot allocate net device\n");
10150 netif_carrier_off(dev);
10152 bp = netdev_priv(dev);
10153 bp->msglevel = debug;
10155 rc = bnx2x_init_dev(pdev, dev);
10161 rc = register_netdev(dev);
10163 dev_err(&pdev->dev, "Cannot register net device\n");
10164 goto init_one_exit;
10167 pci_set_drvdata(pdev, dev);
10169 rc = bnx2x_init_bp(bp);
10171 unregister_netdev(dev);
10172 goto init_one_exit;
10175 bp->common.name = board_info[ent->driver_data].name;
10176 printk(KERN_INFO "%s: %s (%c%d) PCI-E x%d %s found at mem %lx,"
10177 " IRQ %d, ", dev->name, bp->common.name,
10178 (CHIP_REV(bp) >> 12) + 'A', (CHIP_METAL(bp) >> 4),
10179 bnx2x_get_pcie_width(bp),
10180 (bnx2x_get_pcie_speed(bp) == 2) ? "5GHz (Gen2)" : "2.5GHz",
10181 dev->base_addr, bp->pdev->irq);
10182 printk(KERN_CONT "node addr %s\n", print_mac(mac, dev->dev_addr));
10187 iounmap(bp->regview);
10190 iounmap(bp->doorbells);
10194 if (atomic_read(&pdev->enable_cnt) == 1)
10195 pci_release_regions(pdev);
10197 pci_disable_device(pdev);
10198 pci_set_drvdata(pdev, NULL);
10203 static void __devexit bnx2x_remove_one(struct pci_dev *pdev)
10205 struct net_device *dev = pci_get_drvdata(pdev);
10209 printk(KERN_ERR PFX "BAD net device from bnx2x_init_one\n");
10212 bp = netdev_priv(dev);
10214 unregister_netdev(dev);
10217 iounmap(bp->regview);
10220 iounmap(bp->doorbells);
10224 if (atomic_read(&pdev->enable_cnt) == 1)
10225 pci_release_regions(pdev);
10227 pci_disable_device(pdev);
10228 pci_set_drvdata(pdev, NULL);
10231 static int bnx2x_suspend(struct pci_dev *pdev, pm_message_t state)
10233 struct net_device *dev = pci_get_drvdata(pdev);
10237 printk(KERN_ERR PFX "BAD net device from bnx2x_init_one\n");
10240 bp = netdev_priv(dev);
10244 pci_save_state(pdev);
10246 if (!netif_running(dev)) {
10251 netif_device_detach(dev);
10253 bnx2x_nic_unload(bp, UNLOAD_CLOSE);
10255 bnx2x_set_power_state(bp, pci_choose_state(pdev, state));
10262 static int bnx2x_resume(struct pci_dev *pdev)
10264 struct net_device *dev = pci_get_drvdata(pdev);
10269 printk(KERN_ERR PFX "BAD net device from bnx2x_init_one\n");
10272 bp = netdev_priv(dev);
10276 pci_restore_state(pdev);
10278 if (!netif_running(dev)) {
10283 bnx2x_set_power_state(bp, PCI_D0);
10284 netif_device_attach(dev);
10286 rc = bnx2x_nic_load(bp, LOAD_OPEN);
10294 * bnx2x_io_error_detected - called when PCI error is detected
10295 * @pdev: Pointer to PCI device
10296 * @state: The current pci connection state
10298 * This function is called after a PCI bus error affecting
10299 * this device has been detected.
10301 static pci_ers_result_t bnx2x_io_error_detected(struct pci_dev *pdev,
10302 pci_channel_state_t state)
10304 struct net_device *dev = pci_get_drvdata(pdev);
10305 struct bnx2x *bp = netdev_priv(dev);
10309 netif_device_detach(dev);
10311 if (netif_running(dev))
10312 bnx2x_nic_unload(bp, UNLOAD_CLOSE);
10314 pci_disable_device(pdev);
10318 /* Request a slot reset */
10319 return PCI_ERS_RESULT_NEED_RESET;
10323 * bnx2x_io_slot_reset - called after the PCI bus has been reset
10324 * @pdev: Pointer to PCI device
10326 * Restart the card from scratch, as if from a cold-boot.
10328 static pci_ers_result_t bnx2x_io_slot_reset(struct pci_dev *pdev)
10330 struct net_device *dev = pci_get_drvdata(pdev);
10331 struct bnx2x *bp = netdev_priv(dev);
10335 if (pci_enable_device(pdev)) {
10336 dev_err(&pdev->dev,
10337 "Cannot re-enable PCI device after reset\n");
10339 return PCI_ERS_RESULT_DISCONNECT;
10342 pci_set_master(pdev);
10343 pci_restore_state(pdev);
10345 if (netif_running(dev))
10346 bnx2x_set_power_state(bp, PCI_D0);
10350 return PCI_ERS_RESULT_RECOVERED;
10354 * bnx2x_io_resume - called when traffic can start flowing again
10355 * @pdev: Pointer to PCI device
10357 * This callback is called when the error recovery driver tells us that
10358 * its OK to resume normal operation.
10360 static void bnx2x_io_resume(struct pci_dev *pdev)
10362 struct net_device *dev = pci_get_drvdata(pdev);
10363 struct bnx2x *bp = netdev_priv(dev);
10367 if (netif_running(dev))
10368 bnx2x_nic_load(bp, LOAD_OPEN);
10370 netif_device_attach(dev);
10375 static struct pci_error_handlers bnx2x_err_handler = {
10376 .error_detected = bnx2x_io_error_detected,
10377 .slot_reset = bnx2x_io_slot_reset,
10378 .resume = bnx2x_io_resume,
10381 static struct pci_driver bnx2x_pci_driver = {
10382 .name = DRV_MODULE_NAME,
10383 .id_table = bnx2x_pci_tbl,
10384 .probe = bnx2x_init_one,
10385 .remove = __devexit_p(bnx2x_remove_one),
10386 .suspend = bnx2x_suspend,
10387 .resume = bnx2x_resume,
10388 .err_handler = &bnx2x_err_handler,
10391 static int __init bnx2x_init(void)
10393 return pci_register_driver(&bnx2x_pci_driver);
10396 static void __exit bnx2x_cleanup(void)
10398 pci_unregister_driver(&bnx2x_pci_driver);
10401 module_init(bnx2x_init);
10402 module_exit(bnx2x_cleanup);