1 /* bnx2x_main.c: Broadcom Everest network driver.
3 * Copyright (c) 2007-2008 Broadcom Corporation
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation.
9 * Maintained by: Eilon Greenstein <eilong@broadcom.com>
10 * Written by: Eliezer Tamir
11 * Based on code from Michael Chan's bnx2 driver
12 * UDP CSUM errata workaround by Arik Gendelman
13 * Slowpath rework by Vladislav Zolotarov
14 * Statistics and Link management by Yitchak Gertner
18 #include <linux/module.h>
19 #include <linux/moduleparam.h>
20 #include <linux/kernel.h>
21 #include <linux/device.h> /* for dev_info() */
22 #include <linux/timer.h>
23 #include <linux/errno.h>
24 #include <linux/ioport.h>
25 #include <linux/slab.h>
26 #include <linux/vmalloc.h>
27 #include <linux/interrupt.h>
28 #include <linux/pci.h>
29 #include <linux/init.h>
30 #include <linux/netdevice.h>
31 #include <linux/etherdevice.h>
32 #include <linux/skbuff.h>
33 #include <linux/dma-mapping.h>
34 #include <linux/bitops.h>
35 #include <linux/irq.h>
36 #include <linux/delay.h>
37 #include <asm/byteorder.h>
38 #include <linux/time.h>
39 #include <linux/ethtool.h>
40 #include <linux/mii.h>
41 #ifdef NETIF_F_HW_VLAN_TX
42 #include <linux/if_vlan.h>
46 #include <net/checksum.h>
47 #include <linux/version.h>
48 #include <net/ip6_checksum.h>
49 #include <linux/workqueue.h>
50 #include <linux/crc32.h>
51 #include <linux/crc32c.h>
52 #include <linux/prefetch.h>
53 #include <linux/zlib.h>
56 #include "bnx2x_reg.h"
57 #include "bnx2x_fw_defs.h"
58 #include "bnx2x_hsi.h"
59 #include "bnx2x_link.h"
61 #include "bnx2x_init.h"
63 #define DRV_MODULE_VERSION "1.45.6"
64 #define DRV_MODULE_RELDATE "2008/06/23"
65 #define BNX2X_BC_VER 0x040200
67 /* Time in jiffies before concluding the transmitter is hung */
68 #define TX_TIMEOUT (5*HZ)
70 static char version[] __devinitdata =
71 "Broadcom NetXtreme II 5771x 10Gigabit Ethernet Driver "
72 DRV_MODULE_NAME " " DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")\n";
74 MODULE_AUTHOR("Eliezer Tamir");
75 MODULE_DESCRIPTION("Broadcom NetXtreme II BCM57710 Driver");
76 MODULE_LICENSE("GPL");
77 MODULE_VERSION(DRV_MODULE_VERSION);
79 static int disable_tpa;
83 static int load_count[3]; /* 0-common, 1-port0, 2-port1 */
86 module_param(disable_tpa, int, 0);
87 module_param(use_inta, int, 0);
88 module_param(poll, int, 0);
89 module_param(debug, int, 0);
90 MODULE_PARM_DESC(disable_tpa, "disable the TPA (LRO) feature");
91 MODULE_PARM_DESC(use_inta, "use INT#A instead of MSI-X");
92 MODULE_PARM_DESC(poll, "use polling (for debug)");
93 MODULE_PARM_DESC(debug, "default debug msglevel");
96 module_param(use_multi, int, 0);
97 MODULE_PARM_DESC(use_multi, "use per-CPU queues");
100 enum bnx2x_board_type {
106 /* indexed by board_type, above */
109 } board_info[] __devinitdata = {
110 { "Broadcom NetXtreme II BCM57710 XGb" },
111 { "Broadcom NetXtreme II BCM57711 XGb" },
112 { "Broadcom NetXtreme II BCM57711E XGb" }
116 static const struct pci_device_id bnx2x_pci_tbl[] = {
117 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_57710,
118 PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM57710 },
119 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_57711,
120 PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM57711 },
121 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_57711E,
122 PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM57711E },
126 MODULE_DEVICE_TABLE(pci, bnx2x_pci_tbl);
128 /****************************************************************************
129 * General service functions
130 ****************************************************************************/
133 * locking is done by mcp
135 static void bnx2x_reg_wr_ind(struct bnx2x *bp, u32 addr, u32 val)
137 pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS, addr);
138 pci_write_config_dword(bp->pdev, PCICFG_GRC_DATA, val);
139 pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS,
140 PCICFG_VENDOR_ID_OFFSET);
143 static u32 bnx2x_reg_rd_ind(struct bnx2x *bp, u32 addr)
147 pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS, addr);
148 pci_read_config_dword(bp->pdev, PCICFG_GRC_DATA, &val);
149 pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS,
150 PCICFG_VENDOR_ID_OFFSET);
155 static const u32 dmae_reg_go_c[] = {
156 DMAE_REG_GO_C0, DMAE_REG_GO_C1, DMAE_REG_GO_C2, DMAE_REG_GO_C3,
157 DMAE_REG_GO_C4, DMAE_REG_GO_C5, DMAE_REG_GO_C6, DMAE_REG_GO_C7,
158 DMAE_REG_GO_C8, DMAE_REG_GO_C9, DMAE_REG_GO_C10, DMAE_REG_GO_C11,
159 DMAE_REG_GO_C12, DMAE_REG_GO_C13, DMAE_REG_GO_C14, DMAE_REG_GO_C15
162 /* copy command into DMAE command memory and set DMAE command go */
163 static void bnx2x_post_dmae(struct bnx2x *bp, struct dmae_command *dmae,
169 cmd_offset = (DMAE_REG_CMD_MEM + sizeof(struct dmae_command) * idx);
170 for (i = 0; i < (sizeof(struct dmae_command)/4); i++) {
171 REG_WR(bp, cmd_offset + i*4, *(((u32 *)dmae) + i));
173 DP(BNX2X_MSG_OFF, "DMAE cmd[%d].%d (0x%08x) : 0x%08x\n",
174 idx, i, cmd_offset + i*4, *(((u32 *)dmae) + i));
176 REG_WR(bp, dmae_reg_go_c[idx], 1);
179 void bnx2x_write_dmae(struct bnx2x *bp, dma_addr_t dma_addr, u32 dst_addr,
182 struct dmae_command *dmae = &bp->init_dmae;
183 u32 *wb_comp = bnx2x_sp(bp, wb_comp);
186 if (!bp->dmae_ready) {
187 u32 *data = bnx2x_sp(bp, wb_data[0]);
189 DP(BNX2X_MSG_OFF, "DMAE is not ready (dst_addr %08x len32 %d)"
190 " using indirect\n", dst_addr, len32);
191 bnx2x_init_ind_wr(bp, dst_addr, data, len32);
195 mutex_lock(&bp->dmae_mutex);
197 memset(dmae, 0, sizeof(struct dmae_command));
199 dmae->opcode = (DMAE_CMD_SRC_PCI | DMAE_CMD_DST_GRC |
200 DMAE_CMD_C_DST_PCI | DMAE_CMD_C_ENABLE |
201 DMAE_CMD_SRC_RESET | DMAE_CMD_DST_RESET |
203 DMAE_CMD_ENDIANITY_B_DW_SWAP |
205 DMAE_CMD_ENDIANITY_DW_SWAP |
207 (BP_PORT(bp) ? DMAE_CMD_PORT_1 : DMAE_CMD_PORT_0) |
208 (BP_E1HVN(bp) << DMAE_CMD_E1HVN_SHIFT));
209 dmae->src_addr_lo = U64_LO(dma_addr);
210 dmae->src_addr_hi = U64_HI(dma_addr);
211 dmae->dst_addr_lo = dst_addr >> 2;
212 dmae->dst_addr_hi = 0;
214 dmae->comp_addr_lo = U64_LO(bnx2x_sp_mapping(bp, wb_comp));
215 dmae->comp_addr_hi = U64_HI(bnx2x_sp_mapping(bp, wb_comp));
216 dmae->comp_val = DMAE_COMP_VAL;
218 DP(BNX2X_MSG_OFF, "dmae: opcode 0x%08x\n"
219 DP_LEVEL "src_addr [%x:%08x] len [%d *4] "
220 "dst_addr [%x:%08x (%08x)]\n"
221 DP_LEVEL "comp_addr [%x:%08x] comp_val 0x%08x\n",
222 dmae->opcode, dmae->src_addr_hi, dmae->src_addr_lo,
223 dmae->len, dmae->dst_addr_hi, dmae->dst_addr_lo, dst_addr,
224 dmae->comp_addr_hi, dmae->comp_addr_lo, dmae->comp_val);
225 DP(BNX2X_MSG_OFF, "data [0x%08x 0x%08x 0x%08x 0x%08x]\n",
226 bp->slowpath->wb_data[0], bp->slowpath->wb_data[1],
227 bp->slowpath->wb_data[2], bp->slowpath->wb_data[3]);
231 bnx2x_post_dmae(bp, dmae, INIT_DMAE_C(bp));
235 while (*wb_comp != DMAE_COMP_VAL) {
236 DP(BNX2X_MSG_OFF, "wb_comp 0x%08x\n", *wb_comp);
239 BNX2X_ERR("dmae timeout!\n");
243 /* adjust delay for emulation/FPGA */
244 if (CHIP_REV_IS_SLOW(bp))
250 mutex_unlock(&bp->dmae_mutex);
253 void bnx2x_read_dmae(struct bnx2x *bp, u32 src_addr, u32 len32)
255 struct dmae_command *dmae = &bp->init_dmae;
256 u32 *wb_comp = bnx2x_sp(bp, wb_comp);
259 if (!bp->dmae_ready) {
260 u32 *data = bnx2x_sp(bp, wb_data[0]);
263 DP(BNX2X_MSG_OFF, "DMAE is not ready (src_addr %08x len32 %d)"
264 " using indirect\n", src_addr, len32);
265 for (i = 0; i < len32; i++)
266 data[i] = bnx2x_reg_rd_ind(bp, src_addr + i*4);
270 mutex_lock(&bp->dmae_mutex);
272 memset(bnx2x_sp(bp, wb_data[0]), 0, sizeof(u32) * 4);
273 memset(dmae, 0, sizeof(struct dmae_command));
275 dmae->opcode = (DMAE_CMD_SRC_GRC | DMAE_CMD_DST_PCI |
276 DMAE_CMD_C_DST_PCI | DMAE_CMD_C_ENABLE |
277 DMAE_CMD_SRC_RESET | DMAE_CMD_DST_RESET |
279 DMAE_CMD_ENDIANITY_B_DW_SWAP |
281 DMAE_CMD_ENDIANITY_DW_SWAP |
283 (BP_PORT(bp) ? DMAE_CMD_PORT_1 : DMAE_CMD_PORT_0) |
284 (BP_E1HVN(bp) << DMAE_CMD_E1HVN_SHIFT));
285 dmae->src_addr_lo = src_addr >> 2;
286 dmae->src_addr_hi = 0;
287 dmae->dst_addr_lo = U64_LO(bnx2x_sp_mapping(bp, wb_data));
288 dmae->dst_addr_hi = U64_HI(bnx2x_sp_mapping(bp, wb_data));
290 dmae->comp_addr_lo = U64_LO(bnx2x_sp_mapping(bp, wb_comp));
291 dmae->comp_addr_hi = U64_HI(bnx2x_sp_mapping(bp, wb_comp));
292 dmae->comp_val = DMAE_COMP_VAL;
294 DP(BNX2X_MSG_OFF, "dmae: opcode 0x%08x\n"
295 DP_LEVEL "src_addr [%x:%08x] len [%d *4] "
296 "dst_addr [%x:%08x (%08x)]\n"
297 DP_LEVEL "comp_addr [%x:%08x] comp_val 0x%08x\n",
298 dmae->opcode, dmae->src_addr_hi, dmae->src_addr_lo,
299 dmae->len, dmae->dst_addr_hi, dmae->dst_addr_lo, src_addr,
300 dmae->comp_addr_hi, dmae->comp_addr_lo, dmae->comp_val);
304 bnx2x_post_dmae(bp, dmae, INIT_DMAE_C(bp));
308 while (*wb_comp != DMAE_COMP_VAL) {
311 BNX2X_ERR("dmae timeout!\n");
315 /* adjust delay for emulation/FPGA */
316 if (CHIP_REV_IS_SLOW(bp))
321 DP(BNX2X_MSG_OFF, "data [0x%08x 0x%08x 0x%08x 0x%08x]\n",
322 bp->slowpath->wb_data[0], bp->slowpath->wb_data[1],
323 bp->slowpath->wb_data[2], bp->slowpath->wb_data[3]);
325 mutex_unlock(&bp->dmae_mutex);
328 /* used only for slowpath so not inlined */
329 static void bnx2x_wb_wr(struct bnx2x *bp, int reg, u32 val_hi, u32 val_lo)
333 wb_write[0] = val_hi;
334 wb_write[1] = val_lo;
335 REG_WR_DMAE(bp, reg, wb_write, 2);
339 static u64 bnx2x_wb_rd(struct bnx2x *bp, int reg)
343 REG_RD_DMAE(bp, reg, wb_data, 2);
345 return HILO_U64(wb_data[0], wb_data[1]);
349 static int bnx2x_mc_assert(struct bnx2x *bp)
353 u32 row0, row1, row2, row3;
356 last_idx = REG_RD8(bp, BAR_XSTRORM_INTMEM +
357 XSTORM_ASSERT_LIST_INDEX_OFFSET);
359 BNX2X_ERR("XSTORM_ASSERT_LIST_INDEX 0x%x\n", last_idx);
361 /* print the asserts */
362 for (i = 0; i < STROM_ASSERT_ARRAY_SIZE; i++) {
364 row0 = REG_RD(bp, BAR_XSTRORM_INTMEM +
365 XSTORM_ASSERT_LIST_OFFSET(i));
366 row1 = REG_RD(bp, BAR_XSTRORM_INTMEM +
367 XSTORM_ASSERT_LIST_OFFSET(i) + 4);
368 row2 = REG_RD(bp, BAR_XSTRORM_INTMEM +
369 XSTORM_ASSERT_LIST_OFFSET(i) + 8);
370 row3 = REG_RD(bp, BAR_XSTRORM_INTMEM +
371 XSTORM_ASSERT_LIST_OFFSET(i) + 12);
373 if (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) {
374 BNX2X_ERR("XSTORM_ASSERT_INDEX 0x%x = 0x%08x"
375 " 0x%08x 0x%08x 0x%08x\n",
376 i, row3, row2, row1, row0);
384 last_idx = REG_RD8(bp, BAR_TSTRORM_INTMEM +
385 TSTORM_ASSERT_LIST_INDEX_OFFSET);
387 BNX2X_ERR("TSTORM_ASSERT_LIST_INDEX 0x%x\n", last_idx);
389 /* print the asserts */
390 for (i = 0; i < STROM_ASSERT_ARRAY_SIZE; i++) {
392 row0 = REG_RD(bp, BAR_TSTRORM_INTMEM +
393 TSTORM_ASSERT_LIST_OFFSET(i));
394 row1 = REG_RD(bp, BAR_TSTRORM_INTMEM +
395 TSTORM_ASSERT_LIST_OFFSET(i) + 4);
396 row2 = REG_RD(bp, BAR_TSTRORM_INTMEM +
397 TSTORM_ASSERT_LIST_OFFSET(i) + 8);
398 row3 = REG_RD(bp, BAR_TSTRORM_INTMEM +
399 TSTORM_ASSERT_LIST_OFFSET(i) + 12);
401 if (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) {
402 BNX2X_ERR("TSTORM_ASSERT_INDEX 0x%x = 0x%08x"
403 " 0x%08x 0x%08x 0x%08x\n",
404 i, row3, row2, row1, row0);
412 last_idx = REG_RD8(bp, BAR_CSTRORM_INTMEM +
413 CSTORM_ASSERT_LIST_INDEX_OFFSET);
415 BNX2X_ERR("CSTORM_ASSERT_LIST_INDEX 0x%x\n", last_idx);
417 /* print the asserts */
418 for (i = 0; i < STROM_ASSERT_ARRAY_SIZE; i++) {
420 row0 = REG_RD(bp, BAR_CSTRORM_INTMEM +
421 CSTORM_ASSERT_LIST_OFFSET(i));
422 row1 = REG_RD(bp, BAR_CSTRORM_INTMEM +
423 CSTORM_ASSERT_LIST_OFFSET(i) + 4);
424 row2 = REG_RD(bp, BAR_CSTRORM_INTMEM +
425 CSTORM_ASSERT_LIST_OFFSET(i) + 8);
426 row3 = REG_RD(bp, BAR_CSTRORM_INTMEM +
427 CSTORM_ASSERT_LIST_OFFSET(i) + 12);
429 if (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) {
430 BNX2X_ERR("CSTORM_ASSERT_INDEX 0x%x = 0x%08x"
431 " 0x%08x 0x%08x 0x%08x\n",
432 i, row3, row2, row1, row0);
440 last_idx = REG_RD8(bp, BAR_USTRORM_INTMEM +
441 USTORM_ASSERT_LIST_INDEX_OFFSET);
443 BNX2X_ERR("USTORM_ASSERT_LIST_INDEX 0x%x\n", last_idx);
445 /* print the asserts */
446 for (i = 0; i < STROM_ASSERT_ARRAY_SIZE; i++) {
448 row0 = REG_RD(bp, BAR_USTRORM_INTMEM +
449 USTORM_ASSERT_LIST_OFFSET(i));
450 row1 = REG_RD(bp, BAR_USTRORM_INTMEM +
451 USTORM_ASSERT_LIST_OFFSET(i) + 4);
452 row2 = REG_RD(bp, BAR_USTRORM_INTMEM +
453 USTORM_ASSERT_LIST_OFFSET(i) + 8);
454 row3 = REG_RD(bp, BAR_USTRORM_INTMEM +
455 USTORM_ASSERT_LIST_OFFSET(i) + 12);
457 if (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) {
458 BNX2X_ERR("USTORM_ASSERT_INDEX 0x%x = 0x%08x"
459 " 0x%08x 0x%08x 0x%08x\n",
460 i, row3, row2, row1, row0);
470 static void bnx2x_fw_dump(struct bnx2x *bp)
476 mark = REG_RD(bp, MCP_REG_MCPR_SCRATCH + 0xf104);
477 mark = ((mark + 0x3) & ~0x3);
478 printk(KERN_ERR PFX "begin fw dump (mark 0x%x)\n" KERN_ERR, mark);
480 for (offset = mark - 0x08000000; offset <= 0xF900; offset += 0x8*4) {
481 for (word = 0; word < 8; word++)
482 data[word] = htonl(REG_RD(bp, MCP_REG_MCPR_SCRATCH +
485 printk(KERN_CONT "%s", (char *)data);
487 for (offset = 0xF108; offset <= mark - 0x08000000; offset += 0x8*4) {
488 for (word = 0; word < 8; word++)
489 data[word] = htonl(REG_RD(bp, MCP_REG_MCPR_SCRATCH +
492 printk(KERN_CONT "%s", (char *)data);
494 printk("\n" KERN_ERR PFX "end of fw dump\n");
497 static void bnx2x_panic_dump(struct bnx2x *bp)
502 bp->stats_state = STATS_STATE_DISABLED;
503 DP(BNX2X_MSG_STATS, "stats_state - DISABLED\n");
505 BNX2X_ERR("begin crash dump -----------------\n");
507 for_each_queue(bp, i) {
508 struct bnx2x_fastpath *fp = &bp->fp[i];
509 struct eth_tx_db_data *hw_prods = fp->hw_tx_prods;
511 BNX2X_ERR("queue[%d]: tx_pkt_prod(%x) tx_pkt_cons(%x)"
512 " tx_bd_prod(%x) tx_bd_cons(%x) *tx_cons_sb(%x)\n",
513 i, fp->tx_pkt_prod, fp->tx_pkt_cons, fp->tx_bd_prod,
514 fp->tx_bd_cons, le16_to_cpu(*fp->tx_cons_sb));
515 BNX2X_ERR(" rx_bd_prod(%x) rx_bd_cons(%x)"
516 " *rx_bd_cons_sb(%x) rx_comp_prod(%x)"
517 " rx_comp_cons(%x) *rx_cons_sb(%x)\n",
518 fp->rx_bd_prod, fp->rx_bd_cons,
519 le16_to_cpu(*fp->rx_bd_cons_sb), fp->rx_comp_prod,
520 fp->rx_comp_cons, le16_to_cpu(*fp->rx_cons_sb));
521 BNX2X_ERR(" rx_sge_prod(%x) last_max_sge(%x)"
522 " fp_c_idx(%x) *sb_c_idx(%x) fp_u_idx(%x)"
523 " *sb_u_idx(%x) bd data(%x,%x)\n",
524 fp->rx_sge_prod, fp->last_max_sge, fp->fp_c_idx,
525 fp->status_blk->c_status_block.status_block_index,
527 fp->status_blk->u_status_block.status_block_index,
528 hw_prods->packets_prod, hw_prods->bds_prod);
530 start = TX_BD(le16_to_cpu(*fp->tx_cons_sb) - 10);
531 end = TX_BD(le16_to_cpu(*fp->tx_cons_sb) + 245);
532 for (j = start; j < end; j++) {
533 struct sw_tx_bd *sw_bd = &fp->tx_buf_ring[j];
535 BNX2X_ERR("packet[%x]=[%p,%x]\n", j,
536 sw_bd->skb, sw_bd->first_bd);
539 start = TX_BD(fp->tx_bd_cons - 10);
540 end = TX_BD(fp->tx_bd_cons + 254);
541 for (j = start; j < end; j++) {
542 u32 *tx_bd = (u32 *)&fp->tx_desc_ring[j];
544 BNX2X_ERR("tx_bd[%x]=[%x:%x:%x:%x]\n",
545 j, tx_bd[0], tx_bd[1], tx_bd[2], tx_bd[3]);
548 start = RX_BD(le16_to_cpu(*fp->rx_cons_sb) - 10);
549 end = RX_BD(le16_to_cpu(*fp->rx_cons_sb) + 503);
550 for (j = start; j < end; j++) {
551 u32 *rx_bd = (u32 *)&fp->rx_desc_ring[j];
552 struct sw_rx_bd *sw_bd = &fp->rx_buf_ring[j];
554 BNX2X_ERR("rx_bd[%x]=[%x:%x] sw_bd=[%p]\n",
555 j, rx_bd[1], rx_bd[0], sw_bd->skb);
559 end = RX_SGE_CNT*NUM_RX_SGE_PAGES;
560 for (j = start; j < end; j++) {
561 u32 *rx_sge = (u32 *)&fp->rx_sge_ring[j];
562 struct sw_rx_page *sw_page = &fp->rx_page_ring[j];
564 BNX2X_ERR("rx_sge[%x]=[%x:%x] sw_page=[%p]\n",
565 j, rx_sge[1], rx_sge[0], sw_page->page);
568 start = RCQ_BD(fp->rx_comp_cons - 10);
569 end = RCQ_BD(fp->rx_comp_cons + 503);
570 for (j = start; j < end; j++) {
571 u32 *cqe = (u32 *)&fp->rx_comp_ring[j];
573 BNX2X_ERR("cqe[%x]=[%x:%x:%x:%x]\n",
574 j, cqe[0], cqe[1], cqe[2], cqe[3]);
578 BNX2X_ERR("def_c_idx(%u) def_u_idx(%u) def_x_idx(%u)"
579 " def_t_idx(%u) def_att_idx(%u) attn_state(%u)"
580 " spq_prod_idx(%u)\n",
581 bp->def_c_idx, bp->def_u_idx, bp->def_x_idx, bp->def_t_idx,
582 bp->def_att_idx, bp->attn_state, bp->spq_prod_idx);
586 BNX2X_ERR("end crash dump -----------------\n");
589 static void bnx2x_int_enable(struct bnx2x *bp)
591 int port = BP_PORT(bp);
592 u32 addr = port ? HC_REG_CONFIG_1 : HC_REG_CONFIG_0;
593 u32 val = REG_RD(bp, addr);
594 int msix = (bp->flags & USING_MSIX_FLAG) ? 1 : 0;
597 val &= ~HC_CONFIG_0_REG_SINGLE_ISR_EN_0;
598 val |= (HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |
599 HC_CONFIG_0_REG_ATTN_BIT_EN_0);
601 val |= (HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
602 HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |
603 HC_CONFIG_0_REG_INT_LINE_EN_0 |
604 HC_CONFIG_0_REG_ATTN_BIT_EN_0);
606 DP(NETIF_MSG_INTR, "write %x to HC %d (addr 0x%x) MSI-X %d\n",
607 val, port, addr, msix);
609 REG_WR(bp, addr, val);
611 val &= ~HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0;
614 DP(NETIF_MSG_INTR, "write %x to HC %d (addr 0x%x) MSI-X %d\n",
615 val, port, addr, msix);
617 REG_WR(bp, addr, val);
619 if (CHIP_IS_E1H(bp)) {
620 /* init leading/trailing edge */
622 val = (0xfe0f | (1 << (BP_E1HVN(bp) + 4)));
624 /* enable nig attention */
629 REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, val);
630 REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, val);
634 static void bnx2x_int_disable(struct bnx2x *bp)
636 int port = BP_PORT(bp);
637 u32 addr = port ? HC_REG_CONFIG_1 : HC_REG_CONFIG_0;
638 u32 val = REG_RD(bp, addr);
640 val &= ~(HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
641 HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |
642 HC_CONFIG_0_REG_INT_LINE_EN_0 |
643 HC_CONFIG_0_REG_ATTN_BIT_EN_0);
645 DP(NETIF_MSG_INTR, "write %x to HC %d (addr 0x%x)\n",
648 REG_WR(bp, addr, val);
649 if (REG_RD(bp, addr) != val)
650 BNX2X_ERR("BUG! proper val not read from IGU!\n");
653 static void bnx2x_int_disable_sync(struct bnx2x *bp)
655 int msix = (bp->flags & USING_MSIX_FLAG) ? 1 : 0;
658 /* disable interrupt handling */
659 atomic_inc(&bp->intr_sem);
660 /* prevent the HW from sending interrupts */
661 bnx2x_int_disable(bp);
663 /* make sure all ISRs are done */
665 for_each_queue(bp, i)
666 synchronize_irq(bp->msix_table[i].vector);
668 /* one more for the Slow Path IRQ */
669 synchronize_irq(bp->msix_table[i].vector);
671 synchronize_irq(bp->pdev->irq);
673 /* make sure sp_task is not running */
674 cancel_work_sync(&bp->sp_task);
680 * General service functions
683 static inline void bnx2x_ack_sb(struct bnx2x *bp, u8 sb_id,
684 u8 storm, u16 index, u8 op, u8 update)
686 u32 hc_addr = (HC_REG_COMMAND_REG + BP_PORT(bp)*32 +
687 COMMAND_REG_INT_ACK);
688 struct igu_ack_register igu_ack;
690 igu_ack.status_block_index = index;
691 igu_ack.sb_id_and_flags =
692 ((sb_id << IGU_ACK_REGISTER_STATUS_BLOCK_ID_SHIFT) |
693 (storm << IGU_ACK_REGISTER_STORM_ID_SHIFT) |
694 (update << IGU_ACK_REGISTER_UPDATE_INDEX_SHIFT) |
695 (op << IGU_ACK_REGISTER_INTERRUPT_MODE_SHIFT));
697 DP(BNX2X_MSG_OFF, "write 0x%08x to HC addr 0x%x\n",
698 (*(u32 *)&igu_ack), hc_addr);
699 REG_WR(bp, hc_addr, (*(u32 *)&igu_ack));
702 static inline u16 bnx2x_update_fpsb_idx(struct bnx2x_fastpath *fp)
704 struct host_status_block *fpsb = fp->status_blk;
707 barrier(); /* status block is written to by the chip */
708 if (fp->fp_c_idx != fpsb->c_status_block.status_block_index) {
709 fp->fp_c_idx = fpsb->c_status_block.status_block_index;
712 if (fp->fp_u_idx != fpsb->u_status_block.status_block_index) {
713 fp->fp_u_idx = fpsb->u_status_block.status_block_index;
719 static u16 bnx2x_ack_int(struct bnx2x *bp)
721 u32 hc_addr = (HC_REG_COMMAND_REG + BP_PORT(bp)*32 +
722 COMMAND_REG_SIMD_MASK);
723 u32 result = REG_RD(bp, hc_addr);
725 DP(BNX2X_MSG_OFF, "read 0x%08x from HC addr 0x%x\n",
733 * fast path service functions
736 /* free skb in the packet ring at pos idx
737 * return idx of last bd freed
739 static u16 bnx2x_free_tx_pkt(struct bnx2x *bp, struct bnx2x_fastpath *fp,
742 struct sw_tx_bd *tx_buf = &fp->tx_buf_ring[idx];
743 struct eth_tx_bd *tx_bd;
744 struct sk_buff *skb = tx_buf->skb;
745 u16 bd_idx = TX_BD(tx_buf->first_bd), new_cons;
748 DP(BNX2X_MSG_OFF, "pkt_idx %d buff @(%p)->skb %p\n",
752 DP(BNX2X_MSG_OFF, "free bd_idx %d\n", bd_idx);
753 tx_bd = &fp->tx_desc_ring[bd_idx];
754 pci_unmap_single(bp->pdev, BD_UNMAP_ADDR(tx_bd),
755 BD_UNMAP_LEN(tx_bd), PCI_DMA_TODEVICE);
757 nbd = le16_to_cpu(tx_bd->nbd) - 1;
758 new_cons = nbd + tx_buf->first_bd;
759 #ifdef BNX2X_STOP_ON_ERROR
760 if (nbd > (MAX_SKB_FRAGS + 2)) {
761 BNX2X_ERR("BAD nbd!\n");
766 /* Skip a parse bd and the TSO split header bd
767 since they have no mapping */
769 bd_idx = TX_BD(NEXT_TX_IDX(bd_idx));
771 if (tx_bd->bd_flags.as_bitfield & (ETH_TX_BD_FLAGS_IP_CSUM |
772 ETH_TX_BD_FLAGS_TCP_CSUM |
773 ETH_TX_BD_FLAGS_SW_LSO)) {
775 bd_idx = TX_BD(NEXT_TX_IDX(bd_idx));
776 tx_bd = &fp->tx_desc_ring[bd_idx];
777 /* is this a TSO split header bd? */
778 if (tx_bd->bd_flags.as_bitfield & ETH_TX_BD_FLAGS_SW_LSO) {
780 bd_idx = TX_BD(NEXT_TX_IDX(bd_idx));
787 DP(BNX2X_MSG_OFF, "free frag bd_idx %d\n", bd_idx);
788 tx_bd = &fp->tx_desc_ring[bd_idx];
789 pci_unmap_page(bp->pdev, BD_UNMAP_ADDR(tx_bd),
790 BD_UNMAP_LEN(tx_bd), PCI_DMA_TODEVICE);
792 bd_idx = TX_BD(NEXT_TX_IDX(bd_idx));
798 tx_buf->first_bd = 0;
804 static inline u16 bnx2x_tx_avail(struct bnx2x_fastpath *fp)
810 barrier(); /* Tell compiler that prod and cons can change */
811 prod = fp->tx_bd_prod;
812 cons = fp->tx_bd_cons;
814 /* NUM_TX_RINGS = number of "next-page" entries
815 It will be used as a threshold */
816 used = SUB_S16(prod, cons) + (s16)NUM_TX_RINGS;
818 #ifdef BNX2X_STOP_ON_ERROR
820 WARN_ON(used > fp->bp->tx_ring_size);
821 WARN_ON((fp->bp->tx_ring_size - used) > MAX_TX_AVAIL);
824 return (s16)(fp->bp->tx_ring_size) - used;
827 static void bnx2x_tx_int(struct bnx2x_fastpath *fp, int work)
829 struct bnx2x *bp = fp->bp;
830 u16 hw_cons, sw_cons, bd_cons = fp->tx_bd_cons;
833 #ifdef BNX2X_STOP_ON_ERROR
834 if (unlikely(bp->panic))
838 hw_cons = le16_to_cpu(*fp->tx_cons_sb);
839 sw_cons = fp->tx_pkt_cons;
841 while (sw_cons != hw_cons) {
844 pkt_cons = TX_BD(sw_cons);
846 /* prefetch(bp->tx_buf_ring[pkt_cons].skb); */
848 DP(NETIF_MSG_TX_DONE, "hw_cons %u sw_cons %u pkt_cons %u\n",
849 hw_cons, sw_cons, pkt_cons);
851 /* if (NEXT_TX_IDX(sw_cons) != hw_cons) {
853 prefetch(fp->tx_buf_ring[NEXT_TX_IDX(sw_cons)].skb);
856 bd_cons = bnx2x_free_tx_pkt(bp, fp, pkt_cons);
864 fp->tx_pkt_cons = sw_cons;
865 fp->tx_bd_cons = bd_cons;
867 /* Need to make the tx_cons update visible to start_xmit()
868 * before checking for netif_queue_stopped(). Without the
869 * memory barrier, there is a small possibility that start_xmit()
870 * will miss it and cause the queue to be stopped forever.
874 /* TBD need a thresh? */
875 if (unlikely(netif_queue_stopped(bp->dev))) {
877 netif_tx_lock(bp->dev);
879 if (netif_queue_stopped(bp->dev) &&
880 (bp->state == BNX2X_STATE_OPEN) &&
881 (bnx2x_tx_avail(fp) >= MAX_SKB_FRAGS + 3))
882 netif_wake_queue(bp->dev);
884 netif_tx_unlock(bp->dev);
888 static void bnx2x_sp_event(struct bnx2x_fastpath *fp,
889 union eth_rx_cqe *rr_cqe)
891 struct bnx2x *bp = fp->bp;
892 int cid = SW_CID(rr_cqe->ramrod_cqe.conn_and_cmd_data);
893 int command = CQE_CMD(rr_cqe->ramrod_cqe.conn_and_cmd_data);
896 "fp %d cid %d got ramrod #%d state is %x type is %d\n",
897 FP_IDX(fp), cid, command, bp->state,
898 rr_cqe->ramrod_cqe.ramrod_type);
903 switch (command | fp->state) {
904 case (RAMROD_CMD_ID_ETH_CLIENT_SETUP |
905 BNX2X_FP_STATE_OPENING):
906 DP(NETIF_MSG_IFUP, "got MULTI[%d] setup ramrod\n",
908 fp->state = BNX2X_FP_STATE_OPEN;
911 case (RAMROD_CMD_ID_ETH_HALT | BNX2X_FP_STATE_HALTING):
912 DP(NETIF_MSG_IFDOWN, "got MULTI[%d] halt ramrod\n",
914 fp->state = BNX2X_FP_STATE_HALTED;
918 BNX2X_ERR("unexpected MC reply (%d) "
919 "fp->state is %x\n", command, fp->state);
922 mb(); /* force bnx2x_wait_ramrod() to see the change */
926 switch (command | bp->state) {
927 case (RAMROD_CMD_ID_ETH_PORT_SETUP | BNX2X_STATE_OPENING_WAIT4_PORT):
928 DP(NETIF_MSG_IFUP, "got setup ramrod\n");
929 bp->state = BNX2X_STATE_OPEN;
932 case (RAMROD_CMD_ID_ETH_HALT | BNX2X_STATE_CLOSING_WAIT4_HALT):
933 DP(NETIF_MSG_IFDOWN, "got halt ramrod\n");
934 bp->state = BNX2X_STATE_CLOSING_WAIT4_DELETE;
935 fp->state = BNX2X_FP_STATE_HALTED;
938 case (RAMROD_CMD_ID_ETH_CFC_DEL | BNX2X_STATE_CLOSING_WAIT4_HALT):
939 DP(NETIF_MSG_IFDOWN, "got delete ramrod for MULTI[%d]\n", cid);
940 bnx2x_fp(bp, cid, state) = BNX2X_FP_STATE_CLOSED;
943 case (RAMROD_CMD_ID_ETH_SET_MAC | BNX2X_STATE_OPEN):
944 case (RAMROD_CMD_ID_ETH_SET_MAC | BNX2X_STATE_DIAG):
945 DP(NETIF_MSG_IFUP, "got set mac ramrod\n");
946 bp->set_mac_pending = 0;
949 case (RAMROD_CMD_ID_ETH_SET_MAC | BNX2X_STATE_CLOSING_WAIT4_HALT):
950 DP(NETIF_MSG_IFDOWN, "got (un)set mac ramrod\n");
954 BNX2X_ERR("unexpected MC reply (%d) bp->state is %x\n",
958 mb(); /* force bnx2x_wait_ramrod() to see the change */
961 static inline void bnx2x_free_rx_sge(struct bnx2x *bp,
962 struct bnx2x_fastpath *fp, u16 index)
964 struct sw_rx_page *sw_buf = &fp->rx_page_ring[index];
965 struct page *page = sw_buf->page;
966 struct eth_rx_sge *sge = &fp->rx_sge_ring[index];
968 /* Skip "next page" elements */
972 pci_unmap_page(bp->pdev, pci_unmap_addr(sw_buf, mapping),
973 BCM_PAGE_SIZE*PAGES_PER_SGE, PCI_DMA_FROMDEVICE);
974 __free_pages(page, PAGES_PER_SGE_SHIFT);
981 static inline void bnx2x_free_rx_sge_range(struct bnx2x *bp,
982 struct bnx2x_fastpath *fp, int last)
986 for (i = 0; i < last; i++)
987 bnx2x_free_rx_sge(bp, fp, i);
990 static inline int bnx2x_alloc_rx_sge(struct bnx2x *bp,
991 struct bnx2x_fastpath *fp, u16 index)
993 struct page *page = alloc_pages(GFP_ATOMIC, PAGES_PER_SGE_SHIFT);
994 struct sw_rx_page *sw_buf = &fp->rx_page_ring[index];
995 struct eth_rx_sge *sge = &fp->rx_sge_ring[index];
998 if (unlikely(page == NULL))
1001 mapping = pci_map_page(bp->pdev, page, 0, BCM_PAGE_SIZE*PAGES_PER_SGE,
1002 PCI_DMA_FROMDEVICE);
1003 if (unlikely(dma_mapping_error(&bp->pdev->dev, mapping))) {
1004 __free_pages(page, PAGES_PER_SGE_SHIFT);
1008 sw_buf->page = page;
1009 pci_unmap_addr_set(sw_buf, mapping, mapping);
1011 sge->addr_hi = cpu_to_le32(U64_HI(mapping));
1012 sge->addr_lo = cpu_to_le32(U64_LO(mapping));
1017 static inline int bnx2x_alloc_rx_skb(struct bnx2x *bp,
1018 struct bnx2x_fastpath *fp, u16 index)
1020 struct sk_buff *skb;
1021 struct sw_rx_bd *rx_buf = &fp->rx_buf_ring[index];
1022 struct eth_rx_bd *rx_bd = &fp->rx_desc_ring[index];
1025 skb = netdev_alloc_skb(bp->dev, bp->rx_buf_size);
1026 if (unlikely(skb == NULL))
1029 mapping = pci_map_single(bp->pdev, skb->data, bp->rx_buf_use_size,
1030 PCI_DMA_FROMDEVICE);
1031 if (unlikely(dma_mapping_error(&bp->pdev->dev, mapping))) {
1037 pci_unmap_addr_set(rx_buf, mapping, mapping);
1039 rx_bd->addr_hi = cpu_to_le32(U64_HI(mapping));
1040 rx_bd->addr_lo = cpu_to_le32(U64_LO(mapping));
1045 /* note that we are not allocating a new skb,
1046 * we are just moving one from cons to prod
1047 * we are not creating a new mapping,
1048 * so there is no need to check for dma_mapping_error().
1050 static void bnx2x_reuse_rx_skb(struct bnx2x_fastpath *fp,
1051 struct sk_buff *skb, u16 cons, u16 prod)
1053 struct bnx2x *bp = fp->bp;
1054 struct sw_rx_bd *cons_rx_buf = &fp->rx_buf_ring[cons];
1055 struct sw_rx_bd *prod_rx_buf = &fp->rx_buf_ring[prod];
1056 struct eth_rx_bd *cons_bd = &fp->rx_desc_ring[cons];
1057 struct eth_rx_bd *prod_bd = &fp->rx_desc_ring[prod];
1059 pci_dma_sync_single_for_device(bp->pdev,
1060 pci_unmap_addr(cons_rx_buf, mapping),
1061 bp->rx_offset + RX_COPY_THRESH,
1062 PCI_DMA_FROMDEVICE);
1064 prod_rx_buf->skb = cons_rx_buf->skb;
1065 pci_unmap_addr_set(prod_rx_buf, mapping,
1066 pci_unmap_addr(cons_rx_buf, mapping));
1067 *prod_bd = *cons_bd;
1070 static inline void bnx2x_update_last_max_sge(struct bnx2x_fastpath *fp,
1073 u16 last_max = fp->last_max_sge;
1075 if (SUB_S16(idx, last_max) > 0)
1076 fp->last_max_sge = idx;
1079 static void bnx2x_clear_sge_mask_next_elems(struct bnx2x_fastpath *fp)
1083 for (i = 1; i <= NUM_RX_SGE_PAGES; i++) {
1084 int idx = RX_SGE_CNT * i - 1;
1086 for (j = 0; j < 2; j++) {
1087 SGE_MASK_CLEAR_BIT(fp, idx);
1093 static void bnx2x_update_sge_prod(struct bnx2x_fastpath *fp,
1094 struct eth_fast_path_rx_cqe *fp_cqe)
1096 struct bnx2x *bp = fp->bp;
1097 u16 sge_len = BCM_PAGE_ALIGN(le16_to_cpu(fp_cqe->pkt_len) -
1098 le16_to_cpu(fp_cqe->len_on_bd)) >>
1100 u16 last_max, last_elem, first_elem;
1107 /* First mark all used pages */
1108 for (i = 0; i < sge_len; i++)
1109 SGE_MASK_CLEAR_BIT(fp, RX_SGE(le16_to_cpu(fp_cqe->sgl[i])));
1111 DP(NETIF_MSG_RX_STATUS, "fp_cqe->sgl[%d] = %d\n",
1112 sge_len - 1, le16_to_cpu(fp_cqe->sgl[sge_len - 1]));
1114 /* Here we assume that the last SGE index is the biggest */
1115 prefetch((void *)(fp->sge_mask));
1116 bnx2x_update_last_max_sge(fp, le16_to_cpu(fp_cqe->sgl[sge_len - 1]));
1118 last_max = RX_SGE(fp->last_max_sge);
1119 last_elem = last_max >> RX_SGE_MASK_ELEM_SHIFT;
1120 first_elem = RX_SGE(fp->rx_sge_prod) >> RX_SGE_MASK_ELEM_SHIFT;
1122 /* If ring is not full */
1123 if (last_elem + 1 != first_elem)
1126 /* Now update the prod */
1127 for (i = first_elem; i != last_elem; i = NEXT_SGE_MASK_ELEM(i)) {
1128 if (likely(fp->sge_mask[i]))
1131 fp->sge_mask[i] = RX_SGE_MASK_ELEM_ONE_MASK;
1132 delta += RX_SGE_MASK_ELEM_SZ;
1136 fp->rx_sge_prod += delta;
1137 /* clear page-end entries */
1138 bnx2x_clear_sge_mask_next_elems(fp);
1141 DP(NETIF_MSG_RX_STATUS,
1142 "fp->last_max_sge = %d fp->rx_sge_prod = %d\n",
1143 fp->last_max_sge, fp->rx_sge_prod);
1146 static inline void bnx2x_init_sge_ring_bit_mask(struct bnx2x_fastpath *fp)
1148 /* Set the mask to all 1-s: it's faster to compare to 0 than to 0xf-s */
1149 memset(fp->sge_mask, 0xff,
1150 (NUM_RX_SGE >> RX_SGE_MASK_ELEM_SHIFT)*sizeof(u64));
1152 /* Clear the two last indeces in the page to 1:
1153 these are the indeces that correspond to the "next" element,
1154 hence will never be indicated and should be removed from
1155 the calculations. */
1156 bnx2x_clear_sge_mask_next_elems(fp);
1159 static void bnx2x_tpa_start(struct bnx2x_fastpath *fp, u16 queue,
1160 struct sk_buff *skb, u16 cons, u16 prod)
1162 struct bnx2x *bp = fp->bp;
1163 struct sw_rx_bd *cons_rx_buf = &fp->rx_buf_ring[cons];
1164 struct sw_rx_bd *prod_rx_buf = &fp->rx_buf_ring[prod];
1165 struct eth_rx_bd *prod_bd = &fp->rx_desc_ring[prod];
1168 /* move empty skb from pool to prod and map it */
1169 prod_rx_buf->skb = fp->tpa_pool[queue].skb;
1170 mapping = pci_map_single(bp->pdev, fp->tpa_pool[queue].skb->data,
1171 bp->rx_buf_use_size, PCI_DMA_FROMDEVICE);
1172 pci_unmap_addr_set(prod_rx_buf, mapping, mapping);
1174 /* move partial skb from cons to pool (don't unmap yet) */
1175 fp->tpa_pool[queue] = *cons_rx_buf;
1177 /* mark bin state as start - print error if current state != stop */
1178 if (fp->tpa_state[queue] != BNX2X_TPA_STOP)
1179 BNX2X_ERR("start of bin not in stop [%d]\n", queue);
1181 fp->tpa_state[queue] = BNX2X_TPA_START;
1183 /* point prod_bd to new skb */
1184 prod_bd->addr_hi = cpu_to_le32(U64_HI(mapping));
1185 prod_bd->addr_lo = cpu_to_le32(U64_LO(mapping));
1187 #ifdef BNX2X_STOP_ON_ERROR
1188 fp->tpa_queue_used |= (1 << queue);
1189 #ifdef __powerpc64__
1190 DP(NETIF_MSG_RX_STATUS, "fp->tpa_queue_used = 0x%lx\n",
1192 DP(NETIF_MSG_RX_STATUS, "fp->tpa_queue_used = 0x%llx\n",
1194 fp->tpa_queue_used);
1198 static int bnx2x_fill_frag_skb(struct bnx2x *bp, struct bnx2x_fastpath *fp,
1199 struct sk_buff *skb,
1200 struct eth_fast_path_rx_cqe *fp_cqe,
1203 struct sw_rx_page *rx_pg, old_rx_pg;
1205 u16 len_on_bd = le16_to_cpu(fp_cqe->len_on_bd);
1206 u32 i, frag_len, frag_size, pages;
1210 frag_size = le16_to_cpu(fp_cqe->pkt_len) - len_on_bd;
1211 pages = BCM_PAGE_ALIGN(frag_size) >> BCM_PAGE_SHIFT;
1213 /* This is needed in order to enable forwarding support */
1215 skb_shinfo(skb)->gso_size = min((u32)BCM_PAGE_SIZE,
1216 max(frag_size, (u32)len_on_bd));
1218 #ifdef BNX2X_STOP_ON_ERROR
1219 if (pages > 8*PAGES_PER_SGE) {
1220 BNX2X_ERR("SGL length is too long: %d. CQE index is %d\n",
1222 BNX2X_ERR("fp_cqe->pkt_len = %d fp_cqe->len_on_bd = %d\n",
1223 fp_cqe->pkt_len, len_on_bd);
1229 /* Run through the SGL and compose the fragmented skb */
1230 for (i = 0, j = 0; i < pages; i += PAGES_PER_SGE, j++) {
1231 u16 sge_idx = RX_SGE(le16_to_cpu(fp_cqe->sgl[j]));
1233 /* FW gives the indices of the SGE as if the ring is an array
1234 (meaning that "next" element will consume 2 indices) */
1235 frag_len = min(frag_size, (u32)(BCM_PAGE_SIZE*PAGES_PER_SGE));
1236 rx_pg = &fp->rx_page_ring[sge_idx];
1240 /* If we fail to allocate a substitute page, we simply stop
1241 where we are and drop the whole packet */
1242 err = bnx2x_alloc_rx_sge(bp, fp, sge_idx);
1243 if (unlikely(err)) {
1244 bp->eth_stats.rx_skb_alloc_failed++;
1248 /* Unmap the page as we r going to pass it to the stack */
1249 pci_unmap_page(bp->pdev, pci_unmap_addr(&old_rx_pg, mapping),
1250 BCM_PAGE_SIZE*PAGES_PER_SGE, PCI_DMA_FROMDEVICE);
1252 /* Add one frag and update the appropriate fields in the skb */
1253 skb_fill_page_desc(skb, j, old_rx_pg.page, 0, frag_len);
1255 skb->data_len += frag_len;
1256 skb->truesize += frag_len;
1257 skb->len += frag_len;
1259 frag_size -= frag_len;
1265 static void bnx2x_tpa_stop(struct bnx2x *bp, struct bnx2x_fastpath *fp,
1266 u16 queue, int pad, int len, union eth_rx_cqe *cqe,
1269 struct sw_rx_bd *rx_buf = &fp->tpa_pool[queue];
1270 struct sk_buff *skb = rx_buf->skb;
1272 struct sk_buff *new_skb = netdev_alloc_skb(bp->dev, bp->rx_buf_size);
1274 /* Unmap skb in the pool anyway, as we are going to change
1275 pool entry status to BNX2X_TPA_STOP even if new skb allocation
1277 pci_unmap_single(bp->pdev, pci_unmap_addr(rx_buf, mapping),
1278 bp->rx_buf_use_size, PCI_DMA_FROMDEVICE);
1280 if (likely(new_skb)) {
1281 /* fix ip xsum and give it to the stack */
1282 /* (no need to map the new skb) */
1285 prefetch(((char *)(skb)) + 128);
1287 #ifdef BNX2X_STOP_ON_ERROR
1288 if (pad + len > bp->rx_buf_size) {
1289 BNX2X_ERR("skb_put is about to fail... "
1290 "pad %d len %d rx_buf_size %d\n",
1291 pad, len, bp->rx_buf_size);
1297 skb_reserve(skb, pad);
1300 skb->protocol = eth_type_trans(skb, bp->dev);
1301 skb->ip_summed = CHECKSUM_UNNECESSARY;
1306 iph = (struct iphdr *)skb->data;
1308 iph->check = ip_fast_csum((u8 *)iph, iph->ihl);
1311 if (!bnx2x_fill_frag_skb(bp, fp, skb,
1312 &cqe->fast_path_cqe, cqe_idx)) {
1314 if ((bp->vlgrp != NULL) &&
1315 (le16_to_cpu(cqe->fast_path_cqe.pars_flags.flags) &
1316 PARSING_FLAGS_VLAN))
1317 vlan_hwaccel_receive_skb(skb, bp->vlgrp,
1318 le16_to_cpu(cqe->fast_path_cqe.
1322 netif_receive_skb(skb);
1324 DP(NETIF_MSG_RX_STATUS, "Failed to allocate new pages"
1325 " - dropping packet!\n");
1329 bp->dev->last_rx = jiffies;
1331 /* put new skb in bin */
1332 fp->tpa_pool[queue].skb = new_skb;
1335 /* else drop the packet and keep the buffer in the bin */
1336 DP(NETIF_MSG_RX_STATUS,
1337 "Failed to allocate new skb - dropping packet!\n");
1338 bp->eth_stats.rx_skb_alloc_failed++;
1341 fp->tpa_state[queue] = BNX2X_TPA_STOP;
1344 static inline void bnx2x_update_rx_prod(struct bnx2x *bp,
1345 struct bnx2x_fastpath *fp,
1346 u16 bd_prod, u16 rx_comp_prod,
1349 struct tstorm_eth_rx_producers rx_prods = {0};
1352 /* Update producers */
1353 rx_prods.bd_prod = bd_prod;
1354 rx_prods.cqe_prod = rx_comp_prod;
1355 rx_prods.sge_prod = rx_sge_prod;
1357 for (i = 0; i < sizeof(struct tstorm_eth_rx_producers)/4; i++)
1358 REG_WR(bp, BAR_TSTRORM_INTMEM +
1359 TSTORM_RX_PRODS_OFFSET(BP_PORT(bp), FP_CL_ID(fp)) + i*4,
1360 ((u32 *)&rx_prods)[i]);
1362 DP(NETIF_MSG_RX_STATUS,
1363 "Wrote: bd_prod %u cqe_prod %u sge_prod %u\n",
1364 bd_prod, rx_comp_prod, rx_sge_prod);
1367 static int bnx2x_rx_int(struct bnx2x_fastpath *fp, int budget)
1369 struct bnx2x *bp = fp->bp;
1370 u16 bd_cons, bd_prod, bd_prod_fw, comp_ring_cons;
1371 u16 hw_comp_cons, sw_comp_cons, sw_comp_prod;
1375 #ifdef BNX2X_STOP_ON_ERROR
1376 if (unlikely(bp->panic))
1380 /* CQ "next element" is of the size of the regular element,
1381 that's why it's ok here */
1382 hw_comp_cons = le16_to_cpu(*fp->rx_cons_sb);
1383 if ((hw_comp_cons & MAX_RCQ_DESC_CNT) == MAX_RCQ_DESC_CNT)
1386 bd_cons = fp->rx_bd_cons;
1387 bd_prod = fp->rx_bd_prod;
1388 bd_prod_fw = bd_prod;
1389 sw_comp_cons = fp->rx_comp_cons;
1390 sw_comp_prod = fp->rx_comp_prod;
1392 /* Memory barrier necessary as speculative reads of the rx
1393 * buffer can be ahead of the index in the status block
1397 DP(NETIF_MSG_RX_STATUS,
1398 "queue[%d]: hw_comp_cons %u sw_comp_cons %u\n",
1399 FP_IDX(fp), hw_comp_cons, sw_comp_cons);
1401 while (sw_comp_cons != hw_comp_cons) {
1402 struct sw_rx_bd *rx_buf = NULL;
1403 struct sk_buff *skb;
1404 union eth_rx_cqe *cqe;
1408 comp_ring_cons = RCQ_BD(sw_comp_cons);
1409 bd_prod = RX_BD(bd_prod);
1410 bd_cons = RX_BD(bd_cons);
1412 cqe = &fp->rx_comp_ring[comp_ring_cons];
1413 cqe_fp_flags = cqe->fast_path_cqe.type_error_flags;
1415 DP(NETIF_MSG_RX_STATUS, "CQE type %x err %x status %x"
1416 " queue %x vlan %x len %u\n", CQE_TYPE(cqe_fp_flags),
1417 cqe_fp_flags, cqe->fast_path_cqe.status_flags,
1418 cqe->fast_path_cqe.rss_hash_result,
1419 le16_to_cpu(cqe->fast_path_cqe.vlan_tag),
1420 le16_to_cpu(cqe->fast_path_cqe.pkt_len));
1422 /* is this a slowpath msg? */
1423 if (unlikely(CQE_TYPE(cqe_fp_flags))) {
1424 bnx2x_sp_event(fp, cqe);
1427 /* this is an rx packet */
1429 rx_buf = &fp->rx_buf_ring[bd_cons];
1431 len = le16_to_cpu(cqe->fast_path_cqe.pkt_len);
1432 pad = cqe->fast_path_cqe.placement_offset;
1434 /* If CQE is marked both TPA_START and TPA_END
1435 it is a non-TPA CQE */
1436 if ((!fp->disable_tpa) &&
1437 (TPA_TYPE(cqe_fp_flags) !=
1438 (TPA_TYPE_START | TPA_TYPE_END))) {
1439 queue = cqe->fast_path_cqe.queue_index;
1441 if (TPA_TYPE(cqe_fp_flags) == TPA_TYPE_START) {
1442 DP(NETIF_MSG_RX_STATUS,
1443 "calling tpa_start on queue %d\n",
1446 bnx2x_tpa_start(fp, queue, skb,
1451 if (TPA_TYPE(cqe_fp_flags) == TPA_TYPE_END) {
1452 DP(NETIF_MSG_RX_STATUS,
1453 "calling tpa_stop on queue %d\n",
1456 if (!BNX2X_RX_SUM_FIX(cqe))
1457 BNX2X_ERR("STOP on none TCP "
1460 /* This is a size of the linear data
1462 len = le16_to_cpu(cqe->fast_path_cqe.
1464 bnx2x_tpa_stop(bp, fp, queue, pad,
1465 len, cqe, comp_ring_cons);
1466 #ifdef BNX2X_STOP_ON_ERROR
1471 bnx2x_update_sge_prod(fp,
1472 &cqe->fast_path_cqe);
1477 pci_dma_sync_single_for_device(bp->pdev,
1478 pci_unmap_addr(rx_buf, mapping),
1479 pad + RX_COPY_THRESH,
1480 PCI_DMA_FROMDEVICE);
1482 prefetch(((char *)(skb)) + 128);
1484 /* is this an error packet? */
1485 if (unlikely(cqe_fp_flags & ETH_RX_ERROR_FALGS)) {
1486 DP(NETIF_MSG_RX_ERR,
1487 "ERROR flags %x rx packet %u\n",
1488 cqe_fp_flags, sw_comp_cons);
1489 bp->eth_stats.rx_err_discard_pkt++;
1493 /* Since we don't have a jumbo ring
1494 * copy small packets if mtu > 1500
1496 if ((bp->dev->mtu > ETH_MAX_PACKET_SIZE) &&
1497 (len <= RX_COPY_THRESH)) {
1498 struct sk_buff *new_skb;
1500 new_skb = netdev_alloc_skb(bp->dev,
1502 if (new_skb == NULL) {
1503 DP(NETIF_MSG_RX_ERR,
1504 "ERROR packet dropped "
1505 "because of alloc failure\n");
1506 bp->eth_stats.rx_skb_alloc_failed++;
1511 skb_copy_from_linear_data_offset(skb, pad,
1512 new_skb->data + pad, len);
1513 skb_reserve(new_skb, pad);
1514 skb_put(new_skb, len);
1516 bnx2x_reuse_rx_skb(fp, skb, bd_cons, bd_prod);
1520 } else if (bnx2x_alloc_rx_skb(bp, fp, bd_prod) == 0) {
1521 pci_unmap_single(bp->pdev,
1522 pci_unmap_addr(rx_buf, mapping),
1523 bp->rx_buf_use_size,
1524 PCI_DMA_FROMDEVICE);
1525 skb_reserve(skb, pad);
1529 DP(NETIF_MSG_RX_ERR,
1530 "ERROR packet dropped because "
1531 "of alloc failure\n");
1532 bp->eth_stats.rx_skb_alloc_failed++;
1534 bnx2x_reuse_rx_skb(fp, skb, bd_cons, bd_prod);
1538 skb->protocol = eth_type_trans(skb, bp->dev);
1540 skb->ip_summed = CHECKSUM_NONE;
1542 if (likely(BNX2X_RX_CSUM_OK(cqe)))
1543 skb->ip_summed = CHECKSUM_UNNECESSARY;
1545 bp->eth_stats.hw_csum_err++;
1550 if ((bp->vlgrp != NULL) &&
1551 (le16_to_cpu(cqe->fast_path_cqe.pars_flags.flags) &
1552 PARSING_FLAGS_VLAN))
1553 vlan_hwaccel_receive_skb(skb, bp->vlgrp,
1554 le16_to_cpu(cqe->fast_path_cqe.vlan_tag));
1557 netif_receive_skb(skb);
1559 bp->dev->last_rx = jiffies;
1564 bd_cons = NEXT_RX_IDX(bd_cons);
1565 bd_prod = NEXT_RX_IDX(bd_prod);
1566 bd_prod_fw = NEXT_RX_IDX(bd_prod_fw);
1569 sw_comp_prod = NEXT_RCQ_IDX(sw_comp_prod);
1570 sw_comp_cons = NEXT_RCQ_IDX(sw_comp_cons);
1572 if (rx_pkt == budget)
1576 fp->rx_bd_cons = bd_cons;
1577 fp->rx_bd_prod = bd_prod_fw;
1578 fp->rx_comp_cons = sw_comp_cons;
1579 fp->rx_comp_prod = sw_comp_prod;
1581 /* Update producers */
1582 bnx2x_update_rx_prod(bp, fp, bd_prod_fw, sw_comp_prod,
1584 mmiowb(); /* keep prod updates ordered */
1586 fp->rx_pkt += rx_pkt;
1592 static irqreturn_t bnx2x_msix_fp_int(int irq, void *fp_cookie)
1594 struct bnx2x_fastpath *fp = fp_cookie;
1595 struct bnx2x *bp = fp->bp;
1596 struct net_device *dev = bp->dev;
1597 int index = FP_IDX(fp);
1599 /* Return here if interrupt is disabled */
1600 if (unlikely(atomic_read(&bp->intr_sem) != 0)) {
1601 DP(NETIF_MSG_INTR, "called but intr_sem not 0, returning\n");
1605 DP(BNX2X_MSG_FP, "got an MSI-X interrupt on IDX:SB [%d:%d]\n",
1606 index, FP_SB_ID(fp));
1607 bnx2x_ack_sb(bp, FP_SB_ID(fp), USTORM_ID, 0, IGU_INT_DISABLE, 0);
1609 #ifdef BNX2X_STOP_ON_ERROR
1610 if (unlikely(bp->panic))
1614 prefetch(fp->rx_cons_sb);
1615 prefetch(fp->tx_cons_sb);
1616 prefetch(&fp->status_blk->c_status_block.status_block_index);
1617 prefetch(&fp->status_blk->u_status_block.status_block_index);
1619 netif_rx_schedule(dev, &bnx2x_fp(bp, index, napi));
1624 static irqreturn_t bnx2x_interrupt(int irq, void *dev_instance)
1626 struct net_device *dev = dev_instance;
1627 struct bnx2x *bp = netdev_priv(dev);
1628 u16 status = bnx2x_ack_int(bp);
1631 /* Return here if interrupt is shared and it's not for us */
1632 if (unlikely(status == 0)) {
1633 DP(NETIF_MSG_INTR, "not our interrupt!\n");
1636 DP(NETIF_MSG_INTR, "got an interrupt status %u\n", status);
1638 #ifdef BNX2X_STOP_ON_ERROR
1639 if (unlikely(bp->panic))
1643 /* Return here if interrupt is disabled */
1644 if (unlikely(atomic_read(&bp->intr_sem) != 0)) {
1645 DP(NETIF_MSG_INTR, "called but intr_sem not 0, returning\n");
1649 mask = 0x2 << bp->fp[0].sb_id;
1650 if (status & mask) {
1651 struct bnx2x_fastpath *fp = &bp->fp[0];
1653 prefetch(fp->rx_cons_sb);
1654 prefetch(fp->tx_cons_sb);
1655 prefetch(&fp->status_blk->c_status_block.status_block_index);
1656 prefetch(&fp->status_blk->u_status_block.status_block_index);
1658 netif_rx_schedule(dev, &bnx2x_fp(bp, 0, napi));
1664 if (unlikely(status & 0x1)) {
1665 schedule_work(&bp->sp_task);
1673 DP(NETIF_MSG_INTR, "got an unknown interrupt! (status %u)\n",
1679 /* end of fast path */
1681 static void bnx2x_stats_handle(struct bnx2x *bp, enum bnx2x_stats_event event);
1686 * General service functions
1689 static int bnx2x_acquire_hw_lock(struct bnx2x *bp, u32 resource)
1692 u32 resource_bit = (1 << resource);
1693 int func = BP_FUNC(bp);
1694 u32 hw_lock_control_reg;
1697 /* Validating that the resource is within range */
1698 if (resource > HW_LOCK_MAX_RESOURCE_VALUE) {
1700 "resource(0x%x) > HW_LOCK_MAX_RESOURCE_VALUE(0x%x)\n",
1701 resource, HW_LOCK_MAX_RESOURCE_VALUE);
1706 hw_lock_control_reg = (MISC_REG_DRIVER_CONTROL_1 + func*8);
1708 hw_lock_control_reg =
1709 (MISC_REG_DRIVER_CONTROL_7 + (func - 6)*8);
1712 /* Validating that the resource is not already taken */
1713 lock_status = REG_RD(bp, hw_lock_control_reg);
1714 if (lock_status & resource_bit) {
1715 DP(NETIF_MSG_HW, "lock_status 0x%x resource_bit 0x%x\n",
1716 lock_status, resource_bit);
1720 /* Try for 1 second every 5ms */
1721 for (cnt = 0; cnt < 200; cnt++) {
1722 /* Try to acquire the lock */
1723 REG_WR(bp, hw_lock_control_reg + 4, resource_bit);
1724 lock_status = REG_RD(bp, hw_lock_control_reg);
1725 if (lock_status & resource_bit)
1730 DP(NETIF_MSG_HW, "Timeout\n");
1734 static int bnx2x_release_hw_lock(struct bnx2x *bp, u32 resource)
1737 u32 resource_bit = (1 << resource);
1738 int func = BP_FUNC(bp);
1739 u32 hw_lock_control_reg;
1741 /* Validating that the resource is within range */
1742 if (resource > HW_LOCK_MAX_RESOURCE_VALUE) {
1744 "resource(0x%x) > HW_LOCK_MAX_RESOURCE_VALUE(0x%x)\n",
1745 resource, HW_LOCK_MAX_RESOURCE_VALUE);
1750 hw_lock_control_reg = (MISC_REG_DRIVER_CONTROL_1 + func*8);
1752 hw_lock_control_reg =
1753 (MISC_REG_DRIVER_CONTROL_7 + (func - 6)*8);
1756 /* Validating that the resource is currently taken */
1757 lock_status = REG_RD(bp, hw_lock_control_reg);
1758 if (!(lock_status & resource_bit)) {
1759 DP(NETIF_MSG_HW, "lock_status 0x%x resource_bit 0x%x\n",
1760 lock_status, resource_bit);
1764 REG_WR(bp, hw_lock_control_reg, resource_bit);
1768 /* HW Lock for shared dual port PHYs */
1769 static void bnx2x_acquire_phy_lock(struct bnx2x *bp)
1771 u32 ext_phy_type = XGXS_EXT_PHY_TYPE(bp->link_params.ext_phy_config);
1773 mutex_lock(&bp->port.phy_mutex);
1775 if ((ext_phy_type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8072) ||
1776 (ext_phy_type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073))
1777 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_8072_MDIO);
1780 static void bnx2x_release_phy_lock(struct bnx2x *bp)
1782 u32 ext_phy_type = XGXS_EXT_PHY_TYPE(bp->link_params.ext_phy_config);
1784 if ((ext_phy_type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8072) ||
1785 (ext_phy_type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073))
1786 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_8072_MDIO);
1788 mutex_unlock(&bp->port.phy_mutex);
1791 int bnx2x_set_gpio(struct bnx2x *bp, int gpio_num, u32 mode, u8 port)
1793 /* The GPIO should be swapped if swap register is set and active */
1794 int gpio_port = (REG_RD(bp, NIG_REG_PORT_SWAP) &&
1795 REG_RD(bp, NIG_REG_STRAP_OVERRIDE)) ^ port;
1796 int gpio_shift = gpio_num +
1797 (gpio_port ? MISC_REGISTERS_GPIO_PORT_SHIFT : 0);
1798 u32 gpio_mask = (1 << gpio_shift);
1801 if (gpio_num > MISC_REGISTERS_GPIO_3) {
1802 BNX2X_ERR("Invalid GPIO %d\n", gpio_num);
1806 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_GPIO);
1807 /* read GPIO and mask except the float bits */
1808 gpio_reg = (REG_RD(bp, MISC_REG_GPIO) & MISC_REGISTERS_GPIO_FLOAT);
1811 case MISC_REGISTERS_GPIO_OUTPUT_LOW:
1812 DP(NETIF_MSG_LINK, "Set GPIO %d (shift %d) -> output low\n",
1813 gpio_num, gpio_shift);
1814 /* clear FLOAT and set CLR */
1815 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_FLOAT_POS);
1816 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_CLR_POS);
1819 case MISC_REGISTERS_GPIO_OUTPUT_HIGH:
1820 DP(NETIF_MSG_LINK, "Set GPIO %d (shift %d) -> output high\n",
1821 gpio_num, gpio_shift);
1822 /* clear FLOAT and set SET */
1823 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_FLOAT_POS);
1824 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_SET_POS);
1827 case MISC_REGISTERS_GPIO_INPUT_HI_Z:
1828 DP(NETIF_MSG_LINK, "Set GPIO %d (shift %d) -> input\n",
1829 gpio_num, gpio_shift);
1831 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_FLOAT_POS);
1838 REG_WR(bp, MISC_REG_GPIO, gpio_reg);
1839 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_GPIO);
1844 static int bnx2x_set_spio(struct bnx2x *bp, int spio_num, u32 mode)
1846 u32 spio_mask = (1 << spio_num);
1849 if ((spio_num < MISC_REGISTERS_SPIO_4) ||
1850 (spio_num > MISC_REGISTERS_SPIO_7)) {
1851 BNX2X_ERR("Invalid SPIO %d\n", spio_num);
1855 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_SPIO);
1856 /* read SPIO and mask except the float bits */
1857 spio_reg = (REG_RD(bp, MISC_REG_SPIO) & MISC_REGISTERS_SPIO_FLOAT);
1860 case MISC_REGISTERS_SPIO_OUTPUT_LOW :
1861 DP(NETIF_MSG_LINK, "Set SPIO %d -> output low\n", spio_num);
1862 /* clear FLOAT and set CLR */
1863 spio_reg &= ~(spio_mask << MISC_REGISTERS_SPIO_FLOAT_POS);
1864 spio_reg |= (spio_mask << MISC_REGISTERS_SPIO_CLR_POS);
1867 case MISC_REGISTERS_SPIO_OUTPUT_HIGH :
1868 DP(NETIF_MSG_LINK, "Set SPIO %d -> output high\n", spio_num);
1869 /* clear FLOAT and set SET */
1870 spio_reg &= ~(spio_mask << MISC_REGISTERS_SPIO_FLOAT_POS);
1871 spio_reg |= (spio_mask << MISC_REGISTERS_SPIO_SET_POS);
1874 case MISC_REGISTERS_SPIO_INPUT_HI_Z:
1875 DP(NETIF_MSG_LINK, "Set SPIO %d -> input\n", spio_num);
1877 spio_reg |= (spio_mask << MISC_REGISTERS_SPIO_FLOAT_POS);
1884 REG_WR(bp, MISC_REG_SPIO, spio_reg);
1885 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_SPIO);
1890 static void bnx2x_calc_fc_adv(struct bnx2x *bp)
1892 switch (bp->link_vars.ieee_fc) {
1893 case MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_NONE:
1894 bp->port.advertising &= ~(ADVERTISED_Asym_Pause |
1897 case MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH:
1898 bp->port.advertising |= (ADVERTISED_Asym_Pause |
1901 case MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC:
1902 bp->port.advertising |= ADVERTISED_Asym_Pause;
1905 bp->port.advertising &= ~(ADVERTISED_Asym_Pause |
1911 static void bnx2x_link_report(struct bnx2x *bp)
1913 if (bp->link_vars.link_up) {
1914 if (bp->state == BNX2X_STATE_OPEN)
1915 netif_carrier_on(bp->dev);
1916 printk(KERN_INFO PFX "%s NIC Link is Up, ", bp->dev->name);
1918 printk("%d Mbps ", bp->link_vars.line_speed);
1920 if (bp->link_vars.duplex == DUPLEX_FULL)
1921 printk("full duplex");
1923 printk("half duplex");
1925 if (bp->link_vars.flow_ctrl != FLOW_CTRL_NONE) {
1926 if (bp->link_vars.flow_ctrl & FLOW_CTRL_RX) {
1927 printk(", receive ");
1928 if (bp->link_vars.flow_ctrl & FLOW_CTRL_TX)
1929 printk("& transmit ");
1931 printk(", transmit ");
1933 printk("flow control ON");
1937 } else { /* link_down */
1938 netif_carrier_off(bp->dev);
1939 printk(KERN_ERR PFX "%s NIC Link is Down\n", bp->dev->name);
1943 static u8 bnx2x_initial_phy_init(struct bnx2x *bp)
1945 if (!BP_NOMCP(bp)) {
1948 /* Initialize link parameters structure variables */
1949 /* It is recommended to turn off RX FC for jumbo frames
1950 for better performance */
1952 bp->link_params.req_fc_auto_adv = FLOW_CTRL_BOTH;
1953 else if (bp->dev->mtu > 5000)
1954 bp->link_params.req_fc_auto_adv = FLOW_CTRL_TX;
1956 bp->link_params.req_fc_auto_adv = FLOW_CTRL_BOTH;
1958 bnx2x_acquire_phy_lock(bp);
1959 rc = bnx2x_phy_init(&bp->link_params, &bp->link_vars);
1960 bnx2x_release_phy_lock(bp);
1962 if (bp->link_vars.link_up)
1963 bnx2x_link_report(bp);
1965 bnx2x_calc_fc_adv(bp);
1969 BNX2X_ERR("Bootcode is missing -not initializing link\n");
1973 static void bnx2x_link_set(struct bnx2x *bp)
1975 if (!BP_NOMCP(bp)) {
1976 bnx2x_acquire_phy_lock(bp);
1977 bnx2x_phy_init(&bp->link_params, &bp->link_vars);
1978 bnx2x_release_phy_lock(bp);
1980 bnx2x_calc_fc_adv(bp);
1982 BNX2X_ERR("Bootcode is missing -not setting link\n");
1985 static void bnx2x__link_reset(struct bnx2x *bp)
1987 if (!BP_NOMCP(bp)) {
1988 bnx2x_acquire_phy_lock(bp);
1989 bnx2x_link_reset(&bp->link_params, &bp->link_vars);
1990 bnx2x_release_phy_lock(bp);
1992 BNX2X_ERR("Bootcode is missing -not resetting link\n");
1995 static u8 bnx2x_link_test(struct bnx2x *bp)
1999 bnx2x_acquire_phy_lock(bp);
2000 rc = bnx2x_test_link(&bp->link_params, &bp->link_vars);
2001 bnx2x_release_phy_lock(bp);
2006 /* Calculates the sum of vn_min_rates.
2007 It's needed for further normalizing of the min_rates.
2012 0 - if all the min_rates are 0.
2013 In the later case fainess algorithm should be deactivated.
2014 If not all min_rates are zero then those that are zeroes will
2017 static u32 bnx2x_calc_vn_wsum(struct bnx2x *bp)
2019 int i, port = BP_PORT(bp);
2023 for (i = 0; i < E1HVN_MAX; i++) {
2025 SHMEM_RD(bp, mf_cfg.func_mf_config[2*i + port].config);
2026 u32 vn_min_rate = ((vn_cfg & FUNC_MF_CFG_MIN_BW_MASK) >>
2027 FUNC_MF_CFG_MIN_BW_SHIFT) * 100;
2028 if (!(vn_cfg & FUNC_MF_CFG_FUNC_HIDE)) {
2029 /* If min rate is zero - set it to 1 */
2031 vn_min_rate = DEF_MIN_RATE;
2035 wsum += vn_min_rate;
2039 /* ... only if all min rates are zeros - disable FAIRNESS */
2046 static void bnx2x_init_port_minmax(struct bnx2x *bp,
2049 struct cmng_struct_per_port *m_cmng_port)
2051 u32 r_param = port_rate / 8;
2052 int port = BP_PORT(bp);
2055 memset(m_cmng_port, 0, sizeof(struct cmng_struct_per_port));
2057 /* Enable minmax only if we are in e1hmf mode */
2059 u32 fair_periodic_timeout_usec;
2062 /* Enable rate shaping and fairness */
2063 m_cmng_port->flags.cmng_vn_enable = 1;
2064 m_cmng_port->flags.fairness_enable = en_fness ? 1 : 0;
2065 m_cmng_port->flags.rate_shaping_enable = 1;
2068 DP(NETIF_MSG_IFUP, "All MIN values are zeroes"
2069 " fairness will be disabled\n");
2071 /* 100 usec in SDM ticks = 25 since each tick is 4 usec */
2072 m_cmng_port->rs_vars.rs_periodic_timeout =
2073 RS_PERIODIC_TIMEOUT_USEC / 4;
2075 /* this is the threshold below which no timer arming will occur
2076 1.25 coefficient is for the threshold to be a little bigger
2077 than the real time, to compensate for timer in-accuracy */
2078 m_cmng_port->rs_vars.rs_threshold =
2079 (RS_PERIODIC_TIMEOUT_USEC * r_param * 5) / 4;
2081 /* resolution of fairness timer */
2082 fair_periodic_timeout_usec = QM_ARB_BYTES / r_param;
2083 /* for 10G it is 1000usec. for 1G it is 10000usec. */
2084 t_fair = T_FAIR_COEF / port_rate;
2086 /* this is the threshold below which we won't arm
2087 the timer anymore */
2088 m_cmng_port->fair_vars.fair_threshold = QM_ARB_BYTES;
2090 /* we multiply by 1e3/8 to get bytes/msec.
2091 We don't want the credits to pass a credit
2092 of the T_FAIR*FAIR_MEM (algorithm resolution) */
2093 m_cmng_port->fair_vars.upper_bound =
2094 r_param * t_fair * FAIR_MEM;
2095 /* since each tick is 4 usec */
2096 m_cmng_port->fair_vars.fairness_timeout =
2097 fair_periodic_timeout_usec / 4;
2100 /* Disable rate shaping and fairness */
2101 m_cmng_port->flags.cmng_vn_enable = 0;
2102 m_cmng_port->flags.fairness_enable = 0;
2103 m_cmng_port->flags.rate_shaping_enable = 0;
2106 "Single function mode minmax will be disabled\n");
2109 /* Store it to internal memory */
2110 for (i = 0; i < sizeof(struct cmng_struct_per_port) / 4; i++)
2111 REG_WR(bp, BAR_XSTRORM_INTMEM +
2112 XSTORM_CMNG_PER_PORT_VARS_OFFSET(port) + i * 4,
2113 ((u32 *)(m_cmng_port))[i]);
2116 static void bnx2x_init_vn_minmax(struct bnx2x *bp, int func,
2117 u32 wsum, u16 port_rate,
2118 struct cmng_struct_per_port *m_cmng_port)
2120 struct rate_shaping_vars_per_vn m_rs_vn;
2121 struct fairness_vars_per_vn m_fair_vn;
2122 u32 vn_cfg = SHMEM_RD(bp, mf_cfg.func_mf_config[func].config);
2123 u16 vn_min_rate, vn_max_rate;
2126 /* If function is hidden - set min and max to zeroes */
2127 if (vn_cfg & FUNC_MF_CFG_FUNC_HIDE) {
2132 vn_min_rate = ((vn_cfg & FUNC_MF_CFG_MIN_BW_MASK) >>
2133 FUNC_MF_CFG_MIN_BW_SHIFT) * 100;
2134 /* If FAIRNESS is enabled (not all min rates are zeroes) and
2135 if current min rate is zero - set it to 1.
2136 This is a requirment of the algorithm. */
2137 if ((vn_min_rate == 0) && wsum)
2138 vn_min_rate = DEF_MIN_RATE;
2139 vn_max_rate = ((vn_cfg & FUNC_MF_CFG_MAX_BW_MASK) >>
2140 FUNC_MF_CFG_MAX_BW_SHIFT) * 100;
2143 DP(NETIF_MSG_IFUP, "func %d: vn_min_rate=%d vn_max_rate=%d "
2144 "wsum=%d\n", func, vn_min_rate, vn_max_rate, wsum);
2146 memset(&m_rs_vn, 0, sizeof(struct rate_shaping_vars_per_vn));
2147 memset(&m_fair_vn, 0, sizeof(struct fairness_vars_per_vn));
2149 /* global vn counter - maximal Mbps for this vn */
2150 m_rs_vn.vn_counter.rate = vn_max_rate;
2152 /* quota - number of bytes transmitted in this period */
2153 m_rs_vn.vn_counter.quota =
2154 (vn_max_rate * RS_PERIODIC_TIMEOUT_USEC) / 8;
2156 #ifdef BNX2X_PER_PROT_QOS
2157 /* per protocol counter */
2158 for (protocol = 0; protocol < NUM_OF_PROTOCOLS; protocol++) {
2159 /* maximal Mbps for this protocol */
2160 m_rs_vn.protocol_counters[protocol].rate =
2161 protocol_max_rate[protocol];
2162 /* the quota in each timer period -
2163 number of bytes transmitted in this period */
2164 m_rs_vn.protocol_counters[protocol].quota =
2165 (u32)(rs_periodic_timeout_usec *
2167 protocol_counters[protocol].rate/8));
2172 /* credit for each period of the fairness algorithm:
2173 number of bytes in T_FAIR (the vn share the port rate).
2174 wsum should not be larger than 10000, thus
2175 T_FAIR_COEF / (8 * wsum) will always be grater than zero */
2176 m_fair_vn.vn_credit_delta =
2177 max((u64)(vn_min_rate * (T_FAIR_COEF / (8 * wsum))),
2178 (u64)(m_cmng_port->fair_vars.fair_threshold * 2));
2179 DP(NETIF_MSG_IFUP, "m_fair_vn.vn_credit_delta=%d\n",
2180 m_fair_vn.vn_credit_delta);
2183 #ifdef BNX2X_PER_PROT_QOS
2185 u32 protocolWeightSum = 0;
2187 for (protocol = 0; protocol < NUM_OF_PROTOCOLS; protocol++)
2188 protocolWeightSum +=
2189 drvInit.protocol_min_rate[protocol];
2190 /* per protocol counter -
2191 NOT NEEDED IF NO PER-PROTOCOL CONGESTION MANAGEMENT */
2192 if (protocolWeightSum > 0) {
2194 protocol < NUM_OF_PROTOCOLS; protocol++)
2195 /* credit for each period of the
2196 fairness algorithm - number of bytes in
2197 T_FAIR (the protocol share the vn rate) */
2198 m_fair_vn.protocol_credit_delta[protocol] =
2199 (u32)((vn_min_rate / 8) * t_fair *
2200 protocol_min_rate / protocolWeightSum);
2205 /* Store it to internal memory */
2206 for (i = 0; i < sizeof(struct rate_shaping_vars_per_vn)/4; i++)
2207 REG_WR(bp, BAR_XSTRORM_INTMEM +
2208 XSTORM_RATE_SHAPING_PER_VN_VARS_OFFSET(func) + i * 4,
2209 ((u32 *)(&m_rs_vn))[i]);
2211 for (i = 0; i < sizeof(struct fairness_vars_per_vn)/4; i++)
2212 REG_WR(bp, BAR_XSTRORM_INTMEM +
2213 XSTORM_FAIRNESS_PER_VN_VARS_OFFSET(func) + i * 4,
2214 ((u32 *)(&m_fair_vn))[i]);
2217 /* This function is called upon link interrupt */
2218 static void bnx2x_link_attn(struct bnx2x *bp)
2222 /* Make sure that we are synced with the current statistics */
2223 bnx2x_stats_handle(bp, STATS_EVENT_STOP);
2225 bnx2x_acquire_phy_lock(bp);
2226 bnx2x_link_update(&bp->link_params, &bp->link_vars);
2227 bnx2x_release_phy_lock(bp);
2229 if (bp->link_vars.link_up) {
2231 if (bp->link_vars.mac_type == MAC_TYPE_BMAC) {
2232 struct host_port_stats *pstats;
2234 pstats = bnx2x_sp(bp, port_stats);
2235 /* reset old bmac stats */
2236 memset(&(pstats->mac_stx[0]), 0,
2237 sizeof(struct mac_stx));
2239 if ((bp->state == BNX2X_STATE_OPEN) ||
2240 (bp->state == BNX2X_STATE_DISABLED))
2241 bnx2x_stats_handle(bp, STATS_EVENT_LINK_UP);
2244 /* indicate link status */
2245 bnx2x_link_report(bp);
2250 for (vn = VN_0; vn < E1HVN_MAX; vn++) {
2251 if (vn == BP_E1HVN(bp))
2254 func = ((vn << 1) | BP_PORT(bp));
2256 /* Set the attention towards other drivers
2258 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_0 +
2259 (LINK_SYNC_ATTENTION_BIT_FUNC_0 + func)*4, 1);
2263 if (CHIP_IS_E1H(bp) && (bp->link_vars.line_speed > 0)) {
2264 struct cmng_struct_per_port m_cmng_port;
2266 int port = BP_PORT(bp);
2268 /* Init RATE SHAPING and FAIRNESS contexts */
2269 wsum = bnx2x_calc_vn_wsum(bp);
2270 bnx2x_init_port_minmax(bp, (int)wsum,
2271 bp->link_vars.line_speed,
2274 for (vn = VN_0; vn < E1HVN_MAX; vn++)
2275 bnx2x_init_vn_minmax(bp, 2*vn + port,
2276 wsum, bp->link_vars.line_speed,
2281 static void bnx2x__link_status_update(struct bnx2x *bp)
2283 if (bp->state != BNX2X_STATE_OPEN)
2286 bnx2x_link_status_update(&bp->link_params, &bp->link_vars);
2288 if (bp->link_vars.link_up)
2289 bnx2x_stats_handle(bp, STATS_EVENT_LINK_UP);
2291 bnx2x_stats_handle(bp, STATS_EVENT_STOP);
2293 /* indicate link status */
2294 bnx2x_link_report(bp);
2297 static void bnx2x_pmf_update(struct bnx2x *bp)
2299 int port = BP_PORT(bp);
2303 DP(NETIF_MSG_LINK, "pmf %d\n", bp->port.pmf);
2305 /* enable nig attention */
2306 val = (0xff0f | (1 << (BP_E1HVN(bp) + 4)));
2307 REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, val);
2308 REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, val);
2310 bnx2x_stats_handle(bp, STATS_EVENT_PMF);
2318 * General service functions
2321 /* the slow path queue is odd since completions arrive on the fastpath ring */
2322 static int bnx2x_sp_post(struct bnx2x *bp, int command, int cid,
2323 u32 data_hi, u32 data_lo, int common)
2325 int func = BP_FUNC(bp);
2327 DP(BNX2X_MSG_SP/*NETIF_MSG_TIMER*/,
2328 "SPQE (%x:%x) command %d hw_cid %x data (%x:%x) left %x\n",
2329 (u32)U64_HI(bp->spq_mapping), (u32)(U64_LO(bp->spq_mapping) +
2330 (void *)bp->spq_prod_bd - (void *)bp->spq), command,
2331 HW_CID(bp, cid), data_hi, data_lo, bp->spq_left);
2333 #ifdef BNX2X_STOP_ON_ERROR
2334 if (unlikely(bp->panic))
2338 spin_lock_bh(&bp->spq_lock);
2340 if (!bp->spq_left) {
2341 BNX2X_ERR("BUG! SPQ ring full!\n");
2342 spin_unlock_bh(&bp->spq_lock);
2347 /* CID needs port number to be encoded int it */
2348 bp->spq_prod_bd->hdr.conn_and_cmd_data =
2349 cpu_to_le32(((command << SPE_HDR_CMD_ID_SHIFT) |
2351 bp->spq_prod_bd->hdr.type = cpu_to_le16(ETH_CONNECTION_TYPE);
2353 bp->spq_prod_bd->hdr.type |=
2354 cpu_to_le16((1 << SPE_HDR_COMMON_RAMROD_SHIFT));
2356 bp->spq_prod_bd->data.mac_config_addr.hi = cpu_to_le32(data_hi);
2357 bp->spq_prod_bd->data.mac_config_addr.lo = cpu_to_le32(data_lo);
2361 if (bp->spq_prod_bd == bp->spq_last_bd) {
2362 bp->spq_prod_bd = bp->spq;
2363 bp->spq_prod_idx = 0;
2364 DP(NETIF_MSG_TIMER, "end of spq\n");
2371 REG_WR(bp, BAR_XSTRORM_INTMEM + XSTORM_SPQ_PROD_OFFSET(func),
2374 spin_unlock_bh(&bp->spq_lock);
2378 /* acquire split MCP access lock register */
2379 static int bnx2x_acquire_alr(struct bnx2x *bp)
2386 for (j = 0; j < i*10; j++) {
2388 REG_WR(bp, GRCBASE_MCP + 0x9c, val);
2389 val = REG_RD(bp, GRCBASE_MCP + 0x9c);
2390 if (val & (1L << 31))
2395 if (!(val & (1L << 31))) {
2396 BNX2X_ERR("Cannot acquire MCP access lock register\n");
2403 /* release split MCP access lock register */
2404 static void bnx2x_release_alr(struct bnx2x *bp)
2408 REG_WR(bp, GRCBASE_MCP + 0x9c, val);
2411 static inline u16 bnx2x_update_dsb_idx(struct bnx2x *bp)
2413 struct host_def_status_block *def_sb = bp->def_status_blk;
2416 barrier(); /* status block is written to by the chip */
2417 if (bp->def_att_idx != def_sb->atten_status_block.attn_bits_index) {
2418 bp->def_att_idx = def_sb->atten_status_block.attn_bits_index;
2421 if (bp->def_c_idx != def_sb->c_def_status_block.status_block_index) {
2422 bp->def_c_idx = def_sb->c_def_status_block.status_block_index;
2425 if (bp->def_u_idx != def_sb->u_def_status_block.status_block_index) {
2426 bp->def_u_idx = def_sb->u_def_status_block.status_block_index;
2429 if (bp->def_x_idx != def_sb->x_def_status_block.status_block_index) {
2430 bp->def_x_idx = def_sb->x_def_status_block.status_block_index;
2433 if (bp->def_t_idx != def_sb->t_def_status_block.status_block_index) {
2434 bp->def_t_idx = def_sb->t_def_status_block.status_block_index;
2441 * slow path service functions
2444 static void bnx2x_attn_int_asserted(struct bnx2x *bp, u32 asserted)
2446 int port = BP_PORT(bp);
2447 u32 hc_addr = (HC_REG_COMMAND_REG + port*32 +
2448 COMMAND_REG_ATTN_BITS_SET);
2449 u32 aeu_addr = port ? MISC_REG_AEU_MASK_ATTN_FUNC_1 :
2450 MISC_REG_AEU_MASK_ATTN_FUNC_0;
2451 u32 nig_int_mask_addr = port ? NIG_REG_MASK_INTERRUPT_PORT1 :
2452 NIG_REG_MASK_INTERRUPT_PORT0;
2455 if (bp->attn_state & asserted)
2456 BNX2X_ERR("IGU ERROR\n");
2458 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port);
2459 aeu_mask = REG_RD(bp, aeu_addr);
2461 DP(NETIF_MSG_HW, "aeu_mask %x newly asserted %x\n",
2462 aeu_mask, asserted);
2463 aeu_mask &= ~(asserted & 0xff);
2464 DP(NETIF_MSG_HW, "new mask %x\n", aeu_mask);
2466 REG_WR(bp, aeu_addr, aeu_mask);
2467 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port);
2469 DP(NETIF_MSG_HW, "attn_state %x\n", bp->attn_state);
2470 bp->attn_state |= asserted;
2471 DP(NETIF_MSG_HW, "new state %x\n", bp->attn_state);
2473 if (asserted & ATTN_HARD_WIRED_MASK) {
2474 if (asserted & ATTN_NIG_FOR_FUNC) {
2476 /* save nig interrupt mask */
2477 bp->nig_mask = REG_RD(bp, nig_int_mask_addr);
2478 REG_WR(bp, nig_int_mask_addr, 0);
2480 bnx2x_link_attn(bp);
2482 /* handle unicore attn? */
2484 if (asserted & ATTN_SW_TIMER_4_FUNC)
2485 DP(NETIF_MSG_HW, "ATTN_SW_TIMER_4_FUNC!\n");
2487 if (asserted & GPIO_2_FUNC)
2488 DP(NETIF_MSG_HW, "GPIO_2_FUNC!\n");
2490 if (asserted & GPIO_3_FUNC)
2491 DP(NETIF_MSG_HW, "GPIO_3_FUNC!\n");
2493 if (asserted & GPIO_4_FUNC)
2494 DP(NETIF_MSG_HW, "GPIO_4_FUNC!\n");
2497 if (asserted & ATTN_GENERAL_ATTN_1) {
2498 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_1!\n");
2499 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_1, 0x0);
2501 if (asserted & ATTN_GENERAL_ATTN_2) {
2502 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_2!\n");
2503 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_2, 0x0);
2505 if (asserted & ATTN_GENERAL_ATTN_3) {
2506 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_3!\n");
2507 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_3, 0x0);
2510 if (asserted & ATTN_GENERAL_ATTN_4) {
2511 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_4!\n");
2512 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_4, 0x0);
2514 if (asserted & ATTN_GENERAL_ATTN_5) {
2515 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_5!\n");
2516 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_5, 0x0);
2518 if (asserted & ATTN_GENERAL_ATTN_6) {
2519 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_6!\n");
2520 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_6, 0x0);
2524 } /* if hardwired */
2526 DP(NETIF_MSG_HW, "about to mask 0x%08x at HC addr 0x%x\n",
2528 REG_WR(bp, hc_addr, asserted);
2530 /* now set back the mask */
2531 if (asserted & ATTN_NIG_FOR_FUNC)
2532 REG_WR(bp, nig_int_mask_addr, bp->nig_mask);
2535 static inline void bnx2x_attn_int_deasserted0(struct bnx2x *bp, u32 attn)
2537 int port = BP_PORT(bp);
2541 reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 :
2542 MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0);
2544 if (attn & AEU_INPUTS_ATTN_BITS_SPIO5) {
2546 val = REG_RD(bp, reg_offset);
2547 val &= ~AEU_INPUTS_ATTN_BITS_SPIO5;
2548 REG_WR(bp, reg_offset, val);
2550 BNX2X_ERR("SPIO5 hw attention\n");
2552 switch (bp->common.board & SHARED_HW_CFG_BOARD_TYPE_MASK) {
2553 case SHARED_HW_CFG_BOARD_TYPE_BCM957710A1022G:
2554 /* Fan failure attention */
2556 /* The PHY reset is controlled by GPIO 1 */
2557 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_1,
2558 MISC_REGISTERS_GPIO_OUTPUT_LOW, port);
2559 /* Low power mode is controlled by GPIO 2 */
2560 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2,
2561 MISC_REGISTERS_GPIO_OUTPUT_LOW, port);
2562 /* mark the failure */
2563 bp->link_params.ext_phy_config &=
2564 ~PORT_HW_CFG_XGXS_EXT_PHY_TYPE_MASK;
2565 bp->link_params.ext_phy_config |=
2566 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE;
2568 dev_info.port_hw_config[port].
2569 external_phy_config,
2570 bp->link_params.ext_phy_config);
2571 /* log the failure */
2572 printk(KERN_ERR PFX "Fan Failure on Network"
2573 " Controller %s has caused the driver to"
2574 " shutdown the card to prevent permanent"
2575 " damage. Please contact Dell Support for"
2576 " assistance\n", bp->dev->name);
2584 if (attn & HW_INTERRUT_ASSERT_SET_0) {
2586 val = REG_RD(bp, reg_offset);
2587 val &= ~(attn & HW_INTERRUT_ASSERT_SET_0);
2588 REG_WR(bp, reg_offset, val);
2590 BNX2X_ERR("FATAL HW block attention set0 0x%x\n",
2591 (attn & HW_INTERRUT_ASSERT_SET_0));
2596 static inline void bnx2x_attn_int_deasserted1(struct bnx2x *bp, u32 attn)
2600 if (attn & BNX2X_DOORQ_ASSERT) {
2602 val = REG_RD(bp, DORQ_REG_DORQ_INT_STS_CLR);
2603 BNX2X_ERR("DB hw attention 0x%x\n", val);
2604 /* DORQ discard attention */
2606 BNX2X_ERR("FATAL error from DORQ\n");
2609 if (attn & HW_INTERRUT_ASSERT_SET_1) {
2611 int port = BP_PORT(bp);
2614 reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_1 :
2615 MISC_REG_AEU_ENABLE1_FUNC_0_OUT_1);
2617 val = REG_RD(bp, reg_offset);
2618 val &= ~(attn & HW_INTERRUT_ASSERT_SET_1);
2619 REG_WR(bp, reg_offset, val);
2621 BNX2X_ERR("FATAL HW block attention set1 0x%x\n",
2622 (attn & HW_INTERRUT_ASSERT_SET_1));
2627 static inline void bnx2x_attn_int_deasserted2(struct bnx2x *bp, u32 attn)
2631 if (attn & AEU_INPUTS_ATTN_BITS_CFC_HW_INTERRUPT) {
2633 val = REG_RD(bp, CFC_REG_CFC_INT_STS_CLR);
2634 BNX2X_ERR("CFC hw attention 0x%x\n", val);
2635 /* CFC error attention */
2637 BNX2X_ERR("FATAL error from CFC\n");
2640 if (attn & AEU_INPUTS_ATTN_BITS_PXP_HW_INTERRUPT) {
2642 val = REG_RD(bp, PXP_REG_PXP_INT_STS_CLR_0);
2643 BNX2X_ERR("PXP hw attention 0x%x\n", val);
2644 /* RQ_USDMDP_FIFO_OVERFLOW */
2646 BNX2X_ERR("FATAL error from PXP\n");
2649 if (attn & HW_INTERRUT_ASSERT_SET_2) {
2651 int port = BP_PORT(bp);
2654 reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_2 :
2655 MISC_REG_AEU_ENABLE1_FUNC_0_OUT_2);
2657 val = REG_RD(bp, reg_offset);
2658 val &= ~(attn & HW_INTERRUT_ASSERT_SET_2);
2659 REG_WR(bp, reg_offset, val);
2661 BNX2X_ERR("FATAL HW block attention set2 0x%x\n",
2662 (attn & HW_INTERRUT_ASSERT_SET_2));
2667 static inline void bnx2x_attn_int_deasserted3(struct bnx2x *bp, u32 attn)
2671 if (attn & EVEREST_GEN_ATTN_IN_USE_MASK) {
2673 if (attn & BNX2X_PMF_LINK_ASSERT) {
2674 int func = BP_FUNC(bp);
2676 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_12 + func*4, 0);
2677 bnx2x__link_status_update(bp);
2678 if (SHMEM_RD(bp, func_mb[func].drv_status) &
2680 bnx2x_pmf_update(bp);
2682 } else if (attn & BNX2X_MC_ASSERT_BITS) {
2684 BNX2X_ERR("MC assert!\n");
2685 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_10, 0);
2686 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_9, 0);
2687 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_8, 0);
2688 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_7, 0);
2691 } else if (attn & BNX2X_MCP_ASSERT) {
2693 BNX2X_ERR("MCP assert!\n");
2694 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_11, 0);
2698 BNX2X_ERR("Unknown HW assert! (attn 0x%x)\n", attn);
2701 if (attn & EVEREST_LATCHED_ATTN_IN_USE_MASK) {
2702 BNX2X_ERR("LATCHED attention 0x%08x (masked)\n", attn);
2703 if (attn & BNX2X_GRC_TIMEOUT) {
2704 val = CHIP_IS_E1H(bp) ?
2705 REG_RD(bp, MISC_REG_GRC_TIMEOUT_ATTN) : 0;
2706 BNX2X_ERR("GRC time-out 0x%08x\n", val);
2708 if (attn & BNX2X_GRC_RSV) {
2709 val = CHIP_IS_E1H(bp) ?
2710 REG_RD(bp, MISC_REG_GRC_RSV_ATTN) : 0;
2711 BNX2X_ERR("GRC reserved 0x%08x\n", val);
2713 REG_WR(bp, MISC_REG_AEU_CLR_LATCH_SIGNAL, 0x7ff);
2717 static void bnx2x_attn_int_deasserted(struct bnx2x *bp, u32 deasserted)
2719 struct attn_route attn;
2720 struct attn_route group_mask;
2721 int port = BP_PORT(bp);
2727 /* need to take HW lock because MCP or other port might also
2728 try to handle this event */
2729 bnx2x_acquire_alr(bp);
2731 attn.sig[0] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_1_FUNC_0 + port*4);
2732 attn.sig[1] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_2_FUNC_0 + port*4);
2733 attn.sig[2] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_3_FUNC_0 + port*4);
2734 attn.sig[3] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_4_FUNC_0 + port*4);
2735 DP(NETIF_MSG_HW, "attn: %08x %08x %08x %08x\n",
2736 attn.sig[0], attn.sig[1], attn.sig[2], attn.sig[3]);
2738 for (index = 0; index < MAX_DYNAMIC_ATTN_GRPS; index++) {
2739 if (deasserted & (1 << index)) {
2740 group_mask = bp->attn_group[index];
2742 DP(NETIF_MSG_HW, "group[%d]: %08x %08x %08x %08x\n",
2743 index, group_mask.sig[0], group_mask.sig[1],
2744 group_mask.sig[2], group_mask.sig[3]);
2746 bnx2x_attn_int_deasserted3(bp,
2747 attn.sig[3] & group_mask.sig[3]);
2748 bnx2x_attn_int_deasserted1(bp,
2749 attn.sig[1] & group_mask.sig[1]);
2750 bnx2x_attn_int_deasserted2(bp,
2751 attn.sig[2] & group_mask.sig[2]);
2752 bnx2x_attn_int_deasserted0(bp,
2753 attn.sig[0] & group_mask.sig[0]);
2755 if ((attn.sig[0] & group_mask.sig[0] &
2756 HW_PRTY_ASSERT_SET_0) ||
2757 (attn.sig[1] & group_mask.sig[1] &
2758 HW_PRTY_ASSERT_SET_1) ||
2759 (attn.sig[2] & group_mask.sig[2] &
2760 HW_PRTY_ASSERT_SET_2))
2761 BNX2X_ERR("FATAL HW block parity attention\n");
2765 bnx2x_release_alr(bp);
2767 reg_addr = (HC_REG_COMMAND_REG + port*32 + COMMAND_REG_ATTN_BITS_CLR);
2770 DP(NETIF_MSG_HW, "about to mask 0x%08x at HC addr 0x%x\n",
2772 REG_WR(bp, reg_addr, val);
2774 if (~bp->attn_state & deasserted)
2775 BNX2X_ERR("IGU ERROR\n");
2777 reg_addr = port ? MISC_REG_AEU_MASK_ATTN_FUNC_1 :
2778 MISC_REG_AEU_MASK_ATTN_FUNC_0;
2780 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port);
2781 aeu_mask = REG_RD(bp, reg_addr);
2783 DP(NETIF_MSG_HW, "aeu_mask %x newly deasserted %x\n",
2784 aeu_mask, deasserted);
2785 aeu_mask |= (deasserted & 0xff);
2786 DP(NETIF_MSG_HW, "new mask %x\n", aeu_mask);
2788 REG_WR(bp, reg_addr, aeu_mask);
2789 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port);
2791 DP(NETIF_MSG_HW, "attn_state %x\n", bp->attn_state);
2792 bp->attn_state &= ~deasserted;
2793 DP(NETIF_MSG_HW, "new state %x\n", bp->attn_state);
2796 static void bnx2x_attn_int(struct bnx2x *bp)
2798 /* read local copy of bits */
2799 u32 attn_bits = bp->def_status_blk->atten_status_block.attn_bits;
2800 u32 attn_ack = bp->def_status_blk->atten_status_block.attn_bits_ack;
2801 u32 attn_state = bp->attn_state;
2803 /* look for changed bits */
2804 u32 asserted = attn_bits & ~attn_ack & ~attn_state;
2805 u32 deasserted = ~attn_bits & attn_ack & attn_state;
2808 "attn_bits %x attn_ack %x asserted %x deasserted %x\n",
2809 attn_bits, attn_ack, asserted, deasserted);
2811 if (~(attn_bits ^ attn_ack) & (attn_bits ^ attn_state))
2812 BNX2X_ERR("BAD attention state\n");
2814 /* handle bits that were raised */
2816 bnx2x_attn_int_asserted(bp, asserted);
2819 bnx2x_attn_int_deasserted(bp, deasserted);
2822 static void bnx2x_sp_task(struct work_struct *work)
2824 struct bnx2x *bp = container_of(work, struct bnx2x, sp_task);
2828 /* Return here if interrupt is disabled */
2829 if (unlikely(atomic_read(&bp->intr_sem) != 0)) {
2830 DP(BNX2X_MSG_SP, "called but intr_sem not 0, returning\n");
2834 status = bnx2x_update_dsb_idx(bp);
2835 /* if (status == 0) */
2836 /* BNX2X_ERR("spurious slowpath interrupt!\n"); */
2838 DP(BNX2X_MSG_SP, "got a slowpath interrupt (updated %x)\n", status);
2844 /* CStorm events: query_stats, port delete ramrod */
2846 bp->stats_pending = 0;
2848 bnx2x_ack_sb(bp, DEF_SB_ID, ATTENTION_ID, bp->def_att_idx,
2850 bnx2x_ack_sb(bp, DEF_SB_ID, USTORM_ID, le16_to_cpu(bp->def_u_idx),
2852 bnx2x_ack_sb(bp, DEF_SB_ID, CSTORM_ID, le16_to_cpu(bp->def_c_idx),
2854 bnx2x_ack_sb(bp, DEF_SB_ID, XSTORM_ID, le16_to_cpu(bp->def_x_idx),
2856 bnx2x_ack_sb(bp, DEF_SB_ID, TSTORM_ID, le16_to_cpu(bp->def_t_idx),
2861 static irqreturn_t bnx2x_msix_sp_int(int irq, void *dev_instance)
2863 struct net_device *dev = dev_instance;
2864 struct bnx2x *bp = netdev_priv(dev);
2866 /* Return here if interrupt is disabled */
2867 if (unlikely(atomic_read(&bp->intr_sem) != 0)) {
2868 DP(BNX2X_MSG_SP, "called but intr_sem not 0, returning\n");
2872 bnx2x_ack_sb(bp, DEF_SB_ID, XSTORM_ID, 0, IGU_INT_DISABLE, 0);
2874 #ifdef BNX2X_STOP_ON_ERROR
2875 if (unlikely(bp->panic))
2879 schedule_work(&bp->sp_task);
2884 /* end of slow path */
2888 /****************************************************************************
2890 ****************************************************************************/
2892 /* sum[hi:lo] += add[hi:lo] */
2893 #define ADD_64(s_hi, a_hi, s_lo, a_lo) \
2896 s_hi += a_hi + (s_lo < a_lo) ? 1 : 0; \
2899 /* difference = minuend - subtrahend */
2900 #define DIFF_64(d_hi, m_hi, s_hi, d_lo, m_lo, s_lo) \
2902 if (m_lo < s_lo) { \
2904 d_hi = m_hi - s_hi; \
2906 /* we can 'loan' 1 */ \
2908 d_lo = m_lo + (UINT_MAX - s_lo) + 1; \
2910 /* m_hi <= s_hi */ \
2915 /* m_lo >= s_lo */ \
2916 if (m_hi < s_hi) { \
2920 /* m_hi >= s_hi */ \
2921 d_hi = m_hi - s_hi; \
2922 d_lo = m_lo - s_lo; \
2927 #define UPDATE_STAT64(s, t) \
2929 DIFF_64(diff.hi, new->s##_hi, pstats->mac_stx[0].t##_hi, \
2930 diff.lo, new->s##_lo, pstats->mac_stx[0].t##_lo); \
2931 pstats->mac_stx[0].t##_hi = new->s##_hi; \
2932 pstats->mac_stx[0].t##_lo = new->s##_lo; \
2933 ADD_64(pstats->mac_stx[1].t##_hi, diff.hi, \
2934 pstats->mac_stx[1].t##_lo, diff.lo); \
2937 #define UPDATE_STAT64_NIG(s, t) \
2939 DIFF_64(diff.hi, new->s##_hi, old->s##_hi, \
2940 diff.lo, new->s##_lo, old->s##_lo); \
2941 ADD_64(estats->t##_hi, diff.hi, \
2942 estats->t##_lo, diff.lo); \
2945 /* sum[hi:lo] += add */
2946 #define ADD_EXTEND_64(s_hi, s_lo, a) \
2949 s_hi += (s_lo < a) ? 1 : 0; \
2952 #define UPDATE_EXTEND_STAT(s) \
2954 ADD_EXTEND_64(pstats->mac_stx[1].s##_hi, \
2955 pstats->mac_stx[1].s##_lo, \
2959 #define UPDATE_EXTEND_TSTAT(s, t) \
2961 diff = le32_to_cpu(tclient->s) - old_tclient->s; \
2962 old_tclient->s = le32_to_cpu(tclient->s); \
2963 ADD_EXTEND_64(fstats->t##_hi, fstats->t##_lo, diff); \
2966 #define UPDATE_EXTEND_XSTAT(s, t) \
2968 diff = le32_to_cpu(xclient->s) - old_xclient->s; \
2969 old_xclient->s = le32_to_cpu(xclient->s); \
2970 ADD_EXTEND_64(fstats->t##_hi, fstats->t##_lo, diff); \
2974 * General service functions
2977 static inline long bnx2x_hilo(u32 *hiref)
2979 u32 lo = *(hiref + 1);
2980 #if (BITS_PER_LONG == 64)
2983 return HILO_U64(hi, lo);
2990 * Init service functions
2993 static void bnx2x_storm_stats_post(struct bnx2x *bp)
2995 if (!bp->stats_pending) {
2996 struct eth_query_ramrod_data ramrod_data = {0};
2999 ramrod_data.drv_counter = bp->stats_counter++;
3000 ramrod_data.collect_port_1b = bp->port.pmf ? 1 : 0;
3001 ramrod_data.ctr_id_vector = (1 << BP_CL_ID(bp));
3003 rc = bnx2x_sp_post(bp, RAMROD_CMD_ID_ETH_STAT_QUERY, 0,
3004 ((u32 *)&ramrod_data)[1],
3005 ((u32 *)&ramrod_data)[0], 0);
3007 /* stats ramrod has it's own slot on the spq */
3009 bp->stats_pending = 1;
3014 static void bnx2x_stats_init(struct bnx2x *bp)
3016 int port = BP_PORT(bp);
3018 bp->executer_idx = 0;
3019 bp->stats_counter = 0;
3023 bp->port.port_stx = SHMEM_RD(bp, port_mb[port].port_stx);
3025 bp->port.port_stx = 0;
3026 DP(BNX2X_MSG_STATS, "port_stx 0x%x\n", bp->port.port_stx);
3028 memset(&(bp->port.old_nig_stats), 0, sizeof(struct nig_stats));
3029 bp->port.old_nig_stats.brb_discard =
3030 REG_RD(bp, NIG_REG_STAT0_BRB_DISCARD + port*0x38);
3031 bp->port.old_nig_stats.brb_truncate =
3032 REG_RD(bp, NIG_REG_STAT0_BRB_TRUNCATE + port*0x38);
3033 REG_RD_DMAE(bp, NIG_REG_STAT0_EGRESS_MAC_PKT0 + port*0x50,
3034 &(bp->port.old_nig_stats.egress_mac_pkt0_lo), 2);
3035 REG_RD_DMAE(bp, NIG_REG_STAT0_EGRESS_MAC_PKT1 + port*0x50,
3036 &(bp->port.old_nig_stats.egress_mac_pkt1_lo), 2);
3038 /* function stats */
3039 memset(&bp->dev->stats, 0, sizeof(struct net_device_stats));
3040 memset(&bp->old_tclient, 0, sizeof(struct tstorm_per_client_stats));
3041 memset(&bp->old_xclient, 0, sizeof(struct xstorm_per_client_stats));
3042 memset(&bp->eth_stats, 0, sizeof(struct bnx2x_eth_stats));
3044 bp->stats_state = STATS_STATE_DISABLED;
3045 if (IS_E1HMF(bp) && bp->port.pmf && bp->port.port_stx)
3046 bnx2x_stats_handle(bp, STATS_EVENT_PMF);
3049 static void bnx2x_hw_stats_post(struct bnx2x *bp)
3051 struct dmae_command *dmae = &bp->stats_dmae;
3052 u32 *stats_comp = bnx2x_sp(bp, stats_comp);
3054 *stats_comp = DMAE_COMP_VAL;
3057 if (bp->executer_idx) {
3058 int loader_idx = PMF_DMAE_C(bp);
3060 memset(dmae, 0, sizeof(struct dmae_command));
3062 dmae->opcode = (DMAE_CMD_SRC_PCI | DMAE_CMD_DST_GRC |
3063 DMAE_CMD_C_DST_GRC | DMAE_CMD_C_ENABLE |
3064 DMAE_CMD_DST_RESET |
3066 DMAE_CMD_ENDIANITY_B_DW_SWAP |
3068 DMAE_CMD_ENDIANITY_DW_SWAP |
3070 (BP_PORT(bp) ? DMAE_CMD_PORT_1 :
3072 (BP_E1HVN(bp) << DMAE_CMD_E1HVN_SHIFT));
3073 dmae->src_addr_lo = U64_LO(bnx2x_sp_mapping(bp, dmae[0]));
3074 dmae->src_addr_hi = U64_HI(bnx2x_sp_mapping(bp, dmae[0]));
3075 dmae->dst_addr_lo = (DMAE_REG_CMD_MEM +
3076 sizeof(struct dmae_command) *
3077 (loader_idx + 1)) >> 2;
3078 dmae->dst_addr_hi = 0;
3079 dmae->len = sizeof(struct dmae_command) >> 2;
3082 dmae->comp_addr_lo = dmae_reg_go_c[loader_idx + 1] >> 2;
3083 dmae->comp_addr_hi = 0;
3087 bnx2x_post_dmae(bp, dmae, loader_idx);
3089 } else if (bp->func_stx) {
3091 bnx2x_post_dmae(bp, dmae, INIT_DMAE_C(bp));
3095 static int bnx2x_stats_comp(struct bnx2x *bp)
3097 u32 *stats_comp = bnx2x_sp(bp, stats_comp);
3101 while (*stats_comp != DMAE_COMP_VAL) {
3103 BNX2X_ERR("timeout waiting for stats finished\n");
3113 * Statistics service functions
3116 static void bnx2x_stats_pmf_update(struct bnx2x *bp)
3118 struct dmae_command *dmae;
3120 int loader_idx = PMF_DMAE_C(bp);
3121 u32 *stats_comp = bnx2x_sp(bp, stats_comp);
3124 if (!IS_E1HMF(bp) || !bp->port.pmf || !bp->port.port_stx) {
3125 BNX2X_ERR("BUG!\n");
3129 bp->executer_idx = 0;
3131 opcode = (DMAE_CMD_SRC_GRC | DMAE_CMD_DST_PCI |
3133 DMAE_CMD_SRC_RESET | DMAE_CMD_DST_RESET |
3135 DMAE_CMD_ENDIANITY_B_DW_SWAP |
3137 DMAE_CMD_ENDIANITY_DW_SWAP |
3139 (BP_PORT(bp) ? DMAE_CMD_PORT_1 : DMAE_CMD_PORT_0) |
3140 (BP_E1HVN(bp) << DMAE_CMD_E1HVN_SHIFT));
3142 dmae = bnx2x_sp(bp, dmae[bp->executer_idx++]);
3143 dmae->opcode = (opcode | DMAE_CMD_C_DST_GRC);
3144 dmae->src_addr_lo = bp->port.port_stx >> 2;
3145 dmae->src_addr_hi = 0;
3146 dmae->dst_addr_lo = U64_LO(bnx2x_sp_mapping(bp, port_stats));
3147 dmae->dst_addr_hi = U64_HI(bnx2x_sp_mapping(bp, port_stats));
3148 dmae->len = DMAE_LEN32_RD_MAX;
3149 dmae->comp_addr_lo = dmae_reg_go_c[loader_idx] >> 2;
3150 dmae->comp_addr_hi = 0;
3153 dmae = bnx2x_sp(bp, dmae[bp->executer_idx++]);
3154 dmae->opcode = (opcode | DMAE_CMD_C_DST_PCI);
3155 dmae->src_addr_lo = (bp->port.port_stx >> 2) + DMAE_LEN32_RD_MAX;
3156 dmae->src_addr_hi = 0;
3157 dmae->dst_addr_lo = U64_LO(bnx2x_sp_mapping(bp, port_stats) +
3158 DMAE_LEN32_RD_MAX * 4);
3159 dmae->dst_addr_hi = U64_HI(bnx2x_sp_mapping(bp, port_stats) +
3160 DMAE_LEN32_RD_MAX * 4);
3161 dmae->len = (sizeof(struct host_port_stats) >> 2) - DMAE_LEN32_RD_MAX;
3162 dmae->comp_addr_lo = U64_LO(bnx2x_sp_mapping(bp, stats_comp));
3163 dmae->comp_addr_hi = U64_HI(bnx2x_sp_mapping(bp, stats_comp));
3164 dmae->comp_val = DMAE_COMP_VAL;
3167 bnx2x_hw_stats_post(bp);
3168 bnx2x_stats_comp(bp);
3171 static void bnx2x_port_stats_init(struct bnx2x *bp)
3173 struct dmae_command *dmae;
3174 int port = BP_PORT(bp);
3175 int vn = BP_E1HVN(bp);
3177 int loader_idx = PMF_DMAE_C(bp);
3179 u32 *stats_comp = bnx2x_sp(bp, stats_comp);
3182 if (!bp->link_vars.link_up || !bp->port.pmf) {
3183 BNX2X_ERR("BUG!\n");
3187 bp->executer_idx = 0;
3190 opcode = (DMAE_CMD_SRC_PCI | DMAE_CMD_DST_GRC |
3191 DMAE_CMD_C_DST_GRC | DMAE_CMD_C_ENABLE |
3192 DMAE_CMD_SRC_RESET | DMAE_CMD_DST_RESET |
3194 DMAE_CMD_ENDIANITY_B_DW_SWAP |
3196 DMAE_CMD_ENDIANITY_DW_SWAP |
3198 (port ? DMAE_CMD_PORT_1 : DMAE_CMD_PORT_0) |
3199 (vn << DMAE_CMD_E1HVN_SHIFT));
3201 if (bp->port.port_stx) {
3203 dmae = bnx2x_sp(bp, dmae[bp->executer_idx++]);
3204 dmae->opcode = opcode;
3205 dmae->src_addr_lo = U64_LO(bnx2x_sp_mapping(bp, port_stats));
3206 dmae->src_addr_hi = U64_HI(bnx2x_sp_mapping(bp, port_stats));
3207 dmae->dst_addr_lo = bp->port.port_stx >> 2;
3208 dmae->dst_addr_hi = 0;
3209 dmae->len = sizeof(struct host_port_stats) >> 2;
3210 dmae->comp_addr_lo = dmae_reg_go_c[loader_idx] >> 2;
3211 dmae->comp_addr_hi = 0;
3217 dmae = bnx2x_sp(bp, dmae[bp->executer_idx++]);
3218 dmae->opcode = opcode;
3219 dmae->src_addr_lo = U64_LO(bnx2x_sp_mapping(bp, func_stats));
3220 dmae->src_addr_hi = U64_HI(bnx2x_sp_mapping(bp, func_stats));
3221 dmae->dst_addr_lo = bp->func_stx >> 2;
3222 dmae->dst_addr_hi = 0;
3223 dmae->len = sizeof(struct host_func_stats) >> 2;
3224 dmae->comp_addr_lo = dmae_reg_go_c[loader_idx] >> 2;
3225 dmae->comp_addr_hi = 0;
3230 opcode = (DMAE_CMD_SRC_GRC | DMAE_CMD_DST_PCI |
3231 DMAE_CMD_C_DST_GRC | DMAE_CMD_C_ENABLE |
3232 DMAE_CMD_SRC_RESET | DMAE_CMD_DST_RESET |
3234 DMAE_CMD_ENDIANITY_B_DW_SWAP |
3236 DMAE_CMD_ENDIANITY_DW_SWAP |
3238 (port ? DMAE_CMD_PORT_1 : DMAE_CMD_PORT_0) |
3239 (vn << DMAE_CMD_E1HVN_SHIFT));
3241 if (bp->link_vars.mac_type == MAC_TYPE_BMAC) {
3243 mac_addr = (port ? NIG_REG_INGRESS_BMAC1_MEM :
3244 NIG_REG_INGRESS_BMAC0_MEM);
3246 /* BIGMAC_REGISTER_TX_STAT_GTPKT ..
3247 BIGMAC_REGISTER_TX_STAT_GTBYT */
3248 dmae = bnx2x_sp(bp, dmae[bp->executer_idx++]);
3249 dmae->opcode = opcode;
3250 dmae->src_addr_lo = (mac_addr +
3251 BIGMAC_REGISTER_TX_STAT_GTPKT) >> 2;
3252 dmae->src_addr_hi = 0;
3253 dmae->dst_addr_lo = U64_LO(bnx2x_sp_mapping(bp, mac_stats));
3254 dmae->dst_addr_hi = U64_HI(bnx2x_sp_mapping(bp, mac_stats));
3255 dmae->len = (8 + BIGMAC_REGISTER_TX_STAT_GTBYT -
3256 BIGMAC_REGISTER_TX_STAT_GTPKT) >> 2;
3257 dmae->comp_addr_lo = dmae_reg_go_c[loader_idx] >> 2;
3258 dmae->comp_addr_hi = 0;
3261 /* BIGMAC_REGISTER_RX_STAT_GR64 ..
3262 BIGMAC_REGISTER_RX_STAT_GRIPJ */
3263 dmae = bnx2x_sp(bp, dmae[bp->executer_idx++]);
3264 dmae->opcode = opcode;
3265 dmae->src_addr_lo = (mac_addr +
3266 BIGMAC_REGISTER_RX_STAT_GR64) >> 2;
3267 dmae->src_addr_hi = 0;
3268 dmae->dst_addr_lo = U64_LO(bnx2x_sp_mapping(bp, mac_stats) +
3269 offsetof(struct bmac_stats, rx_stat_gr64_lo));
3270 dmae->dst_addr_hi = U64_HI(bnx2x_sp_mapping(bp, mac_stats) +
3271 offsetof(struct bmac_stats, rx_stat_gr64_lo));
3272 dmae->len = (8 + BIGMAC_REGISTER_RX_STAT_GRIPJ -
3273 BIGMAC_REGISTER_RX_STAT_GR64) >> 2;
3274 dmae->comp_addr_lo = dmae_reg_go_c[loader_idx] >> 2;
3275 dmae->comp_addr_hi = 0;
3278 } else if (bp->link_vars.mac_type == MAC_TYPE_EMAC) {
3280 mac_addr = (port ? GRCBASE_EMAC1 : GRCBASE_EMAC0);
3282 /* EMAC_REG_EMAC_RX_STAT_AC (EMAC_REG_EMAC_RX_STAT_AC_COUNT)*/
3283 dmae = bnx2x_sp(bp, dmae[bp->executer_idx++]);
3284 dmae->opcode = opcode;
3285 dmae->src_addr_lo = (mac_addr +
3286 EMAC_REG_EMAC_RX_STAT_AC) >> 2;
3287 dmae->src_addr_hi = 0;
3288 dmae->dst_addr_lo = U64_LO(bnx2x_sp_mapping(bp, mac_stats));
3289 dmae->dst_addr_hi = U64_HI(bnx2x_sp_mapping(bp, mac_stats));
3290 dmae->len = EMAC_REG_EMAC_RX_STAT_AC_COUNT;
3291 dmae->comp_addr_lo = dmae_reg_go_c[loader_idx] >> 2;
3292 dmae->comp_addr_hi = 0;
3295 /* EMAC_REG_EMAC_RX_STAT_AC_28 */
3296 dmae = bnx2x_sp(bp, dmae[bp->executer_idx++]);
3297 dmae->opcode = opcode;
3298 dmae->src_addr_lo = (mac_addr +
3299 EMAC_REG_EMAC_RX_STAT_AC_28) >> 2;
3300 dmae->src_addr_hi = 0;
3301 dmae->dst_addr_lo = U64_LO(bnx2x_sp_mapping(bp, mac_stats) +
3302 offsetof(struct emac_stats, rx_stat_falsecarriererrors));
3303 dmae->dst_addr_hi = U64_HI(bnx2x_sp_mapping(bp, mac_stats) +
3304 offsetof(struct emac_stats, rx_stat_falsecarriererrors));
3306 dmae->comp_addr_lo = dmae_reg_go_c[loader_idx] >> 2;
3307 dmae->comp_addr_hi = 0;
3310 /* EMAC_REG_EMAC_TX_STAT_AC (EMAC_REG_EMAC_TX_STAT_AC_COUNT)*/
3311 dmae = bnx2x_sp(bp, dmae[bp->executer_idx++]);
3312 dmae->opcode = opcode;
3313 dmae->src_addr_lo = (mac_addr +
3314 EMAC_REG_EMAC_TX_STAT_AC) >> 2;
3315 dmae->src_addr_hi = 0;
3316 dmae->dst_addr_lo = U64_LO(bnx2x_sp_mapping(bp, mac_stats) +
3317 offsetof(struct emac_stats, tx_stat_ifhcoutoctets));
3318 dmae->dst_addr_hi = U64_HI(bnx2x_sp_mapping(bp, mac_stats) +
3319 offsetof(struct emac_stats, tx_stat_ifhcoutoctets));
3320 dmae->len = EMAC_REG_EMAC_TX_STAT_AC_COUNT;
3321 dmae->comp_addr_lo = dmae_reg_go_c[loader_idx] >> 2;
3322 dmae->comp_addr_hi = 0;
3327 dmae = bnx2x_sp(bp, dmae[bp->executer_idx++]);
3328 dmae->opcode = opcode;
3329 dmae->src_addr_lo = (port ? NIG_REG_STAT1_BRB_DISCARD :
3330 NIG_REG_STAT0_BRB_DISCARD) >> 2;
3331 dmae->src_addr_hi = 0;
3332 dmae->dst_addr_lo = U64_LO(bnx2x_sp_mapping(bp, nig_stats));
3333 dmae->dst_addr_hi = U64_HI(bnx2x_sp_mapping(bp, nig_stats));
3334 dmae->len = (sizeof(struct nig_stats) - 4*sizeof(u32)) >> 2;
3335 dmae->comp_addr_lo = dmae_reg_go_c[loader_idx] >> 2;
3336 dmae->comp_addr_hi = 0;
3339 dmae = bnx2x_sp(bp, dmae[bp->executer_idx++]);
3340 dmae->opcode = opcode;
3341 dmae->src_addr_lo = (port ? NIG_REG_STAT1_EGRESS_MAC_PKT0 :
3342 NIG_REG_STAT0_EGRESS_MAC_PKT0) >> 2;
3343 dmae->src_addr_hi = 0;
3344 dmae->dst_addr_lo = U64_LO(bnx2x_sp_mapping(bp, nig_stats) +
3345 offsetof(struct nig_stats, egress_mac_pkt0_lo));
3346 dmae->dst_addr_hi = U64_HI(bnx2x_sp_mapping(bp, nig_stats) +
3347 offsetof(struct nig_stats, egress_mac_pkt0_lo));
3348 dmae->len = (2*sizeof(u32)) >> 2;
3349 dmae->comp_addr_lo = dmae_reg_go_c[loader_idx] >> 2;
3350 dmae->comp_addr_hi = 0;
3353 dmae = bnx2x_sp(bp, dmae[bp->executer_idx++]);
3354 dmae->opcode = (DMAE_CMD_SRC_GRC | DMAE_CMD_DST_PCI |
3355 DMAE_CMD_C_DST_PCI | DMAE_CMD_C_ENABLE |
3356 DMAE_CMD_SRC_RESET | DMAE_CMD_DST_RESET |
3358 DMAE_CMD_ENDIANITY_B_DW_SWAP |
3360 DMAE_CMD_ENDIANITY_DW_SWAP |
3362 (port ? DMAE_CMD_PORT_1 : DMAE_CMD_PORT_0) |
3363 (vn << DMAE_CMD_E1HVN_SHIFT));
3364 dmae->src_addr_lo = (port ? NIG_REG_STAT1_EGRESS_MAC_PKT1 :
3365 NIG_REG_STAT0_EGRESS_MAC_PKT1) >> 2;
3366 dmae->src_addr_hi = 0;
3367 dmae->dst_addr_lo = U64_LO(bnx2x_sp_mapping(bp, nig_stats) +
3368 offsetof(struct nig_stats, egress_mac_pkt1_lo));
3369 dmae->dst_addr_hi = U64_HI(bnx2x_sp_mapping(bp, nig_stats) +
3370 offsetof(struct nig_stats, egress_mac_pkt1_lo));
3371 dmae->len = (2*sizeof(u32)) >> 2;
3372 dmae->comp_addr_lo = U64_LO(bnx2x_sp_mapping(bp, stats_comp));
3373 dmae->comp_addr_hi = U64_HI(bnx2x_sp_mapping(bp, stats_comp));
3374 dmae->comp_val = DMAE_COMP_VAL;
3379 static void bnx2x_func_stats_init(struct bnx2x *bp)
3381 struct dmae_command *dmae = &bp->stats_dmae;
3382 u32 *stats_comp = bnx2x_sp(bp, stats_comp);
3385 if (!bp->func_stx) {
3386 BNX2X_ERR("BUG!\n");
3390 bp->executer_idx = 0;
3391 memset(dmae, 0, sizeof(struct dmae_command));
3393 dmae->opcode = (DMAE_CMD_SRC_PCI | DMAE_CMD_DST_GRC |
3394 DMAE_CMD_C_DST_PCI | DMAE_CMD_C_ENABLE |
3395 DMAE_CMD_SRC_RESET | DMAE_CMD_DST_RESET |
3397 DMAE_CMD_ENDIANITY_B_DW_SWAP |
3399 DMAE_CMD_ENDIANITY_DW_SWAP |
3401 (BP_PORT(bp) ? DMAE_CMD_PORT_1 : DMAE_CMD_PORT_0) |
3402 (BP_E1HVN(bp) << DMAE_CMD_E1HVN_SHIFT));
3403 dmae->src_addr_lo = U64_LO(bnx2x_sp_mapping(bp, func_stats));
3404 dmae->src_addr_hi = U64_HI(bnx2x_sp_mapping(bp, func_stats));
3405 dmae->dst_addr_lo = bp->func_stx >> 2;
3406 dmae->dst_addr_hi = 0;
3407 dmae->len = sizeof(struct host_func_stats) >> 2;
3408 dmae->comp_addr_lo = U64_LO(bnx2x_sp_mapping(bp, stats_comp));
3409 dmae->comp_addr_hi = U64_HI(bnx2x_sp_mapping(bp, stats_comp));
3410 dmae->comp_val = DMAE_COMP_VAL;
3415 static void bnx2x_stats_start(struct bnx2x *bp)
3418 bnx2x_port_stats_init(bp);
3420 else if (bp->func_stx)
3421 bnx2x_func_stats_init(bp);
3423 bnx2x_hw_stats_post(bp);
3424 bnx2x_storm_stats_post(bp);
3427 static void bnx2x_stats_pmf_start(struct bnx2x *bp)
3429 bnx2x_stats_comp(bp);
3430 bnx2x_stats_pmf_update(bp);
3431 bnx2x_stats_start(bp);
3434 static void bnx2x_stats_restart(struct bnx2x *bp)
3436 bnx2x_stats_comp(bp);
3437 bnx2x_stats_start(bp);
3440 static void bnx2x_bmac_stats_update(struct bnx2x *bp)
3442 struct bmac_stats *new = bnx2x_sp(bp, mac_stats.bmac_stats);
3443 struct host_port_stats *pstats = bnx2x_sp(bp, port_stats);
3444 struct regpair diff;
3446 UPDATE_STAT64(rx_stat_grerb, rx_stat_ifhcinbadoctets);
3447 UPDATE_STAT64(rx_stat_grfcs, rx_stat_dot3statsfcserrors);
3448 UPDATE_STAT64(rx_stat_grund, rx_stat_etherstatsundersizepkts);
3449 UPDATE_STAT64(rx_stat_grovr, rx_stat_dot3statsframestoolong);
3450 UPDATE_STAT64(rx_stat_grfrg, rx_stat_etherstatsfragments);
3451 UPDATE_STAT64(rx_stat_grjbr, rx_stat_etherstatsjabbers);
3452 UPDATE_STAT64(rx_stat_grxcf, rx_stat_maccontrolframesreceived);
3453 UPDATE_STAT64(rx_stat_grxpf, rx_stat_xoffstateentered);
3454 UPDATE_STAT64(rx_stat_grxpf, rx_stat_xoffpauseframesreceived);
3455 UPDATE_STAT64(tx_stat_gtxpf, tx_stat_outxoffsent);
3456 UPDATE_STAT64(tx_stat_gtxpf, tx_stat_flowcontroldone);
3457 UPDATE_STAT64(tx_stat_gt64, tx_stat_etherstatspkts64octets);
3458 UPDATE_STAT64(tx_stat_gt127,
3459 tx_stat_etherstatspkts65octetsto127octets);
3460 UPDATE_STAT64(tx_stat_gt255,
3461 tx_stat_etherstatspkts128octetsto255octets);
3462 UPDATE_STAT64(tx_stat_gt511,
3463 tx_stat_etherstatspkts256octetsto511octets);
3464 UPDATE_STAT64(tx_stat_gt1023,
3465 tx_stat_etherstatspkts512octetsto1023octets);
3466 UPDATE_STAT64(tx_stat_gt1518,
3467 tx_stat_etherstatspkts1024octetsto1522octets);
3468 UPDATE_STAT64(tx_stat_gt2047, tx_stat_bmac_2047);
3469 UPDATE_STAT64(tx_stat_gt4095, tx_stat_bmac_4095);
3470 UPDATE_STAT64(tx_stat_gt9216, tx_stat_bmac_9216);
3471 UPDATE_STAT64(tx_stat_gt16383, tx_stat_bmac_16383);
3472 UPDATE_STAT64(tx_stat_gterr,
3473 tx_stat_dot3statsinternalmactransmiterrors);
3474 UPDATE_STAT64(tx_stat_gtufl, tx_stat_bmac_ufl);
3477 static void bnx2x_emac_stats_update(struct bnx2x *bp)
3479 struct emac_stats *new = bnx2x_sp(bp, mac_stats.emac_stats);
3480 struct host_port_stats *pstats = bnx2x_sp(bp, port_stats);
3482 UPDATE_EXTEND_STAT(rx_stat_ifhcinbadoctets);
3483 UPDATE_EXTEND_STAT(tx_stat_ifhcoutbadoctets);
3484 UPDATE_EXTEND_STAT(rx_stat_dot3statsfcserrors);
3485 UPDATE_EXTEND_STAT(rx_stat_dot3statsalignmenterrors);
3486 UPDATE_EXTEND_STAT(rx_stat_dot3statscarriersenseerrors);
3487 UPDATE_EXTEND_STAT(rx_stat_falsecarriererrors);
3488 UPDATE_EXTEND_STAT(rx_stat_etherstatsundersizepkts);
3489 UPDATE_EXTEND_STAT(rx_stat_dot3statsframestoolong);
3490 UPDATE_EXTEND_STAT(rx_stat_etherstatsfragments);
3491 UPDATE_EXTEND_STAT(rx_stat_etherstatsjabbers);
3492 UPDATE_EXTEND_STAT(rx_stat_maccontrolframesreceived);
3493 UPDATE_EXTEND_STAT(rx_stat_xoffstateentered);
3494 UPDATE_EXTEND_STAT(rx_stat_xonpauseframesreceived);
3495 UPDATE_EXTEND_STAT(rx_stat_xoffpauseframesreceived);
3496 UPDATE_EXTEND_STAT(tx_stat_outxonsent);
3497 UPDATE_EXTEND_STAT(tx_stat_outxoffsent);
3498 UPDATE_EXTEND_STAT(tx_stat_flowcontroldone);
3499 UPDATE_EXTEND_STAT(tx_stat_etherstatscollisions);
3500 UPDATE_EXTEND_STAT(tx_stat_dot3statssinglecollisionframes);
3501 UPDATE_EXTEND_STAT(tx_stat_dot3statsmultiplecollisionframes);
3502 UPDATE_EXTEND_STAT(tx_stat_dot3statsdeferredtransmissions);
3503 UPDATE_EXTEND_STAT(tx_stat_dot3statsexcessivecollisions);
3504 UPDATE_EXTEND_STAT(tx_stat_dot3statslatecollisions);
3505 UPDATE_EXTEND_STAT(tx_stat_etherstatspkts64octets);
3506 UPDATE_EXTEND_STAT(tx_stat_etherstatspkts65octetsto127octets);
3507 UPDATE_EXTEND_STAT(tx_stat_etherstatspkts128octetsto255octets);
3508 UPDATE_EXTEND_STAT(tx_stat_etherstatspkts256octetsto511octets);
3509 UPDATE_EXTEND_STAT(tx_stat_etherstatspkts512octetsto1023octets);
3510 UPDATE_EXTEND_STAT(tx_stat_etherstatspkts1024octetsto1522octets);
3511 UPDATE_EXTEND_STAT(tx_stat_etherstatspktsover1522octets);
3512 UPDATE_EXTEND_STAT(tx_stat_dot3statsinternalmactransmiterrors);
3515 static int bnx2x_hw_stats_update(struct bnx2x *bp)
3517 struct nig_stats *new = bnx2x_sp(bp, nig_stats);
3518 struct nig_stats *old = &(bp->port.old_nig_stats);
3519 struct host_port_stats *pstats = bnx2x_sp(bp, port_stats);
3520 struct bnx2x_eth_stats *estats = &bp->eth_stats;
3521 struct regpair diff;
3523 if (bp->link_vars.mac_type == MAC_TYPE_BMAC)
3524 bnx2x_bmac_stats_update(bp);
3526 else if (bp->link_vars.mac_type == MAC_TYPE_EMAC)
3527 bnx2x_emac_stats_update(bp);
3529 else { /* unreached */
3530 BNX2X_ERR("stats updated by dmae but no MAC active\n");
3534 ADD_EXTEND_64(pstats->brb_drop_hi, pstats->brb_drop_lo,
3535 new->brb_discard - old->brb_discard);
3536 ADD_EXTEND_64(estats->brb_truncate_hi, estats->brb_truncate_lo,
3537 new->brb_truncate - old->brb_truncate);
3539 UPDATE_STAT64_NIG(egress_mac_pkt0,
3540 etherstatspkts1024octetsto1522octets);
3541 UPDATE_STAT64_NIG(egress_mac_pkt1, etherstatspktsover1522octets);
3543 memcpy(old, new, sizeof(struct nig_stats));
3545 memcpy(&(estats->rx_stat_ifhcinbadoctets_hi), &(pstats->mac_stx[1]),
3546 sizeof(struct mac_stx));
3547 estats->brb_drop_hi = pstats->brb_drop_hi;
3548 estats->brb_drop_lo = pstats->brb_drop_lo;
3550 pstats->host_port_stats_start = ++pstats->host_port_stats_end;
3555 static int bnx2x_storm_stats_update(struct bnx2x *bp)
3557 struct eth_stats_query *stats = bnx2x_sp(bp, fw_stats);
3558 int cl_id = BP_CL_ID(bp);
3559 struct tstorm_per_port_stats *tport =
3560 &stats->tstorm_common.port_statistics;
3561 struct tstorm_per_client_stats *tclient =
3562 &stats->tstorm_common.client_statistics[cl_id];
3563 struct tstorm_per_client_stats *old_tclient = &bp->old_tclient;
3564 struct xstorm_per_client_stats *xclient =
3565 &stats->xstorm_common.client_statistics[cl_id];
3566 struct xstorm_per_client_stats *old_xclient = &bp->old_xclient;
3567 struct host_func_stats *fstats = bnx2x_sp(bp, func_stats);
3568 struct bnx2x_eth_stats *estats = &bp->eth_stats;
3571 /* are storm stats valid? */
3572 if ((u16)(le16_to_cpu(tclient->stats_counter) + 1) !=
3573 bp->stats_counter) {
3574 DP(BNX2X_MSG_STATS, "stats not updated by tstorm"
3575 " tstorm counter (%d) != stats_counter (%d)\n",
3576 tclient->stats_counter, bp->stats_counter);
3579 if ((u16)(le16_to_cpu(xclient->stats_counter) + 1) !=
3580 bp->stats_counter) {
3581 DP(BNX2X_MSG_STATS, "stats not updated by xstorm"
3582 " xstorm counter (%d) != stats_counter (%d)\n",
3583 xclient->stats_counter, bp->stats_counter);
3587 fstats->total_bytes_received_hi =
3588 fstats->valid_bytes_received_hi =
3589 le32_to_cpu(tclient->total_rcv_bytes.hi);
3590 fstats->total_bytes_received_lo =
3591 fstats->valid_bytes_received_lo =
3592 le32_to_cpu(tclient->total_rcv_bytes.lo);
3594 estats->error_bytes_received_hi =
3595 le32_to_cpu(tclient->rcv_error_bytes.hi);
3596 estats->error_bytes_received_lo =
3597 le32_to_cpu(tclient->rcv_error_bytes.lo);
3598 ADD_64(estats->error_bytes_received_hi,
3599 estats->rx_stat_ifhcinbadoctets_hi,
3600 estats->error_bytes_received_lo,
3601 estats->rx_stat_ifhcinbadoctets_lo);
3603 ADD_64(fstats->total_bytes_received_hi,
3604 estats->error_bytes_received_hi,
3605 fstats->total_bytes_received_lo,
3606 estats->error_bytes_received_lo);
3608 UPDATE_EXTEND_TSTAT(rcv_unicast_pkts, total_unicast_packets_received);
3609 UPDATE_EXTEND_TSTAT(rcv_multicast_pkts,
3610 total_multicast_packets_received);
3611 UPDATE_EXTEND_TSTAT(rcv_broadcast_pkts,
3612 total_broadcast_packets_received);
3614 fstats->total_bytes_transmitted_hi =
3615 le32_to_cpu(xclient->total_sent_bytes.hi);
3616 fstats->total_bytes_transmitted_lo =
3617 le32_to_cpu(xclient->total_sent_bytes.lo);
3619 UPDATE_EXTEND_XSTAT(unicast_pkts_sent,
3620 total_unicast_packets_transmitted);
3621 UPDATE_EXTEND_XSTAT(multicast_pkts_sent,
3622 total_multicast_packets_transmitted);
3623 UPDATE_EXTEND_XSTAT(broadcast_pkts_sent,
3624 total_broadcast_packets_transmitted);
3626 memcpy(estats, &(fstats->total_bytes_received_hi),
3627 sizeof(struct host_func_stats) - 2*sizeof(u32));
3629 estats->mac_filter_discard = le32_to_cpu(tport->mac_filter_discard);
3630 estats->xxoverflow_discard = le32_to_cpu(tport->xxoverflow_discard);
3631 estats->brb_truncate_discard =
3632 le32_to_cpu(tport->brb_truncate_discard);
3633 estats->mac_discard = le32_to_cpu(tport->mac_discard);
3635 old_tclient->rcv_unicast_bytes.hi =
3636 le32_to_cpu(tclient->rcv_unicast_bytes.hi);
3637 old_tclient->rcv_unicast_bytes.lo =
3638 le32_to_cpu(tclient->rcv_unicast_bytes.lo);
3639 old_tclient->rcv_broadcast_bytes.hi =
3640 le32_to_cpu(tclient->rcv_broadcast_bytes.hi);
3641 old_tclient->rcv_broadcast_bytes.lo =
3642 le32_to_cpu(tclient->rcv_broadcast_bytes.lo);
3643 old_tclient->rcv_multicast_bytes.hi =
3644 le32_to_cpu(tclient->rcv_multicast_bytes.hi);
3645 old_tclient->rcv_multicast_bytes.lo =
3646 le32_to_cpu(tclient->rcv_multicast_bytes.lo);
3647 old_tclient->total_rcv_pkts = le32_to_cpu(tclient->total_rcv_pkts);
3649 old_tclient->checksum_discard = le32_to_cpu(tclient->checksum_discard);
3650 old_tclient->packets_too_big_discard =
3651 le32_to_cpu(tclient->packets_too_big_discard);
3652 estats->no_buff_discard =
3653 old_tclient->no_buff_discard = le32_to_cpu(tclient->no_buff_discard);
3654 old_tclient->ttl0_discard = le32_to_cpu(tclient->ttl0_discard);
3656 old_xclient->total_sent_pkts = le32_to_cpu(xclient->total_sent_pkts);
3657 old_xclient->unicast_bytes_sent.hi =
3658 le32_to_cpu(xclient->unicast_bytes_sent.hi);
3659 old_xclient->unicast_bytes_sent.lo =
3660 le32_to_cpu(xclient->unicast_bytes_sent.lo);
3661 old_xclient->multicast_bytes_sent.hi =
3662 le32_to_cpu(xclient->multicast_bytes_sent.hi);
3663 old_xclient->multicast_bytes_sent.lo =
3664 le32_to_cpu(xclient->multicast_bytes_sent.lo);
3665 old_xclient->broadcast_bytes_sent.hi =
3666 le32_to_cpu(xclient->broadcast_bytes_sent.hi);
3667 old_xclient->broadcast_bytes_sent.lo =
3668 le32_to_cpu(xclient->broadcast_bytes_sent.lo);
3670 fstats->host_func_stats_start = ++fstats->host_func_stats_end;
3675 static void bnx2x_net_stats_update(struct bnx2x *bp)
3677 struct tstorm_per_client_stats *old_tclient = &bp->old_tclient;
3678 struct bnx2x_eth_stats *estats = &bp->eth_stats;
3679 struct net_device_stats *nstats = &bp->dev->stats;
3681 nstats->rx_packets =
3682 bnx2x_hilo(&estats->total_unicast_packets_received_hi) +
3683 bnx2x_hilo(&estats->total_multicast_packets_received_hi) +
3684 bnx2x_hilo(&estats->total_broadcast_packets_received_hi);
3686 nstats->tx_packets =
3687 bnx2x_hilo(&estats->total_unicast_packets_transmitted_hi) +
3688 bnx2x_hilo(&estats->total_multicast_packets_transmitted_hi) +
3689 bnx2x_hilo(&estats->total_broadcast_packets_transmitted_hi);
3691 nstats->rx_bytes = bnx2x_hilo(&estats->valid_bytes_received_hi);
3693 nstats->tx_bytes = bnx2x_hilo(&estats->total_bytes_transmitted_hi);
3695 nstats->rx_dropped = old_tclient->checksum_discard +
3696 estats->mac_discard;
3697 nstats->tx_dropped = 0;
3700 bnx2x_hilo(&estats->total_multicast_packets_transmitted_hi);
3702 nstats->collisions =
3703 estats->tx_stat_dot3statssinglecollisionframes_lo +
3704 estats->tx_stat_dot3statsmultiplecollisionframes_lo +
3705 estats->tx_stat_dot3statslatecollisions_lo +
3706 estats->tx_stat_dot3statsexcessivecollisions_lo;
3708 estats->jabber_packets_received =
3709 old_tclient->packets_too_big_discard +
3710 estats->rx_stat_dot3statsframestoolong_lo;
3712 nstats->rx_length_errors =
3713 estats->rx_stat_etherstatsundersizepkts_lo +
3714 estats->jabber_packets_received;
3715 nstats->rx_over_errors = estats->brb_drop_lo + estats->brb_truncate_lo;
3716 nstats->rx_crc_errors = estats->rx_stat_dot3statsfcserrors_lo;
3717 nstats->rx_frame_errors = estats->rx_stat_dot3statsalignmenterrors_lo;
3718 nstats->rx_fifo_errors = old_tclient->no_buff_discard;
3719 nstats->rx_missed_errors = estats->xxoverflow_discard;
3721 nstats->rx_errors = nstats->rx_length_errors +
3722 nstats->rx_over_errors +
3723 nstats->rx_crc_errors +
3724 nstats->rx_frame_errors +
3725 nstats->rx_fifo_errors +
3726 nstats->rx_missed_errors;
3728 nstats->tx_aborted_errors =
3729 estats->tx_stat_dot3statslatecollisions_lo +
3730 estats->tx_stat_dot3statsexcessivecollisions_lo;
3731 nstats->tx_carrier_errors = estats->rx_stat_falsecarriererrors_lo;
3732 nstats->tx_fifo_errors = 0;
3733 nstats->tx_heartbeat_errors = 0;
3734 nstats->tx_window_errors = 0;
3736 nstats->tx_errors = nstats->tx_aborted_errors +
3737 nstats->tx_carrier_errors;
3740 static void bnx2x_stats_update(struct bnx2x *bp)
3742 u32 *stats_comp = bnx2x_sp(bp, stats_comp);
3745 if (*stats_comp != DMAE_COMP_VAL)
3749 update = (bnx2x_hw_stats_update(bp) == 0);
3751 update |= (bnx2x_storm_stats_update(bp) == 0);
3754 bnx2x_net_stats_update(bp);
3757 if (bp->stats_pending) {
3758 bp->stats_pending++;
3759 if (bp->stats_pending == 3) {
3760 BNX2X_ERR("stats not updated for 3 times\n");
3767 if (bp->msglevel & NETIF_MSG_TIMER) {
3768 struct tstorm_per_client_stats *old_tclient = &bp->old_tclient;
3769 struct bnx2x_eth_stats *estats = &bp->eth_stats;
3770 struct net_device_stats *nstats = &bp->dev->stats;
3773 printk(KERN_DEBUG "%s:\n", bp->dev->name);
3774 printk(KERN_DEBUG " tx avail (%4x) tx hc idx (%x)"
3776 bnx2x_tx_avail(bp->fp),
3777 le16_to_cpu(*bp->fp->tx_cons_sb), nstats->tx_packets);
3778 printk(KERN_DEBUG " rx usage (%4x) rx hc idx (%x)"
3780 (u16)(le16_to_cpu(*bp->fp->rx_cons_sb) -
3781 bp->fp->rx_comp_cons),
3782 le16_to_cpu(*bp->fp->rx_cons_sb), nstats->rx_packets);
3783 printk(KERN_DEBUG " %s (Xoff events %u) brb drops %u\n",
3784 netif_queue_stopped(bp->dev)? "Xoff" : "Xon",
3785 estats->driver_xoff, estats->brb_drop_lo);
3786 printk(KERN_DEBUG "tstats: checksum_discard %u "
3787 "packets_too_big_discard %u no_buff_discard %u "
3788 "mac_discard %u mac_filter_discard %u "
3789 "xxovrflow_discard %u brb_truncate_discard %u "
3790 "ttl0_discard %u\n",
3791 old_tclient->checksum_discard,
3792 old_tclient->packets_too_big_discard,
3793 old_tclient->no_buff_discard, estats->mac_discard,
3794 estats->mac_filter_discard, estats->xxoverflow_discard,
3795 estats->brb_truncate_discard,
3796 old_tclient->ttl0_discard);
3798 for_each_queue(bp, i) {
3799 printk(KERN_DEBUG "[%d]: %lu\t%lu\t%lu\n", i,
3800 bnx2x_fp(bp, i, tx_pkt),
3801 bnx2x_fp(bp, i, rx_pkt),
3802 bnx2x_fp(bp, i, rx_calls));
3806 bnx2x_hw_stats_post(bp);
3807 bnx2x_storm_stats_post(bp);
3810 static void bnx2x_port_stats_stop(struct bnx2x *bp)
3812 struct dmae_command *dmae;
3814 int loader_idx = PMF_DMAE_C(bp);
3815 u32 *stats_comp = bnx2x_sp(bp, stats_comp);
3817 bp->executer_idx = 0;
3819 opcode = (DMAE_CMD_SRC_PCI | DMAE_CMD_DST_GRC |
3821 DMAE_CMD_SRC_RESET | DMAE_CMD_DST_RESET |
3823 DMAE_CMD_ENDIANITY_B_DW_SWAP |
3825 DMAE_CMD_ENDIANITY_DW_SWAP |
3827 (BP_PORT(bp) ? DMAE_CMD_PORT_1 : DMAE_CMD_PORT_0) |
3828 (BP_E1HVN(bp) << DMAE_CMD_E1HVN_SHIFT));
3830 if (bp->port.port_stx) {
3832 dmae = bnx2x_sp(bp, dmae[bp->executer_idx++]);
3834 dmae->opcode = (opcode | DMAE_CMD_C_DST_GRC);
3836 dmae->opcode = (opcode | DMAE_CMD_C_DST_PCI);
3837 dmae->src_addr_lo = U64_LO(bnx2x_sp_mapping(bp, port_stats));
3838 dmae->src_addr_hi = U64_HI(bnx2x_sp_mapping(bp, port_stats));
3839 dmae->dst_addr_lo = bp->port.port_stx >> 2;
3840 dmae->dst_addr_hi = 0;
3841 dmae->len = sizeof(struct host_port_stats) >> 2;
3843 dmae->comp_addr_lo = dmae_reg_go_c[loader_idx] >> 2;
3844 dmae->comp_addr_hi = 0;
3847 dmae->comp_addr_lo =
3848 U64_LO(bnx2x_sp_mapping(bp, stats_comp));
3849 dmae->comp_addr_hi =
3850 U64_HI(bnx2x_sp_mapping(bp, stats_comp));
3851 dmae->comp_val = DMAE_COMP_VAL;
3859 dmae = bnx2x_sp(bp, dmae[bp->executer_idx++]);
3860 dmae->opcode = (opcode | DMAE_CMD_C_DST_PCI);
3861 dmae->src_addr_lo = U64_LO(bnx2x_sp_mapping(bp, func_stats));
3862 dmae->src_addr_hi = U64_HI(bnx2x_sp_mapping(bp, func_stats));
3863 dmae->dst_addr_lo = bp->func_stx >> 2;
3864 dmae->dst_addr_hi = 0;
3865 dmae->len = sizeof(struct host_func_stats) >> 2;
3866 dmae->comp_addr_lo = U64_LO(bnx2x_sp_mapping(bp, stats_comp));
3867 dmae->comp_addr_hi = U64_HI(bnx2x_sp_mapping(bp, stats_comp));
3868 dmae->comp_val = DMAE_COMP_VAL;
3874 static void bnx2x_stats_stop(struct bnx2x *bp)
3878 bnx2x_stats_comp(bp);
3881 update = (bnx2x_hw_stats_update(bp) == 0);
3883 update |= (bnx2x_storm_stats_update(bp) == 0);
3886 bnx2x_net_stats_update(bp);
3889 bnx2x_port_stats_stop(bp);
3891 bnx2x_hw_stats_post(bp);
3892 bnx2x_stats_comp(bp);
3896 static void bnx2x_stats_do_nothing(struct bnx2x *bp)
3900 static const struct {
3901 void (*action)(struct bnx2x *bp);
3902 enum bnx2x_stats_state next_state;
3903 } bnx2x_stats_stm[STATS_STATE_MAX][STATS_EVENT_MAX] = {
3906 /* DISABLED PMF */ {bnx2x_stats_pmf_update, STATS_STATE_DISABLED},
3907 /* LINK_UP */ {bnx2x_stats_start, STATS_STATE_ENABLED},
3908 /* UPDATE */ {bnx2x_stats_do_nothing, STATS_STATE_DISABLED},
3909 /* STOP */ {bnx2x_stats_do_nothing, STATS_STATE_DISABLED}
3912 /* ENABLED PMF */ {bnx2x_stats_pmf_start, STATS_STATE_ENABLED},
3913 /* LINK_UP */ {bnx2x_stats_restart, STATS_STATE_ENABLED},
3914 /* UPDATE */ {bnx2x_stats_update, STATS_STATE_ENABLED},
3915 /* STOP */ {bnx2x_stats_stop, STATS_STATE_DISABLED}
3919 static void bnx2x_stats_handle(struct bnx2x *bp, enum bnx2x_stats_event event)
3921 enum bnx2x_stats_state state = bp->stats_state;
3923 bnx2x_stats_stm[state][event].action(bp);
3924 bp->stats_state = bnx2x_stats_stm[state][event].next_state;
3926 if ((event != STATS_EVENT_UPDATE) || (bp->msglevel & NETIF_MSG_TIMER))
3927 DP(BNX2X_MSG_STATS, "state %d -> event %d -> state %d\n",
3928 state, event, bp->stats_state);
3931 static void bnx2x_timer(unsigned long data)
3933 struct bnx2x *bp = (struct bnx2x *) data;
3935 if (!netif_running(bp->dev))
3938 if (atomic_read(&bp->intr_sem) != 0)
3942 struct bnx2x_fastpath *fp = &bp->fp[0];
3945 bnx2x_tx_int(fp, 1000);
3946 rc = bnx2x_rx_int(fp, 1000);
3949 if (!BP_NOMCP(bp)) {
3950 int func = BP_FUNC(bp);
3954 ++bp->fw_drv_pulse_wr_seq;
3955 bp->fw_drv_pulse_wr_seq &= DRV_PULSE_SEQ_MASK;
3956 /* TBD - add SYSTEM_TIME */
3957 drv_pulse = bp->fw_drv_pulse_wr_seq;
3958 SHMEM_WR(bp, func_mb[func].drv_pulse_mb, drv_pulse);
3960 mcp_pulse = (SHMEM_RD(bp, func_mb[func].mcp_pulse_mb) &
3961 MCP_PULSE_SEQ_MASK);
3962 /* The delta between driver pulse and mcp response
3963 * should be 1 (before mcp response) or 0 (after mcp response)
3965 if ((drv_pulse != mcp_pulse) &&
3966 (drv_pulse != ((mcp_pulse + 1) & MCP_PULSE_SEQ_MASK))) {
3967 /* someone lost a heartbeat... */
3968 BNX2X_ERR("drv_pulse (0x%x) != mcp_pulse (0x%x)\n",
3969 drv_pulse, mcp_pulse);
3973 if ((bp->state == BNX2X_STATE_OPEN) ||
3974 (bp->state == BNX2X_STATE_DISABLED))
3975 bnx2x_stats_handle(bp, STATS_EVENT_UPDATE);
3978 mod_timer(&bp->timer, jiffies + bp->current_interval);
3981 /* end of Statistics */
3986 * nic init service functions
3989 static void bnx2x_zero_sb(struct bnx2x *bp, int sb_id)
3991 int port = BP_PORT(bp);
3993 bnx2x_init_fill(bp, BAR_USTRORM_INTMEM +
3994 USTORM_SB_HOST_STATUS_BLOCK_OFFSET(port, sb_id), 0,
3995 sizeof(struct ustorm_status_block)/4);
3996 bnx2x_init_fill(bp, BAR_CSTRORM_INTMEM +
3997 CSTORM_SB_HOST_STATUS_BLOCK_OFFSET(port, sb_id), 0,
3998 sizeof(struct cstorm_status_block)/4);
4001 static void bnx2x_init_sb(struct bnx2x *bp, struct host_status_block *sb,
4002 dma_addr_t mapping, int sb_id)
4004 int port = BP_PORT(bp);
4005 int func = BP_FUNC(bp);
4010 section = ((u64)mapping) + offsetof(struct host_status_block,
4012 sb->u_status_block.status_block_id = sb_id;
4014 REG_WR(bp, BAR_USTRORM_INTMEM +
4015 USTORM_SB_HOST_SB_ADDR_OFFSET(port, sb_id), U64_LO(section));
4016 REG_WR(bp, BAR_USTRORM_INTMEM +
4017 ((USTORM_SB_HOST_SB_ADDR_OFFSET(port, sb_id)) + 4),
4019 REG_WR8(bp, BAR_USTRORM_INTMEM + FP_USB_FUNC_OFF +
4020 USTORM_SB_HOST_STATUS_BLOCK_OFFSET(port, sb_id), func);
4022 for (index = 0; index < HC_USTORM_SB_NUM_INDICES; index++)
4023 REG_WR16(bp, BAR_USTRORM_INTMEM +
4024 USTORM_SB_HC_DISABLE_OFFSET(port, sb_id, index), 1);
4027 section = ((u64)mapping) + offsetof(struct host_status_block,
4029 sb->c_status_block.status_block_id = sb_id;
4031 REG_WR(bp, BAR_CSTRORM_INTMEM +
4032 CSTORM_SB_HOST_SB_ADDR_OFFSET(port, sb_id), U64_LO(section));
4033 REG_WR(bp, BAR_CSTRORM_INTMEM +
4034 ((CSTORM_SB_HOST_SB_ADDR_OFFSET(port, sb_id)) + 4),
4036 REG_WR8(bp, BAR_CSTRORM_INTMEM + FP_CSB_FUNC_OFF +
4037 CSTORM_SB_HOST_STATUS_BLOCK_OFFSET(port, sb_id), func);
4039 for (index = 0; index < HC_CSTORM_SB_NUM_INDICES; index++)
4040 REG_WR16(bp, BAR_CSTRORM_INTMEM +
4041 CSTORM_SB_HC_DISABLE_OFFSET(port, sb_id, index), 1);
4043 bnx2x_ack_sb(bp, sb_id, CSTORM_ID, 0, IGU_INT_ENABLE, 0);
4046 static void bnx2x_zero_def_sb(struct bnx2x *bp)
4048 int func = BP_FUNC(bp);
4050 bnx2x_init_fill(bp, BAR_USTRORM_INTMEM +
4051 USTORM_DEF_SB_HOST_STATUS_BLOCK_OFFSET(func), 0,
4052 sizeof(struct ustorm_def_status_block)/4);
4053 bnx2x_init_fill(bp, BAR_CSTRORM_INTMEM +
4054 CSTORM_DEF_SB_HOST_STATUS_BLOCK_OFFSET(func), 0,
4055 sizeof(struct cstorm_def_status_block)/4);
4056 bnx2x_init_fill(bp, BAR_XSTRORM_INTMEM +
4057 XSTORM_DEF_SB_HOST_STATUS_BLOCK_OFFSET(func), 0,
4058 sizeof(struct xstorm_def_status_block)/4);
4059 bnx2x_init_fill(bp, BAR_TSTRORM_INTMEM +
4060 TSTORM_DEF_SB_HOST_STATUS_BLOCK_OFFSET(func), 0,
4061 sizeof(struct tstorm_def_status_block)/4);
4064 static void bnx2x_init_def_sb(struct bnx2x *bp,
4065 struct host_def_status_block *def_sb,
4066 dma_addr_t mapping, int sb_id)
4068 int port = BP_PORT(bp);
4069 int func = BP_FUNC(bp);
4070 int index, val, reg_offset;
4074 section = ((u64)mapping) + offsetof(struct host_def_status_block,
4075 atten_status_block);
4076 def_sb->atten_status_block.status_block_id = sb_id;
4080 reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 :
4081 MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0);
4083 for (index = 0; index < MAX_DYNAMIC_ATTN_GRPS; index++) {
4084 bp->attn_group[index].sig[0] = REG_RD(bp,
4085 reg_offset + 0x10*index);
4086 bp->attn_group[index].sig[1] = REG_RD(bp,
4087 reg_offset + 0x4 + 0x10*index);
4088 bp->attn_group[index].sig[2] = REG_RD(bp,
4089 reg_offset + 0x8 + 0x10*index);
4090 bp->attn_group[index].sig[3] = REG_RD(bp,
4091 reg_offset + 0xc + 0x10*index);
4094 reg_offset = (port ? HC_REG_ATTN_MSG1_ADDR_L :
4095 HC_REG_ATTN_MSG0_ADDR_L);
4097 REG_WR(bp, reg_offset, U64_LO(section));
4098 REG_WR(bp, reg_offset + 4, U64_HI(section));
4100 reg_offset = (port ? HC_REG_ATTN_NUM_P1 : HC_REG_ATTN_NUM_P0);
4102 val = REG_RD(bp, reg_offset);
4104 REG_WR(bp, reg_offset, val);
4107 section = ((u64)mapping) + offsetof(struct host_def_status_block,
4108 u_def_status_block);
4109 def_sb->u_def_status_block.status_block_id = sb_id;
4111 REG_WR(bp, BAR_USTRORM_INTMEM +
4112 USTORM_DEF_SB_HOST_SB_ADDR_OFFSET(func), U64_LO(section));
4113 REG_WR(bp, BAR_USTRORM_INTMEM +
4114 ((USTORM_DEF_SB_HOST_SB_ADDR_OFFSET(func)) + 4),
4116 REG_WR8(bp, BAR_USTRORM_INTMEM + DEF_USB_FUNC_OFF +
4117 USTORM_DEF_SB_HOST_STATUS_BLOCK_OFFSET(func), func);
4119 for (index = 0; index < HC_USTORM_DEF_SB_NUM_INDICES; index++)
4120 REG_WR16(bp, BAR_USTRORM_INTMEM +
4121 USTORM_DEF_SB_HC_DISABLE_OFFSET(func, index), 1);
4124 section = ((u64)mapping) + offsetof(struct host_def_status_block,
4125 c_def_status_block);
4126 def_sb->c_def_status_block.status_block_id = sb_id;
4128 REG_WR(bp, BAR_CSTRORM_INTMEM +
4129 CSTORM_DEF_SB_HOST_SB_ADDR_OFFSET(func), U64_LO(section));
4130 REG_WR(bp, BAR_CSTRORM_INTMEM +
4131 ((CSTORM_DEF_SB_HOST_SB_ADDR_OFFSET(func)) + 4),
4133 REG_WR8(bp, BAR_CSTRORM_INTMEM + DEF_CSB_FUNC_OFF +
4134 CSTORM_DEF_SB_HOST_STATUS_BLOCK_OFFSET(func), func);
4136 for (index = 0; index < HC_CSTORM_DEF_SB_NUM_INDICES; index++)
4137 REG_WR16(bp, BAR_CSTRORM_INTMEM +
4138 CSTORM_DEF_SB_HC_DISABLE_OFFSET(func, index), 1);
4141 section = ((u64)mapping) + offsetof(struct host_def_status_block,
4142 t_def_status_block);
4143 def_sb->t_def_status_block.status_block_id = sb_id;
4145 REG_WR(bp, BAR_TSTRORM_INTMEM +
4146 TSTORM_DEF_SB_HOST_SB_ADDR_OFFSET(func), U64_LO(section));
4147 REG_WR(bp, BAR_TSTRORM_INTMEM +
4148 ((TSTORM_DEF_SB_HOST_SB_ADDR_OFFSET(func)) + 4),
4150 REG_WR8(bp, BAR_TSTRORM_INTMEM + DEF_TSB_FUNC_OFF +
4151 TSTORM_DEF_SB_HOST_STATUS_BLOCK_OFFSET(func), func);
4153 for (index = 0; index < HC_TSTORM_DEF_SB_NUM_INDICES; index++)
4154 REG_WR16(bp, BAR_TSTRORM_INTMEM +
4155 TSTORM_DEF_SB_HC_DISABLE_OFFSET(func, index), 1);
4158 section = ((u64)mapping) + offsetof(struct host_def_status_block,
4159 x_def_status_block);
4160 def_sb->x_def_status_block.status_block_id = sb_id;
4162 REG_WR(bp, BAR_XSTRORM_INTMEM +
4163 XSTORM_DEF_SB_HOST_SB_ADDR_OFFSET(func), U64_LO(section));
4164 REG_WR(bp, BAR_XSTRORM_INTMEM +
4165 ((XSTORM_DEF_SB_HOST_SB_ADDR_OFFSET(func)) + 4),
4167 REG_WR8(bp, BAR_XSTRORM_INTMEM + DEF_XSB_FUNC_OFF +
4168 XSTORM_DEF_SB_HOST_STATUS_BLOCK_OFFSET(func), func);
4170 for (index = 0; index < HC_XSTORM_DEF_SB_NUM_INDICES; index++)
4171 REG_WR16(bp, BAR_XSTRORM_INTMEM +
4172 XSTORM_DEF_SB_HC_DISABLE_OFFSET(func, index), 1);
4174 bp->stats_pending = 0;
4175 bp->set_mac_pending = 0;
4177 bnx2x_ack_sb(bp, sb_id, CSTORM_ID, 0, IGU_INT_ENABLE, 0);
4180 static void bnx2x_update_coalesce(struct bnx2x *bp)
4182 int port = BP_PORT(bp);
4185 for_each_queue(bp, i) {
4186 int sb_id = bp->fp[i].sb_id;
4188 /* HC_INDEX_U_ETH_RX_CQ_CONS */
4189 REG_WR8(bp, BAR_USTRORM_INTMEM +
4190 USTORM_SB_HC_TIMEOUT_OFFSET(port, sb_id,
4191 U_SB_ETH_RX_CQ_INDEX),
4193 REG_WR16(bp, BAR_USTRORM_INTMEM +
4194 USTORM_SB_HC_DISABLE_OFFSET(port, sb_id,
4195 U_SB_ETH_RX_CQ_INDEX),
4196 bp->rx_ticks ? 0 : 1);
4197 REG_WR16(bp, BAR_USTRORM_INTMEM +
4198 USTORM_SB_HC_DISABLE_OFFSET(port, sb_id,
4199 U_SB_ETH_RX_BD_INDEX),
4200 bp->rx_ticks ? 0 : 1);
4202 /* HC_INDEX_C_ETH_TX_CQ_CONS */
4203 REG_WR8(bp, BAR_CSTRORM_INTMEM +
4204 CSTORM_SB_HC_TIMEOUT_OFFSET(port, sb_id,
4205 C_SB_ETH_TX_CQ_INDEX),
4207 REG_WR16(bp, BAR_CSTRORM_INTMEM +
4208 CSTORM_SB_HC_DISABLE_OFFSET(port, sb_id,
4209 C_SB_ETH_TX_CQ_INDEX),
4210 bp->tx_ticks ? 0 : 1);
4214 static inline void bnx2x_free_tpa_pool(struct bnx2x *bp,
4215 struct bnx2x_fastpath *fp, int last)
4219 for (i = 0; i < last; i++) {
4220 struct sw_rx_bd *rx_buf = &(fp->tpa_pool[i]);
4221 struct sk_buff *skb = rx_buf->skb;
4224 DP(NETIF_MSG_IFDOWN, "tpa bin %d empty on free\n", i);
4228 if (fp->tpa_state[i] == BNX2X_TPA_START)
4229 pci_unmap_single(bp->pdev,
4230 pci_unmap_addr(rx_buf, mapping),
4231 bp->rx_buf_use_size,
4232 PCI_DMA_FROMDEVICE);
4239 static void bnx2x_init_rx_rings(struct bnx2x *bp)
4241 int func = BP_FUNC(bp);
4242 int max_agg_queues = CHIP_IS_E1(bp) ? ETH_MAX_AGGREGATION_QUEUES_E1 :
4243 ETH_MAX_AGGREGATION_QUEUES_E1H;
4244 u16 ring_prod, cqe_ring_prod;
4247 bp->rx_buf_use_size = bp->dev->mtu;
4248 bp->rx_buf_use_size += bp->rx_offset + ETH_OVREHEAD;
4249 bp->rx_buf_size = bp->rx_buf_use_size + 64;
4251 if (bp->flags & TPA_ENABLE_FLAG) {
4253 "rx_buf_use_size %d rx_buf_size %d effective_mtu %d\n",
4254 bp->rx_buf_use_size, bp->rx_buf_size,
4255 bp->dev->mtu + ETH_OVREHEAD);
4257 for_each_queue(bp, j) {
4258 struct bnx2x_fastpath *fp = &bp->fp[j];
4260 for (i = 0; i < max_agg_queues; i++) {
4261 fp->tpa_pool[i].skb =
4262 netdev_alloc_skb(bp->dev, bp->rx_buf_size);
4263 if (!fp->tpa_pool[i].skb) {
4264 BNX2X_ERR("Failed to allocate TPA "
4265 "skb pool for queue[%d] - "
4266 "disabling TPA on this "
4268 bnx2x_free_tpa_pool(bp, fp, i);
4269 fp->disable_tpa = 1;
4272 pci_unmap_addr_set((struct sw_rx_bd *)
4273 &bp->fp->tpa_pool[i],
4275 fp->tpa_state[i] = BNX2X_TPA_STOP;
4280 for_each_queue(bp, j) {
4281 struct bnx2x_fastpath *fp = &bp->fp[j];
4284 fp->rx_cons_sb = BNX2X_RX_SB_INDEX;
4285 fp->rx_bd_cons_sb = BNX2X_RX_SB_BD_INDEX;
4287 /* "next page" elements initialization */
4289 for (i = 1; i <= NUM_RX_SGE_PAGES; i++) {
4290 struct eth_rx_sge *sge;
4292 sge = &fp->rx_sge_ring[RX_SGE_CNT * i - 2];
4294 cpu_to_le32(U64_HI(fp->rx_sge_mapping +
4295 BCM_PAGE_SIZE*(i % NUM_RX_SGE_PAGES)));
4297 cpu_to_le32(U64_LO(fp->rx_sge_mapping +
4298 BCM_PAGE_SIZE*(i % NUM_RX_SGE_PAGES)));
4301 bnx2x_init_sge_ring_bit_mask(fp);
4304 for (i = 1; i <= NUM_RX_RINGS; i++) {
4305 struct eth_rx_bd *rx_bd;
4307 rx_bd = &fp->rx_desc_ring[RX_DESC_CNT * i - 2];
4309 cpu_to_le32(U64_HI(fp->rx_desc_mapping +
4310 BCM_PAGE_SIZE*(i % NUM_RX_RINGS)));
4312 cpu_to_le32(U64_LO(fp->rx_desc_mapping +
4313 BCM_PAGE_SIZE*(i % NUM_RX_RINGS)));
4317 for (i = 1; i <= NUM_RCQ_RINGS; i++) {
4318 struct eth_rx_cqe_next_page *nextpg;
4320 nextpg = (struct eth_rx_cqe_next_page *)
4321 &fp->rx_comp_ring[RCQ_DESC_CNT * i - 1];
4323 cpu_to_le32(U64_HI(fp->rx_comp_mapping +
4324 BCM_PAGE_SIZE*(i % NUM_RCQ_RINGS)));
4326 cpu_to_le32(U64_LO(fp->rx_comp_mapping +
4327 BCM_PAGE_SIZE*(i % NUM_RCQ_RINGS)));
4330 /* Allocate SGEs and initialize the ring elements */
4331 for (i = 0, ring_prod = 0;
4332 i < MAX_RX_SGE_CNT*NUM_RX_SGE_PAGES; i++) {
4334 if (bnx2x_alloc_rx_sge(bp, fp, ring_prod) < 0) {
4335 BNX2X_ERR("was only able to allocate "
4337 BNX2X_ERR("disabling TPA for queue[%d]\n", j);
4338 /* Cleanup already allocated elements */
4339 bnx2x_free_rx_sge_range(bp, fp, ring_prod);
4340 bnx2x_free_tpa_pool(bp, fp, max_agg_queues);
4341 fp->disable_tpa = 1;
4345 ring_prod = NEXT_SGE_IDX(ring_prod);
4347 fp->rx_sge_prod = ring_prod;
4349 /* Allocate BDs and initialize BD ring */
4350 fp->rx_comp_cons = 0;
4351 cqe_ring_prod = ring_prod = 0;
4352 for (i = 0; i < bp->rx_ring_size; i++) {
4353 if (bnx2x_alloc_rx_skb(bp, fp, ring_prod) < 0) {
4354 BNX2X_ERR("was only able to allocate "
4356 bp->eth_stats.rx_skb_alloc_failed++;
4359 ring_prod = NEXT_RX_IDX(ring_prod);
4360 cqe_ring_prod = NEXT_RCQ_IDX(cqe_ring_prod);
4361 WARN_ON(ring_prod <= i);
4364 fp->rx_bd_prod = ring_prod;
4365 /* must not have more available CQEs than BDs */
4366 fp->rx_comp_prod = min((u16)(NUM_RCQ_RINGS*RCQ_DESC_CNT),
4368 fp->rx_pkt = fp->rx_calls = 0;
4371 * this will generate an interrupt (to the TSTORM)
4372 * must only be done after chip is initialized
4374 bnx2x_update_rx_prod(bp, fp, ring_prod, fp->rx_comp_prod,
4379 REG_WR(bp, BAR_USTRORM_INTMEM +
4380 USTORM_MEM_WORKAROUND_ADDRESS_OFFSET(func),
4381 U64_LO(fp->rx_comp_mapping));
4382 REG_WR(bp, BAR_USTRORM_INTMEM +
4383 USTORM_MEM_WORKAROUND_ADDRESS_OFFSET(func) + 4,
4384 U64_HI(fp->rx_comp_mapping));
4388 static void bnx2x_init_tx_ring(struct bnx2x *bp)
4392 for_each_queue(bp, j) {
4393 struct bnx2x_fastpath *fp = &bp->fp[j];
4395 for (i = 1; i <= NUM_TX_RINGS; i++) {
4396 struct eth_tx_bd *tx_bd =
4397 &fp->tx_desc_ring[TX_DESC_CNT * i - 1];
4400 cpu_to_le32(U64_HI(fp->tx_desc_mapping +
4401 BCM_PAGE_SIZE*(i % NUM_TX_RINGS)));
4403 cpu_to_le32(U64_LO(fp->tx_desc_mapping +
4404 BCM_PAGE_SIZE*(i % NUM_TX_RINGS)));
4407 fp->tx_pkt_prod = 0;
4408 fp->tx_pkt_cons = 0;
4411 fp->tx_cons_sb = BNX2X_TX_SB_INDEX;
4416 static void bnx2x_init_sp_ring(struct bnx2x *bp)
4418 int func = BP_FUNC(bp);
4420 spin_lock_init(&bp->spq_lock);
4422 bp->spq_left = MAX_SPQ_PENDING;
4423 bp->spq_prod_idx = 0;
4424 bp->dsb_sp_prod = BNX2X_SP_DSB_INDEX;
4425 bp->spq_prod_bd = bp->spq;
4426 bp->spq_last_bd = bp->spq_prod_bd + MAX_SP_DESC_CNT;
4428 REG_WR(bp, XSEM_REG_FAST_MEMORY + XSTORM_SPQ_PAGE_BASE_OFFSET(func),
4429 U64_LO(bp->spq_mapping));
4431 XSEM_REG_FAST_MEMORY + XSTORM_SPQ_PAGE_BASE_OFFSET(func) + 4,
4432 U64_HI(bp->spq_mapping));
4434 REG_WR(bp, XSEM_REG_FAST_MEMORY + XSTORM_SPQ_PROD_OFFSET(func),
4438 static void bnx2x_init_context(struct bnx2x *bp)
4442 for_each_queue(bp, i) {
4443 struct eth_context *context = bnx2x_sp(bp, context[i].eth);
4444 struct bnx2x_fastpath *fp = &bp->fp[i];
4445 u8 sb_id = FP_SB_ID(fp);
4447 context->xstorm_st_context.tx_bd_page_base_hi =
4448 U64_HI(fp->tx_desc_mapping);
4449 context->xstorm_st_context.tx_bd_page_base_lo =
4450 U64_LO(fp->tx_desc_mapping);
4451 context->xstorm_st_context.db_data_addr_hi =
4452 U64_HI(fp->tx_prods_mapping);
4453 context->xstorm_st_context.db_data_addr_lo =
4454 U64_LO(fp->tx_prods_mapping);
4455 context->xstorm_st_context.statistics_data = (BP_CL_ID(bp) |
4456 XSTORM_ETH_ST_CONTEXT_STATISTICS_ENABLE);
4458 context->ustorm_st_context.common.sb_index_numbers =
4459 BNX2X_RX_SB_INDEX_NUM;
4460 context->ustorm_st_context.common.clientId = FP_CL_ID(fp);
4461 context->ustorm_st_context.common.status_block_id = sb_id;
4462 context->ustorm_st_context.common.flags =
4463 USTORM_ETH_ST_CONTEXT_CONFIG_ENABLE_MC_ALIGNMENT;
4464 context->ustorm_st_context.common.mc_alignment_size = 64;
4465 context->ustorm_st_context.common.bd_buff_size =
4466 bp->rx_buf_use_size;
4467 context->ustorm_st_context.common.bd_page_base_hi =
4468 U64_HI(fp->rx_desc_mapping);
4469 context->ustorm_st_context.common.bd_page_base_lo =
4470 U64_LO(fp->rx_desc_mapping);
4471 if (!fp->disable_tpa) {
4472 context->ustorm_st_context.common.flags |=
4473 (USTORM_ETH_ST_CONTEXT_CONFIG_ENABLE_TPA |
4474 USTORM_ETH_ST_CONTEXT_CONFIG_ENABLE_SGE_RING);
4475 context->ustorm_st_context.common.sge_buff_size =
4476 (u16)(BCM_PAGE_SIZE*PAGES_PER_SGE);
4477 context->ustorm_st_context.common.sge_page_base_hi =
4478 U64_HI(fp->rx_sge_mapping);
4479 context->ustorm_st_context.common.sge_page_base_lo =
4480 U64_LO(fp->rx_sge_mapping);
4483 context->cstorm_st_context.sb_index_number =
4484 C_SB_ETH_TX_CQ_INDEX;
4485 context->cstorm_st_context.status_block_id = sb_id;
4487 context->xstorm_ag_context.cdu_reserved =
4488 CDU_RSRVD_VALUE_TYPE_A(HW_CID(bp, i),
4489 CDU_REGION_NUMBER_XCM_AG,
4490 ETH_CONNECTION_TYPE);
4491 context->ustorm_ag_context.cdu_usage =
4492 CDU_RSRVD_VALUE_TYPE_A(HW_CID(bp, i),
4493 CDU_REGION_NUMBER_UCM_AG,
4494 ETH_CONNECTION_TYPE);
4498 static void bnx2x_init_ind_table(struct bnx2x *bp)
4500 int port = BP_PORT(bp);
4506 DP(NETIF_MSG_IFUP, "Initializing indirection table\n");
4507 for (i = 0; i < TSTORM_INDIRECTION_TABLE_SIZE; i++)
4508 REG_WR8(bp, BAR_TSTRORM_INTMEM +
4509 TSTORM_INDIRECTION_TABLE_OFFSET(port) + i,
4510 i % bp->num_queues);
4512 REG_WR(bp, PRS_REG_A_PRSU_20, 0xf);
4515 static void bnx2x_set_client_config(struct bnx2x *bp)
4517 struct tstorm_eth_client_config tstorm_client = {0};
4518 int port = BP_PORT(bp);
4521 tstorm_client.mtu = bp->dev->mtu + ETH_OVREHEAD;
4522 tstorm_client.statistics_counter_id = BP_CL_ID(bp);
4523 tstorm_client.config_flags =
4524 TSTORM_ETH_CLIENT_CONFIG_STATSITICS_ENABLE;
4526 if (bp->rx_mode && bp->vlgrp) {
4527 tstorm_client.config_flags |=
4528 TSTORM_ETH_CLIENT_CONFIG_VLAN_REMOVAL_ENABLE;
4529 DP(NETIF_MSG_IFUP, "vlan removal enabled\n");
4533 if (bp->flags & TPA_ENABLE_FLAG) {
4534 tstorm_client.max_sges_for_packet =
4535 BCM_PAGE_ALIGN(tstorm_client.mtu) >> BCM_PAGE_SHIFT;
4536 tstorm_client.max_sges_for_packet =
4537 ((tstorm_client.max_sges_for_packet +
4538 PAGES_PER_SGE - 1) & (~(PAGES_PER_SGE - 1))) >>
4539 PAGES_PER_SGE_SHIFT;
4541 tstorm_client.config_flags |=
4542 TSTORM_ETH_CLIENT_CONFIG_ENABLE_SGE_RING;
4545 for_each_queue(bp, i) {
4546 REG_WR(bp, BAR_TSTRORM_INTMEM +
4547 TSTORM_CLIENT_CONFIG_OFFSET(port, bp->fp[i].cl_id),
4548 ((u32 *)&tstorm_client)[0]);
4549 REG_WR(bp, BAR_TSTRORM_INTMEM +
4550 TSTORM_CLIENT_CONFIG_OFFSET(port, bp->fp[i].cl_id) + 4,
4551 ((u32 *)&tstorm_client)[1]);
4554 DP(BNX2X_MSG_OFF, "tstorm_client: 0x%08x 0x%08x\n",
4555 ((u32 *)&tstorm_client)[0], ((u32 *)&tstorm_client)[1]);
4558 static void bnx2x_set_storm_rx_mode(struct bnx2x *bp)
4560 struct tstorm_eth_mac_filter_config tstorm_mac_filter = {0};
4561 int mode = bp->rx_mode;
4562 int mask = (1 << BP_L_ID(bp));
4563 int func = BP_FUNC(bp);
4566 DP(NETIF_MSG_RX_STATUS, "rx mode is %d\n", mode);
4569 case BNX2X_RX_MODE_NONE: /* no Rx */
4570 tstorm_mac_filter.ucast_drop_all = mask;
4571 tstorm_mac_filter.mcast_drop_all = mask;
4572 tstorm_mac_filter.bcast_drop_all = mask;
4574 case BNX2X_RX_MODE_NORMAL:
4575 tstorm_mac_filter.bcast_accept_all = mask;
4577 case BNX2X_RX_MODE_ALLMULTI:
4578 tstorm_mac_filter.mcast_accept_all = mask;
4579 tstorm_mac_filter.bcast_accept_all = mask;
4581 case BNX2X_RX_MODE_PROMISC:
4582 tstorm_mac_filter.ucast_accept_all = mask;
4583 tstorm_mac_filter.mcast_accept_all = mask;
4584 tstorm_mac_filter.bcast_accept_all = mask;
4587 BNX2X_ERR("BAD rx mode (%d)\n", mode);
4591 for (i = 0; i < sizeof(struct tstorm_eth_mac_filter_config)/4; i++) {
4592 REG_WR(bp, BAR_TSTRORM_INTMEM +
4593 TSTORM_MAC_FILTER_CONFIG_OFFSET(func) + i * 4,
4594 ((u32 *)&tstorm_mac_filter)[i]);
4596 /* DP(NETIF_MSG_IFUP, "tstorm_mac_filter[%d]: 0x%08x\n", i,
4597 ((u32 *)&tstorm_mac_filter)[i]); */
4600 if (mode != BNX2X_RX_MODE_NONE)
4601 bnx2x_set_client_config(bp);
4604 static void bnx2x_init_internal_common(struct bnx2x *bp)
4608 /* Zero this manually as its initialization is
4609 currently missing in the initTool */
4610 for (i = 0; i < (USTORM_AGG_DATA_SIZE >> 2); i++)
4611 REG_WR(bp, BAR_USTRORM_INTMEM +
4612 USTORM_AGG_DATA_OFFSET + i * 4, 0);
4615 static void bnx2x_init_internal_port(struct bnx2x *bp)
4617 int port = BP_PORT(bp);
4619 REG_WR(bp, BAR_USTRORM_INTMEM + USTORM_HC_BTR_OFFSET(port), BNX2X_BTR);
4620 REG_WR(bp, BAR_CSTRORM_INTMEM + CSTORM_HC_BTR_OFFSET(port), BNX2X_BTR);
4621 REG_WR(bp, BAR_TSTRORM_INTMEM + TSTORM_HC_BTR_OFFSET(port), BNX2X_BTR);
4622 REG_WR(bp, BAR_XSTRORM_INTMEM + XSTORM_HC_BTR_OFFSET(port), BNX2X_BTR);
4625 static void bnx2x_init_internal_func(struct bnx2x *bp)
4627 struct tstorm_eth_function_common_config tstorm_config = {0};
4628 struct stats_indication_flags stats_flags = {0};
4629 int port = BP_PORT(bp);
4630 int func = BP_FUNC(bp);
4635 tstorm_config.config_flags = MULTI_FLAGS;
4636 tstorm_config.rss_result_mask = MULTI_MASK;
4639 tstorm_config.leading_client_id = BP_L_ID(bp);
4641 REG_WR(bp, BAR_TSTRORM_INTMEM +
4642 TSTORM_FUNCTION_COMMON_CONFIG_OFFSET(func),
4643 (*(u32 *)&tstorm_config));
4645 bp->rx_mode = BNX2X_RX_MODE_NONE; /* no rx until link is up */
4646 bnx2x_set_storm_rx_mode(bp);
4648 /* reset xstorm per client statistics */
4649 for (i = 0; i < sizeof(struct xstorm_per_client_stats) / 4; i++) {
4650 REG_WR(bp, BAR_XSTRORM_INTMEM +
4651 XSTORM_PER_COUNTER_ID_STATS_OFFSET(port, BP_CL_ID(bp)) +
4654 /* reset tstorm per client statistics */
4655 for (i = 0; i < sizeof(struct tstorm_per_client_stats) / 4; i++) {
4656 REG_WR(bp, BAR_TSTRORM_INTMEM +
4657 TSTORM_PER_COUNTER_ID_STATS_OFFSET(port, BP_CL_ID(bp)) +
4661 /* Init statistics related context */
4662 stats_flags.collect_eth = 1;
4664 REG_WR(bp, BAR_XSTRORM_INTMEM + XSTORM_STATS_FLAGS_OFFSET(func),
4665 ((u32 *)&stats_flags)[0]);
4666 REG_WR(bp, BAR_XSTRORM_INTMEM + XSTORM_STATS_FLAGS_OFFSET(func) + 4,
4667 ((u32 *)&stats_flags)[1]);
4669 REG_WR(bp, BAR_TSTRORM_INTMEM + TSTORM_STATS_FLAGS_OFFSET(func),
4670 ((u32 *)&stats_flags)[0]);
4671 REG_WR(bp, BAR_TSTRORM_INTMEM + TSTORM_STATS_FLAGS_OFFSET(func) + 4,
4672 ((u32 *)&stats_flags)[1]);
4674 REG_WR(bp, BAR_CSTRORM_INTMEM + CSTORM_STATS_FLAGS_OFFSET(func),
4675 ((u32 *)&stats_flags)[0]);
4676 REG_WR(bp, BAR_CSTRORM_INTMEM + CSTORM_STATS_FLAGS_OFFSET(func) + 4,
4677 ((u32 *)&stats_flags)[1]);
4679 REG_WR(bp, BAR_XSTRORM_INTMEM +
4680 XSTORM_ETH_STATS_QUERY_ADDR_OFFSET(func),
4681 U64_LO(bnx2x_sp_mapping(bp, fw_stats)));
4682 REG_WR(bp, BAR_XSTRORM_INTMEM +
4683 XSTORM_ETH_STATS_QUERY_ADDR_OFFSET(func) + 4,
4684 U64_HI(bnx2x_sp_mapping(bp, fw_stats)));
4686 REG_WR(bp, BAR_TSTRORM_INTMEM +
4687 TSTORM_ETH_STATS_QUERY_ADDR_OFFSET(func),
4688 U64_LO(bnx2x_sp_mapping(bp, fw_stats)));
4689 REG_WR(bp, BAR_TSTRORM_INTMEM +
4690 TSTORM_ETH_STATS_QUERY_ADDR_OFFSET(func) + 4,
4691 U64_HI(bnx2x_sp_mapping(bp, fw_stats)));
4693 if (CHIP_IS_E1H(bp)) {
4694 REG_WR8(bp, BAR_XSTRORM_INTMEM + XSTORM_FUNCTION_MODE_OFFSET,
4696 REG_WR8(bp, BAR_TSTRORM_INTMEM + TSTORM_FUNCTION_MODE_OFFSET,
4698 REG_WR8(bp, BAR_CSTRORM_INTMEM + CSTORM_FUNCTION_MODE_OFFSET,
4700 REG_WR8(bp, BAR_USTRORM_INTMEM + USTORM_FUNCTION_MODE_OFFSET,
4703 REG_WR16(bp, BAR_XSTRORM_INTMEM + XSTORM_E1HOV_OFFSET(func),
4707 /* Init CQ ring mapping and aggregation size */
4708 max_agg_size = min((u32)(bp->rx_buf_use_size +
4709 8*BCM_PAGE_SIZE*PAGES_PER_SGE),
4711 for_each_queue(bp, i) {
4712 struct bnx2x_fastpath *fp = &bp->fp[i];
4714 REG_WR(bp, BAR_USTRORM_INTMEM +
4715 USTORM_CQE_PAGE_BASE_OFFSET(port, FP_CL_ID(fp)),
4716 U64_LO(fp->rx_comp_mapping));
4717 REG_WR(bp, BAR_USTRORM_INTMEM +
4718 USTORM_CQE_PAGE_BASE_OFFSET(port, FP_CL_ID(fp)) + 4,
4719 U64_HI(fp->rx_comp_mapping));
4721 REG_WR16(bp, BAR_USTRORM_INTMEM +
4722 USTORM_MAX_AGG_SIZE_OFFSET(port, FP_CL_ID(fp)),
4727 static void bnx2x_init_internal(struct bnx2x *bp, u32 load_code)
4729 switch (load_code) {
4730 case FW_MSG_CODE_DRV_LOAD_COMMON:
4731 bnx2x_init_internal_common(bp);
4734 case FW_MSG_CODE_DRV_LOAD_PORT:
4735 bnx2x_init_internal_port(bp);
4738 case FW_MSG_CODE_DRV_LOAD_FUNCTION:
4739 bnx2x_init_internal_func(bp);
4743 BNX2X_ERR("Unknown load_code (0x%x) from MCP\n", load_code);
4748 static void bnx2x_nic_init(struct bnx2x *bp, u32 load_code)
4752 for_each_queue(bp, i) {
4753 struct bnx2x_fastpath *fp = &bp->fp[i];
4756 fp->state = BNX2X_FP_STATE_CLOSED;
4758 fp->cl_id = BP_L_ID(bp) + i;
4759 fp->sb_id = fp->cl_id;
4761 "bnx2x_init_sb(%p,%p) index %d cl_id %d sb %d\n",
4762 bp, fp->status_blk, i, FP_CL_ID(fp), FP_SB_ID(fp));
4763 bnx2x_init_sb(bp, fp->status_blk, fp->status_blk_mapping,
4765 bnx2x_update_fpsb_idx(fp);
4768 bnx2x_init_def_sb(bp, bp->def_status_blk, bp->def_status_blk_mapping,
4770 bnx2x_update_dsb_idx(bp);
4771 bnx2x_update_coalesce(bp);
4772 bnx2x_init_rx_rings(bp);
4773 bnx2x_init_tx_ring(bp);
4774 bnx2x_init_sp_ring(bp);
4775 bnx2x_init_context(bp);
4776 bnx2x_init_internal(bp, load_code);
4777 bnx2x_init_ind_table(bp);
4778 bnx2x_int_enable(bp);
4781 /* end of nic init */
4784 * gzip service functions
4787 static int bnx2x_gunzip_init(struct bnx2x *bp)
4789 bp->gunzip_buf = pci_alloc_consistent(bp->pdev, FW_BUF_SIZE,
4790 &bp->gunzip_mapping);
4791 if (bp->gunzip_buf == NULL)
4794 bp->strm = kmalloc(sizeof(*bp->strm), GFP_KERNEL);
4795 if (bp->strm == NULL)
4798 bp->strm->workspace = kmalloc(zlib_inflate_workspacesize(),
4800 if (bp->strm->workspace == NULL)
4810 pci_free_consistent(bp->pdev, FW_BUF_SIZE, bp->gunzip_buf,
4811 bp->gunzip_mapping);
4812 bp->gunzip_buf = NULL;
4815 printk(KERN_ERR PFX "%s: Cannot allocate firmware buffer for"
4816 " un-compression\n", bp->dev->name);
4820 static void bnx2x_gunzip_end(struct bnx2x *bp)
4822 kfree(bp->strm->workspace);
4827 if (bp->gunzip_buf) {
4828 pci_free_consistent(bp->pdev, FW_BUF_SIZE, bp->gunzip_buf,
4829 bp->gunzip_mapping);
4830 bp->gunzip_buf = NULL;
4834 static int bnx2x_gunzip(struct bnx2x *bp, u8 *zbuf, int len)
4838 /* check gzip header */
4839 if ((zbuf[0] != 0x1f) || (zbuf[1] != 0x8b) || (zbuf[2] != Z_DEFLATED))
4846 if (zbuf[3] & FNAME)
4847 while ((zbuf[n++] != 0) && (n < len));
4849 bp->strm->next_in = zbuf + n;
4850 bp->strm->avail_in = len - n;
4851 bp->strm->next_out = bp->gunzip_buf;
4852 bp->strm->avail_out = FW_BUF_SIZE;
4854 rc = zlib_inflateInit2(bp->strm, -MAX_WBITS);
4858 rc = zlib_inflate(bp->strm, Z_FINISH);
4859 if ((rc != Z_OK) && (rc != Z_STREAM_END))
4860 printk(KERN_ERR PFX "%s: Firmware decompression error: %s\n",
4861 bp->dev->name, bp->strm->msg);
4863 bp->gunzip_outlen = (FW_BUF_SIZE - bp->strm->avail_out);
4864 if (bp->gunzip_outlen & 0x3)
4865 printk(KERN_ERR PFX "%s: Firmware decompression error:"
4866 " gunzip_outlen (%d) not aligned\n",
4867 bp->dev->name, bp->gunzip_outlen);
4868 bp->gunzip_outlen >>= 2;
4870 zlib_inflateEnd(bp->strm);
4872 if (rc == Z_STREAM_END)
4878 /* nic load/unload */
4881 * General service functions
4884 /* send a NIG loopback debug packet */
4885 static void bnx2x_lb_pckt(struct bnx2x *bp)
4889 /* Ethernet source and destination addresses */
4890 wb_write[0] = 0x55555555;
4891 wb_write[1] = 0x55555555;
4892 wb_write[2] = 0x20; /* SOP */
4893 REG_WR_DMAE(bp, NIG_REG_DEBUG_PACKET_LB, wb_write, 3);
4895 /* NON-IP protocol */
4896 wb_write[0] = 0x09000000;
4897 wb_write[1] = 0x55555555;
4898 wb_write[2] = 0x10; /* EOP, eop_bvalid = 0 */
4899 REG_WR_DMAE(bp, NIG_REG_DEBUG_PACKET_LB, wb_write, 3);
4902 /* some of the internal memories
4903 * are not directly readable from the driver
4904 * to test them we send debug packets
4906 static int bnx2x_int_mem_test(struct bnx2x *bp)
4912 if (CHIP_REV_IS_FPGA(bp))
4914 else if (CHIP_REV_IS_EMUL(bp))
4919 DP(NETIF_MSG_HW, "start part1\n");
4921 /* Disable inputs of parser neighbor blocks */
4922 REG_WR(bp, TSDM_REG_ENABLE_IN1, 0x0);
4923 REG_WR(bp, TCM_REG_PRS_IFEN, 0x0);
4924 REG_WR(bp, CFC_REG_DEBUG0, 0x1);
4925 NIG_WR(NIG_REG_PRS_REQ_IN_EN, 0x0);
4927 /* Write 0 to parser credits for CFC search request */
4928 REG_WR(bp, PRS_REG_CFC_SEARCH_INITIAL_CREDIT, 0x0);
4930 /* send Ethernet packet */
4933 /* TODO do i reset NIG statistic? */
4934 /* Wait until NIG register shows 1 packet of size 0x10 */
4935 count = 1000 * factor;
4938 bnx2x_read_dmae(bp, NIG_REG_STAT2_BRB_OCTET, 2);
4939 val = *bnx2x_sp(bp, wb_data[0]);
4947 BNX2X_ERR("NIG timeout val = 0x%x\n", val);
4951 /* Wait until PRS register shows 1 packet */
4952 count = 1000 * factor;
4954 val = REG_RD(bp, PRS_REG_NUM_OF_PACKETS);
4962 BNX2X_ERR("PRS timeout val = 0x%x\n", val);
4966 /* Reset and init BRB, PRS */
4967 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR, 0x03);
4969 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, 0x03);
4971 bnx2x_init_block(bp, BRB1_COMMON_START, BRB1_COMMON_END);
4972 bnx2x_init_block(bp, PRS_COMMON_START, PRS_COMMON_END);
4974 DP(NETIF_MSG_HW, "part2\n");
4976 /* Disable inputs of parser neighbor blocks */
4977 REG_WR(bp, TSDM_REG_ENABLE_IN1, 0x0);
4978 REG_WR(bp, TCM_REG_PRS_IFEN, 0x0);
4979 REG_WR(bp, CFC_REG_DEBUG0, 0x1);
4980 NIG_WR(NIG_REG_PRS_REQ_IN_EN, 0x0);
4982 /* Write 0 to parser credits for CFC search request */
4983 REG_WR(bp, PRS_REG_CFC_SEARCH_INITIAL_CREDIT, 0x0);
4985 /* send 10 Ethernet packets */
4986 for (i = 0; i < 10; i++)
4989 /* Wait until NIG register shows 10 + 1
4990 packets of size 11*0x10 = 0xb0 */
4991 count = 1000 * factor;
4994 bnx2x_read_dmae(bp, NIG_REG_STAT2_BRB_OCTET, 2);
4995 val = *bnx2x_sp(bp, wb_data[0]);
5003 BNX2X_ERR("NIG timeout val = 0x%x\n", val);
5007 /* Wait until PRS register shows 2 packets */
5008 val = REG_RD(bp, PRS_REG_NUM_OF_PACKETS);
5010 BNX2X_ERR("PRS timeout val = 0x%x\n", val);
5012 /* Write 1 to parser credits for CFC search request */
5013 REG_WR(bp, PRS_REG_CFC_SEARCH_INITIAL_CREDIT, 0x1);
5015 /* Wait until PRS register shows 3 packets */
5016 msleep(10 * factor);
5017 /* Wait until NIG register shows 1 packet of size 0x10 */
5018 val = REG_RD(bp, PRS_REG_NUM_OF_PACKETS);
5020 BNX2X_ERR("PRS timeout val = 0x%x\n", val);
5022 /* clear NIG EOP FIFO */
5023 for (i = 0; i < 11; i++)
5024 REG_RD(bp, NIG_REG_INGRESS_EOP_LB_FIFO);
5025 val = REG_RD(bp, NIG_REG_INGRESS_EOP_LB_EMPTY);
5027 BNX2X_ERR("clear of NIG failed\n");
5031 /* Reset and init BRB, PRS, NIG */
5032 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR, 0x03);
5034 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, 0x03);
5036 bnx2x_init_block(bp, BRB1_COMMON_START, BRB1_COMMON_END);
5037 bnx2x_init_block(bp, PRS_COMMON_START, PRS_COMMON_END);
5040 REG_WR(bp, PRS_REG_NIC_MODE, 1);
5043 /* Enable inputs of parser neighbor blocks */
5044 REG_WR(bp, TSDM_REG_ENABLE_IN1, 0x7fffffff);
5045 REG_WR(bp, TCM_REG_PRS_IFEN, 0x1);
5046 REG_WR(bp, CFC_REG_DEBUG0, 0x0);
5047 NIG_WR(NIG_REG_PRS_REQ_IN_EN, 0x1);
5049 DP(NETIF_MSG_HW, "done\n");
5054 static void enable_blocks_attention(struct bnx2x *bp)
5056 REG_WR(bp, PXP_REG_PXP_INT_MASK_0, 0);
5057 REG_WR(bp, PXP_REG_PXP_INT_MASK_1, 0);
5058 REG_WR(bp, DORQ_REG_DORQ_INT_MASK, 0);
5059 REG_WR(bp, CFC_REG_CFC_INT_MASK, 0);
5060 REG_WR(bp, QM_REG_QM_INT_MASK, 0);
5061 REG_WR(bp, TM_REG_TM_INT_MASK, 0);
5062 REG_WR(bp, XSDM_REG_XSDM_INT_MASK_0, 0);
5063 REG_WR(bp, XSDM_REG_XSDM_INT_MASK_1, 0);
5064 REG_WR(bp, XCM_REG_XCM_INT_MASK, 0);
5065 /* REG_WR(bp, XSEM_REG_XSEM_INT_MASK_0, 0); */
5066 /* REG_WR(bp, XSEM_REG_XSEM_INT_MASK_1, 0); */
5067 REG_WR(bp, USDM_REG_USDM_INT_MASK_0, 0);
5068 REG_WR(bp, USDM_REG_USDM_INT_MASK_1, 0);
5069 REG_WR(bp, UCM_REG_UCM_INT_MASK, 0);
5070 /* REG_WR(bp, USEM_REG_USEM_INT_MASK_0, 0); */
5071 /* REG_WR(bp, USEM_REG_USEM_INT_MASK_1, 0); */
5072 REG_WR(bp, GRCBASE_UPB + PB_REG_PB_INT_MASK, 0);
5073 REG_WR(bp, CSDM_REG_CSDM_INT_MASK_0, 0);
5074 REG_WR(bp, CSDM_REG_CSDM_INT_MASK_1, 0);
5075 REG_WR(bp, CCM_REG_CCM_INT_MASK, 0);
5076 /* REG_WR(bp, CSEM_REG_CSEM_INT_MASK_0, 0); */
5077 /* REG_WR(bp, CSEM_REG_CSEM_INT_MASK_1, 0); */
5078 if (CHIP_REV_IS_FPGA(bp))
5079 REG_WR(bp, PXP2_REG_PXP2_INT_MASK_0, 0x580000);
5081 REG_WR(bp, PXP2_REG_PXP2_INT_MASK_0, 0x480000);
5082 REG_WR(bp, TSDM_REG_TSDM_INT_MASK_0, 0);
5083 REG_WR(bp, TSDM_REG_TSDM_INT_MASK_1, 0);
5084 REG_WR(bp, TCM_REG_TCM_INT_MASK, 0);
5085 /* REG_WR(bp, TSEM_REG_TSEM_INT_MASK_0, 0); */
5086 /* REG_WR(bp, TSEM_REG_TSEM_INT_MASK_1, 0); */
5087 REG_WR(bp, CDU_REG_CDU_INT_MASK, 0);
5088 REG_WR(bp, DMAE_REG_DMAE_INT_MASK, 0);
5089 /* REG_WR(bp, MISC_REG_MISC_INT_MASK, 0); */
5090 REG_WR(bp, PBF_REG_PBF_INT_MASK, 0X18); /* bit 3,4 masked */
5094 static int bnx2x_init_common(struct bnx2x *bp)
5098 DP(BNX2X_MSG_MCP, "starting common init func %d\n", BP_FUNC(bp));
5100 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, 0xffffffff);
5101 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET, 0xfffc);
5103 bnx2x_init_block(bp, MISC_COMMON_START, MISC_COMMON_END);
5104 if (CHIP_IS_E1H(bp))
5105 REG_WR(bp, MISC_REG_E1HMF_MODE, IS_E1HMF(bp));
5107 REG_WR(bp, MISC_REG_LCPLL_CTRL_REG_2, 0x100);
5109 REG_WR(bp, MISC_REG_LCPLL_CTRL_REG_2, 0x0);
5111 bnx2x_init_block(bp, PXP_COMMON_START, PXP_COMMON_END);
5112 if (CHIP_IS_E1(bp)) {
5113 /* enable HW interrupt from PXP on USDM overflow
5114 bit 16 on INT_MASK_0 */
5115 REG_WR(bp, PXP_REG_PXP_INT_MASK_0, 0);
5118 bnx2x_init_block(bp, PXP2_COMMON_START, PXP2_COMMON_END);
5122 REG_WR(bp, PXP2_REG_RQ_QM_ENDIAN_M, 1);
5123 REG_WR(bp, PXP2_REG_RQ_TM_ENDIAN_M, 1);
5124 REG_WR(bp, PXP2_REG_RQ_SRC_ENDIAN_M, 1);
5125 REG_WR(bp, PXP2_REG_RQ_CDU_ENDIAN_M, 1);
5126 REG_WR(bp, PXP2_REG_RQ_DBG_ENDIAN_M, 1);
5127 REG_WR(bp, PXP2_REG_RQ_HC_ENDIAN_M, 1);
5129 /* REG_WR(bp, PXP2_REG_RD_PBF_SWAP_MODE, 1); */
5130 REG_WR(bp, PXP2_REG_RD_QM_SWAP_MODE, 1);
5131 REG_WR(bp, PXP2_REG_RD_TM_SWAP_MODE, 1);
5132 REG_WR(bp, PXP2_REG_RD_SRC_SWAP_MODE, 1);
5133 REG_WR(bp, PXP2_REG_RD_CDURD_SWAP_MODE, 1);
5138 REG_WR(bp, PRS_REG_NIC_MODE, 1);
5141 REG_WR(bp, PXP2_REG_RQ_CDU_P_SIZE, 2);
5143 REG_WR(bp, PXP2_REG_RQ_TM_P_SIZE, 5);
5144 REG_WR(bp, PXP2_REG_RQ_QM_P_SIZE, 5);
5145 REG_WR(bp, PXP2_REG_RQ_SRC_P_SIZE, 5);
5148 if (CHIP_REV_IS_FPGA(bp) && CHIP_IS_E1H(bp))
5149 REG_WR(bp, PXP2_REG_PGL_TAGS_LIMIT, 0x1);
5151 /* let the HW do it's magic ... */
5153 /* finish PXP init */
5154 val = REG_RD(bp, PXP2_REG_RQ_CFG_DONE);
5156 BNX2X_ERR("PXP2 CFG failed\n");
5159 val = REG_RD(bp, PXP2_REG_RD_INIT_DONE);
5161 BNX2X_ERR("PXP2 RD_INIT failed\n");
5165 REG_WR(bp, PXP2_REG_RQ_DISABLE_INPUTS, 0);
5166 REG_WR(bp, PXP2_REG_RD_DISABLE_INPUTS, 0);
5168 bnx2x_init_block(bp, DMAE_COMMON_START, DMAE_COMMON_END);
5170 /* clean the DMAE memory */
5172 bnx2x_init_fill(bp, TSEM_REG_PRAM, 0, 8);
5174 bnx2x_init_block(bp, TCM_COMMON_START, TCM_COMMON_END);
5175 bnx2x_init_block(bp, UCM_COMMON_START, UCM_COMMON_END);
5176 bnx2x_init_block(bp, CCM_COMMON_START, CCM_COMMON_END);
5177 bnx2x_init_block(bp, XCM_COMMON_START, XCM_COMMON_END);
5179 bnx2x_read_dmae(bp, XSEM_REG_PASSIVE_BUFFER, 3);
5180 bnx2x_read_dmae(bp, CSEM_REG_PASSIVE_BUFFER, 3);
5181 bnx2x_read_dmae(bp, TSEM_REG_PASSIVE_BUFFER, 3);
5182 bnx2x_read_dmae(bp, USEM_REG_PASSIVE_BUFFER, 3);
5184 bnx2x_init_block(bp, QM_COMMON_START, QM_COMMON_END);
5185 /* soft reset pulse */
5186 REG_WR(bp, QM_REG_SOFT_RESET, 1);
5187 REG_WR(bp, QM_REG_SOFT_RESET, 0);
5190 bnx2x_init_block(bp, TIMERS_COMMON_START, TIMERS_COMMON_END);
5193 bnx2x_init_block(bp, DQ_COMMON_START, DQ_COMMON_END);
5194 REG_WR(bp, DORQ_REG_DPM_CID_OFST, BCM_PAGE_SHIFT);
5195 if (!CHIP_REV_IS_SLOW(bp)) {
5196 /* enable hw interrupt from doorbell Q */
5197 REG_WR(bp, DORQ_REG_DORQ_INT_MASK, 0);
5200 bnx2x_init_block(bp, BRB1_COMMON_START, BRB1_COMMON_END);
5201 if (CHIP_REV_IS_SLOW(bp)) {
5202 /* fix for emulation and FPGA for no pause */
5203 REG_WR(bp, BRB1_REG_PAUSE_HIGH_THRESHOLD_0, 513);
5204 REG_WR(bp, BRB1_REG_PAUSE_HIGH_THRESHOLD_1, 513);
5205 REG_WR(bp, BRB1_REG_PAUSE_LOW_THRESHOLD_0, 0);
5206 REG_WR(bp, BRB1_REG_PAUSE_LOW_THRESHOLD_1, 0);
5209 bnx2x_init_block(bp, PRS_COMMON_START, PRS_COMMON_END);
5210 if (CHIP_IS_E1H(bp))
5211 REG_WR(bp, PRS_REG_E1HOV_MODE, IS_E1HMF(bp));
5213 bnx2x_init_block(bp, TSDM_COMMON_START, TSDM_COMMON_END);
5214 bnx2x_init_block(bp, CSDM_COMMON_START, CSDM_COMMON_END);
5215 bnx2x_init_block(bp, USDM_COMMON_START, USDM_COMMON_END);
5216 bnx2x_init_block(bp, XSDM_COMMON_START, XSDM_COMMON_END);
5218 if (CHIP_IS_E1H(bp)) {
5219 bnx2x_init_fill(bp, TSTORM_INTMEM_ADDR, 0,
5220 STORM_INTMEM_SIZE_E1H/2);
5222 TSTORM_INTMEM_ADDR + STORM_INTMEM_SIZE_E1H/2,
5223 0, STORM_INTMEM_SIZE_E1H/2);
5224 bnx2x_init_fill(bp, CSTORM_INTMEM_ADDR, 0,
5225 STORM_INTMEM_SIZE_E1H/2);
5227 CSTORM_INTMEM_ADDR + STORM_INTMEM_SIZE_E1H/2,
5228 0, STORM_INTMEM_SIZE_E1H/2);
5229 bnx2x_init_fill(bp, XSTORM_INTMEM_ADDR, 0,
5230 STORM_INTMEM_SIZE_E1H/2);
5232 XSTORM_INTMEM_ADDR + STORM_INTMEM_SIZE_E1H/2,
5233 0, STORM_INTMEM_SIZE_E1H/2);
5234 bnx2x_init_fill(bp, USTORM_INTMEM_ADDR, 0,
5235 STORM_INTMEM_SIZE_E1H/2);
5237 USTORM_INTMEM_ADDR + STORM_INTMEM_SIZE_E1H/2,
5238 0, STORM_INTMEM_SIZE_E1H/2);
5240 bnx2x_init_fill(bp, TSTORM_INTMEM_ADDR, 0,
5241 STORM_INTMEM_SIZE_E1);
5242 bnx2x_init_fill(bp, CSTORM_INTMEM_ADDR, 0,
5243 STORM_INTMEM_SIZE_E1);
5244 bnx2x_init_fill(bp, XSTORM_INTMEM_ADDR, 0,
5245 STORM_INTMEM_SIZE_E1);
5246 bnx2x_init_fill(bp, USTORM_INTMEM_ADDR, 0,
5247 STORM_INTMEM_SIZE_E1);
5250 bnx2x_init_block(bp, TSEM_COMMON_START, TSEM_COMMON_END);
5251 bnx2x_init_block(bp, USEM_COMMON_START, USEM_COMMON_END);
5252 bnx2x_init_block(bp, CSEM_COMMON_START, CSEM_COMMON_END);
5253 bnx2x_init_block(bp, XSEM_COMMON_START, XSEM_COMMON_END);
5256 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR,
5258 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET,
5261 bnx2x_init_block(bp, UPB_COMMON_START, UPB_COMMON_END);
5262 bnx2x_init_block(bp, XPB_COMMON_START, XPB_COMMON_END);
5263 bnx2x_init_block(bp, PBF_COMMON_START, PBF_COMMON_END);
5265 REG_WR(bp, SRC_REG_SOFT_RST, 1);
5266 for (i = SRC_REG_KEYRSS0_0; i <= SRC_REG_KEYRSS1_9; i += 4) {
5267 REG_WR(bp, i, 0xc0cac01a);
5268 /* TODO: replace with something meaningful */
5270 if (CHIP_IS_E1H(bp))
5271 bnx2x_init_block(bp, SRCH_COMMON_START, SRCH_COMMON_END);
5272 REG_WR(bp, SRC_REG_SOFT_RST, 0);
5274 if (sizeof(union cdu_context) != 1024)
5275 /* we currently assume that a context is 1024 bytes */
5276 printk(KERN_ALERT PFX "please adjust the size of"
5277 " cdu_context(%ld)\n", (long)sizeof(union cdu_context));
5279 bnx2x_init_block(bp, CDU_COMMON_START, CDU_COMMON_END);
5280 val = (4 << 24) + (0 << 12) + 1024;
5281 REG_WR(bp, CDU_REG_CDU_GLOBAL_PARAMS, val);
5282 if (CHIP_IS_E1(bp)) {
5283 /* !!! fix pxp client crdit until excel update */
5284 REG_WR(bp, CDU_REG_CDU_DEBUG, 0x264);
5285 REG_WR(bp, CDU_REG_CDU_DEBUG, 0);
5288 bnx2x_init_block(bp, CFC_COMMON_START, CFC_COMMON_END);
5289 REG_WR(bp, CFC_REG_INIT_REG, 0x7FF);
5291 bnx2x_init_block(bp, HC_COMMON_START, HC_COMMON_END);
5292 bnx2x_init_block(bp, MISC_AEU_COMMON_START, MISC_AEU_COMMON_END);
5294 /* PXPCS COMMON comes here */
5295 /* Reset PCIE errors for debug */
5296 REG_WR(bp, 0x2814, 0xffffffff);
5297 REG_WR(bp, 0x3820, 0xffffffff);
5299 /* EMAC0 COMMON comes here */
5300 /* EMAC1 COMMON comes here */
5301 /* DBU COMMON comes here */
5302 /* DBG COMMON comes here */
5304 bnx2x_init_block(bp, NIG_COMMON_START, NIG_COMMON_END);
5305 if (CHIP_IS_E1H(bp)) {
5306 REG_WR(bp, NIG_REG_LLH_MF_MODE, IS_E1HMF(bp));
5307 REG_WR(bp, NIG_REG_LLH_E1HOV_MODE, IS_E1HMF(bp));
5310 if (CHIP_REV_IS_SLOW(bp))
5313 /* finish CFC init */
5314 val = reg_poll(bp, CFC_REG_LL_INIT_DONE, 1, 100, 10);
5316 BNX2X_ERR("CFC LL_INIT failed\n");
5319 val = reg_poll(bp, CFC_REG_AC_INIT_DONE, 1, 100, 10);
5321 BNX2X_ERR("CFC AC_INIT failed\n");
5324 val = reg_poll(bp, CFC_REG_CAM_INIT_DONE, 1, 100, 10);
5326 BNX2X_ERR("CFC CAM_INIT failed\n");
5329 REG_WR(bp, CFC_REG_DEBUG0, 0);
5331 /* read NIG statistic
5332 to see if this is our first up since powerup */
5333 bnx2x_read_dmae(bp, NIG_REG_STAT2_BRB_OCTET, 2);
5334 val = *bnx2x_sp(bp, wb_data[0]);
5336 /* do internal memory self test */
5337 if ((CHIP_IS_E1(bp)) && (val == 0) && bnx2x_int_mem_test(bp)) {
5338 BNX2X_ERR("internal mem self test failed\n");
5342 switch (bp->common.board & SHARED_HW_CFG_BOARD_TYPE_MASK) {
5343 case SHARED_HW_CFG_BOARD_TYPE_BCM957710A1022G:
5344 /* Fan failure is indicated by SPIO 5 */
5345 bnx2x_set_spio(bp, MISC_REGISTERS_SPIO_5,
5346 MISC_REGISTERS_SPIO_INPUT_HI_Z);
5348 /* set to active low mode */
5349 val = REG_RD(bp, MISC_REG_SPIO_INT);
5350 val |= ((1 << MISC_REGISTERS_SPIO_5) <<
5351 MISC_REGISTERS_SPIO_INT_OLD_SET_POS);
5352 REG_WR(bp, MISC_REG_SPIO_INT, val);
5354 /* enable interrupt to signal the IGU */
5355 val = REG_RD(bp, MISC_REG_SPIO_EVENT_EN);
5356 val |= (1 << MISC_REGISTERS_SPIO_5);
5357 REG_WR(bp, MISC_REG_SPIO_EVENT_EN, val);
5364 /* clear PXP2 attentions */
5365 REG_RD(bp, PXP2_REG_PXP2_INT_STS_CLR_0);
5367 enable_blocks_attention(bp);
5369 if (bp->flags & TPA_ENABLE_FLAG) {
5370 struct tstorm_eth_tpa_exist tmp = {0};
5374 REG_WR(bp, BAR_TSTRORM_INTMEM + TSTORM_TPA_EXIST_OFFSET,
5376 REG_WR(bp, BAR_TSTRORM_INTMEM + TSTORM_TPA_EXIST_OFFSET + 4,
5383 static int bnx2x_init_port(struct bnx2x *bp)
5385 int port = BP_PORT(bp);
5388 DP(BNX2X_MSG_MCP, "starting port init port %x\n", port);
5390 REG_WR(bp, NIG_REG_MASK_INTERRUPT_PORT0 + port*4, 0);
5392 /* Port PXP comes here */
5393 /* Port PXP2 comes here */
5398 wb_write[0] = ONCHIP_ADDR1(bp->timers_mapping);
5399 wb_write[1] = ONCHIP_ADDR2(bp->timers_mapping);
5400 REG_WR_DMAE(bp, PXP2_REG_RQ_ONCHIP_AT + i*8, wb_write, 2);
5401 REG_WR(bp, PXP2_REG_PSWRQ_TM0_L2P + func*4, PXP_ONE_ILT(i));
5406 wb_write[0] = ONCHIP_ADDR1(bp->qm_mapping);
5407 wb_write[1] = ONCHIP_ADDR2(bp->qm_mapping);
5408 REG_WR_DMAE(bp, PXP2_REG_RQ_ONCHIP_AT + i*8, wb_write, 2);
5409 REG_WR(bp, PXP2_REG_PSWRQ_QM0_L2P + func*4, PXP_ONE_ILT(i));
5414 wb_write[0] = ONCHIP_ADDR1(bp->t1_mapping);
5415 wb_write[1] = ONCHIP_ADDR2(bp->t1_mapping);
5416 REG_WR_DMAE(bp, PXP2_REG_RQ_ONCHIP_AT + i*8, wb_write, 2);
5417 REG_WR(bp, PXP2_REG_PSWRQ_SRC0_L2P + func*4, PXP_ONE_ILT(i));
5419 /* Port CMs come here */
5421 /* Port QM comes here */
5423 REG_WR(bp, TM_REG_LIN0_SCAN_TIME + func*4, 1024/64*20);
5424 REG_WR(bp, TM_REG_LIN0_MAX_ACTIVE_CID + func*4, 31);
5426 bnx2x_init_block(bp, func ? TIMERS_PORT1_START : TIMERS_PORT0_START,
5427 func ? TIMERS_PORT1_END : TIMERS_PORT0_END);
5429 /* Port DQ comes here */
5430 /* Port BRB1 comes here */
5431 /* Port PRS comes here */
5432 /* Port TSDM comes here */
5433 /* Port CSDM comes here */
5434 /* Port USDM comes here */
5435 /* Port XSDM comes here */
5436 bnx2x_init_block(bp, port ? TSEM_PORT1_START : TSEM_PORT0_START,
5437 port ? TSEM_PORT1_END : TSEM_PORT0_END);
5438 bnx2x_init_block(bp, port ? USEM_PORT1_START : USEM_PORT0_START,
5439 port ? USEM_PORT1_END : USEM_PORT0_END);
5440 bnx2x_init_block(bp, port ? CSEM_PORT1_START : CSEM_PORT0_START,
5441 port ? CSEM_PORT1_END : CSEM_PORT0_END);
5442 bnx2x_init_block(bp, port ? XSEM_PORT1_START : XSEM_PORT0_START,
5443 port ? XSEM_PORT1_END : XSEM_PORT0_END);
5444 /* Port UPB comes here */
5445 /* Port XPB comes here */
5447 bnx2x_init_block(bp, port ? PBF_PORT1_START : PBF_PORT0_START,
5448 port ? PBF_PORT1_END : PBF_PORT0_END);
5450 /* configure PBF to work without PAUSE mtu 9000 */
5451 REG_WR(bp, PBF_REG_P0_PAUSE_ENABLE + port*4, 0);
5453 /* update threshold */
5454 REG_WR(bp, PBF_REG_P0_ARB_THRSH + port*4, (9040/16));
5455 /* update init credit */
5456 REG_WR(bp, PBF_REG_P0_INIT_CRD + port*4, (9040/16) + 553 - 22);
5459 REG_WR(bp, PBF_REG_INIT_P0 + port*4, 1);
5461 REG_WR(bp, PBF_REG_INIT_P0 + port*4, 0);
5464 /* tell the searcher where the T2 table is */
5465 REG_WR(bp, SRC_REG_COUNTFREE0 + func*4, 16*1024/64);
5467 wb_write[0] = U64_LO(bp->t2_mapping);
5468 wb_write[1] = U64_HI(bp->t2_mapping);
5469 REG_WR_DMAE(bp, SRC_REG_FIRSTFREE0 + func*4, wb_write, 2);
5470 wb_write[0] = U64_LO((u64)bp->t2_mapping + 16*1024 - 64);
5471 wb_write[1] = U64_HI((u64)bp->t2_mapping + 16*1024 - 64);
5472 REG_WR_DMAE(bp, SRC_REG_LASTFREE0 + func*4, wb_write, 2);
5474 REG_WR(bp, SRC_REG_NUMBER_HASH_BITS0 + func*4, 10);
5475 /* Port SRCH comes here */
5477 /* Port CDU comes here */
5478 /* Port CFC comes here */
5480 if (CHIP_IS_E1(bp)) {
5481 REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, 0);
5482 REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, 0);
5484 bnx2x_init_block(bp, port ? HC_PORT1_START : HC_PORT0_START,
5485 port ? HC_PORT1_END : HC_PORT0_END);
5487 bnx2x_init_block(bp, port ? MISC_AEU_PORT1_START :
5488 MISC_AEU_PORT0_START,
5489 port ? MISC_AEU_PORT1_END : MISC_AEU_PORT0_END);
5490 /* init aeu_mask_attn_func_0/1:
5491 * - SF mode: bits 3-7 are masked. only bits 0-2 are in use
5492 * - MF mode: bit 3 is masked. bits 0-2 are in use as in SF
5493 * bits 4-7 are used for "per vn group attention" */
5494 REG_WR(bp, MISC_REG_AEU_MASK_ATTN_FUNC_0 + port*4,
5495 (IS_E1HMF(bp) ? 0xF7 : 0x7));
5497 /* Port PXPCS comes here */
5498 /* Port EMAC0 comes here */
5499 /* Port EMAC1 comes here */
5500 /* Port DBU comes here */
5501 /* Port DBG comes here */
5502 bnx2x_init_block(bp, port ? NIG_PORT1_START : NIG_PORT0_START,
5503 port ? NIG_PORT1_END : NIG_PORT0_END);
5505 REG_WR(bp, NIG_REG_XGXS_SERDES0_MODE_SEL + port*4, 1);
5507 if (CHIP_IS_E1H(bp)) {
5509 struct cmng_struct_per_port m_cmng_port;
5512 /* 0x2 disable e1hov, 0x1 enable */
5513 REG_WR(bp, NIG_REG_LLH0_BRB1_DRV_MASK_MF + port*4,
5514 (IS_E1HMF(bp) ? 0x1 : 0x2));
5516 /* Init RATE SHAPING and FAIRNESS contexts.
5517 Initialize as if there is 10G link. */
5518 wsum = bnx2x_calc_vn_wsum(bp);
5519 bnx2x_init_port_minmax(bp, (int)wsum, 10000, &m_cmng_port);
5521 for (vn = VN_0; vn < E1HVN_MAX; vn++)
5522 bnx2x_init_vn_minmax(bp, 2*vn + port,
5523 wsum, 10000, &m_cmng_port);
5526 /* Port MCP comes here */
5527 /* Port DMAE comes here */
5529 switch (bp->common.board & SHARED_HW_CFG_BOARD_TYPE_MASK) {
5530 case SHARED_HW_CFG_BOARD_TYPE_BCM957710A1022G:
5531 /* add SPIO 5 to group 0 */
5532 val = REG_RD(bp, MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0);
5533 val |= AEU_INPUTS_ATTN_BITS_SPIO5;
5534 REG_WR(bp, MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0, val);
5541 bnx2x__link_reset(bp);
5546 #define ILT_PER_FUNC (768/2)
5547 #define FUNC_ILT_BASE(func) (func * ILT_PER_FUNC)
5548 /* the phys address is shifted right 12 bits and has an added
5549 1=valid bit added to the 53rd bit
5550 then since this is a wide register(TM)
5551 we split it into two 32 bit writes
5553 #define ONCHIP_ADDR1(x) ((u32)(((u64)x >> 12) & 0xFFFFFFFF))
5554 #define ONCHIP_ADDR2(x) ((u32)((1 << 20) | ((u64)x >> 44)))
5555 #define PXP_ONE_ILT(x) (((x) << 10) | x)
5556 #define PXP_ILT_RANGE(f, l) (((l) << 10) | f)
5558 #define CNIC_ILT_LINES 0
5560 static void bnx2x_ilt_wr(struct bnx2x *bp, u32 index, dma_addr_t addr)
5564 if (CHIP_IS_E1H(bp))
5565 reg = PXP2_REG_RQ_ONCHIP_AT_B0 + index*8;
5567 reg = PXP2_REG_RQ_ONCHIP_AT + index*8;
5569 bnx2x_wb_wr(bp, reg, ONCHIP_ADDR1(addr), ONCHIP_ADDR2(addr));
5572 static int bnx2x_init_func(struct bnx2x *bp)
5574 int port = BP_PORT(bp);
5575 int func = BP_FUNC(bp);
5578 DP(BNX2X_MSG_MCP, "starting func init func %x\n", func);
5580 i = FUNC_ILT_BASE(func);
5582 bnx2x_ilt_wr(bp, i, bnx2x_sp_mapping(bp, context));
5583 if (CHIP_IS_E1H(bp)) {
5584 REG_WR(bp, PXP2_REG_RQ_CDU_FIRST_ILT, i);
5585 REG_WR(bp, PXP2_REG_RQ_CDU_LAST_ILT, i + CNIC_ILT_LINES);
5587 REG_WR(bp, PXP2_REG_PSWRQ_CDU0_L2P + func*4,
5588 PXP_ILT_RANGE(i, i + CNIC_ILT_LINES));
5591 if (CHIP_IS_E1H(bp)) {
5592 for (i = 0; i < 9; i++)
5593 bnx2x_init_block(bp,
5594 cm_start[func][i], cm_end[func][i]);
5596 REG_WR(bp, NIG_REG_LLH0_FUNC_EN + port*8, 1);
5597 REG_WR(bp, NIG_REG_LLH0_FUNC_VLAN_ID + port*8, bp->e1hov);
5600 /* HC init per function */
5601 if (CHIP_IS_E1H(bp)) {
5602 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_12 + func*4, 0);
5604 REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, 0);
5605 REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, 0);
5607 bnx2x_init_block(bp, hc_limits[func][0], hc_limits[func][1]);
5609 if (CHIP_IS_E1H(bp))
5610 REG_WR(bp, HC_REG_FUNC_NUM_P0 + port*4, func);
5612 /* Reset PCIE errors for debug */
5613 REG_WR(bp, 0x2114, 0xffffffff);
5614 REG_WR(bp, 0x2120, 0xffffffff);
5619 static int bnx2x_init_hw(struct bnx2x *bp, u32 load_code)
5623 DP(BNX2X_MSG_MCP, "function %d load_code %x\n",
5624 BP_FUNC(bp), load_code);
5627 mutex_init(&bp->dmae_mutex);
5628 bnx2x_gunzip_init(bp);
5630 switch (load_code) {
5631 case FW_MSG_CODE_DRV_LOAD_COMMON:
5632 rc = bnx2x_init_common(bp);
5637 case FW_MSG_CODE_DRV_LOAD_PORT:
5639 rc = bnx2x_init_port(bp);
5644 case FW_MSG_CODE_DRV_LOAD_FUNCTION:
5646 rc = bnx2x_init_func(bp);
5652 BNX2X_ERR("Unknown load_code (0x%x) from MCP\n", load_code);
5656 if (!BP_NOMCP(bp)) {
5657 int func = BP_FUNC(bp);
5659 bp->fw_drv_pulse_wr_seq =
5660 (SHMEM_RD(bp, func_mb[func].drv_pulse_mb) &
5661 DRV_PULSE_SEQ_MASK);
5662 bp->func_stx = SHMEM_RD(bp, func_mb[func].fw_mb_param);
5663 DP(BNX2X_MSG_MCP, "drv_pulse 0x%x func_stx 0x%x\n",
5664 bp->fw_drv_pulse_wr_seq, bp->func_stx);
5668 /* this needs to be done before gunzip end */
5669 bnx2x_zero_def_sb(bp);
5670 for_each_queue(bp, i)
5671 bnx2x_zero_sb(bp, BP_L_ID(bp) + i);
5674 bnx2x_gunzip_end(bp);
5679 /* send the MCP a request, block until there is a reply */
5680 static u32 bnx2x_fw_command(struct bnx2x *bp, u32 command)
5682 int func = BP_FUNC(bp);
5683 u32 seq = ++bp->fw_seq;
5686 u8 delay = CHIP_REV_IS_SLOW(bp) ? 100 : 10;
5688 SHMEM_WR(bp, func_mb[func].drv_mb_header, (command | seq));
5689 DP(BNX2X_MSG_MCP, "wrote command (%x) to FW MB\n", (command | seq));
5692 /* let the FW do it's magic ... */
5695 rc = SHMEM_RD(bp, func_mb[func].fw_mb_header);
5697 /* Give the FW up to 2 second (200*10ms) */
5698 } while ((seq != (rc & FW_MSG_SEQ_NUMBER_MASK)) && (cnt++ < 200));
5700 DP(BNX2X_MSG_MCP, "[after %d ms] read (%x) seq is (%x) from FW MB\n",
5701 cnt*delay, rc, seq);
5703 /* is this a reply to our command? */
5704 if (seq == (rc & FW_MSG_SEQ_NUMBER_MASK)) {
5705 rc &= FW_MSG_CODE_MASK;
5709 BNX2X_ERR("FW failed to respond!\n");
5717 static void bnx2x_free_mem(struct bnx2x *bp)
5720 #define BNX2X_PCI_FREE(x, y, size) \
5723 pci_free_consistent(bp->pdev, size, x, y); \
5729 #define BNX2X_FREE(x) \
5740 for_each_queue(bp, i) {
5743 BNX2X_PCI_FREE(bnx2x_fp(bp, i, status_blk),
5744 bnx2x_fp(bp, i, status_blk_mapping),
5745 sizeof(struct host_status_block) +
5746 sizeof(struct eth_tx_db_data));
5748 /* fast path rings: tx_buf tx_desc rx_buf rx_desc rx_comp */
5749 BNX2X_FREE(bnx2x_fp(bp, i, tx_buf_ring));
5750 BNX2X_PCI_FREE(bnx2x_fp(bp, i, tx_desc_ring),
5751 bnx2x_fp(bp, i, tx_desc_mapping),
5752 sizeof(struct eth_tx_bd) * NUM_TX_BD);
5754 BNX2X_FREE(bnx2x_fp(bp, i, rx_buf_ring));
5755 BNX2X_PCI_FREE(bnx2x_fp(bp, i, rx_desc_ring),
5756 bnx2x_fp(bp, i, rx_desc_mapping),
5757 sizeof(struct eth_rx_bd) * NUM_RX_BD);
5759 BNX2X_PCI_FREE(bnx2x_fp(bp, i, rx_comp_ring),
5760 bnx2x_fp(bp, i, rx_comp_mapping),
5761 sizeof(struct eth_fast_path_rx_cqe) *
5765 BNX2X_FREE(bnx2x_fp(bp, i, rx_page_ring));
5766 BNX2X_PCI_FREE(bnx2x_fp(bp, i, rx_sge_ring),
5767 bnx2x_fp(bp, i, rx_sge_mapping),
5768 BCM_PAGE_SIZE * NUM_RX_SGE_PAGES);
5770 /* end of fastpath */
5772 BNX2X_PCI_FREE(bp->def_status_blk, bp->def_status_blk_mapping,
5773 sizeof(struct host_def_status_block));
5775 BNX2X_PCI_FREE(bp->slowpath, bp->slowpath_mapping,
5776 sizeof(struct bnx2x_slowpath));
5779 BNX2X_PCI_FREE(bp->t1, bp->t1_mapping, 64*1024);
5780 BNX2X_PCI_FREE(bp->t2, bp->t2_mapping, 16*1024);
5781 BNX2X_PCI_FREE(bp->timers, bp->timers_mapping, 8*1024);
5782 BNX2X_PCI_FREE(bp->qm, bp->qm_mapping, 128*1024);
5784 BNX2X_PCI_FREE(bp->spq, bp->spq_mapping, BCM_PAGE_SIZE);
5786 #undef BNX2X_PCI_FREE
5790 static int bnx2x_alloc_mem(struct bnx2x *bp)
5793 #define BNX2X_PCI_ALLOC(x, y, size) \
5795 x = pci_alloc_consistent(bp->pdev, size, y); \
5797 goto alloc_mem_err; \
5798 memset(x, 0, size); \
5801 #define BNX2X_ALLOC(x, size) \
5803 x = vmalloc(size); \
5805 goto alloc_mem_err; \
5806 memset(x, 0, size); \
5812 for_each_queue(bp, i) {
5813 bnx2x_fp(bp, i, bp) = bp;
5816 BNX2X_PCI_ALLOC(bnx2x_fp(bp, i, status_blk),
5817 &bnx2x_fp(bp, i, status_blk_mapping),
5818 sizeof(struct host_status_block) +
5819 sizeof(struct eth_tx_db_data));
5821 bnx2x_fp(bp, i, hw_tx_prods) =
5822 (void *)(bnx2x_fp(bp, i, status_blk) + 1);
5824 bnx2x_fp(bp, i, tx_prods_mapping) =
5825 bnx2x_fp(bp, i, status_blk_mapping) +
5826 sizeof(struct host_status_block);
5828 /* fast path rings: tx_buf tx_desc rx_buf rx_desc rx_comp */
5829 BNX2X_ALLOC(bnx2x_fp(bp, i, tx_buf_ring),
5830 sizeof(struct sw_tx_bd) * NUM_TX_BD);
5831 BNX2X_PCI_ALLOC(bnx2x_fp(bp, i, tx_desc_ring),
5832 &bnx2x_fp(bp, i, tx_desc_mapping),
5833 sizeof(struct eth_tx_bd) * NUM_TX_BD);
5835 BNX2X_ALLOC(bnx2x_fp(bp, i, rx_buf_ring),
5836 sizeof(struct sw_rx_bd) * NUM_RX_BD);
5837 BNX2X_PCI_ALLOC(bnx2x_fp(bp, i, rx_desc_ring),
5838 &bnx2x_fp(bp, i, rx_desc_mapping),
5839 sizeof(struct eth_rx_bd) * NUM_RX_BD);
5841 BNX2X_PCI_ALLOC(bnx2x_fp(bp, i, rx_comp_ring),
5842 &bnx2x_fp(bp, i, rx_comp_mapping),
5843 sizeof(struct eth_fast_path_rx_cqe) *
5847 BNX2X_ALLOC(bnx2x_fp(bp, i, rx_page_ring),
5848 sizeof(struct sw_rx_page) * NUM_RX_SGE);
5849 BNX2X_PCI_ALLOC(bnx2x_fp(bp, i, rx_sge_ring),
5850 &bnx2x_fp(bp, i, rx_sge_mapping),
5851 BCM_PAGE_SIZE * NUM_RX_SGE_PAGES);
5853 /* end of fastpath */
5855 BNX2X_PCI_ALLOC(bp->def_status_blk, &bp->def_status_blk_mapping,
5856 sizeof(struct host_def_status_block));
5858 BNX2X_PCI_ALLOC(bp->slowpath, &bp->slowpath_mapping,
5859 sizeof(struct bnx2x_slowpath));
5862 BNX2X_PCI_ALLOC(bp->t1, &bp->t1_mapping, 64*1024);
5865 for (i = 0; i < 64*1024; i += 64) {
5866 *(u64 *)((char *)bp->t1 + i + 56) = 0x0UL;
5867 *(u64 *)((char *)bp->t1 + i + 3) = 0x0UL;
5870 /* allocate searcher T2 table
5871 we allocate 1/4 of alloc num for T2
5872 (which is not entered into the ILT) */
5873 BNX2X_PCI_ALLOC(bp->t2, &bp->t2_mapping, 16*1024);
5876 for (i = 0; i < 16*1024; i += 64)
5877 * (u64 *)((char *)bp->t2 + i + 56) = bp->t2_mapping + i + 64;
5879 /* now fixup the last line in the block to point to the next block */
5880 *(u64 *)((char *)bp->t2 + 1024*16-8) = bp->t2_mapping;
5882 /* Timer block array (MAX_CONN*8) phys uncached for now 1024 conns */
5883 BNX2X_PCI_ALLOC(bp->timers, &bp->timers_mapping, 8*1024);
5885 /* QM queues (128*MAX_CONN) */
5886 BNX2X_PCI_ALLOC(bp->qm, &bp->qm_mapping, 128*1024);
5889 /* Slow path ring */
5890 BNX2X_PCI_ALLOC(bp->spq, &bp->spq_mapping, BCM_PAGE_SIZE);
5898 #undef BNX2X_PCI_ALLOC
5902 static void bnx2x_free_tx_skbs(struct bnx2x *bp)
5906 for_each_queue(bp, i) {
5907 struct bnx2x_fastpath *fp = &bp->fp[i];
5909 u16 bd_cons = fp->tx_bd_cons;
5910 u16 sw_prod = fp->tx_pkt_prod;
5911 u16 sw_cons = fp->tx_pkt_cons;
5913 while (sw_cons != sw_prod) {
5914 bd_cons = bnx2x_free_tx_pkt(bp, fp, TX_BD(sw_cons));
5920 static void bnx2x_free_rx_skbs(struct bnx2x *bp)
5924 for_each_queue(bp, j) {
5925 struct bnx2x_fastpath *fp = &bp->fp[j];
5927 for (i = 0; i < NUM_RX_BD; i++) {
5928 struct sw_rx_bd *rx_buf = &fp->rx_buf_ring[i];
5929 struct sk_buff *skb = rx_buf->skb;
5934 pci_unmap_single(bp->pdev,
5935 pci_unmap_addr(rx_buf, mapping),
5936 bp->rx_buf_use_size,
5937 PCI_DMA_FROMDEVICE);
5942 if (!fp->disable_tpa)
5943 bnx2x_free_tpa_pool(bp, fp, CHIP_IS_E1(bp) ?
5944 ETH_MAX_AGGREGATION_QUEUES_E1 :
5945 ETH_MAX_AGGREGATION_QUEUES_E1H);
5949 static void bnx2x_free_skbs(struct bnx2x *bp)
5951 bnx2x_free_tx_skbs(bp);
5952 bnx2x_free_rx_skbs(bp);
5955 static void bnx2x_free_msix_irqs(struct bnx2x *bp)
5959 free_irq(bp->msix_table[0].vector, bp->dev);
5960 DP(NETIF_MSG_IFDOWN, "released sp irq (%d)\n",
5961 bp->msix_table[0].vector);
5963 for_each_queue(bp, i) {
5964 DP(NETIF_MSG_IFDOWN, "about to release fp #%d->%d irq "
5965 "state %x\n", i, bp->msix_table[i + offset].vector,
5966 bnx2x_fp(bp, i, state));
5968 if (bnx2x_fp(bp, i, state) != BNX2X_FP_STATE_CLOSED)
5969 BNX2X_ERR("IRQ of fp #%d being freed while "
5970 "state != closed\n", i);
5972 free_irq(bp->msix_table[i + offset].vector, &bp->fp[i]);
5976 static void bnx2x_free_irq(struct bnx2x *bp)
5978 if (bp->flags & USING_MSIX_FLAG) {
5979 bnx2x_free_msix_irqs(bp);
5980 pci_disable_msix(bp->pdev);
5981 bp->flags &= ~USING_MSIX_FLAG;
5984 free_irq(bp->pdev->irq, bp->dev);
5987 static int bnx2x_enable_msix(struct bnx2x *bp)
5991 bp->msix_table[0].entry = 0;
5993 DP(NETIF_MSG_IFUP, "msix_table[0].entry = 0 (slowpath)\n");
5995 for_each_queue(bp, i) {
5996 int igu_vec = offset + i + BP_L_ID(bp);
5998 bp->msix_table[i + offset].entry = igu_vec;
5999 DP(NETIF_MSG_IFUP, "msix_table[%d].entry = %d "
6000 "(fastpath #%u)\n", i + offset, igu_vec, i);
6003 rc = pci_enable_msix(bp->pdev, &bp->msix_table[0],
6004 bp->num_queues + offset);
6006 DP(NETIF_MSG_IFUP, "MSI-X is not attainable\n");
6009 bp->flags |= USING_MSIX_FLAG;
6014 static int bnx2x_req_msix_irqs(struct bnx2x *bp)
6016 int i, rc, offset = 1;
6018 rc = request_irq(bp->msix_table[0].vector, bnx2x_msix_sp_int, 0,
6019 bp->dev->name, bp->dev);
6021 BNX2X_ERR("request sp irq failed\n");
6025 for_each_queue(bp, i) {
6026 rc = request_irq(bp->msix_table[i + offset].vector,
6027 bnx2x_msix_fp_int, 0,
6028 bp->dev->name, &bp->fp[i]);
6030 BNX2X_ERR("request fp #%d irq failed rc %d\n",
6032 bnx2x_free_msix_irqs(bp);
6036 bnx2x_fp(bp, i, state) = BNX2X_FP_STATE_IRQ;
6042 static int bnx2x_req_irq(struct bnx2x *bp)
6046 rc = request_irq(bp->pdev->irq, bnx2x_interrupt, IRQF_SHARED,
6047 bp->dev->name, bp->dev);
6049 bnx2x_fp(bp, 0, state) = BNX2X_FP_STATE_IRQ;
6055 * Init service functions
6058 static void bnx2x_set_mac_addr_e1(struct bnx2x *bp, int set)
6060 struct mac_configuration_cmd *config = bnx2x_sp(bp, mac_config);
6061 int port = BP_PORT(bp);
6064 * unicasts 0-31:port0 32-63:port1
6065 * multicast 64-127:port0 128-191:port1
6067 config->hdr.length_6b = 2;
6068 config->hdr.offset = port ? 31 : 0;
6069 config->hdr.client_id = BP_CL_ID(bp);
6070 config->hdr.reserved1 = 0;
6073 config->config_table[0].cam_entry.msb_mac_addr =
6074 swab16(*(u16 *)&bp->dev->dev_addr[0]);
6075 config->config_table[0].cam_entry.middle_mac_addr =
6076 swab16(*(u16 *)&bp->dev->dev_addr[2]);
6077 config->config_table[0].cam_entry.lsb_mac_addr =
6078 swab16(*(u16 *)&bp->dev->dev_addr[4]);
6079 config->config_table[0].cam_entry.flags = cpu_to_le16(port);
6081 config->config_table[0].target_table_entry.flags = 0;
6083 CAM_INVALIDATE(config->config_table[0]);
6084 config->config_table[0].target_table_entry.client_id = 0;
6085 config->config_table[0].target_table_entry.vlan_id = 0;
6087 DP(NETIF_MSG_IFUP, "%s MAC (%04x:%04x:%04x)\n",
6088 (set ? "setting" : "clearing"),
6089 config->config_table[0].cam_entry.msb_mac_addr,
6090 config->config_table[0].cam_entry.middle_mac_addr,
6091 config->config_table[0].cam_entry.lsb_mac_addr);
6094 config->config_table[1].cam_entry.msb_mac_addr = 0xffff;
6095 config->config_table[1].cam_entry.middle_mac_addr = 0xffff;
6096 config->config_table[1].cam_entry.lsb_mac_addr = 0xffff;
6097 config->config_table[1].cam_entry.flags = cpu_to_le16(port);
6099 config->config_table[1].target_table_entry.flags =
6100 TSTORM_CAM_TARGET_TABLE_ENTRY_BROADCAST;
6102 CAM_INVALIDATE(config->config_table[1]);
6103 config->config_table[1].target_table_entry.client_id = 0;
6104 config->config_table[1].target_table_entry.vlan_id = 0;
6106 bnx2x_sp_post(bp, RAMROD_CMD_ID_ETH_SET_MAC, 0,
6107 U64_HI(bnx2x_sp_mapping(bp, mac_config)),
6108 U64_LO(bnx2x_sp_mapping(bp, mac_config)), 0);
6111 static void bnx2x_set_mac_addr_e1h(struct bnx2x *bp, int set)
6113 struct mac_configuration_cmd_e1h *config =
6114 (struct mac_configuration_cmd_e1h *)bnx2x_sp(bp, mac_config);
6116 if (set && (bp->state != BNX2X_STATE_OPEN)) {
6117 DP(NETIF_MSG_IFUP, "state is %x, returning\n", bp->state);
6121 /* CAM allocation for E1H
6122 * unicasts: by func number
6123 * multicast: 20+FUNC*20, 20 each
6125 config->hdr.length_6b = 1;
6126 config->hdr.offset = BP_FUNC(bp);
6127 config->hdr.client_id = BP_CL_ID(bp);
6128 config->hdr.reserved1 = 0;
6131 config->config_table[0].msb_mac_addr =
6132 swab16(*(u16 *)&bp->dev->dev_addr[0]);
6133 config->config_table[0].middle_mac_addr =
6134 swab16(*(u16 *)&bp->dev->dev_addr[2]);
6135 config->config_table[0].lsb_mac_addr =
6136 swab16(*(u16 *)&bp->dev->dev_addr[4]);
6137 config->config_table[0].client_id = BP_L_ID(bp);
6138 config->config_table[0].vlan_id = 0;
6139 config->config_table[0].e1hov_id = cpu_to_le16(bp->e1hov);
6141 config->config_table[0].flags = BP_PORT(bp);
6143 config->config_table[0].flags =
6144 MAC_CONFIGURATION_ENTRY_E1H_ACTION_TYPE;
6146 DP(NETIF_MSG_IFUP, "%s MAC (%04x:%04x:%04x) E1HOV %d CLID %d\n",
6147 (set ? "setting" : "clearing"),
6148 config->config_table[0].msb_mac_addr,
6149 config->config_table[0].middle_mac_addr,
6150 config->config_table[0].lsb_mac_addr, bp->e1hov, BP_L_ID(bp));
6152 bnx2x_sp_post(bp, RAMROD_CMD_ID_ETH_SET_MAC, 0,
6153 U64_HI(bnx2x_sp_mapping(bp, mac_config)),
6154 U64_LO(bnx2x_sp_mapping(bp, mac_config)), 0);
6157 static int bnx2x_wait_ramrod(struct bnx2x *bp, int state, int idx,
6158 int *state_p, int poll)
6160 /* can take a while if any port is running */
6163 DP(NETIF_MSG_IFUP, "%s for state to become %x on IDX [%d]\n",
6164 poll ? "polling" : "waiting", state, idx);
6169 bnx2x_rx_int(bp->fp, 10);
6170 /* if index is different from 0
6171 * the reply for some commands will
6172 * be on the non default queue
6175 bnx2x_rx_int(&bp->fp[idx], 10);
6178 mb(); /* state is changed by bnx2x_sp_event() */
6179 if (*state_p == state)
6186 BNX2X_ERR("timeout %s for state %x on IDX [%d]\n",
6187 poll ? "polling" : "waiting", state, idx);
6188 #ifdef BNX2X_STOP_ON_ERROR
6195 static int bnx2x_setup_leading(struct bnx2x *bp)
6199 /* reset IGU state */
6200 bnx2x_ack_sb(bp, bp->fp[0].sb_id, CSTORM_ID, 0, IGU_INT_ENABLE, 0);
6203 bnx2x_sp_post(bp, RAMROD_CMD_ID_ETH_PORT_SETUP, 0, 0, 0, 0);
6205 /* Wait for completion */
6206 rc = bnx2x_wait_ramrod(bp, BNX2X_STATE_OPEN, 0, &(bp->state), 0);
6211 static int bnx2x_setup_multi(struct bnx2x *bp, int index)
6213 /* reset IGU state */
6214 bnx2x_ack_sb(bp, bp->fp[index].sb_id, CSTORM_ID, 0, IGU_INT_ENABLE, 0);
6217 bp->fp[index].state = BNX2X_FP_STATE_OPENING;
6218 bnx2x_sp_post(bp, RAMROD_CMD_ID_ETH_CLIENT_SETUP, index, 0, index, 0);
6220 /* Wait for completion */
6221 return bnx2x_wait_ramrod(bp, BNX2X_FP_STATE_OPEN, index,
6222 &(bp->fp[index].state), 0);
6225 static int bnx2x_poll(struct napi_struct *napi, int budget);
6226 static void bnx2x_set_rx_mode(struct net_device *dev);
6228 /* must be called with rtnl_lock */
6229 static int bnx2x_nic_load(struct bnx2x *bp, int load_mode)
6234 #ifdef BNX2X_STOP_ON_ERROR
6235 if (unlikely(bp->panic))
6239 bp->state = BNX2X_STATE_OPENING_WAIT4_LOAD;
6241 /* Send LOAD_REQUEST command to MCP
6242 Returns the type of LOAD command:
6243 if it is the first port to be initialized
6244 common blocks should be initialized, otherwise - not
6246 if (!BP_NOMCP(bp)) {
6247 load_code = bnx2x_fw_command(bp, DRV_MSG_CODE_LOAD_REQ);
6249 BNX2X_ERR("MCP response failure, aborting\n");
6252 if (load_code == FW_MSG_CODE_DRV_LOAD_REFUSED)
6253 return -EBUSY; /* other port in diagnostic mode */
6256 int port = BP_PORT(bp);
6258 DP(NETIF_MSG_IFUP, "NO MCP load counts before us %d, %d, %d\n",
6259 load_count[0], load_count[1], load_count[2]);
6261 load_count[1 + port]++;
6262 DP(NETIF_MSG_IFUP, "NO MCP new load counts %d, %d, %d\n",
6263 load_count[0], load_count[1], load_count[2]);
6264 if (load_count[0] == 1)
6265 load_code = FW_MSG_CODE_DRV_LOAD_COMMON;
6266 else if (load_count[1 + port] == 1)
6267 load_code = FW_MSG_CODE_DRV_LOAD_PORT;
6269 load_code = FW_MSG_CODE_DRV_LOAD_FUNCTION;
6272 if ((load_code == FW_MSG_CODE_DRV_LOAD_COMMON) ||
6273 (load_code == FW_MSG_CODE_DRV_LOAD_PORT))
6277 DP(NETIF_MSG_LINK, "pmf %d\n", bp->port.pmf);
6279 /* if we can't use MSI-X we only need one fp,
6280 * so try to enable MSI-X with the requested number of fp's
6281 * and fallback to inta with one fp
6287 if ((use_multi > 1) && (use_multi <= BP_MAX_QUEUES(bp)))
6288 /* user requested number */
6289 bp->num_queues = use_multi;
6292 bp->num_queues = min_t(u32, num_online_cpus(),
6297 if (bnx2x_enable_msix(bp)) {
6298 /* failed to enable MSI-X */
6301 BNX2X_ERR("Multi requested but failed"
6302 " to enable MSI-X\n");
6306 "set number of queues to %d\n", bp->num_queues);
6308 if (bnx2x_alloc_mem(bp))
6311 for_each_queue(bp, i)
6312 bnx2x_fp(bp, i, disable_tpa) =
6313 ((bp->flags & TPA_ENABLE_FLAG) == 0);
6315 if (bp->flags & USING_MSIX_FLAG) {
6316 rc = bnx2x_req_msix_irqs(bp);
6318 pci_disable_msix(bp->pdev);
6323 rc = bnx2x_req_irq(bp);
6325 BNX2X_ERR("IRQ request failed, aborting\n");
6330 for_each_queue(bp, i)
6331 netif_napi_add(bp->dev, &bnx2x_fp(bp, i, napi),
6335 rc = bnx2x_init_hw(bp, load_code);
6337 BNX2X_ERR("HW init failed, aborting\n");
6341 /* Setup NIC internals and enable interrupts */
6342 bnx2x_nic_init(bp, load_code);
6344 /* Send LOAD_DONE command to MCP */
6345 if (!BP_NOMCP(bp)) {
6346 load_code = bnx2x_fw_command(bp, DRV_MSG_CODE_LOAD_DONE);
6348 BNX2X_ERR("MCP response failure, aborting\n");
6350 goto load_int_disable;
6354 bnx2x_stats_init(bp);
6356 bp->state = BNX2X_STATE_OPENING_WAIT4_PORT;
6358 /* Enable Rx interrupt handling before sending the ramrod
6359 as it's completed on Rx FP queue */
6360 for_each_queue(bp, i)
6361 napi_enable(&bnx2x_fp(bp, i, napi));
6363 /* Enable interrupt handling */
6364 atomic_set(&bp->intr_sem, 0);
6366 rc = bnx2x_setup_leading(bp);
6368 BNX2X_ERR("Setup leading failed!\n");
6369 goto load_stop_netif;
6372 if (CHIP_IS_E1H(bp))
6373 if (bp->mf_config & FUNC_MF_CFG_FUNC_DISABLED) {
6374 BNX2X_ERR("!!! mf_cfg function disabled\n");
6375 bp->state = BNX2X_STATE_DISABLED;
6378 if (bp->state == BNX2X_STATE_OPEN)
6379 for_each_nondefault_queue(bp, i) {
6380 rc = bnx2x_setup_multi(bp, i);
6382 goto load_stop_netif;
6386 bnx2x_set_mac_addr_e1(bp, 1);
6388 bnx2x_set_mac_addr_e1h(bp, 1);
6391 bnx2x_initial_phy_init(bp);
6393 /* Start fast path */
6394 switch (load_mode) {
6396 /* Tx queue should be only reenabled */
6397 netif_wake_queue(bp->dev);
6398 bnx2x_set_rx_mode(bp->dev);
6402 netif_start_queue(bp->dev);
6403 bnx2x_set_rx_mode(bp->dev);
6404 if (bp->flags & USING_MSIX_FLAG)
6405 printk(KERN_INFO PFX "%s: using MSI-X\n",
6410 bnx2x_set_rx_mode(bp->dev);
6411 bp->state = BNX2X_STATE_DIAG;
6419 bnx2x__link_status_update(bp);
6421 /* start the timer */
6422 mod_timer(&bp->timer, jiffies + bp->current_interval);
6428 for_each_queue(bp, i)
6429 napi_disable(&bnx2x_fp(bp, i, napi));
6432 bnx2x_int_disable_sync(bp);
6437 /* Free SKBs, SGEs, TPA pool and driver internals */
6438 bnx2x_free_skbs(bp);
6439 for_each_queue(bp, i)
6440 bnx2x_free_rx_sge_range(bp, bp->fp + i,
6441 RX_SGE_CNT*NUM_RX_SGE_PAGES);
6445 /* TBD we really need to reset the chip
6446 if we want to recover from this */
6450 static int bnx2x_stop_multi(struct bnx2x *bp, int index)
6454 /* halt the connection */
6455 bp->fp[index].state = BNX2X_FP_STATE_HALTING;
6456 bnx2x_sp_post(bp, RAMROD_CMD_ID_ETH_HALT, index, 0, 0, 0);
6458 /* Wait for completion */
6459 rc = bnx2x_wait_ramrod(bp, BNX2X_FP_STATE_HALTED, index,
6460 &(bp->fp[index].state), 1);
6461 if (rc) /* timeout */
6464 /* delete cfc entry */
6465 bnx2x_sp_post(bp, RAMROD_CMD_ID_ETH_CFC_DEL, index, 0, 0, 1);
6467 /* Wait for completion */
6468 rc = bnx2x_wait_ramrod(bp, BNX2X_FP_STATE_CLOSED, index,
6469 &(bp->fp[index].state), 1);
6473 static int bnx2x_stop_leading(struct bnx2x *bp)
6475 u16 dsb_sp_prod_idx;
6476 /* if the other port is handling traffic,
6477 this can take a lot of time */
6483 /* Send HALT ramrod */
6484 bp->fp[0].state = BNX2X_FP_STATE_HALTING;
6485 bnx2x_sp_post(bp, RAMROD_CMD_ID_ETH_HALT, 0, 0, BP_CL_ID(bp), 0);
6487 /* Wait for completion */
6488 rc = bnx2x_wait_ramrod(bp, BNX2X_FP_STATE_HALTED, 0,
6489 &(bp->fp[0].state), 1);
6490 if (rc) /* timeout */
6493 dsb_sp_prod_idx = *bp->dsb_sp_prod;
6495 /* Send PORT_DELETE ramrod */
6496 bnx2x_sp_post(bp, RAMROD_CMD_ID_ETH_PORT_DEL, 0, 0, 0, 1);
6498 /* Wait for completion to arrive on default status block
6499 we are going to reset the chip anyway
6500 so there is not much to do if this times out
6502 while (dsb_sp_prod_idx == *bp->dsb_sp_prod) {
6504 DP(NETIF_MSG_IFDOWN, "timeout waiting for port del "
6505 "dsb_sp_prod 0x%x != dsb_sp_prod_idx 0x%x\n",
6506 *bp->dsb_sp_prod, dsb_sp_prod_idx);
6507 #ifdef BNX2X_STOP_ON_ERROR
6517 bp->state = BNX2X_STATE_CLOSING_WAIT4_UNLOAD;
6518 bp->fp[0].state = BNX2X_FP_STATE_CLOSED;
6523 static void bnx2x_reset_func(struct bnx2x *bp)
6525 int port = BP_PORT(bp);
6526 int func = BP_FUNC(bp);
6530 REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, 0);
6531 REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, 0);
6533 REG_WR(bp, HC_REG_CONFIG_0 + port*4, 0x1000);
6536 base = FUNC_ILT_BASE(func);
6537 for (i = base; i < base + ILT_PER_FUNC; i++)
6538 bnx2x_ilt_wr(bp, i, 0);
6541 static void bnx2x_reset_port(struct bnx2x *bp)
6543 int port = BP_PORT(bp);
6546 REG_WR(bp, NIG_REG_MASK_INTERRUPT_PORT0 + port*4, 0);
6548 /* Do not rcv packets to BRB */
6549 REG_WR(bp, NIG_REG_LLH0_BRB1_DRV_MASK + port*4, 0x0);
6550 /* Do not direct rcv packets that are not for MCP to the BRB */
6551 REG_WR(bp, (port ? NIG_REG_LLH1_BRB1_NOT_MCP :
6552 NIG_REG_LLH0_BRB1_NOT_MCP), 0x0);
6555 REG_WR(bp, MISC_REG_AEU_MASK_ATTN_FUNC_0 + port*4, 0);
6558 /* Check for BRB port occupancy */
6559 val = REG_RD(bp, BRB1_REG_PORT_NUM_OCC_BLOCKS_0 + port*4);
6561 DP(NETIF_MSG_IFDOWN,
6562 "BRB1 is not empty %d blooks are occupied\n", val);
6564 /* TODO: Close Doorbell port? */
6567 static void bnx2x_reset_common(struct bnx2x *bp)
6570 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR,
6572 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR, 0x1403);
6575 static void bnx2x_reset_chip(struct bnx2x *bp, u32 reset_code)
6577 DP(BNX2X_MSG_MCP, "function %d reset_code %x\n",
6578 BP_FUNC(bp), reset_code);
6580 switch (reset_code) {
6581 case FW_MSG_CODE_DRV_UNLOAD_COMMON:
6582 bnx2x_reset_port(bp);
6583 bnx2x_reset_func(bp);
6584 bnx2x_reset_common(bp);
6587 case FW_MSG_CODE_DRV_UNLOAD_PORT:
6588 bnx2x_reset_port(bp);
6589 bnx2x_reset_func(bp);
6592 case FW_MSG_CODE_DRV_UNLOAD_FUNCTION:
6593 bnx2x_reset_func(bp);
6597 BNX2X_ERR("Unknown reset_code (0x%x) from MCP\n", reset_code);
6602 /* msut be called with rtnl_lock */
6603 static int bnx2x_nic_unload(struct bnx2x *bp, int unload_mode)
6605 int port = BP_PORT(bp);
6609 bp->state = BNX2X_STATE_CLOSING_WAIT4_HALT;
6611 bp->rx_mode = BNX2X_RX_MODE_NONE;
6612 bnx2x_set_storm_rx_mode(bp);
6614 if (netif_running(bp->dev)) {
6615 netif_tx_disable(bp->dev);
6616 bp->dev->trans_start = jiffies; /* prevent tx timeout */
6619 del_timer_sync(&bp->timer);
6620 SHMEM_WR(bp, func_mb[BP_FUNC(bp)].drv_pulse_mb,
6621 (DRV_PULSE_ALWAYS_ALIVE | bp->fw_drv_pulse_wr_seq));
6622 bnx2x_stats_handle(bp, STATS_EVENT_STOP);
6624 /* Wait until tx fast path tasks complete */
6625 for_each_queue(bp, i) {
6626 struct bnx2x_fastpath *fp = &bp->fp[i];
6630 while (BNX2X_HAS_TX_WORK(fp)) {
6632 if (!netif_running(bp->dev))
6633 bnx2x_tx_int(fp, 1000);
6636 BNX2X_ERR("timeout waiting for queue[%d]\n",
6638 #ifdef BNX2X_STOP_ON_ERROR
6651 /* Give HW time to discard old tx messages */
6654 for_each_queue(bp, i)
6655 napi_disable(&bnx2x_fp(bp, i, napi));
6656 /* Disable interrupts after Tx and Rx are disabled on stack level */
6657 bnx2x_int_disable_sync(bp);
6662 if (unload_mode == UNLOAD_NORMAL)
6663 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS;
6665 else if (bp->flags & NO_WOL_FLAG) {
6666 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_MCP;
6667 if (CHIP_IS_E1H(bp))
6668 REG_WR(bp, MISC_REG_E1HMF_MODE, 0);
6670 } else if (bp->wol) {
6671 u32 emac_base = port ? GRCBASE_EMAC1 : GRCBASE_EMAC0;
6672 u8 *mac_addr = bp->dev->dev_addr;
6674 /* The mac address is written to entries 1-4 to
6675 preserve entry 0 which is used by the PMF */
6676 u8 entry = (BP_E1HVN(bp) + 1)*8;
6678 val = (mac_addr[0] << 8) | mac_addr[1];
6679 EMAC_WR(EMAC_REG_EMAC_MAC_MATCH + entry, val);
6681 val = (mac_addr[2] << 24) | (mac_addr[3] << 16) |
6682 (mac_addr[4] << 8) | mac_addr[5];
6683 EMAC_WR(EMAC_REG_EMAC_MAC_MATCH + entry + 4, val);
6685 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_EN;
6688 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS;
6690 if (CHIP_IS_E1(bp)) {
6691 struct mac_configuration_cmd *config =
6692 bnx2x_sp(bp, mcast_config);
6694 bnx2x_set_mac_addr_e1(bp, 0);
6696 for (i = 0; i < config->hdr.length_6b; i++)
6697 CAM_INVALIDATE(config->config_table[i]);
6699 config->hdr.length_6b = i;
6700 if (CHIP_REV_IS_SLOW(bp))
6701 config->hdr.offset = BNX2X_MAX_EMUL_MULTI*(1 + port);
6703 config->hdr.offset = BNX2X_MAX_MULTICAST*(1 + port);
6704 config->hdr.client_id = BP_CL_ID(bp);
6705 config->hdr.reserved1 = 0;
6707 bnx2x_sp_post(bp, RAMROD_CMD_ID_ETH_SET_MAC, 0,
6708 U64_HI(bnx2x_sp_mapping(bp, mcast_config)),
6709 U64_LO(bnx2x_sp_mapping(bp, mcast_config)), 0);
6712 bnx2x_set_mac_addr_e1h(bp, 0);
6714 for (i = 0; i < MC_HASH_SIZE; i++)
6715 REG_WR(bp, MC_HASH_OFFSET(bp, i), 0);
6718 if (CHIP_IS_E1H(bp))
6719 REG_WR(bp, NIG_REG_LLH0_FUNC_EN + port*8, 0);
6721 /* Close multi and leading connections
6722 Completions for ramrods are collected in a synchronous way */
6723 for_each_nondefault_queue(bp, i)
6724 if (bnx2x_stop_multi(bp, i))
6727 rc = bnx2x_stop_leading(bp);
6729 BNX2X_ERR("Stop leading failed!\n");
6730 #ifdef BNX2X_STOP_ON_ERROR
6739 reset_code = bnx2x_fw_command(bp, reset_code);
6741 DP(NETIF_MSG_IFDOWN, "NO MCP load counts %d, %d, %d\n",
6742 load_count[0], load_count[1], load_count[2]);
6744 load_count[1 + port]--;
6745 DP(NETIF_MSG_IFDOWN, "NO MCP new load counts %d, %d, %d\n",
6746 load_count[0], load_count[1], load_count[2]);
6747 if (load_count[0] == 0)
6748 reset_code = FW_MSG_CODE_DRV_UNLOAD_COMMON;
6749 else if (load_count[1 + port] == 0)
6750 reset_code = FW_MSG_CODE_DRV_UNLOAD_PORT;
6752 reset_code = FW_MSG_CODE_DRV_UNLOAD_FUNCTION;
6755 if ((reset_code == FW_MSG_CODE_DRV_UNLOAD_COMMON) ||
6756 (reset_code == FW_MSG_CODE_DRV_UNLOAD_PORT))
6757 bnx2x__link_reset(bp);
6759 /* Reset the chip */
6760 bnx2x_reset_chip(bp, reset_code);
6762 /* Report UNLOAD_DONE to MCP */
6764 bnx2x_fw_command(bp, DRV_MSG_CODE_UNLOAD_DONE);
6766 /* Free SKBs, SGEs, TPA pool and driver internals */
6767 bnx2x_free_skbs(bp);
6768 for_each_queue(bp, i)
6769 bnx2x_free_rx_sge_range(bp, bp->fp + i,
6770 RX_SGE_CNT*NUM_RX_SGE_PAGES);
6773 bp->state = BNX2X_STATE_CLOSED;
6775 netif_carrier_off(bp->dev);
6780 static void bnx2x_reset_task(struct work_struct *work)
6782 struct bnx2x *bp = container_of(work, struct bnx2x, reset_task);
6784 #ifdef BNX2X_STOP_ON_ERROR
6785 BNX2X_ERR("reset task called but STOP_ON_ERROR defined"
6786 " so reset not done to allow debug dump,\n"
6787 KERN_ERR " you will need to reboot when done\n");
6793 if (!netif_running(bp->dev))
6794 goto reset_task_exit;
6796 bnx2x_nic_unload(bp, UNLOAD_NORMAL);
6797 bnx2x_nic_load(bp, LOAD_NORMAL);
6803 /* end of nic load/unload */
6808 * Init service functions
6811 static void __devinit bnx2x_undi_unload(struct bnx2x *bp)
6815 /* Check if there is any driver already loaded */
6816 val = REG_RD(bp, MISC_REG_UNPREPARED);
6818 /* Check if it is the UNDI driver
6819 * UNDI driver initializes CID offset for normal bell to 0x7
6821 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_UNDI);
6822 val = REG_RD(bp, DORQ_REG_NORM_CID_OFST);
6824 u32 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS;
6826 int func = BP_FUNC(bp);
6830 BNX2X_DEV_INFO("UNDI is active! reset device\n");
6832 /* try unload UNDI on port 0 */
6835 (SHMEM_RD(bp, func_mb[bp->func].drv_mb_header) &
6836 DRV_MSG_SEQ_NUMBER_MASK);
6837 reset_code = bnx2x_fw_command(bp, reset_code);
6839 /* if UNDI is loaded on the other port */
6840 if (reset_code != FW_MSG_CODE_DRV_UNLOAD_COMMON) {
6842 /* send "DONE" for previous unload */
6843 bnx2x_fw_command(bp, DRV_MSG_CODE_UNLOAD_DONE);
6845 /* unload UNDI on port 1 */
6848 (SHMEM_RD(bp, func_mb[bp->func].drv_mb_header) &
6849 DRV_MSG_SEQ_NUMBER_MASK);
6850 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS;
6852 bnx2x_fw_command(bp, reset_code);
6855 REG_WR(bp, (BP_PORT(bp) ? HC_REG_CONFIG_1 :
6856 HC_REG_CONFIG_0), 0x1000);
6858 /* close input traffic and wait for it */
6859 /* Do not rcv packets to BRB */
6861 (BP_PORT(bp) ? NIG_REG_LLH1_BRB1_DRV_MASK :
6862 NIG_REG_LLH0_BRB1_DRV_MASK), 0x0);
6863 /* Do not direct rcv packets that are not for MCP to
6866 (BP_PORT(bp) ? NIG_REG_LLH1_BRB1_NOT_MCP :
6867 NIG_REG_LLH0_BRB1_NOT_MCP), 0x0);
6870 (BP_PORT(bp) ? MISC_REG_AEU_MASK_ATTN_FUNC_1 :
6871 MISC_REG_AEU_MASK_ATTN_FUNC_0), 0);
6874 /* save NIG port swap info */
6875 swap_val = REG_RD(bp, NIG_REG_PORT_SWAP);
6876 swap_en = REG_RD(bp, NIG_REG_STRAP_OVERRIDE);
6879 GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR,
6882 GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
6884 /* take the NIG out of reset and restore swap values */
6886 GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET,
6887 MISC_REGISTERS_RESET_REG_1_RST_NIG);
6888 REG_WR(bp, NIG_REG_PORT_SWAP, swap_val);
6889 REG_WR(bp, NIG_REG_STRAP_OVERRIDE, swap_en);
6891 /* send unload done to the MCP */
6892 bnx2x_fw_command(bp, DRV_MSG_CODE_UNLOAD_DONE);
6894 /* restore our func and fw_seq */
6897 (SHMEM_RD(bp, func_mb[bp->func].drv_mb_header) &
6898 DRV_MSG_SEQ_NUMBER_MASK);
6900 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_UNDI);
6904 static void __devinit bnx2x_get_common_hwinfo(struct bnx2x *bp)
6906 u32 val, val2, val3, val4, id;
6909 /* Get the chip revision id and number. */
6910 /* chip num:16-31, rev:12-15, metal:4-11, bond_id:0-3 */
6911 val = REG_RD(bp, MISC_REG_CHIP_NUM);
6912 id = ((val & 0xffff) << 16);
6913 val = REG_RD(bp, MISC_REG_CHIP_REV);
6914 id |= ((val & 0xf) << 12);
6915 val = REG_RD(bp, MISC_REG_CHIP_METAL);
6916 id |= ((val & 0xff) << 4);
6917 REG_RD(bp, MISC_REG_BOND_ID);
6919 bp->common.chip_id = id;
6920 bp->link_params.chip_id = bp->common.chip_id;
6921 BNX2X_DEV_INFO("chip ID is 0x%x\n", id);
6923 val = REG_RD(bp, MCP_REG_MCPR_NVM_CFG4);
6924 bp->common.flash_size = (NVRAM_1MB_SIZE <<
6925 (val & MCPR_NVM_CFG4_FLASH_SIZE));
6926 BNX2X_DEV_INFO("flash_size 0x%x (%d)\n",
6927 bp->common.flash_size, bp->common.flash_size);
6929 bp->common.shmem_base = REG_RD(bp, MISC_REG_SHARED_MEM_ADDR);
6930 bp->link_params.shmem_base = bp->common.shmem_base;
6931 BNX2X_DEV_INFO("shmem offset is 0x%x\n", bp->common.shmem_base);
6933 if (!bp->common.shmem_base ||
6934 (bp->common.shmem_base < 0xA0000) ||
6935 (bp->common.shmem_base >= 0xC0000)) {
6936 BNX2X_DEV_INFO("MCP not active\n");
6937 bp->flags |= NO_MCP_FLAG;
6941 val = SHMEM_RD(bp, validity_map[BP_PORT(bp)]);
6942 if ((val & (SHR_MEM_VALIDITY_DEV_INFO | SHR_MEM_VALIDITY_MB))
6943 != (SHR_MEM_VALIDITY_DEV_INFO | SHR_MEM_VALIDITY_MB))
6944 BNX2X_ERR("BAD MCP validity signature\n");
6946 bp->common.hw_config = SHMEM_RD(bp, dev_info.shared_hw_config.config);
6947 bp->common.board = SHMEM_RD(bp, dev_info.shared_hw_config.board);
6949 BNX2X_DEV_INFO("hw_config 0x%08x board 0x%08x\n",
6950 bp->common.hw_config, bp->common.board);
6952 bp->link_params.hw_led_mode = ((bp->common.hw_config &
6953 SHARED_HW_CFG_LED_MODE_MASK) >>
6954 SHARED_HW_CFG_LED_MODE_SHIFT);
6956 val = SHMEM_RD(bp, dev_info.bc_rev) >> 8;
6957 bp->common.bc_ver = val;
6958 BNX2X_DEV_INFO("bc_ver %X\n", val);
6959 if (val < BNX2X_BC_VER) {
6960 /* for now only warn
6961 * later we might need to enforce this */
6962 BNX2X_ERR("This driver needs bc_ver %X but found %X,"
6963 " please upgrade BC\n", BNX2X_BC_VER, val);
6966 if (BP_E1HVN(bp) == 0) {
6967 pci_read_config_word(bp->pdev, bp->pm_cap + PCI_PM_PMC, &pmc);
6968 bp->flags |= (pmc & PCI_PM_CAP_PME_D3cold) ? 0 : NO_WOL_FLAG;
6970 /* no WOL capability for E1HVN != 0 */
6971 bp->flags |= NO_WOL_FLAG;
6973 BNX2X_DEV_INFO("%sWoL capable\n",
6974 (bp->flags & NO_WOL_FLAG) ? "Not " : "");
6976 val = SHMEM_RD(bp, dev_info.shared_hw_config.part_num);
6977 val2 = SHMEM_RD(bp, dev_info.shared_hw_config.part_num[4]);
6978 val3 = SHMEM_RD(bp, dev_info.shared_hw_config.part_num[8]);
6979 val4 = SHMEM_RD(bp, dev_info.shared_hw_config.part_num[12]);
6981 printk(KERN_INFO PFX "part number %X-%X-%X-%X\n",
6982 val, val2, val3, val4);
6985 static void __devinit bnx2x_link_settings_supported(struct bnx2x *bp,
6988 int port = BP_PORT(bp);
6991 switch (switch_cfg) {
6993 BNX2X_DEV_INFO("switch_cfg 0x%x (1G)\n", switch_cfg);
6996 SERDES_EXT_PHY_TYPE(bp->link_params.ext_phy_config);
6997 switch (ext_phy_type) {
6998 case PORT_HW_CFG_SERDES_EXT_PHY_TYPE_DIRECT:
6999 BNX2X_DEV_INFO("ext_phy_type 0x%x (Direct)\n",
7002 bp->port.supported |= (SUPPORTED_10baseT_Half |
7003 SUPPORTED_10baseT_Full |
7004 SUPPORTED_100baseT_Half |
7005 SUPPORTED_100baseT_Full |
7006 SUPPORTED_1000baseT_Full |
7007 SUPPORTED_2500baseX_Full |
7012 SUPPORTED_Asym_Pause);
7015 case PORT_HW_CFG_SERDES_EXT_PHY_TYPE_BCM5482:
7016 BNX2X_DEV_INFO("ext_phy_type 0x%x (5482)\n",
7019 bp->port.supported |= (SUPPORTED_10baseT_Half |
7020 SUPPORTED_10baseT_Full |
7021 SUPPORTED_100baseT_Half |
7022 SUPPORTED_100baseT_Full |
7023 SUPPORTED_1000baseT_Full |
7028 SUPPORTED_Asym_Pause);
7032 BNX2X_ERR("NVRAM config error. "
7033 "BAD SerDes ext_phy_config 0x%x\n",
7034 bp->link_params.ext_phy_config);
7038 bp->port.phy_addr = REG_RD(bp, NIG_REG_SERDES0_CTRL_PHY_ADDR +
7040 BNX2X_DEV_INFO("phy_addr 0x%x\n", bp->port.phy_addr);
7043 case SWITCH_CFG_10G:
7044 BNX2X_DEV_INFO("switch_cfg 0x%x (10G)\n", switch_cfg);
7047 XGXS_EXT_PHY_TYPE(bp->link_params.ext_phy_config);
7048 switch (ext_phy_type) {
7049 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT:
7050 BNX2X_DEV_INFO("ext_phy_type 0x%x (Direct)\n",
7053 bp->port.supported |= (SUPPORTED_10baseT_Half |
7054 SUPPORTED_10baseT_Full |
7055 SUPPORTED_100baseT_Half |
7056 SUPPORTED_100baseT_Full |
7057 SUPPORTED_1000baseT_Full |
7058 SUPPORTED_2500baseX_Full |
7059 SUPPORTED_10000baseT_Full |
7064 SUPPORTED_Asym_Pause);
7067 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8705:
7068 BNX2X_DEV_INFO("ext_phy_type 0x%x (8705)\n",
7071 bp->port.supported |= (SUPPORTED_10000baseT_Full |
7074 SUPPORTED_Asym_Pause);
7077 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8706:
7078 BNX2X_DEV_INFO("ext_phy_type 0x%x (8706)\n",
7081 bp->port.supported |= (SUPPORTED_10000baseT_Full |
7082 SUPPORTED_1000baseT_Full |
7085 SUPPORTED_Asym_Pause);
7088 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8072:
7089 BNX2X_DEV_INFO("ext_phy_type 0x%x (8072)\n",
7092 bp->port.supported |= (SUPPORTED_10000baseT_Full |
7093 SUPPORTED_1000baseT_Full |
7097 SUPPORTED_Asym_Pause);
7100 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073:
7101 BNX2X_DEV_INFO("ext_phy_type 0x%x (8073)\n",
7104 bp->port.supported |= (SUPPORTED_10000baseT_Full |
7105 SUPPORTED_2500baseX_Full |
7106 SUPPORTED_1000baseT_Full |
7110 SUPPORTED_Asym_Pause);
7113 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101:
7114 BNX2X_DEV_INFO("ext_phy_type 0x%x (SFX7101)\n",
7117 bp->port.supported |= (SUPPORTED_10000baseT_Full |
7121 SUPPORTED_Asym_Pause);
7124 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE:
7125 BNX2X_ERR("XGXS PHY Failure detected 0x%x\n",
7126 bp->link_params.ext_phy_config);
7130 BNX2X_ERR("NVRAM config error. "
7131 "BAD XGXS ext_phy_config 0x%x\n",
7132 bp->link_params.ext_phy_config);
7136 bp->port.phy_addr = REG_RD(bp, NIG_REG_XGXS0_CTRL_PHY_ADDR +
7138 BNX2X_DEV_INFO("phy_addr 0x%x\n", bp->port.phy_addr);
7143 BNX2X_ERR("BAD switch_cfg link_config 0x%x\n",
7144 bp->port.link_config);
7147 bp->link_params.phy_addr = bp->port.phy_addr;
7149 /* mask what we support according to speed_cap_mask */
7150 if (!(bp->link_params.speed_cap_mask &
7151 PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_HALF))
7152 bp->port.supported &= ~SUPPORTED_10baseT_Half;
7154 if (!(bp->link_params.speed_cap_mask &
7155 PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_FULL))
7156 bp->port.supported &= ~SUPPORTED_10baseT_Full;
7158 if (!(bp->link_params.speed_cap_mask &
7159 PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_HALF))
7160 bp->port.supported &= ~SUPPORTED_100baseT_Half;
7162 if (!(bp->link_params.speed_cap_mask &
7163 PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_FULL))
7164 bp->port.supported &= ~SUPPORTED_100baseT_Full;
7166 if (!(bp->link_params.speed_cap_mask &
7167 PORT_HW_CFG_SPEED_CAPABILITY_D0_1G))
7168 bp->port.supported &= ~(SUPPORTED_1000baseT_Half |
7169 SUPPORTED_1000baseT_Full);
7171 if (!(bp->link_params.speed_cap_mask &
7172 PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G))
7173 bp->port.supported &= ~SUPPORTED_2500baseX_Full;
7175 if (!(bp->link_params.speed_cap_mask &
7176 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G))
7177 bp->port.supported &= ~SUPPORTED_10000baseT_Full;
7179 BNX2X_DEV_INFO("supported 0x%x\n", bp->port.supported);
7182 static void __devinit bnx2x_link_settings_requested(struct bnx2x *bp)
7184 bp->link_params.req_duplex = DUPLEX_FULL;
7186 switch (bp->port.link_config & PORT_FEATURE_LINK_SPEED_MASK) {
7187 case PORT_FEATURE_LINK_SPEED_AUTO:
7188 if (bp->port.supported & SUPPORTED_Autoneg) {
7189 bp->link_params.req_line_speed = SPEED_AUTO_NEG;
7190 bp->port.advertising = bp->port.supported;
7193 XGXS_EXT_PHY_TYPE(bp->link_params.ext_phy_config);
7195 if ((ext_phy_type ==
7196 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8705) ||
7198 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8706)) {
7199 /* force 10G, no AN */
7200 bp->link_params.req_line_speed = SPEED_10000;
7201 bp->port.advertising =
7202 (ADVERTISED_10000baseT_Full |
7206 BNX2X_ERR("NVRAM config error. "
7207 "Invalid link_config 0x%x"
7208 " Autoneg not supported\n",
7209 bp->port.link_config);
7214 case PORT_FEATURE_LINK_SPEED_10M_FULL:
7215 if (bp->port.supported & SUPPORTED_10baseT_Full) {
7216 bp->link_params.req_line_speed = SPEED_10;
7217 bp->port.advertising = (ADVERTISED_10baseT_Full |
7220 BNX2X_ERR("NVRAM config error. "
7221 "Invalid link_config 0x%x"
7222 " speed_cap_mask 0x%x\n",
7223 bp->port.link_config,
7224 bp->link_params.speed_cap_mask);
7229 case PORT_FEATURE_LINK_SPEED_10M_HALF:
7230 if (bp->port.supported & SUPPORTED_10baseT_Half) {
7231 bp->link_params.req_line_speed = SPEED_10;
7232 bp->link_params.req_duplex = DUPLEX_HALF;
7233 bp->port.advertising = (ADVERTISED_10baseT_Half |
7236 BNX2X_ERR("NVRAM config error. "
7237 "Invalid link_config 0x%x"
7238 " speed_cap_mask 0x%x\n",
7239 bp->port.link_config,
7240 bp->link_params.speed_cap_mask);
7245 case PORT_FEATURE_LINK_SPEED_100M_FULL:
7246 if (bp->port.supported & SUPPORTED_100baseT_Full) {
7247 bp->link_params.req_line_speed = SPEED_100;
7248 bp->port.advertising = (ADVERTISED_100baseT_Full |
7251 BNX2X_ERR("NVRAM config error. "
7252 "Invalid link_config 0x%x"
7253 " speed_cap_mask 0x%x\n",
7254 bp->port.link_config,
7255 bp->link_params.speed_cap_mask);
7260 case PORT_FEATURE_LINK_SPEED_100M_HALF:
7261 if (bp->port.supported & SUPPORTED_100baseT_Half) {
7262 bp->link_params.req_line_speed = SPEED_100;
7263 bp->link_params.req_duplex = DUPLEX_HALF;
7264 bp->port.advertising = (ADVERTISED_100baseT_Half |
7267 BNX2X_ERR("NVRAM config error. "
7268 "Invalid link_config 0x%x"
7269 " speed_cap_mask 0x%x\n",
7270 bp->port.link_config,
7271 bp->link_params.speed_cap_mask);
7276 case PORT_FEATURE_LINK_SPEED_1G:
7277 if (bp->port.supported & SUPPORTED_1000baseT_Full) {
7278 bp->link_params.req_line_speed = SPEED_1000;
7279 bp->port.advertising = (ADVERTISED_1000baseT_Full |
7282 BNX2X_ERR("NVRAM config error. "
7283 "Invalid link_config 0x%x"
7284 " speed_cap_mask 0x%x\n",
7285 bp->port.link_config,
7286 bp->link_params.speed_cap_mask);
7291 case PORT_FEATURE_LINK_SPEED_2_5G:
7292 if (bp->port.supported & SUPPORTED_2500baseX_Full) {
7293 bp->link_params.req_line_speed = SPEED_2500;
7294 bp->port.advertising = (ADVERTISED_2500baseX_Full |
7297 BNX2X_ERR("NVRAM config error. "
7298 "Invalid link_config 0x%x"
7299 " speed_cap_mask 0x%x\n",
7300 bp->port.link_config,
7301 bp->link_params.speed_cap_mask);
7306 case PORT_FEATURE_LINK_SPEED_10G_CX4:
7307 case PORT_FEATURE_LINK_SPEED_10G_KX4:
7308 case PORT_FEATURE_LINK_SPEED_10G_KR:
7309 if (bp->port.supported & SUPPORTED_10000baseT_Full) {
7310 bp->link_params.req_line_speed = SPEED_10000;
7311 bp->port.advertising = (ADVERTISED_10000baseT_Full |
7314 BNX2X_ERR("NVRAM config error. "
7315 "Invalid link_config 0x%x"
7316 " speed_cap_mask 0x%x\n",
7317 bp->port.link_config,
7318 bp->link_params.speed_cap_mask);
7324 BNX2X_ERR("NVRAM config error. "
7325 "BAD link speed link_config 0x%x\n",
7326 bp->port.link_config);
7327 bp->link_params.req_line_speed = SPEED_AUTO_NEG;
7328 bp->port.advertising = bp->port.supported;
7332 bp->link_params.req_flow_ctrl = (bp->port.link_config &
7333 PORT_FEATURE_FLOW_CONTROL_MASK);
7334 if ((bp->link_params.req_flow_ctrl == FLOW_CTRL_AUTO) &&
7335 !(bp->port.supported & SUPPORTED_Autoneg))
7336 bp->link_params.req_flow_ctrl = FLOW_CTRL_NONE;
7338 BNX2X_DEV_INFO("req_line_speed %d req_duplex %d req_flow_ctrl 0x%x"
7339 " advertising 0x%x\n",
7340 bp->link_params.req_line_speed,
7341 bp->link_params.req_duplex,
7342 bp->link_params.req_flow_ctrl, bp->port.advertising);
7345 static void __devinit bnx2x_get_port_hwinfo(struct bnx2x *bp)
7347 int port = BP_PORT(bp);
7350 bp->link_params.bp = bp;
7351 bp->link_params.port = port;
7353 bp->link_params.serdes_config =
7354 SHMEM_RD(bp, dev_info.port_hw_config[port].serdes_config);
7355 bp->link_params.lane_config =
7356 SHMEM_RD(bp, dev_info.port_hw_config[port].lane_config);
7357 bp->link_params.ext_phy_config =
7359 dev_info.port_hw_config[port].external_phy_config);
7360 bp->link_params.speed_cap_mask =
7362 dev_info.port_hw_config[port].speed_capability_mask);
7364 bp->port.link_config =
7365 SHMEM_RD(bp, dev_info.port_feature_config[port].link_config);
7367 BNX2X_DEV_INFO("serdes_config 0x%08x lane_config 0x%08x\n"
7368 KERN_INFO " ext_phy_config 0x%08x speed_cap_mask 0x%08x"
7369 " link_config 0x%08x\n",
7370 bp->link_params.serdes_config,
7371 bp->link_params.lane_config,
7372 bp->link_params.ext_phy_config,
7373 bp->link_params.speed_cap_mask, bp->port.link_config);
7375 bp->link_params.switch_cfg = (bp->port.link_config &
7376 PORT_FEATURE_CONNECTED_SWITCH_MASK);
7377 bnx2x_link_settings_supported(bp, bp->link_params.switch_cfg);
7379 bnx2x_link_settings_requested(bp);
7381 val2 = SHMEM_RD(bp, dev_info.port_hw_config[port].mac_upper);
7382 val = SHMEM_RD(bp, dev_info.port_hw_config[port].mac_lower);
7383 bp->dev->dev_addr[0] = (u8)(val2 >> 8 & 0xff);
7384 bp->dev->dev_addr[1] = (u8)(val2 & 0xff);
7385 bp->dev->dev_addr[2] = (u8)(val >> 24 & 0xff);
7386 bp->dev->dev_addr[3] = (u8)(val >> 16 & 0xff);
7387 bp->dev->dev_addr[4] = (u8)(val >> 8 & 0xff);
7388 bp->dev->dev_addr[5] = (u8)(val & 0xff);
7389 memcpy(bp->link_params.mac_addr, bp->dev->dev_addr, ETH_ALEN);
7390 memcpy(bp->dev->perm_addr, bp->dev->dev_addr, ETH_ALEN);
7393 static int __devinit bnx2x_get_hwinfo(struct bnx2x *bp)
7395 int func = BP_FUNC(bp);
7399 bnx2x_get_common_hwinfo(bp);
7403 if (CHIP_IS_E1H(bp)) {
7405 SHMEM_RD(bp, mf_cfg.func_mf_config[func].config);
7408 (SHMEM_RD(bp, mf_cfg.func_mf_config[func].e1hov_tag) &
7409 FUNC_MF_CFG_E1HOV_TAG_MASK);
7410 if (val != FUNC_MF_CFG_E1HOV_TAG_DEFAULT) {
7414 BNX2X_DEV_INFO("MF mode E1HOV for func %d is %d "
7416 func, bp->e1hov, bp->e1hov);
7418 BNX2X_DEV_INFO("Single function mode\n");
7420 BNX2X_ERR("!!! No valid E1HOV for func %d,"
7421 " aborting\n", func);
7427 if (!BP_NOMCP(bp)) {
7428 bnx2x_get_port_hwinfo(bp);
7430 bp->fw_seq = (SHMEM_RD(bp, func_mb[func].drv_mb_header) &
7431 DRV_MSG_SEQ_NUMBER_MASK);
7432 BNX2X_DEV_INFO("fw_seq 0x%08x\n", bp->fw_seq);
7436 val2 = SHMEM_RD(bp, mf_cfg.func_mf_config[func].mac_upper);
7437 val = SHMEM_RD(bp, mf_cfg.func_mf_config[func].mac_lower);
7438 if ((val2 != FUNC_MF_CFG_UPPERMAC_DEFAULT) &&
7439 (val != FUNC_MF_CFG_LOWERMAC_DEFAULT)) {
7440 bp->dev->dev_addr[0] = (u8)(val2 >> 8 & 0xff);
7441 bp->dev->dev_addr[1] = (u8)(val2 & 0xff);
7442 bp->dev->dev_addr[2] = (u8)(val >> 24 & 0xff);
7443 bp->dev->dev_addr[3] = (u8)(val >> 16 & 0xff);
7444 bp->dev->dev_addr[4] = (u8)(val >> 8 & 0xff);
7445 bp->dev->dev_addr[5] = (u8)(val & 0xff);
7446 memcpy(bp->link_params.mac_addr, bp->dev->dev_addr,
7448 memcpy(bp->dev->perm_addr, bp->dev->dev_addr,
7456 /* only supposed to happen on emulation/FPGA */
7457 BNX2X_ERR("warning rendom MAC workaround active\n");
7458 random_ether_addr(bp->dev->dev_addr);
7459 memcpy(bp->dev->perm_addr, bp->dev->dev_addr, ETH_ALEN);
7465 static int __devinit bnx2x_init_bp(struct bnx2x *bp)
7467 int func = BP_FUNC(bp);
7470 /* Disable interrupt handling until HW is initialized */
7471 atomic_set(&bp->intr_sem, 1);
7473 mutex_init(&bp->port.phy_mutex);
7475 INIT_WORK(&bp->sp_task, bnx2x_sp_task);
7476 INIT_WORK(&bp->reset_task, bnx2x_reset_task);
7478 rc = bnx2x_get_hwinfo(bp);
7480 /* need to reset chip if undi was active */
7482 bnx2x_undi_unload(bp);
7484 if (CHIP_REV_IS_FPGA(bp))
7485 printk(KERN_ERR PFX "FPGA detected\n");
7487 if (BP_NOMCP(bp) && (func == 0))
7489 "MCP disabled, must load devices in order!\n");
7493 bp->flags &= ~TPA_ENABLE_FLAG;
7494 bp->dev->features &= ~NETIF_F_LRO;
7496 bp->flags |= TPA_ENABLE_FLAG;
7497 bp->dev->features |= NETIF_F_LRO;
7501 bp->tx_ring_size = MAX_TX_AVAIL;
7502 bp->rx_ring_size = MAX_RX_AVAIL;
7510 bp->timer_interval = (CHIP_REV_IS_SLOW(bp) ? 5*HZ : HZ);
7511 bp->current_interval = (poll ? poll : bp->timer_interval);
7513 init_timer(&bp->timer);
7514 bp->timer.expires = jiffies + bp->current_interval;
7515 bp->timer.data = (unsigned long) bp;
7516 bp->timer.function = bnx2x_timer;
7522 * ethtool service functions
7525 /* All ethtool functions called with rtnl_lock */
7527 static int bnx2x_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
7529 struct bnx2x *bp = netdev_priv(dev);
7531 cmd->supported = bp->port.supported;
7532 cmd->advertising = bp->port.advertising;
7534 if (netif_carrier_ok(dev)) {
7535 cmd->speed = bp->link_vars.line_speed;
7536 cmd->duplex = bp->link_vars.duplex;
7538 cmd->speed = bp->link_params.req_line_speed;
7539 cmd->duplex = bp->link_params.req_duplex;
7544 vn_max_rate = ((bp->mf_config & FUNC_MF_CFG_MAX_BW_MASK) >>
7545 FUNC_MF_CFG_MAX_BW_SHIFT) * 100;
7546 if (vn_max_rate < cmd->speed)
7547 cmd->speed = vn_max_rate;
7550 if (bp->link_params.switch_cfg == SWITCH_CFG_10G) {
7552 XGXS_EXT_PHY_TYPE(bp->link_params.ext_phy_config);
7554 switch (ext_phy_type) {
7555 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT:
7556 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8705:
7557 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8706:
7558 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8072:
7559 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073:
7560 cmd->port = PORT_FIBRE;
7563 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101:
7564 cmd->port = PORT_TP;
7567 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE:
7568 BNX2X_ERR("XGXS PHY Failure detected 0x%x\n",
7569 bp->link_params.ext_phy_config);
7573 DP(NETIF_MSG_LINK, "BAD XGXS ext_phy_config 0x%x\n",
7574 bp->link_params.ext_phy_config);
7578 cmd->port = PORT_TP;
7580 cmd->phy_address = bp->port.phy_addr;
7581 cmd->transceiver = XCVR_INTERNAL;
7583 if (bp->link_params.req_line_speed == SPEED_AUTO_NEG)
7584 cmd->autoneg = AUTONEG_ENABLE;
7586 cmd->autoneg = AUTONEG_DISABLE;
7591 DP(NETIF_MSG_LINK, "ethtool_cmd: cmd %d\n"
7592 DP_LEVEL " supported 0x%x advertising 0x%x speed %d\n"
7593 DP_LEVEL " duplex %d port %d phy_address %d transceiver %d\n"
7594 DP_LEVEL " autoneg %d maxtxpkt %d maxrxpkt %d\n",
7595 cmd->cmd, cmd->supported, cmd->advertising, cmd->speed,
7596 cmd->duplex, cmd->port, cmd->phy_address, cmd->transceiver,
7597 cmd->autoneg, cmd->maxtxpkt, cmd->maxrxpkt);
7602 static int bnx2x_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
7604 struct bnx2x *bp = netdev_priv(dev);
7610 DP(NETIF_MSG_LINK, "ethtool_cmd: cmd %d\n"
7611 DP_LEVEL " supported 0x%x advertising 0x%x speed %d\n"
7612 DP_LEVEL " duplex %d port %d phy_address %d transceiver %d\n"
7613 DP_LEVEL " autoneg %d maxtxpkt %d maxrxpkt %d\n",
7614 cmd->cmd, cmd->supported, cmd->advertising, cmd->speed,
7615 cmd->duplex, cmd->port, cmd->phy_address, cmd->transceiver,
7616 cmd->autoneg, cmd->maxtxpkt, cmd->maxrxpkt);
7618 if (cmd->autoneg == AUTONEG_ENABLE) {
7619 if (!(bp->port.supported & SUPPORTED_Autoneg)) {
7620 DP(NETIF_MSG_LINK, "Autoneg not supported\n");
7624 /* advertise the requested speed and duplex if supported */
7625 cmd->advertising &= bp->port.supported;
7627 bp->link_params.req_line_speed = SPEED_AUTO_NEG;
7628 bp->link_params.req_duplex = DUPLEX_FULL;
7629 bp->port.advertising |= (ADVERTISED_Autoneg |
7632 } else { /* forced speed */
7633 /* advertise the requested speed and duplex if supported */
7634 switch (cmd->speed) {
7636 if (cmd->duplex == DUPLEX_FULL) {
7637 if (!(bp->port.supported &
7638 SUPPORTED_10baseT_Full)) {
7640 "10M full not supported\n");
7644 advertising = (ADVERTISED_10baseT_Full |
7647 if (!(bp->port.supported &
7648 SUPPORTED_10baseT_Half)) {
7650 "10M half not supported\n");
7654 advertising = (ADVERTISED_10baseT_Half |
7660 if (cmd->duplex == DUPLEX_FULL) {
7661 if (!(bp->port.supported &
7662 SUPPORTED_100baseT_Full)) {
7664 "100M full not supported\n");
7668 advertising = (ADVERTISED_100baseT_Full |
7671 if (!(bp->port.supported &
7672 SUPPORTED_100baseT_Half)) {
7674 "100M half not supported\n");
7678 advertising = (ADVERTISED_100baseT_Half |
7684 if (cmd->duplex != DUPLEX_FULL) {
7685 DP(NETIF_MSG_LINK, "1G half not supported\n");
7689 if (!(bp->port.supported & SUPPORTED_1000baseT_Full)) {
7690 DP(NETIF_MSG_LINK, "1G full not supported\n");
7694 advertising = (ADVERTISED_1000baseT_Full |
7699 if (cmd->duplex != DUPLEX_FULL) {
7701 "2.5G half not supported\n");
7705 if (!(bp->port.supported & SUPPORTED_2500baseX_Full)) {
7707 "2.5G full not supported\n");
7711 advertising = (ADVERTISED_2500baseX_Full |
7716 if (cmd->duplex != DUPLEX_FULL) {
7717 DP(NETIF_MSG_LINK, "10G half not supported\n");
7721 if (!(bp->port.supported & SUPPORTED_10000baseT_Full)) {
7722 DP(NETIF_MSG_LINK, "10G full not supported\n");
7726 advertising = (ADVERTISED_10000baseT_Full |
7731 DP(NETIF_MSG_LINK, "Unsupported speed\n");
7735 bp->link_params.req_line_speed = cmd->speed;
7736 bp->link_params.req_duplex = cmd->duplex;
7737 bp->port.advertising = advertising;
7740 DP(NETIF_MSG_LINK, "req_line_speed %d\n"
7741 DP_LEVEL " req_duplex %d advertising 0x%x\n",
7742 bp->link_params.req_line_speed, bp->link_params.req_duplex,
7743 bp->port.advertising);
7745 if (netif_running(dev)) {
7746 bnx2x_stats_handle(bp, STATS_EVENT_STOP);
7753 #define PHY_FW_VER_LEN 10
7755 static void bnx2x_get_drvinfo(struct net_device *dev,
7756 struct ethtool_drvinfo *info)
7758 struct bnx2x *bp = netdev_priv(dev);
7759 char phy_fw_ver[PHY_FW_VER_LEN];
7761 strcpy(info->driver, DRV_MODULE_NAME);
7762 strcpy(info->version, DRV_MODULE_VERSION);
7764 phy_fw_ver[0] = '\0';
7766 bnx2x_acquire_phy_lock(bp);
7767 bnx2x_get_ext_phy_fw_version(&bp->link_params,
7768 (bp->state != BNX2X_STATE_CLOSED),
7769 phy_fw_ver, PHY_FW_VER_LEN);
7770 bnx2x_release_phy_lock(bp);
7773 snprintf(info->fw_version, 32, "%d.%d.%d:%d BC:%x%s%s",
7774 BCM_5710_FW_MAJOR_VERSION, BCM_5710_FW_MINOR_VERSION,
7775 BCM_5710_FW_REVISION_VERSION,
7776 BCM_5710_FW_COMPILE_FLAGS, bp->common.bc_ver,
7777 ((phy_fw_ver[0] != '\0')? " PHY:":""), phy_fw_ver);
7778 strcpy(info->bus_info, pci_name(bp->pdev));
7779 info->n_stats = BNX2X_NUM_STATS;
7780 info->testinfo_len = BNX2X_NUM_TESTS;
7781 info->eedump_len = bp->common.flash_size;
7782 info->regdump_len = 0;
7785 static void bnx2x_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
7787 struct bnx2x *bp = netdev_priv(dev);
7789 if (bp->flags & NO_WOL_FLAG) {
7793 wol->supported = WAKE_MAGIC;
7795 wol->wolopts = WAKE_MAGIC;
7799 memset(&wol->sopass, 0, sizeof(wol->sopass));
7802 static int bnx2x_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
7804 struct bnx2x *bp = netdev_priv(dev);
7806 if (wol->wolopts & ~WAKE_MAGIC)
7809 if (wol->wolopts & WAKE_MAGIC) {
7810 if (bp->flags & NO_WOL_FLAG)
7820 static u32 bnx2x_get_msglevel(struct net_device *dev)
7822 struct bnx2x *bp = netdev_priv(dev);
7824 return bp->msglevel;
7827 static void bnx2x_set_msglevel(struct net_device *dev, u32 level)
7829 struct bnx2x *bp = netdev_priv(dev);
7831 if (capable(CAP_NET_ADMIN))
7832 bp->msglevel = level;
7835 static int bnx2x_nway_reset(struct net_device *dev)
7837 struct bnx2x *bp = netdev_priv(dev);
7842 if (netif_running(dev)) {
7843 bnx2x_stats_handle(bp, STATS_EVENT_STOP);
7850 static int bnx2x_get_eeprom_len(struct net_device *dev)
7852 struct bnx2x *bp = netdev_priv(dev);
7854 return bp->common.flash_size;
7857 static int bnx2x_acquire_nvram_lock(struct bnx2x *bp)
7859 int port = BP_PORT(bp);
7863 /* adjust timeout for emulation/FPGA */
7864 count = NVRAM_TIMEOUT_COUNT;
7865 if (CHIP_REV_IS_SLOW(bp))
7868 /* request access to nvram interface */
7869 REG_WR(bp, MCP_REG_MCPR_NVM_SW_ARB,
7870 (MCPR_NVM_SW_ARB_ARB_REQ_SET1 << port));
7872 for (i = 0; i < count*10; i++) {
7873 val = REG_RD(bp, MCP_REG_MCPR_NVM_SW_ARB);
7874 if (val & (MCPR_NVM_SW_ARB_ARB_ARB1 << port))
7880 if (!(val & (MCPR_NVM_SW_ARB_ARB_ARB1 << port))) {
7881 DP(BNX2X_MSG_NVM, "cannot get access to nvram interface\n");
7888 static int bnx2x_release_nvram_lock(struct bnx2x *bp)
7890 int port = BP_PORT(bp);
7894 /* adjust timeout for emulation/FPGA */
7895 count = NVRAM_TIMEOUT_COUNT;
7896 if (CHIP_REV_IS_SLOW(bp))
7899 /* relinquish nvram interface */
7900 REG_WR(bp, MCP_REG_MCPR_NVM_SW_ARB,
7901 (MCPR_NVM_SW_ARB_ARB_REQ_CLR1 << port));
7903 for (i = 0; i < count*10; i++) {
7904 val = REG_RD(bp, MCP_REG_MCPR_NVM_SW_ARB);
7905 if (!(val & (MCPR_NVM_SW_ARB_ARB_ARB1 << port)))
7911 if (val & (MCPR_NVM_SW_ARB_ARB_ARB1 << port)) {
7912 DP(BNX2X_MSG_NVM, "cannot free access to nvram interface\n");
7919 static void bnx2x_enable_nvram_access(struct bnx2x *bp)
7923 val = REG_RD(bp, MCP_REG_MCPR_NVM_ACCESS_ENABLE);
7925 /* enable both bits, even on read */
7926 REG_WR(bp, MCP_REG_MCPR_NVM_ACCESS_ENABLE,
7927 (val | MCPR_NVM_ACCESS_ENABLE_EN |
7928 MCPR_NVM_ACCESS_ENABLE_WR_EN));
7931 static void bnx2x_disable_nvram_access(struct bnx2x *bp)
7935 val = REG_RD(bp, MCP_REG_MCPR_NVM_ACCESS_ENABLE);
7937 /* disable both bits, even after read */
7938 REG_WR(bp, MCP_REG_MCPR_NVM_ACCESS_ENABLE,
7939 (val & ~(MCPR_NVM_ACCESS_ENABLE_EN |
7940 MCPR_NVM_ACCESS_ENABLE_WR_EN)));
7943 static int bnx2x_nvram_read_dword(struct bnx2x *bp, u32 offset, u32 *ret_val,
7949 /* build the command word */
7950 cmd_flags |= MCPR_NVM_COMMAND_DOIT;
7952 /* need to clear DONE bit separately */
7953 REG_WR(bp, MCP_REG_MCPR_NVM_COMMAND, MCPR_NVM_COMMAND_DONE);
7955 /* address of the NVRAM to read from */
7956 REG_WR(bp, MCP_REG_MCPR_NVM_ADDR,
7957 (offset & MCPR_NVM_ADDR_NVM_ADDR_VALUE));
7959 /* issue a read command */
7960 REG_WR(bp, MCP_REG_MCPR_NVM_COMMAND, cmd_flags);
7962 /* adjust timeout for emulation/FPGA */
7963 count = NVRAM_TIMEOUT_COUNT;
7964 if (CHIP_REV_IS_SLOW(bp))
7967 /* wait for completion */
7970 for (i = 0; i < count; i++) {
7972 val = REG_RD(bp, MCP_REG_MCPR_NVM_COMMAND);
7974 if (val & MCPR_NVM_COMMAND_DONE) {
7975 val = REG_RD(bp, MCP_REG_MCPR_NVM_READ);
7976 /* we read nvram data in cpu order
7977 * but ethtool sees it as an array of bytes
7978 * converting to big-endian will do the work */
7979 val = cpu_to_be32(val);
7989 static int bnx2x_nvram_read(struct bnx2x *bp, u32 offset, u8 *ret_buf,
7996 if ((offset & 0x03) || (buf_size & 0x03) || (buf_size == 0)) {
7998 "Invalid parameter: offset 0x%x buf_size 0x%x\n",
8003 if (offset + buf_size > bp->common.flash_size) {
8004 DP(BNX2X_MSG_NVM, "Invalid parameter: offset (0x%x) +"
8005 " buf_size (0x%x) > flash_size (0x%x)\n",
8006 offset, buf_size, bp->common.flash_size);
8010 /* request access to nvram interface */
8011 rc = bnx2x_acquire_nvram_lock(bp);
8015 /* enable access to nvram interface */
8016 bnx2x_enable_nvram_access(bp);
8018 /* read the first word(s) */
8019 cmd_flags = MCPR_NVM_COMMAND_FIRST;
8020 while ((buf_size > sizeof(u32)) && (rc == 0)) {
8021 rc = bnx2x_nvram_read_dword(bp, offset, &val, cmd_flags);
8022 memcpy(ret_buf, &val, 4);
8024 /* advance to the next dword */
8025 offset += sizeof(u32);
8026 ret_buf += sizeof(u32);
8027 buf_size -= sizeof(u32);
8032 cmd_flags |= MCPR_NVM_COMMAND_LAST;
8033 rc = bnx2x_nvram_read_dword(bp, offset, &val, cmd_flags);
8034 memcpy(ret_buf, &val, 4);
8037 /* disable access to nvram interface */
8038 bnx2x_disable_nvram_access(bp);
8039 bnx2x_release_nvram_lock(bp);
8044 static int bnx2x_get_eeprom(struct net_device *dev,
8045 struct ethtool_eeprom *eeprom, u8 *eebuf)
8047 struct bnx2x *bp = netdev_priv(dev);
8050 DP(BNX2X_MSG_NVM, "ethtool_eeprom: cmd %d\n"
8051 DP_LEVEL " magic 0x%x offset 0x%x (%d) len 0x%x (%d)\n",
8052 eeprom->cmd, eeprom->magic, eeprom->offset, eeprom->offset,
8053 eeprom->len, eeprom->len);
8055 /* parameters already validated in ethtool_get_eeprom */
8057 rc = bnx2x_nvram_read(bp, eeprom->offset, eebuf, eeprom->len);
8062 static int bnx2x_nvram_write_dword(struct bnx2x *bp, u32 offset, u32 val,
8067 /* build the command word */
8068 cmd_flags |= MCPR_NVM_COMMAND_DOIT | MCPR_NVM_COMMAND_WR;
8070 /* need to clear DONE bit separately */
8071 REG_WR(bp, MCP_REG_MCPR_NVM_COMMAND, MCPR_NVM_COMMAND_DONE);
8073 /* write the data */
8074 REG_WR(bp, MCP_REG_MCPR_NVM_WRITE, val);
8076 /* address of the NVRAM to write to */
8077 REG_WR(bp, MCP_REG_MCPR_NVM_ADDR,
8078 (offset & MCPR_NVM_ADDR_NVM_ADDR_VALUE));
8080 /* issue the write command */
8081 REG_WR(bp, MCP_REG_MCPR_NVM_COMMAND, cmd_flags);
8083 /* adjust timeout for emulation/FPGA */
8084 count = NVRAM_TIMEOUT_COUNT;
8085 if (CHIP_REV_IS_SLOW(bp))
8088 /* wait for completion */
8090 for (i = 0; i < count; i++) {
8092 val = REG_RD(bp, MCP_REG_MCPR_NVM_COMMAND);
8093 if (val & MCPR_NVM_COMMAND_DONE) {
8102 #define BYTE_OFFSET(offset) (8 * (offset & 0x03))
8104 static int bnx2x_nvram_write1(struct bnx2x *bp, u32 offset, u8 *data_buf,
8112 if (offset + buf_size > bp->common.flash_size) {
8113 DP(BNX2X_MSG_NVM, "Invalid parameter: offset (0x%x) +"
8114 " buf_size (0x%x) > flash_size (0x%x)\n",
8115 offset, buf_size, bp->common.flash_size);
8119 /* request access to nvram interface */
8120 rc = bnx2x_acquire_nvram_lock(bp);
8124 /* enable access to nvram interface */
8125 bnx2x_enable_nvram_access(bp);
8127 cmd_flags = (MCPR_NVM_COMMAND_FIRST | MCPR_NVM_COMMAND_LAST);
8128 align_offset = (offset & ~0x03);
8129 rc = bnx2x_nvram_read_dword(bp, align_offset, &val, cmd_flags);
8132 val &= ~(0xff << BYTE_OFFSET(offset));
8133 val |= (*data_buf << BYTE_OFFSET(offset));
8135 /* nvram data is returned as an array of bytes
8136 * convert it back to cpu order */
8137 val = be32_to_cpu(val);
8139 rc = bnx2x_nvram_write_dword(bp, align_offset, val,
8143 /* disable access to nvram interface */
8144 bnx2x_disable_nvram_access(bp);
8145 bnx2x_release_nvram_lock(bp);
8150 static int bnx2x_nvram_write(struct bnx2x *bp, u32 offset, u8 *data_buf,
8158 if (buf_size == 1) /* ethtool */
8159 return bnx2x_nvram_write1(bp, offset, data_buf, buf_size);
8161 if ((offset & 0x03) || (buf_size & 0x03) || (buf_size == 0)) {
8163 "Invalid parameter: offset 0x%x buf_size 0x%x\n",
8168 if (offset + buf_size > bp->common.flash_size) {
8169 DP(BNX2X_MSG_NVM, "Invalid parameter: offset (0x%x) +"
8170 " buf_size (0x%x) > flash_size (0x%x)\n",
8171 offset, buf_size, bp->common.flash_size);
8175 /* request access to nvram interface */
8176 rc = bnx2x_acquire_nvram_lock(bp);
8180 /* enable access to nvram interface */
8181 bnx2x_enable_nvram_access(bp);
8184 cmd_flags = MCPR_NVM_COMMAND_FIRST;
8185 while ((written_so_far < buf_size) && (rc == 0)) {
8186 if (written_so_far == (buf_size - sizeof(u32)))
8187 cmd_flags |= MCPR_NVM_COMMAND_LAST;
8188 else if (((offset + 4) % NVRAM_PAGE_SIZE) == 0)
8189 cmd_flags |= MCPR_NVM_COMMAND_LAST;
8190 else if ((offset % NVRAM_PAGE_SIZE) == 0)
8191 cmd_flags |= MCPR_NVM_COMMAND_FIRST;
8193 memcpy(&val, data_buf, 4);
8195 rc = bnx2x_nvram_write_dword(bp, offset, val, cmd_flags);
8197 /* advance to the next dword */
8198 offset += sizeof(u32);
8199 data_buf += sizeof(u32);
8200 written_so_far += sizeof(u32);
8204 /* disable access to nvram interface */
8205 bnx2x_disable_nvram_access(bp);
8206 bnx2x_release_nvram_lock(bp);
8211 static int bnx2x_set_eeprom(struct net_device *dev,
8212 struct ethtool_eeprom *eeprom, u8 *eebuf)
8214 struct bnx2x *bp = netdev_priv(dev);
8217 DP(BNX2X_MSG_NVM, "ethtool_eeprom: cmd %d\n"
8218 DP_LEVEL " magic 0x%x offset 0x%x (%d) len 0x%x (%d)\n",
8219 eeprom->cmd, eeprom->magic, eeprom->offset, eeprom->offset,
8220 eeprom->len, eeprom->len);
8222 /* parameters already validated in ethtool_set_eeprom */
8224 /* If the magic number is PHY (0x00504859) upgrade the PHY FW */
8225 if (eeprom->magic == 0x00504859)
8228 bnx2x_acquire_phy_lock(bp);
8229 rc = bnx2x_flash_download(bp, BP_PORT(bp),
8230 bp->link_params.ext_phy_config,
8231 (bp->state != BNX2X_STATE_CLOSED),
8232 eebuf, eeprom->len);
8233 if ((bp->state == BNX2X_STATE_OPEN) ||
8234 (bp->state == BNX2X_STATE_DISABLED)) {
8235 rc |= bnx2x_link_reset(&bp->link_params,
8237 rc |= bnx2x_phy_init(&bp->link_params,
8240 bnx2x_release_phy_lock(bp);
8242 } else /* Only the PMF can access the PHY */
8245 rc = bnx2x_nvram_write(bp, eeprom->offset, eebuf, eeprom->len);
8250 static int bnx2x_get_coalesce(struct net_device *dev,
8251 struct ethtool_coalesce *coal)
8253 struct bnx2x *bp = netdev_priv(dev);
8255 memset(coal, 0, sizeof(struct ethtool_coalesce));
8257 coal->rx_coalesce_usecs = bp->rx_ticks;
8258 coal->tx_coalesce_usecs = bp->tx_ticks;
8263 static int bnx2x_set_coalesce(struct net_device *dev,
8264 struct ethtool_coalesce *coal)
8266 struct bnx2x *bp = netdev_priv(dev);
8268 bp->rx_ticks = (u16) coal->rx_coalesce_usecs;
8269 if (bp->rx_ticks > 3000)
8270 bp->rx_ticks = 3000;
8272 bp->tx_ticks = (u16) coal->tx_coalesce_usecs;
8273 if (bp->tx_ticks > 0x3000)
8274 bp->tx_ticks = 0x3000;
8276 if (netif_running(dev))
8277 bnx2x_update_coalesce(bp);
8282 static void bnx2x_get_ringparam(struct net_device *dev,
8283 struct ethtool_ringparam *ering)
8285 struct bnx2x *bp = netdev_priv(dev);
8287 ering->rx_max_pending = MAX_RX_AVAIL;
8288 ering->rx_mini_max_pending = 0;
8289 ering->rx_jumbo_max_pending = 0;
8291 ering->rx_pending = bp->rx_ring_size;
8292 ering->rx_mini_pending = 0;
8293 ering->rx_jumbo_pending = 0;
8295 ering->tx_max_pending = MAX_TX_AVAIL;
8296 ering->tx_pending = bp->tx_ring_size;
8299 static int bnx2x_set_ringparam(struct net_device *dev,
8300 struct ethtool_ringparam *ering)
8302 struct bnx2x *bp = netdev_priv(dev);
8305 if ((ering->rx_pending > MAX_RX_AVAIL) ||
8306 (ering->tx_pending > MAX_TX_AVAIL) ||
8307 (ering->tx_pending <= MAX_SKB_FRAGS + 4))
8310 bp->rx_ring_size = ering->rx_pending;
8311 bp->tx_ring_size = ering->tx_pending;
8313 if (netif_running(dev)) {
8314 bnx2x_nic_unload(bp, UNLOAD_NORMAL);
8315 rc = bnx2x_nic_load(bp, LOAD_NORMAL);
8321 static void bnx2x_get_pauseparam(struct net_device *dev,
8322 struct ethtool_pauseparam *epause)
8324 struct bnx2x *bp = netdev_priv(dev);
8326 epause->autoneg = (bp->link_params.req_flow_ctrl == FLOW_CTRL_AUTO) &&
8327 (bp->link_params.req_line_speed == SPEED_AUTO_NEG);
8329 epause->rx_pause = ((bp->link_vars.flow_ctrl & FLOW_CTRL_RX) ==
8331 epause->tx_pause = ((bp->link_vars.flow_ctrl & FLOW_CTRL_TX) ==
8334 DP(NETIF_MSG_LINK, "ethtool_pauseparam: cmd %d\n"
8335 DP_LEVEL " autoneg %d rx_pause %d tx_pause %d\n",
8336 epause->cmd, epause->autoneg, epause->rx_pause, epause->tx_pause);
8339 static int bnx2x_set_pauseparam(struct net_device *dev,
8340 struct ethtool_pauseparam *epause)
8342 struct bnx2x *bp = netdev_priv(dev);
8347 DP(NETIF_MSG_LINK, "ethtool_pauseparam: cmd %d\n"
8348 DP_LEVEL " autoneg %d rx_pause %d tx_pause %d\n",
8349 epause->cmd, epause->autoneg, epause->rx_pause, epause->tx_pause);
8351 bp->link_params.req_flow_ctrl = FLOW_CTRL_AUTO;
8353 if (epause->rx_pause)
8354 bp->link_params.req_flow_ctrl |= FLOW_CTRL_RX;
8356 if (epause->tx_pause)
8357 bp->link_params.req_flow_ctrl |= FLOW_CTRL_TX;
8359 if (bp->link_params.req_flow_ctrl == FLOW_CTRL_AUTO)
8360 bp->link_params.req_flow_ctrl = FLOW_CTRL_NONE;
8362 if (epause->autoneg) {
8363 if (!(bp->port.supported & SUPPORTED_Autoneg)) {
8364 DP(NETIF_MSG_LINK, "Autoneg not supported\n");
8368 if (bp->link_params.req_line_speed == SPEED_AUTO_NEG)
8369 bp->link_params.req_flow_ctrl = FLOW_CTRL_AUTO;
8373 "req_flow_ctrl 0x%x\n", bp->link_params.req_flow_ctrl);
8375 if (netif_running(dev)) {
8376 bnx2x_stats_handle(bp, STATS_EVENT_STOP);
8383 static int bnx2x_set_flags(struct net_device *dev, u32 data)
8385 struct bnx2x *bp = netdev_priv(dev);
8389 /* TPA requires Rx CSUM offloading */
8390 if ((data & ETH_FLAG_LRO) && bp->rx_csum) {
8391 if (!(dev->features & NETIF_F_LRO)) {
8392 dev->features |= NETIF_F_LRO;
8393 bp->flags |= TPA_ENABLE_FLAG;
8397 } else if (dev->features & NETIF_F_LRO) {
8398 dev->features &= ~NETIF_F_LRO;
8399 bp->flags &= ~TPA_ENABLE_FLAG;
8403 if (changed && netif_running(dev)) {
8404 bnx2x_nic_unload(bp, UNLOAD_NORMAL);
8405 rc = bnx2x_nic_load(bp, LOAD_NORMAL);
8411 static u32 bnx2x_get_rx_csum(struct net_device *dev)
8413 struct bnx2x *bp = netdev_priv(dev);
8418 static int bnx2x_set_rx_csum(struct net_device *dev, u32 data)
8420 struct bnx2x *bp = netdev_priv(dev);
8425 /* Disable TPA, when Rx CSUM is disabled. Otherwise all
8426 TPA'ed packets will be discarded due to wrong TCP CSUM */
8428 u32 flags = ethtool_op_get_flags(dev);
8430 rc = bnx2x_set_flags(dev, (flags & ~ETH_FLAG_LRO));
8436 static int bnx2x_set_tso(struct net_device *dev, u32 data)
8439 dev->features |= (NETIF_F_TSO | NETIF_F_TSO_ECN);
8440 dev->features |= NETIF_F_TSO6;
8442 dev->features &= ~(NETIF_F_TSO | NETIF_F_TSO_ECN);
8443 dev->features &= ~NETIF_F_TSO6;
8449 static const struct {
8450 char string[ETH_GSTRING_LEN];
8451 } bnx2x_tests_str_arr[BNX2X_NUM_TESTS] = {
8452 { "register_test (offline)" },
8453 { "memory_test (offline)" },
8454 { "loopback_test (offline)" },
8455 { "nvram_test (online)" },
8456 { "interrupt_test (online)" },
8457 { "link_test (online)" },
8458 { "idle check (online)" },
8459 { "MC errors (online)" }
8462 static int bnx2x_self_test_count(struct net_device *dev)
8464 return BNX2X_NUM_TESTS;
8467 static int bnx2x_test_registers(struct bnx2x *bp)
8469 int idx, i, rc = -ENODEV;
8471 int port = BP_PORT(bp);
8472 static const struct {
8477 /* 0 */ { BRB1_REG_PAUSE_LOW_THRESHOLD_0, 4, 0x000003ff },
8478 { DORQ_REG_DB_ADDR0, 4, 0xffffffff },
8479 { HC_REG_AGG_INT_0, 4, 0x000003ff },
8480 { PBF_REG_MAC_IF0_ENABLE, 4, 0x00000001 },
8481 { PBF_REG_P0_INIT_CRD, 4, 0x000007ff },
8482 { PRS_REG_CID_PORT_0, 4, 0x00ffffff },
8483 { PXP2_REG_PSWRQ_CDU0_L2P, 4, 0x000fffff },
8484 { PXP2_REG_RQ_CDU0_EFIRST_MEM_ADDR, 8, 0x0003ffff },
8485 { PXP2_REG_PSWRQ_TM0_L2P, 4, 0x000fffff },
8486 { PXP2_REG_RQ_USDM0_EFIRST_MEM_ADDR, 8, 0x0003ffff },
8487 /* 10 */ { PXP2_REG_PSWRQ_TSDM0_L2P, 4, 0x000fffff },
8488 { QM_REG_CONNNUM_0, 4, 0x000fffff },
8489 { TM_REG_LIN0_MAX_ACTIVE_CID, 4, 0x0003ffff },
8490 { SRC_REG_KEYRSS0_0, 40, 0xffffffff },
8491 { SRC_REG_KEYRSS0_7, 40, 0xffffffff },
8492 { XCM_REG_WU_DA_SET_TMR_CNT_FLG_CMD00, 4, 0x00000001 },
8493 { XCM_REG_WU_DA_CNT_CMD00, 4, 0x00000003 },
8494 { XCM_REG_GLB_DEL_ACK_MAX_CNT_0, 4, 0x000000ff },
8495 { NIG_REG_EGRESS_MNG0_FIFO, 20, 0xffffffff },
8496 { NIG_REG_LLH0_T_BIT, 4, 0x00000001 },
8497 /* 20 */ { NIG_REG_EMAC0_IN_EN, 4, 0x00000001 },
8498 { NIG_REG_BMAC0_IN_EN, 4, 0x00000001 },
8499 { NIG_REG_XCM0_OUT_EN, 4, 0x00000001 },
8500 { NIG_REG_BRB0_OUT_EN, 4, 0x00000001 },
8501 { NIG_REG_LLH0_XCM_MASK, 4, 0x00000007 },
8502 { NIG_REG_LLH0_ACPI_PAT_6_LEN, 68, 0x000000ff },
8503 { NIG_REG_LLH0_ACPI_PAT_0_CRC, 68, 0xffffffff },
8504 { NIG_REG_LLH0_DEST_MAC_0_0, 160, 0xffffffff },
8505 { NIG_REG_LLH0_DEST_IP_0_1, 160, 0xffffffff },
8506 { NIG_REG_LLH0_IPV4_IPV6_0, 160, 0x00000001 },
8507 /* 30 */ { NIG_REG_LLH0_DEST_UDP_0, 160, 0x0000ffff },
8508 { NIG_REG_LLH0_DEST_TCP_0, 160, 0x0000ffff },
8509 { NIG_REG_LLH0_VLAN_ID_0, 160, 0x00000fff },
8510 { NIG_REG_XGXS_SERDES0_MODE_SEL, 4, 0x00000001 },
8511 { NIG_REG_LED_CONTROL_OVERRIDE_TRAFFIC_P0, 4, 0x00000001 },
8512 { NIG_REG_STATUS_INTERRUPT_PORT0, 4, 0x07ffffff },
8513 { NIG_REG_XGXS0_CTRL_EXTREMOTEMDIOST, 24, 0x00000001 },
8514 { NIG_REG_SERDES0_CTRL_PHY_ADDR, 16, 0x0000001f },
8516 { 0xffffffff, 0, 0x00000000 }
8519 if (!netif_running(bp->dev))
8522 /* Repeat the test twice:
8523 First by writing 0x00000000, second by writing 0xffffffff */
8524 for (idx = 0; idx < 2; idx++) {
8531 wr_val = 0xffffffff;
8535 for (i = 0; reg_tbl[i].offset0 != 0xffffffff; i++) {
8536 u32 offset, mask, save_val, val;
8538 offset = reg_tbl[i].offset0 + port*reg_tbl[i].offset1;
8539 mask = reg_tbl[i].mask;
8541 save_val = REG_RD(bp, offset);
8543 REG_WR(bp, offset, wr_val);
8544 val = REG_RD(bp, offset);
8546 /* Restore the original register's value */
8547 REG_WR(bp, offset, save_val);
8549 /* verify that value is as expected value */
8550 if ((val & mask) != (wr_val & mask))
8561 static int bnx2x_test_memory(struct bnx2x *bp)
8563 int i, j, rc = -ENODEV;
8565 static const struct {
8569 { CCM_REG_XX_DESCR_TABLE, CCM_REG_XX_DESCR_TABLE_SIZE },
8570 { CFC_REG_ACTIVITY_COUNTER, CFC_REG_ACTIVITY_COUNTER_SIZE },
8571 { CFC_REG_LINK_LIST, CFC_REG_LINK_LIST_SIZE },
8572 { DMAE_REG_CMD_MEM, DMAE_REG_CMD_MEM_SIZE },
8573 { TCM_REG_XX_DESCR_TABLE, TCM_REG_XX_DESCR_TABLE_SIZE },
8574 { UCM_REG_XX_DESCR_TABLE, UCM_REG_XX_DESCR_TABLE_SIZE },
8575 { XCM_REG_XX_DESCR_TABLE, XCM_REG_XX_DESCR_TABLE_SIZE },
8579 static const struct {
8585 { "CCM_PRTY_STS", CCM_REG_CCM_PRTY_STS, 0x3ffc0, 0 },
8586 { "CFC_PRTY_STS", CFC_REG_CFC_PRTY_STS, 0x2, 0x2 },
8587 { "DMAE_PRTY_STS", DMAE_REG_DMAE_PRTY_STS, 0, 0 },
8588 { "TCM_PRTY_STS", TCM_REG_TCM_PRTY_STS, 0x3ffc0, 0 },
8589 { "UCM_PRTY_STS", UCM_REG_UCM_PRTY_STS, 0x3ffc0, 0 },
8590 { "XCM_PRTY_STS", XCM_REG_XCM_PRTY_STS, 0x3ffc1, 0 },
8592 { NULL, 0xffffffff, 0, 0 }
8595 if (!netif_running(bp->dev))
8598 /* Go through all the memories */
8599 for (i = 0; mem_tbl[i].offset != 0xffffffff; i++)
8600 for (j = 0; j < mem_tbl[i].size; j++)
8601 REG_RD(bp, mem_tbl[i].offset + j*4);
8603 /* Check the parity status */
8604 for (i = 0; prty_tbl[i].offset != 0xffffffff; i++) {
8605 val = REG_RD(bp, prty_tbl[i].offset);
8606 if ((CHIP_IS_E1(bp) && (val & ~(prty_tbl[i].e1_mask))) ||
8607 (CHIP_IS_E1H(bp) && (val & ~(prty_tbl[i].e1h_mask)))) {
8609 "%s is 0x%x\n", prty_tbl[i].name, val);
8620 static void bnx2x_netif_start(struct bnx2x *bp)
8624 if (atomic_dec_and_test(&bp->intr_sem)) {
8625 if (netif_running(bp->dev)) {
8626 bnx2x_int_enable(bp);
8627 for_each_queue(bp, i)
8628 napi_enable(&bnx2x_fp(bp, i, napi));
8629 if (bp->state == BNX2X_STATE_OPEN)
8630 netif_wake_queue(bp->dev);
8635 static void bnx2x_netif_stop(struct bnx2x *bp)
8639 if (netif_running(bp->dev)) {
8640 netif_tx_disable(bp->dev);
8641 bp->dev->trans_start = jiffies; /* prevent tx timeout */
8642 for_each_queue(bp, i)
8643 napi_disable(&bnx2x_fp(bp, i, napi));
8645 bnx2x_int_disable_sync(bp);
8648 static void bnx2x_wait_for_link(struct bnx2x *bp, u8 link_up)
8653 while (bnx2x_link_test(bp) && cnt--)
8657 static int bnx2x_run_loopback(struct bnx2x *bp, int loopback_mode, u8 link_up)
8659 unsigned int pkt_size, num_pkts, i;
8660 struct sk_buff *skb;
8661 unsigned char *packet;
8662 struct bnx2x_fastpath *fp = &bp->fp[0];
8663 u16 tx_start_idx, tx_idx;
8664 u16 rx_start_idx, rx_idx;
8666 struct sw_tx_bd *tx_buf;
8667 struct eth_tx_bd *tx_bd;
8669 union eth_rx_cqe *cqe;
8671 struct sw_rx_bd *rx_buf;
8675 if (loopback_mode == BNX2X_MAC_LOOPBACK) {
8676 bp->link_params.loopback_mode = LOOPBACK_BMAC;
8677 bnx2x_acquire_phy_lock(bp);
8678 bnx2x_phy_init(&bp->link_params, &bp->link_vars);
8679 bnx2x_release_phy_lock(bp);
8681 } else if (loopback_mode == BNX2X_PHY_LOOPBACK) {
8682 bp->link_params.loopback_mode = LOOPBACK_XGXS_10;
8683 bnx2x_acquire_phy_lock(bp);
8684 bnx2x_phy_init(&bp->link_params, &bp->link_vars);
8685 bnx2x_release_phy_lock(bp);
8686 /* wait until link state is restored */
8687 bnx2x_wait_for_link(bp, link_up);
8693 skb = netdev_alloc_skb(bp->dev, bp->rx_buf_size);
8696 goto test_loopback_exit;
8698 packet = skb_put(skb, pkt_size);
8699 memcpy(packet, bp->dev->dev_addr, ETH_ALEN);
8700 memset(packet + ETH_ALEN, 0, (ETH_HLEN - ETH_ALEN));
8701 for (i = ETH_HLEN; i < pkt_size; i++)
8702 packet[i] = (unsigned char) (i & 0xff);
8705 tx_start_idx = le16_to_cpu(*fp->tx_cons_sb);
8706 rx_start_idx = le16_to_cpu(*fp->rx_cons_sb);
8708 pkt_prod = fp->tx_pkt_prod++;
8709 tx_buf = &fp->tx_buf_ring[TX_BD(pkt_prod)];
8710 tx_buf->first_bd = fp->tx_bd_prod;
8713 tx_bd = &fp->tx_desc_ring[TX_BD(fp->tx_bd_prod)];
8714 mapping = pci_map_single(bp->pdev, skb->data,
8715 skb_headlen(skb), PCI_DMA_TODEVICE);
8716 tx_bd->addr_hi = cpu_to_le32(U64_HI(mapping));
8717 tx_bd->addr_lo = cpu_to_le32(U64_LO(mapping));
8718 tx_bd->nbd = cpu_to_le16(1);
8719 tx_bd->nbytes = cpu_to_le16(skb_headlen(skb));
8720 tx_bd->vlan = cpu_to_le16(pkt_prod);
8721 tx_bd->bd_flags.as_bitfield = (ETH_TX_BD_FLAGS_START_BD |
8722 ETH_TX_BD_FLAGS_END_BD);
8723 tx_bd->general_data = ((UNICAST_ADDRESS <<
8724 ETH_TX_BD_ETH_ADDR_TYPE_SHIFT) | 1);
8726 fp->hw_tx_prods->bds_prod =
8727 cpu_to_le16(le16_to_cpu(fp->hw_tx_prods->bds_prod) + 1);
8728 mb(); /* FW restriction: must not reorder writing nbd and packets */
8729 fp->hw_tx_prods->packets_prod =
8730 cpu_to_le32(le32_to_cpu(fp->hw_tx_prods->packets_prod) + 1);
8731 DOORBELL(bp, FP_IDX(fp), 0);
8737 bp->dev->trans_start = jiffies;
8741 tx_idx = le16_to_cpu(*fp->tx_cons_sb);
8742 if (tx_idx != tx_start_idx + num_pkts)
8743 goto test_loopback_exit;
8745 rx_idx = le16_to_cpu(*fp->rx_cons_sb);
8746 if (rx_idx != rx_start_idx + num_pkts)
8747 goto test_loopback_exit;
8749 cqe = &fp->rx_comp_ring[RCQ_BD(fp->rx_comp_cons)];
8750 cqe_fp_flags = cqe->fast_path_cqe.type_error_flags;
8751 if (CQE_TYPE(cqe_fp_flags) || (cqe_fp_flags & ETH_RX_ERROR_FALGS))
8752 goto test_loopback_rx_exit;
8754 len = le16_to_cpu(cqe->fast_path_cqe.pkt_len);
8755 if (len != pkt_size)
8756 goto test_loopback_rx_exit;
8758 rx_buf = &fp->rx_buf_ring[RX_BD(fp->rx_bd_cons)];
8760 skb_reserve(skb, cqe->fast_path_cqe.placement_offset);
8761 for (i = ETH_HLEN; i < pkt_size; i++)
8762 if (*(skb->data + i) != (unsigned char) (i & 0xff))
8763 goto test_loopback_rx_exit;
8767 test_loopback_rx_exit:
8768 bp->dev->last_rx = jiffies;
8770 fp->rx_bd_cons = NEXT_RX_IDX(fp->rx_bd_cons);
8771 fp->rx_bd_prod = NEXT_RX_IDX(fp->rx_bd_prod);
8772 fp->rx_comp_cons = NEXT_RCQ_IDX(fp->rx_comp_cons);
8773 fp->rx_comp_prod = NEXT_RCQ_IDX(fp->rx_comp_prod);
8775 /* Update producers */
8776 bnx2x_update_rx_prod(bp, fp, fp->rx_bd_prod, fp->rx_comp_prod,
8778 mmiowb(); /* keep prod updates ordered */
8781 bp->link_params.loopback_mode = LOOPBACK_NONE;
8786 static int bnx2x_test_loopback(struct bnx2x *bp, u8 link_up)
8790 if (!netif_running(bp->dev))
8791 return BNX2X_LOOPBACK_FAILED;
8793 bnx2x_netif_stop(bp);
8795 if (bnx2x_run_loopback(bp, BNX2X_MAC_LOOPBACK, link_up)) {
8796 DP(NETIF_MSG_PROBE, "MAC loopback failed\n");
8797 rc |= BNX2X_MAC_LOOPBACK_FAILED;
8800 if (bnx2x_run_loopback(bp, BNX2X_PHY_LOOPBACK, link_up)) {
8801 DP(NETIF_MSG_PROBE, "PHY loopback failed\n");
8802 rc |= BNX2X_PHY_LOOPBACK_FAILED;
8805 bnx2x_netif_start(bp);
8810 #define CRC32_RESIDUAL 0xdebb20e3
8812 static int bnx2x_test_nvram(struct bnx2x *bp)
8814 static const struct {
8818 { 0, 0x14 }, /* bootstrap */
8819 { 0x14, 0xec }, /* dir */
8820 { 0x100, 0x350 }, /* manuf_info */
8821 { 0x450, 0xf0 }, /* feature_info */
8822 { 0x640, 0x64 }, /* upgrade_key_info */
8824 { 0x708, 0x70 }, /* manuf_key_info */
8829 u8 *data = (u8 *)buf;
8833 rc = bnx2x_nvram_read(bp, 0, data, 4);
8835 DP(NETIF_MSG_PROBE, "magic value read (rc -%d)\n", -rc);
8836 goto test_nvram_exit;
8839 magic = be32_to_cpu(buf[0]);
8840 if (magic != 0x669955aa) {
8841 DP(NETIF_MSG_PROBE, "magic value (0x%08x)\n", magic);
8843 goto test_nvram_exit;
8846 for (i = 0; nvram_tbl[i].size; i++) {
8848 rc = bnx2x_nvram_read(bp, nvram_tbl[i].offset, data,
8852 "nvram_tbl[%d] read data (rc -%d)\n", i, -rc);
8853 goto test_nvram_exit;
8856 csum = ether_crc_le(nvram_tbl[i].size, data);
8857 if (csum != CRC32_RESIDUAL) {
8859 "nvram_tbl[%d] csum value (0x%08x)\n", i, csum);
8861 goto test_nvram_exit;
8869 static int bnx2x_test_intr(struct bnx2x *bp)
8871 struct mac_configuration_cmd *config = bnx2x_sp(bp, mac_config);
8874 if (!netif_running(bp->dev))
8877 config->hdr.length_6b = 0;
8878 config->hdr.offset = 0;
8879 config->hdr.client_id = BP_CL_ID(bp);
8880 config->hdr.reserved1 = 0;
8882 rc = bnx2x_sp_post(bp, RAMROD_CMD_ID_ETH_SET_MAC, 0,
8883 U64_HI(bnx2x_sp_mapping(bp, mac_config)),
8884 U64_LO(bnx2x_sp_mapping(bp, mac_config)), 0);
8886 bp->set_mac_pending++;
8887 for (i = 0; i < 10; i++) {
8888 if (!bp->set_mac_pending)
8890 msleep_interruptible(10);
8899 static void bnx2x_self_test(struct net_device *dev,
8900 struct ethtool_test *etest, u64 *buf)
8902 struct bnx2x *bp = netdev_priv(dev);
8904 memset(buf, 0, sizeof(u64) * BNX2X_NUM_TESTS);
8906 if (!netif_running(dev))
8909 /* offline tests are not suppoerted in MF mode */
8911 etest->flags &= ~ETH_TEST_FL_OFFLINE;
8913 if (etest->flags & ETH_TEST_FL_OFFLINE) {
8916 link_up = bp->link_vars.link_up;
8917 bnx2x_nic_unload(bp, UNLOAD_NORMAL);
8918 bnx2x_nic_load(bp, LOAD_DIAG);
8919 /* wait until link state is restored */
8920 bnx2x_wait_for_link(bp, link_up);
8922 if (bnx2x_test_registers(bp) != 0) {
8924 etest->flags |= ETH_TEST_FL_FAILED;
8926 if (bnx2x_test_memory(bp) != 0) {
8928 etest->flags |= ETH_TEST_FL_FAILED;
8930 buf[2] = bnx2x_test_loopback(bp, link_up);
8932 etest->flags |= ETH_TEST_FL_FAILED;
8934 bnx2x_nic_unload(bp, UNLOAD_NORMAL);
8935 bnx2x_nic_load(bp, LOAD_NORMAL);
8936 /* wait until link state is restored */
8937 bnx2x_wait_for_link(bp, link_up);
8939 if (bnx2x_test_nvram(bp) != 0) {
8941 etest->flags |= ETH_TEST_FL_FAILED;
8943 if (bnx2x_test_intr(bp) != 0) {
8945 etest->flags |= ETH_TEST_FL_FAILED;
8948 if (bnx2x_link_test(bp) != 0) {
8950 etest->flags |= ETH_TEST_FL_FAILED;
8952 buf[7] = bnx2x_mc_assert(bp);
8954 etest->flags |= ETH_TEST_FL_FAILED;
8956 #ifdef BNX2X_EXTRA_DEBUG
8957 bnx2x_panic_dump(bp);
8961 static const struct {
8965 #define STATS_FLAGS_PORT 1
8966 #define STATS_FLAGS_FUNC 2
8967 u8 string[ETH_GSTRING_LEN];
8968 } bnx2x_stats_arr[BNX2X_NUM_STATS] = {
8969 /* 1 */ { STATS_OFFSET32(valid_bytes_received_hi),
8970 8, STATS_FLAGS_FUNC, "rx_bytes" },
8971 { STATS_OFFSET32(error_bytes_received_hi),
8972 8, STATS_FLAGS_FUNC, "rx_error_bytes" },
8973 { STATS_OFFSET32(total_bytes_transmitted_hi),
8974 8, STATS_FLAGS_FUNC, "tx_bytes" },
8975 { STATS_OFFSET32(tx_stat_ifhcoutbadoctets_hi),
8976 8, STATS_FLAGS_PORT, "tx_error_bytes" },
8977 { STATS_OFFSET32(total_unicast_packets_received_hi),
8978 8, STATS_FLAGS_FUNC, "rx_ucast_packets" },
8979 { STATS_OFFSET32(total_multicast_packets_received_hi),
8980 8, STATS_FLAGS_FUNC, "rx_mcast_packets" },
8981 { STATS_OFFSET32(total_broadcast_packets_received_hi),
8982 8, STATS_FLAGS_FUNC, "rx_bcast_packets" },
8983 { STATS_OFFSET32(total_unicast_packets_transmitted_hi),
8984 8, STATS_FLAGS_FUNC, "tx_packets" },
8985 { STATS_OFFSET32(tx_stat_dot3statsinternalmactransmiterrors_hi),
8986 8, STATS_FLAGS_PORT, "tx_mac_errors" },
8987 /* 10 */{ STATS_OFFSET32(rx_stat_dot3statscarriersenseerrors_hi),
8988 8, STATS_FLAGS_PORT, "tx_carrier_errors" },
8989 { STATS_OFFSET32(rx_stat_dot3statsfcserrors_hi),
8990 8, STATS_FLAGS_PORT, "rx_crc_errors" },
8991 { STATS_OFFSET32(rx_stat_dot3statsalignmenterrors_hi),
8992 8, STATS_FLAGS_PORT, "rx_align_errors" },
8993 { STATS_OFFSET32(tx_stat_dot3statssinglecollisionframes_hi),
8994 8, STATS_FLAGS_PORT, "tx_single_collisions" },
8995 { STATS_OFFSET32(tx_stat_dot3statsmultiplecollisionframes_hi),
8996 8, STATS_FLAGS_PORT, "tx_multi_collisions" },
8997 { STATS_OFFSET32(tx_stat_dot3statsdeferredtransmissions_hi),
8998 8, STATS_FLAGS_PORT, "tx_deferred" },
8999 { STATS_OFFSET32(tx_stat_dot3statsexcessivecollisions_hi),
9000 8, STATS_FLAGS_PORT, "tx_excess_collisions" },
9001 { STATS_OFFSET32(tx_stat_dot3statslatecollisions_hi),
9002 8, STATS_FLAGS_PORT, "tx_late_collisions" },
9003 { STATS_OFFSET32(tx_stat_etherstatscollisions_hi),
9004 8, STATS_FLAGS_PORT, "tx_total_collisions" },
9005 { STATS_OFFSET32(rx_stat_etherstatsfragments_hi),
9006 8, STATS_FLAGS_PORT, "rx_fragments" },
9007 /* 20 */{ STATS_OFFSET32(rx_stat_etherstatsjabbers_hi),
9008 8, STATS_FLAGS_PORT, "rx_jabbers" },
9009 { STATS_OFFSET32(rx_stat_etherstatsundersizepkts_hi),
9010 8, STATS_FLAGS_PORT, "rx_undersize_packets" },
9011 { STATS_OFFSET32(jabber_packets_received),
9012 4, STATS_FLAGS_FUNC, "rx_oversize_packets" },
9013 { STATS_OFFSET32(tx_stat_etherstatspkts64octets_hi),
9014 8, STATS_FLAGS_PORT, "tx_64_byte_packets" },
9015 { STATS_OFFSET32(tx_stat_etherstatspkts65octetsto127octets_hi),
9016 8, STATS_FLAGS_PORT, "tx_65_to_127_byte_packets" },
9017 { STATS_OFFSET32(tx_stat_etherstatspkts128octetsto255octets_hi),
9018 8, STATS_FLAGS_PORT, "tx_128_to_255_byte_packets" },
9019 { STATS_OFFSET32(tx_stat_etherstatspkts256octetsto511octets_hi),
9020 8, STATS_FLAGS_PORT, "tx_256_to_511_byte_packets" },
9021 { STATS_OFFSET32(tx_stat_etherstatspkts512octetsto1023octets_hi),
9022 8, STATS_FLAGS_PORT, "tx_512_to_1023_byte_packets" },
9023 { STATS_OFFSET32(etherstatspkts1024octetsto1522octets_hi),
9024 8, STATS_FLAGS_PORT, "tx_1024_to_1522_byte_packets" },
9025 { STATS_OFFSET32(etherstatspktsover1522octets_hi),
9026 8, STATS_FLAGS_PORT, "tx_1523_to_9022_byte_packets" },
9027 /* 30 */{ STATS_OFFSET32(rx_stat_xonpauseframesreceived_hi),
9028 8, STATS_FLAGS_PORT, "rx_xon_frames" },
9029 { STATS_OFFSET32(rx_stat_xoffpauseframesreceived_hi),
9030 8, STATS_FLAGS_PORT, "rx_xoff_frames" },
9031 { STATS_OFFSET32(tx_stat_outxonsent_hi),
9032 8, STATS_FLAGS_PORT, "tx_xon_frames" },
9033 { STATS_OFFSET32(tx_stat_outxoffsent_hi),
9034 8, STATS_FLAGS_PORT, "tx_xoff_frames" },
9035 { STATS_OFFSET32(rx_stat_maccontrolframesreceived_hi),
9036 8, STATS_FLAGS_PORT, "rx_mac_ctrl_frames" },
9037 { STATS_OFFSET32(mac_filter_discard),
9038 4, STATS_FLAGS_PORT, "rx_filtered_packets" },
9039 { STATS_OFFSET32(no_buff_discard),
9040 4, STATS_FLAGS_FUNC, "rx_discards" },
9041 { STATS_OFFSET32(xxoverflow_discard),
9042 4, STATS_FLAGS_PORT, "rx_fw_discards" },
9043 { STATS_OFFSET32(brb_drop_hi),
9044 8, STATS_FLAGS_PORT, "brb_discard" },
9045 { STATS_OFFSET32(brb_truncate_hi),
9046 8, STATS_FLAGS_PORT, "brb_truncate" },
9047 /* 40 */{ STATS_OFFSET32(rx_err_discard_pkt),
9048 4, STATS_FLAGS_FUNC, "rx_phy_ip_err_discards"},
9049 { STATS_OFFSET32(rx_skb_alloc_failed),
9050 4, STATS_FLAGS_FUNC, "rx_skb_alloc_discard" },
9051 /* 42 */{ STATS_OFFSET32(hw_csum_err),
9052 4, STATS_FLAGS_FUNC, "rx_csum_offload_errors" }
9055 #define IS_NOT_E1HMF_STAT(bp, i) \
9056 (IS_E1HMF(bp) && (bnx2x_stats_arr[i].flags & STATS_FLAGS_PORT))
9058 static void bnx2x_get_strings(struct net_device *dev, u32 stringset, u8 *buf)
9060 struct bnx2x *bp = netdev_priv(dev);
9063 switch (stringset) {
9065 for (i = 0, j = 0; i < BNX2X_NUM_STATS; i++) {
9066 if (IS_NOT_E1HMF_STAT(bp, i))
9068 strcpy(buf + j*ETH_GSTRING_LEN,
9069 bnx2x_stats_arr[i].string);
9075 memcpy(buf, bnx2x_tests_str_arr, sizeof(bnx2x_tests_str_arr));
9080 static int bnx2x_get_stats_count(struct net_device *dev)
9082 struct bnx2x *bp = netdev_priv(dev);
9083 int i, num_stats = 0;
9085 for (i = 0; i < BNX2X_NUM_STATS; i++) {
9086 if (IS_NOT_E1HMF_STAT(bp, i))
9093 static void bnx2x_get_ethtool_stats(struct net_device *dev,
9094 struct ethtool_stats *stats, u64 *buf)
9096 struct bnx2x *bp = netdev_priv(dev);
9097 u32 *hw_stats = (u32 *)&bp->eth_stats;
9100 for (i = 0, j = 0; i < BNX2X_NUM_STATS; i++) {
9101 if (IS_NOT_E1HMF_STAT(bp, i))
9104 if (bnx2x_stats_arr[i].size == 0) {
9105 /* skip this counter */
9110 if (bnx2x_stats_arr[i].size == 4) {
9111 /* 4-byte counter */
9112 buf[j] = (u64) *(hw_stats + bnx2x_stats_arr[i].offset);
9116 /* 8-byte counter */
9117 buf[j] = HILO_U64(*(hw_stats + bnx2x_stats_arr[i].offset),
9118 *(hw_stats + bnx2x_stats_arr[i].offset + 1));
9123 static int bnx2x_phys_id(struct net_device *dev, u32 data)
9125 struct bnx2x *bp = netdev_priv(dev);
9126 int port = BP_PORT(bp);
9129 if (!netif_running(dev))
9138 for (i = 0; i < (data * 2); i++) {
9140 bnx2x_set_led(bp, port, LED_MODE_OPER, SPEED_1000,
9141 bp->link_params.hw_led_mode,
9142 bp->link_params.chip_id);
9144 bnx2x_set_led(bp, port, LED_MODE_OFF, 0,
9145 bp->link_params.hw_led_mode,
9146 bp->link_params.chip_id);
9148 msleep_interruptible(500);
9149 if (signal_pending(current))
9153 if (bp->link_vars.link_up)
9154 bnx2x_set_led(bp, port, LED_MODE_OPER,
9155 bp->link_vars.line_speed,
9156 bp->link_params.hw_led_mode,
9157 bp->link_params.chip_id);
9162 static struct ethtool_ops bnx2x_ethtool_ops = {
9163 .get_settings = bnx2x_get_settings,
9164 .set_settings = bnx2x_set_settings,
9165 .get_drvinfo = bnx2x_get_drvinfo,
9166 .get_wol = bnx2x_get_wol,
9167 .set_wol = bnx2x_set_wol,
9168 .get_msglevel = bnx2x_get_msglevel,
9169 .set_msglevel = bnx2x_set_msglevel,
9170 .nway_reset = bnx2x_nway_reset,
9171 .get_link = ethtool_op_get_link,
9172 .get_eeprom_len = bnx2x_get_eeprom_len,
9173 .get_eeprom = bnx2x_get_eeprom,
9174 .set_eeprom = bnx2x_set_eeprom,
9175 .get_coalesce = bnx2x_get_coalesce,
9176 .set_coalesce = bnx2x_set_coalesce,
9177 .get_ringparam = bnx2x_get_ringparam,
9178 .set_ringparam = bnx2x_set_ringparam,
9179 .get_pauseparam = bnx2x_get_pauseparam,
9180 .set_pauseparam = bnx2x_set_pauseparam,
9181 .get_rx_csum = bnx2x_get_rx_csum,
9182 .set_rx_csum = bnx2x_set_rx_csum,
9183 .get_tx_csum = ethtool_op_get_tx_csum,
9184 .set_tx_csum = ethtool_op_set_tx_hw_csum,
9185 .set_flags = bnx2x_set_flags,
9186 .get_flags = ethtool_op_get_flags,
9187 .get_sg = ethtool_op_get_sg,
9188 .set_sg = ethtool_op_set_sg,
9189 .get_tso = ethtool_op_get_tso,
9190 .set_tso = bnx2x_set_tso,
9191 .self_test_count = bnx2x_self_test_count,
9192 .self_test = bnx2x_self_test,
9193 .get_strings = bnx2x_get_strings,
9194 .phys_id = bnx2x_phys_id,
9195 .get_stats_count = bnx2x_get_stats_count,
9196 .get_ethtool_stats = bnx2x_get_ethtool_stats,
9199 /* end of ethtool_ops */
9201 /****************************************************************************
9202 * General service functions
9203 ****************************************************************************/
9205 static int bnx2x_set_power_state(struct bnx2x *bp, pci_power_t state)
9209 pci_read_config_word(bp->pdev, bp->pm_cap + PCI_PM_CTRL, &pmcsr);
9213 pci_write_config_word(bp->pdev, bp->pm_cap + PCI_PM_CTRL,
9214 ((pmcsr & ~PCI_PM_CTRL_STATE_MASK) |
9215 PCI_PM_CTRL_PME_STATUS));
9217 if (pmcsr & PCI_PM_CTRL_STATE_MASK)
9218 /* delay required during transition out of D3hot */
9223 pmcsr &= ~PCI_PM_CTRL_STATE_MASK;
9227 pmcsr |= PCI_PM_CTRL_PME_ENABLE;
9229 pci_write_config_word(bp->pdev, bp->pm_cap + PCI_PM_CTRL,
9232 /* No more memory access after this point until
9233 * device is brought back to D0.
9244 * net_device service functions
9247 static int bnx2x_poll(struct napi_struct *napi, int budget)
9249 struct bnx2x_fastpath *fp = container_of(napi, struct bnx2x_fastpath,
9251 struct bnx2x *bp = fp->bp;
9254 #ifdef BNX2X_STOP_ON_ERROR
9255 if (unlikely(bp->panic))
9259 prefetch(fp->tx_buf_ring[TX_BD(fp->tx_pkt_cons)].skb);
9260 prefetch(fp->rx_buf_ring[RX_BD(fp->rx_bd_cons)].skb);
9261 prefetch((char *)(fp->rx_buf_ring[RX_BD(fp->rx_bd_cons)].skb) + 256);
9263 bnx2x_update_fpsb_idx(fp);
9265 if (BNX2X_HAS_TX_WORK(fp))
9266 bnx2x_tx_int(fp, budget);
9268 if (BNX2X_HAS_RX_WORK(fp))
9269 work_done = bnx2x_rx_int(fp, budget);
9271 rmb(); /* BNX2X_HAS_WORK() reads the status block */
9273 /* must not complete if we consumed full budget */
9274 if ((work_done < budget) && !BNX2X_HAS_WORK(fp)) {
9276 #ifdef BNX2X_STOP_ON_ERROR
9279 netif_rx_complete(bp->dev, napi);
9281 bnx2x_ack_sb(bp, FP_SB_ID(fp), USTORM_ID,
9282 le16_to_cpu(fp->fp_u_idx), IGU_INT_NOP, 1);
9283 bnx2x_ack_sb(bp, FP_SB_ID(fp), CSTORM_ID,
9284 le16_to_cpu(fp->fp_c_idx), IGU_INT_ENABLE, 1);
9290 /* we split the first BD into headers and data BDs
9291 * to ease the pain of our fellow micocode engineers
9292 * we use one mapping for both BDs
9293 * So far this has only been observed to happen
9294 * in Other Operating Systems(TM)
9296 static noinline u16 bnx2x_tx_split(struct bnx2x *bp,
9297 struct bnx2x_fastpath *fp,
9298 struct eth_tx_bd **tx_bd, u16 hlen,
9299 u16 bd_prod, int nbd)
9301 struct eth_tx_bd *h_tx_bd = *tx_bd;
9302 struct eth_tx_bd *d_tx_bd;
9304 int old_len = le16_to_cpu(h_tx_bd->nbytes);
9306 /* first fix first BD */
9307 h_tx_bd->nbd = cpu_to_le16(nbd);
9308 h_tx_bd->nbytes = cpu_to_le16(hlen);
9310 DP(NETIF_MSG_TX_QUEUED, "TSO split header size is %d "
9311 "(%x:%x) nbd %d\n", h_tx_bd->nbytes, h_tx_bd->addr_hi,
9312 h_tx_bd->addr_lo, h_tx_bd->nbd);
9314 /* now get a new data BD
9315 * (after the pbd) and fill it */
9316 bd_prod = TX_BD(NEXT_TX_IDX(bd_prod));
9317 d_tx_bd = &fp->tx_desc_ring[bd_prod];
9319 mapping = HILO_U64(le32_to_cpu(h_tx_bd->addr_hi),
9320 le32_to_cpu(h_tx_bd->addr_lo)) + hlen;
9322 d_tx_bd->addr_hi = cpu_to_le32(U64_HI(mapping));
9323 d_tx_bd->addr_lo = cpu_to_le32(U64_LO(mapping));
9324 d_tx_bd->nbytes = cpu_to_le16(old_len - hlen);
9326 /* this marks the BD as one that has no individual mapping
9327 * the FW ignores this flag in a BD not marked start
9329 d_tx_bd->bd_flags.as_bitfield = ETH_TX_BD_FLAGS_SW_LSO;
9330 DP(NETIF_MSG_TX_QUEUED,
9331 "TSO split data size is %d (%x:%x)\n",
9332 d_tx_bd->nbytes, d_tx_bd->addr_hi, d_tx_bd->addr_lo);
9334 /* update tx_bd for marking the last BD flag */
9340 static inline u16 bnx2x_csum_fix(unsigned char *t_header, u16 csum, s8 fix)
9343 csum = (u16) ~csum_fold(csum_sub(csum,
9344 csum_partial(t_header - fix, fix, 0)));
9347 csum = (u16) ~csum_fold(csum_add(csum,
9348 csum_partial(t_header, -fix, 0)));
9350 return swab16(csum);
9353 static inline u32 bnx2x_xmit_type(struct bnx2x *bp, struct sk_buff *skb)
9357 if (skb->ip_summed != CHECKSUM_PARTIAL)
9361 if (skb->protocol == ntohs(ETH_P_IPV6)) {
9363 if (ipv6_hdr(skb)->nexthdr == IPPROTO_TCP)
9364 rc |= XMIT_CSUM_TCP;
9368 if (ip_hdr(skb)->protocol == IPPROTO_TCP)
9369 rc |= XMIT_CSUM_TCP;
9373 if (skb_shinfo(skb)->gso_type & SKB_GSO_TCPV4)
9376 else if (skb_shinfo(skb)->gso_type & SKB_GSO_TCPV6)
9382 /* check if packet requires linearization (packet is too fragmented) */
9383 static int bnx2x_pkt_req_lin(struct bnx2x *bp, struct sk_buff *skb,
9388 int first_bd_sz = 0;
9390 /* 3 = 1 (for linear data BD) + 2 (for PBD and last BD) */
9391 if (skb_shinfo(skb)->nr_frags >= (MAX_FETCH_BD - 3)) {
9393 if (xmit_type & XMIT_GSO) {
9394 unsigned short lso_mss = skb_shinfo(skb)->gso_size;
9395 /* Check if LSO packet needs to be copied:
9396 3 = 1 (for headers BD) + 2 (for PBD and last BD) */
9397 int wnd_size = MAX_FETCH_BD - 3;
9398 /* Number of widnows to check */
9399 int num_wnds = skb_shinfo(skb)->nr_frags - wnd_size;
9404 /* Headers length */
9405 hlen = (int)(skb_transport_header(skb) - skb->data) +
9408 /* Amount of data (w/o headers) on linear part of SKB*/
9409 first_bd_sz = skb_headlen(skb) - hlen;
9411 wnd_sum = first_bd_sz;
9413 /* Calculate the first sum - it's special */
9414 for (frag_idx = 0; frag_idx < wnd_size - 1; frag_idx++)
9416 skb_shinfo(skb)->frags[frag_idx].size;
9418 /* If there was data on linear skb data - check it */
9419 if (first_bd_sz > 0) {
9420 if (unlikely(wnd_sum < lso_mss)) {
9425 wnd_sum -= first_bd_sz;
9428 /* Others are easier: run through the frag list and
9429 check all windows */
9430 for (wnd_idx = 0; wnd_idx <= num_wnds; wnd_idx++) {
9432 skb_shinfo(skb)->frags[wnd_idx + wnd_size - 1].size;
9434 if (unlikely(wnd_sum < lso_mss)) {
9439 skb_shinfo(skb)->frags[wnd_idx].size;
9443 /* in non-LSO too fragmented packet should always
9450 if (unlikely(to_copy))
9451 DP(NETIF_MSG_TX_QUEUED,
9452 "Linearization IS REQUIRED for %s packet. "
9453 "num_frags %d hlen %d first_bd_sz %d\n",
9454 (xmit_type & XMIT_GSO) ? "LSO" : "non-LSO",
9455 skb_shinfo(skb)->nr_frags, hlen, first_bd_sz);
9460 /* called with netif_tx_lock
9461 * bnx2x_tx_int() runs without netif_tx_lock unless it needs to call
9462 * netif_wake_queue()
9464 static int bnx2x_start_xmit(struct sk_buff *skb, struct net_device *dev)
9466 struct bnx2x *bp = netdev_priv(dev);
9467 struct bnx2x_fastpath *fp;
9468 struct sw_tx_bd *tx_buf;
9469 struct eth_tx_bd *tx_bd;
9470 struct eth_tx_parse_bd *pbd = NULL;
9471 u16 pkt_prod, bd_prod;
9474 u32 xmit_type = bnx2x_xmit_type(bp, skb);
9475 int vlan_off = (bp->e1hov ? 4 : 0);
9479 #ifdef BNX2X_STOP_ON_ERROR
9480 if (unlikely(bp->panic))
9481 return NETDEV_TX_BUSY;
9484 fp_index = (smp_processor_id() % bp->num_queues);
9485 fp = &bp->fp[fp_index];
9487 if (unlikely(bnx2x_tx_avail(bp->fp) <
9488 (skb_shinfo(skb)->nr_frags + 3))) {
9489 bp->eth_stats.driver_xoff++,
9490 netif_stop_queue(dev);
9491 BNX2X_ERR("BUG! Tx ring full when queue awake!\n");
9492 return NETDEV_TX_BUSY;
9495 DP(NETIF_MSG_TX_QUEUED, "SKB: summed %x protocol %x protocol(%x,%x)"
9496 " gso type %x xmit_type %x\n",
9497 skb->ip_summed, skb->protocol, ipv6_hdr(skb)->nexthdr,
9498 ip_hdr(skb)->protocol, skb_shinfo(skb)->gso_type, xmit_type);
9500 /* First, check if we need to linearaize the skb
9501 (due to FW restrictions) */
9502 if (bnx2x_pkt_req_lin(bp, skb, xmit_type)) {
9503 /* Statistics of linearization */
9505 if (skb_linearize(skb) != 0) {
9506 DP(NETIF_MSG_TX_QUEUED, "SKB linearization failed - "
9507 "silently dropping this SKB\n");
9508 dev_kfree_skb_any(skb);
9509 return NETDEV_TX_OK;
9514 Please read carefully. First we use one BD which we mark as start,
9515 then for TSO or xsum we have a parsing info BD,
9516 and only then we have the rest of the TSO BDs.
9517 (don't forget to mark the last one as last,
9518 and to unmap only AFTER you write to the BD ...)
9519 And above all, all pdb sizes are in words - NOT DWORDS!
9522 pkt_prod = fp->tx_pkt_prod++;
9523 bd_prod = TX_BD(fp->tx_bd_prod);
9525 /* get a tx_buf and first BD */
9526 tx_buf = &fp->tx_buf_ring[TX_BD(pkt_prod)];
9527 tx_bd = &fp->tx_desc_ring[bd_prod];
9529 tx_bd->bd_flags.as_bitfield = ETH_TX_BD_FLAGS_START_BD;
9530 tx_bd->general_data = (UNICAST_ADDRESS <<
9531 ETH_TX_BD_ETH_ADDR_TYPE_SHIFT);
9532 tx_bd->general_data |= 1; /* header nbd */
9534 /* remember the first BD of the packet */
9535 tx_buf->first_bd = fp->tx_bd_prod;
9538 DP(NETIF_MSG_TX_QUEUED,
9539 "sending pkt %u @%p next_idx %u bd %u @%p\n",
9540 pkt_prod, tx_buf, fp->tx_pkt_prod, bd_prod, tx_bd);
9542 if ((bp->vlgrp != NULL) && vlan_tx_tag_present(skb)) {
9543 tx_bd->vlan = cpu_to_le16(vlan_tx_tag_get(skb));
9544 tx_bd->bd_flags.as_bitfield |= ETH_TX_BD_FLAGS_VLAN_TAG;
9547 tx_bd->vlan = cpu_to_le16(pkt_prod);
9551 /* turn on parsing and get a BD */
9552 bd_prod = TX_BD(NEXT_TX_IDX(bd_prod));
9553 pbd = (void *)&fp->tx_desc_ring[bd_prod];
9555 memset(pbd, 0, sizeof(struct eth_tx_parse_bd));
9558 if (xmit_type & XMIT_CSUM) {
9559 hlen = (skb_network_header(skb) - skb->data + vlan_off) / 2;
9561 /* for now NS flag is not used in Linux */
9562 pbd->global_data = (hlen |
9563 ((skb->protocol == ntohs(ETH_P_8021Q)) <<
9564 ETH_TX_PARSE_BD_LLC_SNAP_EN_SHIFT));
9566 pbd->ip_hlen = (skb_transport_header(skb) -
9567 skb_network_header(skb)) / 2;
9569 hlen += pbd->ip_hlen + tcp_hdrlen(skb) / 2;
9571 pbd->total_hlen = cpu_to_le16(hlen);
9572 hlen = hlen*2 - vlan_off;
9574 tx_bd->bd_flags.as_bitfield |= ETH_TX_BD_FLAGS_TCP_CSUM;
9576 if (xmit_type & XMIT_CSUM_V4)
9577 tx_bd->bd_flags.as_bitfield |=
9578 ETH_TX_BD_FLAGS_IP_CSUM;
9580 tx_bd->bd_flags.as_bitfield |= ETH_TX_BD_FLAGS_IPV6;
9582 if (xmit_type & XMIT_CSUM_TCP) {
9583 pbd->tcp_pseudo_csum = swab16(tcp_hdr(skb)->check);
9586 s8 fix = SKB_CS_OFF(skb); /* signed! */
9588 pbd->global_data |= ETH_TX_PARSE_BD_CS_ANY_FLG;
9589 pbd->cs_offset = fix / 2;
9591 DP(NETIF_MSG_TX_QUEUED,
9592 "hlen %d offset %d fix %d csum before fix %x\n",
9593 le16_to_cpu(pbd->total_hlen), pbd->cs_offset, fix,
9596 /* HW bug: fixup the CSUM */
9597 pbd->tcp_pseudo_csum =
9598 bnx2x_csum_fix(skb_transport_header(skb),
9601 DP(NETIF_MSG_TX_QUEUED, "csum after fix %x\n",
9602 pbd->tcp_pseudo_csum);
9606 mapping = pci_map_single(bp->pdev, skb->data,
9607 skb_headlen(skb), PCI_DMA_TODEVICE);
9609 tx_bd->addr_hi = cpu_to_le32(U64_HI(mapping));
9610 tx_bd->addr_lo = cpu_to_le32(U64_LO(mapping));
9611 nbd = skb_shinfo(skb)->nr_frags + ((pbd == NULL)? 1 : 2);
9612 tx_bd->nbd = cpu_to_le16(nbd);
9613 tx_bd->nbytes = cpu_to_le16(skb_headlen(skb));
9615 DP(NETIF_MSG_TX_QUEUED, "first bd @%p addr (%x:%x) nbd %d"
9616 " nbytes %d flags %x vlan %x\n",
9617 tx_bd, tx_bd->addr_hi, tx_bd->addr_lo, le16_to_cpu(tx_bd->nbd),
9618 le16_to_cpu(tx_bd->nbytes), tx_bd->bd_flags.as_bitfield,
9619 le16_to_cpu(tx_bd->vlan));
9621 if (xmit_type & XMIT_GSO) {
9623 DP(NETIF_MSG_TX_QUEUED,
9624 "TSO packet len %d hlen %d total len %d tso size %d\n",
9625 skb->len, hlen, skb_headlen(skb),
9626 skb_shinfo(skb)->gso_size);
9628 tx_bd->bd_flags.as_bitfield |= ETH_TX_BD_FLAGS_SW_LSO;
9630 if (unlikely(skb_headlen(skb) > hlen))
9631 bd_prod = bnx2x_tx_split(bp, fp, &tx_bd, hlen,
9634 pbd->lso_mss = cpu_to_le16(skb_shinfo(skb)->gso_size);
9635 pbd->tcp_send_seq = swab32(tcp_hdr(skb)->seq);
9636 pbd->tcp_flags = pbd_tcp_flags(skb);
9638 if (xmit_type & XMIT_GSO_V4) {
9639 pbd->ip_id = swab16(ip_hdr(skb)->id);
9640 pbd->tcp_pseudo_csum =
9641 swab16(~csum_tcpudp_magic(ip_hdr(skb)->saddr,
9643 0, IPPROTO_TCP, 0));
9646 pbd->tcp_pseudo_csum =
9647 swab16(~csum_ipv6_magic(&ipv6_hdr(skb)->saddr,
9648 &ipv6_hdr(skb)->daddr,
9649 0, IPPROTO_TCP, 0));
9651 pbd->global_data |= ETH_TX_PARSE_BD_PSEUDO_CS_WITHOUT_LEN;
9654 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
9655 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
9657 bd_prod = TX_BD(NEXT_TX_IDX(bd_prod));
9658 tx_bd = &fp->tx_desc_ring[bd_prod];
9660 mapping = pci_map_page(bp->pdev, frag->page, frag->page_offset,
9661 frag->size, PCI_DMA_TODEVICE);
9663 tx_bd->addr_hi = cpu_to_le32(U64_HI(mapping));
9664 tx_bd->addr_lo = cpu_to_le32(U64_LO(mapping));
9665 tx_bd->nbytes = cpu_to_le16(frag->size);
9666 tx_bd->vlan = cpu_to_le16(pkt_prod);
9667 tx_bd->bd_flags.as_bitfield = 0;
9669 DP(NETIF_MSG_TX_QUEUED,
9670 "frag %d bd @%p addr (%x:%x) nbytes %d flags %x\n",
9671 i, tx_bd, tx_bd->addr_hi, tx_bd->addr_lo,
9672 le16_to_cpu(tx_bd->nbytes), tx_bd->bd_flags.as_bitfield);
9675 /* now at last mark the BD as the last BD */
9676 tx_bd->bd_flags.as_bitfield |= ETH_TX_BD_FLAGS_END_BD;
9678 DP(NETIF_MSG_TX_QUEUED, "last bd @%p flags %x\n",
9679 tx_bd, tx_bd->bd_flags.as_bitfield);
9681 bd_prod = TX_BD(NEXT_TX_IDX(bd_prod));
9683 /* now send a tx doorbell, counting the next BD
9684 * if the packet contains or ends with it
9686 if (TX_BD_POFF(bd_prod) < nbd)
9690 DP(NETIF_MSG_TX_QUEUED,
9691 "PBD @%p ip_data %x ip_hlen %u ip_id %u lso_mss %u"
9692 " tcp_flags %x xsum %x seq %u hlen %u\n",
9693 pbd, pbd->global_data, pbd->ip_hlen, pbd->ip_id,
9694 pbd->lso_mss, pbd->tcp_flags, pbd->tcp_pseudo_csum,
9695 pbd->tcp_send_seq, le16_to_cpu(pbd->total_hlen));
9697 DP(NETIF_MSG_TX_QUEUED, "doorbell: nbd %d bd %u\n", nbd, bd_prod);
9699 fp->hw_tx_prods->bds_prod =
9700 cpu_to_le16(le16_to_cpu(fp->hw_tx_prods->bds_prod) + nbd);
9701 mb(); /* FW restriction: must not reorder writing nbd and packets */
9702 fp->hw_tx_prods->packets_prod =
9703 cpu_to_le32(le32_to_cpu(fp->hw_tx_prods->packets_prod) + 1);
9704 DOORBELL(bp, FP_IDX(fp), 0);
9708 fp->tx_bd_prod += nbd;
9709 dev->trans_start = jiffies;
9711 if (unlikely(bnx2x_tx_avail(fp) < MAX_SKB_FRAGS + 3)) {
9712 netif_stop_queue(dev);
9713 bp->eth_stats.driver_xoff++;
9714 if (bnx2x_tx_avail(fp) >= MAX_SKB_FRAGS + 3)
9715 netif_wake_queue(dev);
9719 return NETDEV_TX_OK;
9722 /* called with rtnl_lock */
9723 static int bnx2x_open(struct net_device *dev)
9725 struct bnx2x *bp = netdev_priv(dev);
9727 bnx2x_set_power_state(bp, PCI_D0);
9729 return bnx2x_nic_load(bp, LOAD_OPEN);
9732 /* called with rtnl_lock */
9733 static int bnx2x_close(struct net_device *dev)
9735 struct bnx2x *bp = netdev_priv(dev);
9737 /* Unload the driver, release IRQs */
9738 bnx2x_nic_unload(bp, UNLOAD_CLOSE);
9739 if (atomic_read(&bp->pdev->enable_cnt) == 1)
9740 if (!CHIP_REV_IS_SLOW(bp))
9741 bnx2x_set_power_state(bp, PCI_D3hot);
9746 /* called with netif_tx_lock from set_multicast */
9747 static void bnx2x_set_rx_mode(struct net_device *dev)
9749 struct bnx2x *bp = netdev_priv(dev);
9750 u32 rx_mode = BNX2X_RX_MODE_NORMAL;
9751 int port = BP_PORT(bp);
9753 if (bp->state != BNX2X_STATE_OPEN) {
9754 DP(NETIF_MSG_IFUP, "state is %x, returning\n", bp->state);
9758 DP(NETIF_MSG_IFUP, "dev->flags = %x\n", dev->flags);
9760 if (dev->flags & IFF_PROMISC)
9761 rx_mode = BNX2X_RX_MODE_PROMISC;
9763 else if ((dev->flags & IFF_ALLMULTI) ||
9764 ((dev->mc_count > BNX2X_MAX_MULTICAST) && CHIP_IS_E1(bp)))
9765 rx_mode = BNX2X_RX_MODE_ALLMULTI;
9767 else { /* some multicasts */
9768 if (CHIP_IS_E1(bp)) {
9770 struct dev_mc_list *mclist;
9771 struct mac_configuration_cmd *config =
9772 bnx2x_sp(bp, mcast_config);
9774 for (i = 0, mclist = dev->mc_list;
9775 mclist && (i < dev->mc_count);
9776 i++, mclist = mclist->next) {
9778 config->config_table[i].
9779 cam_entry.msb_mac_addr =
9780 swab16(*(u16 *)&mclist->dmi_addr[0]);
9781 config->config_table[i].
9782 cam_entry.middle_mac_addr =
9783 swab16(*(u16 *)&mclist->dmi_addr[2]);
9784 config->config_table[i].
9785 cam_entry.lsb_mac_addr =
9786 swab16(*(u16 *)&mclist->dmi_addr[4]);
9787 config->config_table[i].cam_entry.flags =
9789 config->config_table[i].
9790 target_table_entry.flags = 0;
9791 config->config_table[i].
9792 target_table_entry.client_id = 0;
9793 config->config_table[i].
9794 target_table_entry.vlan_id = 0;
9797 "setting MCAST[%d] (%04x:%04x:%04x)\n", i,
9798 config->config_table[i].
9799 cam_entry.msb_mac_addr,
9800 config->config_table[i].
9801 cam_entry.middle_mac_addr,
9802 config->config_table[i].
9803 cam_entry.lsb_mac_addr);
9805 old = config->hdr.length_6b;
9807 for (; i < old; i++) {
9808 if (CAM_IS_INVALID(config->
9810 i--; /* already invalidated */
9814 CAM_INVALIDATE(config->
9819 if (CHIP_REV_IS_SLOW(bp))
9820 offset = BNX2X_MAX_EMUL_MULTI*(1 + port);
9822 offset = BNX2X_MAX_MULTICAST*(1 + port);
9824 config->hdr.length_6b = i;
9825 config->hdr.offset = offset;
9826 config->hdr.client_id = BP_CL_ID(bp);
9827 config->hdr.reserved1 = 0;
9829 bnx2x_sp_post(bp, RAMROD_CMD_ID_ETH_SET_MAC, 0,
9830 U64_HI(bnx2x_sp_mapping(bp, mcast_config)),
9831 U64_LO(bnx2x_sp_mapping(bp, mcast_config)),
9834 /* Accept one or more multicasts */
9835 struct dev_mc_list *mclist;
9836 u32 mc_filter[MC_HASH_SIZE];
9837 u32 crc, bit, regidx;
9840 memset(mc_filter, 0, 4 * MC_HASH_SIZE);
9842 for (i = 0, mclist = dev->mc_list;
9843 mclist && (i < dev->mc_count);
9844 i++, mclist = mclist->next) {
9846 DP(NETIF_MSG_IFUP, "Adding mcast MAC: "
9847 "%02x:%02x:%02x:%02x:%02x:%02x\n",
9848 mclist->dmi_addr[0], mclist->dmi_addr[1],
9849 mclist->dmi_addr[2], mclist->dmi_addr[3],
9850 mclist->dmi_addr[4], mclist->dmi_addr[5]);
9852 crc = crc32c_le(0, mclist->dmi_addr, ETH_ALEN);
9853 bit = (crc >> 24) & 0xff;
9856 mc_filter[regidx] |= (1 << bit);
9859 for (i = 0; i < MC_HASH_SIZE; i++)
9860 REG_WR(bp, MC_HASH_OFFSET(bp, i),
9865 bp->rx_mode = rx_mode;
9866 bnx2x_set_storm_rx_mode(bp);
9869 /* called with rtnl_lock */
9870 static int bnx2x_change_mac_addr(struct net_device *dev, void *p)
9872 struct sockaddr *addr = p;
9873 struct bnx2x *bp = netdev_priv(dev);
9875 if (!is_valid_ether_addr((u8 *)(addr->sa_data)))
9878 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
9879 if (netif_running(dev)) {
9881 bnx2x_set_mac_addr_e1(bp, 1);
9883 bnx2x_set_mac_addr_e1h(bp, 1);
9889 /* called with rtnl_lock */
9890 static int bnx2x_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
9892 struct mii_ioctl_data *data = if_mii(ifr);
9893 struct bnx2x *bp = netdev_priv(dev);
9898 data->phy_id = bp->port.phy_addr;
9905 if (!netif_running(dev))
9908 mutex_lock(&bp->port.phy_mutex);
9909 err = bnx2x_cl45_read(bp, BP_PORT(bp), 0, bp->port.phy_addr,
9910 DEFAULT_PHY_DEV_ADDR,
9911 (data->reg_num & 0x1f), &mii_regval);
9912 data->val_out = mii_regval;
9913 mutex_unlock(&bp->port.phy_mutex);
9918 if (!capable(CAP_NET_ADMIN))
9921 if (!netif_running(dev))
9924 mutex_lock(&bp->port.phy_mutex);
9925 err = bnx2x_cl45_write(bp, BP_PORT(bp), 0, bp->port.phy_addr,
9926 DEFAULT_PHY_DEV_ADDR,
9927 (data->reg_num & 0x1f), data->val_in);
9928 mutex_unlock(&bp->port.phy_mutex);
9939 /* called with rtnl_lock */
9940 static int bnx2x_change_mtu(struct net_device *dev, int new_mtu)
9942 struct bnx2x *bp = netdev_priv(dev);
9945 if ((new_mtu > ETH_MAX_JUMBO_PACKET_SIZE) ||
9946 ((new_mtu + ETH_HLEN) < ETH_MIN_PACKET_SIZE))
9949 /* This does not race with packet allocation
9950 * because the actual alloc size is
9951 * only updated as part of load
9955 if (netif_running(dev)) {
9956 bnx2x_nic_unload(bp, UNLOAD_NORMAL);
9957 rc = bnx2x_nic_load(bp, LOAD_NORMAL);
9963 static void bnx2x_tx_timeout(struct net_device *dev)
9965 struct bnx2x *bp = netdev_priv(dev);
9967 #ifdef BNX2X_STOP_ON_ERROR
9971 /* This allows the netif to be shutdown gracefully before resetting */
9972 schedule_work(&bp->reset_task);
9976 /* called with rtnl_lock */
9977 static void bnx2x_vlan_rx_register(struct net_device *dev,
9978 struct vlan_group *vlgrp)
9980 struct bnx2x *bp = netdev_priv(dev);
9983 if (netif_running(dev))
9984 bnx2x_set_client_config(bp);
9989 #if defined(HAVE_POLL_CONTROLLER) || defined(CONFIG_NET_POLL_CONTROLLER)
9990 static void poll_bnx2x(struct net_device *dev)
9992 struct bnx2x *bp = netdev_priv(dev);
9994 disable_irq(bp->pdev->irq);
9995 bnx2x_interrupt(bp->pdev->irq, dev);
9996 enable_irq(bp->pdev->irq);
10000 static int __devinit bnx2x_init_dev(struct pci_dev *pdev,
10001 struct net_device *dev)
10006 SET_NETDEV_DEV(dev, &pdev->dev);
10007 bp = netdev_priv(dev);
10012 bp->func = PCI_FUNC(pdev->devfn);
10014 rc = pci_enable_device(pdev);
10016 printk(KERN_ERR PFX "Cannot enable PCI device, aborting\n");
10020 if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
10021 printk(KERN_ERR PFX "Cannot find PCI device base address,"
10024 goto err_out_disable;
10027 if (!(pci_resource_flags(pdev, 2) & IORESOURCE_MEM)) {
10028 printk(KERN_ERR PFX "Cannot find second PCI device"
10029 " base address, aborting\n");
10031 goto err_out_disable;
10034 if (atomic_read(&pdev->enable_cnt) == 1) {
10035 rc = pci_request_regions(pdev, DRV_MODULE_NAME);
10037 printk(KERN_ERR PFX "Cannot obtain PCI resources,"
10039 goto err_out_disable;
10042 pci_set_master(pdev);
10043 pci_save_state(pdev);
10046 bp->pm_cap = pci_find_capability(pdev, PCI_CAP_ID_PM);
10047 if (bp->pm_cap == 0) {
10048 printk(KERN_ERR PFX "Cannot find power management"
10049 " capability, aborting\n");
10051 goto err_out_release;
10054 bp->pcie_cap = pci_find_capability(pdev, PCI_CAP_ID_EXP);
10055 if (bp->pcie_cap == 0) {
10056 printk(KERN_ERR PFX "Cannot find PCI Express capability,"
10059 goto err_out_release;
10062 if (pci_set_dma_mask(pdev, DMA_64BIT_MASK) == 0) {
10063 bp->flags |= USING_DAC_FLAG;
10064 if (pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK) != 0) {
10065 printk(KERN_ERR PFX "pci_set_consistent_dma_mask"
10066 " failed, aborting\n");
10068 goto err_out_release;
10071 } else if (pci_set_dma_mask(pdev, DMA_32BIT_MASK) != 0) {
10072 printk(KERN_ERR PFX "System does not support DMA,"
10075 goto err_out_release;
10078 dev->mem_start = pci_resource_start(pdev, 0);
10079 dev->base_addr = dev->mem_start;
10080 dev->mem_end = pci_resource_end(pdev, 0);
10082 dev->irq = pdev->irq;
10084 bp->regview = ioremap_nocache(dev->base_addr,
10085 pci_resource_len(pdev, 0));
10086 if (!bp->regview) {
10087 printk(KERN_ERR PFX "Cannot map register space, aborting\n");
10089 goto err_out_release;
10092 bp->doorbells = ioremap_nocache(pci_resource_start(pdev, 2),
10093 min_t(u64, BNX2X_DB_SIZE,
10094 pci_resource_len(pdev, 2)));
10095 if (!bp->doorbells) {
10096 printk(KERN_ERR PFX "Cannot map doorbell space, aborting\n");
10098 goto err_out_unmap;
10101 bnx2x_set_power_state(bp, PCI_D0);
10103 /* clean indirect addresses */
10104 pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS,
10105 PCICFG_VENDOR_ID_OFFSET);
10106 REG_WR(bp, PXP2_REG_PGL_ADDR_88_F0 + BP_PORT(bp)*16, 0);
10107 REG_WR(bp, PXP2_REG_PGL_ADDR_8C_F0 + BP_PORT(bp)*16, 0);
10108 REG_WR(bp, PXP2_REG_PGL_ADDR_90_F0 + BP_PORT(bp)*16, 0);
10109 REG_WR(bp, PXP2_REG_PGL_ADDR_94_F0 + BP_PORT(bp)*16, 0);
10111 dev->hard_start_xmit = bnx2x_start_xmit;
10112 dev->watchdog_timeo = TX_TIMEOUT;
10114 dev->ethtool_ops = &bnx2x_ethtool_ops;
10115 dev->open = bnx2x_open;
10116 dev->stop = bnx2x_close;
10117 dev->set_multicast_list = bnx2x_set_rx_mode;
10118 dev->set_mac_address = bnx2x_change_mac_addr;
10119 dev->do_ioctl = bnx2x_ioctl;
10120 dev->change_mtu = bnx2x_change_mtu;
10121 dev->tx_timeout = bnx2x_tx_timeout;
10123 dev->vlan_rx_register = bnx2x_vlan_rx_register;
10125 #if defined(HAVE_POLL_CONTROLLER) || defined(CONFIG_NET_POLL_CONTROLLER)
10126 dev->poll_controller = poll_bnx2x;
10128 dev->features |= NETIF_F_SG;
10129 dev->features |= NETIF_F_HW_CSUM;
10130 if (bp->flags & USING_DAC_FLAG)
10131 dev->features |= NETIF_F_HIGHDMA;
10133 dev->features |= (NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX);
10135 dev->features |= (NETIF_F_TSO | NETIF_F_TSO_ECN);
10136 dev->features |= NETIF_F_TSO6;
10142 iounmap(bp->regview);
10143 bp->regview = NULL;
10145 if (bp->doorbells) {
10146 iounmap(bp->doorbells);
10147 bp->doorbells = NULL;
10151 if (atomic_read(&pdev->enable_cnt) == 1)
10152 pci_release_regions(pdev);
10155 pci_disable_device(pdev);
10156 pci_set_drvdata(pdev, NULL);
10162 static int __devinit bnx2x_get_pcie_width(struct bnx2x *bp)
10164 u32 val = REG_RD(bp, PCICFG_OFFSET + PCICFG_LINK_CONTROL);
10166 val = (val & PCICFG_LINK_WIDTH) >> PCICFG_LINK_WIDTH_SHIFT;
10170 /* return value of 1=2.5GHz 2=5GHz */
10171 static int __devinit bnx2x_get_pcie_speed(struct bnx2x *bp)
10173 u32 val = REG_RD(bp, PCICFG_OFFSET + PCICFG_LINK_CONTROL);
10175 val = (val & PCICFG_LINK_SPEED) >> PCICFG_LINK_SPEED_SHIFT;
10179 static int __devinit bnx2x_init_one(struct pci_dev *pdev,
10180 const struct pci_device_id *ent)
10182 static int version_printed;
10183 struct net_device *dev = NULL;
10186 DECLARE_MAC_BUF(mac);
10188 if (version_printed++ == 0)
10189 printk(KERN_INFO "%s", version);
10191 /* dev zeroed in init_etherdev */
10192 dev = alloc_etherdev(sizeof(*bp));
10194 printk(KERN_ERR PFX "Cannot allocate net device\n");
10198 netif_carrier_off(dev);
10200 bp = netdev_priv(dev);
10201 bp->msglevel = debug;
10203 rc = bnx2x_init_dev(pdev, dev);
10209 rc = register_netdev(dev);
10211 dev_err(&pdev->dev, "Cannot register net device\n");
10212 goto init_one_exit;
10215 pci_set_drvdata(pdev, dev);
10217 rc = bnx2x_init_bp(bp);
10219 unregister_netdev(dev);
10220 goto init_one_exit;
10223 bp->common.name = board_info[ent->driver_data].name;
10224 printk(KERN_INFO "%s: %s (%c%d) PCI-E x%d %s found at mem %lx,"
10225 " IRQ %d, ", dev->name, bp->common.name,
10226 (CHIP_REV(bp) >> 12) + 'A', (CHIP_METAL(bp) >> 4),
10227 bnx2x_get_pcie_width(bp),
10228 (bnx2x_get_pcie_speed(bp) == 2) ? "5GHz (Gen2)" : "2.5GHz",
10229 dev->base_addr, bp->pdev->irq);
10230 printk(KERN_CONT "node addr %s\n", print_mac(mac, dev->dev_addr));
10235 iounmap(bp->regview);
10238 iounmap(bp->doorbells);
10242 if (atomic_read(&pdev->enable_cnt) == 1)
10243 pci_release_regions(pdev);
10245 pci_disable_device(pdev);
10246 pci_set_drvdata(pdev, NULL);
10251 static void __devexit bnx2x_remove_one(struct pci_dev *pdev)
10253 struct net_device *dev = pci_get_drvdata(pdev);
10257 printk(KERN_ERR PFX "BAD net device from bnx2x_init_one\n");
10260 bp = netdev_priv(dev);
10262 unregister_netdev(dev);
10265 iounmap(bp->regview);
10268 iounmap(bp->doorbells);
10272 if (atomic_read(&pdev->enable_cnt) == 1)
10273 pci_release_regions(pdev);
10275 pci_disable_device(pdev);
10276 pci_set_drvdata(pdev, NULL);
10279 static int bnx2x_suspend(struct pci_dev *pdev, pm_message_t state)
10281 struct net_device *dev = pci_get_drvdata(pdev);
10285 printk(KERN_ERR PFX "BAD net device from bnx2x_init_one\n");
10288 bp = netdev_priv(dev);
10292 pci_save_state(pdev);
10294 if (!netif_running(dev)) {
10299 netif_device_detach(dev);
10301 bnx2x_nic_unload(bp, UNLOAD_CLOSE);
10303 bnx2x_set_power_state(bp, pci_choose_state(pdev, state));
10310 static int bnx2x_resume(struct pci_dev *pdev)
10312 struct net_device *dev = pci_get_drvdata(pdev);
10317 printk(KERN_ERR PFX "BAD net device from bnx2x_init_one\n");
10320 bp = netdev_priv(dev);
10324 pci_restore_state(pdev);
10326 if (!netif_running(dev)) {
10331 bnx2x_set_power_state(bp, PCI_D0);
10332 netif_device_attach(dev);
10334 rc = bnx2x_nic_load(bp, LOAD_OPEN);
10342 * bnx2x_io_error_detected - called when PCI error is detected
10343 * @pdev: Pointer to PCI device
10344 * @state: The current pci connection state
10346 * This function is called after a PCI bus error affecting
10347 * this device has been detected.
10349 static pci_ers_result_t bnx2x_io_error_detected(struct pci_dev *pdev,
10350 pci_channel_state_t state)
10352 struct net_device *dev = pci_get_drvdata(pdev);
10353 struct bnx2x *bp = netdev_priv(dev);
10357 netif_device_detach(dev);
10359 if (netif_running(dev))
10360 bnx2x_nic_unload(bp, UNLOAD_CLOSE);
10362 pci_disable_device(pdev);
10366 /* Request a slot reset */
10367 return PCI_ERS_RESULT_NEED_RESET;
10371 * bnx2x_io_slot_reset - called after the PCI bus has been reset
10372 * @pdev: Pointer to PCI device
10374 * Restart the card from scratch, as if from a cold-boot.
10376 static pci_ers_result_t bnx2x_io_slot_reset(struct pci_dev *pdev)
10378 struct net_device *dev = pci_get_drvdata(pdev);
10379 struct bnx2x *bp = netdev_priv(dev);
10383 if (pci_enable_device(pdev)) {
10384 dev_err(&pdev->dev,
10385 "Cannot re-enable PCI device after reset\n");
10387 return PCI_ERS_RESULT_DISCONNECT;
10390 pci_set_master(pdev);
10391 pci_restore_state(pdev);
10393 if (netif_running(dev))
10394 bnx2x_set_power_state(bp, PCI_D0);
10398 return PCI_ERS_RESULT_RECOVERED;
10402 * bnx2x_io_resume - called when traffic can start flowing again
10403 * @pdev: Pointer to PCI device
10405 * This callback is called when the error recovery driver tells us that
10406 * its OK to resume normal operation.
10408 static void bnx2x_io_resume(struct pci_dev *pdev)
10410 struct net_device *dev = pci_get_drvdata(pdev);
10411 struct bnx2x *bp = netdev_priv(dev);
10415 if (netif_running(dev))
10416 bnx2x_nic_load(bp, LOAD_OPEN);
10418 netif_device_attach(dev);
10423 static struct pci_error_handlers bnx2x_err_handler = {
10424 .error_detected = bnx2x_io_error_detected,
10425 .slot_reset = bnx2x_io_slot_reset,
10426 .resume = bnx2x_io_resume,
10429 static struct pci_driver bnx2x_pci_driver = {
10430 .name = DRV_MODULE_NAME,
10431 .id_table = bnx2x_pci_tbl,
10432 .probe = bnx2x_init_one,
10433 .remove = __devexit_p(bnx2x_remove_one),
10434 .suspend = bnx2x_suspend,
10435 .resume = bnx2x_resume,
10436 .err_handler = &bnx2x_err_handler,
10439 static int __init bnx2x_init(void)
10441 return pci_register_driver(&bnx2x_pci_driver);
10444 static void __exit bnx2x_cleanup(void)
10446 pci_unregister_driver(&bnx2x_pci_driver);
10449 module_init(bnx2x_init);
10450 module_exit(bnx2x_cleanup);