1 /* Copyright 2008 Broadcom Corporation
3 * Unless you and Broadcom execute a separate written software license
4 * agreement governing use of this software, this software is licensed to you
5 * under the terms of the GNU General Public License version 2, available
6 * at http://www.gnu.org/licenses/old-licenses/gpl-2.0.html (the "GPL").
8 * Notwithstanding the above, under no circumstances may you combine this
9 * software in any way with any other Broadcom software provided under a
10 * license other than the GPL, without Broadcom's express prior written
13 * Written by Yaniv Rosner
22 /***********************************************************/
24 /***********************************************************/
25 #define DEFAULT_PHY_DEV_ADDR 3
29 #define FLOW_CTRL_AUTO PORT_FEATURE_FLOW_CONTROL_AUTO
30 #define FLOW_CTRL_TX PORT_FEATURE_FLOW_CONTROL_TX
31 #define FLOW_CTRL_RX PORT_FEATURE_FLOW_CONTROL_RX
32 #define FLOW_CTRL_BOTH PORT_FEATURE_FLOW_CONTROL_BOTH
33 #define FLOW_CTRL_NONE PORT_FEATURE_FLOW_CONTROL_NONE
35 #define SPEED_AUTO_NEG 0
36 #define SPEED_12000 12000
37 #define SPEED_12500 12500
38 #define SPEED_13000 13000
39 #define SPEED_15000 15000
40 #define SPEED_16000 16000
43 /***********************************************************/
45 /***********************************************************/
46 /* Inputs parameters to the CLC */
51 /* Default / User Configuration */
53 #define LOOPBACK_NONE 0
54 #define LOOPBACK_EMAC 1
55 #define LOOPBACK_BMAC 2
56 #define LOOPBACK_XGXS_10 3
57 #define LOOPBACK_EXT_PHY 4
61 u16 req_fc_auto_adv; /* Should be set to TX / BOTH when
62 req_flow_ctrl is set to AUTO */
63 u16 req_line_speed; /* Also determine AutoNeg */
65 /* Device parameters */
70 /* shmem parameters */
74 #define SWITCH_CFG_1G PORT_FEATURE_CON_SWITCH_1G_SWITCH
75 #define SWITCH_CFG_10G PORT_FEATURE_CON_SWITCH_10G_SWITCH
76 #define SWITCH_CFG_AUTO_DETECT PORT_FEATURE_CON_SWITCH_AUTO_DETECT
78 u16 hw_led_mode; /* part of the hw_config read from the shmem */
82 #define XGXS_EXT_PHY_TYPE(ext_phy_config) (ext_phy_config & \
83 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_MASK)
84 #define SERDES_EXT_PHY_TYPE(ext_phy_config) (ext_phy_config & \
85 PORT_HW_CFG_SERDES_EXT_PHY_TYPE_MASK)
86 /* Phy register parameter */
89 /* phy_addr populated by the CLC */
91 /* Device pointer passed to all callback functions */
95 /* Output parameters */
97 u8 phy_link_up; /* internal phy link indication */
104 #define MAC_TYPE_NONE 0
105 #define MAC_TYPE_EMAC 1
106 #define MAC_TYPE_BMAC 2
109 #define AUTO_NEG_DISABLED 0x0
110 #define AUTO_NEG_ENABLED 0x1
111 #define AUTO_NEG_COMPLETE 0x2
112 #define AUTO_NEG_PARALLEL_DETECTION_USED 0x3
116 /* The same definitions as the shmem parameter */
120 /***********************************************************/
122 /***********************************************************/
124 /* Initialize the phy */
125 u8 bnx2x_phy_init(struct link_params *input, struct link_vars *output);
127 /* Reset the link. Should be called when driver or interface goes down */
128 u8 bnx2x_link_reset(struct link_params *params, struct link_vars *vars);
130 /* bnx2x_link_update should be called upon link interrupt */
131 u8 bnx2x_link_update(struct link_params *input, struct link_vars *output);
133 /* use the following cl45 functions to read/write from external_phy
134 In order to use it to read/write internal phy registers, use
135 DEFAULT_PHY_DEV_ADDR as devad, and (_bank + (_addr & 0xf)) as
136 Use ext_phy_type of 0 in case of cl22 over cl45
138 u8 bnx2x_cl45_read(struct bnx2x *bp, u8 port, u32 ext_phy_type,
139 u8 phy_addr, u8 devad, u16 reg, u16 *ret_val);
141 u8 bnx2x_cl45_write(struct bnx2x *bp, u8 port, u32 ext_phy_type,
142 u8 phy_addr, u8 devad, u16 reg, u16 val);
144 /* Reads the link_status from the shmem,
145 and update the link vars accordinaly */
146 void bnx2x_link_status_update(struct link_params *input,
147 struct link_vars *output);
148 /* returns string representing the fw_version of the external phy */
149 u8 bnx2x_get_ext_phy_fw_version(struct link_params *params, u8 driver_loaded,
150 u8 *version, u16 len);
153 Basically, the CLC takes care of the led for the link, but in case one needs
154 to set/unset the led unnatually, set the "mode" to LED_MODE_OPER to
155 blink the led, and LED_MODE_OFF to set the led off.*/
156 u8 bnx2x_set_led(struct bnx2x *bp, u8 port, u8 mode, u32 speed,
157 u16 hw_led_mode, u32 chip_id);
158 #define LED_MODE_OFF 0
159 #define LED_MODE_OPER 2
161 u8 bnx2x_override_led_value(struct bnx2x *bp, u8 port, u32 led_idx, u32 value);
163 u8 bnx2x_flash_download(struct bnx2x *bp, u8 port, u32 ext_phy_config,
164 u8 driver_loaded, char data[], u32 size);
165 /* Get the actual link status. In case it returns 0, link is up,
166 otherwise link is down*/
167 u8 bnx2x_test_link(struct link_params *input, struct link_vars *vars);
170 #endif /* BNX2X_LINK_H */