1 /* bnx2x_init.h: Broadcom Everest network driver.
3 * Copyright (c) 2007-2008 Broadcom Corporation
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation.
9 * Maintained by: Eilon Greenstein <eilong@broadcom.com>
10 * Written by: Eliezer Tamir
20 #define INIT_EMULATION 0x1
23 #define INIT_HARDWARE 0x7
25 #define STORM_INTMEM_SIZE (0x5800 / 4)
26 #define TSTORM_INTMEM_ADDR 0x1a0000
27 #define CSTORM_INTMEM_ADDR 0x220000
28 #define XSTORM_INTMEM_ADDR 0x2a0000
29 #define USTORM_INTMEM_ADDR 0x320000
32 /* Init operation types and structures */
34 #define OP_RD 0x1 /* read single register */
35 #define OP_WR 0x2 /* write single register */
36 #define OP_IW 0x3 /* write single register using mailbox */
37 #define OP_SW 0x4 /* copy a string to the device */
38 #define OP_SI 0x5 /* copy a string using mailbox */
39 #define OP_ZR 0x6 /* clear memory */
40 #define OP_ZP 0x7 /* unzip then copy with DMAE */
41 #define OP_WB 0x8 /* copy a string using DMAE */
61 struct op_string_write {
64 #ifdef __LITTLE_ENDIAN
67 #else /* __BIG_ENDIAN */
81 struct op_write write;
82 struct op_string_write str_wr;
87 #include "bnx2x_init_values.h"
89 static void bnx2x_reg_wr_ind(struct bnx2x *bp, u32 addr, u32 val);
90 static int bnx2x_gunzip(struct bnx2x *bp, u8 *zbuf, int len);
92 static void bnx2x_init_str_wr(struct bnx2x *bp, u32 addr, const u32 *data,
97 for (i = 0; i < len; i++) {
98 REG_WR(bp, addr + i*4, data[i]);
100 touch_softlockup_watchdog();
106 static void bnx2x_init_ind_wr(struct bnx2x *bp, u32 addr, const u32 *data,
111 for (i = 0; i < len; i++) {
112 REG_WR_IND(bp, addr + i*4, data[i]);
114 touch_softlockup_watchdog();
120 static void bnx2x_init_wr_wb(struct bnx2x *bp, u32 addr, const u32 *data,
131 temp = kmalloc(len, GFP_KERNEL);
132 size = (len / 4) + ((len % 4) ? 1 : 0);
133 for (i = 0; i < size; i++)
134 temp[i] = swab32(data[i]);
137 rc = bnx2x_gunzip(bp, (u8 *)data, len);
139 DP(NETIF_MSG_HW, "gunzip failed ! rc %d\n", rc);
142 len = bp->gunzip_outlen;
145 for (i = 0; i < len; i++)
146 ((u32 *)bp->gunzip_buf)[i] =
147 swab32(((u32 *)bp->gunzip_buf)[i]);
150 if ((len * 4) > FW_BUF_SIZE) {
151 BNX2X_ERR("LARGE DMAE OPERATION ! len 0x%x\n", len*4);
154 memcpy(bp->gunzip_buf, data, len * 4);
157 while (len > DMAE_LEN32_MAX) {
158 bnx2x_write_dmae(bp, bp->gunzip_mapping + offset,
159 addr + offset, DMAE_LEN32_MAX);
160 offset += DMAE_LEN32_MAX * 4;
161 len -= DMAE_LEN32_MAX;
163 bnx2x_write_dmae(bp, bp->gunzip_mapping + offset, addr + offset, len);
166 #define INIT_MEM_WB(reg, data, reg_off, len) \
167 bnx2x_init_wr_wb(bp, reg + reg_off*4, data, len, 0)
169 #define INIT_GUNZIP_DMAE(reg, data, reg_off, len) \
170 bnx2x_init_wr_wb(bp, reg + reg_off*4, data, len, 1)
172 static void bnx2x_init_fill(struct bnx2x *bp, u32 addr, int fill, u32 len)
176 if ((len * 4) > FW_BUF_SIZE) {
177 BNX2X_ERR("LARGE DMAE OPERATION ! len 0x%x\n", len * 4);
180 memset(bp->gunzip_buf, fill, len * 4);
182 while (len > DMAE_LEN32_MAX) {
183 bnx2x_write_dmae(bp, bp->gunzip_mapping + offset,
184 addr + offset, DMAE_LEN32_MAX);
185 offset += DMAE_LEN32_MAX * 4;
186 len -= DMAE_LEN32_MAX;
188 bnx2x_write_dmae(bp, bp->gunzip_mapping + offset, addr + offset, len);
191 static void bnx2x_init_block(struct bnx2x *bp, u32 op_start, u32 op_end)
195 u32 op_type, addr, len;
198 for (i = op_start; i < op_end; i++) {
200 op = (union init_op *)&(init_ops[i]);
202 op_type = op->str_wr.op;
203 addr = op->str_wr.offset;
204 len = op->str_wr.data_len;
205 data = init_data + op->str_wr.data_off;
212 REG_WR(bp, addr, op->write.val);
215 bnx2x_init_str_wr(bp, addr, data, len);
218 bnx2x_init_wr_wb(bp, addr, data, len, 0);
221 bnx2x_init_ind_wr(bp, addr, data, len);
224 bnx2x_init_fill(bp, addr, 0, op->zero.len);
227 bnx2x_init_wr_wb(bp, addr, data, len, 1);
230 BNX2X_ERR("BAD init operation!\n");
236 /****************************************************************************
238 ****************************************************************************/
240 * This code configures the PCI read/write arbiter
241 * which implements a wighted round robin
242 * between the virtual queues in the chip.
244 * The values were derived for each PCI max payload and max request size.
245 * since max payload and max request size are only known at run time,
246 * this is done as a separate init stage.
254 /* configuration for one arbiter queue */
261 /* derived configuration for each read queue for each max request size */
262 static const struct arb_line read_arb_data[NUM_RD_Q][MAX_RD_ORD + 1] = {
263 {{8 , 64 , 25}, {16 , 64 , 25}, {32 , 64 , 25}, {64 , 64 , 41} },
264 {{4 , 8 , 4}, {4 , 8 , 4}, {4 , 8 , 4}, {4 , 8 , 4} },
265 {{4 , 3 , 3}, {4 , 3 , 3}, {4 , 3 , 3}, {4 , 3 , 3} },
266 {{8 , 3 , 6}, {16 , 3 , 11}, {16 , 3 , 11}, {16 , 3 , 11} },
267 {{8 , 64 , 25}, {16 , 64 , 25}, {32 , 64 , 25}, {64 , 64 , 41} },
268 {{8 , 3 , 6}, {16 , 3 , 11}, {32 , 3 , 21}, {64 , 3 , 41} },
269 {{8 , 3 , 6}, {16 , 3 , 11}, {32 , 3 , 21}, {64 , 3 , 41} },
270 {{8 , 3 , 6}, {16 , 3 , 11}, {32 , 3 , 21}, {64 , 3 , 41} },
271 {{8 , 3 , 6}, {16 , 3 , 11}, {32 , 3 , 21}, {64 , 3 , 41} },
272 {{8 , 3 , 6}, {16 , 3 , 11}, {32 , 3 , 21}, {32 , 3 , 21} },
273 {{8 , 3 , 6}, {16 , 3 , 11}, {32 , 3 , 21}, {32 , 3 , 21} },
274 {{8 , 3 , 6}, {16 , 3 , 11}, {32 , 3 , 21}, {32 , 3 , 21} },
275 {{8 , 3 , 6}, {16 , 3 , 11}, {32 , 3 , 21}, {32 , 3 , 21} },
276 {{8 , 3 , 6}, {16 , 3 , 11}, {32 , 3 , 21}, {32 , 3 , 21} },
277 {{8 , 3 , 6}, {16 , 3 , 11}, {32 , 3 , 21}, {32 , 3 , 21} },
278 {{8 , 3 , 6}, {16 , 3 , 11}, {32 , 3 , 21}, {32 , 3 , 21} },
279 {{8 , 3 , 6}, {16 , 3 , 11}, {32 , 3 , 21}, {32 , 3 , 21} },
280 {{8 , 3 , 6}, {16 , 3 , 11}, {32 , 3 , 21}, {32 , 3 , 21} },
281 {{8 , 3 , 6}, {16 , 3 , 11}, {32 , 3 , 21}, {32 , 3 , 21} },
282 {{8 , 3 , 6}, {16 , 3 , 11}, {32 , 3 , 21}, {32 , 3 , 21} },
283 {{8 , 3 , 6}, {16 , 3 , 11}, {32 , 3 , 21}, {32 , 3 , 21} },
284 {{8 , 3 , 6}, {16 , 3 , 11}, {32 , 3 , 21}, {32 , 3 , 21} },
285 {{8 , 3 , 6}, {16 , 3 , 11}, {32 , 3 , 21}, {32 , 3 , 21} },
286 {{8 , 3 , 6}, {16 , 3 , 11}, {32 , 3 , 21}, {32 , 3 , 21} },
287 {{8 , 3 , 6}, {16 , 3 , 11}, {32 , 3 , 21}, {32 , 3 , 21} },
288 {{8 , 3 , 6}, {16 , 3 , 11}, {32 , 3 , 21}, {32 , 3 , 21} },
289 {{8 , 3 , 6}, {16 , 3 , 11}, {32 , 3 , 21}, {32 , 3 , 21} },
290 {{8 , 3 , 6}, {16 , 3 , 11}, {32 , 3 , 21}, {32 , 3 , 21} },
291 {{8 , 64 , 25}, {16 , 64 , 41}, {32 , 64 , 81}, {64 , 64 , 120} }
294 /* derived configuration for each write queue for each max request size */
295 static const struct arb_line write_arb_data[NUM_WR_Q][MAX_WR_ORD + 1] = {
296 {{4 , 6 , 3}, {4 , 6 , 3}, {4 , 6 , 3} },
297 {{4 , 2 , 3}, {4 , 2 , 3}, {4 , 2 , 3} },
298 {{8 , 2 , 6}, {16 , 2 , 11}, {16 , 2 , 11} },
299 {{8 , 2 , 6}, {16 , 2 , 11}, {32 , 2 , 21} },
300 {{8 , 2 , 6}, {16 , 2 , 11}, {32 , 2 , 21} },
301 {{8 , 2 , 6}, {16 , 2 , 11}, {32 , 2 , 21} },
302 {{8 , 64 , 25}, {16 , 64 , 25}, {32 , 64 , 25} },
303 {{8 , 2 , 6}, {16 , 2 , 11}, {16 , 2 , 11} },
304 {{8 , 2 , 6}, {16 , 2 , 11}, {16 , 2 , 11} },
305 {{8 , 9 , 6}, {16 , 9 , 11}, {32 , 9 , 21} },
306 {{8 , 47 , 19}, {16 , 47 , 19}, {32 , 47 , 21} },
307 {{8 , 9 , 6}, {16 , 9 , 11}, {16 , 9 , 11} },
308 {{8 , 64 , 25}, {16 , 64 , 41}, {32 , 64 , 81} }
311 /* register adresses for read queues */
312 static const struct arb_line read_arb_addr[NUM_RD_Q-1] = {
313 {PXP2_REG_RQ_BW_RD_L0, PXP2_REG_RQ_BW_RD_ADD0,
314 PXP2_REG_RQ_BW_RD_UBOUND0},
315 {PXP2_REG_PSWRQ_BW_L1, PXP2_REG_PSWRQ_BW_ADD1,
316 PXP2_REG_PSWRQ_BW_UB1},
317 {PXP2_REG_PSWRQ_BW_L2, PXP2_REG_PSWRQ_BW_ADD2,
318 PXP2_REG_PSWRQ_BW_UB2},
319 {PXP2_REG_PSWRQ_BW_L3, PXP2_REG_PSWRQ_BW_ADD3,
320 PXP2_REG_PSWRQ_BW_UB3},
321 {PXP2_REG_RQ_BW_RD_L4, PXP2_REG_RQ_BW_RD_ADD4,
322 PXP2_REG_RQ_BW_RD_UBOUND4},
323 {PXP2_REG_RQ_BW_RD_L5, PXP2_REG_RQ_BW_RD_ADD5,
324 PXP2_REG_RQ_BW_RD_UBOUND5},
325 {PXP2_REG_PSWRQ_BW_L6, PXP2_REG_PSWRQ_BW_ADD6,
326 PXP2_REG_PSWRQ_BW_UB6},
327 {PXP2_REG_PSWRQ_BW_L7, PXP2_REG_PSWRQ_BW_ADD7,
328 PXP2_REG_PSWRQ_BW_UB7},
329 {PXP2_REG_PSWRQ_BW_L8, PXP2_REG_PSWRQ_BW_ADD8,
330 PXP2_REG_PSWRQ_BW_UB8},
331 {PXP2_REG_PSWRQ_BW_L9, PXP2_REG_PSWRQ_BW_ADD9,
332 PXP2_REG_PSWRQ_BW_UB9},
333 {PXP2_REG_PSWRQ_BW_L10, PXP2_REG_PSWRQ_BW_ADD10,
334 PXP2_REG_PSWRQ_BW_UB10},
335 {PXP2_REG_PSWRQ_BW_L11, PXP2_REG_PSWRQ_BW_ADD11,
336 PXP2_REG_PSWRQ_BW_UB11},
337 {PXP2_REG_RQ_BW_RD_L12, PXP2_REG_RQ_BW_RD_ADD12,
338 PXP2_REG_RQ_BW_RD_UBOUND12},
339 {PXP2_REG_RQ_BW_RD_L13, PXP2_REG_RQ_BW_RD_ADD13,
340 PXP2_REG_RQ_BW_RD_UBOUND13},
341 {PXP2_REG_RQ_BW_RD_L14, PXP2_REG_RQ_BW_RD_ADD14,
342 PXP2_REG_RQ_BW_RD_UBOUND14},
343 {PXP2_REG_RQ_BW_RD_L15, PXP2_REG_RQ_BW_RD_ADD15,
344 PXP2_REG_RQ_BW_RD_UBOUND15},
345 {PXP2_REG_RQ_BW_RD_L16, PXP2_REG_RQ_BW_RD_ADD16,
346 PXP2_REG_RQ_BW_RD_UBOUND16},
347 {PXP2_REG_RQ_BW_RD_L17, PXP2_REG_RQ_BW_RD_ADD17,
348 PXP2_REG_RQ_BW_RD_UBOUND17},
349 {PXP2_REG_RQ_BW_RD_L18, PXP2_REG_RQ_BW_RD_ADD18,
350 PXP2_REG_RQ_BW_RD_UBOUND18},
351 {PXP2_REG_RQ_BW_RD_L19, PXP2_REG_RQ_BW_RD_ADD19,
352 PXP2_REG_RQ_BW_RD_UBOUND19},
353 {PXP2_REG_RQ_BW_RD_L20, PXP2_REG_RQ_BW_RD_ADD20,
354 PXP2_REG_RQ_BW_RD_UBOUND20},
355 {PXP2_REG_RQ_BW_RD_L22, PXP2_REG_RQ_BW_RD_ADD22,
356 PXP2_REG_RQ_BW_RD_UBOUND22},
357 {PXP2_REG_RQ_BW_RD_L23, PXP2_REG_RQ_BW_RD_ADD23,
358 PXP2_REG_RQ_BW_RD_UBOUND23},
359 {PXP2_REG_RQ_BW_RD_L24, PXP2_REG_RQ_BW_RD_ADD24,
360 PXP2_REG_RQ_BW_RD_UBOUND24},
361 {PXP2_REG_RQ_BW_RD_L25, PXP2_REG_RQ_BW_RD_ADD25,
362 PXP2_REG_RQ_BW_RD_UBOUND25},
363 {PXP2_REG_RQ_BW_RD_L26, PXP2_REG_RQ_BW_RD_ADD26,
364 PXP2_REG_RQ_BW_RD_UBOUND26},
365 {PXP2_REG_RQ_BW_RD_L27, PXP2_REG_RQ_BW_RD_ADD27,
366 PXP2_REG_RQ_BW_RD_UBOUND27},
367 {PXP2_REG_PSWRQ_BW_L28, PXP2_REG_PSWRQ_BW_ADD28,
368 PXP2_REG_PSWRQ_BW_UB28}
371 /* register adresses for wrtie queues */
372 static const struct arb_line write_arb_addr[NUM_WR_Q-1] = {
373 {PXP2_REG_PSWRQ_BW_L1, PXP2_REG_PSWRQ_BW_ADD1,
374 PXP2_REG_PSWRQ_BW_UB1},
375 {PXP2_REG_PSWRQ_BW_L2, PXP2_REG_PSWRQ_BW_ADD2,
376 PXP2_REG_PSWRQ_BW_UB2},
377 {PXP2_REG_PSWRQ_BW_L3, PXP2_REG_PSWRQ_BW_ADD3,
378 PXP2_REG_PSWRQ_BW_UB3},
379 {PXP2_REG_PSWRQ_BW_L6, PXP2_REG_PSWRQ_BW_ADD6,
380 PXP2_REG_PSWRQ_BW_UB6},
381 {PXP2_REG_PSWRQ_BW_L7, PXP2_REG_PSWRQ_BW_ADD7,
382 PXP2_REG_PSWRQ_BW_UB7},
383 {PXP2_REG_PSWRQ_BW_L8, PXP2_REG_PSWRQ_BW_ADD8,
384 PXP2_REG_PSWRQ_BW_UB8},
385 {PXP2_REG_PSWRQ_BW_L9, PXP2_REG_PSWRQ_BW_ADD9,
386 PXP2_REG_PSWRQ_BW_UB9},
387 {PXP2_REG_PSWRQ_BW_L10, PXP2_REG_PSWRQ_BW_ADD10,
388 PXP2_REG_PSWRQ_BW_UB10},
389 {PXP2_REG_PSWRQ_BW_L11, PXP2_REG_PSWRQ_BW_ADD11,
390 PXP2_REG_PSWRQ_BW_UB11},
391 {PXP2_REG_PSWRQ_BW_L28, PXP2_REG_PSWRQ_BW_ADD28,
392 PXP2_REG_PSWRQ_BW_UB28},
393 {PXP2_REG_RQ_BW_WR_L29, PXP2_REG_RQ_BW_WR_ADD29,
394 PXP2_REG_RQ_BW_WR_UBOUND29},
395 {PXP2_REG_RQ_BW_WR_L30, PXP2_REG_RQ_BW_WR_ADD30,
396 PXP2_REG_RQ_BW_WR_UBOUND30}
399 static void bnx2x_init_pxp(struct bnx2x *bp)
401 int r_order, w_order;
404 pci_read_config_word(bp->pdev,
405 bp->pcie_cap + PCI_EXP_DEVCTL, (u16 *)&val);
406 DP(NETIF_MSG_HW, "read 0x%x from devctl\n", (u16)val);
407 w_order = ((val & PCI_EXP_DEVCTL_PAYLOAD) >> 5);
408 r_order = ((val & PCI_EXP_DEVCTL_READRQ) >> 12);
410 if (r_order > MAX_RD_ORD) {
411 DP(NETIF_MSG_HW, "read order of %d order adjusted to %d\n",
412 r_order, MAX_RD_ORD);
413 r_order = MAX_RD_ORD;
415 if (w_order > MAX_WR_ORD) {
416 DP(NETIF_MSG_HW, "write order of %d order adjusted to %d\n",
417 w_order, MAX_WR_ORD);
418 w_order = MAX_WR_ORD;
420 DP(NETIF_MSG_HW, "read order %d write order %d\n", r_order, w_order);
422 for (i = 0; i < NUM_RD_Q-1; i++) {
423 REG_WR(bp, read_arb_addr[i].l, read_arb_data[i][r_order].l);
424 REG_WR(bp, read_arb_addr[i].add,
425 read_arb_data[i][r_order].add);
426 REG_WR(bp, read_arb_addr[i].ubound,
427 read_arb_data[i][r_order].ubound);
430 for (i = 0; i < NUM_WR_Q-1; i++) {
431 if ((write_arb_addr[i].l == PXP2_REG_RQ_BW_WR_L29) ||
432 (write_arb_addr[i].l == PXP2_REG_RQ_BW_WR_L30)) {
434 REG_WR(bp, write_arb_addr[i].l,
435 write_arb_data[i][w_order].l);
437 REG_WR(bp, write_arb_addr[i].add,
438 write_arb_data[i][w_order].add);
440 REG_WR(bp, write_arb_addr[i].ubound,
441 write_arb_data[i][w_order].ubound);
444 val = REG_RD(bp, write_arb_addr[i].l);
445 REG_WR(bp, write_arb_addr[i].l,
446 val | (write_arb_data[i][w_order].l << 10));
448 val = REG_RD(bp, write_arb_addr[i].add);
449 REG_WR(bp, write_arb_addr[i].add,
450 val | (write_arb_data[i][w_order].add << 10));
452 val = REG_RD(bp, write_arb_addr[i].ubound);
453 REG_WR(bp, write_arb_addr[i].ubound,
454 val | (write_arb_data[i][w_order].ubound << 7));
458 val = write_arb_data[NUM_WR_Q-1][w_order].add;
459 val += write_arb_data[NUM_WR_Q-1][w_order].ubound << 10;
460 val += write_arb_data[NUM_WR_Q-1][w_order].l << 17;
461 REG_WR(bp, PXP2_REG_PSWRQ_BW_RD, val);
463 val = read_arb_data[NUM_RD_Q-1][r_order].add;
464 val += read_arb_data[NUM_RD_Q-1][r_order].ubound << 10;
465 val += read_arb_data[NUM_RD_Q-1][r_order].l << 17;
466 REG_WR(bp, PXP2_REG_PSWRQ_BW_WR, val);
468 REG_WR(bp, PXP2_REG_RQ_WR_MBS0, w_order);
469 REG_WR(bp, PXP2_REG_RQ_WR_MBS1, w_order);
470 REG_WR(bp, PXP2_REG_RQ_RD_MBS0, r_order);
471 REG_WR(bp, PXP2_REG_RQ_RD_MBS1, r_order);
473 if (r_order == MAX_RD_ORD)
474 REG_WR(bp, PXP2_REG_RQ_PDR_LIMIT, 0xe00);
476 REG_WR(bp, PXP2_REG_WR_USDMDP_TH, (0x18 << w_order));
477 REG_WR(bp, PXP2_REG_WR_DMAE_TH, (128 << w_order)/16);
481 /****************************************************************************
483 ****************************************************************************/
485 #define CDU_REGION_NUMBER_XCM_AG 2
486 #define CDU_REGION_NUMBER_UCM_AG 4
489 * String-to-compress [31:8] = CID (all 24 bits)
490 * String-to-compress [7:4] = Region
491 * String-to-compress [3:0] = Type
493 #define CDU_VALID_DATA(_cid, _region, _type) \
494 (((_cid) << 8) | (((_region) & 0xf) << 4) | (((_type) & 0xf)))
495 #define CDU_CRC8(_cid, _region, _type) \
496 calc_crc8(CDU_VALID_DATA(_cid, _region, _type), 0xff)
497 #define CDU_RSRVD_VALUE_TYPE_A(_cid, _region, _type) \
498 (0x80 | (CDU_CRC8(_cid, _region, _type) & 0x7f))
499 #define CDU_RSRVD_VALUE_TYPE_B(_crc, _type) \
500 (0x80 | ((_type) & 0xf << 3) | (CDU_CRC8(_cid, _region, _type) & 0x7))
501 #define CDU_RSRVD_INVALIDATE_CONTEXT_VALUE(_val) ((_val) & ~0x80)
503 /*****************************************************************************
505 * Calculates crc 8 on a word value: polynomial 0-1-2-8
506 * Code was translated from Verilog.
507 ****************************************************************************/
508 static u8 calc_crc8(u32 data, u8 crc)
516 /* split the data into 31 bits */
517 for (i = 0; i < 32; i++) {
522 /* split the crc into 8 bits */
523 for (i = 0; i < 8; i++) {
528 NewCRC[0] = D[31] ^ D[30] ^ D[28] ^ D[23] ^ D[21] ^ D[19] ^ D[18] ^
529 D[16] ^ D[14] ^ D[12] ^ D[8] ^ D[7] ^ D[6] ^ D[0] ^ C[4] ^
531 NewCRC[1] = D[30] ^ D[29] ^ D[28] ^ D[24] ^ D[23] ^ D[22] ^ D[21] ^
532 D[20] ^ D[18] ^ D[17] ^ D[16] ^ D[15] ^ D[14] ^ D[13] ^
533 D[12] ^ D[9] ^ D[6] ^ D[1] ^ D[0] ^ C[0] ^ C[4] ^ C[5] ^ C[6];
534 NewCRC[2] = D[29] ^ D[28] ^ D[25] ^ D[24] ^ D[22] ^ D[17] ^ D[15] ^
535 D[13] ^ D[12] ^ D[10] ^ D[8] ^ D[6] ^ D[2] ^ D[1] ^ D[0] ^
536 C[0] ^ C[1] ^ C[4] ^ C[5];
537 NewCRC[3] = D[30] ^ D[29] ^ D[26] ^ D[25] ^ D[23] ^ D[18] ^ D[16] ^
538 D[14] ^ D[13] ^ D[11] ^ D[9] ^ D[7] ^ D[3] ^ D[2] ^ D[1] ^
539 C[1] ^ C[2] ^ C[5] ^ C[6];
540 NewCRC[4] = D[31] ^ D[30] ^ D[27] ^ D[26] ^ D[24] ^ D[19] ^ D[17] ^
541 D[15] ^ D[14] ^ D[12] ^ D[10] ^ D[8] ^ D[4] ^ D[3] ^ D[2] ^
542 C[0] ^ C[2] ^ C[3] ^ C[6] ^ C[7];
543 NewCRC[5] = D[31] ^ D[28] ^ D[27] ^ D[25] ^ D[20] ^ D[18] ^ D[16] ^
544 D[15] ^ D[13] ^ D[11] ^ D[9] ^ D[5] ^ D[4] ^ D[3] ^ C[1] ^
546 NewCRC[6] = D[29] ^ D[28] ^ D[26] ^ D[21] ^ D[19] ^ D[17] ^ D[16] ^
547 D[14] ^ D[12] ^ D[10] ^ D[6] ^ D[5] ^ D[4] ^ C[2] ^ C[4] ^
549 NewCRC[7] = D[30] ^ D[29] ^ D[27] ^ D[22] ^ D[20] ^ D[18] ^ D[17] ^
550 D[15] ^ D[13] ^ D[11] ^ D[7] ^ D[6] ^ D[5] ^ C[3] ^ C[5] ^
554 for (i = 0; i < 8; i++)
555 crc_res |= (NewCRC[i] << i);
561 #endif /* BNX2X_INIT_H */