1 /* bnx2.c: Broadcom NX2 network driver.
3 * Copyright (c) 2004-2007 Broadcom Corporation
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation.
9 * Written by: Michael Chan (mchan@broadcom.com)
13 #include <linux/module.h>
14 #include <linux/moduleparam.h>
16 #include <linux/kernel.h>
17 #include <linux/timer.h>
18 #include <linux/errno.h>
19 #include <linux/ioport.h>
20 #include <linux/slab.h>
21 #include <linux/vmalloc.h>
22 #include <linux/interrupt.h>
23 #include <linux/pci.h>
24 #include <linux/init.h>
25 #include <linux/netdevice.h>
26 #include <linux/etherdevice.h>
27 #include <linux/skbuff.h>
28 #include <linux/dma-mapping.h>
29 #include <asm/bitops.h>
32 #include <linux/delay.h>
33 #include <asm/byteorder.h>
35 #include <linux/time.h>
36 #include <linux/ethtool.h>
37 #include <linux/mii.h>
38 #ifdef NETIF_F_HW_VLAN_TX
39 #include <linux/if_vlan.h>
44 #include <net/checksum.h>
45 #include <linux/workqueue.h>
46 #include <linux/crc32.h>
47 #include <linux/prefetch.h>
48 #include <linux/cache.h>
49 #include <linux/zlib.h>
55 #define DRV_MODULE_NAME "bnx2"
56 #define PFX DRV_MODULE_NAME ": "
57 #define DRV_MODULE_VERSION "1.6.2"
58 #define DRV_MODULE_RELDATE "July 6, 2007"
60 #define RUN_AT(x) (jiffies + (x))
62 /* Time in jiffies before concluding the transmitter is hung. */
63 #define TX_TIMEOUT (5*HZ)
65 static const char version[] __devinitdata =
66 "Broadcom NetXtreme II Gigabit Ethernet Driver " DRV_MODULE_NAME " v" DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")\n";
68 MODULE_AUTHOR("Michael Chan <mchan@broadcom.com>");
69 MODULE_DESCRIPTION("Broadcom NetXtreme II BCM5706/5708 Driver");
70 MODULE_LICENSE("GPL");
71 MODULE_VERSION(DRV_MODULE_VERSION);
73 static int disable_msi = 0;
75 module_param(disable_msi, int, 0);
76 MODULE_PARM_DESC(disable_msi, "Disable Message Signaled Interrupt (MSI)");
90 /* indexed by board_t, above */
93 } board_info[] __devinitdata = {
94 { "Broadcom NetXtreme II BCM5706 1000Base-T" },
95 { "HP NC370T Multifunction Gigabit Server Adapter" },
96 { "HP NC370i Multifunction Gigabit Server Adapter" },
97 { "Broadcom NetXtreme II BCM5706 1000Base-SX" },
98 { "HP NC370F Multifunction Gigabit Server Adapter" },
99 { "Broadcom NetXtreme II BCM5708 1000Base-T" },
100 { "Broadcom NetXtreme II BCM5708 1000Base-SX" },
101 { "Broadcom NetXtreme II BCM5709 1000Base-T" },
102 { "Broadcom NetXtreme II BCM5709 1000Base-SX" },
105 static struct pci_device_id bnx2_pci_tbl[] = {
106 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5706,
107 PCI_VENDOR_ID_HP, 0x3101, 0, 0, NC370T },
108 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5706,
109 PCI_VENDOR_ID_HP, 0x3106, 0, 0, NC370I },
110 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5706,
111 PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5706 },
112 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5708,
113 PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5708 },
114 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5706S,
115 PCI_VENDOR_ID_HP, 0x3102, 0, 0, NC370F },
116 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5706S,
117 PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5706S },
118 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5708S,
119 PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5708S },
120 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5709,
121 PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5709 },
122 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5709S,
123 PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5709S },
127 static struct flash_spec flash_table[] =
129 #define BUFFERED_FLAGS (BNX2_NV_BUFFERED | BNX2_NV_TRANSLATE)
130 #define NONBUFFERED_FLAGS (BNX2_NV_WREN)
132 {0x00000000, 0x40830380, 0x009f0081, 0xa184a053, 0xaf000400,
133 BUFFERED_FLAGS, SEEPROM_PAGE_BITS, SEEPROM_PAGE_SIZE,
134 SEEPROM_BYTE_ADDR_MASK, SEEPROM_TOTAL_SIZE,
136 /* Expansion entry 0001 */
137 {0x08000002, 0x4b808201, 0x00050081, 0x03840253, 0xaf020406,
138 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
139 SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
141 /* Saifun SA25F010 (non-buffered flash) */
142 /* strap, cfg1, & write1 need updates */
143 {0x04000001, 0x47808201, 0x00050081, 0x03840253, 0xaf020406,
144 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
145 SAIFUN_FLASH_BYTE_ADDR_MASK, SAIFUN_FLASH_BASE_TOTAL_SIZE*2,
146 "Non-buffered flash (128kB)"},
147 /* Saifun SA25F020 (non-buffered flash) */
148 /* strap, cfg1, & write1 need updates */
149 {0x0c000003, 0x4f808201, 0x00050081, 0x03840253, 0xaf020406,
150 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
151 SAIFUN_FLASH_BYTE_ADDR_MASK, SAIFUN_FLASH_BASE_TOTAL_SIZE*4,
152 "Non-buffered flash (256kB)"},
153 /* Expansion entry 0100 */
154 {0x11000000, 0x53808201, 0x00050081, 0x03840253, 0xaf020406,
155 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
156 SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
158 /* Entry 0101: ST M45PE10 (non-buffered flash, TetonII B0) */
159 {0x19000002, 0x5b808201, 0x000500db, 0x03840253, 0xaf020406,
160 NONBUFFERED_FLAGS, ST_MICRO_FLASH_PAGE_BITS, ST_MICRO_FLASH_PAGE_SIZE,
161 ST_MICRO_FLASH_BYTE_ADDR_MASK, ST_MICRO_FLASH_BASE_TOTAL_SIZE*2,
162 "Entry 0101: ST M45PE10 (128kB non-bufferred)"},
163 /* Entry 0110: ST M45PE20 (non-buffered flash)*/
164 {0x15000001, 0x57808201, 0x000500db, 0x03840253, 0xaf020406,
165 NONBUFFERED_FLAGS, ST_MICRO_FLASH_PAGE_BITS, ST_MICRO_FLASH_PAGE_SIZE,
166 ST_MICRO_FLASH_BYTE_ADDR_MASK, ST_MICRO_FLASH_BASE_TOTAL_SIZE*4,
167 "Entry 0110: ST M45PE20 (256kB non-bufferred)"},
168 /* Saifun SA25F005 (non-buffered flash) */
169 /* strap, cfg1, & write1 need updates */
170 {0x1d000003, 0x5f808201, 0x00050081, 0x03840253, 0xaf020406,
171 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
172 SAIFUN_FLASH_BYTE_ADDR_MASK, SAIFUN_FLASH_BASE_TOTAL_SIZE,
173 "Non-buffered flash (64kB)"},
175 {0x22000000, 0x62808380, 0x009f0081, 0xa184a053, 0xaf000400,
176 BUFFERED_FLAGS, SEEPROM_PAGE_BITS, SEEPROM_PAGE_SIZE,
177 SEEPROM_BYTE_ADDR_MASK, SEEPROM_TOTAL_SIZE,
179 /* Expansion entry 1001 */
180 {0x2a000002, 0x6b808201, 0x00050081, 0x03840253, 0xaf020406,
181 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
182 SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
184 /* Expansion entry 1010 */
185 {0x26000001, 0x67808201, 0x00050081, 0x03840253, 0xaf020406,
186 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
187 SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
189 /* ATMEL AT45DB011B (buffered flash) */
190 {0x2e000003, 0x6e808273, 0x00570081, 0x68848353, 0xaf000400,
191 BUFFERED_FLAGS, BUFFERED_FLASH_PAGE_BITS, BUFFERED_FLASH_PAGE_SIZE,
192 BUFFERED_FLASH_BYTE_ADDR_MASK, BUFFERED_FLASH_TOTAL_SIZE,
193 "Buffered flash (128kB)"},
194 /* Expansion entry 1100 */
195 {0x33000000, 0x73808201, 0x00050081, 0x03840253, 0xaf020406,
196 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
197 SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
199 /* Expansion entry 1101 */
200 {0x3b000002, 0x7b808201, 0x00050081, 0x03840253, 0xaf020406,
201 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
202 SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
204 /* Ateml Expansion entry 1110 */
205 {0x37000001, 0x76808273, 0x00570081, 0x68848353, 0xaf000400,
206 BUFFERED_FLAGS, BUFFERED_FLASH_PAGE_BITS, BUFFERED_FLASH_PAGE_SIZE,
207 BUFFERED_FLASH_BYTE_ADDR_MASK, 0,
208 "Entry 1110 (Atmel)"},
209 /* ATMEL AT45DB021B (buffered flash) */
210 {0x3f000003, 0x7e808273, 0x00570081, 0x68848353, 0xaf000400,
211 BUFFERED_FLAGS, BUFFERED_FLASH_PAGE_BITS, BUFFERED_FLASH_PAGE_SIZE,
212 BUFFERED_FLASH_BYTE_ADDR_MASK, BUFFERED_FLASH_TOTAL_SIZE*2,
213 "Buffered flash (256kB)"},
216 static struct flash_spec flash_5709 = {
217 .flags = BNX2_NV_BUFFERED,
218 .page_bits = BCM5709_FLASH_PAGE_BITS,
219 .page_size = BCM5709_FLASH_PAGE_SIZE,
220 .addr_mask = BCM5709_FLASH_BYTE_ADDR_MASK,
221 .total_size = BUFFERED_FLASH_TOTAL_SIZE*2,
222 .name = "5709 Buffered flash (256kB)",
225 MODULE_DEVICE_TABLE(pci, bnx2_pci_tbl);
227 static inline u32 bnx2_tx_avail(struct bnx2 *bp)
233 /* The ring uses 256 indices for 255 entries, one of them
234 * needs to be skipped.
236 diff = bp->tx_prod - bp->tx_cons;
237 if (unlikely(diff >= TX_DESC_CNT)) {
239 if (diff == TX_DESC_CNT)
240 diff = MAX_TX_DESC_CNT;
242 return (bp->tx_ring_size - diff);
246 bnx2_reg_rd_ind(struct bnx2 *bp, u32 offset)
250 spin_lock_bh(&bp->indirect_lock);
251 REG_WR(bp, BNX2_PCICFG_REG_WINDOW_ADDRESS, offset);
252 val = REG_RD(bp, BNX2_PCICFG_REG_WINDOW);
253 spin_unlock_bh(&bp->indirect_lock);
258 bnx2_reg_wr_ind(struct bnx2 *bp, u32 offset, u32 val)
260 spin_lock_bh(&bp->indirect_lock);
261 REG_WR(bp, BNX2_PCICFG_REG_WINDOW_ADDRESS, offset);
262 REG_WR(bp, BNX2_PCICFG_REG_WINDOW, val);
263 spin_unlock_bh(&bp->indirect_lock);
267 bnx2_ctx_wr(struct bnx2 *bp, u32 cid_addr, u32 offset, u32 val)
270 spin_lock_bh(&bp->indirect_lock);
271 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
274 REG_WR(bp, BNX2_CTX_CTX_DATA, val);
275 REG_WR(bp, BNX2_CTX_CTX_CTRL,
276 offset | BNX2_CTX_CTX_CTRL_WRITE_REQ);
277 for (i = 0; i < 5; i++) {
279 val = REG_RD(bp, BNX2_CTX_CTX_CTRL);
280 if ((val & BNX2_CTX_CTX_CTRL_WRITE_REQ) == 0)
285 REG_WR(bp, BNX2_CTX_DATA_ADR, offset);
286 REG_WR(bp, BNX2_CTX_DATA, val);
288 spin_unlock_bh(&bp->indirect_lock);
292 bnx2_read_phy(struct bnx2 *bp, u32 reg, u32 *val)
297 if (bp->phy_flags & PHY_INT_MODE_AUTO_POLLING_FLAG) {
298 val1 = REG_RD(bp, BNX2_EMAC_MDIO_MODE);
299 val1 &= ~BNX2_EMAC_MDIO_MODE_AUTO_POLL;
301 REG_WR(bp, BNX2_EMAC_MDIO_MODE, val1);
302 REG_RD(bp, BNX2_EMAC_MDIO_MODE);
307 val1 = (bp->phy_addr << 21) | (reg << 16) |
308 BNX2_EMAC_MDIO_COMM_COMMAND_READ | BNX2_EMAC_MDIO_COMM_DISEXT |
309 BNX2_EMAC_MDIO_COMM_START_BUSY;
310 REG_WR(bp, BNX2_EMAC_MDIO_COMM, val1);
312 for (i = 0; i < 50; i++) {
315 val1 = REG_RD(bp, BNX2_EMAC_MDIO_COMM);
316 if (!(val1 & BNX2_EMAC_MDIO_COMM_START_BUSY)) {
319 val1 = REG_RD(bp, BNX2_EMAC_MDIO_COMM);
320 val1 &= BNX2_EMAC_MDIO_COMM_DATA;
326 if (val1 & BNX2_EMAC_MDIO_COMM_START_BUSY) {
335 if (bp->phy_flags & PHY_INT_MODE_AUTO_POLLING_FLAG) {
336 val1 = REG_RD(bp, BNX2_EMAC_MDIO_MODE);
337 val1 |= BNX2_EMAC_MDIO_MODE_AUTO_POLL;
339 REG_WR(bp, BNX2_EMAC_MDIO_MODE, val1);
340 REG_RD(bp, BNX2_EMAC_MDIO_MODE);
349 bnx2_write_phy(struct bnx2 *bp, u32 reg, u32 val)
354 if (bp->phy_flags & PHY_INT_MODE_AUTO_POLLING_FLAG) {
355 val1 = REG_RD(bp, BNX2_EMAC_MDIO_MODE);
356 val1 &= ~BNX2_EMAC_MDIO_MODE_AUTO_POLL;
358 REG_WR(bp, BNX2_EMAC_MDIO_MODE, val1);
359 REG_RD(bp, BNX2_EMAC_MDIO_MODE);
364 val1 = (bp->phy_addr << 21) | (reg << 16) | val |
365 BNX2_EMAC_MDIO_COMM_COMMAND_WRITE |
366 BNX2_EMAC_MDIO_COMM_START_BUSY | BNX2_EMAC_MDIO_COMM_DISEXT;
367 REG_WR(bp, BNX2_EMAC_MDIO_COMM, val1);
369 for (i = 0; i < 50; i++) {
372 val1 = REG_RD(bp, BNX2_EMAC_MDIO_COMM);
373 if (!(val1 & BNX2_EMAC_MDIO_COMM_START_BUSY)) {
379 if (val1 & BNX2_EMAC_MDIO_COMM_START_BUSY)
384 if (bp->phy_flags & PHY_INT_MODE_AUTO_POLLING_FLAG) {
385 val1 = REG_RD(bp, BNX2_EMAC_MDIO_MODE);
386 val1 |= BNX2_EMAC_MDIO_MODE_AUTO_POLL;
388 REG_WR(bp, BNX2_EMAC_MDIO_MODE, val1);
389 REG_RD(bp, BNX2_EMAC_MDIO_MODE);
398 bnx2_disable_int(struct bnx2 *bp)
400 REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD,
401 BNX2_PCICFG_INT_ACK_CMD_MASK_INT);
402 REG_RD(bp, BNX2_PCICFG_INT_ACK_CMD);
406 bnx2_enable_int(struct bnx2 *bp)
408 REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD,
409 BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID |
410 BNX2_PCICFG_INT_ACK_CMD_MASK_INT | bp->last_status_idx);
412 REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD,
413 BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID | bp->last_status_idx);
415 REG_WR(bp, BNX2_HC_COMMAND, bp->hc_cmd | BNX2_HC_COMMAND_COAL_NOW);
419 bnx2_disable_int_sync(struct bnx2 *bp)
421 atomic_inc(&bp->intr_sem);
422 bnx2_disable_int(bp);
423 synchronize_irq(bp->pdev->irq);
427 bnx2_netif_stop(struct bnx2 *bp)
429 bnx2_disable_int_sync(bp);
430 if (netif_running(bp->dev)) {
431 netif_poll_disable(bp->dev);
432 netif_tx_disable(bp->dev);
433 bp->dev->trans_start = jiffies; /* prevent tx timeout */
438 bnx2_netif_start(struct bnx2 *bp)
440 if (atomic_dec_and_test(&bp->intr_sem)) {
441 if (netif_running(bp->dev)) {
442 netif_wake_queue(bp->dev);
443 netif_poll_enable(bp->dev);
450 bnx2_free_mem(struct bnx2 *bp)
454 for (i = 0; i < bp->ctx_pages; i++) {
455 if (bp->ctx_blk[i]) {
456 pci_free_consistent(bp->pdev, BCM_PAGE_SIZE,
458 bp->ctx_blk_mapping[i]);
459 bp->ctx_blk[i] = NULL;
462 if (bp->status_blk) {
463 pci_free_consistent(bp->pdev, bp->status_stats_size,
464 bp->status_blk, bp->status_blk_mapping);
465 bp->status_blk = NULL;
466 bp->stats_blk = NULL;
468 if (bp->tx_desc_ring) {
469 pci_free_consistent(bp->pdev,
470 sizeof(struct tx_bd) * TX_DESC_CNT,
471 bp->tx_desc_ring, bp->tx_desc_mapping);
472 bp->tx_desc_ring = NULL;
474 kfree(bp->tx_buf_ring);
475 bp->tx_buf_ring = NULL;
476 for (i = 0; i < bp->rx_max_ring; i++) {
477 if (bp->rx_desc_ring[i])
478 pci_free_consistent(bp->pdev,
479 sizeof(struct rx_bd) * RX_DESC_CNT,
481 bp->rx_desc_mapping[i]);
482 bp->rx_desc_ring[i] = NULL;
484 vfree(bp->rx_buf_ring);
485 bp->rx_buf_ring = NULL;
489 bnx2_alloc_mem(struct bnx2 *bp)
491 int i, status_blk_size;
493 bp->tx_buf_ring = kzalloc(sizeof(struct sw_bd) * TX_DESC_CNT,
495 if (bp->tx_buf_ring == NULL)
498 bp->tx_desc_ring = pci_alloc_consistent(bp->pdev,
499 sizeof(struct tx_bd) *
501 &bp->tx_desc_mapping);
502 if (bp->tx_desc_ring == NULL)
505 bp->rx_buf_ring = vmalloc(sizeof(struct sw_bd) * RX_DESC_CNT *
507 if (bp->rx_buf_ring == NULL)
510 memset(bp->rx_buf_ring, 0, sizeof(struct sw_bd) * RX_DESC_CNT *
513 for (i = 0; i < bp->rx_max_ring; i++) {
514 bp->rx_desc_ring[i] =
515 pci_alloc_consistent(bp->pdev,
516 sizeof(struct rx_bd) * RX_DESC_CNT,
517 &bp->rx_desc_mapping[i]);
518 if (bp->rx_desc_ring[i] == NULL)
523 /* Combine status and statistics blocks into one allocation. */
524 status_blk_size = L1_CACHE_ALIGN(sizeof(struct status_block));
525 bp->status_stats_size = status_blk_size +
526 sizeof(struct statistics_block);
528 bp->status_blk = pci_alloc_consistent(bp->pdev, bp->status_stats_size,
529 &bp->status_blk_mapping);
530 if (bp->status_blk == NULL)
533 memset(bp->status_blk, 0, bp->status_stats_size);
535 bp->stats_blk = (void *) ((unsigned long) bp->status_blk +
538 bp->stats_blk_mapping = bp->status_blk_mapping + status_blk_size;
540 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
541 bp->ctx_pages = 0x2000 / BCM_PAGE_SIZE;
542 if (bp->ctx_pages == 0)
544 for (i = 0; i < bp->ctx_pages; i++) {
545 bp->ctx_blk[i] = pci_alloc_consistent(bp->pdev,
547 &bp->ctx_blk_mapping[i]);
548 if (bp->ctx_blk[i] == NULL)
560 bnx2_report_fw_link(struct bnx2 *bp)
562 u32 fw_link_status = 0;
564 if (bp->phy_flags & REMOTE_PHY_CAP_FLAG)
570 switch (bp->line_speed) {
572 if (bp->duplex == DUPLEX_HALF)
573 fw_link_status = BNX2_LINK_STATUS_10HALF;
575 fw_link_status = BNX2_LINK_STATUS_10FULL;
578 if (bp->duplex == DUPLEX_HALF)
579 fw_link_status = BNX2_LINK_STATUS_100HALF;
581 fw_link_status = BNX2_LINK_STATUS_100FULL;
584 if (bp->duplex == DUPLEX_HALF)
585 fw_link_status = BNX2_LINK_STATUS_1000HALF;
587 fw_link_status = BNX2_LINK_STATUS_1000FULL;
590 if (bp->duplex == DUPLEX_HALF)
591 fw_link_status = BNX2_LINK_STATUS_2500HALF;
593 fw_link_status = BNX2_LINK_STATUS_2500FULL;
597 fw_link_status |= BNX2_LINK_STATUS_LINK_UP;
600 fw_link_status |= BNX2_LINK_STATUS_AN_ENABLED;
602 bnx2_read_phy(bp, bp->mii_bmsr, &bmsr);
603 bnx2_read_phy(bp, bp->mii_bmsr, &bmsr);
605 if (!(bmsr & BMSR_ANEGCOMPLETE) ||
606 bp->phy_flags & PHY_PARALLEL_DETECT_FLAG)
607 fw_link_status |= BNX2_LINK_STATUS_PARALLEL_DET;
609 fw_link_status |= BNX2_LINK_STATUS_AN_COMPLETE;
613 fw_link_status = BNX2_LINK_STATUS_LINK_DOWN;
615 REG_WR_IND(bp, bp->shmem_base + BNX2_LINK_STATUS, fw_link_status);
619 bnx2_xceiver_str(struct bnx2 *bp)
621 return ((bp->phy_port == PORT_FIBRE) ? "SerDes" :
622 ((bp->phy_flags & PHY_SERDES_FLAG) ? "Remote Copper" :
627 bnx2_report_link(struct bnx2 *bp)
630 netif_carrier_on(bp->dev);
631 printk(KERN_INFO PFX "%s NIC %s Link is Up, ", bp->dev->name,
632 bnx2_xceiver_str(bp));
634 printk("%d Mbps ", bp->line_speed);
636 if (bp->duplex == DUPLEX_FULL)
637 printk("full duplex");
639 printk("half duplex");
642 if (bp->flow_ctrl & FLOW_CTRL_RX) {
643 printk(", receive ");
644 if (bp->flow_ctrl & FLOW_CTRL_TX)
645 printk("& transmit ");
648 printk(", transmit ");
650 printk("flow control ON");
655 netif_carrier_off(bp->dev);
656 printk(KERN_ERR PFX "%s NIC %s Link is Down\n", bp->dev->name,
657 bnx2_xceiver_str(bp));
660 bnx2_report_fw_link(bp);
664 bnx2_resolve_flow_ctrl(struct bnx2 *bp)
666 u32 local_adv, remote_adv;
669 if ((bp->autoneg & (AUTONEG_SPEED | AUTONEG_FLOW_CTRL)) !=
670 (AUTONEG_SPEED | AUTONEG_FLOW_CTRL)) {
672 if (bp->duplex == DUPLEX_FULL) {
673 bp->flow_ctrl = bp->req_flow_ctrl;
678 if (bp->duplex != DUPLEX_FULL) {
682 if ((bp->phy_flags & PHY_SERDES_FLAG) &&
683 (CHIP_NUM(bp) == CHIP_NUM_5708)) {
686 bnx2_read_phy(bp, BCM5708S_1000X_STAT1, &val);
687 if (val & BCM5708S_1000X_STAT1_TX_PAUSE)
688 bp->flow_ctrl |= FLOW_CTRL_TX;
689 if (val & BCM5708S_1000X_STAT1_RX_PAUSE)
690 bp->flow_ctrl |= FLOW_CTRL_RX;
694 bnx2_read_phy(bp, bp->mii_adv, &local_adv);
695 bnx2_read_phy(bp, bp->mii_lpa, &remote_adv);
697 if (bp->phy_flags & PHY_SERDES_FLAG) {
698 u32 new_local_adv = 0;
699 u32 new_remote_adv = 0;
701 if (local_adv & ADVERTISE_1000XPAUSE)
702 new_local_adv |= ADVERTISE_PAUSE_CAP;
703 if (local_adv & ADVERTISE_1000XPSE_ASYM)
704 new_local_adv |= ADVERTISE_PAUSE_ASYM;
705 if (remote_adv & ADVERTISE_1000XPAUSE)
706 new_remote_adv |= ADVERTISE_PAUSE_CAP;
707 if (remote_adv & ADVERTISE_1000XPSE_ASYM)
708 new_remote_adv |= ADVERTISE_PAUSE_ASYM;
710 local_adv = new_local_adv;
711 remote_adv = new_remote_adv;
714 /* See Table 28B-3 of 802.3ab-1999 spec. */
715 if (local_adv & ADVERTISE_PAUSE_CAP) {
716 if(local_adv & ADVERTISE_PAUSE_ASYM) {
717 if (remote_adv & ADVERTISE_PAUSE_CAP) {
718 bp->flow_ctrl = FLOW_CTRL_TX | FLOW_CTRL_RX;
720 else if (remote_adv & ADVERTISE_PAUSE_ASYM) {
721 bp->flow_ctrl = FLOW_CTRL_RX;
725 if (remote_adv & ADVERTISE_PAUSE_CAP) {
726 bp->flow_ctrl = FLOW_CTRL_TX | FLOW_CTRL_RX;
730 else if (local_adv & ADVERTISE_PAUSE_ASYM) {
731 if ((remote_adv & ADVERTISE_PAUSE_CAP) &&
732 (remote_adv & ADVERTISE_PAUSE_ASYM)) {
734 bp->flow_ctrl = FLOW_CTRL_TX;
740 bnx2_5709s_linkup(struct bnx2 *bp)
746 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_GP_STATUS);
747 bnx2_read_phy(bp, MII_BNX2_GP_TOP_AN_STATUS1, &val);
748 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_COMBO_IEEEB0);
750 if ((bp->autoneg & AUTONEG_SPEED) == 0) {
751 bp->line_speed = bp->req_line_speed;
752 bp->duplex = bp->req_duplex;
755 speed = val & MII_BNX2_GP_TOP_AN_SPEED_MSK;
757 case MII_BNX2_GP_TOP_AN_SPEED_10:
758 bp->line_speed = SPEED_10;
760 case MII_BNX2_GP_TOP_AN_SPEED_100:
761 bp->line_speed = SPEED_100;
763 case MII_BNX2_GP_TOP_AN_SPEED_1G:
764 case MII_BNX2_GP_TOP_AN_SPEED_1GKV:
765 bp->line_speed = SPEED_1000;
767 case MII_BNX2_GP_TOP_AN_SPEED_2_5G:
768 bp->line_speed = SPEED_2500;
771 if (val & MII_BNX2_GP_TOP_AN_FD)
772 bp->duplex = DUPLEX_FULL;
774 bp->duplex = DUPLEX_HALF;
779 bnx2_5708s_linkup(struct bnx2 *bp)
784 bnx2_read_phy(bp, BCM5708S_1000X_STAT1, &val);
785 switch (val & BCM5708S_1000X_STAT1_SPEED_MASK) {
786 case BCM5708S_1000X_STAT1_SPEED_10:
787 bp->line_speed = SPEED_10;
789 case BCM5708S_1000X_STAT1_SPEED_100:
790 bp->line_speed = SPEED_100;
792 case BCM5708S_1000X_STAT1_SPEED_1G:
793 bp->line_speed = SPEED_1000;
795 case BCM5708S_1000X_STAT1_SPEED_2G5:
796 bp->line_speed = SPEED_2500;
799 if (val & BCM5708S_1000X_STAT1_FD)
800 bp->duplex = DUPLEX_FULL;
802 bp->duplex = DUPLEX_HALF;
808 bnx2_5706s_linkup(struct bnx2 *bp)
810 u32 bmcr, local_adv, remote_adv, common;
813 bp->line_speed = SPEED_1000;
815 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
816 if (bmcr & BMCR_FULLDPLX) {
817 bp->duplex = DUPLEX_FULL;
820 bp->duplex = DUPLEX_HALF;
823 if (!(bmcr & BMCR_ANENABLE)) {
827 bnx2_read_phy(bp, bp->mii_adv, &local_adv);
828 bnx2_read_phy(bp, bp->mii_lpa, &remote_adv);
830 common = local_adv & remote_adv;
831 if (common & (ADVERTISE_1000XHALF | ADVERTISE_1000XFULL)) {
833 if (common & ADVERTISE_1000XFULL) {
834 bp->duplex = DUPLEX_FULL;
837 bp->duplex = DUPLEX_HALF;
845 bnx2_copper_linkup(struct bnx2 *bp)
849 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
850 if (bmcr & BMCR_ANENABLE) {
851 u32 local_adv, remote_adv, common;
853 bnx2_read_phy(bp, MII_CTRL1000, &local_adv);
854 bnx2_read_phy(bp, MII_STAT1000, &remote_adv);
856 common = local_adv & (remote_adv >> 2);
857 if (common & ADVERTISE_1000FULL) {
858 bp->line_speed = SPEED_1000;
859 bp->duplex = DUPLEX_FULL;
861 else if (common & ADVERTISE_1000HALF) {
862 bp->line_speed = SPEED_1000;
863 bp->duplex = DUPLEX_HALF;
866 bnx2_read_phy(bp, bp->mii_adv, &local_adv);
867 bnx2_read_phy(bp, bp->mii_lpa, &remote_adv);
869 common = local_adv & remote_adv;
870 if (common & ADVERTISE_100FULL) {
871 bp->line_speed = SPEED_100;
872 bp->duplex = DUPLEX_FULL;
874 else if (common & ADVERTISE_100HALF) {
875 bp->line_speed = SPEED_100;
876 bp->duplex = DUPLEX_HALF;
878 else if (common & ADVERTISE_10FULL) {
879 bp->line_speed = SPEED_10;
880 bp->duplex = DUPLEX_FULL;
882 else if (common & ADVERTISE_10HALF) {
883 bp->line_speed = SPEED_10;
884 bp->duplex = DUPLEX_HALF;
893 if (bmcr & BMCR_SPEED100) {
894 bp->line_speed = SPEED_100;
897 bp->line_speed = SPEED_10;
899 if (bmcr & BMCR_FULLDPLX) {
900 bp->duplex = DUPLEX_FULL;
903 bp->duplex = DUPLEX_HALF;
911 bnx2_set_mac_link(struct bnx2 *bp)
915 REG_WR(bp, BNX2_EMAC_TX_LENGTHS, 0x2620);
916 if (bp->link_up && (bp->line_speed == SPEED_1000) &&
917 (bp->duplex == DUPLEX_HALF)) {
918 REG_WR(bp, BNX2_EMAC_TX_LENGTHS, 0x26ff);
921 /* Configure the EMAC mode register. */
922 val = REG_RD(bp, BNX2_EMAC_MODE);
924 val &= ~(BNX2_EMAC_MODE_PORT | BNX2_EMAC_MODE_HALF_DUPLEX |
925 BNX2_EMAC_MODE_MAC_LOOP | BNX2_EMAC_MODE_FORCE_LINK |
926 BNX2_EMAC_MODE_25G_MODE);
929 switch (bp->line_speed) {
931 if (CHIP_NUM(bp) != CHIP_NUM_5706) {
932 val |= BNX2_EMAC_MODE_PORT_MII_10M;
937 val |= BNX2_EMAC_MODE_PORT_MII;
940 val |= BNX2_EMAC_MODE_25G_MODE;
943 val |= BNX2_EMAC_MODE_PORT_GMII;
948 val |= BNX2_EMAC_MODE_PORT_GMII;
951 /* Set the MAC to operate in the appropriate duplex mode. */
952 if (bp->duplex == DUPLEX_HALF)
953 val |= BNX2_EMAC_MODE_HALF_DUPLEX;
954 REG_WR(bp, BNX2_EMAC_MODE, val);
956 /* Enable/disable rx PAUSE. */
957 bp->rx_mode &= ~BNX2_EMAC_RX_MODE_FLOW_EN;
959 if (bp->flow_ctrl & FLOW_CTRL_RX)
960 bp->rx_mode |= BNX2_EMAC_RX_MODE_FLOW_EN;
961 REG_WR(bp, BNX2_EMAC_RX_MODE, bp->rx_mode);
963 /* Enable/disable tx PAUSE. */
964 val = REG_RD(bp, BNX2_EMAC_TX_MODE);
965 val &= ~BNX2_EMAC_TX_MODE_FLOW_EN;
967 if (bp->flow_ctrl & FLOW_CTRL_TX)
968 val |= BNX2_EMAC_TX_MODE_FLOW_EN;
969 REG_WR(bp, BNX2_EMAC_TX_MODE, val);
971 /* Acknowledge the interrupt. */
972 REG_WR(bp, BNX2_EMAC_STATUS, BNX2_EMAC_STATUS_LINK_CHANGE);
978 bnx2_enable_bmsr1(struct bnx2 *bp)
980 if ((bp->phy_flags & PHY_SERDES_FLAG) &&
981 (CHIP_NUM(bp) == CHIP_NUM_5709))
982 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR,
983 MII_BNX2_BLK_ADDR_GP_STATUS);
987 bnx2_disable_bmsr1(struct bnx2 *bp)
989 if ((bp->phy_flags & PHY_SERDES_FLAG) &&
990 (CHIP_NUM(bp) == CHIP_NUM_5709))
991 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR,
992 MII_BNX2_BLK_ADDR_COMBO_IEEEB0);
996 bnx2_test_and_enable_2g5(struct bnx2 *bp)
1001 if (!(bp->phy_flags & PHY_2_5G_CAPABLE_FLAG))
1004 if (bp->autoneg & AUTONEG_SPEED)
1005 bp->advertising |= ADVERTISED_2500baseX_Full;
1007 if (CHIP_NUM(bp) == CHIP_NUM_5709)
1008 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_OVER1G);
1010 bnx2_read_phy(bp, bp->mii_up1, &up1);
1011 if (!(up1 & BCM5708S_UP1_2G5)) {
1012 up1 |= BCM5708S_UP1_2G5;
1013 bnx2_write_phy(bp, bp->mii_up1, up1);
1017 if (CHIP_NUM(bp) == CHIP_NUM_5709)
1018 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR,
1019 MII_BNX2_BLK_ADDR_COMBO_IEEEB0);
1025 bnx2_test_and_disable_2g5(struct bnx2 *bp)
1030 if (!(bp->phy_flags & PHY_2_5G_CAPABLE_FLAG))
1033 if (CHIP_NUM(bp) == CHIP_NUM_5709)
1034 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_OVER1G);
1036 bnx2_read_phy(bp, bp->mii_up1, &up1);
1037 if (up1 & BCM5708S_UP1_2G5) {
1038 up1 &= ~BCM5708S_UP1_2G5;
1039 bnx2_write_phy(bp, bp->mii_up1, up1);
1043 if (CHIP_NUM(bp) == CHIP_NUM_5709)
1044 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR,
1045 MII_BNX2_BLK_ADDR_COMBO_IEEEB0);
1051 bnx2_enable_forced_2g5(struct bnx2 *bp)
1055 if (!(bp->phy_flags & PHY_2_5G_CAPABLE_FLAG))
1058 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
1061 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR,
1062 MII_BNX2_BLK_ADDR_SERDES_DIG);
1063 bnx2_read_phy(bp, MII_BNX2_SERDES_DIG_MISC1, &val);
1064 val &= ~MII_BNX2_SD_MISC1_FORCE_MSK;
1065 val |= MII_BNX2_SD_MISC1_FORCE | MII_BNX2_SD_MISC1_FORCE_2_5G;
1066 bnx2_write_phy(bp, MII_BNX2_SERDES_DIG_MISC1, val);
1068 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR,
1069 MII_BNX2_BLK_ADDR_COMBO_IEEEB0);
1070 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
1072 } else if (CHIP_NUM(bp) == CHIP_NUM_5708) {
1073 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
1074 bmcr |= BCM5708S_BMCR_FORCE_2500;
1077 if (bp->autoneg & AUTONEG_SPEED) {
1078 bmcr &= ~BMCR_ANENABLE;
1079 if (bp->req_duplex == DUPLEX_FULL)
1080 bmcr |= BMCR_FULLDPLX;
1082 bnx2_write_phy(bp, bp->mii_bmcr, bmcr);
1086 bnx2_disable_forced_2g5(struct bnx2 *bp)
1090 if (!(bp->phy_flags & PHY_2_5G_CAPABLE_FLAG))
1093 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
1096 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR,
1097 MII_BNX2_BLK_ADDR_SERDES_DIG);
1098 bnx2_read_phy(bp, MII_BNX2_SERDES_DIG_MISC1, &val);
1099 val &= ~MII_BNX2_SD_MISC1_FORCE;
1100 bnx2_write_phy(bp, MII_BNX2_SERDES_DIG_MISC1, val);
1102 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR,
1103 MII_BNX2_BLK_ADDR_COMBO_IEEEB0);
1104 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
1106 } else if (CHIP_NUM(bp) == CHIP_NUM_5708) {
1107 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
1108 bmcr &= ~BCM5708S_BMCR_FORCE_2500;
1111 if (bp->autoneg & AUTONEG_SPEED)
1112 bmcr |= BMCR_SPEED1000 | BMCR_ANENABLE | BMCR_ANRESTART;
1113 bnx2_write_phy(bp, bp->mii_bmcr, bmcr);
1117 bnx2_set_link(struct bnx2 *bp)
1122 if (bp->loopback == MAC_LOOPBACK || bp->loopback == PHY_LOOPBACK) {
1127 if (bp->phy_flags & REMOTE_PHY_CAP_FLAG)
1130 link_up = bp->link_up;
1132 bnx2_enable_bmsr1(bp);
1133 bnx2_read_phy(bp, bp->mii_bmsr1, &bmsr);
1134 bnx2_read_phy(bp, bp->mii_bmsr1, &bmsr);
1135 bnx2_disable_bmsr1(bp);
1137 if ((bp->phy_flags & PHY_SERDES_FLAG) &&
1138 (CHIP_NUM(bp) == CHIP_NUM_5706)) {
1141 val = REG_RD(bp, BNX2_EMAC_STATUS);
1142 if (val & BNX2_EMAC_STATUS_LINK)
1143 bmsr |= BMSR_LSTATUS;
1145 bmsr &= ~BMSR_LSTATUS;
1148 if (bmsr & BMSR_LSTATUS) {
1151 if (bp->phy_flags & PHY_SERDES_FLAG) {
1152 if (CHIP_NUM(bp) == CHIP_NUM_5706)
1153 bnx2_5706s_linkup(bp);
1154 else if (CHIP_NUM(bp) == CHIP_NUM_5708)
1155 bnx2_5708s_linkup(bp);
1156 else if (CHIP_NUM(bp) == CHIP_NUM_5709)
1157 bnx2_5709s_linkup(bp);
1160 bnx2_copper_linkup(bp);
1162 bnx2_resolve_flow_ctrl(bp);
1165 if ((bp->phy_flags & PHY_SERDES_FLAG) &&
1166 (bp->autoneg & AUTONEG_SPEED))
1167 bnx2_disable_forced_2g5(bp);
1169 bp->phy_flags &= ~PHY_PARALLEL_DETECT_FLAG;
1173 if (bp->link_up != link_up) {
1174 bnx2_report_link(bp);
1177 bnx2_set_mac_link(bp);
1183 bnx2_reset_phy(struct bnx2 *bp)
1188 bnx2_write_phy(bp, bp->mii_bmcr, BMCR_RESET);
1190 #define PHY_RESET_MAX_WAIT 100
1191 for (i = 0; i < PHY_RESET_MAX_WAIT; i++) {
1194 bnx2_read_phy(bp, bp->mii_bmcr, ®);
1195 if (!(reg & BMCR_RESET)) {
1200 if (i == PHY_RESET_MAX_WAIT) {
1207 bnx2_phy_get_pause_adv(struct bnx2 *bp)
1211 if ((bp->req_flow_ctrl & (FLOW_CTRL_RX | FLOW_CTRL_TX)) ==
1212 (FLOW_CTRL_RX | FLOW_CTRL_TX)) {
1214 if (bp->phy_flags & PHY_SERDES_FLAG) {
1215 adv = ADVERTISE_1000XPAUSE;
1218 adv = ADVERTISE_PAUSE_CAP;
1221 else if (bp->req_flow_ctrl & FLOW_CTRL_TX) {
1222 if (bp->phy_flags & PHY_SERDES_FLAG) {
1223 adv = ADVERTISE_1000XPSE_ASYM;
1226 adv = ADVERTISE_PAUSE_ASYM;
1229 else if (bp->req_flow_ctrl & FLOW_CTRL_RX) {
1230 if (bp->phy_flags & PHY_SERDES_FLAG) {
1231 adv = ADVERTISE_1000XPAUSE | ADVERTISE_1000XPSE_ASYM;
1234 adv = ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
1240 static int bnx2_fw_sync(struct bnx2 *, u32, int);
1243 bnx2_setup_remote_phy(struct bnx2 *bp, u8 port)
1245 u32 speed_arg = 0, pause_adv;
1247 pause_adv = bnx2_phy_get_pause_adv(bp);
1249 if (bp->autoneg & AUTONEG_SPEED) {
1250 speed_arg |= BNX2_NETLINK_SET_LINK_ENABLE_AUTONEG;
1251 if (bp->advertising & ADVERTISED_10baseT_Half)
1252 speed_arg |= BNX2_NETLINK_SET_LINK_SPEED_10HALF;
1253 if (bp->advertising & ADVERTISED_10baseT_Full)
1254 speed_arg |= BNX2_NETLINK_SET_LINK_SPEED_10FULL;
1255 if (bp->advertising & ADVERTISED_100baseT_Half)
1256 speed_arg |= BNX2_NETLINK_SET_LINK_SPEED_100HALF;
1257 if (bp->advertising & ADVERTISED_100baseT_Full)
1258 speed_arg |= BNX2_NETLINK_SET_LINK_SPEED_100FULL;
1259 if (bp->advertising & ADVERTISED_1000baseT_Full)
1260 speed_arg |= BNX2_NETLINK_SET_LINK_SPEED_1GFULL;
1261 if (bp->advertising & ADVERTISED_2500baseX_Full)
1262 speed_arg |= BNX2_NETLINK_SET_LINK_SPEED_2G5FULL;
1264 if (bp->req_line_speed == SPEED_2500)
1265 speed_arg = BNX2_NETLINK_SET_LINK_SPEED_2G5FULL;
1266 else if (bp->req_line_speed == SPEED_1000)
1267 speed_arg = BNX2_NETLINK_SET_LINK_SPEED_1GFULL;
1268 else if (bp->req_line_speed == SPEED_100) {
1269 if (bp->req_duplex == DUPLEX_FULL)
1270 speed_arg = BNX2_NETLINK_SET_LINK_SPEED_100FULL;
1272 speed_arg = BNX2_NETLINK_SET_LINK_SPEED_100HALF;
1273 } else if (bp->req_line_speed == SPEED_10) {
1274 if (bp->req_duplex == DUPLEX_FULL)
1275 speed_arg = BNX2_NETLINK_SET_LINK_SPEED_10FULL;
1277 speed_arg = BNX2_NETLINK_SET_LINK_SPEED_10HALF;
1281 if (pause_adv & (ADVERTISE_1000XPAUSE | ADVERTISE_PAUSE_CAP))
1282 speed_arg |= BNX2_NETLINK_SET_LINK_FC_SYM_PAUSE;
1283 if (pause_adv & (ADVERTISE_1000XPSE_ASYM | ADVERTISE_1000XPSE_ASYM))
1284 speed_arg |= BNX2_NETLINK_SET_LINK_FC_ASYM_PAUSE;
1286 if (port == PORT_TP)
1287 speed_arg |= BNX2_NETLINK_SET_LINK_PHY_APP_REMOTE |
1288 BNX2_NETLINK_SET_LINK_ETH_AT_WIRESPEED;
1290 REG_WR_IND(bp, bp->shmem_base + BNX2_DRV_MB_ARG0, speed_arg);
1292 spin_unlock_bh(&bp->phy_lock);
1293 bnx2_fw_sync(bp, BNX2_DRV_MSG_CODE_CMD_SET_LINK, 0);
1294 spin_lock_bh(&bp->phy_lock);
1300 bnx2_setup_serdes_phy(struct bnx2 *bp, u8 port)
1305 if (bp->phy_flags & REMOTE_PHY_CAP_FLAG)
1306 return (bnx2_setup_remote_phy(bp, port));
1308 if (!(bp->autoneg & AUTONEG_SPEED)) {
1310 int force_link_down = 0;
1312 if (bp->req_line_speed == SPEED_2500) {
1313 if (!bnx2_test_and_enable_2g5(bp))
1314 force_link_down = 1;
1315 } else if (bp->req_line_speed == SPEED_1000) {
1316 if (bnx2_test_and_disable_2g5(bp))
1317 force_link_down = 1;
1319 bnx2_read_phy(bp, bp->mii_adv, &adv);
1320 adv &= ~(ADVERTISE_1000XFULL | ADVERTISE_1000XHALF);
1322 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
1323 new_bmcr = bmcr & ~BMCR_ANENABLE;
1324 new_bmcr |= BMCR_SPEED1000;
1326 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
1327 if (bp->req_line_speed == SPEED_2500)
1328 bnx2_enable_forced_2g5(bp);
1329 else if (bp->req_line_speed == SPEED_1000) {
1330 bnx2_disable_forced_2g5(bp);
1331 new_bmcr &= ~0x2000;
1334 } else if (CHIP_NUM(bp) == CHIP_NUM_5708) {
1335 if (bp->req_line_speed == SPEED_2500)
1336 new_bmcr |= BCM5708S_BMCR_FORCE_2500;
1338 new_bmcr = bmcr & ~BCM5708S_BMCR_FORCE_2500;
1341 if (bp->req_duplex == DUPLEX_FULL) {
1342 adv |= ADVERTISE_1000XFULL;
1343 new_bmcr |= BMCR_FULLDPLX;
1346 adv |= ADVERTISE_1000XHALF;
1347 new_bmcr &= ~BMCR_FULLDPLX;
1349 if ((new_bmcr != bmcr) || (force_link_down)) {
1350 /* Force a link down visible on the other side */
1352 bnx2_write_phy(bp, bp->mii_adv, adv &
1353 ~(ADVERTISE_1000XFULL |
1354 ADVERTISE_1000XHALF));
1355 bnx2_write_phy(bp, bp->mii_bmcr, bmcr |
1356 BMCR_ANRESTART | BMCR_ANENABLE);
1359 netif_carrier_off(bp->dev);
1360 bnx2_write_phy(bp, bp->mii_bmcr, new_bmcr);
1361 bnx2_report_link(bp);
1363 bnx2_write_phy(bp, bp->mii_adv, adv);
1364 bnx2_write_phy(bp, bp->mii_bmcr, new_bmcr);
1366 bnx2_resolve_flow_ctrl(bp);
1367 bnx2_set_mac_link(bp);
1372 bnx2_test_and_enable_2g5(bp);
1374 if (bp->advertising & ADVERTISED_1000baseT_Full)
1375 new_adv |= ADVERTISE_1000XFULL;
1377 new_adv |= bnx2_phy_get_pause_adv(bp);
1379 bnx2_read_phy(bp, bp->mii_adv, &adv);
1380 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
1382 bp->serdes_an_pending = 0;
1383 if ((adv != new_adv) || ((bmcr & BMCR_ANENABLE) == 0)) {
1384 /* Force a link down visible on the other side */
1386 bnx2_write_phy(bp, bp->mii_bmcr, BMCR_LOOPBACK);
1387 spin_unlock_bh(&bp->phy_lock);
1389 spin_lock_bh(&bp->phy_lock);
1392 bnx2_write_phy(bp, bp->mii_adv, new_adv);
1393 bnx2_write_phy(bp, bp->mii_bmcr, bmcr | BMCR_ANRESTART |
1395 /* Speed up link-up time when the link partner
1396 * does not autonegotiate which is very common
1397 * in blade servers. Some blade servers use
1398 * IPMI for kerboard input and it's important
1399 * to minimize link disruptions. Autoneg. involves
1400 * exchanging base pages plus 3 next pages and
1401 * normally completes in about 120 msec.
1403 bp->current_interval = SERDES_AN_TIMEOUT;
1404 bp->serdes_an_pending = 1;
1405 mod_timer(&bp->timer, jiffies + bp->current_interval);
1407 bnx2_resolve_flow_ctrl(bp);
1408 bnx2_set_mac_link(bp);
1414 #define ETHTOOL_ALL_FIBRE_SPEED \
1415 (bp->phy_flags & PHY_2_5G_CAPABLE_FLAG) ? \
1416 (ADVERTISED_2500baseX_Full | ADVERTISED_1000baseT_Full) :\
1417 (ADVERTISED_1000baseT_Full)
1419 #define ETHTOOL_ALL_COPPER_SPEED \
1420 (ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full | \
1421 ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full | \
1422 ADVERTISED_1000baseT_Full)
1424 #define PHY_ALL_10_100_SPEED (ADVERTISE_10HALF | ADVERTISE_10FULL | \
1425 ADVERTISE_100HALF | ADVERTISE_100FULL | ADVERTISE_CSMA)
1427 #define PHY_ALL_1000_SPEED (ADVERTISE_1000HALF | ADVERTISE_1000FULL)
1430 bnx2_set_default_remote_link(struct bnx2 *bp)
1434 if (bp->phy_port == PORT_TP)
1435 link = REG_RD_IND(bp, bp->shmem_base + BNX2_RPHY_COPPER_LINK);
1437 link = REG_RD_IND(bp, bp->shmem_base + BNX2_RPHY_SERDES_LINK);
1439 if (link & BNX2_NETLINK_SET_LINK_ENABLE_AUTONEG) {
1440 bp->req_line_speed = 0;
1441 bp->autoneg |= AUTONEG_SPEED;
1442 bp->advertising = ADVERTISED_Autoneg;
1443 if (link & BNX2_NETLINK_SET_LINK_SPEED_10HALF)
1444 bp->advertising |= ADVERTISED_10baseT_Half;
1445 if (link & BNX2_NETLINK_SET_LINK_SPEED_10FULL)
1446 bp->advertising |= ADVERTISED_10baseT_Full;
1447 if (link & BNX2_NETLINK_SET_LINK_SPEED_100HALF)
1448 bp->advertising |= ADVERTISED_100baseT_Half;
1449 if (link & BNX2_NETLINK_SET_LINK_SPEED_100FULL)
1450 bp->advertising |= ADVERTISED_100baseT_Full;
1451 if (link & BNX2_NETLINK_SET_LINK_SPEED_1GFULL)
1452 bp->advertising |= ADVERTISED_1000baseT_Full;
1453 if (link & BNX2_NETLINK_SET_LINK_SPEED_2G5FULL)
1454 bp->advertising |= ADVERTISED_2500baseX_Full;
1457 bp->advertising = 0;
1458 bp->req_duplex = DUPLEX_FULL;
1459 if (link & BNX2_NETLINK_SET_LINK_SPEED_10) {
1460 bp->req_line_speed = SPEED_10;
1461 if (link & BNX2_NETLINK_SET_LINK_SPEED_10HALF)
1462 bp->req_duplex = DUPLEX_HALF;
1464 if (link & BNX2_NETLINK_SET_LINK_SPEED_100) {
1465 bp->req_line_speed = SPEED_100;
1466 if (link & BNX2_NETLINK_SET_LINK_SPEED_100HALF)
1467 bp->req_duplex = DUPLEX_HALF;
1469 if (link & BNX2_NETLINK_SET_LINK_SPEED_1GFULL)
1470 bp->req_line_speed = SPEED_1000;
1471 if (link & BNX2_NETLINK_SET_LINK_SPEED_2G5FULL)
1472 bp->req_line_speed = SPEED_2500;
1477 bnx2_set_default_link(struct bnx2 *bp)
1479 if (bp->phy_flags & REMOTE_PHY_CAP_FLAG)
1480 return bnx2_set_default_remote_link(bp);
1482 bp->autoneg = AUTONEG_SPEED | AUTONEG_FLOW_CTRL;
1483 bp->req_line_speed = 0;
1484 if (bp->phy_flags & PHY_SERDES_FLAG) {
1487 bp->advertising = ETHTOOL_ALL_FIBRE_SPEED | ADVERTISED_Autoneg;
1489 reg = REG_RD_IND(bp, bp->shmem_base + BNX2_PORT_HW_CFG_CONFIG);
1490 reg &= BNX2_PORT_HW_CFG_CFG_DFLT_LINK_MASK;
1491 if (reg == BNX2_PORT_HW_CFG_CFG_DFLT_LINK_1G) {
1493 bp->req_line_speed = bp->line_speed = SPEED_1000;
1494 bp->req_duplex = DUPLEX_FULL;
1497 bp->advertising = ETHTOOL_ALL_COPPER_SPEED | ADVERTISED_Autoneg;
1501 bnx2_send_heart_beat(struct bnx2 *bp)
1506 spin_lock(&bp->indirect_lock);
1507 msg = (u32) (++bp->fw_drv_pulse_wr_seq & BNX2_DRV_PULSE_SEQ_MASK);
1508 addr = bp->shmem_base + BNX2_DRV_PULSE_MB;
1509 REG_WR(bp, BNX2_PCICFG_REG_WINDOW_ADDRESS, addr);
1510 REG_WR(bp, BNX2_PCICFG_REG_WINDOW, msg);
1511 spin_unlock(&bp->indirect_lock);
1515 bnx2_remote_phy_event(struct bnx2 *bp)
1518 u8 link_up = bp->link_up;
1521 msg = REG_RD_IND(bp, bp->shmem_base + BNX2_LINK_STATUS);
1523 if (msg & BNX2_LINK_STATUS_HEART_BEAT_EXPIRED)
1524 bnx2_send_heart_beat(bp);
1526 msg &= ~BNX2_LINK_STATUS_HEART_BEAT_EXPIRED;
1528 if ((msg & BNX2_LINK_STATUS_LINK_UP) == BNX2_LINK_STATUS_LINK_DOWN)
1534 speed = msg & BNX2_LINK_STATUS_SPEED_MASK;
1535 bp->duplex = DUPLEX_FULL;
1537 case BNX2_LINK_STATUS_10HALF:
1538 bp->duplex = DUPLEX_HALF;
1539 case BNX2_LINK_STATUS_10FULL:
1540 bp->line_speed = SPEED_10;
1542 case BNX2_LINK_STATUS_100HALF:
1543 bp->duplex = DUPLEX_HALF;
1544 case BNX2_LINK_STATUS_100BASE_T4:
1545 case BNX2_LINK_STATUS_100FULL:
1546 bp->line_speed = SPEED_100;
1548 case BNX2_LINK_STATUS_1000HALF:
1549 bp->duplex = DUPLEX_HALF;
1550 case BNX2_LINK_STATUS_1000FULL:
1551 bp->line_speed = SPEED_1000;
1553 case BNX2_LINK_STATUS_2500HALF:
1554 bp->duplex = DUPLEX_HALF;
1555 case BNX2_LINK_STATUS_2500FULL:
1556 bp->line_speed = SPEED_2500;
1563 spin_lock(&bp->phy_lock);
1565 if ((bp->autoneg & (AUTONEG_SPEED | AUTONEG_FLOW_CTRL)) !=
1566 (AUTONEG_SPEED | AUTONEG_FLOW_CTRL)) {
1567 if (bp->duplex == DUPLEX_FULL)
1568 bp->flow_ctrl = bp->req_flow_ctrl;
1570 if (msg & BNX2_LINK_STATUS_TX_FC_ENABLED)
1571 bp->flow_ctrl |= FLOW_CTRL_TX;
1572 if (msg & BNX2_LINK_STATUS_RX_FC_ENABLED)
1573 bp->flow_ctrl |= FLOW_CTRL_RX;
1576 old_port = bp->phy_port;
1577 if (msg & BNX2_LINK_STATUS_SERDES_LINK)
1578 bp->phy_port = PORT_FIBRE;
1580 bp->phy_port = PORT_TP;
1582 if (old_port != bp->phy_port)
1583 bnx2_set_default_link(bp);
1585 spin_unlock(&bp->phy_lock);
1587 if (bp->link_up != link_up)
1588 bnx2_report_link(bp);
1590 bnx2_set_mac_link(bp);
1594 bnx2_set_remote_link(struct bnx2 *bp)
1598 evt_code = REG_RD_IND(bp, bp->shmem_base + BNX2_FW_EVT_CODE_MB);
1600 case BNX2_FW_EVT_CODE_LINK_EVENT:
1601 bnx2_remote_phy_event(bp);
1603 case BNX2_FW_EVT_CODE_SW_TIMER_EXPIRATION_EVENT:
1605 bnx2_send_heart_beat(bp);
1612 bnx2_setup_copper_phy(struct bnx2 *bp)
1617 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
1619 if (bp->autoneg & AUTONEG_SPEED) {
1620 u32 adv_reg, adv1000_reg;
1621 u32 new_adv_reg = 0;
1622 u32 new_adv1000_reg = 0;
1624 bnx2_read_phy(bp, bp->mii_adv, &adv_reg);
1625 adv_reg &= (PHY_ALL_10_100_SPEED | ADVERTISE_PAUSE_CAP |
1626 ADVERTISE_PAUSE_ASYM);
1628 bnx2_read_phy(bp, MII_CTRL1000, &adv1000_reg);
1629 adv1000_reg &= PHY_ALL_1000_SPEED;
1631 if (bp->advertising & ADVERTISED_10baseT_Half)
1632 new_adv_reg |= ADVERTISE_10HALF;
1633 if (bp->advertising & ADVERTISED_10baseT_Full)
1634 new_adv_reg |= ADVERTISE_10FULL;
1635 if (bp->advertising & ADVERTISED_100baseT_Half)
1636 new_adv_reg |= ADVERTISE_100HALF;
1637 if (bp->advertising & ADVERTISED_100baseT_Full)
1638 new_adv_reg |= ADVERTISE_100FULL;
1639 if (bp->advertising & ADVERTISED_1000baseT_Full)
1640 new_adv1000_reg |= ADVERTISE_1000FULL;
1642 new_adv_reg |= ADVERTISE_CSMA;
1644 new_adv_reg |= bnx2_phy_get_pause_adv(bp);
1646 if ((adv1000_reg != new_adv1000_reg) ||
1647 (adv_reg != new_adv_reg) ||
1648 ((bmcr & BMCR_ANENABLE) == 0)) {
1650 bnx2_write_phy(bp, bp->mii_adv, new_adv_reg);
1651 bnx2_write_phy(bp, MII_CTRL1000, new_adv1000_reg);
1652 bnx2_write_phy(bp, bp->mii_bmcr, BMCR_ANRESTART |
1655 else if (bp->link_up) {
1656 /* Flow ctrl may have changed from auto to forced */
1657 /* or vice-versa. */
1659 bnx2_resolve_flow_ctrl(bp);
1660 bnx2_set_mac_link(bp);
1666 if (bp->req_line_speed == SPEED_100) {
1667 new_bmcr |= BMCR_SPEED100;
1669 if (bp->req_duplex == DUPLEX_FULL) {
1670 new_bmcr |= BMCR_FULLDPLX;
1672 if (new_bmcr != bmcr) {
1675 bnx2_read_phy(bp, bp->mii_bmsr, &bmsr);
1676 bnx2_read_phy(bp, bp->mii_bmsr, &bmsr);
1678 if (bmsr & BMSR_LSTATUS) {
1679 /* Force link down */
1680 bnx2_write_phy(bp, bp->mii_bmcr, BMCR_LOOPBACK);
1681 spin_unlock_bh(&bp->phy_lock);
1683 spin_lock_bh(&bp->phy_lock);
1685 bnx2_read_phy(bp, bp->mii_bmsr, &bmsr);
1686 bnx2_read_phy(bp, bp->mii_bmsr, &bmsr);
1689 bnx2_write_phy(bp, bp->mii_bmcr, new_bmcr);
1691 /* Normally, the new speed is setup after the link has
1692 * gone down and up again. In some cases, link will not go
1693 * down so we need to set up the new speed here.
1695 if (bmsr & BMSR_LSTATUS) {
1696 bp->line_speed = bp->req_line_speed;
1697 bp->duplex = bp->req_duplex;
1698 bnx2_resolve_flow_ctrl(bp);
1699 bnx2_set_mac_link(bp);
1702 bnx2_resolve_flow_ctrl(bp);
1703 bnx2_set_mac_link(bp);
1709 bnx2_setup_phy(struct bnx2 *bp, u8 port)
1711 if (bp->loopback == MAC_LOOPBACK)
1714 if (bp->phy_flags & PHY_SERDES_FLAG) {
1715 return (bnx2_setup_serdes_phy(bp, port));
1718 return (bnx2_setup_copper_phy(bp));
1723 bnx2_init_5709s_phy(struct bnx2 *bp)
1727 bp->mii_bmcr = MII_BMCR + 0x10;
1728 bp->mii_bmsr = MII_BMSR + 0x10;
1729 bp->mii_bmsr1 = MII_BNX2_GP_TOP_AN_STATUS1;
1730 bp->mii_adv = MII_ADVERTISE + 0x10;
1731 bp->mii_lpa = MII_LPA + 0x10;
1732 bp->mii_up1 = MII_BNX2_OVER1G_UP1;
1734 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_AER);
1735 bnx2_write_phy(bp, MII_BNX2_AER_AER, MII_BNX2_AER_AER_AN_MMD);
1737 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_COMBO_IEEEB0);
1740 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_SERDES_DIG);
1742 bnx2_read_phy(bp, MII_BNX2_SERDES_DIG_1000XCTL1, &val);
1743 val &= ~MII_BNX2_SD_1000XCTL1_AUTODET;
1744 val |= MII_BNX2_SD_1000XCTL1_FIBER;
1745 bnx2_write_phy(bp, MII_BNX2_SERDES_DIG_1000XCTL1, val);
1747 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_OVER1G);
1748 bnx2_read_phy(bp, MII_BNX2_OVER1G_UP1, &val);
1749 if (bp->phy_flags & PHY_2_5G_CAPABLE_FLAG)
1750 val |= BCM5708S_UP1_2G5;
1752 val &= ~BCM5708S_UP1_2G5;
1753 bnx2_write_phy(bp, MII_BNX2_OVER1G_UP1, val);
1755 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_BAM_NXTPG);
1756 bnx2_read_phy(bp, MII_BNX2_BAM_NXTPG_CTL, &val);
1757 val |= MII_BNX2_NXTPG_CTL_T2 | MII_BNX2_NXTPG_CTL_BAM;
1758 bnx2_write_phy(bp, MII_BNX2_BAM_NXTPG_CTL, val);
1760 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_CL73_USERB0);
1762 val = MII_BNX2_CL73_BAM_EN | MII_BNX2_CL73_BAM_STA_MGR_EN |
1763 MII_BNX2_CL73_BAM_NP_AFT_BP_EN;
1764 bnx2_write_phy(bp, MII_BNX2_CL73_BAM_CTL1, val);
1766 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_COMBO_IEEEB0);
1772 bnx2_init_5708s_phy(struct bnx2 *bp)
1778 bp->mii_up1 = BCM5708S_UP1;
1780 bnx2_write_phy(bp, BCM5708S_BLK_ADDR, BCM5708S_BLK_ADDR_DIG3);
1781 bnx2_write_phy(bp, BCM5708S_DIG_3_0, BCM5708S_DIG_3_0_USE_IEEE);
1782 bnx2_write_phy(bp, BCM5708S_BLK_ADDR, BCM5708S_BLK_ADDR_DIG);
1784 bnx2_read_phy(bp, BCM5708S_1000X_CTL1, &val);
1785 val |= BCM5708S_1000X_CTL1_FIBER_MODE | BCM5708S_1000X_CTL1_AUTODET_EN;
1786 bnx2_write_phy(bp, BCM5708S_1000X_CTL1, val);
1788 bnx2_read_phy(bp, BCM5708S_1000X_CTL2, &val);
1789 val |= BCM5708S_1000X_CTL2_PLLEL_DET_EN;
1790 bnx2_write_phy(bp, BCM5708S_1000X_CTL2, val);
1792 if (bp->phy_flags & PHY_2_5G_CAPABLE_FLAG) {
1793 bnx2_read_phy(bp, BCM5708S_UP1, &val);
1794 val |= BCM5708S_UP1_2G5;
1795 bnx2_write_phy(bp, BCM5708S_UP1, val);
1798 if ((CHIP_ID(bp) == CHIP_ID_5708_A0) ||
1799 (CHIP_ID(bp) == CHIP_ID_5708_B0) ||
1800 (CHIP_ID(bp) == CHIP_ID_5708_B1)) {
1801 /* increase tx signal amplitude */
1802 bnx2_write_phy(bp, BCM5708S_BLK_ADDR,
1803 BCM5708S_BLK_ADDR_TX_MISC);
1804 bnx2_read_phy(bp, BCM5708S_TX_ACTL1, &val);
1805 val &= ~BCM5708S_TX_ACTL1_DRIVER_VCM;
1806 bnx2_write_phy(bp, BCM5708S_TX_ACTL1, val);
1807 bnx2_write_phy(bp, BCM5708S_BLK_ADDR, BCM5708S_BLK_ADDR_DIG);
1810 val = REG_RD_IND(bp, bp->shmem_base + BNX2_PORT_HW_CFG_CONFIG) &
1811 BNX2_PORT_HW_CFG_CFG_TXCTL3_MASK;
1816 is_backplane = REG_RD_IND(bp, bp->shmem_base +
1817 BNX2_SHARED_HW_CFG_CONFIG);
1818 if (is_backplane & BNX2_SHARED_HW_CFG_PHY_BACKPLANE) {
1819 bnx2_write_phy(bp, BCM5708S_BLK_ADDR,
1820 BCM5708S_BLK_ADDR_TX_MISC);
1821 bnx2_write_phy(bp, BCM5708S_TX_ACTL3, val);
1822 bnx2_write_phy(bp, BCM5708S_BLK_ADDR,
1823 BCM5708S_BLK_ADDR_DIG);
1830 bnx2_init_5706s_phy(struct bnx2 *bp)
1834 bp->phy_flags &= ~PHY_PARALLEL_DETECT_FLAG;
1836 if (CHIP_NUM(bp) == CHIP_NUM_5706)
1837 REG_WR(bp, BNX2_MISC_GP_HW_CTL0, 0x300);
1839 if (bp->dev->mtu > 1500) {
1842 /* Set extended packet length bit */
1843 bnx2_write_phy(bp, 0x18, 0x7);
1844 bnx2_read_phy(bp, 0x18, &val);
1845 bnx2_write_phy(bp, 0x18, (val & 0xfff8) | 0x4000);
1847 bnx2_write_phy(bp, 0x1c, 0x6c00);
1848 bnx2_read_phy(bp, 0x1c, &val);
1849 bnx2_write_phy(bp, 0x1c, (val & 0x3ff) | 0xec02);
1854 bnx2_write_phy(bp, 0x18, 0x7);
1855 bnx2_read_phy(bp, 0x18, &val);
1856 bnx2_write_phy(bp, 0x18, val & ~0x4007);
1858 bnx2_write_phy(bp, 0x1c, 0x6c00);
1859 bnx2_read_phy(bp, 0x1c, &val);
1860 bnx2_write_phy(bp, 0x1c, (val & 0x3fd) | 0xec00);
1867 bnx2_init_copper_phy(struct bnx2 *bp)
1873 if (bp->phy_flags & PHY_CRC_FIX_FLAG) {
1874 bnx2_write_phy(bp, 0x18, 0x0c00);
1875 bnx2_write_phy(bp, 0x17, 0x000a);
1876 bnx2_write_phy(bp, 0x15, 0x310b);
1877 bnx2_write_phy(bp, 0x17, 0x201f);
1878 bnx2_write_phy(bp, 0x15, 0x9506);
1879 bnx2_write_phy(bp, 0x17, 0x401f);
1880 bnx2_write_phy(bp, 0x15, 0x14e2);
1881 bnx2_write_phy(bp, 0x18, 0x0400);
1884 if (bp->phy_flags & PHY_DIS_EARLY_DAC_FLAG) {
1885 bnx2_write_phy(bp, MII_BNX2_DSP_ADDRESS,
1886 MII_BNX2_DSP_EXPAND_REG | 0x8);
1887 bnx2_read_phy(bp, MII_BNX2_DSP_RW_PORT, &val);
1889 bnx2_write_phy(bp, MII_BNX2_DSP_RW_PORT, val);
1892 if (bp->dev->mtu > 1500) {
1893 /* Set extended packet length bit */
1894 bnx2_write_phy(bp, 0x18, 0x7);
1895 bnx2_read_phy(bp, 0x18, &val);
1896 bnx2_write_phy(bp, 0x18, val | 0x4000);
1898 bnx2_read_phy(bp, 0x10, &val);
1899 bnx2_write_phy(bp, 0x10, val | 0x1);
1902 bnx2_write_phy(bp, 0x18, 0x7);
1903 bnx2_read_phy(bp, 0x18, &val);
1904 bnx2_write_phy(bp, 0x18, val & ~0x4007);
1906 bnx2_read_phy(bp, 0x10, &val);
1907 bnx2_write_phy(bp, 0x10, val & ~0x1);
1910 /* ethernet@wirespeed */
1911 bnx2_write_phy(bp, 0x18, 0x7007);
1912 bnx2_read_phy(bp, 0x18, &val);
1913 bnx2_write_phy(bp, 0x18, val | (1 << 15) | (1 << 4));
1919 bnx2_init_phy(struct bnx2 *bp)
1924 bp->phy_flags &= ~PHY_INT_MODE_MASK_FLAG;
1925 bp->phy_flags |= PHY_INT_MODE_LINK_READY_FLAG;
1927 bp->mii_bmcr = MII_BMCR;
1928 bp->mii_bmsr = MII_BMSR;
1929 bp->mii_bmsr1 = MII_BMSR;
1930 bp->mii_adv = MII_ADVERTISE;
1931 bp->mii_lpa = MII_LPA;
1933 REG_WR(bp, BNX2_EMAC_ATTENTION_ENA, BNX2_EMAC_ATTENTION_ENA_LINK);
1935 if (bp->phy_flags & REMOTE_PHY_CAP_FLAG)
1938 bnx2_read_phy(bp, MII_PHYSID1, &val);
1939 bp->phy_id = val << 16;
1940 bnx2_read_phy(bp, MII_PHYSID2, &val);
1941 bp->phy_id |= val & 0xffff;
1943 if (bp->phy_flags & PHY_SERDES_FLAG) {
1944 if (CHIP_NUM(bp) == CHIP_NUM_5706)
1945 rc = bnx2_init_5706s_phy(bp);
1946 else if (CHIP_NUM(bp) == CHIP_NUM_5708)
1947 rc = bnx2_init_5708s_phy(bp);
1948 else if (CHIP_NUM(bp) == CHIP_NUM_5709)
1949 rc = bnx2_init_5709s_phy(bp);
1952 rc = bnx2_init_copper_phy(bp);
1957 rc = bnx2_setup_phy(bp, bp->phy_port);
1963 bnx2_set_mac_loopback(struct bnx2 *bp)
1967 mac_mode = REG_RD(bp, BNX2_EMAC_MODE);
1968 mac_mode &= ~BNX2_EMAC_MODE_PORT;
1969 mac_mode |= BNX2_EMAC_MODE_MAC_LOOP | BNX2_EMAC_MODE_FORCE_LINK;
1970 REG_WR(bp, BNX2_EMAC_MODE, mac_mode);
1975 static int bnx2_test_link(struct bnx2 *);
1978 bnx2_set_phy_loopback(struct bnx2 *bp)
1983 spin_lock_bh(&bp->phy_lock);
1984 rc = bnx2_write_phy(bp, bp->mii_bmcr, BMCR_LOOPBACK | BMCR_FULLDPLX |
1986 spin_unlock_bh(&bp->phy_lock);
1990 for (i = 0; i < 10; i++) {
1991 if (bnx2_test_link(bp) == 0)
1996 mac_mode = REG_RD(bp, BNX2_EMAC_MODE);
1997 mac_mode &= ~(BNX2_EMAC_MODE_PORT | BNX2_EMAC_MODE_HALF_DUPLEX |
1998 BNX2_EMAC_MODE_MAC_LOOP | BNX2_EMAC_MODE_FORCE_LINK |
1999 BNX2_EMAC_MODE_25G_MODE);
2001 mac_mode |= BNX2_EMAC_MODE_PORT_GMII;
2002 REG_WR(bp, BNX2_EMAC_MODE, mac_mode);
2008 bnx2_fw_sync(struct bnx2 *bp, u32 msg_data, int silent)
2014 msg_data |= bp->fw_wr_seq;
2016 REG_WR_IND(bp, bp->shmem_base + BNX2_DRV_MB, msg_data);
2018 /* wait for an acknowledgement. */
2019 for (i = 0; i < (FW_ACK_TIME_OUT_MS / 10); i++) {
2022 val = REG_RD_IND(bp, bp->shmem_base + BNX2_FW_MB);
2024 if ((val & BNX2_FW_MSG_ACK) == (msg_data & BNX2_DRV_MSG_SEQ))
2027 if ((msg_data & BNX2_DRV_MSG_DATA) == BNX2_DRV_MSG_DATA_WAIT0)
2030 /* If we timed out, inform the firmware that this is the case. */
2031 if ((val & BNX2_FW_MSG_ACK) != (msg_data & BNX2_DRV_MSG_SEQ)) {
2033 printk(KERN_ERR PFX "fw sync timeout, reset code = "
2036 msg_data &= ~BNX2_DRV_MSG_CODE;
2037 msg_data |= BNX2_DRV_MSG_CODE_FW_TIMEOUT;
2039 REG_WR_IND(bp, bp->shmem_base + BNX2_DRV_MB, msg_data);
2044 if ((val & BNX2_FW_MSG_STATUS_MASK) != BNX2_FW_MSG_STATUS_OK)
2051 bnx2_init_5709_context(struct bnx2 *bp)
2056 val = BNX2_CTX_COMMAND_ENABLED | BNX2_CTX_COMMAND_MEM_INIT | (1 << 12);
2057 val |= (BCM_PAGE_BITS - 8) << 16;
2058 REG_WR(bp, BNX2_CTX_COMMAND, val);
2059 for (i = 0; i < 10; i++) {
2060 val = REG_RD(bp, BNX2_CTX_COMMAND);
2061 if (!(val & BNX2_CTX_COMMAND_MEM_INIT))
2065 if (val & BNX2_CTX_COMMAND_MEM_INIT)
2068 for (i = 0; i < bp->ctx_pages; i++) {
2071 REG_WR(bp, BNX2_CTX_HOST_PAGE_TBL_DATA0,
2072 (bp->ctx_blk_mapping[i] & 0xffffffff) |
2073 BNX2_CTX_HOST_PAGE_TBL_DATA0_VALID);
2074 REG_WR(bp, BNX2_CTX_HOST_PAGE_TBL_DATA1,
2075 (u64) bp->ctx_blk_mapping[i] >> 32);
2076 REG_WR(bp, BNX2_CTX_HOST_PAGE_TBL_CTRL, i |
2077 BNX2_CTX_HOST_PAGE_TBL_CTRL_WRITE_REQ);
2078 for (j = 0; j < 10; j++) {
2080 val = REG_RD(bp, BNX2_CTX_HOST_PAGE_TBL_CTRL);
2081 if (!(val & BNX2_CTX_HOST_PAGE_TBL_CTRL_WRITE_REQ))
2085 if (val & BNX2_CTX_HOST_PAGE_TBL_CTRL_WRITE_REQ) {
2094 bnx2_init_context(struct bnx2 *bp)
2100 u32 vcid_addr, pcid_addr, offset;
2105 if (CHIP_ID(bp) == CHIP_ID_5706_A0) {
2108 vcid_addr = GET_PCID_ADDR(vcid);
2110 new_vcid = 0x60 + (vcid & 0xf0) + (vcid & 0x7);
2115 pcid_addr = GET_PCID_ADDR(new_vcid);
2118 vcid_addr = GET_CID_ADDR(vcid);
2119 pcid_addr = vcid_addr;
2122 for (i = 0; i < (CTX_SIZE / PHY_CTX_SIZE); i++) {
2123 vcid_addr += (i << PHY_CTX_SHIFT);
2124 pcid_addr += (i << PHY_CTX_SHIFT);
2126 REG_WR(bp, BNX2_CTX_VIRT_ADDR, 0x00);
2127 REG_WR(bp, BNX2_CTX_PAGE_TBL, pcid_addr);
2129 /* Zero out the context. */
2130 for (offset = 0; offset < PHY_CTX_SIZE; offset += 4)
2131 CTX_WR(bp, 0x00, offset, 0);
2133 REG_WR(bp, BNX2_CTX_VIRT_ADDR, vcid_addr);
2134 REG_WR(bp, BNX2_CTX_PAGE_TBL, pcid_addr);
2140 bnx2_alloc_bad_rbuf(struct bnx2 *bp)
2146 good_mbuf = kmalloc(512 * sizeof(u16), GFP_KERNEL);
2147 if (good_mbuf == NULL) {
2148 printk(KERN_ERR PFX "Failed to allocate memory in "
2149 "bnx2_alloc_bad_rbuf\n");
2153 REG_WR(bp, BNX2_MISC_ENABLE_SET_BITS,
2154 BNX2_MISC_ENABLE_SET_BITS_RX_MBUF_ENABLE);
2158 /* Allocate a bunch of mbufs and save the good ones in an array. */
2159 val = REG_RD_IND(bp, BNX2_RBUF_STATUS1);
2160 while (val & BNX2_RBUF_STATUS1_FREE_COUNT) {
2161 REG_WR_IND(bp, BNX2_RBUF_COMMAND, BNX2_RBUF_COMMAND_ALLOC_REQ);
2163 val = REG_RD_IND(bp, BNX2_RBUF_FW_BUF_ALLOC);
2165 val &= BNX2_RBUF_FW_BUF_ALLOC_VALUE;
2167 /* The addresses with Bit 9 set are bad memory blocks. */
2168 if (!(val & (1 << 9))) {
2169 good_mbuf[good_mbuf_cnt] = (u16) val;
2173 val = REG_RD_IND(bp, BNX2_RBUF_STATUS1);
2176 /* Free the good ones back to the mbuf pool thus discarding
2177 * all the bad ones. */
2178 while (good_mbuf_cnt) {
2181 val = good_mbuf[good_mbuf_cnt];
2182 val = (val << 9) | val | 1;
2184 REG_WR_IND(bp, BNX2_RBUF_FW_BUF_FREE, val);
2191 bnx2_set_mac_addr(struct bnx2 *bp)
2194 u8 *mac_addr = bp->dev->dev_addr;
2196 val = (mac_addr[0] << 8) | mac_addr[1];
2198 REG_WR(bp, BNX2_EMAC_MAC_MATCH0, val);
2200 val = (mac_addr[2] << 24) | (mac_addr[3] << 16) |
2201 (mac_addr[4] << 8) | mac_addr[5];
2203 REG_WR(bp, BNX2_EMAC_MAC_MATCH1, val);
2207 bnx2_alloc_rx_skb(struct bnx2 *bp, u16 index)
2209 struct sk_buff *skb;
2210 struct sw_bd *rx_buf = &bp->rx_buf_ring[index];
2212 struct rx_bd *rxbd = &bp->rx_desc_ring[RX_RING(index)][RX_IDX(index)];
2213 unsigned long align;
2215 skb = netdev_alloc_skb(bp->dev, bp->rx_buf_size);
2220 if (unlikely((align = (unsigned long) skb->data & (BNX2_RX_ALIGN - 1))))
2221 skb_reserve(skb, BNX2_RX_ALIGN - align);
2223 mapping = pci_map_single(bp->pdev, skb->data, bp->rx_buf_use_size,
2224 PCI_DMA_FROMDEVICE);
2227 pci_unmap_addr_set(rx_buf, mapping, mapping);
2229 rxbd->rx_bd_haddr_hi = (u64) mapping >> 32;
2230 rxbd->rx_bd_haddr_lo = (u64) mapping & 0xffffffff;
2232 bp->rx_prod_bseq += bp->rx_buf_use_size;
2238 bnx2_phy_event_is_set(struct bnx2 *bp, u32 event)
2240 struct status_block *sblk = bp->status_blk;
2241 u32 new_link_state, old_link_state;
2244 new_link_state = sblk->status_attn_bits & event;
2245 old_link_state = sblk->status_attn_bits_ack & event;
2246 if (new_link_state != old_link_state) {
2248 REG_WR(bp, BNX2_PCICFG_STATUS_BIT_SET_CMD, event);
2250 REG_WR(bp, BNX2_PCICFG_STATUS_BIT_CLEAR_CMD, event);
2258 bnx2_phy_int(struct bnx2 *bp)
2260 if (bnx2_phy_event_is_set(bp, STATUS_ATTN_BITS_LINK_STATE)) {
2261 spin_lock(&bp->phy_lock);
2263 spin_unlock(&bp->phy_lock);
2265 if (bnx2_phy_event_is_set(bp, STATUS_ATTN_BITS_TIMER_ABORT))
2266 bnx2_set_remote_link(bp);
2271 bnx2_tx_int(struct bnx2 *bp)
2273 struct status_block *sblk = bp->status_blk;
2274 u16 hw_cons, sw_cons, sw_ring_cons;
2277 hw_cons = bp->hw_tx_cons = sblk->status_tx_quick_consumer_index0;
2278 if ((hw_cons & MAX_TX_DESC_CNT) == MAX_TX_DESC_CNT) {
2281 sw_cons = bp->tx_cons;
2283 while (sw_cons != hw_cons) {
2284 struct sw_bd *tx_buf;
2285 struct sk_buff *skb;
2288 sw_ring_cons = TX_RING_IDX(sw_cons);
2290 tx_buf = &bp->tx_buf_ring[sw_ring_cons];
2293 /* partial BD completions possible with TSO packets */
2294 if (skb_is_gso(skb)) {
2295 u16 last_idx, last_ring_idx;
2297 last_idx = sw_cons +
2298 skb_shinfo(skb)->nr_frags + 1;
2299 last_ring_idx = sw_ring_cons +
2300 skb_shinfo(skb)->nr_frags + 1;
2301 if (unlikely(last_ring_idx >= MAX_TX_DESC_CNT)) {
2304 if (((s16) ((s16) last_idx - (s16) hw_cons)) > 0) {
2309 pci_unmap_single(bp->pdev, pci_unmap_addr(tx_buf, mapping),
2310 skb_headlen(skb), PCI_DMA_TODEVICE);
2313 last = skb_shinfo(skb)->nr_frags;
2315 for (i = 0; i < last; i++) {
2316 sw_cons = NEXT_TX_BD(sw_cons);
2318 pci_unmap_page(bp->pdev,
2320 &bp->tx_buf_ring[TX_RING_IDX(sw_cons)],
2322 skb_shinfo(skb)->frags[i].size,
2326 sw_cons = NEXT_TX_BD(sw_cons);
2328 tx_free_bd += last + 1;
2332 hw_cons = bp->hw_tx_cons =
2333 sblk->status_tx_quick_consumer_index0;
2335 if ((hw_cons & MAX_TX_DESC_CNT) == MAX_TX_DESC_CNT) {
2340 bp->tx_cons = sw_cons;
2341 /* Need to make the tx_cons update visible to bnx2_start_xmit()
2342 * before checking for netif_queue_stopped(). Without the
2343 * memory barrier, there is a small possibility that bnx2_start_xmit()
2344 * will miss it and cause the queue to be stopped forever.
2348 if (unlikely(netif_queue_stopped(bp->dev)) &&
2349 (bnx2_tx_avail(bp) > bp->tx_wake_thresh)) {
2350 netif_tx_lock(bp->dev);
2351 if ((netif_queue_stopped(bp->dev)) &&
2352 (bnx2_tx_avail(bp) > bp->tx_wake_thresh))
2353 netif_wake_queue(bp->dev);
2354 netif_tx_unlock(bp->dev);
2359 bnx2_reuse_rx_skb(struct bnx2 *bp, struct sk_buff *skb,
2362 struct sw_bd *cons_rx_buf, *prod_rx_buf;
2363 struct rx_bd *cons_bd, *prod_bd;
2365 cons_rx_buf = &bp->rx_buf_ring[cons];
2366 prod_rx_buf = &bp->rx_buf_ring[prod];
2368 pci_dma_sync_single_for_device(bp->pdev,
2369 pci_unmap_addr(cons_rx_buf, mapping),
2370 bp->rx_offset + RX_COPY_THRESH, PCI_DMA_FROMDEVICE);
2372 bp->rx_prod_bseq += bp->rx_buf_use_size;
2374 prod_rx_buf->skb = skb;
2379 pci_unmap_addr_set(prod_rx_buf, mapping,
2380 pci_unmap_addr(cons_rx_buf, mapping));
2382 cons_bd = &bp->rx_desc_ring[RX_RING(cons)][RX_IDX(cons)];
2383 prod_bd = &bp->rx_desc_ring[RX_RING(prod)][RX_IDX(prod)];
2384 prod_bd->rx_bd_haddr_hi = cons_bd->rx_bd_haddr_hi;
2385 prod_bd->rx_bd_haddr_lo = cons_bd->rx_bd_haddr_lo;
2389 bnx2_rx_int(struct bnx2 *bp, int budget)
2391 struct status_block *sblk = bp->status_blk;
2392 u16 hw_cons, sw_cons, sw_ring_cons, sw_prod, sw_ring_prod;
2393 struct l2_fhdr *rx_hdr;
2396 hw_cons = bp->hw_rx_cons = sblk->status_rx_quick_consumer_index0;
2397 if ((hw_cons & MAX_RX_DESC_CNT) == MAX_RX_DESC_CNT) {
2400 sw_cons = bp->rx_cons;
2401 sw_prod = bp->rx_prod;
2403 /* Memory barrier necessary as speculative reads of the rx
2404 * buffer can be ahead of the index in the status block
2407 while (sw_cons != hw_cons) {
2410 struct sw_bd *rx_buf;
2411 struct sk_buff *skb;
2412 dma_addr_t dma_addr;
2414 sw_ring_cons = RX_RING_IDX(sw_cons);
2415 sw_ring_prod = RX_RING_IDX(sw_prod);
2417 rx_buf = &bp->rx_buf_ring[sw_ring_cons];
2422 dma_addr = pci_unmap_addr(rx_buf, mapping);
2424 pci_dma_sync_single_for_cpu(bp->pdev, dma_addr,
2425 bp->rx_offset + RX_COPY_THRESH, PCI_DMA_FROMDEVICE);
2427 rx_hdr = (struct l2_fhdr *) skb->data;
2428 len = rx_hdr->l2_fhdr_pkt_len - 4;
2430 if ((status = rx_hdr->l2_fhdr_status) &
2431 (L2_FHDR_ERRORS_BAD_CRC |
2432 L2_FHDR_ERRORS_PHY_DECODE |
2433 L2_FHDR_ERRORS_ALIGNMENT |
2434 L2_FHDR_ERRORS_TOO_SHORT |
2435 L2_FHDR_ERRORS_GIANT_FRAME)) {
2440 /* Since we don't have a jumbo ring, copy small packets
2443 if ((bp->dev->mtu > 1500) && (len <= RX_COPY_THRESH)) {
2444 struct sk_buff *new_skb;
2446 new_skb = netdev_alloc_skb(bp->dev, len + 2);
2447 if (new_skb == NULL)
2451 skb_copy_from_linear_data_offset(skb, bp->rx_offset - 2,
2452 new_skb->data, len + 2);
2453 skb_reserve(new_skb, 2);
2454 skb_put(new_skb, len);
2456 bnx2_reuse_rx_skb(bp, skb,
2457 sw_ring_cons, sw_ring_prod);
2461 else if (bnx2_alloc_rx_skb(bp, sw_ring_prod) == 0) {
2462 pci_unmap_single(bp->pdev, dma_addr,
2463 bp->rx_buf_use_size, PCI_DMA_FROMDEVICE);
2465 skb_reserve(skb, bp->rx_offset);
2470 bnx2_reuse_rx_skb(bp, skb,
2471 sw_ring_cons, sw_ring_prod);
2475 skb->protocol = eth_type_trans(skb, bp->dev);
2477 if ((len > (bp->dev->mtu + ETH_HLEN)) &&
2478 (ntohs(skb->protocol) != 0x8100)) {
2485 skb->ip_summed = CHECKSUM_NONE;
2487 (status & (L2_FHDR_STATUS_TCP_SEGMENT |
2488 L2_FHDR_STATUS_UDP_DATAGRAM))) {
2490 if (likely((status & (L2_FHDR_ERRORS_TCP_XSUM |
2491 L2_FHDR_ERRORS_UDP_XSUM)) == 0))
2492 skb->ip_summed = CHECKSUM_UNNECESSARY;
2496 if ((status & L2_FHDR_STATUS_L2_VLAN_TAG) && (bp->vlgrp != 0)) {
2497 vlan_hwaccel_receive_skb(skb, bp->vlgrp,
2498 rx_hdr->l2_fhdr_vlan_tag);
2502 netif_receive_skb(skb);
2504 bp->dev->last_rx = jiffies;
2508 sw_cons = NEXT_RX_BD(sw_cons);
2509 sw_prod = NEXT_RX_BD(sw_prod);
2511 if ((rx_pkt == budget))
2514 /* Refresh hw_cons to see if there is new work */
2515 if (sw_cons == hw_cons) {
2516 hw_cons = bp->hw_rx_cons =
2517 sblk->status_rx_quick_consumer_index0;
2518 if ((hw_cons & MAX_RX_DESC_CNT) == MAX_RX_DESC_CNT)
2523 bp->rx_cons = sw_cons;
2524 bp->rx_prod = sw_prod;
2526 REG_WR16(bp, MB_RX_CID_ADDR + BNX2_L2CTX_HOST_BDIDX, sw_prod);
2528 REG_WR(bp, MB_RX_CID_ADDR + BNX2_L2CTX_HOST_BSEQ, bp->rx_prod_bseq);
2536 /* MSI ISR - The only difference between this and the INTx ISR
2537 * is that the MSI interrupt is always serviced.
2540 bnx2_msi(int irq, void *dev_instance)
2542 struct net_device *dev = dev_instance;
2543 struct bnx2 *bp = netdev_priv(dev);
2545 prefetch(bp->status_blk);
2546 REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD,
2547 BNX2_PCICFG_INT_ACK_CMD_USE_INT_HC_PARAM |
2548 BNX2_PCICFG_INT_ACK_CMD_MASK_INT);
2550 /* Return here if interrupt is disabled. */
2551 if (unlikely(atomic_read(&bp->intr_sem) != 0))
2554 netif_rx_schedule(dev);
2560 bnx2_msi_1shot(int irq, void *dev_instance)
2562 struct net_device *dev = dev_instance;
2563 struct bnx2 *bp = netdev_priv(dev);
2565 prefetch(bp->status_blk);
2567 /* Return here if interrupt is disabled. */
2568 if (unlikely(atomic_read(&bp->intr_sem) != 0))
2571 netif_rx_schedule(dev);
2577 bnx2_interrupt(int irq, void *dev_instance)
2579 struct net_device *dev = dev_instance;
2580 struct bnx2 *bp = netdev_priv(dev);
2581 struct status_block *sblk = bp->status_blk;
2583 /* When using INTx, it is possible for the interrupt to arrive
2584 * at the CPU before the status block posted prior to the
2585 * interrupt. Reading a register will flush the status block.
2586 * When using MSI, the MSI message will always complete after
2587 * the status block write.
2589 if ((sblk->status_idx == bp->last_status_idx) &&
2590 (REG_RD(bp, BNX2_PCICFG_MISC_STATUS) &
2591 BNX2_PCICFG_MISC_STATUS_INTA_VALUE))
2594 REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD,
2595 BNX2_PCICFG_INT_ACK_CMD_USE_INT_HC_PARAM |
2596 BNX2_PCICFG_INT_ACK_CMD_MASK_INT);
2598 /* Read back to deassert IRQ immediately to avoid too many
2599 * spurious interrupts.
2601 REG_RD(bp, BNX2_PCICFG_INT_ACK_CMD);
2603 /* Return here if interrupt is shared and is disabled. */
2604 if (unlikely(atomic_read(&bp->intr_sem) != 0))
2607 if (netif_rx_schedule_prep(dev)) {
2608 bp->last_status_idx = sblk->status_idx;
2609 __netif_rx_schedule(dev);
2615 #define STATUS_ATTN_EVENTS (STATUS_ATTN_BITS_LINK_STATE | \
2616 STATUS_ATTN_BITS_TIMER_ABORT)
2619 bnx2_has_work(struct bnx2 *bp)
2621 struct status_block *sblk = bp->status_blk;
2623 if ((sblk->status_rx_quick_consumer_index0 != bp->hw_rx_cons) ||
2624 (sblk->status_tx_quick_consumer_index0 != bp->hw_tx_cons))
2627 if ((sblk->status_attn_bits & STATUS_ATTN_EVENTS) !=
2628 (sblk->status_attn_bits_ack & STATUS_ATTN_EVENTS))
2635 bnx2_poll(struct net_device *dev, int *budget)
2637 struct bnx2 *bp = netdev_priv(dev);
2638 struct status_block *sblk = bp->status_blk;
2639 u32 status_attn_bits = sblk->status_attn_bits;
2640 u32 status_attn_bits_ack = sblk->status_attn_bits_ack;
2642 if ((status_attn_bits & STATUS_ATTN_EVENTS) !=
2643 (status_attn_bits_ack & STATUS_ATTN_EVENTS)) {
2647 /* This is needed to take care of transient status
2648 * during link changes.
2650 REG_WR(bp, BNX2_HC_COMMAND,
2651 bp->hc_cmd | BNX2_HC_COMMAND_COAL_NOW_WO_INT);
2652 REG_RD(bp, BNX2_HC_COMMAND);
2655 if (bp->status_blk->status_tx_quick_consumer_index0 != bp->hw_tx_cons)
2658 if (bp->status_blk->status_rx_quick_consumer_index0 != bp->hw_rx_cons) {
2659 int orig_budget = *budget;
2662 if (orig_budget > dev->quota)
2663 orig_budget = dev->quota;
2665 work_done = bnx2_rx_int(bp, orig_budget);
2666 *budget -= work_done;
2667 dev->quota -= work_done;
2670 bp->last_status_idx = bp->status_blk->status_idx;
2673 if (!bnx2_has_work(bp)) {
2674 netif_rx_complete(dev);
2675 if (likely(bp->flags & USING_MSI_FLAG)) {
2676 REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD,
2677 BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID |
2678 bp->last_status_idx);
2681 REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD,
2682 BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID |
2683 BNX2_PCICFG_INT_ACK_CMD_MASK_INT |
2684 bp->last_status_idx);
2686 REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD,
2687 BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID |
2688 bp->last_status_idx);
2695 /* Called with rtnl_lock from vlan functions and also netif_tx_lock
2696 * from set_multicast.
2699 bnx2_set_rx_mode(struct net_device *dev)
2701 struct bnx2 *bp = netdev_priv(dev);
2702 u32 rx_mode, sort_mode;
2705 spin_lock_bh(&bp->phy_lock);
2707 rx_mode = bp->rx_mode & ~(BNX2_EMAC_RX_MODE_PROMISCUOUS |
2708 BNX2_EMAC_RX_MODE_KEEP_VLAN_TAG);
2709 sort_mode = 1 | BNX2_RPM_SORT_USER0_BC_EN;
2711 if (!bp->vlgrp && !(bp->flags & ASF_ENABLE_FLAG))
2712 rx_mode |= BNX2_EMAC_RX_MODE_KEEP_VLAN_TAG;
2714 if (!(bp->flags & ASF_ENABLE_FLAG))
2715 rx_mode |= BNX2_EMAC_RX_MODE_KEEP_VLAN_TAG;
2717 if (dev->flags & IFF_PROMISC) {
2718 /* Promiscuous mode. */
2719 rx_mode |= BNX2_EMAC_RX_MODE_PROMISCUOUS;
2720 sort_mode |= BNX2_RPM_SORT_USER0_PROM_EN |
2721 BNX2_RPM_SORT_USER0_PROM_VLAN;
2723 else if (dev->flags & IFF_ALLMULTI) {
2724 for (i = 0; i < NUM_MC_HASH_REGISTERS; i++) {
2725 REG_WR(bp, BNX2_EMAC_MULTICAST_HASH0 + (i * 4),
2728 sort_mode |= BNX2_RPM_SORT_USER0_MC_EN;
2731 /* Accept one or more multicast(s). */
2732 struct dev_mc_list *mclist;
2733 u32 mc_filter[NUM_MC_HASH_REGISTERS];
2738 memset(mc_filter, 0, 4 * NUM_MC_HASH_REGISTERS);
2740 for (i = 0, mclist = dev->mc_list; mclist && i < dev->mc_count;
2741 i++, mclist = mclist->next) {
2743 crc = ether_crc_le(ETH_ALEN, mclist->dmi_addr);
2745 regidx = (bit & 0xe0) >> 5;
2747 mc_filter[regidx] |= (1 << bit);
2750 for (i = 0; i < NUM_MC_HASH_REGISTERS; i++) {
2751 REG_WR(bp, BNX2_EMAC_MULTICAST_HASH0 + (i * 4),
2755 sort_mode |= BNX2_RPM_SORT_USER0_MC_HSH_EN;
2758 if (rx_mode != bp->rx_mode) {
2759 bp->rx_mode = rx_mode;
2760 REG_WR(bp, BNX2_EMAC_RX_MODE, rx_mode);
2763 REG_WR(bp, BNX2_RPM_SORT_USER0, 0x0);
2764 REG_WR(bp, BNX2_RPM_SORT_USER0, sort_mode);
2765 REG_WR(bp, BNX2_RPM_SORT_USER0, sort_mode | BNX2_RPM_SORT_USER0_ENA);
2767 spin_unlock_bh(&bp->phy_lock);
2770 #define FW_BUF_SIZE 0x8000
2773 bnx2_gunzip_init(struct bnx2 *bp)
2775 if ((bp->gunzip_buf = vmalloc(FW_BUF_SIZE)) == NULL)
2778 if ((bp->strm = kmalloc(sizeof(*bp->strm), GFP_KERNEL)) == NULL)
2781 bp->strm->workspace = kmalloc(zlib_inflate_workspacesize(), GFP_KERNEL);
2782 if (bp->strm->workspace == NULL)
2792 vfree(bp->gunzip_buf);
2793 bp->gunzip_buf = NULL;
2796 printk(KERN_ERR PFX "%s: Cannot allocate firmware buffer for "
2797 "uncompression.\n", bp->dev->name);
2802 bnx2_gunzip_end(struct bnx2 *bp)
2804 kfree(bp->strm->workspace);
2809 if (bp->gunzip_buf) {
2810 vfree(bp->gunzip_buf);
2811 bp->gunzip_buf = NULL;
2816 bnx2_gunzip(struct bnx2 *bp, u8 *zbuf, int len, void **outbuf, int *outlen)
2820 /* check gzip header */
2821 if ((zbuf[0] != 0x1f) || (zbuf[1] != 0x8b) || (zbuf[2] != Z_DEFLATED))
2827 if (zbuf[3] & FNAME)
2828 while ((zbuf[n++] != 0) && (n < len));
2830 bp->strm->next_in = zbuf + n;
2831 bp->strm->avail_in = len - n;
2832 bp->strm->next_out = bp->gunzip_buf;
2833 bp->strm->avail_out = FW_BUF_SIZE;
2835 rc = zlib_inflateInit2(bp->strm, -MAX_WBITS);
2839 rc = zlib_inflate(bp->strm, Z_FINISH);
2841 *outlen = FW_BUF_SIZE - bp->strm->avail_out;
2842 *outbuf = bp->gunzip_buf;
2844 if ((rc != Z_OK) && (rc != Z_STREAM_END))
2845 printk(KERN_ERR PFX "%s: Firmware decompression error: %s\n",
2846 bp->dev->name, bp->strm->msg);
2848 zlib_inflateEnd(bp->strm);
2850 if (rc == Z_STREAM_END)
2857 load_rv2p_fw(struct bnx2 *bp, u32 *rv2p_code, u32 rv2p_code_len,
2864 for (i = 0; i < rv2p_code_len; i += 8) {
2865 REG_WR(bp, BNX2_RV2P_INSTR_HIGH, cpu_to_le32(*rv2p_code));
2867 REG_WR(bp, BNX2_RV2P_INSTR_LOW, cpu_to_le32(*rv2p_code));
2870 if (rv2p_proc == RV2P_PROC1) {
2871 val = (i / 8) | BNX2_RV2P_PROC1_ADDR_CMD_RDWR;
2872 REG_WR(bp, BNX2_RV2P_PROC1_ADDR_CMD, val);
2875 val = (i / 8) | BNX2_RV2P_PROC2_ADDR_CMD_RDWR;
2876 REG_WR(bp, BNX2_RV2P_PROC2_ADDR_CMD, val);
2880 /* Reset the processor, un-stall is done later. */
2881 if (rv2p_proc == RV2P_PROC1) {
2882 REG_WR(bp, BNX2_RV2P_COMMAND, BNX2_RV2P_COMMAND_PROC1_RESET);
2885 REG_WR(bp, BNX2_RV2P_COMMAND, BNX2_RV2P_COMMAND_PROC2_RESET);
2890 load_cpu_fw(struct bnx2 *bp, struct cpu_reg *cpu_reg, struct fw_info *fw)
2897 val = REG_RD_IND(bp, cpu_reg->mode);
2898 val |= cpu_reg->mode_value_halt;
2899 REG_WR_IND(bp, cpu_reg->mode, val);
2900 REG_WR_IND(bp, cpu_reg->state, cpu_reg->state_value_clear);
2902 /* Load the Text area. */
2903 offset = cpu_reg->spad_base + (fw->text_addr - cpu_reg->mips_view_base);
2908 rc = bnx2_gunzip(bp, fw->gz_text, fw->gz_text_len, &text,
2918 for (j = 0; j < (fw->text_len / 4); j++, offset += 4) {
2919 REG_WR_IND(bp, offset, cpu_to_le32(fw->text[j]));
2923 /* Load the Data area. */
2924 offset = cpu_reg->spad_base + (fw->data_addr - cpu_reg->mips_view_base);
2928 for (j = 0; j < (fw->data_len / 4); j++, offset += 4) {
2929 REG_WR_IND(bp, offset, fw->data[j]);
2933 /* Load the SBSS area. */
2934 offset = cpu_reg->spad_base + (fw->sbss_addr - cpu_reg->mips_view_base);
2938 for (j = 0; j < (fw->sbss_len / 4); j++, offset += 4) {
2939 REG_WR_IND(bp, offset, fw->sbss[j]);
2943 /* Load the BSS area. */
2944 offset = cpu_reg->spad_base + (fw->bss_addr - cpu_reg->mips_view_base);
2948 for (j = 0; j < (fw->bss_len/4); j++, offset += 4) {
2949 REG_WR_IND(bp, offset, fw->bss[j]);
2953 /* Load the Read-Only area. */
2954 offset = cpu_reg->spad_base +
2955 (fw->rodata_addr - cpu_reg->mips_view_base);
2959 for (j = 0; j < (fw->rodata_len / 4); j++, offset += 4) {
2960 REG_WR_IND(bp, offset, fw->rodata[j]);
2964 /* Clear the pre-fetch instruction. */
2965 REG_WR_IND(bp, cpu_reg->inst, 0);
2966 REG_WR_IND(bp, cpu_reg->pc, fw->start_addr);
2968 /* Start the CPU. */
2969 val = REG_RD_IND(bp, cpu_reg->mode);
2970 val &= ~cpu_reg->mode_value_halt;
2971 REG_WR_IND(bp, cpu_reg->state, cpu_reg->state_value_clear);
2972 REG_WR_IND(bp, cpu_reg->mode, val);
2978 bnx2_init_cpus(struct bnx2 *bp)
2980 struct cpu_reg cpu_reg;
2986 if ((rc = bnx2_gunzip_init(bp)) != 0)
2989 /* Initialize the RV2P processor. */
2990 rc = bnx2_gunzip(bp, bnx2_rv2p_proc1, sizeof(bnx2_rv2p_proc1), &text,
2995 load_rv2p_fw(bp, text, text_len, RV2P_PROC1);
2997 rc = bnx2_gunzip(bp, bnx2_rv2p_proc2, sizeof(bnx2_rv2p_proc2), &text,
3002 load_rv2p_fw(bp, text, text_len, RV2P_PROC2);
3004 /* Initialize the RX Processor. */
3005 cpu_reg.mode = BNX2_RXP_CPU_MODE;
3006 cpu_reg.mode_value_halt = BNX2_RXP_CPU_MODE_SOFT_HALT;
3007 cpu_reg.mode_value_sstep = BNX2_RXP_CPU_MODE_STEP_ENA;
3008 cpu_reg.state = BNX2_RXP_CPU_STATE;
3009 cpu_reg.state_value_clear = 0xffffff;
3010 cpu_reg.gpr0 = BNX2_RXP_CPU_REG_FILE;
3011 cpu_reg.evmask = BNX2_RXP_CPU_EVENT_MASK;
3012 cpu_reg.pc = BNX2_RXP_CPU_PROGRAM_COUNTER;
3013 cpu_reg.inst = BNX2_RXP_CPU_INSTRUCTION;
3014 cpu_reg.bp = BNX2_RXP_CPU_HW_BREAKPOINT;
3015 cpu_reg.spad_base = BNX2_RXP_SCRATCH;
3016 cpu_reg.mips_view_base = 0x8000000;
3018 if (CHIP_NUM(bp) == CHIP_NUM_5709)
3019 fw = &bnx2_rxp_fw_09;
3021 fw = &bnx2_rxp_fw_06;
3023 rc = load_cpu_fw(bp, &cpu_reg, fw);
3027 /* Initialize the TX Processor. */
3028 cpu_reg.mode = BNX2_TXP_CPU_MODE;
3029 cpu_reg.mode_value_halt = BNX2_TXP_CPU_MODE_SOFT_HALT;
3030 cpu_reg.mode_value_sstep = BNX2_TXP_CPU_MODE_STEP_ENA;
3031 cpu_reg.state = BNX2_TXP_CPU_STATE;
3032 cpu_reg.state_value_clear = 0xffffff;
3033 cpu_reg.gpr0 = BNX2_TXP_CPU_REG_FILE;
3034 cpu_reg.evmask = BNX2_TXP_CPU_EVENT_MASK;
3035 cpu_reg.pc = BNX2_TXP_CPU_PROGRAM_COUNTER;
3036 cpu_reg.inst = BNX2_TXP_CPU_INSTRUCTION;
3037 cpu_reg.bp = BNX2_TXP_CPU_HW_BREAKPOINT;
3038 cpu_reg.spad_base = BNX2_TXP_SCRATCH;
3039 cpu_reg.mips_view_base = 0x8000000;
3041 if (CHIP_NUM(bp) == CHIP_NUM_5709)
3042 fw = &bnx2_txp_fw_09;
3044 fw = &bnx2_txp_fw_06;
3046 rc = load_cpu_fw(bp, &cpu_reg, fw);
3050 /* Initialize the TX Patch-up Processor. */
3051 cpu_reg.mode = BNX2_TPAT_CPU_MODE;
3052 cpu_reg.mode_value_halt = BNX2_TPAT_CPU_MODE_SOFT_HALT;
3053 cpu_reg.mode_value_sstep = BNX2_TPAT_CPU_MODE_STEP_ENA;
3054 cpu_reg.state = BNX2_TPAT_CPU_STATE;
3055 cpu_reg.state_value_clear = 0xffffff;
3056 cpu_reg.gpr0 = BNX2_TPAT_CPU_REG_FILE;
3057 cpu_reg.evmask = BNX2_TPAT_CPU_EVENT_MASK;
3058 cpu_reg.pc = BNX2_TPAT_CPU_PROGRAM_COUNTER;
3059 cpu_reg.inst = BNX2_TPAT_CPU_INSTRUCTION;
3060 cpu_reg.bp = BNX2_TPAT_CPU_HW_BREAKPOINT;
3061 cpu_reg.spad_base = BNX2_TPAT_SCRATCH;
3062 cpu_reg.mips_view_base = 0x8000000;
3064 if (CHIP_NUM(bp) == CHIP_NUM_5709)
3065 fw = &bnx2_tpat_fw_09;
3067 fw = &bnx2_tpat_fw_06;
3069 rc = load_cpu_fw(bp, &cpu_reg, fw);
3073 /* Initialize the Completion Processor. */
3074 cpu_reg.mode = BNX2_COM_CPU_MODE;
3075 cpu_reg.mode_value_halt = BNX2_COM_CPU_MODE_SOFT_HALT;
3076 cpu_reg.mode_value_sstep = BNX2_COM_CPU_MODE_STEP_ENA;
3077 cpu_reg.state = BNX2_COM_CPU_STATE;
3078 cpu_reg.state_value_clear = 0xffffff;
3079 cpu_reg.gpr0 = BNX2_COM_CPU_REG_FILE;
3080 cpu_reg.evmask = BNX2_COM_CPU_EVENT_MASK;
3081 cpu_reg.pc = BNX2_COM_CPU_PROGRAM_COUNTER;
3082 cpu_reg.inst = BNX2_COM_CPU_INSTRUCTION;
3083 cpu_reg.bp = BNX2_COM_CPU_HW_BREAKPOINT;
3084 cpu_reg.spad_base = BNX2_COM_SCRATCH;
3085 cpu_reg.mips_view_base = 0x8000000;
3087 if (CHIP_NUM(bp) == CHIP_NUM_5709)
3088 fw = &bnx2_com_fw_09;
3090 fw = &bnx2_com_fw_06;
3092 rc = load_cpu_fw(bp, &cpu_reg, fw);
3096 /* Initialize the Command Processor. */
3097 cpu_reg.mode = BNX2_CP_CPU_MODE;
3098 cpu_reg.mode_value_halt = BNX2_CP_CPU_MODE_SOFT_HALT;
3099 cpu_reg.mode_value_sstep = BNX2_CP_CPU_MODE_STEP_ENA;
3100 cpu_reg.state = BNX2_CP_CPU_STATE;
3101 cpu_reg.state_value_clear = 0xffffff;
3102 cpu_reg.gpr0 = BNX2_CP_CPU_REG_FILE;
3103 cpu_reg.evmask = BNX2_CP_CPU_EVENT_MASK;
3104 cpu_reg.pc = BNX2_CP_CPU_PROGRAM_COUNTER;
3105 cpu_reg.inst = BNX2_CP_CPU_INSTRUCTION;
3106 cpu_reg.bp = BNX2_CP_CPU_HW_BREAKPOINT;
3107 cpu_reg.spad_base = BNX2_CP_SCRATCH;
3108 cpu_reg.mips_view_base = 0x8000000;
3110 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
3111 fw = &bnx2_cp_fw_09;
3113 rc = load_cpu_fw(bp, &cpu_reg, fw);
3118 bnx2_gunzip_end(bp);
3123 bnx2_set_power_state(struct bnx2 *bp, pci_power_t state)
3127 pci_read_config_word(bp->pdev, bp->pm_cap + PCI_PM_CTRL, &pmcsr);
3133 pci_write_config_word(bp->pdev, bp->pm_cap + PCI_PM_CTRL,
3134 (pmcsr & ~PCI_PM_CTRL_STATE_MASK) |
3135 PCI_PM_CTRL_PME_STATUS);
3137 if (pmcsr & PCI_PM_CTRL_STATE_MASK)
3138 /* delay required during transition out of D3hot */
3141 val = REG_RD(bp, BNX2_EMAC_MODE);
3142 val |= BNX2_EMAC_MODE_MPKT_RCVD | BNX2_EMAC_MODE_ACPI_RCVD;
3143 val &= ~BNX2_EMAC_MODE_MPKT;
3144 REG_WR(bp, BNX2_EMAC_MODE, val);
3146 val = REG_RD(bp, BNX2_RPM_CONFIG);
3147 val &= ~BNX2_RPM_CONFIG_ACPI_ENA;
3148 REG_WR(bp, BNX2_RPM_CONFIG, val);
3159 autoneg = bp->autoneg;
3160 advertising = bp->advertising;
3162 bp->autoneg = AUTONEG_SPEED;
3163 bp->advertising = ADVERTISED_10baseT_Half |
3164 ADVERTISED_10baseT_Full |
3165 ADVERTISED_100baseT_Half |
3166 ADVERTISED_100baseT_Full |
3169 bnx2_setup_copper_phy(bp);
3171 bp->autoneg = autoneg;
3172 bp->advertising = advertising;
3174 bnx2_set_mac_addr(bp);
3176 val = REG_RD(bp, BNX2_EMAC_MODE);
3178 /* Enable port mode. */
3179 val &= ~BNX2_EMAC_MODE_PORT;
3180 val |= BNX2_EMAC_MODE_PORT_MII |
3181 BNX2_EMAC_MODE_MPKT_RCVD |
3182 BNX2_EMAC_MODE_ACPI_RCVD |
3183 BNX2_EMAC_MODE_MPKT;
3185 REG_WR(bp, BNX2_EMAC_MODE, val);
3187 /* receive all multicast */
3188 for (i = 0; i < NUM_MC_HASH_REGISTERS; i++) {
3189 REG_WR(bp, BNX2_EMAC_MULTICAST_HASH0 + (i * 4),
3192 REG_WR(bp, BNX2_EMAC_RX_MODE,
3193 BNX2_EMAC_RX_MODE_SORT_MODE);
3195 val = 1 | BNX2_RPM_SORT_USER0_BC_EN |
3196 BNX2_RPM_SORT_USER0_MC_EN;
3197 REG_WR(bp, BNX2_RPM_SORT_USER0, 0x0);
3198 REG_WR(bp, BNX2_RPM_SORT_USER0, val);
3199 REG_WR(bp, BNX2_RPM_SORT_USER0, val |
3200 BNX2_RPM_SORT_USER0_ENA);
3202 /* Need to enable EMAC and RPM for WOL. */
3203 REG_WR(bp, BNX2_MISC_ENABLE_SET_BITS,
3204 BNX2_MISC_ENABLE_SET_BITS_RX_PARSER_MAC_ENABLE |
3205 BNX2_MISC_ENABLE_SET_BITS_TX_HEADER_Q_ENABLE |
3206 BNX2_MISC_ENABLE_SET_BITS_EMAC_ENABLE);
3208 val = REG_RD(bp, BNX2_RPM_CONFIG);
3209 val &= ~BNX2_RPM_CONFIG_ACPI_ENA;
3210 REG_WR(bp, BNX2_RPM_CONFIG, val);
3212 wol_msg = BNX2_DRV_MSG_CODE_SUSPEND_WOL;
3215 wol_msg = BNX2_DRV_MSG_CODE_SUSPEND_NO_WOL;
3218 if (!(bp->flags & NO_WOL_FLAG))
3219 bnx2_fw_sync(bp, BNX2_DRV_MSG_DATA_WAIT3 | wol_msg, 0);
3221 pmcsr &= ~PCI_PM_CTRL_STATE_MASK;
3222 if ((CHIP_ID(bp) == CHIP_ID_5706_A0) ||
3223 (CHIP_ID(bp) == CHIP_ID_5706_A1)) {
3232 pmcsr |= PCI_PM_CTRL_PME_ENABLE;
3234 pci_write_config_word(bp->pdev, bp->pm_cap + PCI_PM_CTRL,
3237 /* No more memory access after this point until
3238 * device is brought back to D0.
3250 bnx2_acquire_nvram_lock(struct bnx2 *bp)
3255 /* Request access to the flash interface. */
3256 REG_WR(bp, BNX2_NVM_SW_ARB, BNX2_NVM_SW_ARB_ARB_REQ_SET2);
3257 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
3258 val = REG_RD(bp, BNX2_NVM_SW_ARB);
3259 if (val & BNX2_NVM_SW_ARB_ARB_ARB2)
3265 if (j >= NVRAM_TIMEOUT_COUNT)
3272 bnx2_release_nvram_lock(struct bnx2 *bp)
3277 /* Relinquish nvram interface. */
3278 REG_WR(bp, BNX2_NVM_SW_ARB, BNX2_NVM_SW_ARB_ARB_REQ_CLR2);
3280 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
3281 val = REG_RD(bp, BNX2_NVM_SW_ARB);
3282 if (!(val & BNX2_NVM_SW_ARB_ARB_ARB2))
3288 if (j >= NVRAM_TIMEOUT_COUNT)
3296 bnx2_enable_nvram_write(struct bnx2 *bp)
3300 val = REG_RD(bp, BNX2_MISC_CFG);
3301 REG_WR(bp, BNX2_MISC_CFG, val | BNX2_MISC_CFG_NVM_WR_EN_PCI);
3303 if (bp->flash_info->flags & BNX2_NV_WREN) {
3306 REG_WR(bp, BNX2_NVM_COMMAND, BNX2_NVM_COMMAND_DONE);
3307 REG_WR(bp, BNX2_NVM_COMMAND,
3308 BNX2_NVM_COMMAND_WREN | BNX2_NVM_COMMAND_DOIT);
3310 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
3313 val = REG_RD(bp, BNX2_NVM_COMMAND);
3314 if (val & BNX2_NVM_COMMAND_DONE)
3318 if (j >= NVRAM_TIMEOUT_COUNT)
3325 bnx2_disable_nvram_write(struct bnx2 *bp)
3329 val = REG_RD(bp, BNX2_MISC_CFG);
3330 REG_WR(bp, BNX2_MISC_CFG, val & ~BNX2_MISC_CFG_NVM_WR_EN);
3335 bnx2_enable_nvram_access(struct bnx2 *bp)
3339 val = REG_RD(bp, BNX2_NVM_ACCESS_ENABLE);
3340 /* Enable both bits, even on read. */
3341 REG_WR(bp, BNX2_NVM_ACCESS_ENABLE,
3342 val | BNX2_NVM_ACCESS_ENABLE_EN | BNX2_NVM_ACCESS_ENABLE_WR_EN);
3346 bnx2_disable_nvram_access(struct bnx2 *bp)
3350 val = REG_RD(bp, BNX2_NVM_ACCESS_ENABLE);
3351 /* Disable both bits, even after read. */
3352 REG_WR(bp, BNX2_NVM_ACCESS_ENABLE,
3353 val & ~(BNX2_NVM_ACCESS_ENABLE_EN |
3354 BNX2_NVM_ACCESS_ENABLE_WR_EN));
3358 bnx2_nvram_erase_page(struct bnx2 *bp, u32 offset)
3363 if (bp->flash_info->flags & BNX2_NV_BUFFERED)
3364 /* Buffered flash, no erase needed */
3367 /* Build an erase command */
3368 cmd = BNX2_NVM_COMMAND_ERASE | BNX2_NVM_COMMAND_WR |
3369 BNX2_NVM_COMMAND_DOIT;
3371 /* Need to clear DONE bit separately. */
3372 REG_WR(bp, BNX2_NVM_COMMAND, BNX2_NVM_COMMAND_DONE);
3374 /* Address of the NVRAM to read from. */
3375 REG_WR(bp, BNX2_NVM_ADDR, offset & BNX2_NVM_ADDR_NVM_ADDR_VALUE);
3377 /* Issue an erase command. */
3378 REG_WR(bp, BNX2_NVM_COMMAND, cmd);
3380 /* Wait for completion. */
3381 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
3386 val = REG_RD(bp, BNX2_NVM_COMMAND);
3387 if (val & BNX2_NVM_COMMAND_DONE)
3391 if (j >= NVRAM_TIMEOUT_COUNT)
3398 bnx2_nvram_read_dword(struct bnx2 *bp, u32 offset, u8 *ret_val, u32 cmd_flags)
3403 /* Build the command word. */
3404 cmd = BNX2_NVM_COMMAND_DOIT | cmd_flags;
3406 /* Calculate an offset of a buffered flash, not needed for 5709. */
3407 if (bp->flash_info->flags & BNX2_NV_TRANSLATE) {
3408 offset = ((offset / bp->flash_info->page_size) <<
3409 bp->flash_info->page_bits) +
3410 (offset % bp->flash_info->page_size);
3413 /* Need to clear DONE bit separately. */
3414 REG_WR(bp, BNX2_NVM_COMMAND, BNX2_NVM_COMMAND_DONE);
3416 /* Address of the NVRAM to read from. */
3417 REG_WR(bp, BNX2_NVM_ADDR, offset & BNX2_NVM_ADDR_NVM_ADDR_VALUE);
3419 /* Issue a read command. */
3420 REG_WR(bp, BNX2_NVM_COMMAND, cmd);
3422 /* Wait for completion. */
3423 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
3428 val = REG_RD(bp, BNX2_NVM_COMMAND);
3429 if (val & BNX2_NVM_COMMAND_DONE) {
3430 val = REG_RD(bp, BNX2_NVM_READ);
3432 val = be32_to_cpu(val);
3433 memcpy(ret_val, &val, 4);
3437 if (j >= NVRAM_TIMEOUT_COUNT)
3445 bnx2_nvram_write_dword(struct bnx2 *bp, u32 offset, u8 *val, u32 cmd_flags)
3450 /* Build the command word. */
3451 cmd = BNX2_NVM_COMMAND_DOIT | BNX2_NVM_COMMAND_WR | cmd_flags;
3453 /* Calculate an offset of a buffered flash, not needed for 5709. */
3454 if (bp->flash_info->flags & BNX2_NV_TRANSLATE) {
3455 offset = ((offset / bp->flash_info->page_size) <<
3456 bp->flash_info->page_bits) +
3457 (offset % bp->flash_info->page_size);
3460 /* Need to clear DONE bit separately. */
3461 REG_WR(bp, BNX2_NVM_COMMAND, BNX2_NVM_COMMAND_DONE);
3463 memcpy(&val32, val, 4);
3464 val32 = cpu_to_be32(val32);
3466 /* Write the data. */
3467 REG_WR(bp, BNX2_NVM_WRITE, val32);
3469 /* Address of the NVRAM to write to. */
3470 REG_WR(bp, BNX2_NVM_ADDR, offset & BNX2_NVM_ADDR_NVM_ADDR_VALUE);
3472 /* Issue the write command. */
3473 REG_WR(bp, BNX2_NVM_COMMAND, cmd);
3475 /* Wait for completion. */
3476 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
3479 if (REG_RD(bp, BNX2_NVM_COMMAND) & BNX2_NVM_COMMAND_DONE)
3482 if (j >= NVRAM_TIMEOUT_COUNT)
3489 bnx2_init_nvram(struct bnx2 *bp)
3492 int j, entry_count, rc = 0;
3493 struct flash_spec *flash;
3495 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
3496 bp->flash_info = &flash_5709;
3497 goto get_flash_size;
3500 /* Determine the selected interface. */
3501 val = REG_RD(bp, BNX2_NVM_CFG1);
3503 entry_count = sizeof(flash_table) / sizeof(struct flash_spec);
3505 if (val & 0x40000000) {
3507 /* Flash interface has been reconfigured */
3508 for (j = 0, flash = &flash_table[0]; j < entry_count;
3510 if ((val & FLASH_BACKUP_STRAP_MASK) ==
3511 (flash->config1 & FLASH_BACKUP_STRAP_MASK)) {
3512 bp->flash_info = flash;
3519 /* Not yet been reconfigured */
3521 if (val & (1 << 23))
3522 mask = FLASH_BACKUP_STRAP_MASK;
3524 mask = FLASH_STRAP_MASK;
3526 for (j = 0, flash = &flash_table[0]; j < entry_count;
3529 if ((val & mask) == (flash->strapping & mask)) {
3530 bp->flash_info = flash;
3532 /* Request access to the flash interface. */
3533 if ((rc = bnx2_acquire_nvram_lock(bp)) != 0)
3536 /* Enable access to flash interface */
3537 bnx2_enable_nvram_access(bp);
3539 /* Reconfigure the flash interface */
3540 REG_WR(bp, BNX2_NVM_CFG1, flash->config1);
3541 REG_WR(bp, BNX2_NVM_CFG2, flash->config2);
3542 REG_WR(bp, BNX2_NVM_CFG3, flash->config3);
3543 REG_WR(bp, BNX2_NVM_WRITE1, flash->write1);
3545 /* Disable access to flash interface */
3546 bnx2_disable_nvram_access(bp);
3547 bnx2_release_nvram_lock(bp);
3552 } /* if (val & 0x40000000) */
3554 if (j == entry_count) {
3555 bp->flash_info = NULL;
3556 printk(KERN_ALERT PFX "Unknown flash/EEPROM type.\n");
3561 val = REG_RD_IND(bp, bp->shmem_base + BNX2_SHARED_HW_CFG_CONFIG2);
3562 val &= BNX2_SHARED_HW_CFG2_NVM_SIZE_MASK;
3564 bp->flash_size = val;
3566 bp->flash_size = bp->flash_info->total_size;
3572 bnx2_nvram_read(struct bnx2 *bp, u32 offset, u8 *ret_buf,
3576 u32 cmd_flags, offset32, len32, extra;
3581 /* Request access to the flash interface. */
3582 if ((rc = bnx2_acquire_nvram_lock(bp)) != 0)
3585 /* Enable access to flash interface */
3586 bnx2_enable_nvram_access(bp);
3599 pre_len = 4 - (offset & 3);
3601 if (pre_len >= len32) {
3603 cmd_flags = BNX2_NVM_COMMAND_FIRST |
3604 BNX2_NVM_COMMAND_LAST;
3607 cmd_flags = BNX2_NVM_COMMAND_FIRST;
3610 rc = bnx2_nvram_read_dword(bp, offset32, buf, cmd_flags);
3615 memcpy(ret_buf, buf + (offset & 3), pre_len);
3622 extra = 4 - (len32 & 3);
3623 len32 = (len32 + 4) & ~3;
3630 cmd_flags = BNX2_NVM_COMMAND_LAST;
3632 cmd_flags = BNX2_NVM_COMMAND_FIRST |
3633 BNX2_NVM_COMMAND_LAST;
3635 rc = bnx2_nvram_read_dword(bp, offset32, buf, cmd_flags);
3637 memcpy(ret_buf, buf, 4 - extra);
3639 else if (len32 > 0) {
3642 /* Read the first word. */
3646 cmd_flags = BNX2_NVM_COMMAND_FIRST;
3648 rc = bnx2_nvram_read_dword(bp, offset32, ret_buf, cmd_flags);
3650 /* Advance to the next dword. */
3655 while (len32 > 4 && rc == 0) {
3656 rc = bnx2_nvram_read_dword(bp, offset32, ret_buf, 0);
3658 /* Advance to the next dword. */
3667 cmd_flags = BNX2_NVM_COMMAND_LAST;
3668 rc = bnx2_nvram_read_dword(bp, offset32, buf, cmd_flags);
3670 memcpy(ret_buf, buf, 4 - extra);
3673 /* Disable access to flash interface */
3674 bnx2_disable_nvram_access(bp);
3676 bnx2_release_nvram_lock(bp);
3682 bnx2_nvram_write(struct bnx2 *bp, u32 offset, u8 *data_buf,
3685 u32 written, offset32, len32;
3686 u8 *buf, start[4], end[4], *align_buf = NULL, *flash_buffer = NULL;
3688 int align_start, align_end;
3693 align_start = align_end = 0;
3695 if ((align_start = (offset32 & 3))) {
3697 len32 += align_start;
3700 if ((rc = bnx2_nvram_read(bp, offset32, start, 4)))
3705 align_end = 4 - (len32 & 3);
3707 if ((rc = bnx2_nvram_read(bp, offset32 + len32 - 4, end, 4)))
3711 if (align_start || align_end) {
3712 align_buf = kmalloc(len32, GFP_KERNEL);
3713 if (align_buf == NULL)
3716 memcpy(align_buf, start, 4);
3719 memcpy(align_buf + len32 - 4, end, 4);
3721 memcpy(align_buf + align_start, data_buf, buf_size);
3725 if (!(bp->flash_info->flags & BNX2_NV_BUFFERED)) {
3726 flash_buffer = kmalloc(264, GFP_KERNEL);
3727 if (flash_buffer == NULL) {
3729 goto nvram_write_end;
3734 while ((written < len32) && (rc == 0)) {
3735 u32 page_start, page_end, data_start, data_end;
3736 u32 addr, cmd_flags;
3739 /* Find the page_start addr */
3740 page_start = offset32 + written;
3741 page_start -= (page_start % bp->flash_info->page_size);
3742 /* Find the page_end addr */
3743 page_end = page_start + bp->flash_info->page_size;
3744 /* Find the data_start addr */
3745 data_start = (written == 0) ? offset32 : page_start;
3746 /* Find the data_end addr */
3747 data_end = (page_end > offset32 + len32) ?
3748 (offset32 + len32) : page_end;
3750 /* Request access to the flash interface. */
3751 if ((rc = bnx2_acquire_nvram_lock(bp)) != 0)
3752 goto nvram_write_end;
3754 /* Enable access to flash interface */
3755 bnx2_enable_nvram_access(bp);
3757 cmd_flags = BNX2_NVM_COMMAND_FIRST;
3758 if (!(bp->flash_info->flags & BNX2_NV_BUFFERED)) {
3761 /* Read the whole page into the buffer
3762 * (non-buffer flash only) */
3763 for (j = 0; j < bp->flash_info->page_size; j += 4) {
3764 if (j == (bp->flash_info->page_size - 4)) {
3765 cmd_flags |= BNX2_NVM_COMMAND_LAST;
3767 rc = bnx2_nvram_read_dword(bp,
3773 goto nvram_write_end;
3779 /* Enable writes to flash interface (unlock write-protect) */
3780 if ((rc = bnx2_enable_nvram_write(bp)) != 0)
3781 goto nvram_write_end;
3783 /* Loop to write back the buffer data from page_start to
3786 if (!(bp->flash_info->flags & BNX2_NV_BUFFERED)) {
3787 /* Erase the page */
3788 if ((rc = bnx2_nvram_erase_page(bp, page_start)) != 0)
3789 goto nvram_write_end;
3791 /* Re-enable the write again for the actual write */
3792 bnx2_enable_nvram_write(bp);
3794 for (addr = page_start; addr < data_start;
3795 addr += 4, i += 4) {
3797 rc = bnx2_nvram_write_dword(bp, addr,
3798 &flash_buffer[i], cmd_flags);
3801 goto nvram_write_end;
3807 /* Loop to write the new data from data_start to data_end */
3808 for (addr = data_start; addr < data_end; addr += 4, i += 4) {
3809 if ((addr == page_end - 4) ||
3810 ((bp->flash_info->flags & BNX2_NV_BUFFERED) &&
3811 (addr == data_end - 4))) {
3813 cmd_flags |= BNX2_NVM_COMMAND_LAST;
3815 rc = bnx2_nvram_write_dword(bp, addr, buf,
3819 goto nvram_write_end;
3825 /* Loop to write back the buffer data from data_end
3827 if (!(bp->flash_info->flags & BNX2_NV_BUFFERED)) {
3828 for (addr = data_end; addr < page_end;
3829 addr += 4, i += 4) {
3831 if (addr == page_end-4) {
3832 cmd_flags = BNX2_NVM_COMMAND_LAST;
3834 rc = bnx2_nvram_write_dword(bp, addr,
3835 &flash_buffer[i], cmd_flags);
3838 goto nvram_write_end;
3844 /* Disable writes to flash interface (lock write-protect) */
3845 bnx2_disable_nvram_write(bp);
3847 /* Disable access to flash interface */
3848 bnx2_disable_nvram_access(bp);
3849 bnx2_release_nvram_lock(bp);
3851 /* Increment written */
3852 written += data_end - data_start;
3856 kfree(flash_buffer);
3862 bnx2_init_remote_phy(struct bnx2 *bp)
3866 bp->phy_flags &= ~REMOTE_PHY_CAP_FLAG;
3867 if (!(bp->phy_flags & PHY_SERDES_FLAG))
3870 val = REG_RD_IND(bp, bp->shmem_base + BNX2_FW_CAP_MB);
3871 if ((val & BNX2_FW_CAP_SIGNATURE_MASK) != BNX2_FW_CAP_SIGNATURE)
3874 if (val & BNX2_FW_CAP_REMOTE_PHY_CAPABLE) {
3875 if (netif_running(bp->dev)) {
3876 val = BNX2_DRV_ACK_CAP_SIGNATURE |
3877 BNX2_FW_CAP_REMOTE_PHY_CAPABLE;
3878 REG_WR_IND(bp, bp->shmem_base + BNX2_DRV_ACK_CAP_MB,
3881 bp->phy_flags |= REMOTE_PHY_CAP_FLAG;
3883 val = REG_RD_IND(bp, bp->shmem_base + BNX2_LINK_STATUS);
3884 if (val & BNX2_LINK_STATUS_SERDES_LINK)
3885 bp->phy_port = PORT_FIBRE;
3887 bp->phy_port = PORT_TP;
3892 bnx2_reset_chip(struct bnx2 *bp, u32 reset_code)
3897 /* Wait for the current PCI transaction to complete before
3898 * issuing a reset. */
3899 REG_WR(bp, BNX2_MISC_ENABLE_CLR_BITS,
3900 BNX2_MISC_ENABLE_CLR_BITS_TX_DMA_ENABLE |
3901 BNX2_MISC_ENABLE_CLR_BITS_DMA_ENGINE_ENABLE |
3902 BNX2_MISC_ENABLE_CLR_BITS_RX_DMA_ENABLE |
3903 BNX2_MISC_ENABLE_CLR_BITS_HOST_COALESCE_ENABLE);
3904 val = REG_RD(bp, BNX2_MISC_ENABLE_CLR_BITS);
3907 /* Wait for the firmware to tell us it is ok to issue a reset. */
3908 bnx2_fw_sync(bp, BNX2_DRV_MSG_DATA_WAIT0 | reset_code, 1);
3910 /* Deposit a driver reset signature so the firmware knows that
3911 * this is a soft reset. */
3912 REG_WR_IND(bp, bp->shmem_base + BNX2_DRV_RESET_SIGNATURE,
3913 BNX2_DRV_RESET_SIGNATURE_MAGIC);
3915 /* Do a dummy read to force the chip to complete all current transaction
3916 * before we issue a reset. */
3917 val = REG_RD(bp, BNX2_MISC_ID);
3919 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
3920 REG_WR(bp, BNX2_MISC_COMMAND, BNX2_MISC_COMMAND_SW_RESET);
3921 REG_RD(bp, BNX2_MISC_COMMAND);
3924 val = BNX2_PCICFG_MISC_CONFIG_REG_WINDOW_ENA |
3925 BNX2_PCICFG_MISC_CONFIG_TARGET_MB_WORD_SWAP;
3927 pci_write_config_dword(bp->pdev, BNX2_PCICFG_MISC_CONFIG, val);
3930 val = BNX2_PCICFG_MISC_CONFIG_CORE_RST_REQ |
3931 BNX2_PCICFG_MISC_CONFIG_REG_WINDOW_ENA |
3932 BNX2_PCICFG_MISC_CONFIG_TARGET_MB_WORD_SWAP;
3935 REG_WR(bp, BNX2_PCICFG_MISC_CONFIG, val);
3937 if ((CHIP_ID(bp) == CHIP_ID_5706_A0) ||
3938 (CHIP_ID(bp) == CHIP_ID_5706_A1)) {
3939 current->state = TASK_UNINTERRUPTIBLE;
3940 schedule_timeout(HZ / 50);
3943 /* Reset takes approximate 30 usec */
3944 for (i = 0; i < 10; i++) {
3945 val = REG_RD(bp, BNX2_PCICFG_MISC_CONFIG);
3946 if ((val & (BNX2_PCICFG_MISC_CONFIG_CORE_RST_REQ |
3947 BNX2_PCICFG_MISC_CONFIG_CORE_RST_BSY)) == 0)
3952 if (val & (BNX2_PCICFG_MISC_CONFIG_CORE_RST_REQ |
3953 BNX2_PCICFG_MISC_CONFIG_CORE_RST_BSY)) {
3954 printk(KERN_ERR PFX "Chip reset did not complete\n");
3959 /* Make sure byte swapping is properly configured. */
3960 val = REG_RD(bp, BNX2_PCI_SWAP_DIAG0);
3961 if (val != 0x01020304) {
3962 printk(KERN_ERR PFX "Chip not in correct endian mode\n");
3966 /* Wait for the firmware to finish its initialization. */
3967 rc = bnx2_fw_sync(bp, BNX2_DRV_MSG_DATA_WAIT1 | reset_code, 0);
3971 spin_lock_bh(&bp->phy_lock);
3972 bnx2_init_remote_phy(bp);
3973 if (bp->phy_flags & REMOTE_PHY_CAP_FLAG)
3974 bnx2_set_default_remote_link(bp);
3975 spin_unlock_bh(&bp->phy_lock);
3977 if (CHIP_ID(bp) == CHIP_ID_5706_A0) {
3978 /* Adjust the voltage regular to two steps lower. The default
3979 * of this register is 0x0000000e. */
3980 REG_WR(bp, BNX2_MISC_VREG_CONTROL, 0x000000fa);
3982 /* Remove bad rbuf memory from the free pool. */
3983 rc = bnx2_alloc_bad_rbuf(bp);
3990 bnx2_init_chip(struct bnx2 *bp)
3995 /* Make sure the interrupt is not active. */
3996 REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD, BNX2_PCICFG_INT_ACK_CMD_MASK_INT);
3998 val = BNX2_DMA_CONFIG_DATA_BYTE_SWAP |
3999 BNX2_DMA_CONFIG_DATA_WORD_SWAP |
4001 BNX2_DMA_CONFIG_CNTL_BYTE_SWAP |
4003 BNX2_DMA_CONFIG_CNTL_WORD_SWAP |
4004 DMA_READ_CHANS << 12 |
4005 DMA_WRITE_CHANS << 16;
4007 val |= (0x2 << 20) | (1 << 11);
4009 if ((bp->flags & PCIX_FLAG) && (bp->bus_speed_mhz == 133))
4012 if ((CHIP_NUM(bp) == CHIP_NUM_5706) &&
4013 (CHIP_ID(bp) != CHIP_ID_5706_A0) && !(bp->flags & PCIX_FLAG))
4014 val |= BNX2_DMA_CONFIG_CNTL_PING_PONG_DMA;
4016 REG_WR(bp, BNX2_DMA_CONFIG, val);
4018 if (CHIP_ID(bp) == CHIP_ID_5706_A0) {
4019 val = REG_RD(bp, BNX2_TDMA_CONFIG);
4020 val |= BNX2_TDMA_CONFIG_ONE_DMA;
4021 REG_WR(bp, BNX2_TDMA_CONFIG, val);
4024 if (bp->flags & PCIX_FLAG) {
4027 pci_read_config_word(bp->pdev, bp->pcix_cap + PCI_X_CMD,
4029 pci_write_config_word(bp->pdev, bp->pcix_cap + PCI_X_CMD,
4030 val16 & ~PCI_X_CMD_ERO);
4033 REG_WR(bp, BNX2_MISC_ENABLE_SET_BITS,
4034 BNX2_MISC_ENABLE_SET_BITS_HOST_COALESCE_ENABLE |
4035 BNX2_MISC_ENABLE_STATUS_BITS_RX_V2P_ENABLE |
4036 BNX2_MISC_ENABLE_STATUS_BITS_CONTEXT_ENABLE);
4038 /* Initialize context mapping and zero out the quick contexts. The
4039 * context block must have already been enabled. */
4040 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
4041 rc = bnx2_init_5709_context(bp);
4045 bnx2_init_context(bp);
4047 if ((rc = bnx2_init_cpus(bp)) != 0)
4050 bnx2_init_nvram(bp);
4052 bnx2_set_mac_addr(bp);
4054 val = REG_RD(bp, BNX2_MQ_CONFIG);
4055 val &= ~BNX2_MQ_CONFIG_KNL_BYP_BLK_SIZE;
4056 val |= BNX2_MQ_CONFIG_KNL_BYP_BLK_SIZE_256;
4057 if (CHIP_ID(bp) == CHIP_ID_5709_A0 || CHIP_ID(bp) == CHIP_ID_5709_A1)
4058 val |= BNX2_MQ_CONFIG_HALT_DIS;
4060 REG_WR(bp, BNX2_MQ_CONFIG, val);
4062 val = 0x10000 + (MAX_CID_CNT * MB_KERNEL_CTX_SIZE);
4063 REG_WR(bp, BNX2_MQ_KNL_BYP_WIND_START, val);
4064 REG_WR(bp, BNX2_MQ_KNL_WIND_END, val);
4066 val = (BCM_PAGE_BITS - 8) << 24;
4067 REG_WR(bp, BNX2_RV2P_CONFIG, val);
4069 /* Configure page size. */
4070 val = REG_RD(bp, BNX2_TBDR_CONFIG);
4071 val &= ~BNX2_TBDR_CONFIG_PAGE_SIZE;
4072 val |= (BCM_PAGE_BITS - 8) << 24 | 0x40;
4073 REG_WR(bp, BNX2_TBDR_CONFIG, val);
4075 val = bp->mac_addr[0] +
4076 (bp->mac_addr[1] << 8) +
4077 (bp->mac_addr[2] << 16) +
4079 (bp->mac_addr[4] << 8) +
4080 (bp->mac_addr[5] << 16);
4081 REG_WR(bp, BNX2_EMAC_BACKOFF_SEED, val);
4083 /* Program the MTU. Also include 4 bytes for CRC32. */
4084 val = bp->dev->mtu + ETH_HLEN + 4;
4085 if (val > (MAX_ETHERNET_PACKET_SIZE + 4))
4086 val |= BNX2_EMAC_RX_MTU_SIZE_JUMBO_ENA;
4087 REG_WR(bp, BNX2_EMAC_RX_MTU_SIZE, val);
4089 bp->last_status_idx = 0;
4090 bp->rx_mode = BNX2_EMAC_RX_MODE_SORT_MODE;
4092 /* Set up how to generate a link change interrupt. */
4093 REG_WR(bp, BNX2_EMAC_ATTENTION_ENA, BNX2_EMAC_ATTENTION_ENA_LINK);
4095 REG_WR(bp, BNX2_HC_STATUS_ADDR_L,
4096 (u64) bp->status_blk_mapping & 0xffffffff);
4097 REG_WR(bp, BNX2_HC_STATUS_ADDR_H, (u64) bp->status_blk_mapping >> 32);
4099 REG_WR(bp, BNX2_HC_STATISTICS_ADDR_L,
4100 (u64) bp->stats_blk_mapping & 0xffffffff);
4101 REG_WR(bp, BNX2_HC_STATISTICS_ADDR_H,
4102 (u64) bp->stats_blk_mapping >> 32);
4104 REG_WR(bp, BNX2_HC_TX_QUICK_CONS_TRIP,
4105 (bp->tx_quick_cons_trip_int << 16) | bp->tx_quick_cons_trip);
4107 REG_WR(bp, BNX2_HC_RX_QUICK_CONS_TRIP,
4108 (bp->rx_quick_cons_trip_int << 16) | bp->rx_quick_cons_trip);
4110 REG_WR(bp, BNX2_HC_COMP_PROD_TRIP,
4111 (bp->comp_prod_trip_int << 16) | bp->comp_prod_trip);
4113 REG_WR(bp, BNX2_HC_TX_TICKS, (bp->tx_ticks_int << 16) | bp->tx_ticks);
4115 REG_WR(bp, BNX2_HC_RX_TICKS, (bp->rx_ticks_int << 16) | bp->rx_ticks);
4117 REG_WR(bp, BNX2_HC_COM_TICKS,
4118 (bp->com_ticks_int << 16) | bp->com_ticks);
4120 REG_WR(bp, BNX2_HC_CMD_TICKS,
4121 (bp->cmd_ticks_int << 16) | bp->cmd_ticks);
4123 if (CHIP_NUM(bp) == CHIP_NUM_5708)
4124 REG_WR(bp, BNX2_HC_STATS_TICKS, 0);
4126 REG_WR(bp, BNX2_HC_STATS_TICKS, bp->stats_ticks & 0xffff00);
4127 REG_WR(bp, BNX2_HC_STAT_COLLECT_TICKS, 0xbb8); /* 3ms */
4129 if (CHIP_ID(bp) == CHIP_ID_5706_A1)
4130 val = BNX2_HC_CONFIG_COLLECT_STATS;
4132 val = BNX2_HC_CONFIG_RX_TMR_MODE | BNX2_HC_CONFIG_TX_TMR_MODE |
4133 BNX2_HC_CONFIG_COLLECT_STATS;
4136 if (bp->flags & ONE_SHOT_MSI_FLAG)
4137 val |= BNX2_HC_CONFIG_ONE_SHOT;
4139 REG_WR(bp, BNX2_HC_CONFIG, val);
4141 /* Clear internal stats counters. */
4142 REG_WR(bp, BNX2_HC_COMMAND, BNX2_HC_COMMAND_CLR_STAT_NOW);
4144 REG_WR(bp, BNX2_HC_ATTN_BITS_ENABLE, STATUS_ATTN_EVENTS);
4146 if (REG_RD_IND(bp, bp->shmem_base + BNX2_PORT_FEATURE) &
4147 BNX2_PORT_FEATURE_ASF_ENABLED)
4148 bp->flags |= ASF_ENABLE_FLAG;
4150 /* Initialize the receive filter. */
4151 bnx2_set_rx_mode(bp->dev);
4153 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
4154 val = REG_RD(bp, BNX2_MISC_NEW_CORE_CTL);
4155 val |= BNX2_MISC_NEW_CORE_CTL_DMA_ENABLE;
4156 REG_WR(bp, BNX2_MISC_NEW_CORE_CTL, val);
4158 rc = bnx2_fw_sync(bp, BNX2_DRV_MSG_DATA_WAIT2 | BNX2_DRV_MSG_CODE_RESET,
4161 REG_WR(bp, BNX2_MISC_ENABLE_SET_BITS, BNX2_MISC_ENABLE_DEFAULT);
4162 REG_RD(bp, BNX2_MISC_ENABLE_SET_BITS);
4166 bp->hc_cmd = REG_RD(bp, BNX2_HC_COMMAND);
4172 bnx2_init_tx_context(struct bnx2 *bp, u32 cid)
4174 u32 val, offset0, offset1, offset2, offset3;
4176 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
4177 offset0 = BNX2_L2CTX_TYPE_XI;
4178 offset1 = BNX2_L2CTX_CMD_TYPE_XI;
4179 offset2 = BNX2_L2CTX_TBDR_BHADDR_HI_XI;
4180 offset3 = BNX2_L2CTX_TBDR_BHADDR_LO_XI;
4182 offset0 = BNX2_L2CTX_TYPE;
4183 offset1 = BNX2_L2CTX_CMD_TYPE;
4184 offset2 = BNX2_L2CTX_TBDR_BHADDR_HI;
4185 offset3 = BNX2_L2CTX_TBDR_BHADDR_LO;
4187 val = BNX2_L2CTX_TYPE_TYPE_L2 | BNX2_L2CTX_TYPE_SIZE_L2;
4188 CTX_WR(bp, GET_CID_ADDR(cid), offset0, val);
4190 val = BNX2_L2CTX_CMD_TYPE_TYPE_L2 | (8 << 16);
4191 CTX_WR(bp, GET_CID_ADDR(cid), offset1, val);
4193 val = (u64) bp->tx_desc_mapping >> 32;
4194 CTX_WR(bp, GET_CID_ADDR(cid), offset2, val);
4196 val = (u64) bp->tx_desc_mapping & 0xffffffff;
4197 CTX_WR(bp, GET_CID_ADDR(cid), offset3, val);
4201 bnx2_init_tx_ring(struct bnx2 *bp)
4206 bp->tx_wake_thresh = bp->tx_ring_size / 2;
4208 txbd = &bp->tx_desc_ring[MAX_TX_DESC_CNT];
4210 txbd->tx_bd_haddr_hi = (u64) bp->tx_desc_mapping >> 32;
4211 txbd->tx_bd_haddr_lo = (u64) bp->tx_desc_mapping & 0xffffffff;
4216 bp->tx_prod_bseq = 0;
4219 bp->tx_bidx_addr = MB_GET_CID_ADDR(cid) + BNX2_L2CTX_TX_HOST_BIDX;
4220 bp->tx_bseq_addr = MB_GET_CID_ADDR(cid) + BNX2_L2CTX_TX_HOST_BSEQ;
4222 bnx2_init_tx_context(bp, cid);
4226 bnx2_init_rx_ring(struct bnx2 *bp)
4230 u16 prod, ring_prod;
4233 /* 8 for CRC and VLAN */
4234 bp->rx_buf_use_size = bp->dev->mtu + ETH_HLEN + bp->rx_offset + 8;
4236 bp->rx_buf_size = bp->rx_buf_use_size + BNX2_RX_ALIGN;
4238 ring_prod = prod = bp->rx_prod = 0;
4241 bp->rx_prod_bseq = 0;
4243 for (i = 0; i < bp->rx_max_ring; i++) {
4246 rxbd = &bp->rx_desc_ring[i][0];
4247 for (j = 0; j < MAX_RX_DESC_CNT; j++, rxbd++) {
4248 rxbd->rx_bd_len = bp->rx_buf_use_size;
4249 rxbd->rx_bd_flags = RX_BD_FLAGS_START | RX_BD_FLAGS_END;
4251 if (i == (bp->rx_max_ring - 1))
4255 rxbd->rx_bd_haddr_hi = (u64) bp->rx_desc_mapping[j] >> 32;
4256 rxbd->rx_bd_haddr_lo = (u64) bp->rx_desc_mapping[j] &
4260 val = BNX2_L2CTX_CTX_TYPE_CTX_BD_CHN_TYPE_VALUE;
4261 val |= BNX2_L2CTX_CTX_TYPE_SIZE_L2;
4263 CTX_WR(bp, GET_CID_ADDR(RX_CID), BNX2_L2CTX_CTX_TYPE, val);
4265 val = (u64) bp->rx_desc_mapping[0] >> 32;
4266 CTX_WR(bp, GET_CID_ADDR(RX_CID), BNX2_L2CTX_NX_BDHADDR_HI, val);
4268 val = (u64) bp->rx_desc_mapping[0] & 0xffffffff;
4269 CTX_WR(bp, GET_CID_ADDR(RX_CID), BNX2_L2CTX_NX_BDHADDR_LO, val);
4271 for (i = 0; i < bp->rx_ring_size; i++) {
4272 if (bnx2_alloc_rx_skb(bp, ring_prod) < 0) {
4275 prod = NEXT_RX_BD(prod);
4276 ring_prod = RX_RING_IDX(prod);
4280 REG_WR16(bp, MB_RX_CID_ADDR + BNX2_L2CTX_HOST_BDIDX, prod);
4282 REG_WR(bp, MB_RX_CID_ADDR + BNX2_L2CTX_HOST_BSEQ, bp->rx_prod_bseq);
4286 bnx2_set_rx_ring_size(struct bnx2 *bp, u32 size)
4290 bp->rx_ring_size = size;
4292 while (size > MAX_RX_DESC_CNT) {
4293 size -= MAX_RX_DESC_CNT;
4296 /* round to next power of 2 */
4298 while ((max & num_rings) == 0)
4301 if (num_rings != max)
4304 bp->rx_max_ring = max;
4305 bp->rx_max_ring_idx = (bp->rx_max_ring * RX_DESC_CNT) - 1;
4309 bnx2_free_tx_skbs(struct bnx2 *bp)
4313 if (bp->tx_buf_ring == NULL)
4316 for (i = 0; i < TX_DESC_CNT; ) {
4317 struct sw_bd *tx_buf = &bp->tx_buf_ring[i];
4318 struct sk_buff *skb = tx_buf->skb;
4326 pci_unmap_single(bp->pdev, pci_unmap_addr(tx_buf, mapping),
4327 skb_headlen(skb), PCI_DMA_TODEVICE);
4331 last = skb_shinfo(skb)->nr_frags;
4332 for (j = 0; j < last; j++) {
4333 tx_buf = &bp->tx_buf_ring[i + j + 1];
4334 pci_unmap_page(bp->pdev,
4335 pci_unmap_addr(tx_buf, mapping),
4336 skb_shinfo(skb)->frags[j].size,
4346 bnx2_free_rx_skbs(struct bnx2 *bp)
4350 if (bp->rx_buf_ring == NULL)
4353 for (i = 0; i < bp->rx_max_ring_idx; i++) {
4354 struct sw_bd *rx_buf = &bp->rx_buf_ring[i];
4355 struct sk_buff *skb = rx_buf->skb;
4360 pci_unmap_single(bp->pdev, pci_unmap_addr(rx_buf, mapping),
4361 bp->rx_buf_use_size, PCI_DMA_FROMDEVICE);
4370 bnx2_free_skbs(struct bnx2 *bp)
4372 bnx2_free_tx_skbs(bp);
4373 bnx2_free_rx_skbs(bp);
4377 bnx2_reset_nic(struct bnx2 *bp, u32 reset_code)
4381 rc = bnx2_reset_chip(bp, reset_code);
4386 if ((rc = bnx2_init_chip(bp)) != 0)
4389 bnx2_init_tx_ring(bp);
4390 bnx2_init_rx_ring(bp);
4395 bnx2_init_nic(struct bnx2 *bp)
4399 if ((rc = bnx2_reset_nic(bp, BNX2_DRV_MSG_CODE_RESET)) != 0)
4402 spin_lock_bh(&bp->phy_lock);
4405 spin_unlock_bh(&bp->phy_lock);
4410 bnx2_test_registers(struct bnx2 *bp)
4414 static const struct {
4417 #define BNX2_FL_NOT_5709 1
4421 { 0x006c, 0, 0x00000000, 0x0000003f },
4422 { 0x0090, 0, 0xffffffff, 0x00000000 },
4423 { 0x0094, 0, 0x00000000, 0x00000000 },
4425 { 0x0404, BNX2_FL_NOT_5709, 0x00003f00, 0x00000000 },
4426 { 0x0418, BNX2_FL_NOT_5709, 0x00000000, 0xffffffff },
4427 { 0x041c, BNX2_FL_NOT_5709, 0x00000000, 0xffffffff },
4428 { 0x0420, BNX2_FL_NOT_5709, 0x00000000, 0x80ffffff },
4429 { 0x0424, BNX2_FL_NOT_5709, 0x00000000, 0x00000000 },
4430 { 0x0428, BNX2_FL_NOT_5709, 0x00000000, 0x00000001 },
4431 { 0x0450, BNX2_FL_NOT_5709, 0x00000000, 0x0000ffff },
4432 { 0x0454, BNX2_FL_NOT_5709, 0x00000000, 0xffffffff },
4433 { 0x0458, BNX2_FL_NOT_5709, 0x00000000, 0xffffffff },
4435 { 0x0808, BNX2_FL_NOT_5709, 0x00000000, 0xffffffff },
4436 { 0x0854, BNX2_FL_NOT_5709, 0x00000000, 0xffffffff },
4437 { 0x0868, BNX2_FL_NOT_5709, 0x00000000, 0x77777777 },
4438 { 0x086c, BNX2_FL_NOT_5709, 0x00000000, 0x77777777 },
4439 { 0x0870, BNX2_FL_NOT_5709, 0x00000000, 0x77777777 },
4440 { 0x0874, BNX2_FL_NOT_5709, 0x00000000, 0x77777777 },
4442 { 0x0c00, BNX2_FL_NOT_5709, 0x00000000, 0x00000001 },
4443 { 0x0c04, BNX2_FL_NOT_5709, 0x00000000, 0x03ff0001 },
4444 { 0x0c08, BNX2_FL_NOT_5709, 0x0f0ff073, 0x00000000 },
4446 { 0x1000, 0, 0x00000000, 0x00000001 },
4447 { 0x1004, 0, 0x00000000, 0x000f0001 },
4449 { 0x1408, 0, 0x01c00800, 0x00000000 },
4450 { 0x149c, 0, 0x8000ffff, 0x00000000 },
4451 { 0x14a8, 0, 0x00000000, 0x000001ff },
4452 { 0x14ac, 0, 0x0fffffff, 0x10000000 },
4453 { 0x14b0, 0, 0x00000002, 0x00000001 },
4454 { 0x14b8, 0, 0x00000000, 0x00000000 },
4455 { 0x14c0, 0, 0x00000000, 0x00000009 },
4456 { 0x14c4, 0, 0x00003fff, 0x00000000 },
4457 { 0x14cc, 0, 0x00000000, 0x00000001 },
4458 { 0x14d0, 0, 0xffffffff, 0x00000000 },
4460 { 0x1800, 0, 0x00000000, 0x00000001 },
4461 { 0x1804, 0, 0x00000000, 0x00000003 },
4463 { 0x2800, 0, 0x00000000, 0x00000001 },
4464 { 0x2804, 0, 0x00000000, 0x00003f01 },
4465 { 0x2808, 0, 0x0f3f3f03, 0x00000000 },
4466 { 0x2810, 0, 0xffff0000, 0x00000000 },
4467 { 0x2814, 0, 0xffff0000, 0x00000000 },
4468 { 0x2818, 0, 0xffff0000, 0x00000000 },
4469 { 0x281c, 0, 0xffff0000, 0x00000000 },
4470 { 0x2834, 0, 0xffffffff, 0x00000000 },
4471 { 0x2840, 0, 0x00000000, 0xffffffff },
4472 { 0x2844, 0, 0x00000000, 0xffffffff },
4473 { 0x2848, 0, 0xffffffff, 0x00000000 },
4474 { 0x284c, 0, 0xf800f800, 0x07ff07ff },
4476 { 0x2c00, 0, 0x00000000, 0x00000011 },
4477 { 0x2c04, 0, 0x00000000, 0x00030007 },
4479 { 0x3c00, 0, 0x00000000, 0x00000001 },
4480 { 0x3c04, 0, 0x00000000, 0x00070000 },
4481 { 0x3c08, 0, 0x00007f71, 0x07f00000 },
4482 { 0x3c0c, 0, 0x1f3ffffc, 0x00000000 },
4483 { 0x3c10, 0, 0xffffffff, 0x00000000 },
4484 { 0x3c14, 0, 0x00000000, 0xffffffff },
4485 { 0x3c18, 0, 0x00000000, 0xffffffff },
4486 { 0x3c1c, 0, 0xfffff000, 0x00000000 },
4487 { 0x3c20, 0, 0xffffff00, 0x00000000 },
4489 { 0x5004, 0, 0x00000000, 0x0000007f },
4490 { 0x5008, 0, 0x0f0007ff, 0x00000000 },
4492 { 0x5c00, 0, 0x00000000, 0x00000001 },
4493 { 0x5c04, 0, 0x00000000, 0x0003000f },
4494 { 0x5c08, 0, 0x00000003, 0x00000000 },
4495 { 0x5c0c, 0, 0x0000fff8, 0x00000000 },
4496 { 0x5c10, 0, 0x00000000, 0xffffffff },
4497 { 0x5c80, 0, 0x00000000, 0x0f7113f1 },
4498 { 0x5c84, 0, 0x00000000, 0x0000f333 },
4499 { 0x5c88, 0, 0x00000000, 0x00077373 },
4500 { 0x5c8c, 0, 0x00000000, 0x0007f737 },
4502 { 0x6808, 0, 0x0000ff7f, 0x00000000 },
4503 { 0x680c, 0, 0xffffffff, 0x00000000 },
4504 { 0x6810, 0, 0xffffffff, 0x00000000 },
4505 { 0x6814, 0, 0xffffffff, 0x00000000 },
4506 { 0x6818, 0, 0xffffffff, 0x00000000 },
4507 { 0x681c, 0, 0xffffffff, 0x00000000 },
4508 { 0x6820, 0, 0x00ff00ff, 0x00000000 },
4509 { 0x6824, 0, 0x00ff00ff, 0x00000000 },
4510 { 0x6828, 0, 0x00ff00ff, 0x00000000 },
4511 { 0x682c, 0, 0x03ff03ff, 0x00000000 },
4512 { 0x6830, 0, 0x03ff03ff, 0x00000000 },
4513 { 0x6834, 0, 0x03ff03ff, 0x00000000 },
4514 { 0x6838, 0, 0x03ff03ff, 0x00000000 },
4515 { 0x683c, 0, 0x0000ffff, 0x00000000 },
4516 { 0x6840, 0, 0x00000ff0, 0x00000000 },
4517 { 0x6844, 0, 0x00ffff00, 0x00000000 },
4518 { 0x684c, 0, 0xffffffff, 0x00000000 },
4519 { 0x6850, 0, 0x7f7f7f7f, 0x00000000 },
4520 { 0x6854, 0, 0x7f7f7f7f, 0x00000000 },
4521 { 0x6858, 0, 0x7f7f7f7f, 0x00000000 },
4522 { 0x685c, 0, 0x7f7f7f7f, 0x00000000 },
4523 { 0x6908, 0, 0x00000000, 0x0001ff0f },
4524 { 0x690c, 0, 0x00000000, 0x0ffe00f0 },
4526 { 0xffff, 0, 0x00000000, 0x00000000 },
4531 if (CHIP_NUM(bp) == CHIP_NUM_5709)
4534 for (i = 0; reg_tbl[i].offset != 0xffff; i++) {
4535 u32 offset, rw_mask, ro_mask, save_val, val;
4536 u16 flags = reg_tbl[i].flags;
4538 if (is_5709 && (flags & BNX2_FL_NOT_5709))
4541 offset = (u32) reg_tbl[i].offset;
4542 rw_mask = reg_tbl[i].rw_mask;
4543 ro_mask = reg_tbl[i].ro_mask;
4545 save_val = readl(bp->regview + offset);
4547 writel(0, bp->regview + offset);
4549 val = readl(bp->regview + offset);
4550 if ((val & rw_mask) != 0) {
4554 if ((val & ro_mask) != (save_val & ro_mask)) {
4558 writel(0xffffffff, bp->regview + offset);
4560 val = readl(bp->regview + offset);
4561 if ((val & rw_mask) != rw_mask) {
4565 if ((val & ro_mask) != (save_val & ro_mask)) {
4569 writel(save_val, bp->regview + offset);
4573 writel(save_val, bp->regview + offset);
4581 bnx2_do_mem_test(struct bnx2 *bp, u32 start, u32 size)
4583 static const u32 test_pattern[] = { 0x00000000, 0xffffffff, 0x55555555,
4584 0xaaaaaaaa , 0xaa55aa55, 0x55aa55aa };
4587 for (i = 0; i < sizeof(test_pattern) / 4; i++) {
4590 for (offset = 0; offset < size; offset += 4) {
4592 REG_WR_IND(bp, start + offset, test_pattern[i]);
4594 if (REG_RD_IND(bp, start + offset) !=
4604 bnx2_test_memory(struct bnx2 *bp)
4608 static struct mem_entry {
4611 } mem_tbl_5706[] = {
4612 { 0x60000, 0x4000 },
4613 { 0xa0000, 0x3000 },
4614 { 0xe0000, 0x4000 },
4615 { 0x120000, 0x4000 },
4616 { 0x1a0000, 0x4000 },
4617 { 0x160000, 0x4000 },
4621 { 0x60000, 0x4000 },
4622 { 0xa0000, 0x3000 },
4623 { 0xe0000, 0x4000 },
4624 { 0x120000, 0x4000 },
4625 { 0x1a0000, 0x4000 },
4628 struct mem_entry *mem_tbl;
4630 if (CHIP_NUM(bp) == CHIP_NUM_5709)
4631 mem_tbl = mem_tbl_5709;
4633 mem_tbl = mem_tbl_5706;
4635 for (i = 0; mem_tbl[i].offset != 0xffffffff; i++) {
4636 if ((ret = bnx2_do_mem_test(bp, mem_tbl[i].offset,
4637 mem_tbl[i].len)) != 0) {
4645 #define BNX2_MAC_LOOPBACK 0
4646 #define BNX2_PHY_LOOPBACK 1
4649 bnx2_run_loopback(struct bnx2 *bp, int loopback_mode)
4651 unsigned int pkt_size, num_pkts, i;
4652 struct sk_buff *skb, *rx_skb;
4653 unsigned char *packet;
4654 u16 rx_start_idx, rx_idx;
4657 struct sw_bd *rx_buf;
4658 struct l2_fhdr *rx_hdr;
4661 if (loopback_mode == BNX2_MAC_LOOPBACK) {
4662 bp->loopback = MAC_LOOPBACK;
4663 bnx2_set_mac_loopback(bp);
4665 else if (loopback_mode == BNX2_PHY_LOOPBACK) {
4666 bp->loopback = PHY_LOOPBACK;
4667 bnx2_set_phy_loopback(bp);
4673 skb = netdev_alloc_skb(bp->dev, pkt_size);
4676 packet = skb_put(skb, pkt_size);
4677 memcpy(packet, bp->dev->dev_addr, 6);
4678 memset(packet + 6, 0x0, 8);
4679 for (i = 14; i < pkt_size; i++)
4680 packet[i] = (unsigned char) (i & 0xff);
4682 map = pci_map_single(bp->pdev, skb->data, pkt_size,
4685 REG_WR(bp, BNX2_HC_COMMAND,
4686 bp->hc_cmd | BNX2_HC_COMMAND_COAL_NOW_WO_INT);
4688 REG_RD(bp, BNX2_HC_COMMAND);
4691 rx_start_idx = bp->status_blk->status_rx_quick_consumer_index0;
4695 txbd = &bp->tx_desc_ring[TX_RING_IDX(bp->tx_prod)];
4697 txbd->tx_bd_haddr_hi = (u64) map >> 32;
4698 txbd->tx_bd_haddr_lo = (u64) map & 0xffffffff;
4699 txbd->tx_bd_mss_nbytes = pkt_size;
4700 txbd->tx_bd_vlan_tag_flags = TX_BD_FLAGS_START | TX_BD_FLAGS_END;
4703 bp->tx_prod = NEXT_TX_BD(bp->tx_prod);
4704 bp->tx_prod_bseq += pkt_size;
4706 REG_WR16(bp, bp->tx_bidx_addr, bp->tx_prod);
4707 REG_WR(bp, bp->tx_bseq_addr, bp->tx_prod_bseq);
4711 REG_WR(bp, BNX2_HC_COMMAND,
4712 bp->hc_cmd | BNX2_HC_COMMAND_COAL_NOW_WO_INT);
4714 REG_RD(bp, BNX2_HC_COMMAND);
4718 pci_unmap_single(bp->pdev, map, pkt_size, PCI_DMA_TODEVICE);
4721 if (bp->status_blk->status_tx_quick_consumer_index0 != bp->tx_prod) {
4722 goto loopback_test_done;
4725 rx_idx = bp->status_blk->status_rx_quick_consumer_index0;
4726 if (rx_idx != rx_start_idx + num_pkts) {
4727 goto loopback_test_done;
4730 rx_buf = &bp->rx_buf_ring[rx_start_idx];
4731 rx_skb = rx_buf->skb;
4733 rx_hdr = (struct l2_fhdr *) rx_skb->data;
4734 skb_reserve(rx_skb, bp->rx_offset);
4736 pci_dma_sync_single_for_cpu(bp->pdev,
4737 pci_unmap_addr(rx_buf, mapping),
4738 bp->rx_buf_size, PCI_DMA_FROMDEVICE);
4740 if (rx_hdr->l2_fhdr_status &
4741 (L2_FHDR_ERRORS_BAD_CRC |
4742 L2_FHDR_ERRORS_PHY_DECODE |
4743 L2_FHDR_ERRORS_ALIGNMENT |
4744 L2_FHDR_ERRORS_TOO_SHORT |
4745 L2_FHDR_ERRORS_GIANT_FRAME)) {
4747 goto loopback_test_done;
4750 if ((rx_hdr->l2_fhdr_pkt_len - 4) != pkt_size) {
4751 goto loopback_test_done;
4754 for (i = 14; i < pkt_size; i++) {
4755 if (*(rx_skb->data + i) != (unsigned char) (i & 0xff)) {
4756 goto loopback_test_done;
4767 #define BNX2_MAC_LOOPBACK_FAILED 1
4768 #define BNX2_PHY_LOOPBACK_FAILED 2
4769 #define BNX2_LOOPBACK_FAILED (BNX2_MAC_LOOPBACK_FAILED | \
4770 BNX2_PHY_LOOPBACK_FAILED)
4773 bnx2_test_loopback(struct bnx2 *bp)
4777 if (!netif_running(bp->dev))
4778 return BNX2_LOOPBACK_FAILED;
4780 bnx2_reset_nic(bp, BNX2_DRV_MSG_CODE_RESET);
4781 spin_lock_bh(&bp->phy_lock);
4783 spin_unlock_bh(&bp->phy_lock);
4784 if (bnx2_run_loopback(bp, BNX2_MAC_LOOPBACK))
4785 rc |= BNX2_MAC_LOOPBACK_FAILED;
4786 if (bnx2_run_loopback(bp, BNX2_PHY_LOOPBACK))
4787 rc |= BNX2_PHY_LOOPBACK_FAILED;
4791 #define NVRAM_SIZE 0x200
4792 #define CRC32_RESIDUAL 0xdebb20e3
4795 bnx2_test_nvram(struct bnx2 *bp)
4797 u32 buf[NVRAM_SIZE / 4];
4798 u8 *data = (u8 *) buf;
4802 if ((rc = bnx2_nvram_read(bp, 0, data, 4)) != 0)
4803 goto test_nvram_done;
4805 magic = be32_to_cpu(buf[0]);
4806 if (magic != 0x669955aa) {
4808 goto test_nvram_done;
4811 if ((rc = bnx2_nvram_read(bp, 0x100, data, NVRAM_SIZE)) != 0)
4812 goto test_nvram_done;
4814 csum = ether_crc_le(0x100, data);
4815 if (csum != CRC32_RESIDUAL) {
4817 goto test_nvram_done;
4820 csum = ether_crc_le(0x100, data + 0x100);
4821 if (csum != CRC32_RESIDUAL) {
4830 bnx2_test_link(struct bnx2 *bp)
4834 spin_lock_bh(&bp->phy_lock);
4835 bnx2_enable_bmsr1(bp);
4836 bnx2_read_phy(bp, bp->mii_bmsr1, &bmsr);
4837 bnx2_read_phy(bp, bp->mii_bmsr1, &bmsr);
4838 bnx2_disable_bmsr1(bp);
4839 spin_unlock_bh(&bp->phy_lock);
4841 if (bmsr & BMSR_LSTATUS) {
4848 bnx2_test_intr(struct bnx2 *bp)
4853 if (!netif_running(bp->dev))
4856 status_idx = REG_RD(bp, BNX2_PCICFG_INT_ACK_CMD) & 0xffff;
4858 /* This register is not touched during run-time. */
4859 REG_WR(bp, BNX2_HC_COMMAND, bp->hc_cmd | BNX2_HC_COMMAND_COAL_NOW);
4860 REG_RD(bp, BNX2_HC_COMMAND);
4862 for (i = 0; i < 10; i++) {
4863 if ((REG_RD(bp, BNX2_PCICFG_INT_ACK_CMD) & 0xffff) !=
4869 msleep_interruptible(10);
4878 bnx2_5706_serdes_timer(struct bnx2 *bp)
4880 spin_lock(&bp->phy_lock);
4881 if (bp->serdes_an_pending)
4882 bp->serdes_an_pending--;
4883 else if ((bp->link_up == 0) && (bp->autoneg & AUTONEG_SPEED)) {
4886 bp->current_interval = bp->timer_interval;
4888 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
4890 if (bmcr & BMCR_ANENABLE) {
4893 bnx2_write_phy(bp, 0x1c, 0x7c00);
4894 bnx2_read_phy(bp, 0x1c, &phy1);
4896 bnx2_write_phy(bp, 0x17, 0x0f01);
4897 bnx2_read_phy(bp, 0x15, &phy2);
4898 bnx2_write_phy(bp, 0x17, 0x0f01);
4899 bnx2_read_phy(bp, 0x15, &phy2);
4901 if ((phy1 & 0x10) && /* SIGNAL DETECT */
4902 !(phy2 & 0x20)) { /* no CONFIG */
4904 bmcr &= ~BMCR_ANENABLE;
4905 bmcr |= BMCR_SPEED1000 | BMCR_FULLDPLX;
4906 bnx2_write_phy(bp, bp->mii_bmcr, bmcr);
4907 bp->phy_flags |= PHY_PARALLEL_DETECT_FLAG;
4911 else if ((bp->link_up) && (bp->autoneg & AUTONEG_SPEED) &&
4912 (bp->phy_flags & PHY_PARALLEL_DETECT_FLAG)) {
4915 bnx2_write_phy(bp, 0x17, 0x0f01);
4916 bnx2_read_phy(bp, 0x15, &phy2);
4920 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
4921 bmcr |= BMCR_ANENABLE;
4922 bnx2_write_phy(bp, bp->mii_bmcr, bmcr);
4924 bp->phy_flags &= ~PHY_PARALLEL_DETECT_FLAG;
4927 bp->current_interval = bp->timer_interval;
4929 spin_unlock(&bp->phy_lock);
4933 bnx2_5708_serdes_timer(struct bnx2 *bp)
4935 if (bp->phy_flags & REMOTE_PHY_CAP_FLAG)
4938 if ((bp->phy_flags & PHY_2_5G_CAPABLE_FLAG) == 0) {
4939 bp->serdes_an_pending = 0;
4943 spin_lock(&bp->phy_lock);
4944 if (bp->serdes_an_pending)
4945 bp->serdes_an_pending--;
4946 else if ((bp->link_up == 0) && (bp->autoneg & AUTONEG_SPEED)) {
4949 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
4950 if (bmcr & BMCR_ANENABLE) {
4951 bnx2_enable_forced_2g5(bp);
4952 bp->current_interval = SERDES_FORCED_TIMEOUT;
4954 bnx2_disable_forced_2g5(bp);
4955 bp->serdes_an_pending = 2;
4956 bp->current_interval = bp->timer_interval;
4960 bp->current_interval = bp->timer_interval;
4962 spin_unlock(&bp->phy_lock);
4966 bnx2_timer(unsigned long data)
4968 struct bnx2 *bp = (struct bnx2 *) data;
4970 if (!netif_running(bp->dev))
4973 if (atomic_read(&bp->intr_sem) != 0)
4974 goto bnx2_restart_timer;
4976 bnx2_send_heart_beat(bp);
4978 bp->stats_blk->stat_FwRxDrop = REG_RD_IND(bp, BNX2_FW_RX_DROP_COUNT);
4980 /* workaround occasional corrupted counters */
4981 if (CHIP_NUM(bp) == CHIP_NUM_5708 && bp->stats_ticks)
4982 REG_WR(bp, BNX2_HC_COMMAND, bp->hc_cmd |
4983 BNX2_HC_COMMAND_STATS_NOW);
4985 if (bp->phy_flags & PHY_SERDES_FLAG) {
4986 if (CHIP_NUM(bp) == CHIP_NUM_5706)
4987 bnx2_5706_serdes_timer(bp);
4989 bnx2_5708_serdes_timer(bp);
4993 mod_timer(&bp->timer, jiffies + bp->current_interval);
4997 bnx2_request_irq(struct bnx2 *bp)
4999 struct net_device *dev = bp->dev;
5002 if (bp->flags & USING_MSI_FLAG) {
5003 irq_handler_t fn = bnx2_msi;
5005 if (bp->flags & ONE_SHOT_MSI_FLAG)
5006 fn = bnx2_msi_1shot;
5008 rc = request_irq(bp->pdev->irq, fn, 0, dev->name, dev);
5010 rc = request_irq(bp->pdev->irq, bnx2_interrupt,
5011 IRQF_SHARED, dev->name, dev);
5016 bnx2_free_irq(struct bnx2 *bp)
5018 struct net_device *dev = bp->dev;
5020 if (bp->flags & USING_MSI_FLAG) {
5021 free_irq(bp->pdev->irq, dev);
5022 pci_disable_msi(bp->pdev);
5023 bp->flags &= ~(USING_MSI_FLAG | ONE_SHOT_MSI_FLAG);
5025 free_irq(bp->pdev->irq, dev);
5028 /* Called with rtnl_lock */
5030 bnx2_open(struct net_device *dev)
5032 struct bnx2 *bp = netdev_priv(dev);
5035 netif_carrier_off(dev);
5037 bnx2_set_power_state(bp, PCI_D0);
5038 bnx2_disable_int(bp);
5040 rc = bnx2_alloc_mem(bp);
5044 if ((bp->flags & MSI_CAP_FLAG) && !disable_msi) {
5045 if (pci_enable_msi(bp->pdev) == 0) {
5046 bp->flags |= USING_MSI_FLAG;
5047 if (CHIP_NUM(bp) == CHIP_NUM_5709)
5048 bp->flags |= ONE_SHOT_MSI_FLAG;
5051 rc = bnx2_request_irq(bp);
5058 rc = bnx2_init_nic(bp);
5067 mod_timer(&bp->timer, jiffies + bp->current_interval);
5069 atomic_set(&bp->intr_sem, 0);
5071 bnx2_enable_int(bp);
5073 if (bp->flags & USING_MSI_FLAG) {
5074 /* Test MSI to make sure it is working
5075 * If MSI test fails, go back to INTx mode
5077 if (bnx2_test_intr(bp) != 0) {
5078 printk(KERN_WARNING PFX "%s: No interrupt was generated"
5079 " using MSI, switching to INTx mode. Please"
5080 " report this failure to the PCI maintainer"
5081 " and include system chipset information.\n",
5084 bnx2_disable_int(bp);
5087 rc = bnx2_init_nic(bp);
5090 rc = bnx2_request_irq(bp);
5095 del_timer_sync(&bp->timer);
5098 bnx2_enable_int(bp);
5101 if (bp->flags & USING_MSI_FLAG) {
5102 printk(KERN_INFO PFX "%s: using MSI\n", dev->name);
5105 netif_start_queue(dev);
5111 bnx2_reset_task(struct work_struct *work)
5113 struct bnx2 *bp = container_of(work, struct bnx2, reset_task);
5115 if (!netif_running(bp->dev))
5118 bp->in_reset_task = 1;
5119 bnx2_netif_stop(bp);
5123 atomic_set(&bp->intr_sem, 1);
5124 bnx2_netif_start(bp);
5125 bp->in_reset_task = 0;
5129 bnx2_tx_timeout(struct net_device *dev)
5131 struct bnx2 *bp = netdev_priv(dev);
5133 /* This allows the netif to be shutdown gracefully before resetting */
5134 schedule_work(&bp->reset_task);
5138 /* Called with rtnl_lock */
5140 bnx2_vlan_rx_register(struct net_device *dev, struct vlan_group *vlgrp)
5142 struct bnx2 *bp = netdev_priv(dev);
5144 bnx2_netif_stop(bp);
5147 bnx2_set_rx_mode(dev);
5149 bnx2_netif_start(bp);
5153 /* Called with netif_tx_lock.
5154 * bnx2_tx_int() runs without netif_tx_lock unless it needs to call
5155 * netif_wake_queue().
5158 bnx2_start_xmit(struct sk_buff *skb, struct net_device *dev)
5160 struct bnx2 *bp = netdev_priv(dev);
5163 struct sw_bd *tx_buf;
5164 u32 len, vlan_tag_flags, last_frag, mss;
5165 u16 prod, ring_prod;
5168 if (unlikely(bnx2_tx_avail(bp) < (skb_shinfo(skb)->nr_frags + 1))) {
5169 netif_stop_queue(dev);
5170 printk(KERN_ERR PFX "%s: BUG! Tx ring full when queue awake!\n",
5173 return NETDEV_TX_BUSY;
5175 len = skb_headlen(skb);
5177 ring_prod = TX_RING_IDX(prod);
5180 if (skb->ip_summed == CHECKSUM_PARTIAL) {
5181 vlan_tag_flags |= TX_BD_FLAGS_TCP_UDP_CKSUM;
5184 if (bp->vlgrp != 0 && vlan_tx_tag_present(skb)) {
5186 (TX_BD_FLAGS_VLAN_TAG | (vlan_tx_tag_get(skb) << 16));
5188 if ((mss = skb_shinfo(skb)->gso_size)) {
5189 u32 tcp_opt_len, ip_tcp_len;
5192 vlan_tag_flags |= TX_BD_FLAGS_SW_LSO;
5194 tcp_opt_len = tcp_optlen(skb);
5196 if (skb_shinfo(skb)->gso_type & SKB_GSO_TCPV6) {
5197 u32 tcp_off = skb_transport_offset(skb) -
5198 sizeof(struct ipv6hdr) - ETH_HLEN;
5200 vlan_tag_flags |= ((tcp_opt_len >> 2) << 8) |
5201 TX_BD_FLAGS_SW_FLAGS;
5202 if (likely(tcp_off == 0))
5203 vlan_tag_flags &= ~TX_BD_FLAGS_TCP6_OFF0_MSK;
5206 vlan_tag_flags |= ((tcp_off & 0x3) <<
5207 TX_BD_FLAGS_TCP6_OFF0_SHL) |
5208 ((tcp_off & 0x10) <<
5209 TX_BD_FLAGS_TCP6_OFF4_SHL);
5210 mss |= (tcp_off & 0xc) << TX_BD_TCP6_OFF2_SHL;
5213 if (skb_header_cloned(skb) &&
5214 pskb_expand_head(skb, 0, 0, GFP_ATOMIC)) {
5216 return NETDEV_TX_OK;
5219 ip_tcp_len = ip_hdrlen(skb) + sizeof(struct tcphdr);
5223 iph->tot_len = htons(mss + ip_tcp_len + tcp_opt_len);
5224 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
5228 if (tcp_opt_len || (iph->ihl > 5)) {
5229 vlan_tag_flags |= ((iph->ihl - 5) +
5230 (tcp_opt_len >> 2)) << 8;
5236 mapping = pci_map_single(bp->pdev, skb->data, len, PCI_DMA_TODEVICE);
5238 tx_buf = &bp->tx_buf_ring[ring_prod];
5240 pci_unmap_addr_set(tx_buf, mapping, mapping);
5242 txbd = &bp->tx_desc_ring[ring_prod];
5244 txbd->tx_bd_haddr_hi = (u64) mapping >> 32;
5245 txbd->tx_bd_haddr_lo = (u64) mapping & 0xffffffff;
5246 txbd->tx_bd_mss_nbytes = len | (mss << 16);
5247 txbd->tx_bd_vlan_tag_flags = vlan_tag_flags | TX_BD_FLAGS_START;
5249 last_frag = skb_shinfo(skb)->nr_frags;
5251 for (i = 0; i < last_frag; i++) {
5252 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
5254 prod = NEXT_TX_BD(prod);
5255 ring_prod = TX_RING_IDX(prod);
5256 txbd = &bp->tx_desc_ring[ring_prod];
5259 mapping = pci_map_page(bp->pdev, frag->page, frag->page_offset,
5260 len, PCI_DMA_TODEVICE);
5261 pci_unmap_addr_set(&bp->tx_buf_ring[ring_prod],
5264 txbd->tx_bd_haddr_hi = (u64) mapping >> 32;
5265 txbd->tx_bd_haddr_lo = (u64) mapping & 0xffffffff;
5266 txbd->tx_bd_mss_nbytes = len | (mss << 16);
5267 txbd->tx_bd_vlan_tag_flags = vlan_tag_flags;
5270 txbd->tx_bd_vlan_tag_flags |= TX_BD_FLAGS_END;
5272 prod = NEXT_TX_BD(prod);
5273 bp->tx_prod_bseq += skb->len;
5275 REG_WR16(bp, bp->tx_bidx_addr, prod);
5276 REG_WR(bp, bp->tx_bseq_addr, bp->tx_prod_bseq);
5281 dev->trans_start = jiffies;
5283 if (unlikely(bnx2_tx_avail(bp) <= MAX_SKB_FRAGS)) {
5284 netif_stop_queue(dev);
5285 if (bnx2_tx_avail(bp) > bp->tx_wake_thresh)
5286 netif_wake_queue(dev);
5289 return NETDEV_TX_OK;
5292 /* Called with rtnl_lock */
5294 bnx2_close(struct net_device *dev)
5296 struct bnx2 *bp = netdev_priv(dev);
5299 /* Calling flush_scheduled_work() may deadlock because
5300 * linkwatch_event() may be on the workqueue and it will try to get
5301 * the rtnl_lock which we are holding.
5303 while (bp->in_reset_task)
5306 bnx2_netif_stop(bp);
5307 del_timer_sync(&bp->timer);
5308 if (bp->flags & NO_WOL_FLAG)
5309 reset_code = BNX2_DRV_MSG_CODE_UNLOAD_LNK_DN;
5311 reset_code = BNX2_DRV_MSG_CODE_SUSPEND_WOL;
5313 reset_code = BNX2_DRV_MSG_CODE_SUSPEND_NO_WOL;
5314 bnx2_reset_chip(bp, reset_code);
5319 netif_carrier_off(bp->dev);
5320 bnx2_set_power_state(bp, PCI_D3hot);
5324 #define GET_NET_STATS64(ctr) \
5325 (unsigned long) ((unsigned long) (ctr##_hi) << 32) + \
5326 (unsigned long) (ctr##_lo)
5328 #define GET_NET_STATS32(ctr) \
5331 #if (BITS_PER_LONG == 64)
5332 #define GET_NET_STATS GET_NET_STATS64
5334 #define GET_NET_STATS GET_NET_STATS32
5337 static struct net_device_stats *
5338 bnx2_get_stats(struct net_device *dev)
5340 struct bnx2 *bp = netdev_priv(dev);
5341 struct statistics_block *stats_blk = bp->stats_blk;
5342 struct net_device_stats *net_stats = &bp->net_stats;
5344 if (bp->stats_blk == NULL) {
5347 net_stats->rx_packets =
5348 GET_NET_STATS(stats_blk->stat_IfHCInUcastPkts) +
5349 GET_NET_STATS(stats_blk->stat_IfHCInMulticastPkts) +
5350 GET_NET_STATS(stats_blk->stat_IfHCInBroadcastPkts);
5352 net_stats->tx_packets =
5353 GET_NET_STATS(stats_blk->stat_IfHCOutUcastPkts) +
5354 GET_NET_STATS(stats_blk->stat_IfHCOutMulticastPkts) +
5355 GET_NET_STATS(stats_blk->stat_IfHCOutBroadcastPkts);
5357 net_stats->rx_bytes =
5358 GET_NET_STATS(stats_blk->stat_IfHCInOctets);
5360 net_stats->tx_bytes =
5361 GET_NET_STATS(stats_blk->stat_IfHCOutOctets);
5363 net_stats->multicast =
5364 GET_NET_STATS(stats_blk->stat_IfHCOutMulticastPkts);
5366 net_stats->collisions =
5367 (unsigned long) stats_blk->stat_EtherStatsCollisions;
5369 net_stats->rx_length_errors =
5370 (unsigned long) (stats_blk->stat_EtherStatsUndersizePkts +
5371 stats_blk->stat_EtherStatsOverrsizePkts);
5373 net_stats->rx_over_errors =
5374 (unsigned long) stats_blk->stat_IfInMBUFDiscards;
5376 net_stats->rx_frame_errors =
5377 (unsigned long) stats_blk->stat_Dot3StatsAlignmentErrors;
5379 net_stats->rx_crc_errors =
5380 (unsigned long) stats_blk->stat_Dot3StatsFCSErrors;
5382 net_stats->rx_errors = net_stats->rx_length_errors +
5383 net_stats->rx_over_errors + net_stats->rx_frame_errors +
5384 net_stats->rx_crc_errors;
5386 net_stats->tx_aborted_errors =
5387 (unsigned long) (stats_blk->stat_Dot3StatsExcessiveCollisions +
5388 stats_blk->stat_Dot3StatsLateCollisions);
5390 if ((CHIP_NUM(bp) == CHIP_NUM_5706) ||
5391 (CHIP_ID(bp) == CHIP_ID_5708_A0))
5392 net_stats->tx_carrier_errors = 0;
5394 net_stats->tx_carrier_errors =
5396 stats_blk->stat_Dot3StatsCarrierSenseErrors;
5399 net_stats->tx_errors =
5401 stats_blk->stat_emac_tx_stat_dot3statsinternalmactransmiterrors
5403 net_stats->tx_aborted_errors +
5404 net_stats->tx_carrier_errors;
5406 net_stats->rx_missed_errors =
5407 (unsigned long) (stats_blk->stat_IfInMBUFDiscards +
5408 stats_blk->stat_FwRxDrop);
5413 /* All ethtool functions called with rtnl_lock */
5416 bnx2_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
5418 struct bnx2 *bp = netdev_priv(dev);
5419 int support_serdes = 0, support_copper = 0;
5421 cmd->supported = SUPPORTED_Autoneg;
5422 if (bp->phy_flags & REMOTE_PHY_CAP_FLAG) {
5425 } else if (bp->phy_port == PORT_FIBRE)
5430 if (support_serdes) {
5431 cmd->supported |= SUPPORTED_1000baseT_Full |
5433 if (bp->phy_flags & PHY_2_5G_CAPABLE_FLAG)
5434 cmd->supported |= SUPPORTED_2500baseX_Full;
5437 if (support_copper) {
5438 cmd->supported |= SUPPORTED_10baseT_Half |
5439 SUPPORTED_10baseT_Full |
5440 SUPPORTED_100baseT_Half |
5441 SUPPORTED_100baseT_Full |
5442 SUPPORTED_1000baseT_Full |
5447 spin_lock_bh(&bp->phy_lock);
5448 cmd->port = bp->phy_port;
5449 cmd->advertising = bp->advertising;
5451 if (bp->autoneg & AUTONEG_SPEED) {
5452 cmd->autoneg = AUTONEG_ENABLE;
5455 cmd->autoneg = AUTONEG_DISABLE;
5458 if (netif_carrier_ok(dev)) {
5459 cmd->speed = bp->line_speed;
5460 cmd->duplex = bp->duplex;
5466 spin_unlock_bh(&bp->phy_lock);
5468 cmd->transceiver = XCVR_INTERNAL;
5469 cmd->phy_address = bp->phy_addr;
5475 bnx2_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
5477 struct bnx2 *bp = netdev_priv(dev);
5478 u8 autoneg = bp->autoneg;
5479 u8 req_duplex = bp->req_duplex;
5480 u16 req_line_speed = bp->req_line_speed;
5481 u32 advertising = bp->advertising;
5484 spin_lock_bh(&bp->phy_lock);
5486 if (cmd->port != PORT_TP && cmd->port != PORT_FIBRE)
5487 goto err_out_unlock;
5489 if (cmd->port != bp->phy_port && !(bp->phy_flags & REMOTE_PHY_CAP_FLAG))
5490 goto err_out_unlock;
5492 if (cmd->autoneg == AUTONEG_ENABLE) {
5493 autoneg |= AUTONEG_SPEED;
5495 cmd->advertising &= ETHTOOL_ALL_COPPER_SPEED;
5497 /* allow advertising 1 speed */
5498 if ((cmd->advertising == ADVERTISED_10baseT_Half) ||
5499 (cmd->advertising == ADVERTISED_10baseT_Full) ||
5500 (cmd->advertising == ADVERTISED_100baseT_Half) ||
5501 (cmd->advertising == ADVERTISED_100baseT_Full)) {
5503 if (cmd->port == PORT_FIBRE)
5504 goto err_out_unlock;
5506 advertising = cmd->advertising;
5508 } else if (cmd->advertising == ADVERTISED_2500baseX_Full) {
5509 if (!(bp->phy_flags & PHY_2_5G_CAPABLE_FLAG) ||
5510 (cmd->port == PORT_TP))
5511 goto err_out_unlock;
5512 } else if (cmd->advertising == ADVERTISED_1000baseT_Full)
5513 advertising = cmd->advertising;
5514 else if (cmd->advertising == ADVERTISED_1000baseT_Half)
5515 goto err_out_unlock;
5517 if (cmd->port == PORT_FIBRE)
5518 advertising = ETHTOOL_ALL_FIBRE_SPEED;
5520 advertising = ETHTOOL_ALL_COPPER_SPEED;
5522 advertising |= ADVERTISED_Autoneg;
5525 if (cmd->port == PORT_FIBRE) {
5526 if ((cmd->speed != SPEED_1000 &&
5527 cmd->speed != SPEED_2500) ||
5528 (cmd->duplex != DUPLEX_FULL))
5529 goto err_out_unlock;
5531 if (cmd->speed == SPEED_2500 &&
5532 !(bp->phy_flags & PHY_2_5G_CAPABLE_FLAG))
5533 goto err_out_unlock;
5535 else if (cmd->speed == SPEED_1000 || cmd->speed == SPEED_2500)
5536 goto err_out_unlock;
5538 autoneg &= ~AUTONEG_SPEED;
5539 req_line_speed = cmd->speed;
5540 req_duplex = cmd->duplex;
5544 bp->autoneg = autoneg;
5545 bp->advertising = advertising;
5546 bp->req_line_speed = req_line_speed;
5547 bp->req_duplex = req_duplex;
5549 err = bnx2_setup_phy(bp, cmd->port);
5552 spin_unlock_bh(&bp->phy_lock);
5558 bnx2_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
5560 struct bnx2 *bp = netdev_priv(dev);
5562 strcpy(info->driver, DRV_MODULE_NAME);
5563 strcpy(info->version, DRV_MODULE_VERSION);
5564 strcpy(info->bus_info, pci_name(bp->pdev));
5565 strcpy(info->fw_version, bp->fw_version);
5568 #define BNX2_REGDUMP_LEN (32 * 1024)
5571 bnx2_get_regs_len(struct net_device *dev)
5573 return BNX2_REGDUMP_LEN;
5577 bnx2_get_regs(struct net_device *dev, struct ethtool_regs *regs, void *_p)
5579 u32 *p = _p, i, offset;
5581 struct bnx2 *bp = netdev_priv(dev);
5582 u32 reg_boundaries[] = { 0x0000, 0x0098, 0x0400, 0x045c,
5583 0x0800, 0x0880, 0x0c00, 0x0c10,
5584 0x0c30, 0x0d08, 0x1000, 0x101c,
5585 0x1040, 0x1048, 0x1080, 0x10a4,
5586 0x1400, 0x1490, 0x1498, 0x14f0,
5587 0x1500, 0x155c, 0x1580, 0x15dc,
5588 0x1600, 0x1658, 0x1680, 0x16d8,
5589 0x1800, 0x1820, 0x1840, 0x1854,
5590 0x1880, 0x1894, 0x1900, 0x1984,
5591 0x1c00, 0x1c0c, 0x1c40, 0x1c54,
5592 0x1c80, 0x1c94, 0x1d00, 0x1d84,
5593 0x2000, 0x2030, 0x23c0, 0x2400,
5594 0x2800, 0x2820, 0x2830, 0x2850,
5595 0x2b40, 0x2c10, 0x2fc0, 0x3058,
5596 0x3c00, 0x3c94, 0x4000, 0x4010,
5597 0x4080, 0x4090, 0x43c0, 0x4458,
5598 0x4c00, 0x4c18, 0x4c40, 0x4c54,
5599 0x4fc0, 0x5010, 0x53c0, 0x5444,
5600 0x5c00, 0x5c18, 0x5c80, 0x5c90,
5601 0x5fc0, 0x6000, 0x6400, 0x6428,
5602 0x6800, 0x6848, 0x684c, 0x6860,
5603 0x6888, 0x6910, 0x8000 };
5607 memset(p, 0, BNX2_REGDUMP_LEN);
5609 if (!netif_running(bp->dev))
5613 offset = reg_boundaries[0];
5615 while (offset < BNX2_REGDUMP_LEN) {
5616 *p++ = REG_RD(bp, offset);
5618 if (offset == reg_boundaries[i + 1]) {
5619 offset = reg_boundaries[i + 2];
5620 p = (u32 *) (orig_p + offset);
5627 bnx2_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
5629 struct bnx2 *bp = netdev_priv(dev);
5631 if (bp->flags & NO_WOL_FLAG) {
5636 wol->supported = WAKE_MAGIC;
5638 wol->wolopts = WAKE_MAGIC;
5642 memset(&wol->sopass, 0, sizeof(wol->sopass));
5646 bnx2_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
5648 struct bnx2 *bp = netdev_priv(dev);
5650 if (wol->wolopts & ~WAKE_MAGIC)
5653 if (wol->wolopts & WAKE_MAGIC) {
5654 if (bp->flags & NO_WOL_FLAG)
5666 bnx2_nway_reset(struct net_device *dev)
5668 struct bnx2 *bp = netdev_priv(dev);
5671 if (!(bp->autoneg & AUTONEG_SPEED)) {
5675 spin_lock_bh(&bp->phy_lock);
5677 if (bp->phy_flags & REMOTE_PHY_CAP_FLAG) {
5680 rc = bnx2_setup_remote_phy(bp, bp->phy_port);
5681 spin_unlock_bh(&bp->phy_lock);
5685 /* Force a link down visible on the other side */
5686 if (bp->phy_flags & PHY_SERDES_FLAG) {
5687 bnx2_write_phy(bp, bp->mii_bmcr, BMCR_LOOPBACK);
5688 spin_unlock_bh(&bp->phy_lock);
5692 spin_lock_bh(&bp->phy_lock);
5694 bp->current_interval = SERDES_AN_TIMEOUT;
5695 bp->serdes_an_pending = 1;
5696 mod_timer(&bp->timer, jiffies + bp->current_interval);
5699 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
5700 bmcr &= ~BMCR_LOOPBACK;
5701 bnx2_write_phy(bp, bp->mii_bmcr, bmcr | BMCR_ANRESTART | BMCR_ANENABLE);
5703 spin_unlock_bh(&bp->phy_lock);
5709 bnx2_get_eeprom_len(struct net_device *dev)
5711 struct bnx2 *bp = netdev_priv(dev);
5713 if (bp->flash_info == NULL)
5716 return (int) bp->flash_size;
5720 bnx2_get_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom,
5723 struct bnx2 *bp = netdev_priv(dev);
5726 /* parameters already validated in ethtool_get_eeprom */
5728 rc = bnx2_nvram_read(bp, eeprom->offset, eebuf, eeprom->len);
5734 bnx2_set_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom,
5737 struct bnx2 *bp = netdev_priv(dev);
5740 /* parameters already validated in ethtool_set_eeprom */
5742 rc = bnx2_nvram_write(bp, eeprom->offset, eebuf, eeprom->len);
5748 bnx2_get_coalesce(struct net_device *dev, struct ethtool_coalesce *coal)
5750 struct bnx2 *bp = netdev_priv(dev);
5752 memset(coal, 0, sizeof(struct ethtool_coalesce));
5754 coal->rx_coalesce_usecs = bp->rx_ticks;
5755 coal->rx_max_coalesced_frames = bp->rx_quick_cons_trip;
5756 coal->rx_coalesce_usecs_irq = bp->rx_ticks_int;
5757 coal->rx_max_coalesced_frames_irq = bp->rx_quick_cons_trip_int;
5759 coal->tx_coalesce_usecs = bp->tx_ticks;
5760 coal->tx_max_coalesced_frames = bp->tx_quick_cons_trip;
5761 coal->tx_coalesce_usecs_irq = bp->tx_ticks_int;
5762 coal->tx_max_coalesced_frames_irq = bp->tx_quick_cons_trip_int;
5764 coal->stats_block_coalesce_usecs = bp->stats_ticks;
5770 bnx2_set_coalesce(struct net_device *dev, struct ethtool_coalesce *coal)
5772 struct bnx2 *bp = netdev_priv(dev);
5774 bp->rx_ticks = (u16) coal->rx_coalesce_usecs;
5775 if (bp->rx_ticks > 0x3ff) bp->rx_ticks = 0x3ff;
5777 bp->rx_quick_cons_trip = (u16) coal->rx_max_coalesced_frames;
5778 if (bp->rx_quick_cons_trip > 0xff) bp->rx_quick_cons_trip = 0xff;
5780 bp->rx_ticks_int = (u16) coal->rx_coalesce_usecs_irq;
5781 if (bp->rx_ticks_int > 0x3ff) bp->rx_ticks_int = 0x3ff;
5783 bp->rx_quick_cons_trip_int = (u16) coal->rx_max_coalesced_frames_irq;
5784 if (bp->rx_quick_cons_trip_int > 0xff)
5785 bp->rx_quick_cons_trip_int = 0xff;
5787 bp->tx_ticks = (u16) coal->tx_coalesce_usecs;
5788 if (bp->tx_ticks > 0x3ff) bp->tx_ticks = 0x3ff;
5790 bp->tx_quick_cons_trip = (u16) coal->tx_max_coalesced_frames;
5791 if (bp->tx_quick_cons_trip > 0xff) bp->tx_quick_cons_trip = 0xff;
5793 bp->tx_ticks_int = (u16) coal->tx_coalesce_usecs_irq;
5794 if (bp->tx_ticks_int > 0x3ff) bp->tx_ticks_int = 0x3ff;
5796 bp->tx_quick_cons_trip_int = (u16) coal->tx_max_coalesced_frames_irq;
5797 if (bp->tx_quick_cons_trip_int > 0xff) bp->tx_quick_cons_trip_int =
5800 bp->stats_ticks = coal->stats_block_coalesce_usecs;
5801 if (CHIP_NUM(bp) == CHIP_NUM_5708) {
5802 if (bp->stats_ticks != 0 && bp->stats_ticks != USEC_PER_SEC)
5803 bp->stats_ticks = USEC_PER_SEC;
5805 if (bp->stats_ticks > 0xffff00) bp->stats_ticks = 0xffff00;
5806 bp->stats_ticks &= 0xffff00;
5808 if (netif_running(bp->dev)) {
5809 bnx2_netif_stop(bp);
5811 bnx2_netif_start(bp);
5818 bnx2_get_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
5820 struct bnx2 *bp = netdev_priv(dev);
5822 ering->rx_max_pending = MAX_TOTAL_RX_DESC_CNT;
5823 ering->rx_mini_max_pending = 0;
5824 ering->rx_jumbo_max_pending = 0;
5826 ering->rx_pending = bp->rx_ring_size;
5827 ering->rx_mini_pending = 0;
5828 ering->rx_jumbo_pending = 0;
5830 ering->tx_max_pending = MAX_TX_DESC_CNT;
5831 ering->tx_pending = bp->tx_ring_size;
5835 bnx2_set_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
5837 struct bnx2 *bp = netdev_priv(dev);
5839 if ((ering->rx_pending > MAX_TOTAL_RX_DESC_CNT) ||
5840 (ering->tx_pending > MAX_TX_DESC_CNT) ||
5841 (ering->tx_pending <= MAX_SKB_FRAGS)) {
5845 if (netif_running(bp->dev)) {
5846 bnx2_netif_stop(bp);
5847 bnx2_reset_chip(bp, BNX2_DRV_MSG_CODE_RESET);
5852 bnx2_set_rx_ring_size(bp, ering->rx_pending);
5853 bp->tx_ring_size = ering->tx_pending;
5855 if (netif_running(bp->dev)) {
5858 rc = bnx2_alloc_mem(bp);
5862 bnx2_netif_start(bp);
5869 bnx2_get_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
5871 struct bnx2 *bp = netdev_priv(dev);
5873 epause->autoneg = ((bp->autoneg & AUTONEG_FLOW_CTRL) != 0);
5874 epause->rx_pause = ((bp->flow_ctrl & FLOW_CTRL_RX) != 0);
5875 epause->tx_pause = ((bp->flow_ctrl & FLOW_CTRL_TX) != 0);
5879 bnx2_set_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
5881 struct bnx2 *bp = netdev_priv(dev);
5883 bp->req_flow_ctrl = 0;
5884 if (epause->rx_pause)
5885 bp->req_flow_ctrl |= FLOW_CTRL_RX;
5886 if (epause->tx_pause)
5887 bp->req_flow_ctrl |= FLOW_CTRL_TX;
5889 if (epause->autoneg) {
5890 bp->autoneg |= AUTONEG_FLOW_CTRL;
5893 bp->autoneg &= ~AUTONEG_FLOW_CTRL;
5896 spin_lock_bh(&bp->phy_lock);
5898 bnx2_setup_phy(bp, bp->phy_port);
5900 spin_unlock_bh(&bp->phy_lock);
5906 bnx2_get_rx_csum(struct net_device *dev)
5908 struct bnx2 *bp = netdev_priv(dev);
5914 bnx2_set_rx_csum(struct net_device *dev, u32 data)
5916 struct bnx2 *bp = netdev_priv(dev);
5923 bnx2_set_tso(struct net_device *dev, u32 data)
5925 struct bnx2 *bp = netdev_priv(dev);
5928 dev->features |= NETIF_F_TSO | NETIF_F_TSO_ECN;
5929 if (CHIP_NUM(bp) == CHIP_NUM_5709)
5930 dev->features |= NETIF_F_TSO6;
5932 dev->features &= ~(NETIF_F_TSO | NETIF_F_TSO6 |
5937 #define BNX2_NUM_STATS 46
5940 char string[ETH_GSTRING_LEN];
5941 } bnx2_stats_str_arr[BNX2_NUM_STATS] = {
5943 { "rx_error_bytes" },
5945 { "tx_error_bytes" },
5946 { "rx_ucast_packets" },
5947 { "rx_mcast_packets" },
5948 { "rx_bcast_packets" },
5949 { "tx_ucast_packets" },
5950 { "tx_mcast_packets" },
5951 { "tx_bcast_packets" },
5952 { "tx_mac_errors" },
5953 { "tx_carrier_errors" },
5954 { "rx_crc_errors" },
5955 { "rx_align_errors" },
5956 { "tx_single_collisions" },
5957 { "tx_multi_collisions" },
5959 { "tx_excess_collisions" },
5960 { "tx_late_collisions" },
5961 { "tx_total_collisions" },
5964 { "rx_undersize_packets" },
5965 { "rx_oversize_packets" },
5966 { "rx_64_byte_packets" },
5967 { "rx_65_to_127_byte_packets" },
5968 { "rx_128_to_255_byte_packets" },
5969 { "rx_256_to_511_byte_packets" },
5970 { "rx_512_to_1023_byte_packets" },
5971 { "rx_1024_to_1522_byte_packets" },
5972 { "rx_1523_to_9022_byte_packets" },
5973 { "tx_64_byte_packets" },
5974 { "tx_65_to_127_byte_packets" },
5975 { "tx_128_to_255_byte_packets" },
5976 { "tx_256_to_511_byte_packets" },
5977 { "tx_512_to_1023_byte_packets" },
5978 { "tx_1024_to_1522_byte_packets" },
5979 { "tx_1523_to_9022_byte_packets" },
5980 { "rx_xon_frames" },
5981 { "rx_xoff_frames" },
5982 { "tx_xon_frames" },
5983 { "tx_xoff_frames" },
5984 { "rx_mac_ctrl_frames" },
5985 { "rx_filtered_packets" },
5987 { "rx_fw_discards" },
5990 #define STATS_OFFSET32(offset_name) (offsetof(struct statistics_block, offset_name) / 4)
5992 static const unsigned long bnx2_stats_offset_arr[BNX2_NUM_STATS] = {
5993 STATS_OFFSET32(stat_IfHCInOctets_hi),
5994 STATS_OFFSET32(stat_IfHCInBadOctets_hi),
5995 STATS_OFFSET32(stat_IfHCOutOctets_hi),
5996 STATS_OFFSET32(stat_IfHCOutBadOctets_hi),
5997 STATS_OFFSET32(stat_IfHCInUcastPkts_hi),
5998 STATS_OFFSET32(stat_IfHCInMulticastPkts_hi),
5999 STATS_OFFSET32(stat_IfHCInBroadcastPkts_hi),
6000 STATS_OFFSET32(stat_IfHCOutUcastPkts_hi),
6001 STATS_OFFSET32(stat_IfHCOutMulticastPkts_hi),
6002 STATS_OFFSET32(stat_IfHCOutBroadcastPkts_hi),
6003 STATS_OFFSET32(stat_emac_tx_stat_dot3statsinternalmactransmiterrors),
6004 STATS_OFFSET32(stat_Dot3StatsCarrierSenseErrors),
6005 STATS_OFFSET32(stat_Dot3StatsFCSErrors),
6006 STATS_OFFSET32(stat_Dot3StatsAlignmentErrors),
6007 STATS_OFFSET32(stat_Dot3StatsSingleCollisionFrames),
6008 STATS_OFFSET32(stat_Dot3StatsMultipleCollisionFrames),
6009 STATS_OFFSET32(stat_Dot3StatsDeferredTransmissions),
6010 STATS_OFFSET32(stat_Dot3StatsExcessiveCollisions),
6011 STATS_OFFSET32(stat_Dot3StatsLateCollisions),
6012 STATS_OFFSET32(stat_EtherStatsCollisions),
6013 STATS_OFFSET32(stat_EtherStatsFragments),
6014 STATS_OFFSET32(stat_EtherStatsJabbers),
6015 STATS_OFFSET32(stat_EtherStatsUndersizePkts),
6016 STATS_OFFSET32(stat_EtherStatsOverrsizePkts),
6017 STATS_OFFSET32(stat_EtherStatsPktsRx64Octets),
6018 STATS_OFFSET32(stat_EtherStatsPktsRx65Octetsto127Octets),
6019 STATS_OFFSET32(stat_EtherStatsPktsRx128Octetsto255Octets),
6020 STATS_OFFSET32(stat_EtherStatsPktsRx256Octetsto511Octets),
6021 STATS_OFFSET32(stat_EtherStatsPktsRx512Octetsto1023Octets),
6022 STATS_OFFSET32(stat_EtherStatsPktsRx1024Octetsto1522Octets),
6023 STATS_OFFSET32(stat_EtherStatsPktsRx1523Octetsto9022Octets),
6024 STATS_OFFSET32(stat_EtherStatsPktsTx64Octets),
6025 STATS_OFFSET32(stat_EtherStatsPktsTx65Octetsto127Octets),
6026 STATS_OFFSET32(stat_EtherStatsPktsTx128Octetsto255Octets),
6027 STATS_OFFSET32(stat_EtherStatsPktsTx256Octetsto511Octets),
6028 STATS_OFFSET32(stat_EtherStatsPktsTx512Octetsto1023Octets),
6029 STATS_OFFSET32(stat_EtherStatsPktsTx1024Octetsto1522Octets),
6030 STATS_OFFSET32(stat_EtherStatsPktsTx1523Octetsto9022Octets),
6031 STATS_OFFSET32(stat_XonPauseFramesReceived),
6032 STATS_OFFSET32(stat_XoffPauseFramesReceived),
6033 STATS_OFFSET32(stat_OutXonSent),
6034 STATS_OFFSET32(stat_OutXoffSent),
6035 STATS_OFFSET32(stat_MacControlFramesReceived),
6036 STATS_OFFSET32(stat_IfInFramesL2FilterDiscards),
6037 STATS_OFFSET32(stat_IfInMBUFDiscards),
6038 STATS_OFFSET32(stat_FwRxDrop),
6041 /* stat_IfHCInBadOctets and stat_Dot3StatsCarrierSenseErrors are
6042 * skipped because of errata.
6044 static u8 bnx2_5706_stats_len_arr[BNX2_NUM_STATS] = {
6045 8,0,8,8,8,8,8,8,8,8,
6046 4,0,4,4,4,4,4,4,4,4,
6047 4,4,4,4,4,4,4,4,4,4,
6048 4,4,4,4,4,4,4,4,4,4,
6052 static u8 bnx2_5708_stats_len_arr[BNX2_NUM_STATS] = {
6053 8,0,8,8,8,8,8,8,8,8,
6054 4,4,4,4,4,4,4,4,4,4,
6055 4,4,4,4,4,4,4,4,4,4,
6056 4,4,4,4,4,4,4,4,4,4,
6060 #define BNX2_NUM_TESTS 6
6063 char string[ETH_GSTRING_LEN];
6064 } bnx2_tests_str_arr[BNX2_NUM_TESTS] = {
6065 { "register_test (offline)" },
6066 { "memory_test (offline)" },
6067 { "loopback_test (offline)" },
6068 { "nvram_test (online)" },
6069 { "interrupt_test (online)" },
6070 { "link_test (online)" },
6074 bnx2_self_test_count(struct net_device *dev)
6076 return BNX2_NUM_TESTS;
6080 bnx2_self_test(struct net_device *dev, struct ethtool_test *etest, u64 *buf)
6082 struct bnx2 *bp = netdev_priv(dev);
6084 memset(buf, 0, sizeof(u64) * BNX2_NUM_TESTS);
6085 if (etest->flags & ETH_TEST_FL_OFFLINE) {
6088 bnx2_netif_stop(bp);
6089 bnx2_reset_chip(bp, BNX2_DRV_MSG_CODE_DIAG);
6092 if (bnx2_test_registers(bp) != 0) {
6094 etest->flags |= ETH_TEST_FL_FAILED;
6096 if (bnx2_test_memory(bp) != 0) {
6098 etest->flags |= ETH_TEST_FL_FAILED;
6100 if ((buf[2] = bnx2_test_loopback(bp)) != 0)
6101 etest->flags |= ETH_TEST_FL_FAILED;
6103 if (!netif_running(bp->dev)) {
6104 bnx2_reset_chip(bp, BNX2_DRV_MSG_CODE_RESET);
6108 bnx2_netif_start(bp);
6111 /* wait for link up */
6112 for (i = 0; i < 7; i++) {
6115 msleep_interruptible(1000);
6119 if (bnx2_test_nvram(bp) != 0) {
6121 etest->flags |= ETH_TEST_FL_FAILED;
6123 if (bnx2_test_intr(bp) != 0) {
6125 etest->flags |= ETH_TEST_FL_FAILED;
6128 if (bnx2_test_link(bp) != 0) {
6130 etest->flags |= ETH_TEST_FL_FAILED;
6136 bnx2_get_strings(struct net_device *dev, u32 stringset, u8 *buf)
6138 switch (stringset) {
6140 memcpy(buf, bnx2_stats_str_arr,
6141 sizeof(bnx2_stats_str_arr));
6144 memcpy(buf, bnx2_tests_str_arr,
6145 sizeof(bnx2_tests_str_arr));
6151 bnx2_get_stats_count(struct net_device *dev)
6153 return BNX2_NUM_STATS;
6157 bnx2_get_ethtool_stats(struct net_device *dev,
6158 struct ethtool_stats *stats, u64 *buf)
6160 struct bnx2 *bp = netdev_priv(dev);
6162 u32 *hw_stats = (u32 *) bp->stats_blk;
6163 u8 *stats_len_arr = NULL;
6165 if (hw_stats == NULL) {
6166 memset(buf, 0, sizeof(u64) * BNX2_NUM_STATS);
6170 if ((CHIP_ID(bp) == CHIP_ID_5706_A0) ||
6171 (CHIP_ID(bp) == CHIP_ID_5706_A1) ||
6172 (CHIP_ID(bp) == CHIP_ID_5706_A2) ||
6173 (CHIP_ID(bp) == CHIP_ID_5708_A0))
6174 stats_len_arr = bnx2_5706_stats_len_arr;
6176 stats_len_arr = bnx2_5708_stats_len_arr;
6178 for (i = 0; i < BNX2_NUM_STATS; i++) {
6179 if (stats_len_arr[i] == 0) {
6180 /* skip this counter */
6184 if (stats_len_arr[i] == 4) {
6185 /* 4-byte counter */
6187 *(hw_stats + bnx2_stats_offset_arr[i]);
6190 /* 8-byte counter */
6191 buf[i] = (((u64) *(hw_stats +
6192 bnx2_stats_offset_arr[i])) << 32) +
6193 *(hw_stats + bnx2_stats_offset_arr[i] + 1);
6198 bnx2_phys_id(struct net_device *dev, u32 data)
6200 struct bnx2 *bp = netdev_priv(dev);
6207 save = REG_RD(bp, BNX2_MISC_CFG);
6208 REG_WR(bp, BNX2_MISC_CFG, BNX2_MISC_CFG_LEDMODE_MAC);
6210 for (i = 0; i < (data * 2); i++) {
6212 REG_WR(bp, BNX2_EMAC_LED, BNX2_EMAC_LED_OVERRIDE);
6215 REG_WR(bp, BNX2_EMAC_LED, BNX2_EMAC_LED_OVERRIDE |
6216 BNX2_EMAC_LED_1000MB_OVERRIDE |
6217 BNX2_EMAC_LED_100MB_OVERRIDE |
6218 BNX2_EMAC_LED_10MB_OVERRIDE |
6219 BNX2_EMAC_LED_TRAFFIC_OVERRIDE |
6220 BNX2_EMAC_LED_TRAFFIC);
6222 msleep_interruptible(500);
6223 if (signal_pending(current))
6226 REG_WR(bp, BNX2_EMAC_LED, 0);
6227 REG_WR(bp, BNX2_MISC_CFG, save);
6232 bnx2_set_tx_csum(struct net_device *dev, u32 data)
6234 struct bnx2 *bp = netdev_priv(dev);
6236 if (CHIP_NUM(bp) == CHIP_NUM_5709)
6237 return (ethtool_op_set_tx_ipv6_csum(dev, data));
6239 return (ethtool_op_set_tx_csum(dev, data));
6242 static const struct ethtool_ops bnx2_ethtool_ops = {
6243 .get_settings = bnx2_get_settings,
6244 .set_settings = bnx2_set_settings,
6245 .get_drvinfo = bnx2_get_drvinfo,
6246 .get_regs_len = bnx2_get_regs_len,
6247 .get_regs = bnx2_get_regs,
6248 .get_wol = bnx2_get_wol,
6249 .set_wol = bnx2_set_wol,
6250 .nway_reset = bnx2_nway_reset,
6251 .get_link = ethtool_op_get_link,
6252 .get_eeprom_len = bnx2_get_eeprom_len,
6253 .get_eeprom = bnx2_get_eeprom,
6254 .set_eeprom = bnx2_set_eeprom,
6255 .get_coalesce = bnx2_get_coalesce,
6256 .set_coalesce = bnx2_set_coalesce,
6257 .get_ringparam = bnx2_get_ringparam,
6258 .set_ringparam = bnx2_set_ringparam,
6259 .get_pauseparam = bnx2_get_pauseparam,
6260 .set_pauseparam = bnx2_set_pauseparam,
6261 .get_rx_csum = bnx2_get_rx_csum,
6262 .set_rx_csum = bnx2_set_rx_csum,
6263 .get_tx_csum = ethtool_op_get_tx_csum,
6264 .set_tx_csum = bnx2_set_tx_csum,
6265 .get_sg = ethtool_op_get_sg,
6266 .set_sg = ethtool_op_set_sg,
6267 .get_tso = ethtool_op_get_tso,
6268 .set_tso = bnx2_set_tso,
6269 .self_test_count = bnx2_self_test_count,
6270 .self_test = bnx2_self_test,
6271 .get_strings = bnx2_get_strings,
6272 .phys_id = bnx2_phys_id,
6273 .get_stats_count = bnx2_get_stats_count,
6274 .get_ethtool_stats = bnx2_get_ethtool_stats,
6275 .get_perm_addr = ethtool_op_get_perm_addr,
6278 /* Called with rtnl_lock */
6280 bnx2_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
6282 struct mii_ioctl_data *data = if_mii(ifr);
6283 struct bnx2 *bp = netdev_priv(dev);
6288 data->phy_id = bp->phy_addr;
6294 if (bp->phy_flags & REMOTE_PHY_CAP_FLAG)
6297 if (!netif_running(dev))
6300 spin_lock_bh(&bp->phy_lock);
6301 err = bnx2_read_phy(bp, data->reg_num & 0x1f, &mii_regval);
6302 spin_unlock_bh(&bp->phy_lock);
6304 data->val_out = mii_regval;
6310 if (!capable(CAP_NET_ADMIN))
6313 if (bp->phy_flags & REMOTE_PHY_CAP_FLAG)
6316 if (!netif_running(dev))
6319 spin_lock_bh(&bp->phy_lock);
6320 err = bnx2_write_phy(bp, data->reg_num & 0x1f, data->val_in);
6321 spin_unlock_bh(&bp->phy_lock);
6332 /* Called with rtnl_lock */
6334 bnx2_change_mac_addr(struct net_device *dev, void *p)
6336 struct sockaddr *addr = p;
6337 struct bnx2 *bp = netdev_priv(dev);
6339 if (!is_valid_ether_addr(addr->sa_data))
6342 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
6343 if (netif_running(dev))
6344 bnx2_set_mac_addr(bp);
6349 /* Called with rtnl_lock */
6351 bnx2_change_mtu(struct net_device *dev, int new_mtu)
6353 struct bnx2 *bp = netdev_priv(dev);
6355 if (((new_mtu + ETH_HLEN) > MAX_ETHERNET_JUMBO_PACKET_SIZE) ||
6356 ((new_mtu + ETH_HLEN) < MIN_ETHERNET_PACKET_SIZE))
6360 if (netif_running(dev)) {
6361 bnx2_netif_stop(bp);
6365 bnx2_netif_start(bp);
6370 #if defined(HAVE_POLL_CONTROLLER) || defined(CONFIG_NET_POLL_CONTROLLER)
6372 poll_bnx2(struct net_device *dev)
6374 struct bnx2 *bp = netdev_priv(dev);
6376 disable_irq(bp->pdev->irq);
6377 bnx2_interrupt(bp->pdev->irq, dev);
6378 enable_irq(bp->pdev->irq);
6382 static void __devinit
6383 bnx2_get_5709_media(struct bnx2 *bp)
6385 u32 val = REG_RD(bp, BNX2_MISC_DUAL_MEDIA_CTRL);
6386 u32 bond_id = val & BNX2_MISC_DUAL_MEDIA_CTRL_BOND_ID;
6389 if (bond_id == BNX2_MISC_DUAL_MEDIA_CTRL_BOND_ID_C)
6391 else if (bond_id == BNX2_MISC_DUAL_MEDIA_CTRL_BOND_ID_S) {
6392 bp->phy_flags |= PHY_SERDES_FLAG;
6396 if (val & BNX2_MISC_DUAL_MEDIA_CTRL_STRAP_OVERRIDE)
6397 strap = (val & BNX2_MISC_DUAL_MEDIA_CTRL_PHY_CTRL) >> 21;
6399 strap = (val & BNX2_MISC_DUAL_MEDIA_CTRL_PHY_CTRL_STRAP) >> 8;
6401 if (PCI_FUNC(bp->pdev->devfn) == 0) {
6406 bp->phy_flags |= PHY_SERDES_FLAG;
6414 bp->phy_flags |= PHY_SERDES_FLAG;
6420 static void __devinit
6421 bnx2_get_pci_speed(struct bnx2 *bp)
6425 reg = REG_RD(bp, BNX2_PCICFG_MISC_STATUS);
6426 if (reg & BNX2_PCICFG_MISC_STATUS_PCIX_DET) {
6429 bp->flags |= PCIX_FLAG;
6431 clkreg = REG_RD(bp, BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS);
6433 clkreg &= BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET;
6435 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_133MHZ:
6436 bp->bus_speed_mhz = 133;
6439 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_95MHZ:
6440 bp->bus_speed_mhz = 100;
6443 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_66MHZ:
6444 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_80MHZ:
6445 bp->bus_speed_mhz = 66;
6448 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_48MHZ:
6449 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_55MHZ:
6450 bp->bus_speed_mhz = 50;
6453 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_LOW:
6454 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_32MHZ:
6455 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_38MHZ:
6456 bp->bus_speed_mhz = 33;
6461 if (reg & BNX2_PCICFG_MISC_STATUS_M66EN)
6462 bp->bus_speed_mhz = 66;
6464 bp->bus_speed_mhz = 33;
6467 if (reg & BNX2_PCICFG_MISC_STATUS_32BIT_DET)
6468 bp->flags |= PCI_32BIT_FLAG;
6472 static int __devinit
6473 bnx2_init_board(struct pci_dev *pdev, struct net_device *dev)
6476 unsigned long mem_len;
6479 u64 dma_mask, persist_dma_mask;
6481 SET_MODULE_OWNER(dev);
6482 SET_NETDEV_DEV(dev, &pdev->dev);
6483 bp = netdev_priv(dev);
6488 /* enable device (incl. PCI PM wakeup), and bus-mastering */
6489 rc = pci_enable_device(pdev);
6491 dev_err(&pdev->dev, "Cannot enable PCI device, aborting.");
6495 if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
6497 "Cannot find PCI device base address, aborting.\n");
6499 goto err_out_disable;
6502 rc = pci_request_regions(pdev, DRV_MODULE_NAME);
6504 dev_err(&pdev->dev, "Cannot obtain PCI resources, aborting.\n");
6505 goto err_out_disable;
6508 pci_set_master(pdev);
6510 bp->pm_cap = pci_find_capability(pdev, PCI_CAP_ID_PM);
6511 if (bp->pm_cap == 0) {
6513 "Cannot find power management capability, aborting.\n");
6515 goto err_out_release;
6521 spin_lock_init(&bp->phy_lock);
6522 spin_lock_init(&bp->indirect_lock);
6523 INIT_WORK(&bp->reset_task, bnx2_reset_task);
6525 dev->base_addr = dev->mem_start = pci_resource_start(pdev, 0);
6526 mem_len = MB_GET_CID_ADDR(TX_TSS_CID + 1);
6527 dev->mem_end = dev->mem_start + mem_len;
6528 dev->irq = pdev->irq;
6530 bp->regview = ioremap_nocache(dev->base_addr, mem_len);
6533 dev_err(&pdev->dev, "Cannot map register space, aborting.\n");
6535 goto err_out_release;
6538 /* Configure byte swap and enable write to the reg_window registers.
6539 * Rely on CPU to do target byte swapping on big endian systems
6540 * The chip's target access swapping will not swap all accesses
6542 pci_write_config_dword(bp->pdev, BNX2_PCICFG_MISC_CONFIG,
6543 BNX2_PCICFG_MISC_CONFIG_REG_WINDOW_ENA |
6544 BNX2_PCICFG_MISC_CONFIG_TARGET_MB_WORD_SWAP);
6546 bnx2_set_power_state(bp, PCI_D0);
6548 bp->chip_id = REG_RD(bp, BNX2_MISC_ID);
6550 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
6551 if (pci_find_capability(pdev, PCI_CAP_ID_EXP) == 0) {
6553 "Cannot find PCIE capability, aborting.\n");
6557 bp->flags |= PCIE_FLAG;
6559 bp->pcix_cap = pci_find_capability(pdev, PCI_CAP_ID_PCIX);
6560 if (bp->pcix_cap == 0) {
6562 "Cannot find PCIX capability, aborting.\n");
6568 if (CHIP_ID(bp) != CHIP_ID_5706_A0 && CHIP_ID(bp) != CHIP_ID_5706_A1) {
6569 if (pci_find_capability(pdev, PCI_CAP_ID_MSI))
6570 bp->flags |= MSI_CAP_FLAG;
6573 /* 5708 cannot support DMA addresses > 40-bit. */
6574 if (CHIP_NUM(bp) == CHIP_NUM_5708)
6575 persist_dma_mask = dma_mask = DMA_40BIT_MASK;
6577 persist_dma_mask = dma_mask = DMA_64BIT_MASK;
6579 /* Configure DMA attributes. */
6580 if (pci_set_dma_mask(pdev, dma_mask) == 0) {
6581 dev->features |= NETIF_F_HIGHDMA;
6582 rc = pci_set_consistent_dma_mask(pdev, persist_dma_mask);
6585 "pci_set_consistent_dma_mask failed, aborting.\n");
6588 } else if ((rc = pci_set_dma_mask(pdev, DMA_32BIT_MASK)) != 0) {
6589 dev_err(&pdev->dev, "System does not support DMA, aborting.\n");
6593 if (!(bp->flags & PCIE_FLAG))
6594 bnx2_get_pci_speed(bp);
6596 /* 5706A0 may falsely detect SERR and PERR. */
6597 if (CHIP_ID(bp) == CHIP_ID_5706_A0) {
6598 reg = REG_RD(bp, PCI_COMMAND);
6599 reg &= ~(PCI_COMMAND_SERR | PCI_COMMAND_PARITY);
6600 REG_WR(bp, PCI_COMMAND, reg);
6602 else if ((CHIP_ID(bp) == CHIP_ID_5706_A1) &&
6603 !(bp->flags & PCIX_FLAG)) {
6606 "5706 A1 can only be used in a PCIX bus, aborting.\n");
6610 bnx2_init_nvram(bp);
6612 reg = REG_RD_IND(bp, BNX2_SHM_HDR_SIGNATURE);
6614 if ((reg & BNX2_SHM_HDR_SIGNATURE_SIG_MASK) ==
6615 BNX2_SHM_HDR_SIGNATURE_SIG) {
6616 u32 off = PCI_FUNC(pdev->devfn) << 2;
6618 bp->shmem_base = REG_RD_IND(bp, BNX2_SHM_HDR_ADDR_0 + off);
6620 bp->shmem_base = HOST_VIEW_SHMEM_BASE;
6622 /* Get the permanent MAC address. First we need to make sure the
6623 * firmware is actually running.
6625 reg = REG_RD_IND(bp, bp->shmem_base + BNX2_DEV_INFO_SIGNATURE);
6627 if ((reg & BNX2_DEV_INFO_SIGNATURE_MAGIC_MASK) !=
6628 BNX2_DEV_INFO_SIGNATURE_MAGIC) {
6629 dev_err(&pdev->dev, "Firmware not running, aborting.\n");
6634 reg = REG_RD_IND(bp, bp->shmem_base + BNX2_DEV_INFO_BC_REV);
6635 for (i = 0, j = 0; i < 3; i++) {
6638 num = (u8) (reg >> (24 - (i * 8)));
6639 for (k = 100, skip0 = 1; k >= 1; num %= k, k /= 10) {
6640 if (num >= k || !skip0 || k == 1) {
6641 bp->fw_version[j++] = (num / k) + '0';
6646 bp->fw_version[j++] = '.';
6648 reg = REG_RD_IND(bp, bp->shmem_base + BNX2_BC_STATE_CONDITION);
6649 reg &= BNX2_CONDITION_MFW_RUN_MASK;
6650 if (reg != BNX2_CONDITION_MFW_RUN_UNKNOWN &&
6651 reg != BNX2_CONDITION_MFW_RUN_NONE) {
6653 u32 addr = REG_RD_IND(bp, bp->shmem_base + BNX2_MFW_VER_PTR);
6655 bp->fw_version[j++] = ' ';
6656 for (i = 0; i < 3; i++) {
6657 reg = REG_RD_IND(bp, addr + i * 4);
6659 memcpy(&bp->fw_version[j], ®, 4);
6664 reg = REG_RD_IND(bp, bp->shmem_base + BNX2_PORT_HW_CFG_MAC_UPPER);
6665 bp->mac_addr[0] = (u8) (reg >> 8);
6666 bp->mac_addr[1] = (u8) reg;
6668 reg = REG_RD_IND(bp, bp->shmem_base + BNX2_PORT_HW_CFG_MAC_LOWER);
6669 bp->mac_addr[2] = (u8) (reg >> 24);
6670 bp->mac_addr[3] = (u8) (reg >> 16);
6671 bp->mac_addr[4] = (u8) (reg >> 8);
6672 bp->mac_addr[5] = (u8) reg;
6674 bp->tx_ring_size = MAX_TX_DESC_CNT;
6675 bnx2_set_rx_ring_size(bp, 255);
6679 bp->rx_offset = sizeof(struct l2_fhdr) + 2;
6681 bp->tx_quick_cons_trip_int = 20;
6682 bp->tx_quick_cons_trip = 20;
6683 bp->tx_ticks_int = 80;
6686 bp->rx_quick_cons_trip_int = 6;
6687 bp->rx_quick_cons_trip = 6;
6688 bp->rx_ticks_int = 18;
6691 bp->stats_ticks = 1000000 & 0xffff00;
6693 bp->timer_interval = HZ;
6694 bp->current_interval = HZ;
6698 /* Disable WOL support if we are running on a SERDES chip. */
6699 if (CHIP_NUM(bp) == CHIP_NUM_5709)
6700 bnx2_get_5709_media(bp);
6701 else if (CHIP_BOND_ID(bp) & CHIP_BOND_ID_SERDES_BIT)
6702 bp->phy_flags |= PHY_SERDES_FLAG;
6704 bp->phy_port = PORT_TP;
6705 if (bp->phy_flags & PHY_SERDES_FLAG) {
6706 bp->phy_port = PORT_FIBRE;
6707 bp->flags |= NO_WOL_FLAG;
6708 if (CHIP_NUM(bp) != CHIP_NUM_5706) {
6710 reg = REG_RD_IND(bp, bp->shmem_base +
6711 BNX2_SHARED_HW_CFG_CONFIG);
6712 if (reg & BNX2_SHARED_HW_CFG_PHY_2_5G)
6713 bp->phy_flags |= PHY_2_5G_CAPABLE_FLAG;
6715 bnx2_init_remote_phy(bp);
6717 } else if (CHIP_NUM(bp) == CHIP_NUM_5706 ||
6718 CHIP_NUM(bp) == CHIP_NUM_5708)
6719 bp->phy_flags |= PHY_CRC_FIX_FLAG;
6720 else if (CHIP_ID(bp) == CHIP_ID_5709_A0)
6721 bp->phy_flags |= PHY_DIS_EARLY_DAC_FLAG;
6723 if ((CHIP_ID(bp) == CHIP_ID_5708_A0) ||
6724 (CHIP_ID(bp) == CHIP_ID_5708_B0) ||
6725 (CHIP_ID(bp) == CHIP_ID_5708_B1))
6726 bp->flags |= NO_WOL_FLAG;
6728 if (CHIP_ID(bp) == CHIP_ID_5706_A0) {
6729 bp->tx_quick_cons_trip_int =
6730 bp->tx_quick_cons_trip;
6731 bp->tx_ticks_int = bp->tx_ticks;
6732 bp->rx_quick_cons_trip_int =
6733 bp->rx_quick_cons_trip;
6734 bp->rx_ticks_int = bp->rx_ticks;
6735 bp->comp_prod_trip_int = bp->comp_prod_trip;
6736 bp->com_ticks_int = bp->com_ticks;
6737 bp->cmd_ticks_int = bp->cmd_ticks;
6740 /* Disable MSI on 5706 if AMD 8132 bridge is found.
6742 * MSI is defined to be 32-bit write. The 5706 does 64-bit MSI writes
6743 * with byte enables disabled on the unused 32-bit word. This is legal
6744 * but causes problems on the AMD 8132 which will eventually stop
6745 * responding after a while.
6747 * AMD believes this incompatibility is unique to the 5706, and
6748 * prefers to locally disable MSI rather than globally disabling it.
6750 if (CHIP_NUM(bp) == CHIP_NUM_5706 && disable_msi == 0) {
6751 struct pci_dev *amd_8132 = NULL;
6753 while ((amd_8132 = pci_get_device(PCI_VENDOR_ID_AMD,
6754 PCI_DEVICE_ID_AMD_8132_BRIDGE,
6757 if (amd_8132->revision >= 0x10 &&
6758 amd_8132->revision <= 0x13) {
6760 pci_dev_put(amd_8132);
6766 bnx2_set_default_link(bp);
6767 bp->req_flow_ctrl = FLOW_CTRL_RX | FLOW_CTRL_TX;
6769 init_timer(&bp->timer);
6770 bp->timer.expires = RUN_AT(bp->timer_interval);
6771 bp->timer.data = (unsigned long) bp;
6772 bp->timer.function = bnx2_timer;
6778 iounmap(bp->regview);
6783 pci_release_regions(pdev);
6786 pci_disable_device(pdev);
6787 pci_set_drvdata(pdev, NULL);
6793 static char * __devinit
6794 bnx2_bus_string(struct bnx2 *bp, char *str)
6798 if (bp->flags & PCIE_FLAG) {
6799 s += sprintf(s, "PCI Express");
6801 s += sprintf(s, "PCI");
6802 if (bp->flags & PCIX_FLAG)
6803 s += sprintf(s, "-X");
6804 if (bp->flags & PCI_32BIT_FLAG)
6805 s += sprintf(s, " 32-bit");
6807 s += sprintf(s, " 64-bit");
6808 s += sprintf(s, " %dMHz", bp->bus_speed_mhz);
6813 static int __devinit
6814 bnx2_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
6816 static int version_printed = 0;
6817 struct net_device *dev = NULL;
6822 if (version_printed++ == 0)
6823 printk(KERN_INFO "%s", version);
6825 /* dev zeroed in init_etherdev */
6826 dev = alloc_etherdev(sizeof(*bp));
6831 rc = bnx2_init_board(pdev, dev);
6837 dev->open = bnx2_open;
6838 dev->hard_start_xmit = bnx2_start_xmit;
6839 dev->stop = bnx2_close;
6840 dev->get_stats = bnx2_get_stats;
6841 dev->set_multicast_list = bnx2_set_rx_mode;
6842 dev->do_ioctl = bnx2_ioctl;
6843 dev->set_mac_address = bnx2_change_mac_addr;
6844 dev->change_mtu = bnx2_change_mtu;
6845 dev->tx_timeout = bnx2_tx_timeout;
6846 dev->watchdog_timeo = TX_TIMEOUT;
6848 dev->vlan_rx_register = bnx2_vlan_rx_register;
6850 dev->poll = bnx2_poll;
6851 dev->ethtool_ops = &bnx2_ethtool_ops;
6854 bp = netdev_priv(dev);
6856 #if defined(HAVE_POLL_CONTROLLER) || defined(CONFIG_NET_POLL_CONTROLLER)
6857 dev->poll_controller = poll_bnx2;
6860 pci_set_drvdata(pdev, dev);
6862 memcpy(dev->dev_addr, bp->mac_addr, 6);
6863 memcpy(dev->perm_addr, bp->mac_addr, 6);
6864 bp->name = board_info[ent->driver_data].name;
6866 dev->features |= NETIF_F_IP_CSUM | NETIF_F_SG;
6867 if (CHIP_NUM(bp) == CHIP_NUM_5709)
6868 dev->features |= NETIF_F_IPV6_CSUM;
6871 dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
6873 dev->features |= NETIF_F_TSO | NETIF_F_TSO_ECN;
6874 if (CHIP_NUM(bp) == CHIP_NUM_5709)
6875 dev->features |= NETIF_F_TSO6;
6877 if ((rc = register_netdev(dev))) {
6878 dev_err(&pdev->dev, "Cannot register net device\n");
6880 iounmap(bp->regview);
6881 pci_release_regions(pdev);
6882 pci_disable_device(pdev);
6883 pci_set_drvdata(pdev, NULL);
6888 printk(KERN_INFO "%s: %s (%c%d) %s found at mem %lx, "
6892 ((CHIP_ID(bp) & 0xf000) >> 12) + 'A',
6893 ((CHIP_ID(bp) & 0x0ff0) >> 4),
6894 bnx2_bus_string(bp, str),
6898 printk("node addr ");
6899 for (i = 0; i < 6; i++)
6900 printk("%2.2x", dev->dev_addr[i]);
6906 static void __devexit
6907 bnx2_remove_one(struct pci_dev *pdev)
6909 struct net_device *dev = pci_get_drvdata(pdev);
6910 struct bnx2 *bp = netdev_priv(dev);
6912 flush_scheduled_work();
6914 unregister_netdev(dev);
6917 iounmap(bp->regview);
6920 pci_release_regions(pdev);
6921 pci_disable_device(pdev);
6922 pci_set_drvdata(pdev, NULL);
6926 bnx2_suspend(struct pci_dev *pdev, pm_message_t state)
6928 struct net_device *dev = pci_get_drvdata(pdev);
6929 struct bnx2 *bp = netdev_priv(dev);
6932 if (!netif_running(dev))
6935 flush_scheduled_work();
6936 bnx2_netif_stop(bp);
6937 netif_device_detach(dev);
6938 del_timer_sync(&bp->timer);
6939 if (bp->flags & NO_WOL_FLAG)
6940 reset_code = BNX2_DRV_MSG_CODE_UNLOAD_LNK_DN;
6942 reset_code = BNX2_DRV_MSG_CODE_SUSPEND_WOL;
6944 reset_code = BNX2_DRV_MSG_CODE_SUSPEND_NO_WOL;
6945 bnx2_reset_chip(bp, reset_code);
6947 pci_save_state(pdev);
6948 bnx2_set_power_state(bp, pci_choose_state(pdev, state));
6953 bnx2_resume(struct pci_dev *pdev)
6955 struct net_device *dev = pci_get_drvdata(pdev);
6956 struct bnx2 *bp = netdev_priv(dev);
6958 if (!netif_running(dev))
6961 pci_restore_state(pdev);
6962 bnx2_set_power_state(bp, PCI_D0);
6963 netif_device_attach(dev);
6965 bnx2_netif_start(bp);
6969 static struct pci_driver bnx2_pci_driver = {
6970 .name = DRV_MODULE_NAME,
6971 .id_table = bnx2_pci_tbl,
6972 .probe = bnx2_init_one,
6973 .remove = __devexit_p(bnx2_remove_one),
6974 .suspend = bnx2_suspend,
6975 .resume = bnx2_resume,
6978 static int __init bnx2_init(void)
6980 return pci_register_driver(&bnx2_pci_driver);
6983 static void __exit bnx2_cleanup(void)
6985 pci_unregister_driver(&bnx2_pci_driver);
6988 module_init(bnx2_init);
6989 module_exit(bnx2_cleanup);