3 * Alchemy Au1x00 ethernet driver
5 * Copyright 2001-2003, 2006 MontaVista Software Inc.
6 * Copyright 2002 TimeSys Corp.
7 * Added ethtool/mii-tool support,
8 * Copyright 2004 Matt Porter <mporter@kernel.crashing.org>
9 * Update: 2004 Bjoern Riemer, riemer@fokus.fraunhofer.de
10 * or riemer@riemer-nt.de: fixed the link beat detection with
11 * ioctls (SIOCGMIIPHY)
12 * Author: MontaVista Software, Inc.
13 * ppopov@mvista.com or source@mvista.com
15 * ########################################################################
17 * This program is free software; you can distribute it and/or modify it
18 * under the terms of the GNU General Public License (Version 2) as
19 * published by the Free Software Foundation.
21 * This program is distributed in the hope it will be useful, but WITHOUT
22 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
23 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
26 * You should have received a copy of the GNU General Public License along
27 * with this program; if not, write to the Free Software Foundation, Inc.,
28 * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
30 * ########################################################################
35 #include <linux/config.h>
36 #include <linux/module.h>
37 #include <linux/kernel.h>
38 #include <linux/sched.h>
39 #include <linux/string.h>
40 #include <linux/timer.h>
41 #include <linux/errno.h>
43 #include <linux/ioport.h>
44 #include <linux/bitops.h>
45 #include <linux/slab.h>
46 #include <linux/interrupt.h>
47 #include <linux/pci.h>
48 #include <linux/init.h>
49 #include <linux/netdevice.h>
50 #include <linux/etherdevice.h>
51 #include <linux/ethtool.h>
52 #include <linux/mii.h>
53 #include <linux/skbuff.h>
54 #include <linux/delay.h>
55 #include <linux/crc32.h>
56 #include <asm/mipsregs.h>
59 #include <asm/processor.h>
61 #include <asm/mach-au1x00/au1000.h>
63 #include "au1000_eth.h"
65 #ifdef AU1000_ETH_DEBUG
66 static int au1000_debug = 5;
68 static int au1000_debug = 3;
71 #define DRV_NAME "au1000_eth"
72 #define DRV_VERSION "1.5"
73 #define DRV_AUTHOR "Pete Popov <ppopov@embeddedalley.com>"
74 #define DRV_DESC "Au1xxx on-chip Ethernet driver"
76 MODULE_AUTHOR(DRV_AUTHOR);
77 MODULE_DESCRIPTION(DRV_DESC);
78 MODULE_LICENSE("GPL");
81 static void hard_stop(struct net_device *);
82 static void enable_rx_tx(struct net_device *dev);
83 static struct net_device * au1000_probe(int port_num);
84 static int au1000_init(struct net_device *);
85 static int au1000_open(struct net_device *);
86 static int au1000_close(struct net_device *);
87 static int au1000_tx(struct sk_buff *, struct net_device *);
88 static int au1000_rx(struct net_device *);
89 static irqreturn_t au1000_interrupt(int, void *, struct pt_regs *);
90 static void au1000_tx_timeout(struct net_device *);
91 static int au1000_set_config(struct net_device *dev, struct ifmap *map);
92 static void set_rx_mode(struct net_device *);
93 static struct net_device_stats *au1000_get_stats(struct net_device *);
94 static void au1000_timer(unsigned long);
95 static int au1000_ioctl(struct net_device *, struct ifreq *, int);
96 static int mdio_read(struct net_device *, int, int);
97 static void mdio_write(struct net_device *, int, int, u16);
98 static void dump_mii(struct net_device *dev, int phy_id);
101 extern void ack_rise_edge_irq(unsigned int);
102 extern int get_ethernet_addr(char *ethernet_addr);
103 extern void str2eaddr(unsigned char *ea, unsigned char *str);
104 extern char * __init prom_getcmdline(void);
107 * Theory of operation
109 * The Au1000 MACs use a simple rx and tx descriptor ring scheme.
110 * There are four receive and four transmit descriptors. These
111 * descriptors are not in memory; rather, they are just a set of
112 * hardware registers.
114 * Since the Au1000 has a coherent data cache, the receive and
115 * transmit buffers are allocated from the KSEG0 segment. The
116 * hardware registers, however, are still mapped at KSEG1 to
117 * make sure there's no out-of-order writes, and that all writes
118 * complete immediately.
121 /* These addresses are only used if yamon doesn't tell us what
122 * the mac address is, and the mac address is not passed on the
125 static unsigned char au1000_mac_addr[6] __devinitdata = {
126 0x00, 0x50, 0xc2, 0x0c, 0x30, 0x00
129 #define nibswap(x) ((((x) >> 4) & 0x0f) | (((x) << 4) & 0xf0))
130 #define RUN_AT(x) (jiffies + (x))
132 // For reading/writing 32-bit words from/to DMA memory
133 #define cpu_to_dma32 cpu_to_be32
134 #define dma32_to_cpu be32_to_cpu
136 struct au1000_private *au_macs[NUM_ETH_INTERFACES];
139 * All of the PHY code really should be detached from the MAC
143 /* Default advertise */
144 #define GENMII_DEFAULT_ADVERTISE \
145 ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full | \
146 ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full | \
149 #define GENMII_DEFAULT_FEATURES \
150 SUPPORTED_10baseT_Half | SUPPORTED_10baseT_Full | \
151 SUPPORTED_100baseT_Half | SUPPORTED_100baseT_Full | \
154 int bcm_5201_init(struct net_device *dev, int phy_addr)
158 /* Stop auto-negotiation */
159 data = mdio_read(dev, phy_addr, MII_CONTROL);
160 mdio_write(dev, phy_addr, MII_CONTROL, data & ~MII_CNTL_AUTO);
162 /* Set advertisement to 10/100 and Half/Full duplex
163 * (full capabilities) */
164 data = mdio_read(dev, phy_addr, MII_ANADV);
165 data |= MII_NWAY_TX | MII_NWAY_TX_FDX | MII_NWAY_T_FDX | MII_NWAY_T;
166 mdio_write(dev, phy_addr, MII_ANADV, data);
168 /* Restart auto-negotiation */
169 data = mdio_read(dev, phy_addr, MII_CONTROL);
170 data |= MII_CNTL_RST_AUTO | MII_CNTL_AUTO;
171 mdio_write(dev, phy_addr, MII_CONTROL, data);
173 if (au1000_debug > 4)
174 dump_mii(dev, phy_addr);
178 int bcm_5201_reset(struct net_device *dev, int phy_addr)
180 s16 mii_control, timeout;
182 mii_control = mdio_read(dev, phy_addr, MII_CONTROL);
183 mdio_write(dev, phy_addr, MII_CONTROL, mii_control | MII_CNTL_RESET);
185 for (timeout = 100; timeout > 0; --timeout) {
186 mii_control = mdio_read(dev, phy_addr, MII_CONTROL);
187 if ((mii_control & MII_CNTL_RESET) == 0)
191 if (mii_control & MII_CNTL_RESET) {
192 printk(KERN_ERR "%s PHY reset timeout !\n", dev->name);
199 bcm_5201_status(struct net_device *dev, int phy_addr, u16 *link, u16 *speed)
202 struct au1000_private *aup;
205 printk(KERN_ERR "bcm_5201_status error: NULL dev\n");
208 aup = (struct au1000_private *) dev->priv;
210 mii_data = mdio_read(dev, aup->phy_addr, MII_STATUS);
211 if (mii_data & MII_STAT_LINK) {
213 mii_data = mdio_read(dev, aup->phy_addr, MII_AUX_CNTRL);
214 if (mii_data & MII_AUX_100) {
215 if (mii_data & MII_AUX_FDX) {
216 *speed = IF_PORT_100BASEFX;
217 dev->if_port = IF_PORT_100BASEFX;
220 *speed = IF_PORT_100BASETX;
221 dev->if_port = IF_PORT_100BASETX;
225 *speed = IF_PORT_10BASET;
226 dev->if_port = IF_PORT_10BASET;
233 dev->if_port = IF_PORT_UNKNOWN;
238 int lsi_80227_init(struct net_device *dev, int phy_addr)
240 if (au1000_debug > 4)
241 printk("lsi_80227_init\n");
243 /* restart auto-negotiation */
244 mdio_write(dev, phy_addr, MII_CONTROL,
245 MII_CNTL_F100 | MII_CNTL_AUTO | MII_CNTL_RST_AUTO); // | MII_CNTL_FDX);
248 /* set up LEDs to correct display */
249 #ifdef CONFIG_MIPS_MTX1
250 mdio_write(dev, phy_addr, 17, 0xff80);
252 mdio_write(dev, phy_addr, 17, 0xffc0);
255 if (au1000_debug > 4)
256 dump_mii(dev, phy_addr);
260 int lsi_80227_reset(struct net_device *dev, int phy_addr)
262 s16 mii_control, timeout;
264 if (au1000_debug > 4) {
265 printk("lsi_80227_reset\n");
266 dump_mii(dev, phy_addr);
269 mii_control = mdio_read(dev, phy_addr, MII_CONTROL);
270 mdio_write(dev, phy_addr, MII_CONTROL, mii_control | MII_CNTL_RESET);
272 for (timeout = 100; timeout > 0; --timeout) {
273 mii_control = mdio_read(dev, phy_addr, MII_CONTROL);
274 if ((mii_control & MII_CNTL_RESET) == 0)
278 if (mii_control & MII_CNTL_RESET) {
279 printk(KERN_ERR "%s PHY reset timeout !\n", dev->name);
286 lsi_80227_status(struct net_device *dev, int phy_addr, u16 *link, u16 *speed)
289 struct au1000_private *aup;
292 printk(KERN_ERR "lsi_80227_status error: NULL dev\n");
295 aup = (struct au1000_private *) dev->priv;
297 mii_data = mdio_read(dev, aup->phy_addr, MII_STATUS);
298 if (mii_data & MII_STAT_LINK) {
300 mii_data = mdio_read(dev, aup->phy_addr, MII_LSI_PHY_STAT);
301 if (mii_data & MII_LSI_PHY_STAT_SPD) {
302 if (mii_data & MII_LSI_PHY_STAT_FDX) {
303 *speed = IF_PORT_100BASEFX;
304 dev->if_port = IF_PORT_100BASEFX;
307 *speed = IF_PORT_100BASETX;
308 dev->if_port = IF_PORT_100BASETX;
312 *speed = IF_PORT_10BASET;
313 dev->if_port = IF_PORT_10BASET;
320 dev->if_port = IF_PORT_UNKNOWN;
325 int am79c901_init(struct net_device *dev, int phy_addr)
327 printk("am79c901_init\n");
331 int am79c901_reset(struct net_device *dev, int phy_addr)
333 printk("am79c901_reset\n");
338 am79c901_status(struct net_device *dev, int phy_addr, u16 *link, u16 *speed)
343 int am79c874_init(struct net_device *dev, int phy_addr)
347 /* 79c874 has quit resembled bit assignments to BCM5201 */
348 if (au1000_debug > 4)
349 printk("am79c847_init\n");
351 /* Stop auto-negotiation */
352 data = mdio_read(dev, phy_addr, MII_CONTROL);
353 mdio_write(dev, phy_addr, MII_CONTROL, data & ~MII_CNTL_AUTO);
355 /* Set advertisement to 10/100 and Half/Full duplex
356 * (full capabilities) */
357 data = mdio_read(dev, phy_addr, MII_ANADV);
358 data |= MII_NWAY_TX | MII_NWAY_TX_FDX | MII_NWAY_T_FDX | MII_NWAY_T;
359 mdio_write(dev, phy_addr, MII_ANADV, data);
361 /* Restart auto-negotiation */
362 data = mdio_read(dev, phy_addr, MII_CONTROL);
363 data |= MII_CNTL_RST_AUTO | MII_CNTL_AUTO;
365 mdio_write(dev, phy_addr, MII_CONTROL, data);
367 if (au1000_debug > 4) dump_mii(dev, phy_addr);
371 int am79c874_reset(struct net_device *dev, int phy_addr)
373 s16 mii_control, timeout;
375 if (au1000_debug > 4)
376 printk("am79c874_reset\n");
378 mii_control = mdio_read(dev, phy_addr, MII_CONTROL);
379 mdio_write(dev, phy_addr, MII_CONTROL, mii_control | MII_CNTL_RESET);
381 for (timeout = 100; timeout > 0; --timeout) {
382 mii_control = mdio_read(dev, phy_addr, MII_CONTROL);
383 if ((mii_control & MII_CNTL_RESET) == 0)
387 if (mii_control & MII_CNTL_RESET) {
388 printk(KERN_ERR "%s PHY reset timeout !\n", dev->name);
395 am79c874_status(struct net_device *dev, int phy_addr, u16 *link, u16 *speed)
398 struct au1000_private *aup;
400 // printk("am79c874_status\n");
402 printk(KERN_ERR "am79c874_status error: NULL dev\n");
406 aup = (struct au1000_private *) dev->priv;
407 mii_data = mdio_read(dev, aup->phy_addr, MII_STATUS);
409 if (mii_data & MII_STAT_LINK) {
411 mii_data = mdio_read(dev, aup->phy_addr, MII_AMD_PHY_STAT);
412 if (mii_data & MII_AMD_PHY_STAT_SPD) {
413 if (mii_data & MII_AMD_PHY_STAT_FDX) {
414 *speed = IF_PORT_100BASEFX;
415 dev->if_port = IF_PORT_100BASEFX;
418 *speed = IF_PORT_100BASETX;
419 dev->if_port = IF_PORT_100BASETX;
423 *speed = IF_PORT_10BASET;
424 dev->if_port = IF_PORT_10BASET;
431 dev->if_port = IF_PORT_UNKNOWN;
436 int lxt971a_init(struct net_device *dev, int phy_addr)
438 if (au1000_debug > 4)
439 printk("lxt971a_init\n");
441 /* restart auto-negotiation */
442 mdio_write(dev, phy_addr, MII_CONTROL,
443 MII_CNTL_F100 | MII_CNTL_AUTO | MII_CNTL_RST_AUTO | MII_CNTL_FDX);
445 /* set up LEDs to correct display */
446 mdio_write(dev, phy_addr, 20, 0x0422);
448 if (au1000_debug > 4)
449 dump_mii(dev, phy_addr);
453 int lxt971a_reset(struct net_device *dev, int phy_addr)
455 s16 mii_control, timeout;
457 if (au1000_debug > 4) {
458 printk("lxt971a_reset\n");
459 dump_mii(dev, phy_addr);
462 mii_control = mdio_read(dev, phy_addr, MII_CONTROL);
463 mdio_write(dev, phy_addr, MII_CONTROL, mii_control | MII_CNTL_RESET);
465 for (timeout = 100; timeout > 0; --timeout) {
466 mii_control = mdio_read(dev, phy_addr, MII_CONTROL);
467 if ((mii_control & MII_CNTL_RESET) == 0)
471 if (mii_control & MII_CNTL_RESET) {
472 printk(KERN_ERR "%s PHY reset timeout !\n", dev->name);
479 lxt971a_status(struct net_device *dev, int phy_addr, u16 *link, u16 *speed)
482 struct au1000_private *aup;
485 printk(KERN_ERR "lxt971a_status error: NULL dev\n");
488 aup = (struct au1000_private *) dev->priv;
490 mii_data = mdio_read(dev, aup->phy_addr, MII_STATUS);
491 if (mii_data & MII_STAT_LINK) {
493 mii_data = mdio_read(dev, aup->phy_addr, MII_INTEL_PHY_STAT);
494 if (mii_data & MII_INTEL_PHY_STAT_SPD) {
495 if (mii_data & MII_INTEL_PHY_STAT_FDX) {
496 *speed = IF_PORT_100BASEFX;
497 dev->if_port = IF_PORT_100BASEFX;
500 *speed = IF_PORT_100BASETX;
501 dev->if_port = IF_PORT_100BASETX;
505 *speed = IF_PORT_10BASET;
506 dev->if_port = IF_PORT_10BASET;
513 dev->if_port = IF_PORT_UNKNOWN;
518 int ks8995m_init(struct net_device *dev, int phy_addr)
522 // printk("ks8995m_init\n");
523 /* Stop auto-negotiation */
524 data = mdio_read(dev, phy_addr, MII_CONTROL);
525 mdio_write(dev, phy_addr, MII_CONTROL, data & ~MII_CNTL_AUTO);
527 /* Set advertisement to 10/100 and Half/Full duplex
528 * (full capabilities) */
529 data = mdio_read(dev, phy_addr, MII_ANADV);
530 data |= MII_NWAY_TX | MII_NWAY_TX_FDX | MII_NWAY_T_FDX | MII_NWAY_T;
531 mdio_write(dev, phy_addr, MII_ANADV, data);
533 /* Restart auto-negotiation */
534 data = mdio_read(dev, phy_addr, MII_CONTROL);
535 data |= MII_CNTL_RST_AUTO | MII_CNTL_AUTO;
536 mdio_write(dev, phy_addr, MII_CONTROL, data);
538 if (au1000_debug > 4) dump_mii(dev, phy_addr);
543 int ks8995m_reset(struct net_device *dev, int phy_addr)
545 s16 mii_control, timeout;
547 // printk("ks8995m_reset\n");
548 mii_control = mdio_read(dev, phy_addr, MII_CONTROL);
549 mdio_write(dev, phy_addr, MII_CONTROL, mii_control | MII_CNTL_RESET);
551 for (timeout = 100; timeout > 0; --timeout) {
552 mii_control = mdio_read(dev, phy_addr, MII_CONTROL);
553 if ((mii_control & MII_CNTL_RESET) == 0)
557 if (mii_control & MII_CNTL_RESET) {
558 printk(KERN_ERR "%s PHY reset timeout !\n", dev->name);
564 int ks8995m_status(struct net_device *dev, int phy_addr, u16 *link, u16 *speed)
567 struct au1000_private *aup;
570 printk(KERN_ERR "ks8995m_status error: NULL dev\n");
573 aup = (struct au1000_private *) dev->priv;
575 mii_data = mdio_read(dev, aup->phy_addr, MII_STATUS);
576 if (mii_data & MII_STAT_LINK) {
578 mii_data = mdio_read(dev, aup->phy_addr, MII_AUX_CNTRL);
579 if (mii_data & MII_AUX_100) {
580 if (mii_data & MII_AUX_FDX) {
581 *speed = IF_PORT_100BASEFX;
582 dev->if_port = IF_PORT_100BASEFX;
585 *speed = IF_PORT_100BASETX;
586 dev->if_port = IF_PORT_100BASETX;
590 *speed = IF_PORT_10BASET;
591 dev->if_port = IF_PORT_10BASET;
598 dev->if_port = IF_PORT_UNKNOWN;
604 smsc_83C185_init (struct net_device *dev, int phy_addr)
608 if (au1000_debug > 4)
609 printk("smsc_83C185_init\n");
611 /* Stop auto-negotiation */
612 data = mdio_read(dev, phy_addr, MII_CONTROL);
613 mdio_write(dev, phy_addr, MII_CONTROL, data & ~MII_CNTL_AUTO);
615 /* Set advertisement to 10/100 and Half/Full duplex
616 * (full capabilities) */
617 data = mdio_read(dev, phy_addr, MII_ANADV);
618 data |= MII_NWAY_TX | MII_NWAY_TX_FDX | MII_NWAY_T_FDX | MII_NWAY_T;
619 mdio_write(dev, phy_addr, MII_ANADV, data);
621 /* Restart auto-negotiation */
622 data = mdio_read(dev, phy_addr, MII_CONTROL);
623 data |= MII_CNTL_RST_AUTO | MII_CNTL_AUTO;
625 mdio_write(dev, phy_addr, MII_CONTROL, data);
627 if (au1000_debug > 4) dump_mii(dev, phy_addr);
632 smsc_83C185_reset (struct net_device *dev, int phy_addr)
634 s16 mii_control, timeout;
636 if (au1000_debug > 4)
637 printk("smsc_83C185_reset\n");
639 mii_control = mdio_read(dev, phy_addr, MII_CONTROL);
640 mdio_write(dev, phy_addr, MII_CONTROL, mii_control | MII_CNTL_RESET);
642 for (timeout = 100; timeout > 0; --timeout) {
643 mii_control = mdio_read(dev, phy_addr, MII_CONTROL);
644 if ((mii_control & MII_CNTL_RESET) == 0)
648 if (mii_control & MII_CNTL_RESET) {
649 printk(KERN_ERR "%s PHY reset timeout !\n", dev->name);
656 smsc_83C185_status (struct net_device *dev, int phy_addr, u16 *link, u16 *speed)
659 struct au1000_private *aup;
662 printk(KERN_ERR "smsc_83C185_status error: NULL dev\n");
666 aup = (struct au1000_private *) dev->priv;
667 mii_data = mdio_read(dev, aup->phy_addr, MII_STATUS);
669 if (mii_data & MII_STAT_LINK) {
671 mii_data = mdio_read(dev, aup->phy_addr, 0x1f);
672 if (mii_data & (1<<3)) {
673 if (mii_data & (1<<4)) {
674 *speed = IF_PORT_100BASEFX;
675 dev->if_port = IF_PORT_100BASEFX;
678 *speed = IF_PORT_100BASETX;
679 dev->if_port = IF_PORT_100BASETX;
683 *speed = IF_PORT_10BASET;
684 dev->if_port = IF_PORT_10BASET;
690 dev->if_port = IF_PORT_UNKNOWN;
696 #ifdef CONFIG_MIPS_BOSPORUS
697 int stub_init(struct net_device *dev, int phy_addr)
699 //printk("PHY stub_init\n");
703 int stub_reset(struct net_device *dev, int phy_addr)
705 //printk("PHY stub_reset\n");
710 stub_status(struct net_device *dev, int phy_addr, u16 *link, u16 *speed)
712 //printk("PHY stub_status\n");
715 *speed = IF_PORT_100BASEFX;
716 dev->if_port = IF_PORT_100BASEFX;
721 struct phy_ops bcm_5201_ops = {
727 struct phy_ops am79c874_ops = {
733 struct phy_ops am79c901_ops = {
739 struct phy_ops lsi_80227_ops = {
745 struct phy_ops lxt971a_ops = {
751 struct phy_ops ks8995m_ops = {
757 struct phy_ops smsc_83C185_ops = {
763 #ifdef CONFIG_MIPS_BOSPORUS
764 struct phy_ops stub_ops = {
771 static struct mii_chip_info {
775 struct phy_ops *phy_ops;
777 } mii_chip_table[] = {
778 {"Broadcom BCM5201 10/100 BaseT PHY",0x0040,0x6212, &bcm_5201_ops,0},
779 {"Broadcom BCM5221 10/100 BaseT PHY",0x0040,0x61e4, &bcm_5201_ops,0},
780 {"Broadcom BCM5222 10/100 BaseT PHY",0x0040,0x6322, &bcm_5201_ops,1},
781 {"NS DP83847 PHY", 0x2000, 0x5c30, &bcm_5201_ops ,0},
782 {"AMD 79C901 HomePNA PHY",0x0000,0x35c8, &am79c901_ops,0},
783 {"AMD 79C874 10/100 BaseT PHY",0x0022,0x561b, &am79c874_ops,0},
784 {"LSI 80227 10/100 BaseT PHY",0x0016,0xf840, &lsi_80227_ops,0},
785 {"Intel LXT971A Dual Speed PHY",0x0013,0x78e2, &lxt971a_ops,0},
786 {"Kendin KS8995M 10/100 BaseT PHY",0x0022,0x1450, &ks8995m_ops,0},
787 {"SMSC LAN83C185 10/100 BaseT PHY",0x0007,0xc0a3, &smsc_83C185_ops,0},
788 #ifdef CONFIG_MIPS_BOSPORUS
789 {"Stub", 0x1234, 0x5678, &stub_ops },
794 static int mdio_read(struct net_device *dev, int phy_id, int reg)
796 struct au1000_private *aup = (struct au1000_private *) dev->priv;
797 volatile u32 *mii_control_reg;
798 volatile u32 *mii_data_reg;
802 #ifdef CONFIG_BCM5222_DUAL_PHY
803 /* First time we probe, it's for the mac0 phy.
804 * Since we haven't determined yet that we have a dual phy,
805 * aup->mii->mii_control_reg won't be setup and we'll
806 * default to the else statement.
807 * By the time we probe for the mac1 phy, the mii_control_reg
808 * will be setup to be the address of the mac0 phy control since
809 * both phys are controlled through mac0.
811 if (aup->mii && aup->mii->mii_control_reg) {
812 mii_control_reg = aup->mii->mii_control_reg;
813 mii_data_reg = aup->mii->mii_data_reg;
815 else if (au_macs[0]->mii && au_macs[0]->mii->mii_control_reg) {
816 /* assume both phys are controlled through mac0 */
817 mii_control_reg = au_macs[0]->mii->mii_control_reg;
818 mii_data_reg = au_macs[0]->mii->mii_data_reg;
823 /* default control and data reg addresses */
824 mii_control_reg = &aup->mac->mii_control;
825 mii_data_reg = &aup->mac->mii_data;
828 while (*mii_control_reg & MAC_MII_BUSY) {
830 if (--timedout == 0) {
831 printk(KERN_ERR "%s: read_MII busy timeout!!\n",
837 mii_control = MAC_SET_MII_SELECT_REG(reg) |
838 MAC_SET_MII_SELECT_PHY(phy_id) | MAC_MII_READ;
840 *mii_control_reg = mii_control;
843 while (*mii_control_reg & MAC_MII_BUSY) {
845 if (--timedout == 0) {
846 printk(KERN_ERR "%s: mdio_read busy timeout!!\n",
851 return (int)*mii_data_reg;
854 static void mdio_write(struct net_device *dev, int phy_id, int reg, u16 value)
856 struct au1000_private *aup = (struct au1000_private *) dev->priv;
857 volatile u32 *mii_control_reg;
858 volatile u32 *mii_data_reg;
862 #ifdef CONFIG_BCM5222_DUAL_PHY
863 if (aup->mii && aup->mii->mii_control_reg) {
864 mii_control_reg = aup->mii->mii_control_reg;
865 mii_data_reg = aup->mii->mii_data_reg;
867 else if (au_macs[0]->mii && au_macs[0]->mii->mii_control_reg) {
868 /* assume both phys are controlled through mac0 */
869 mii_control_reg = au_macs[0]->mii->mii_control_reg;
870 mii_data_reg = au_macs[0]->mii->mii_data_reg;
875 /* default control and data reg addresses */
876 mii_control_reg = &aup->mac->mii_control;
877 mii_data_reg = &aup->mac->mii_data;
880 while (*mii_control_reg & MAC_MII_BUSY) {
882 if (--timedout == 0) {
883 printk(KERN_ERR "%s: mdio_write busy timeout!!\n",
889 mii_control = MAC_SET_MII_SELECT_REG(reg) |
890 MAC_SET_MII_SELECT_PHY(phy_id) | MAC_MII_WRITE;
892 *mii_data_reg = value;
893 *mii_control_reg = mii_control;
897 static void dump_mii(struct net_device *dev, int phy_id)
901 for (i = 0; i < 7; i++) {
902 if ((val = mdio_read(dev, phy_id, i)) >= 0)
903 printk("%s: MII Reg %d=%x\n", dev->name, i, val);
905 for (i = 16; i < 25; i++) {
906 if ((val = mdio_read(dev, phy_id, i)) >= 0)
907 printk("%s: MII Reg %d=%x\n", dev->name, i, val);
911 static int mii_probe (struct net_device * dev)
913 struct au1000_private *aup = (struct au1000_private *) dev->priv;
915 #ifdef CONFIG_MIPS_BOSPORUS
919 /* search for total of 32 possible mii phy addresses */
920 for (phy_addr = 0; phy_addr < 32; phy_addr++) {
922 u16 phy_id0, phy_id1;
925 #ifdef CONFIG_BCM5222_DUAL_PHY
926 /* Mask the already found phy, try next one */
927 if (au_macs[0]->mii && au_macs[0]->mii->mii_control_reg) {
928 if (au_macs[0]->phy_addr == phy_addr)
933 mii_status = mdio_read(dev, phy_addr, MII_STATUS);
934 if (mii_status == 0xffff || mii_status == 0x0000)
935 /* the mii is not accessable, try next one */
938 phy_id0 = mdio_read(dev, phy_addr, MII_PHY_ID0);
939 phy_id1 = mdio_read(dev, phy_addr, MII_PHY_ID1);
941 /* search our mii table for the current mii */
942 for (i = 0; mii_chip_table[i].phy_id1; i++) {
943 if (phy_id0 == mii_chip_table[i].phy_id0 &&
944 phy_id1 == mii_chip_table[i].phy_id1) {
945 struct mii_phy * mii_phy = aup->mii;
947 printk(KERN_INFO "%s: %s at phy address %d\n",
948 dev->name, mii_chip_table[i].name,
950 #ifdef CONFIG_MIPS_BOSPORUS
953 mii_phy->chip_info = mii_chip_table+i;
954 aup->phy_addr = phy_addr;
955 aup->want_autoneg = 1;
956 aup->phy_ops = mii_chip_table[i].phy_ops;
957 aup->phy_ops->phy_init(dev,phy_addr);
959 // Check for dual-phy and then store required
960 // values and set indicators. We need to do
961 // this now since mdio_{read,write} need the
962 // control and data register addresses.
963 #ifdef CONFIG_BCM5222_DUAL_PHY
964 if ( mii_chip_table[i].dual_phy) {
966 /* assume both phys are controlled
967 * through MAC0. Board specific? */
970 if (!au_macs[0] || !au_macs[0]->mii)
972 aup->mii->mii_control_reg = (u32 *)
973 &au_macs[0]->mac->mii_control;
974 aup->mii->mii_data_reg = (u32 *)
975 &au_macs[0]->mac->mii_data;
984 #ifdef CONFIG_MIPS_BOSPORUS
985 /* This is a workaround for the Micrel/Kendin 5 port switch
986 The second MAC doesn't see a PHY connected... so we need to
987 trick it into thinking we have one.
989 If this kernel is run on another Au1500 development board
990 the stub will be found as well as the actual PHY. However,
991 the last found PHY will be used... usually at Addr 31 (Db1500).
995 u16 phy_id0, phy_id1;
1001 /* search our mii table for the current mii */
1002 for (i = 0; mii_chip_table[i].phy_id1; i++) {
1003 if (phy_id0 == mii_chip_table[i].phy_id0 &&
1004 phy_id1 == mii_chip_table[i].phy_id1) {
1005 struct mii_phy * mii_phy;
1007 printk(KERN_INFO "%s: %s at phy address %d\n",
1008 dev->name, mii_chip_table[i].name,
1010 mii_phy = kmalloc(sizeof(struct mii_phy),
1013 mii_phy->chip_info = mii_chip_table+i;
1014 aup->phy_addr = phy_addr;
1015 mii_phy->next = aup->mii;
1017 mii_chip_table[i].phy_ops;
1019 aup->phy_ops->phy_init(dev,phy_addr);
1021 printk(KERN_ERR "%s: out of memory\n",
1025 mii_phy->chip_info = mii_chip_table+i;
1026 aup->phy_addr = phy_addr;
1027 aup->phy_ops = mii_chip_table[i].phy_ops;
1028 aup->phy_ops->phy_init(dev,phy_addr);
1033 if (aup->mac_id == 0) {
1034 /* the Bosporus phy responds to addresses 0-5 but
1035 * 5 is the correct one.
1041 if (aup->mii->chip_info == NULL) {
1042 printk(KERN_ERR "%s: Au1x No known MII transceivers found!\n",
1047 printk(KERN_INFO "%s: Using %s as default\n",
1048 dev->name, aup->mii->chip_info->name);
1055 * Buffer allocation/deallocation routines. The buffer descriptor returned
1056 * has the virtual and dma address of a buffer suitable for
1057 * both, receive and transmit operations.
1059 static db_dest_t *GetFreeDB(struct au1000_private *aup)
1065 aup->pDBfree = pDB->pnext;
1070 void ReleaseDB(struct au1000_private *aup, db_dest_t *pDB)
1072 db_dest_t *pDBfree = aup->pDBfree;
1074 pDBfree->pnext = pDB;
1078 static void enable_rx_tx(struct net_device *dev)
1080 struct au1000_private *aup = (struct au1000_private *) dev->priv;
1082 if (au1000_debug > 4)
1083 printk(KERN_INFO "%s: enable_rx_tx\n", dev->name);
1085 aup->mac->control |= (MAC_RX_ENABLE | MAC_TX_ENABLE);
1089 static void hard_stop(struct net_device *dev)
1091 struct au1000_private *aup = (struct au1000_private *) dev->priv;
1093 if (au1000_debug > 4)
1094 printk(KERN_INFO "%s: hard stop\n", dev->name);
1096 aup->mac->control &= ~(MAC_RX_ENABLE | MAC_TX_ENABLE);
1101 static void reset_mac(struct net_device *dev)
1105 struct au1000_private *aup = (struct au1000_private *) dev->priv;
1107 if (au1000_debug > 4)
1108 printk(KERN_INFO "%s: reset mac, aup %x\n",
1109 dev->name, (unsigned)aup);
1111 spin_lock_irqsave(&aup->lock, flags);
1112 if (aup->timer.function == &au1000_timer) {/* check if timer initted */
1113 del_timer(&aup->timer);
1117 #ifdef CONFIG_BCM5222_DUAL_PHY
1118 if (aup->mac_id != 0) {
1120 /* If BCM5222, we can't leave MAC0 in reset because then
1121 * we can't access the dual phy for ETH1 */
1122 *aup->enable = MAC_EN_CLOCK_ENABLE;
1126 #ifdef CONFIG_BCM5222_DUAL_PHY
1130 for (i = 0; i < NUM_RX_DMA; i++) {
1131 /* reset control bits */
1132 aup->rx_dma_ring[i]->buff_stat &= ~0xf;
1134 for (i = 0; i < NUM_TX_DMA; i++) {
1135 /* reset control bits */
1136 aup->tx_dma_ring[i]->buff_stat &= ~0xf;
1138 spin_unlock_irqrestore(&aup->lock, flags);
1143 * Setup the receive and transmit "rings". These pointers are the addresses
1144 * of the rx and tx MAC DMA registers so they are fixed by the hardware --
1145 * these are not descriptors sitting in memory.
1148 setup_hw_rings(struct au1000_private *aup, u32 rx_base, u32 tx_base)
1152 for (i = 0; i < NUM_RX_DMA; i++) {
1153 aup->rx_dma_ring[i] =
1154 (volatile rx_dma_t *) (rx_base + sizeof(rx_dma_t)*i);
1156 for (i = 0; i < NUM_TX_DMA; i++) {
1157 aup->tx_dma_ring[i] =
1158 (volatile tx_dma_t *) (tx_base + sizeof(tx_dma_t)*i);
1166 struct net_device *dev;
1168 #ifdef CONFIG_SOC_AU1000
1169 {AU1000_ETH0_BASE, AU1000_MAC0_ENABLE, AU1000_MAC0_DMA_INT},
1170 {AU1000_ETH1_BASE, AU1000_MAC1_ENABLE, AU1000_MAC1_DMA_INT}
1172 #ifdef CONFIG_SOC_AU1100
1173 {AU1100_ETH0_BASE, AU1100_MAC0_ENABLE, AU1100_MAC0_DMA_INT}
1175 #ifdef CONFIG_SOC_AU1500
1176 {AU1500_ETH0_BASE, AU1500_MAC0_ENABLE, AU1500_MAC0_DMA_INT},
1177 {AU1500_ETH1_BASE, AU1500_MAC1_ENABLE, AU1500_MAC1_DMA_INT}
1179 #ifdef CONFIG_SOC_AU1550
1180 {AU1550_ETH0_BASE, AU1550_MAC0_ENABLE, AU1550_MAC0_DMA_INT},
1181 {AU1550_ETH1_BASE, AU1550_MAC1_ENABLE, AU1550_MAC1_DMA_INT}
1188 * Setup the base address and interupt of the Au1xxx ethernet macs
1189 * based on cpu type and whether the interface is enabled in sys_pinfunc
1190 * register. The last interface is enabled if SYS_PF_NI2 (bit 4) is 0.
1192 static int __init au1000_init_module(void)
1194 int ni = (int)((au_readl(SYS_PINFUNC) & (u32)(SYS_PF_NI2)) >> 4);
1195 struct net_device *dev;
1196 int i, found_one = 0;
1198 num_ifs = NUM_ETH_INTERFACES - ni;
1200 for(i = 0; i < num_ifs; i++) {
1201 dev = au1000_probe(i);
1202 iflist[i].dev = dev;
1211 static int au1000_setup_aneg(struct net_device *dev, u32 advertise)
1213 struct au1000_private *aup = (struct au1000_private *)dev->priv;
1216 /* Setup standard advertise */
1217 adv = mdio_read(dev, aup->phy_addr, MII_ADVERTISE);
1218 adv &= ~(ADVERTISE_ALL | ADVERTISE_100BASE4);
1219 if (advertise & ADVERTISED_10baseT_Half)
1220 adv |= ADVERTISE_10HALF;
1221 if (advertise & ADVERTISED_10baseT_Full)
1222 adv |= ADVERTISE_10FULL;
1223 if (advertise & ADVERTISED_100baseT_Half)
1224 adv |= ADVERTISE_100HALF;
1225 if (advertise & ADVERTISED_100baseT_Full)
1226 adv |= ADVERTISE_100FULL;
1227 mdio_write(dev, aup->phy_addr, MII_ADVERTISE, adv);
1229 /* Start/Restart aneg */
1230 ctl = mdio_read(dev, aup->phy_addr, MII_BMCR);
1231 ctl |= (BMCR_ANENABLE | BMCR_ANRESTART);
1232 mdio_write(dev, aup->phy_addr, MII_BMCR, ctl);
1237 static int au1000_setup_forced(struct net_device *dev, int speed, int fd)
1239 struct au1000_private *aup = (struct au1000_private *)dev->priv;
1242 ctl = mdio_read(dev, aup->phy_addr, MII_BMCR);
1243 ctl &= ~(BMCR_FULLDPLX | BMCR_SPEED100 | BMCR_ANENABLE);
1245 /* First reset the PHY */
1246 mdio_write(dev, aup->phy_addr, MII_BMCR, ctl | BMCR_RESET);
1248 /* Select speed & duplex */
1253 ctl |= BMCR_SPEED100;
1259 if (fd == DUPLEX_FULL)
1260 ctl |= BMCR_FULLDPLX;
1261 mdio_write(dev, aup->phy_addr, MII_BMCR, ctl);
1268 au1000_start_link(struct net_device *dev, struct ethtool_cmd *cmd)
1270 struct au1000_private *aup = (struct au1000_private *)dev->priv;
1276 /* Default advertise */
1277 advertise = GENMII_DEFAULT_ADVERTISE;
1278 autoneg = aup->want_autoneg;
1279 forced_speed = SPEED_100;
1280 forced_duplex = DUPLEX_FULL;
1282 /* Setup link parameters */
1284 if (cmd->autoneg == AUTONEG_ENABLE) {
1285 advertise = cmd->advertising;
1290 forced_speed = cmd->speed;
1291 forced_duplex = cmd->duplex;
1295 /* Configure PHY & start aneg */
1296 aup->want_autoneg = autoneg;
1298 au1000_setup_aneg(dev, advertise);
1300 au1000_setup_forced(dev, forced_speed, forced_duplex);
1301 mod_timer(&aup->timer, jiffies + HZ);
1304 static int au1000_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1306 struct au1000_private *aup = (struct au1000_private *)dev->priv;
1309 cmd->supported = GENMII_DEFAULT_FEATURES;
1310 cmd->advertising = GENMII_DEFAULT_ADVERTISE;
1311 cmd->port = PORT_MII;
1312 cmd->transceiver = XCVR_EXTERNAL;
1313 cmd->phy_address = aup->phy_addr;
1314 spin_lock_irq(&aup->lock);
1315 cmd->autoneg = aup->want_autoneg;
1316 aup->phy_ops->phy_status(dev, aup->phy_addr, &link, &speed);
1317 if ((speed == IF_PORT_100BASETX) || (speed == IF_PORT_100BASEFX))
1318 cmd->speed = SPEED_100;
1319 else if (speed == IF_PORT_10BASET)
1320 cmd->speed = SPEED_10;
1321 if (link && (dev->if_port == IF_PORT_100BASEFX))
1322 cmd->duplex = DUPLEX_FULL;
1324 cmd->duplex = DUPLEX_HALF;
1325 spin_unlock_irq(&aup->lock);
1329 static int au1000_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1331 struct au1000_private *aup = (struct au1000_private *)dev->priv;
1332 unsigned long features = GENMII_DEFAULT_FEATURES;
1334 if (!capable(CAP_NET_ADMIN))
1337 if (cmd->autoneg != AUTONEG_ENABLE && cmd->autoneg != AUTONEG_DISABLE)
1339 if (cmd->autoneg == AUTONEG_ENABLE && cmd->advertising == 0)
1341 if (cmd->duplex != DUPLEX_HALF && cmd->duplex != DUPLEX_FULL)
1343 if (cmd->autoneg == AUTONEG_DISABLE)
1344 switch (cmd->speed) {
1346 if (cmd->duplex == DUPLEX_HALF &&
1347 (features & SUPPORTED_10baseT_Half) == 0)
1349 if (cmd->duplex == DUPLEX_FULL &&
1350 (features & SUPPORTED_10baseT_Full) == 0)
1354 if (cmd->duplex == DUPLEX_HALF &&
1355 (features & SUPPORTED_100baseT_Half) == 0)
1357 if (cmd->duplex == DUPLEX_FULL &&
1358 (features & SUPPORTED_100baseT_Full) == 0)
1364 else if ((features & SUPPORTED_Autoneg) == 0)
1367 spin_lock_irq(&aup->lock);
1368 au1000_start_link(dev, cmd);
1369 spin_unlock_irq(&aup->lock);
1373 static int au1000_nway_reset(struct net_device *dev)
1375 struct au1000_private *aup = (struct au1000_private *)dev->priv;
1377 if (!aup->want_autoneg)
1379 spin_lock_irq(&aup->lock);
1380 au1000_start_link(dev, NULL);
1381 spin_unlock_irq(&aup->lock);
1386 au1000_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
1388 struct au1000_private *aup = (struct au1000_private *)dev->priv;
1390 strcpy(info->driver, DRV_NAME);
1391 strcpy(info->version, DRV_VERSION);
1392 info->fw_version[0] = '\0';
1393 sprintf(info->bus_info, "%s %d", DRV_NAME, aup->mac_id);
1394 info->regdump_len = 0;
1397 static u32 au1000_get_link(struct net_device *dev)
1399 return netif_carrier_ok(dev);
1402 static struct ethtool_ops au1000_ethtool_ops = {
1403 .get_settings = au1000_get_settings,
1404 .set_settings = au1000_set_settings,
1405 .get_drvinfo = au1000_get_drvinfo,
1406 .nway_reset = au1000_nway_reset,
1407 .get_link = au1000_get_link
1410 static struct net_device * au1000_probe(int port_num)
1412 static unsigned version_printed = 0;
1413 struct au1000_private *aup = NULL;
1414 struct net_device *dev = NULL;
1415 db_dest_t *pDB, *pDBfree;
1416 char *pmac, *argptr;
1421 if (port_num >= NUM_ETH_INTERFACES)
1424 base = CPHYSADDR(iflist[port_num].base_addr );
1425 macen = CPHYSADDR(iflist[port_num].macen_addr);
1426 irq = iflist[port_num].irq;
1428 if (!request_mem_region( base, MAC_IOSIZE, "Au1x00 ENET") ||
1429 !request_mem_region(macen, 4, "Au1x00 ENET"))
1432 if (version_printed++ == 0)
1433 printk("%s version %s %s\n", DRV_NAME, DRV_VERSION, DRV_AUTHOR);
1435 dev = alloc_etherdev(sizeof(struct au1000_private));
1437 printk(KERN_ERR "%s: alloc_etherdev failed\n", DRV_NAME);
1441 if ((err = register_netdev(dev)) != 0) {
1442 printk(KERN_ERR "%s: Cannot register net device, error %d\n",
1448 printk("%s: Au1xx0 Ethernet found at 0x%x, irq %d\n",
1449 dev->name, base, irq);
1453 /* Allocate the data buffers */
1454 /* Snooping works fine with eth on all au1xxx */
1455 aup->vaddr = (u32)dma_alloc_noncoherent(NULL, MAX_BUF_SIZE *
1456 (NUM_TX_BUFFS + NUM_RX_BUFFS),
1460 release_mem_region( base, MAC_IOSIZE);
1461 release_mem_region(macen, 4);
1465 /* aup->mac is the base address of the MAC's registers */
1466 aup->mac = (volatile mac_reg_t *)iflist[port_num].base_addr;
1468 /* Setup some variables for quick register address access */
1469 aup->enable = (volatile u32 *)iflist[port_num].macen_addr;
1470 aup->mac_id = port_num;
1471 au_macs[port_num] = aup;
1473 if (port_num == 0) {
1474 /* Check the environment variables first */
1475 if (get_ethernet_addr(ethaddr) == 0)
1476 memcpy(au1000_mac_addr, ethaddr, sizeof(au1000_mac_addr));
1478 /* Check command line */
1479 argptr = prom_getcmdline();
1480 if ((pmac = strstr(argptr, "ethaddr=")) == NULL)
1481 printk(KERN_INFO "%s: No MAC address found\n",
1483 /* Use the hard coded MAC addresses */
1485 str2eaddr(ethaddr, pmac + strlen("ethaddr="));
1486 memcpy(au1000_mac_addr, ethaddr,
1487 sizeof(au1000_mac_addr));
1491 setup_hw_rings(aup, MAC0_RX_DMA_ADDR, MAC0_TX_DMA_ADDR);
1492 } else if (port_num == 1)
1493 setup_hw_rings(aup, MAC1_RX_DMA_ADDR, MAC1_TX_DMA_ADDR);
1496 * Assign to the Ethernet ports two consecutive MAC addresses
1497 * to match those that are printed on their stickers
1499 memcpy(dev->dev_addr, au1000_mac_addr, sizeof(au1000_mac_addr));
1500 dev->dev_addr[5] += port_num;
1502 /* Bring the device out of reset, otherwise probing the MII will hang */
1503 *aup->enable = MAC_EN_CLOCK_ENABLE;
1505 *aup->enable = MAC_EN_RESET0 | MAC_EN_RESET1 | MAC_EN_RESET2 |
1506 MAC_EN_CLOCK_ENABLE;
1509 aup->mii = kmalloc(sizeof(struct mii_phy), GFP_KERNEL);
1511 printk(KERN_ERR "%s: out of memory\n", dev->name);
1514 aup->mii->next = NULL;
1515 aup->mii->chip_info = NULL;
1516 aup->mii->status = 0;
1517 aup->mii->mii_control_reg = 0;
1518 aup->mii->mii_data_reg = 0;
1520 if (mii_probe(dev) != 0) {
1525 /* setup the data buffer descriptors and attach a buffer to each one */
1527 for (i = 0; i < (NUM_TX_BUFFS+NUM_RX_BUFFS); i++) {
1528 pDB->pnext = pDBfree;
1530 pDB->vaddr = (u32 *)((unsigned)aup->vaddr + MAX_BUF_SIZE*i);
1531 pDB->dma_addr = (dma_addr_t)virt_to_bus(pDB->vaddr);
1534 aup->pDBfree = pDBfree;
1536 for (i = 0; i < NUM_RX_DMA; i++) {
1537 pDB = GetFreeDB(aup);
1541 aup->rx_dma_ring[i]->buff_stat = (unsigned)pDB->dma_addr;
1542 aup->rx_db_inuse[i] = pDB;
1544 for (i = 0; i < NUM_TX_DMA; i++) {
1545 pDB = GetFreeDB(aup);
1549 aup->tx_dma_ring[i]->buff_stat = (unsigned)pDB->dma_addr;
1550 aup->tx_dma_ring[i]->len = 0;
1551 aup->tx_db_inuse[i] = pDB;
1554 spin_lock_init(&aup->lock);
1555 dev->base_addr = base;
1557 dev->open = au1000_open;
1558 dev->hard_start_xmit = au1000_tx;
1559 dev->stop = au1000_close;
1560 dev->get_stats = au1000_get_stats;
1561 dev->set_multicast_list = &set_rx_mode;
1562 dev->do_ioctl = &au1000_ioctl;
1563 SET_ETHTOOL_OPS(dev, &au1000_ethtool_ops);
1564 dev->set_config = &au1000_set_config;
1565 dev->tx_timeout = au1000_tx_timeout;
1566 dev->watchdog_timeo = ETH_TX_TIMEOUT;
1569 * The boot code uses the ethernet controller, so reset it to start
1570 * fresh. au1000_init() expects that the device is in reset state.
1577 /* here we should have a valid dev plus aup-> register addresses
1578 * so we can reset the mac properly.*/
1581 for (i = 0; i < NUM_RX_DMA; i++) {
1582 if (aup->rx_db_inuse[i])
1583 ReleaseDB(aup, aup->rx_db_inuse[i]);
1585 for (i = 0; i < NUM_TX_DMA; i++) {
1586 if (aup->tx_db_inuse[i])
1587 ReleaseDB(aup, aup->tx_db_inuse[i]);
1589 dma_free_noncoherent(NULL, MAX_BUF_SIZE * (NUM_TX_BUFFS + NUM_RX_BUFFS),
1590 (void *)aup->vaddr, aup->dma_addr);
1591 unregister_netdev(dev);
1593 release_mem_region( base, MAC_IOSIZE);
1594 release_mem_region(macen, 4);
1599 * Initialize the interface.
1601 * When the device powers up, the clocks are disabled and the
1602 * mac is in reset state. When the interface is closed, we
1603 * do the same -- reset the device and disable the clocks to
1604 * conserve power. Thus, whenever au1000_init() is called,
1605 * the device should already be in reset state.
1607 static int au1000_init(struct net_device *dev)
1609 struct au1000_private *aup = (struct au1000_private *) dev->priv;
1615 if (au1000_debug > 4)
1616 printk("%s: au1000_init\n", dev->name);
1618 spin_lock_irqsave(&aup->lock, flags);
1620 /* bring the device out of reset */
1621 *aup->enable = MAC_EN_CLOCK_ENABLE;
1623 *aup->enable = MAC_EN_RESET0 | MAC_EN_RESET1 |
1624 MAC_EN_RESET2 | MAC_EN_CLOCK_ENABLE;
1627 aup->mac->control = 0;
1628 aup->tx_head = (aup->tx_dma_ring[0]->buff_stat & 0xC) >> 2;
1629 aup->tx_tail = aup->tx_head;
1630 aup->rx_head = (aup->rx_dma_ring[0]->buff_stat & 0xC) >> 2;
1632 aup->mac->mac_addr_high = dev->dev_addr[5]<<8 | dev->dev_addr[4];
1633 aup->mac->mac_addr_low = dev->dev_addr[3]<<24 | dev->dev_addr[2]<<16 |
1634 dev->dev_addr[1]<<8 | dev->dev_addr[0];
1636 for (i = 0; i < NUM_RX_DMA; i++) {
1637 aup->rx_dma_ring[i]->buff_stat |= RX_DMA_ENABLE;
1641 aup->phy_ops->phy_status(dev, aup->phy_addr, &link, &speed);
1642 control = MAC_DISABLE_RX_OWN | MAC_RX_ENABLE | MAC_TX_ENABLE;
1643 #ifndef CONFIG_CPU_LITTLE_ENDIAN
1644 control |= MAC_BIG_ENDIAN;
1646 if (link && (dev->if_port == IF_PORT_100BASEFX)) {
1647 control |= MAC_FULL_DUPLEX;
1650 aup->mac->control = control;
1651 aup->mac->vlan1_tag = 0x8100; /* activate vlan support */
1654 spin_unlock_irqrestore(&aup->lock, flags);
1658 static void au1000_timer(unsigned long data)
1660 struct net_device *dev = (struct net_device *)data;
1661 struct au1000_private *aup = (struct au1000_private *) dev->priv;
1662 unsigned char if_port;
1666 /* fatal error, don't restart the timer */
1667 printk(KERN_ERR "au1000_timer error: NULL dev\n");
1671 if_port = dev->if_port;
1672 if (aup->phy_ops->phy_status(dev, aup->phy_addr, &link, &speed) == 0) {
1674 if (!netif_carrier_ok(dev)) {
1675 netif_carrier_on(dev);
1676 printk(KERN_INFO "%s: link up\n", dev->name);
1680 if (netif_carrier_ok(dev)) {
1681 netif_carrier_off(dev);
1683 printk(KERN_INFO "%s: link down\n", dev->name);
1688 if (link && (dev->if_port != if_port) &&
1689 (dev->if_port != IF_PORT_UNKNOWN)) {
1691 if (dev->if_port == IF_PORT_100BASEFX) {
1692 printk(KERN_INFO "%s: going to full duplex\n",
1694 aup->mac->control |= MAC_FULL_DUPLEX;
1698 aup->mac->control &= ~MAC_FULL_DUPLEX;
1704 aup->timer.expires = RUN_AT((1*HZ));
1705 aup->timer.data = (unsigned long)dev;
1706 aup->timer.function = &au1000_timer; /* timer handler */
1707 add_timer(&aup->timer);
1711 static int au1000_open(struct net_device *dev)
1714 struct au1000_private *aup = (struct au1000_private *) dev->priv;
1716 if (au1000_debug > 4)
1717 printk("%s: open: dev=%p\n", dev->name, dev);
1719 if ((retval = au1000_init(dev))) {
1720 printk(KERN_ERR "%s: error in au1000_init\n", dev->name);
1721 free_irq(dev->irq, dev);
1724 netif_start_queue(dev);
1726 if ((retval = request_irq(dev->irq, &au1000_interrupt, 0,
1728 printk(KERN_ERR "%s: unable to get IRQ %d\n",
1729 dev->name, dev->irq);
1733 init_timer(&aup->timer); /* used in ioctl() */
1734 aup->timer.expires = RUN_AT((3*HZ));
1735 aup->timer.data = (unsigned long)dev;
1736 aup->timer.function = &au1000_timer; /* timer handler */
1737 add_timer(&aup->timer);
1739 if (au1000_debug > 4)
1740 printk("%s: open: Initialization done.\n", dev->name);
1745 static int au1000_close(struct net_device *dev)
1748 struct au1000_private *aup = (struct au1000_private *) dev->priv;
1750 if (au1000_debug > 4)
1751 printk("%s: close: dev=%p\n", dev->name, dev);
1755 spin_lock_irqsave(&aup->lock, flags);
1757 /* stop the device */
1758 netif_stop_queue(dev);
1760 /* disable the interrupt */
1761 free_irq(dev->irq, dev);
1762 spin_unlock_irqrestore(&aup->lock, flags);
1767 static void __exit au1000_cleanup_module(void)
1770 struct net_device *dev;
1771 struct au1000_private *aup;
1773 for (i = 0; i < num_ifs; i++) {
1774 dev = iflist[i].dev;
1776 aup = (struct au1000_private *) dev->priv;
1777 unregister_netdev(dev);
1779 for (j = 0; j < NUM_RX_DMA; j++)
1780 if (aup->rx_db_inuse[j])
1781 ReleaseDB(aup, aup->rx_db_inuse[j]);
1782 for (j = 0; j < NUM_TX_DMA; j++)
1783 if (aup->tx_db_inuse[j])
1784 ReleaseDB(aup, aup->tx_db_inuse[j]);
1785 dma_free_noncoherent(NULL, MAX_BUF_SIZE *
1786 (NUM_TX_BUFFS + NUM_RX_BUFFS),
1787 (void *)aup->vaddr, aup->dma_addr);
1788 release_mem_region(dev->base_addr, MAC_IOSIZE);
1789 release_mem_region(CPHYSADDR(iflist[i].macen_addr), 4);
1795 static void update_tx_stats(struct net_device *dev, u32 status)
1797 struct au1000_private *aup = (struct au1000_private *) dev->priv;
1798 struct net_device_stats *ps = &aup->stats;
1800 if (status & TX_FRAME_ABORTED) {
1801 if (dev->if_port == IF_PORT_100BASEFX) {
1802 if (status & (TX_JAB_TIMEOUT | TX_UNDERRUN)) {
1803 /* any other tx errors are only valid
1804 * in half duplex mode */
1806 ps->tx_aborted_errors++;
1811 ps->tx_aborted_errors++;
1812 if (status & (TX_NO_CARRIER | TX_LOSS_CARRIER))
1813 ps->tx_carrier_errors++;
1820 * Called from the interrupt service routine to acknowledge
1821 * the TX DONE bits. This is a must if the irq is setup as
1824 static void au1000_tx_ack(struct net_device *dev)
1826 struct au1000_private *aup = (struct au1000_private *) dev->priv;
1827 volatile tx_dma_t *ptxd;
1829 ptxd = aup->tx_dma_ring[aup->tx_tail];
1831 while (ptxd->buff_stat & TX_T_DONE) {
1832 update_tx_stats(dev, ptxd->status);
1833 ptxd->buff_stat &= ~TX_T_DONE;
1837 aup->tx_tail = (aup->tx_tail + 1) & (NUM_TX_DMA - 1);
1838 ptxd = aup->tx_dma_ring[aup->tx_tail];
1842 netif_wake_queue(dev);
1849 * Au1000 transmit routine.
1851 static int au1000_tx(struct sk_buff *skb, struct net_device *dev)
1853 struct au1000_private *aup = (struct au1000_private *) dev->priv;
1854 struct net_device_stats *ps = &aup->stats;
1855 volatile tx_dma_t *ptxd;
1860 if (au1000_debug > 5)
1861 printk("%s: tx: aup %x len=%d, data=%p, head %d\n",
1862 dev->name, (unsigned)aup, skb->len,
1863 skb->data, aup->tx_head);
1865 ptxd = aup->tx_dma_ring[aup->tx_head];
1866 buff_stat = ptxd->buff_stat;
1867 if (buff_stat & TX_DMA_ENABLE) {
1868 /* We've wrapped around and the transmitter is still busy */
1869 netif_stop_queue(dev);
1873 else if (buff_stat & TX_T_DONE) {
1874 update_tx_stats(dev, ptxd->status);
1880 netif_wake_queue(dev);
1883 pDB = aup->tx_db_inuse[aup->tx_head];
1884 memcpy((void *)pDB->vaddr, skb->data, skb->len);
1885 if (skb->len < ETH_ZLEN) {
1886 for (i=skb->len; i<ETH_ZLEN; i++) {
1887 ((char *)pDB->vaddr)[i] = 0;
1889 ptxd->len = ETH_ZLEN;
1892 ptxd->len = skb->len;
1895 ps->tx_bytes += ptxd->len;
1897 ptxd->buff_stat = pDB->dma_addr | TX_DMA_ENABLE;
1900 aup->tx_head = (aup->tx_head + 1) & (NUM_TX_DMA - 1);
1901 dev->trans_start = jiffies;
1905 static inline void update_rx_stats(struct net_device *dev, u32 status)
1907 struct au1000_private *aup = (struct au1000_private *) dev->priv;
1908 struct net_device_stats *ps = &aup->stats;
1911 if (status & RX_MCAST_FRAME)
1914 if (status & RX_ERROR) {
1916 if (status & RX_MISSED_FRAME)
1917 ps->rx_missed_errors++;
1918 if (status & (RX_OVERLEN | RX_OVERLEN | RX_LEN_ERROR))
1919 ps->rx_length_errors++;
1920 if (status & RX_CRC_ERROR)
1921 ps->rx_crc_errors++;
1922 if (status & RX_COLL)
1926 ps->rx_bytes += status & RX_FRAME_LEN_MASK;
1931 * Au1000 receive routine.
1933 static int au1000_rx(struct net_device *dev)
1935 struct au1000_private *aup = (struct au1000_private *) dev->priv;
1936 struct sk_buff *skb;
1937 volatile rx_dma_t *prxd;
1938 u32 buff_stat, status;
1942 if (au1000_debug > 5)
1943 printk("%s: au1000_rx head %d\n", dev->name, aup->rx_head);
1945 prxd = aup->rx_dma_ring[aup->rx_head];
1946 buff_stat = prxd->buff_stat;
1947 while (buff_stat & RX_T_DONE) {
1948 status = prxd->status;
1949 pDB = aup->rx_db_inuse[aup->rx_head];
1950 update_rx_stats(dev, status);
1951 if (!(status & RX_ERROR)) {
1954 frmlen = (status & RX_FRAME_LEN_MASK);
1955 frmlen -= 4; /* Remove FCS */
1956 skb = dev_alloc_skb(frmlen + 2);
1959 "%s: Memory squeeze, dropping packet.\n",
1961 aup->stats.rx_dropped++;
1965 skb_reserve(skb, 2); /* 16 byte IP header align */
1966 eth_copy_and_sum(skb,
1967 (unsigned char *)pDB->vaddr, frmlen, 0);
1968 skb_put(skb, frmlen);
1969 skb->protocol = eth_type_trans(skb, dev);
1970 netif_rx(skb); /* pass the packet to upper layers */
1973 if (au1000_debug > 4) {
1974 if (status & RX_MISSED_FRAME)
1975 printk("rx miss\n");
1976 if (status & RX_WDOG_TIMER)
1977 printk("rx wdog\n");
1978 if (status & RX_RUNT)
1979 printk("rx runt\n");
1980 if (status & RX_OVERLEN)
1981 printk("rx overlen\n");
1982 if (status & RX_COLL)
1983 printk("rx coll\n");
1984 if (status & RX_MII_ERROR)
1985 printk("rx mii error\n");
1986 if (status & RX_CRC_ERROR)
1987 printk("rx crc error\n");
1988 if (status & RX_LEN_ERROR)
1989 printk("rx len error\n");
1990 if (status & RX_U_CNTRL_FRAME)
1991 printk("rx u control frame\n");
1992 if (status & RX_MISSED_FRAME)
1993 printk("rx miss\n");
1996 prxd->buff_stat = (u32)(pDB->dma_addr | RX_DMA_ENABLE);
1997 aup->rx_head = (aup->rx_head + 1) & (NUM_RX_DMA - 1);
2000 /* next descriptor */
2001 prxd = aup->rx_dma_ring[aup->rx_head];
2002 buff_stat = prxd->buff_stat;
2003 dev->last_rx = jiffies;
2010 * Au1000 interrupt service routine.
2012 static irqreturn_t au1000_interrupt(int irq, void *dev_id, struct pt_regs *regs)
2014 struct net_device *dev = (struct net_device *) dev_id;
2017 printk(KERN_ERR "%s: isr: null dev ptr\n", dev->name);
2018 return IRQ_RETVAL(1);
2021 /* Handle RX interrupts first to minimize chance of overrun */
2025 return IRQ_RETVAL(1);
2030 * The Tx ring has been full longer than the watchdog timeout
2031 * value. The transmitter must be hung?
2033 static void au1000_tx_timeout(struct net_device *dev)
2035 printk(KERN_ERR "%s: au1000_tx_timeout: dev=%p\n", dev->name, dev);
2038 dev->trans_start = jiffies;
2039 netif_wake_queue(dev);
2042 static void set_rx_mode(struct net_device *dev)
2044 struct au1000_private *aup = (struct au1000_private *) dev->priv;
2046 if (au1000_debug > 4)
2047 printk("%s: set_rx_mode: flags=%x\n", dev->name, dev->flags);
2049 if (dev->flags & IFF_PROMISC) { /* Set promiscuous. */
2050 aup->mac->control |= MAC_PROMISCUOUS;
2051 printk(KERN_INFO "%s: Promiscuous mode enabled.\n", dev->name);
2052 } else if ((dev->flags & IFF_ALLMULTI) ||
2053 dev->mc_count > MULTICAST_FILTER_LIMIT) {
2054 aup->mac->control |= MAC_PASS_ALL_MULTI;
2055 aup->mac->control &= ~MAC_PROMISCUOUS;
2056 printk(KERN_INFO "%s: Pass all multicast\n", dev->name);
2059 struct dev_mc_list *mclist;
2060 u32 mc_filter[2]; /* Multicast hash filter */
2062 mc_filter[1] = mc_filter[0] = 0;
2063 for (i = 0, mclist = dev->mc_list; mclist && i < dev->mc_count;
2064 i++, mclist = mclist->next) {
2065 set_bit(ether_crc(ETH_ALEN, mclist->dmi_addr)>>26,
2068 aup->mac->multi_hash_high = mc_filter[1];
2069 aup->mac->multi_hash_low = mc_filter[0];
2070 aup->mac->control &= ~MAC_PROMISCUOUS;
2071 aup->mac->control |= MAC_HASH_MODE;
2076 static int au1000_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
2078 struct au1000_private *aup = (struct au1000_private *)dev->priv;
2079 u16 *data = (u16 *)&rq->ifr_ifru;
2082 case SIOCDEVPRIVATE: /* Get the address of the PHY in use. */
2084 if (!netif_running(dev)) return -EINVAL;
2085 data[0] = aup->phy_addr;
2086 case SIOCDEVPRIVATE+1: /* Read the specified MII register. */
2088 data[3] = mdio_read(dev, data[0], data[1]);
2090 case SIOCDEVPRIVATE+2: /* Write the specified MII register */
2092 if (!capable(CAP_NET_ADMIN))
2094 mdio_write(dev, data[0], data[1],data[2]);
2103 static int au1000_set_config(struct net_device *dev, struct ifmap *map)
2105 struct au1000_private *aup = (struct au1000_private *) dev->priv;
2108 if (au1000_debug > 4) {
2109 printk("%s: set_config called: dev->if_port %d map->port %x\n",
2110 dev->name, dev->if_port, map->port);
2114 case IF_PORT_UNKNOWN: /* use auto here */
2115 printk(KERN_INFO "%s: config phy for aneg\n",
2117 dev->if_port = map->port;
2118 /* Link Down: the timer will bring it up */
2119 netif_carrier_off(dev);
2121 /* read current control */
2122 control = mdio_read(dev, aup->phy_addr, MII_CONTROL);
2123 control &= ~(MII_CNTL_FDX | MII_CNTL_F100);
2125 /* enable auto negotiation and reset the negotiation */
2126 mdio_write(dev, aup->phy_addr, MII_CONTROL,
2127 control | MII_CNTL_AUTO |
2132 case IF_PORT_10BASET: /* 10BaseT */
2133 printk(KERN_INFO "%s: config phy for 10BaseT\n",
2135 dev->if_port = map->port;
2137 /* Link Down: the timer will bring it up */
2138 netif_carrier_off(dev);
2140 /* set Speed to 10Mbps, Half Duplex */
2141 control = mdio_read(dev, aup->phy_addr, MII_CONTROL);
2142 control &= ~(MII_CNTL_F100 | MII_CNTL_AUTO |
2145 /* disable auto negotiation and force 10M/HD mode*/
2146 mdio_write(dev, aup->phy_addr, MII_CONTROL, control);
2149 case IF_PORT_100BASET: /* 100BaseT */
2150 case IF_PORT_100BASETX: /* 100BaseTx */
2151 printk(KERN_INFO "%s: config phy for 100BaseTX\n",
2153 dev->if_port = map->port;
2155 /* Link Down: the timer will bring it up */
2156 netif_carrier_off(dev);
2158 /* set Speed to 100Mbps, Half Duplex */
2159 /* disable auto negotiation and enable 100MBit Mode */
2160 control = mdio_read(dev, aup->phy_addr, MII_CONTROL);
2161 control &= ~(MII_CNTL_AUTO | MII_CNTL_FDX);
2162 control |= MII_CNTL_F100;
2163 mdio_write(dev, aup->phy_addr, MII_CONTROL, control);
2166 case IF_PORT_100BASEFX: /* 100BaseFx */
2167 printk(KERN_INFO "%s: config phy for 100BaseFX\n",
2169 dev->if_port = map->port;
2171 /* Link Down: the timer will bring it up */
2172 netif_carrier_off(dev);
2174 /* set Speed to 100Mbps, Full Duplex */
2175 /* disable auto negotiation and enable 100MBit Mode */
2176 control = mdio_read(dev, aup->phy_addr, MII_CONTROL);
2177 control &= ~MII_CNTL_AUTO;
2178 control |= MII_CNTL_F100 | MII_CNTL_FDX;
2179 mdio_write(dev, aup->phy_addr, MII_CONTROL, control);
2181 case IF_PORT_10BASE2: /* 10Base2 */
2182 case IF_PORT_AUI: /* AUI */
2183 /* These Modes are not supported (are they?)*/
2184 printk(KERN_ERR "%s: 10Base2/AUI not supported",
2190 printk(KERN_ERR "%s: Invalid media selected",
2197 static struct net_device_stats *au1000_get_stats(struct net_device *dev)
2199 struct au1000_private *aup = (struct au1000_private *) dev->priv;
2201 if (au1000_debug > 4)
2202 printk("%s: au1000_get_stats: dev=%p\n", dev->name, dev);
2204 if (netif_device_present(dev)) {
2210 module_init(au1000_init_module);
2211 module_exit(au1000_cleanup_module);