3 * Alchemy Au1x00 ethernet driver
5 * Copyright 2001-2003, 2006 MontaVista Software Inc.
6 * Copyright 2002 TimeSys Corp.
7 * Added ethtool/mii-tool support,
8 * Copyright 2004 Matt Porter <mporter@kernel.crashing.org>
9 * Update: 2004 Bjoern Riemer, riemer@fokus.fraunhofer.de
10 * or riemer@riemer-nt.de: fixed the link beat detection with
11 * ioctls (SIOCGMIIPHY)
12 * Author: MontaVista Software, Inc.
13 * ppopov@mvista.com or source@mvista.com
15 * ########################################################################
17 * This program is free software; you can distribute it and/or modify it
18 * under the terms of the GNU General Public License (Version 2) as
19 * published by the Free Software Foundation.
21 * This program is distributed in the hope it will be useful, but WITHOUT
22 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
23 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
26 * You should have received a copy of the GNU General Public License along
27 * with this program; if not, write to the Free Software Foundation, Inc.,
28 * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
30 * ########################################################################
35 #include <linux/config.h>
36 #include <linux/module.h>
37 #include <linux/kernel.h>
38 #include <linux/sched.h>
39 #include <linux/string.h>
40 #include <linux/timer.h>
41 #include <linux/errno.h>
43 #include <linux/ioport.h>
44 #include <linux/bitops.h>
45 #include <linux/slab.h>
46 #include <linux/interrupt.h>
47 #include <linux/pci.h>
48 #include <linux/init.h>
49 #include <linux/netdevice.h>
50 #include <linux/etherdevice.h>
51 #include <linux/ethtool.h>
52 #include <linux/mii.h>
53 #include <linux/skbuff.h>
54 #include <linux/delay.h>
55 #include <asm/mipsregs.h>
58 #include <asm/processor.h>
60 #include <asm/mach-au1x00/au1000.h>
62 #include "au1000_eth.h"
64 #ifdef AU1000_ETH_DEBUG
65 static int au1000_debug = 5;
67 static int au1000_debug = 3;
70 #define DRV_NAME "au1000_eth"
71 #define DRV_VERSION "1.5"
72 #define DRV_AUTHOR "Pete Popov <ppopov@embeddedalley.com>"
73 #define DRV_DESC "Au1xxx on-chip Ethernet driver"
75 MODULE_AUTHOR(DRV_AUTHOR);
76 MODULE_DESCRIPTION(DRV_DESC);
77 MODULE_LICENSE("GPL");
80 static void hard_stop(struct net_device *);
81 static void enable_rx_tx(struct net_device *dev);
82 static struct net_device * au1000_probe(int port_num);
83 static int au1000_init(struct net_device *);
84 static int au1000_open(struct net_device *);
85 static int au1000_close(struct net_device *);
86 static int au1000_tx(struct sk_buff *, struct net_device *);
87 static int au1000_rx(struct net_device *);
88 static irqreturn_t au1000_interrupt(int, void *, struct pt_regs *);
89 static void au1000_tx_timeout(struct net_device *);
90 static int au1000_set_config(struct net_device *dev, struct ifmap *map);
91 static void set_rx_mode(struct net_device *);
92 static struct net_device_stats *au1000_get_stats(struct net_device *);
93 static void au1000_timer(unsigned long);
94 static int au1000_ioctl(struct net_device *, struct ifreq *, int);
95 static int mdio_read(struct net_device *, int, int);
96 static void mdio_write(struct net_device *, int, int, u16);
97 static void dump_mii(struct net_device *dev, int phy_id);
100 extern void ack_rise_edge_irq(unsigned int);
101 extern int get_ethernet_addr(char *ethernet_addr);
102 extern void str2eaddr(unsigned char *ea, unsigned char *str);
103 extern char * __init prom_getcmdline(void);
106 * Theory of operation
108 * The Au1000 MACs use a simple rx and tx descriptor ring scheme.
109 * There are four receive and four transmit descriptors. These
110 * descriptors are not in memory; rather, they are just a set of
111 * hardware registers.
113 * Since the Au1000 has a coherent data cache, the receive and
114 * transmit buffers are allocated from the KSEG0 segment. The
115 * hardware registers, however, are still mapped at KSEG1 to
116 * make sure there's no out-of-order writes, and that all writes
117 * complete immediately.
120 /* These addresses are only used if yamon doesn't tell us what
121 * the mac address is, and the mac address is not passed on the
124 static unsigned char au1000_mac_addr[6] __devinitdata = {
125 0x00, 0x50, 0xc2, 0x0c, 0x30, 0x00
128 #define nibswap(x) ((((x) >> 4) & 0x0f) | (((x) << 4) & 0xf0))
129 #define RUN_AT(x) (jiffies + (x))
131 // For reading/writing 32-bit words from/to DMA memory
132 #define cpu_to_dma32 cpu_to_be32
133 #define dma32_to_cpu be32_to_cpu
135 struct au1000_private *au_macs[NUM_ETH_INTERFACES];
138 * All of the PHY code really should be detached from the MAC
142 /* Default advertise */
143 #define GENMII_DEFAULT_ADVERTISE \
144 ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full | \
145 ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full | \
148 #define GENMII_DEFAULT_FEATURES \
149 SUPPORTED_10baseT_Half | SUPPORTED_10baseT_Full | \
150 SUPPORTED_100baseT_Half | SUPPORTED_100baseT_Full | \
153 int bcm_5201_init(struct net_device *dev, int phy_addr)
157 /* Stop auto-negotiation */
158 data = mdio_read(dev, phy_addr, MII_CONTROL);
159 mdio_write(dev, phy_addr, MII_CONTROL, data & ~MII_CNTL_AUTO);
161 /* Set advertisement to 10/100 and Half/Full duplex
162 * (full capabilities) */
163 data = mdio_read(dev, phy_addr, MII_ANADV);
164 data |= MII_NWAY_TX | MII_NWAY_TX_FDX | MII_NWAY_T_FDX | MII_NWAY_T;
165 mdio_write(dev, phy_addr, MII_ANADV, data);
167 /* Restart auto-negotiation */
168 data = mdio_read(dev, phy_addr, MII_CONTROL);
169 data |= MII_CNTL_RST_AUTO | MII_CNTL_AUTO;
170 mdio_write(dev, phy_addr, MII_CONTROL, data);
172 if (au1000_debug > 4)
173 dump_mii(dev, phy_addr);
177 int bcm_5201_reset(struct net_device *dev, int phy_addr)
179 s16 mii_control, timeout;
181 mii_control = mdio_read(dev, phy_addr, MII_CONTROL);
182 mdio_write(dev, phy_addr, MII_CONTROL, mii_control | MII_CNTL_RESET);
184 for (timeout = 100; timeout > 0; --timeout) {
185 mii_control = mdio_read(dev, phy_addr, MII_CONTROL);
186 if ((mii_control & MII_CNTL_RESET) == 0)
190 if (mii_control & MII_CNTL_RESET) {
191 printk(KERN_ERR "%s PHY reset timeout !\n", dev->name);
198 bcm_5201_status(struct net_device *dev, int phy_addr, u16 *link, u16 *speed)
201 struct au1000_private *aup;
204 printk(KERN_ERR "bcm_5201_status error: NULL dev\n");
207 aup = (struct au1000_private *) dev->priv;
209 mii_data = mdio_read(dev, aup->phy_addr, MII_STATUS);
210 if (mii_data & MII_STAT_LINK) {
212 mii_data = mdio_read(dev, aup->phy_addr, MII_AUX_CNTRL);
213 if (mii_data & MII_AUX_100) {
214 if (mii_data & MII_AUX_FDX) {
215 *speed = IF_PORT_100BASEFX;
216 dev->if_port = IF_PORT_100BASEFX;
219 *speed = IF_PORT_100BASETX;
220 dev->if_port = IF_PORT_100BASETX;
224 *speed = IF_PORT_10BASET;
225 dev->if_port = IF_PORT_10BASET;
232 dev->if_port = IF_PORT_UNKNOWN;
237 int lsi_80227_init(struct net_device *dev, int phy_addr)
239 if (au1000_debug > 4)
240 printk("lsi_80227_init\n");
242 /* restart auto-negotiation */
243 mdio_write(dev, phy_addr, MII_CONTROL,
244 MII_CNTL_F100 | MII_CNTL_AUTO | MII_CNTL_RST_AUTO); // | MII_CNTL_FDX);
247 /* set up LEDs to correct display */
248 #ifdef CONFIG_MIPS_MTX1
249 mdio_write(dev, phy_addr, 17, 0xff80);
251 mdio_write(dev, phy_addr, 17, 0xffc0);
254 if (au1000_debug > 4)
255 dump_mii(dev, phy_addr);
259 int lsi_80227_reset(struct net_device *dev, int phy_addr)
261 s16 mii_control, timeout;
263 if (au1000_debug > 4) {
264 printk("lsi_80227_reset\n");
265 dump_mii(dev, phy_addr);
268 mii_control = mdio_read(dev, phy_addr, MII_CONTROL);
269 mdio_write(dev, phy_addr, MII_CONTROL, mii_control | MII_CNTL_RESET);
271 for (timeout = 100; timeout > 0; --timeout) {
272 mii_control = mdio_read(dev, phy_addr, MII_CONTROL);
273 if ((mii_control & MII_CNTL_RESET) == 0)
277 if (mii_control & MII_CNTL_RESET) {
278 printk(KERN_ERR "%s PHY reset timeout !\n", dev->name);
285 lsi_80227_status(struct net_device *dev, int phy_addr, u16 *link, u16 *speed)
288 struct au1000_private *aup;
291 printk(KERN_ERR "lsi_80227_status error: NULL dev\n");
294 aup = (struct au1000_private *) dev->priv;
296 mii_data = mdio_read(dev, aup->phy_addr, MII_STATUS);
297 if (mii_data & MII_STAT_LINK) {
299 mii_data = mdio_read(dev, aup->phy_addr, MII_LSI_PHY_STAT);
300 if (mii_data & MII_LSI_PHY_STAT_SPD) {
301 if (mii_data & MII_LSI_PHY_STAT_FDX) {
302 *speed = IF_PORT_100BASEFX;
303 dev->if_port = IF_PORT_100BASEFX;
306 *speed = IF_PORT_100BASETX;
307 dev->if_port = IF_PORT_100BASETX;
311 *speed = IF_PORT_10BASET;
312 dev->if_port = IF_PORT_10BASET;
319 dev->if_port = IF_PORT_UNKNOWN;
324 int am79c901_init(struct net_device *dev, int phy_addr)
326 printk("am79c901_init\n");
330 int am79c901_reset(struct net_device *dev, int phy_addr)
332 printk("am79c901_reset\n");
337 am79c901_status(struct net_device *dev, int phy_addr, u16 *link, u16 *speed)
342 int am79c874_init(struct net_device *dev, int phy_addr)
346 /* 79c874 has quit resembled bit assignments to BCM5201 */
347 if (au1000_debug > 4)
348 printk("am79c847_init\n");
350 /* Stop auto-negotiation */
351 data = mdio_read(dev, phy_addr, MII_CONTROL);
352 mdio_write(dev, phy_addr, MII_CONTROL, data & ~MII_CNTL_AUTO);
354 /* Set advertisement to 10/100 and Half/Full duplex
355 * (full capabilities) */
356 data = mdio_read(dev, phy_addr, MII_ANADV);
357 data |= MII_NWAY_TX | MII_NWAY_TX_FDX | MII_NWAY_T_FDX | MII_NWAY_T;
358 mdio_write(dev, phy_addr, MII_ANADV, data);
360 /* Restart auto-negotiation */
361 data = mdio_read(dev, phy_addr, MII_CONTROL);
362 data |= MII_CNTL_RST_AUTO | MII_CNTL_AUTO;
364 mdio_write(dev, phy_addr, MII_CONTROL, data);
366 if (au1000_debug > 4) dump_mii(dev, phy_addr);
370 int am79c874_reset(struct net_device *dev, int phy_addr)
372 s16 mii_control, timeout;
374 if (au1000_debug > 4)
375 printk("am79c874_reset\n");
377 mii_control = mdio_read(dev, phy_addr, MII_CONTROL);
378 mdio_write(dev, phy_addr, MII_CONTROL, mii_control | MII_CNTL_RESET);
380 for (timeout = 100; timeout > 0; --timeout) {
381 mii_control = mdio_read(dev, phy_addr, MII_CONTROL);
382 if ((mii_control & MII_CNTL_RESET) == 0)
386 if (mii_control & MII_CNTL_RESET) {
387 printk(KERN_ERR "%s PHY reset timeout !\n", dev->name);
394 am79c874_status(struct net_device *dev, int phy_addr, u16 *link, u16 *speed)
397 struct au1000_private *aup;
399 // printk("am79c874_status\n");
401 printk(KERN_ERR "am79c874_status error: NULL dev\n");
405 aup = (struct au1000_private *) dev->priv;
406 mii_data = mdio_read(dev, aup->phy_addr, MII_STATUS);
408 if (mii_data & MII_STAT_LINK) {
410 mii_data = mdio_read(dev, aup->phy_addr, MII_AMD_PHY_STAT);
411 if (mii_data & MII_AMD_PHY_STAT_SPD) {
412 if (mii_data & MII_AMD_PHY_STAT_FDX) {
413 *speed = IF_PORT_100BASEFX;
414 dev->if_port = IF_PORT_100BASEFX;
417 *speed = IF_PORT_100BASETX;
418 dev->if_port = IF_PORT_100BASETX;
422 *speed = IF_PORT_10BASET;
423 dev->if_port = IF_PORT_10BASET;
430 dev->if_port = IF_PORT_UNKNOWN;
435 int lxt971a_init(struct net_device *dev, int phy_addr)
437 if (au1000_debug > 4)
438 printk("lxt971a_init\n");
440 /* restart auto-negotiation */
441 mdio_write(dev, phy_addr, MII_CONTROL,
442 MII_CNTL_F100 | MII_CNTL_AUTO | MII_CNTL_RST_AUTO | MII_CNTL_FDX);
444 /* set up LEDs to correct display */
445 mdio_write(dev, phy_addr, 20, 0x0422);
447 if (au1000_debug > 4)
448 dump_mii(dev, phy_addr);
452 int lxt971a_reset(struct net_device *dev, int phy_addr)
454 s16 mii_control, timeout;
456 if (au1000_debug > 4) {
457 printk("lxt971a_reset\n");
458 dump_mii(dev, phy_addr);
461 mii_control = mdio_read(dev, phy_addr, MII_CONTROL);
462 mdio_write(dev, phy_addr, MII_CONTROL, mii_control | MII_CNTL_RESET);
464 for (timeout = 100; timeout > 0; --timeout) {
465 mii_control = mdio_read(dev, phy_addr, MII_CONTROL);
466 if ((mii_control & MII_CNTL_RESET) == 0)
470 if (mii_control & MII_CNTL_RESET) {
471 printk(KERN_ERR "%s PHY reset timeout !\n", dev->name);
478 lxt971a_status(struct net_device *dev, int phy_addr, u16 *link, u16 *speed)
481 struct au1000_private *aup;
484 printk(KERN_ERR "lxt971a_status error: NULL dev\n");
487 aup = (struct au1000_private *) dev->priv;
489 mii_data = mdio_read(dev, aup->phy_addr, MII_STATUS);
490 if (mii_data & MII_STAT_LINK) {
492 mii_data = mdio_read(dev, aup->phy_addr, MII_INTEL_PHY_STAT);
493 if (mii_data & MII_INTEL_PHY_STAT_SPD) {
494 if (mii_data & MII_INTEL_PHY_STAT_FDX) {
495 *speed = IF_PORT_100BASEFX;
496 dev->if_port = IF_PORT_100BASEFX;
499 *speed = IF_PORT_100BASETX;
500 dev->if_port = IF_PORT_100BASETX;
504 *speed = IF_PORT_10BASET;
505 dev->if_port = IF_PORT_10BASET;
512 dev->if_port = IF_PORT_UNKNOWN;
517 int ks8995m_init(struct net_device *dev, int phy_addr)
521 // printk("ks8995m_init\n");
522 /* Stop auto-negotiation */
523 data = mdio_read(dev, phy_addr, MII_CONTROL);
524 mdio_write(dev, phy_addr, MII_CONTROL, data & ~MII_CNTL_AUTO);
526 /* Set advertisement to 10/100 and Half/Full duplex
527 * (full capabilities) */
528 data = mdio_read(dev, phy_addr, MII_ANADV);
529 data |= MII_NWAY_TX | MII_NWAY_TX_FDX | MII_NWAY_T_FDX | MII_NWAY_T;
530 mdio_write(dev, phy_addr, MII_ANADV, data);
532 /* Restart auto-negotiation */
533 data = mdio_read(dev, phy_addr, MII_CONTROL);
534 data |= MII_CNTL_RST_AUTO | MII_CNTL_AUTO;
535 mdio_write(dev, phy_addr, MII_CONTROL, data);
537 if (au1000_debug > 4) dump_mii(dev, phy_addr);
542 int ks8995m_reset(struct net_device *dev, int phy_addr)
544 s16 mii_control, timeout;
546 // printk("ks8995m_reset\n");
547 mii_control = mdio_read(dev, phy_addr, MII_CONTROL);
548 mdio_write(dev, phy_addr, MII_CONTROL, mii_control | MII_CNTL_RESET);
550 for (timeout = 100; timeout > 0; --timeout) {
551 mii_control = mdio_read(dev, phy_addr, MII_CONTROL);
552 if ((mii_control & MII_CNTL_RESET) == 0)
556 if (mii_control & MII_CNTL_RESET) {
557 printk(KERN_ERR "%s PHY reset timeout !\n", dev->name);
563 int ks8995m_status(struct net_device *dev, int phy_addr, u16 *link, u16 *speed)
566 struct au1000_private *aup;
569 printk(KERN_ERR "ks8995m_status error: NULL dev\n");
572 aup = (struct au1000_private *) dev->priv;
574 mii_data = mdio_read(dev, aup->phy_addr, MII_STATUS);
575 if (mii_data & MII_STAT_LINK) {
577 mii_data = mdio_read(dev, aup->phy_addr, MII_AUX_CNTRL);
578 if (mii_data & MII_AUX_100) {
579 if (mii_data & MII_AUX_FDX) {
580 *speed = IF_PORT_100BASEFX;
581 dev->if_port = IF_PORT_100BASEFX;
584 *speed = IF_PORT_100BASETX;
585 dev->if_port = IF_PORT_100BASETX;
589 *speed = IF_PORT_10BASET;
590 dev->if_port = IF_PORT_10BASET;
597 dev->if_port = IF_PORT_UNKNOWN;
603 smsc_83C185_init (struct net_device *dev, int phy_addr)
607 if (au1000_debug > 4)
608 printk("smsc_83C185_init\n");
610 /* Stop auto-negotiation */
611 data = mdio_read(dev, phy_addr, MII_CONTROL);
612 mdio_write(dev, phy_addr, MII_CONTROL, data & ~MII_CNTL_AUTO);
614 /* Set advertisement to 10/100 and Half/Full duplex
615 * (full capabilities) */
616 data = mdio_read(dev, phy_addr, MII_ANADV);
617 data |= MII_NWAY_TX | MII_NWAY_TX_FDX | MII_NWAY_T_FDX | MII_NWAY_T;
618 mdio_write(dev, phy_addr, MII_ANADV, data);
620 /* Restart auto-negotiation */
621 data = mdio_read(dev, phy_addr, MII_CONTROL);
622 data |= MII_CNTL_RST_AUTO | MII_CNTL_AUTO;
624 mdio_write(dev, phy_addr, MII_CONTROL, data);
626 if (au1000_debug > 4) dump_mii(dev, phy_addr);
631 smsc_83C185_reset (struct net_device *dev, int phy_addr)
633 s16 mii_control, timeout;
635 if (au1000_debug > 4)
636 printk("smsc_83C185_reset\n");
638 mii_control = mdio_read(dev, phy_addr, MII_CONTROL);
639 mdio_write(dev, phy_addr, MII_CONTROL, mii_control | MII_CNTL_RESET);
641 for (timeout = 100; timeout > 0; --timeout) {
642 mii_control = mdio_read(dev, phy_addr, MII_CONTROL);
643 if ((mii_control & MII_CNTL_RESET) == 0)
647 if (mii_control & MII_CNTL_RESET) {
648 printk(KERN_ERR "%s PHY reset timeout !\n", dev->name);
655 smsc_83C185_status (struct net_device *dev, int phy_addr, u16 *link, u16 *speed)
658 struct au1000_private *aup;
661 printk(KERN_ERR "smsc_83C185_status error: NULL dev\n");
665 aup = (struct au1000_private *) dev->priv;
666 mii_data = mdio_read(dev, aup->phy_addr, MII_STATUS);
668 if (mii_data & MII_STAT_LINK) {
670 mii_data = mdio_read(dev, aup->phy_addr, 0x1f);
671 if (mii_data & (1<<3)) {
672 if (mii_data & (1<<4)) {
673 *speed = IF_PORT_100BASEFX;
674 dev->if_port = IF_PORT_100BASEFX;
677 *speed = IF_PORT_100BASETX;
678 dev->if_port = IF_PORT_100BASETX;
682 *speed = IF_PORT_10BASET;
683 dev->if_port = IF_PORT_10BASET;
689 dev->if_port = IF_PORT_UNKNOWN;
695 #ifdef CONFIG_MIPS_BOSPORUS
696 int stub_init(struct net_device *dev, int phy_addr)
698 //printk("PHY stub_init\n");
702 int stub_reset(struct net_device *dev, int phy_addr)
704 //printk("PHY stub_reset\n");
709 stub_status(struct net_device *dev, int phy_addr, u16 *link, u16 *speed)
711 //printk("PHY stub_status\n");
714 *speed = IF_PORT_100BASEFX;
715 dev->if_port = IF_PORT_100BASEFX;
720 struct phy_ops bcm_5201_ops = {
726 struct phy_ops am79c874_ops = {
732 struct phy_ops am79c901_ops = {
738 struct phy_ops lsi_80227_ops = {
744 struct phy_ops lxt971a_ops = {
750 struct phy_ops ks8995m_ops = {
756 struct phy_ops smsc_83C185_ops = {
762 #ifdef CONFIG_MIPS_BOSPORUS
763 struct phy_ops stub_ops = {
770 static struct mii_chip_info {
774 struct phy_ops *phy_ops;
776 } mii_chip_table[] = {
777 {"Broadcom BCM5201 10/100 BaseT PHY",0x0040,0x6212, &bcm_5201_ops,0},
778 {"Broadcom BCM5221 10/100 BaseT PHY",0x0040,0x61e4, &bcm_5201_ops,0},
779 {"Broadcom BCM5222 10/100 BaseT PHY",0x0040,0x6322, &bcm_5201_ops,1},
780 {"NS DP83847 PHY", 0x2000, 0x5c30, &bcm_5201_ops ,0},
781 {"AMD 79C901 HomePNA PHY",0x0000,0x35c8, &am79c901_ops,0},
782 {"AMD 79C874 10/100 BaseT PHY",0x0022,0x561b, &am79c874_ops,0},
783 {"LSI 80227 10/100 BaseT PHY",0x0016,0xf840, &lsi_80227_ops,0},
784 {"Intel LXT971A Dual Speed PHY",0x0013,0x78e2, &lxt971a_ops,0},
785 {"Kendin KS8995M 10/100 BaseT PHY",0x0022,0x1450, &ks8995m_ops,0},
786 {"SMSC LAN83C185 10/100 BaseT PHY",0x0007,0xc0a3, &smsc_83C185_ops,0},
787 #ifdef CONFIG_MIPS_BOSPORUS
788 {"Stub", 0x1234, 0x5678, &stub_ops },
793 static int mdio_read(struct net_device *dev, int phy_id, int reg)
795 struct au1000_private *aup = (struct au1000_private *) dev->priv;
796 volatile u32 *mii_control_reg;
797 volatile u32 *mii_data_reg;
801 #ifdef CONFIG_BCM5222_DUAL_PHY
802 /* First time we probe, it's for the mac0 phy.
803 * Since we haven't determined yet that we have a dual phy,
804 * aup->mii->mii_control_reg won't be setup and we'll
805 * default to the else statement.
806 * By the time we probe for the mac1 phy, the mii_control_reg
807 * will be setup to be the address of the mac0 phy control since
808 * both phys are controlled through mac0.
810 if (aup->mii && aup->mii->mii_control_reg) {
811 mii_control_reg = aup->mii->mii_control_reg;
812 mii_data_reg = aup->mii->mii_data_reg;
814 else if (au_macs[0]->mii && au_macs[0]->mii->mii_control_reg) {
815 /* assume both phys are controlled through mac0 */
816 mii_control_reg = au_macs[0]->mii->mii_control_reg;
817 mii_data_reg = au_macs[0]->mii->mii_data_reg;
822 /* default control and data reg addresses */
823 mii_control_reg = &aup->mac->mii_control;
824 mii_data_reg = &aup->mac->mii_data;
827 while (*mii_control_reg & MAC_MII_BUSY) {
829 if (--timedout == 0) {
830 printk(KERN_ERR "%s: read_MII busy timeout!!\n",
836 mii_control = MAC_SET_MII_SELECT_REG(reg) |
837 MAC_SET_MII_SELECT_PHY(phy_id) | MAC_MII_READ;
839 *mii_control_reg = mii_control;
842 while (*mii_control_reg & MAC_MII_BUSY) {
844 if (--timedout == 0) {
845 printk(KERN_ERR "%s: mdio_read busy timeout!!\n",
850 return (int)*mii_data_reg;
853 static void mdio_write(struct net_device *dev, int phy_id, int reg, u16 value)
855 struct au1000_private *aup = (struct au1000_private *) dev->priv;
856 volatile u32 *mii_control_reg;
857 volatile u32 *mii_data_reg;
861 #ifdef CONFIG_BCM5222_DUAL_PHY
862 if (aup->mii && aup->mii->mii_control_reg) {
863 mii_control_reg = aup->mii->mii_control_reg;
864 mii_data_reg = aup->mii->mii_data_reg;
866 else if (au_macs[0]->mii && au_macs[0]->mii->mii_control_reg) {
867 /* assume both phys are controlled through mac0 */
868 mii_control_reg = au_macs[0]->mii->mii_control_reg;
869 mii_data_reg = au_macs[0]->mii->mii_data_reg;
874 /* default control and data reg addresses */
875 mii_control_reg = &aup->mac->mii_control;
876 mii_data_reg = &aup->mac->mii_data;
879 while (*mii_control_reg & MAC_MII_BUSY) {
881 if (--timedout == 0) {
882 printk(KERN_ERR "%s: mdio_write busy timeout!!\n",
888 mii_control = MAC_SET_MII_SELECT_REG(reg) |
889 MAC_SET_MII_SELECT_PHY(phy_id) | MAC_MII_WRITE;
891 *mii_data_reg = value;
892 *mii_control_reg = mii_control;
896 static void dump_mii(struct net_device *dev, int phy_id)
900 for (i = 0; i < 7; i++) {
901 if ((val = mdio_read(dev, phy_id, i)) >= 0)
902 printk("%s: MII Reg %d=%x\n", dev->name, i, val);
904 for (i = 16; i < 25; i++) {
905 if ((val = mdio_read(dev, phy_id, i)) >= 0)
906 printk("%s: MII Reg %d=%x\n", dev->name, i, val);
910 static int mii_probe (struct net_device * dev)
912 struct au1000_private *aup = (struct au1000_private *) dev->priv;
914 #ifdef CONFIG_MIPS_BOSPORUS
918 /* search for total of 32 possible mii phy addresses */
919 for (phy_addr = 0; phy_addr < 32; phy_addr++) {
921 u16 phy_id0, phy_id1;
924 #ifdef CONFIG_BCM5222_DUAL_PHY
925 /* Mask the already found phy, try next one */
926 if (au_macs[0]->mii && au_macs[0]->mii->mii_control_reg) {
927 if (au_macs[0]->phy_addr == phy_addr)
932 mii_status = mdio_read(dev, phy_addr, MII_STATUS);
933 if (mii_status == 0xffff || mii_status == 0x0000)
934 /* the mii is not accessable, try next one */
937 phy_id0 = mdio_read(dev, phy_addr, MII_PHY_ID0);
938 phy_id1 = mdio_read(dev, phy_addr, MII_PHY_ID1);
940 /* search our mii table for the current mii */
941 for (i = 0; mii_chip_table[i].phy_id1; i++) {
942 if (phy_id0 == mii_chip_table[i].phy_id0 &&
943 phy_id1 == mii_chip_table[i].phy_id1) {
944 struct mii_phy * mii_phy = aup->mii;
946 printk(KERN_INFO "%s: %s at phy address %d\n",
947 dev->name, mii_chip_table[i].name,
949 #ifdef CONFIG_MIPS_BOSPORUS
952 mii_phy->chip_info = mii_chip_table+i;
953 aup->phy_addr = phy_addr;
954 aup->want_autoneg = 1;
955 aup->phy_ops = mii_chip_table[i].phy_ops;
956 aup->phy_ops->phy_init(dev,phy_addr);
958 // Check for dual-phy and then store required
959 // values and set indicators. We need to do
960 // this now since mdio_{read,write} need the
961 // control and data register addresses.
962 #ifdef CONFIG_BCM5222_DUAL_PHY
963 if ( mii_chip_table[i].dual_phy) {
965 /* assume both phys are controlled
966 * through MAC0. Board specific? */
969 if (!au_macs[0] || !au_macs[0]->mii)
971 aup->mii->mii_control_reg = (u32 *)
972 &au_macs[0]->mac->mii_control;
973 aup->mii->mii_data_reg = (u32 *)
974 &au_macs[0]->mac->mii_data;
983 #ifdef CONFIG_MIPS_BOSPORUS
984 /* This is a workaround for the Micrel/Kendin 5 port switch
985 The second MAC doesn't see a PHY connected... so we need to
986 trick it into thinking we have one.
988 If this kernel is run on another Au1500 development board
989 the stub will be found as well as the actual PHY. However,
990 the last found PHY will be used... usually at Addr 31 (Db1500).
994 u16 phy_id0, phy_id1;
1000 /* search our mii table for the current mii */
1001 for (i = 0; mii_chip_table[i].phy_id1; i++) {
1002 if (phy_id0 == mii_chip_table[i].phy_id0 &&
1003 phy_id1 == mii_chip_table[i].phy_id1) {
1004 struct mii_phy * mii_phy;
1006 printk(KERN_INFO "%s: %s at phy address %d\n",
1007 dev->name, mii_chip_table[i].name,
1009 mii_phy = kmalloc(sizeof(struct mii_phy),
1012 mii_phy->chip_info = mii_chip_table+i;
1013 aup->phy_addr = phy_addr;
1014 mii_phy->next = aup->mii;
1016 mii_chip_table[i].phy_ops;
1018 aup->phy_ops->phy_init(dev,phy_addr);
1020 printk(KERN_ERR "%s: out of memory\n",
1024 mii_phy->chip_info = mii_chip_table+i;
1025 aup->phy_addr = phy_addr;
1026 aup->phy_ops = mii_chip_table[i].phy_ops;
1027 aup->phy_ops->phy_init(dev,phy_addr);
1032 if (aup->mac_id == 0) {
1033 /* the Bosporus phy responds to addresses 0-5 but
1034 * 5 is the correct one.
1040 if (aup->mii->chip_info == NULL) {
1041 printk(KERN_ERR "%s: Au1x No known MII transceivers found!\n",
1046 printk(KERN_INFO "%s: Using %s as default\n",
1047 dev->name, aup->mii->chip_info->name);
1054 * Buffer allocation/deallocation routines. The buffer descriptor returned
1055 * has the virtual and dma address of a buffer suitable for
1056 * both, receive and transmit operations.
1058 static db_dest_t *GetFreeDB(struct au1000_private *aup)
1064 aup->pDBfree = pDB->pnext;
1069 void ReleaseDB(struct au1000_private *aup, db_dest_t *pDB)
1071 db_dest_t *pDBfree = aup->pDBfree;
1073 pDBfree->pnext = pDB;
1077 static void enable_rx_tx(struct net_device *dev)
1079 struct au1000_private *aup = (struct au1000_private *) dev->priv;
1081 if (au1000_debug > 4)
1082 printk(KERN_INFO "%s: enable_rx_tx\n", dev->name);
1084 aup->mac->control |= (MAC_RX_ENABLE | MAC_TX_ENABLE);
1088 static void hard_stop(struct net_device *dev)
1090 struct au1000_private *aup = (struct au1000_private *) dev->priv;
1092 if (au1000_debug > 4)
1093 printk(KERN_INFO "%s: hard stop\n", dev->name);
1095 aup->mac->control &= ~(MAC_RX_ENABLE | MAC_TX_ENABLE);
1100 static void reset_mac(struct net_device *dev)
1104 struct au1000_private *aup = (struct au1000_private *) dev->priv;
1106 if (au1000_debug > 4)
1107 printk(KERN_INFO "%s: reset mac, aup %x\n",
1108 dev->name, (unsigned)aup);
1110 spin_lock_irqsave(&aup->lock, flags);
1111 if (aup->timer.function == &au1000_timer) {/* check if timer initted */
1112 del_timer(&aup->timer);
1116 #ifdef CONFIG_BCM5222_DUAL_PHY
1117 if (aup->mac_id != 0) {
1119 /* If BCM5222, we can't leave MAC0 in reset because then
1120 * we can't access the dual phy for ETH1 */
1121 *aup->enable = MAC_EN_CLOCK_ENABLE;
1125 #ifdef CONFIG_BCM5222_DUAL_PHY
1129 for (i = 0; i < NUM_RX_DMA; i++) {
1130 /* reset control bits */
1131 aup->rx_dma_ring[i]->buff_stat &= ~0xf;
1133 for (i = 0; i < NUM_TX_DMA; i++) {
1134 /* reset control bits */
1135 aup->tx_dma_ring[i]->buff_stat &= ~0xf;
1137 spin_unlock_irqrestore(&aup->lock, flags);
1142 * Setup the receive and transmit "rings". These pointers are the addresses
1143 * of the rx and tx MAC DMA registers so they are fixed by the hardware --
1144 * these are not descriptors sitting in memory.
1147 setup_hw_rings(struct au1000_private *aup, u32 rx_base, u32 tx_base)
1151 for (i = 0; i < NUM_RX_DMA; i++) {
1152 aup->rx_dma_ring[i] =
1153 (volatile rx_dma_t *) (rx_base + sizeof(rx_dma_t)*i);
1155 for (i = 0; i < NUM_TX_DMA; i++) {
1156 aup->tx_dma_ring[i] =
1157 (volatile tx_dma_t *) (tx_base + sizeof(tx_dma_t)*i);
1165 struct net_device *dev;
1167 #ifdef CONFIG_SOC_AU1000
1168 {AU1000_ETH0_BASE, AU1000_MAC0_ENABLE, AU1000_MAC0_DMA_INT},
1169 {AU1000_ETH1_BASE, AU1000_MAC1_ENABLE, AU1000_MAC1_DMA_INT}
1171 #ifdef CONFIG_SOC_AU1100
1172 {AU1100_ETH0_BASE, AU1100_MAC0_ENABLE, AU1100_MAC0_DMA_INT}
1174 #ifdef CONFIG_SOC_AU1500
1175 {AU1500_ETH0_BASE, AU1500_MAC0_ENABLE, AU1500_MAC0_DMA_INT},
1176 {AU1500_ETH1_BASE, AU1500_MAC1_ENABLE, AU1500_MAC1_DMA_INT}
1178 #ifdef CONFIG_SOC_AU1550
1179 {AU1550_ETH0_BASE, AU1550_MAC0_ENABLE, AU1550_MAC0_DMA_INT},
1180 {AU1550_ETH1_BASE, AU1550_MAC1_ENABLE, AU1550_MAC1_DMA_INT}
1187 * Setup the base address and interupt of the Au1xxx ethernet macs
1188 * based on cpu type and whether the interface is enabled in sys_pinfunc
1189 * register. The last interface is enabled if SYS_PF_NI2 (bit 4) is 0.
1191 static int __init au1000_init_module(void)
1193 int ni = (int)((au_readl(SYS_PINFUNC) & (u32)(SYS_PF_NI2)) >> 4);
1194 struct net_device *dev;
1195 int i, found_one = 0;
1197 num_ifs = NUM_ETH_INTERFACES - ni;
1199 for(i = 0; i < num_ifs; i++) {
1200 dev = au1000_probe(i);
1201 iflist[i].dev = dev;
1210 static int au1000_setup_aneg(struct net_device *dev, u32 advertise)
1212 struct au1000_private *aup = (struct au1000_private *)dev->priv;
1215 /* Setup standard advertise */
1216 adv = mdio_read(dev, aup->phy_addr, MII_ADVERTISE);
1217 adv &= ~(ADVERTISE_ALL | ADVERTISE_100BASE4);
1218 if (advertise & ADVERTISED_10baseT_Half)
1219 adv |= ADVERTISE_10HALF;
1220 if (advertise & ADVERTISED_10baseT_Full)
1221 adv |= ADVERTISE_10FULL;
1222 if (advertise & ADVERTISED_100baseT_Half)
1223 adv |= ADVERTISE_100HALF;
1224 if (advertise & ADVERTISED_100baseT_Full)
1225 adv |= ADVERTISE_100FULL;
1226 mdio_write(dev, aup->phy_addr, MII_ADVERTISE, adv);
1228 /* Start/Restart aneg */
1229 ctl = mdio_read(dev, aup->phy_addr, MII_BMCR);
1230 ctl |= (BMCR_ANENABLE | BMCR_ANRESTART);
1231 mdio_write(dev, aup->phy_addr, MII_BMCR, ctl);
1236 static int au1000_setup_forced(struct net_device *dev, int speed, int fd)
1238 struct au1000_private *aup = (struct au1000_private *)dev->priv;
1241 ctl = mdio_read(dev, aup->phy_addr, MII_BMCR);
1242 ctl &= ~(BMCR_FULLDPLX | BMCR_SPEED100 | BMCR_ANENABLE);
1244 /* First reset the PHY */
1245 mdio_write(dev, aup->phy_addr, MII_BMCR, ctl | BMCR_RESET);
1247 /* Select speed & duplex */
1252 ctl |= BMCR_SPEED100;
1258 if (fd == DUPLEX_FULL)
1259 ctl |= BMCR_FULLDPLX;
1260 mdio_write(dev, aup->phy_addr, MII_BMCR, ctl);
1267 au1000_start_link(struct net_device *dev, struct ethtool_cmd *cmd)
1269 struct au1000_private *aup = (struct au1000_private *)dev->priv;
1275 /* Default advertise */
1276 advertise = GENMII_DEFAULT_ADVERTISE;
1277 autoneg = aup->want_autoneg;
1278 forced_speed = SPEED_100;
1279 forced_duplex = DUPLEX_FULL;
1281 /* Setup link parameters */
1283 if (cmd->autoneg == AUTONEG_ENABLE) {
1284 advertise = cmd->advertising;
1289 forced_speed = cmd->speed;
1290 forced_duplex = cmd->duplex;
1294 /* Configure PHY & start aneg */
1295 aup->want_autoneg = autoneg;
1297 au1000_setup_aneg(dev, advertise);
1299 au1000_setup_forced(dev, forced_speed, forced_duplex);
1300 mod_timer(&aup->timer, jiffies + HZ);
1303 static int au1000_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1305 struct au1000_private *aup = (struct au1000_private *)dev->priv;
1308 cmd->supported = GENMII_DEFAULT_FEATURES;
1309 cmd->advertising = GENMII_DEFAULT_ADVERTISE;
1310 cmd->port = PORT_MII;
1311 cmd->transceiver = XCVR_EXTERNAL;
1312 cmd->phy_address = aup->phy_addr;
1313 spin_lock_irq(&aup->lock);
1314 cmd->autoneg = aup->want_autoneg;
1315 aup->phy_ops->phy_status(dev, aup->phy_addr, &link, &speed);
1316 if ((speed == IF_PORT_100BASETX) || (speed == IF_PORT_100BASEFX))
1317 cmd->speed = SPEED_100;
1318 else if (speed == IF_PORT_10BASET)
1319 cmd->speed = SPEED_10;
1320 if (link && (dev->if_port == IF_PORT_100BASEFX))
1321 cmd->duplex = DUPLEX_FULL;
1323 cmd->duplex = DUPLEX_HALF;
1324 spin_unlock_irq(&aup->lock);
1328 static int au1000_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1330 struct au1000_private *aup = (struct au1000_private *)dev->priv;
1331 unsigned long features = GENMII_DEFAULT_FEATURES;
1333 if (!capable(CAP_NET_ADMIN))
1336 if (cmd->autoneg != AUTONEG_ENABLE && cmd->autoneg != AUTONEG_DISABLE)
1338 if (cmd->autoneg == AUTONEG_ENABLE && cmd->advertising == 0)
1340 if (cmd->duplex != DUPLEX_HALF && cmd->duplex != DUPLEX_FULL)
1342 if (cmd->autoneg == AUTONEG_DISABLE)
1343 switch (cmd->speed) {
1345 if (cmd->duplex == DUPLEX_HALF &&
1346 (features & SUPPORTED_10baseT_Half) == 0)
1348 if (cmd->duplex == DUPLEX_FULL &&
1349 (features & SUPPORTED_10baseT_Full) == 0)
1353 if (cmd->duplex == DUPLEX_HALF &&
1354 (features & SUPPORTED_100baseT_Half) == 0)
1356 if (cmd->duplex == DUPLEX_FULL &&
1357 (features & SUPPORTED_100baseT_Full) == 0)
1363 else if ((features & SUPPORTED_Autoneg) == 0)
1366 spin_lock_irq(&aup->lock);
1367 au1000_start_link(dev, cmd);
1368 spin_unlock_irq(&aup->lock);
1372 static int au1000_nway_reset(struct net_device *dev)
1374 struct au1000_private *aup = (struct au1000_private *)dev->priv;
1376 if (!aup->want_autoneg)
1378 spin_lock_irq(&aup->lock);
1379 au1000_start_link(dev, NULL);
1380 spin_unlock_irq(&aup->lock);
1385 au1000_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
1387 struct au1000_private *aup = (struct au1000_private *)dev->priv;
1389 strcpy(info->driver, DRV_NAME);
1390 strcpy(info->version, DRV_VERSION);
1391 info->fw_version[0] = '\0';
1392 sprintf(info->bus_info, "%s %d", DRV_NAME, aup->mac_id);
1393 info->regdump_len = 0;
1396 static u32 au1000_get_link(struct net_device *dev)
1398 return netif_carrier_ok(dev);
1401 static struct ethtool_ops au1000_ethtool_ops = {
1402 .get_settings = au1000_get_settings,
1403 .set_settings = au1000_set_settings,
1404 .get_drvinfo = au1000_get_drvinfo,
1405 .nway_reset = au1000_nway_reset,
1406 .get_link = au1000_get_link
1409 static struct net_device * au1000_probe(int port_num)
1411 static unsigned version_printed = 0;
1412 struct au1000_private *aup = NULL;
1413 struct net_device *dev = NULL;
1414 db_dest_t *pDB, *pDBfree;
1415 char *pmac, *argptr;
1420 if (port_num >= NUM_ETH_INTERFACES)
1423 base = CPHYSADDR(iflist[port_num].base_addr );
1424 macen = CPHYSADDR(iflist[port_num].macen_addr);
1425 irq = iflist[port_num].irq;
1427 if (!request_mem_region( base, MAC_IOSIZE, "Au1x00 ENET") ||
1428 !request_mem_region(macen, 4, "Au1x00 ENET"))
1431 if (version_printed++ == 0)
1432 printk("%s version %s %s\n", DRV_NAME, DRV_VERSION, DRV_AUTHOR);
1434 dev = alloc_etherdev(sizeof(struct au1000_private));
1436 printk(KERN_ERR "%s: alloc_etherdev failed\n", DRV_NAME);
1440 if ((err = register_netdev(dev)) != 0) {
1441 printk(KERN_ERR "%s: Cannot register net device, error %d\n",
1447 printk("%s: Au1xx0 Ethernet found at 0x%x, irq %d\n",
1448 dev->name, base, irq);
1452 /* Allocate the data buffers */
1453 /* Snooping works fine with eth on all au1xxx */
1454 aup->vaddr = (u32)dma_alloc_noncoherent(NULL, MAX_BUF_SIZE *
1455 (NUM_TX_BUFFS + NUM_RX_BUFFS),
1459 release_mem_region( base, MAC_IOSIZE);
1460 release_mem_region(macen, 4);
1464 /* aup->mac is the base address of the MAC's registers */
1465 aup->mac = (volatile mac_reg_t *)iflist[port_num].base_addr;
1467 /* Setup some variables for quick register address access */
1468 aup->enable = (volatile u32 *)iflist[port_num].macen_addr;
1469 aup->mac_id = port_num;
1470 au_macs[port_num] = aup;
1472 if (port_num == 0) {
1473 /* Check the environment variables first */
1474 if (get_ethernet_addr(ethaddr) == 0)
1475 memcpy(au1000_mac_addr, ethaddr, sizeof(au1000_mac_addr));
1477 /* Check command line */
1478 argptr = prom_getcmdline();
1479 if ((pmac = strstr(argptr, "ethaddr=")) == NULL)
1480 printk(KERN_INFO "%s: No MAC address found\n",
1482 /* Use the hard coded MAC addresses */
1484 str2eaddr(ethaddr, pmac + strlen("ethaddr="));
1485 memcpy(au1000_mac_addr, ethaddr,
1486 sizeof(au1000_mac_addr));
1490 setup_hw_rings(aup, MAC0_RX_DMA_ADDR, MAC0_TX_DMA_ADDR);
1491 } else if (port_num == 1)
1492 setup_hw_rings(aup, MAC1_RX_DMA_ADDR, MAC1_TX_DMA_ADDR);
1495 * Assign to the Ethernet ports two consecutive MAC addresses
1496 * to match those that are printed on their stickers
1498 memcpy(dev->dev_addr, au1000_mac_addr, sizeof(au1000_mac_addr));
1499 dev->dev_addr[5] += port_num;
1501 /* Bring the device out of reset, otherwise probing the MII will hang */
1502 *aup->enable = MAC_EN_CLOCK_ENABLE;
1504 *aup->enable = MAC_EN_RESET0 | MAC_EN_RESET1 | MAC_EN_RESET2 |
1505 MAC_EN_CLOCK_ENABLE;
1508 aup->mii = kmalloc(sizeof(struct mii_phy), GFP_KERNEL);
1510 printk(KERN_ERR "%s: out of memory\n", dev->name);
1513 aup->mii->next = NULL;
1514 aup->mii->chip_info = NULL;
1515 aup->mii->status = 0;
1516 aup->mii->mii_control_reg = 0;
1517 aup->mii->mii_data_reg = 0;
1519 if (mii_probe(dev) != 0) {
1524 /* setup the data buffer descriptors and attach a buffer to each one */
1526 for (i = 0; i < (NUM_TX_BUFFS+NUM_RX_BUFFS); i++) {
1527 pDB->pnext = pDBfree;
1529 pDB->vaddr = (u32 *)((unsigned)aup->vaddr + MAX_BUF_SIZE*i);
1530 pDB->dma_addr = (dma_addr_t)virt_to_bus(pDB->vaddr);
1533 aup->pDBfree = pDBfree;
1535 for (i = 0; i < NUM_RX_DMA; i++) {
1536 pDB = GetFreeDB(aup);
1540 aup->rx_dma_ring[i]->buff_stat = (unsigned)pDB->dma_addr;
1541 aup->rx_db_inuse[i] = pDB;
1543 for (i = 0; i < NUM_TX_DMA; i++) {
1544 pDB = GetFreeDB(aup);
1548 aup->tx_dma_ring[i]->buff_stat = (unsigned)pDB->dma_addr;
1549 aup->tx_dma_ring[i]->len = 0;
1550 aup->tx_db_inuse[i] = pDB;
1553 spin_lock_init(&aup->lock);
1554 dev->base_addr = base;
1556 dev->open = au1000_open;
1557 dev->hard_start_xmit = au1000_tx;
1558 dev->stop = au1000_close;
1559 dev->get_stats = au1000_get_stats;
1560 dev->set_multicast_list = &set_rx_mode;
1561 dev->do_ioctl = &au1000_ioctl;
1562 SET_ETHTOOL_OPS(dev, &au1000_ethtool_ops);
1563 dev->set_config = &au1000_set_config;
1564 dev->tx_timeout = au1000_tx_timeout;
1565 dev->watchdog_timeo = ETH_TX_TIMEOUT;
1568 * The boot code uses the ethernet controller, so reset it to start
1569 * fresh. au1000_init() expects that the device is in reset state.
1576 /* here we should have a valid dev plus aup-> register addresses
1577 * so we can reset the mac properly.*/
1580 for (i = 0; i < NUM_RX_DMA; i++) {
1581 if (aup->rx_db_inuse[i])
1582 ReleaseDB(aup, aup->rx_db_inuse[i]);
1584 for (i = 0; i < NUM_TX_DMA; i++) {
1585 if (aup->tx_db_inuse[i])
1586 ReleaseDB(aup, aup->tx_db_inuse[i]);
1588 dma_free_noncoherent(NULL, MAX_BUF_SIZE * (NUM_TX_BUFFS + NUM_RX_BUFFS),
1589 (void *)aup->vaddr, aup->dma_addr);
1590 unregister_netdev(dev);
1592 release_mem_region( base, MAC_IOSIZE);
1593 release_mem_region(macen, 4);
1598 * Initialize the interface.
1600 * When the device powers up, the clocks are disabled and the
1601 * mac is in reset state. When the interface is closed, we
1602 * do the same -- reset the device and disable the clocks to
1603 * conserve power. Thus, whenever au1000_init() is called,
1604 * the device should already be in reset state.
1606 static int au1000_init(struct net_device *dev)
1608 struct au1000_private *aup = (struct au1000_private *) dev->priv;
1614 if (au1000_debug > 4)
1615 printk("%s: au1000_init\n", dev->name);
1617 spin_lock_irqsave(&aup->lock, flags);
1619 /* bring the device out of reset */
1620 *aup->enable = MAC_EN_CLOCK_ENABLE;
1622 *aup->enable = MAC_EN_RESET0 | MAC_EN_RESET1 |
1623 MAC_EN_RESET2 | MAC_EN_CLOCK_ENABLE;
1626 aup->mac->control = 0;
1627 aup->tx_head = (aup->tx_dma_ring[0]->buff_stat & 0xC) >> 2;
1628 aup->tx_tail = aup->tx_head;
1629 aup->rx_head = (aup->rx_dma_ring[0]->buff_stat & 0xC) >> 2;
1631 aup->mac->mac_addr_high = dev->dev_addr[5]<<8 | dev->dev_addr[4];
1632 aup->mac->mac_addr_low = dev->dev_addr[3]<<24 | dev->dev_addr[2]<<16 |
1633 dev->dev_addr[1]<<8 | dev->dev_addr[0];
1635 for (i = 0; i < NUM_RX_DMA; i++) {
1636 aup->rx_dma_ring[i]->buff_stat |= RX_DMA_ENABLE;
1640 aup->phy_ops->phy_status(dev, aup->phy_addr, &link, &speed);
1641 control = MAC_DISABLE_RX_OWN | MAC_RX_ENABLE | MAC_TX_ENABLE;
1642 #ifndef CONFIG_CPU_LITTLE_ENDIAN
1643 control |= MAC_BIG_ENDIAN;
1645 if (link && (dev->if_port == IF_PORT_100BASEFX)) {
1646 control |= MAC_FULL_DUPLEX;
1649 aup->mac->control = control;
1650 aup->mac->vlan1_tag = 0x8100; /* activate vlan support */
1653 spin_unlock_irqrestore(&aup->lock, flags);
1657 static void au1000_timer(unsigned long data)
1659 struct net_device *dev = (struct net_device *)data;
1660 struct au1000_private *aup = (struct au1000_private *) dev->priv;
1661 unsigned char if_port;
1665 /* fatal error, don't restart the timer */
1666 printk(KERN_ERR "au1000_timer error: NULL dev\n");
1670 if_port = dev->if_port;
1671 if (aup->phy_ops->phy_status(dev, aup->phy_addr, &link, &speed) == 0) {
1673 if (!netif_carrier_ok(dev)) {
1674 netif_carrier_on(dev);
1675 printk(KERN_INFO "%s: link up\n", dev->name);
1679 if (netif_carrier_ok(dev)) {
1680 netif_carrier_off(dev);
1682 printk(KERN_INFO "%s: link down\n", dev->name);
1687 if (link && (dev->if_port != if_port) &&
1688 (dev->if_port != IF_PORT_UNKNOWN)) {
1690 if (dev->if_port == IF_PORT_100BASEFX) {
1691 printk(KERN_INFO "%s: going to full duplex\n",
1693 aup->mac->control |= MAC_FULL_DUPLEX;
1697 aup->mac->control &= ~MAC_FULL_DUPLEX;
1703 aup->timer.expires = RUN_AT((1*HZ));
1704 aup->timer.data = (unsigned long)dev;
1705 aup->timer.function = &au1000_timer; /* timer handler */
1706 add_timer(&aup->timer);
1710 static int au1000_open(struct net_device *dev)
1713 struct au1000_private *aup = (struct au1000_private *) dev->priv;
1715 if (au1000_debug > 4)
1716 printk("%s: open: dev=%p\n", dev->name, dev);
1718 if ((retval = au1000_init(dev))) {
1719 printk(KERN_ERR "%s: error in au1000_init\n", dev->name);
1720 free_irq(dev->irq, dev);
1723 netif_start_queue(dev);
1725 if ((retval = request_irq(dev->irq, &au1000_interrupt, 0,
1727 printk(KERN_ERR "%s: unable to get IRQ %d\n",
1728 dev->name, dev->irq);
1732 init_timer(&aup->timer); /* used in ioctl() */
1733 aup->timer.expires = RUN_AT((3*HZ));
1734 aup->timer.data = (unsigned long)dev;
1735 aup->timer.function = &au1000_timer; /* timer handler */
1736 add_timer(&aup->timer);
1738 if (au1000_debug > 4)
1739 printk("%s: open: Initialization done.\n", dev->name);
1744 static int au1000_close(struct net_device *dev)
1747 struct au1000_private *aup = (struct au1000_private *) dev->priv;
1749 if (au1000_debug > 4)
1750 printk("%s: close: dev=%p\n", dev->name, dev);
1754 spin_lock_irqsave(&aup->lock, flags);
1756 /* stop the device */
1757 netif_stop_queue(dev);
1759 /* disable the interrupt */
1760 free_irq(dev->irq, dev);
1761 spin_unlock_irqrestore(&aup->lock, flags);
1766 static void __exit au1000_cleanup_module(void)
1769 struct net_device *dev;
1770 struct au1000_private *aup;
1772 for (i = 0; i < num_ifs; i++) {
1773 dev = iflist[i].dev;
1775 aup = (struct au1000_private *) dev->priv;
1776 unregister_netdev(dev);
1778 for (j = 0; j < NUM_RX_DMA; j++)
1779 if (aup->rx_db_inuse[j])
1780 ReleaseDB(aup, aup->rx_db_inuse[j]);
1781 for (j = 0; j < NUM_TX_DMA; j++)
1782 if (aup->tx_db_inuse[j])
1783 ReleaseDB(aup, aup->tx_db_inuse[j]);
1784 dma_free_noncoherent(NULL, MAX_BUF_SIZE *
1785 (NUM_TX_BUFFS + NUM_RX_BUFFS),
1786 (void *)aup->vaddr, aup->dma_addr);
1787 release_mem_region(dev->base_addr, MAC_IOSIZE);
1788 release_mem_region(CPHYSADDR(iflist[i].macen_addr), 4);
1794 static void update_tx_stats(struct net_device *dev, u32 status)
1796 struct au1000_private *aup = (struct au1000_private *) dev->priv;
1797 struct net_device_stats *ps = &aup->stats;
1799 if (status & TX_FRAME_ABORTED) {
1800 if (dev->if_port == IF_PORT_100BASEFX) {
1801 if (status & (TX_JAB_TIMEOUT | TX_UNDERRUN)) {
1802 /* any other tx errors are only valid
1803 * in half duplex mode */
1805 ps->tx_aborted_errors++;
1810 ps->tx_aborted_errors++;
1811 if (status & (TX_NO_CARRIER | TX_LOSS_CARRIER))
1812 ps->tx_carrier_errors++;
1819 * Called from the interrupt service routine to acknowledge
1820 * the TX DONE bits. This is a must if the irq is setup as
1823 static void au1000_tx_ack(struct net_device *dev)
1825 struct au1000_private *aup = (struct au1000_private *) dev->priv;
1826 volatile tx_dma_t *ptxd;
1828 ptxd = aup->tx_dma_ring[aup->tx_tail];
1830 while (ptxd->buff_stat & TX_T_DONE) {
1831 update_tx_stats(dev, ptxd->status);
1832 ptxd->buff_stat &= ~TX_T_DONE;
1836 aup->tx_tail = (aup->tx_tail + 1) & (NUM_TX_DMA - 1);
1837 ptxd = aup->tx_dma_ring[aup->tx_tail];
1841 netif_wake_queue(dev);
1848 * Au1000 transmit routine.
1850 static int au1000_tx(struct sk_buff *skb, struct net_device *dev)
1852 struct au1000_private *aup = (struct au1000_private *) dev->priv;
1853 struct net_device_stats *ps = &aup->stats;
1854 volatile tx_dma_t *ptxd;
1859 if (au1000_debug > 5)
1860 printk("%s: tx: aup %x len=%d, data=%p, head %d\n",
1861 dev->name, (unsigned)aup, skb->len,
1862 skb->data, aup->tx_head);
1864 ptxd = aup->tx_dma_ring[aup->tx_head];
1865 buff_stat = ptxd->buff_stat;
1866 if (buff_stat & TX_DMA_ENABLE) {
1867 /* We've wrapped around and the transmitter is still busy */
1868 netif_stop_queue(dev);
1872 else if (buff_stat & TX_T_DONE) {
1873 update_tx_stats(dev, ptxd->status);
1879 netif_wake_queue(dev);
1882 pDB = aup->tx_db_inuse[aup->tx_head];
1883 memcpy((void *)pDB->vaddr, skb->data, skb->len);
1884 if (skb->len < ETH_ZLEN) {
1885 for (i=skb->len; i<ETH_ZLEN; i++) {
1886 ((char *)pDB->vaddr)[i] = 0;
1888 ptxd->len = ETH_ZLEN;
1891 ptxd->len = skb->len;
1894 ps->tx_bytes += ptxd->len;
1896 ptxd->buff_stat = pDB->dma_addr | TX_DMA_ENABLE;
1899 aup->tx_head = (aup->tx_head + 1) & (NUM_TX_DMA - 1);
1900 dev->trans_start = jiffies;
1904 static inline void update_rx_stats(struct net_device *dev, u32 status)
1906 struct au1000_private *aup = (struct au1000_private *) dev->priv;
1907 struct net_device_stats *ps = &aup->stats;
1910 if (status & RX_MCAST_FRAME)
1913 if (status & RX_ERROR) {
1915 if (status & RX_MISSED_FRAME)
1916 ps->rx_missed_errors++;
1917 if (status & (RX_OVERLEN | RX_OVERLEN | RX_LEN_ERROR))
1918 ps->rx_length_errors++;
1919 if (status & RX_CRC_ERROR)
1920 ps->rx_crc_errors++;
1921 if (status & RX_COLL)
1925 ps->rx_bytes += status & RX_FRAME_LEN_MASK;
1930 * Au1000 receive routine.
1932 static int au1000_rx(struct net_device *dev)
1934 struct au1000_private *aup = (struct au1000_private *) dev->priv;
1935 struct sk_buff *skb;
1936 volatile rx_dma_t *prxd;
1937 u32 buff_stat, status;
1941 if (au1000_debug > 5)
1942 printk("%s: au1000_rx head %d\n", dev->name, aup->rx_head);
1944 prxd = aup->rx_dma_ring[aup->rx_head];
1945 buff_stat = prxd->buff_stat;
1946 while (buff_stat & RX_T_DONE) {
1947 status = prxd->status;
1948 pDB = aup->rx_db_inuse[aup->rx_head];
1949 update_rx_stats(dev, status);
1950 if (!(status & RX_ERROR)) {
1953 frmlen = (status & RX_FRAME_LEN_MASK);
1954 frmlen -= 4; /* Remove FCS */
1955 skb = dev_alloc_skb(frmlen + 2);
1958 "%s: Memory squeeze, dropping packet.\n",
1960 aup->stats.rx_dropped++;
1964 skb_reserve(skb, 2); /* 16 byte IP header align */
1965 eth_copy_and_sum(skb,
1966 (unsigned char *)pDB->vaddr, frmlen, 0);
1967 skb_put(skb, frmlen);
1968 skb->protocol = eth_type_trans(skb, dev);
1969 netif_rx(skb); /* pass the packet to upper layers */
1972 if (au1000_debug > 4) {
1973 if (status & RX_MISSED_FRAME)
1974 printk("rx miss\n");
1975 if (status & RX_WDOG_TIMER)
1976 printk("rx wdog\n");
1977 if (status & RX_RUNT)
1978 printk("rx runt\n");
1979 if (status & RX_OVERLEN)
1980 printk("rx overlen\n");
1981 if (status & RX_COLL)
1982 printk("rx coll\n");
1983 if (status & RX_MII_ERROR)
1984 printk("rx mii error\n");
1985 if (status & RX_CRC_ERROR)
1986 printk("rx crc error\n");
1987 if (status & RX_LEN_ERROR)
1988 printk("rx len error\n");
1989 if (status & RX_U_CNTRL_FRAME)
1990 printk("rx u control frame\n");
1991 if (status & RX_MISSED_FRAME)
1992 printk("rx miss\n");
1995 prxd->buff_stat = (u32)(pDB->dma_addr | RX_DMA_ENABLE);
1996 aup->rx_head = (aup->rx_head + 1) & (NUM_RX_DMA - 1);
1999 /* next descriptor */
2000 prxd = aup->rx_dma_ring[aup->rx_head];
2001 buff_stat = prxd->buff_stat;
2002 dev->last_rx = jiffies;
2009 * Au1000 interrupt service routine.
2011 static irqreturn_t au1000_interrupt(int irq, void *dev_id, struct pt_regs *regs)
2013 struct net_device *dev = (struct net_device *) dev_id;
2016 printk(KERN_ERR "%s: isr: null dev ptr\n", dev->name);
2017 return IRQ_RETVAL(1);
2020 /* Handle RX interrupts first to minimize chance of overrun */
2024 return IRQ_RETVAL(1);
2029 * The Tx ring has been full longer than the watchdog timeout
2030 * value. The transmitter must be hung?
2032 static void au1000_tx_timeout(struct net_device *dev)
2034 printk(KERN_ERR "%s: au1000_tx_timeout: dev=%p\n", dev->name, dev);
2037 dev->trans_start = jiffies;
2038 netif_wake_queue(dev);
2042 static unsigned const ethernet_polynomial = 0x04c11db7U;
2043 static inline u32 ether_crc(int length, unsigned char *data)
2047 while(--length >= 0) {
2048 unsigned char current_octet = *data++;
2050 for (bit = 0; bit < 8; bit++, current_octet >>= 1)
2052 ((crc < 0) ^ (current_octet & 1) ?
2053 ethernet_polynomial : 0);
2058 static void set_rx_mode(struct net_device *dev)
2060 struct au1000_private *aup = (struct au1000_private *) dev->priv;
2062 if (au1000_debug > 4)
2063 printk("%s: set_rx_mode: flags=%x\n", dev->name, dev->flags);
2065 if (dev->flags & IFF_PROMISC) { /* Set promiscuous. */
2066 aup->mac->control |= MAC_PROMISCUOUS;
2067 printk(KERN_INFO "%s: Promiscuous mode enabled.\n", dev->name);
2068 } else if ((dev->flags & IFF_ALLMULTI) ||
2069 dev->mc_count > MULTICAST_FILTER_LIMIT) {
2070 aup->mac->control |= MAC_PASS_ALL_MULTI;
2071 aup->mac->control &= ~MAC_PROMISCUOUS;
2072 printk(KERN_INFO "%s: Pass all multicast\n", dev->name);
2075 struct dev_mc_list *mclist;
2076 u32 mc_filter[2]; /* Multicast hash filter */
2078 mc_filter[1] = mc_filter[0] = 0;
2079 for (i = 0, mclist = dev->mc_list; mclist && i < dev->mc_count;
2080 i++, mclist = mclist->next) {
2081 set_bit(ether_crc(ETH_ALEN, mclist->dmi_addr)>>26,
2084 aup->mac->multi_hash_high = mc_filter[1];
2085 aup->mac->multi_hash_low = mc_filter[0];
2086 aup->mac->control &= ~MAC_PROMISCUOUS;
2087 aup->mac->control |= MAC_HASH_MODE;
2092 static int au1000_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
2094 struct au1000_private *aup = (struct au1000_private *)dev->priv;
2095 u16 *data = (u16 *)&rq->ifr_ifru;
2098 case SIOCDEVPRIVATE: /* Get the address of the PHY in use. */
2100 if (!netif_running(dev)) return -EINVAL;
2101 data[0] = aup->phy_addr;
2102 case SIOCDEVPRIVATE+1: /* Read the specified MII register. */
2104 data[3] = mdio_read(dev, data[0], data[1]);
2106 case SIOCDEVPRIVATE+2: /* Write the specified MII register */
2108 if (!capable(CAP_NET_ADMIN))
2110 mdio_write(dev, data[0], data[1],data[2]);
2119 static int au1000_set_config(struct net_device *dev, struct ifmap *map)
2121 struct au1000_private *aup = (struct au1000_private *) dev->priv;
2124 if (au1000_debug > 4) {
2125 printk("%s: set_config called: dev->if_port %d map->port %x\n",
2126 dev->name, dev->if_port, map->port);
2130 case IF_PORT_UNKNOWN: /* use auto here */
2131 printk(KERN_INFO "%s: config phy for aneg\n",
2133 dev->if_port = map->port;
2134 /* Link Down: the timer will bring it up */
2135 netif_carrier_off(dev);
2137 /* read current control */
2138 control = mdio_read(dev, aup->phy_addr, MII_CONTROL);
2139 control &= ~(MII_CNTL_FDX | MII_CNTL_F100);
2141 /* enable auto negotiation and reset the negotiation */
2142 mdio_write(dev, aup->phy_addr, MII_CONTROL,
2143 control | MII_CNTL_AUTO |
2148 case IF_PORT_10BASET: /* 10BaseT */
2149 printk(KERN_INFO "%s: config phy for 10BaseT\n",
2151 dev->if_port = map->port;
2153 /* Link Down: the timer will bring it up */
2154 netif_carrier_off(dev);
2156 /* set Speed to 10Mbps, Half Duplex */
2157 control = mdio_read(dev, aup->phy_addr, MII_CONTROL);
2158 control &= ~(MII_CNTL_F100 | MII_CNTL_AUTO |
2161 /* disable auto negotiation and force 10M/HD mode*/
2162 mdio_write(dev, aup->phy_addr, MII_CONTROL, control);
2165 case IF_PORT_100BASET: /* 100BaseT */
2166 case IF_PORT_100BASETX: /* 100BaseTx */
2167 printk(KERN_INFO "%s: config phy for 100BaseTX\n",
2169 dev->if_port = map->port;
2171 /* Link Down: the timer will bring it up */
2172 netif_carrier_off(dev);
2174 /* set Speed to 100Mbps, Half Duplex */
2175 /* disable auto negotiation and enable 100MBit Mode */
2176 control = mdio_read(dev, aup->phy_addr, MII_CONTROL);
2177 control &= ~(MII_CNTL_AUTO | MII_CNTL_FDX);
2178 control |= MII_CNTL_F100;
2179 mdio_write(dev, aup->phy_addr, MII_CONTROL, control);
2182 case IF_PORT_100BASEFX: /* 100BaseFx */
2183 printk(KERN_INFO "%s: config phy for 100BaseFX\n",
2185 dev->if_port = map->port;
2187 /* Link Down: the timer will bring it up */
2188 netif_carrier_off(dev);
2190 /* set Speed to 100Mbps, Full Duplex */
2191 /* disable auto negotiation and enable 100MBit Mode */
2192 control = mdio_read(dev, aup->phy_addr, MII_CONTROL);
2193 control &= ~MII_CNTL_AUTO;
2194 control |= MII_CNTL_F100 | MII_CNTL_FDX;
2195 mdio_write(dev, aup->phy_addr, MII_CONTROL, control);
2197 case IF_PORT_10BASE2: /* 10Base2 */
2198 case IF_PORT_AUI: /* AUI */
2199 /* These Modes are not supported (are they?)*/
2200 printk(KERN_ERR "%s: 10Base2/AUI not supported",
2206 printk(KERN_ERR "%s: Invalid media selected",
2213 static struct net_device_stats *au1000_get_stats(struct net_device *dev)
2215 struct au1000_private *aup = (struct au1000_private *) dev->priv;
2217 if (au1000_debug > 4)
2218 printk("%s: au1000_get_stats: dev=%p\n", dev->name, dev);
2220 if (netif_device_present(dev)) {
2226 module_init(au1000_init_module);
2227 module_exit(au1000_cleanup_module);