2 * Copyright(c) 2005 - 2006 Attansic Corporation. All rights reserved.
3 * Copyright(c) 2006 - 2007 Chris Snook <csnook@redhat.com>
4 * Copyright(c) 2006 Jay Cliburn <jcliburn@gmail.com>
6 * Derived from Intel e1000 driver
7 * Copyright(c) 1999 - 2005 Intel Corporation. All rights reserved.
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms of the GNU General Public License as published by the Free
11 * Software Foundation; either version 2 of the License, or (at your option)
14 * This program is distributed in the hope that it will be useful, but WITHOUT
15 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
16 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
19 * You should have received a copy of the GNU General Public License along with
20 * this program; if not, write to the Free Software Foundation, Inc., 59
21 * Temple Place - Suite 330, Boston, MA 02111-1307, USA.
27 #include <linux/compiler.h>
28 #include <linux/ethtool.h>
29 #include <linux/if_vlan.h>
30 #include <linux/mii.h>
31 #include <linux/module.h>
32 #include <linux/skbuff.h>
33 #include <linux/spinlock.h>
34 #include <linux/timer.h>
35 #include <linux/types.h>
36 #include <linux/workqueue.h>
40 #define ATLX_DRIVER_NAME "atl1"
42 MODULE_DESCRIPTION("Atheros L1 Gigabit Ethernet Driver");
44 #define atlx_adapter atl1_adapter
45 #define atlx_check_for_link atl1_check_for_link
46 #define atlx_check_link atl1_check_link
47 #define atlx_hash_mc_addr atl1_hash_mc_addr
48 #define atlx_hash_set atl1_hash_set
49 #define atlx_hw atl1_hw
50 #define atlx_mii_ioctl atl1_mii_ioctl
51 #define atlx_read_phy_reg atl1_read_phy_reg
52 #define atlx_set_mac atl1_set_mac
53 #define atlx_set_mac_addr atl1_set_mac_addr
58 /* function prototypes needed by multiple files */
59 s32 atl1_phy_setup_autoneg_adv(struct atl1_hw *hw);
60 s32 atl1_write_phy_reg(struct atl1_hw *hw, u32 reg_addr, u16 phy_data);
61 s32 atl1_get_speed_and_duplex(struct atl1_hw *hw, u16 *speed, u16 *duplex);
62 s32 atl1_read_mac_addr(struct atl1_hw *hw);
63 s32 atl1_init_hw(struct atl1_hw *hw);
64 s32 atl1_get_speed_and_duplex(struct atl1_hw *hw, u16 *speed, u16 *duplex);
65 s32 atl1_set_speed_and_duplex(struct atl1_hw *hw, u16 speed, u16 duplex);
66 u32 atl1_hash_mc_addr(struct atl1_hw *hw, u8 *mc_addr);
67 void atl1_hash_set(struct atl1_hw *hw, u32 hash_value);
68 s32 atl1_read_phy_reg(struct atl1_hw *hw, u16 reg_addr, u16 *phy_data);
69 void atl1_set_mac_addr(struct atl1_hw *hw);
70 s32 atl1_phy_enter_power_saving(struct atl1_hw *hw);
71 s32 atl1_reset_hw(struct atl1_hw *hw);
72 void atl1_check_options(struct atl1_adapter *adapter);
73 static int atl1_mii_ioctl(struct net_device *netdev, struct ifreq *ifr,
75 static u32 atl1_check_link(struct atl1_adapter *adapter);
77 extern const struct ethtool_ops atl1_ethtool_ops;
79 /* hardware definitions specific to L1 */
81 /* Block IDLE Status Register */
82 #define IDLE_STATUS_RXMAC 0x1
83 #define IDLE_STATUS_TXMAC 0x2
84 #define IDLE_STATUS_RXQ 0x4
85 #define IDLE_STATUS_TXQ 0x8
86 #define IDLE_STATUS_DMAR 0x10
87 #define IDLE_STATUS_DMAW 0x20
88 #define IDLE_STATUS_SMB 0x40
89 #define IDLE_STATUS_CMB 0x80
91 /* MDIO Control Register */
92 #define MDIO_WAIT_TIMES 30
94 /* MAC Control Register */
95 #define MAC_CTRL_TX_PAUSE 0x10000
96 #define MAC_CTRL_SCNT 0x20000
97 #define MAC_CTRL_SRST_TX 0x40000
98 #define MAC_CTRL_TX_SIMURST 0x80000
99 #define MAC_CTRL_SPEED_SHIFT 20
100 #define MAC_CTRL_SPEED_MASK 0x300000
101 #define MAC_CTRL_SPEED_1000 0x2
102 #define MAC_CTRL_SPEED_10_100 0x1
103 #define MAC_CTRL_DBG_TX_BKPRESURE 0x400000
104 #define MAC_CTRL_TX_HUGE 0x800000
105 #define MAC_CTRL_RX_CHKSUM_EN 0x1000000
106 #define MAC_CTRL_DBG 0x8000000
108 /* Wake-On-Lan control register */
109 #define WOL_CLK_SWITCH_EN 0x8000
110 #define WOL_PT5_EN 0x200000
111 #define WOL_PT6_EN 0x400000
112 #define WOL_PT5_MATCH 0x8000000
113 #define WOL_PT6_MATCH 0x10000000
115 /* WOL Length ( 2 DWORD ) */
116 #define REG_WOL_PATTERN_LEN 0x14A4
117 #define WOL_PT_LEN_MASK 0x7F
118 #define WOL_PT0_LEN_SHIFT 0
119 #define WOL_PT1_LEN_SHIFT 8
120 #define WOL_PT2_LEN_SHIFT 16
121 #define WOL_PT3_LEN_SHIFT 24
122 #define WOL_PT4_LEN_SHIFT 0
123 #define WOL_PT5_LEN_SHIFT 8
124 #define WOL_PT6_LEN_SHIFT 16
126 /* Internal SRAM Partition Registers, low 32 bits */
127 #define REG_SRAM_RFD_LEN 0x1504
128 #define REG_SRAM_RRD_ADDR 0x1508
129 #define REG_SRAM_RRD_LEN 0x150C
130 #define REG_SRAM_TPD_ADDR 0x1510
131 #define REG_SRAM_TPD_LEN 0x1514
132 #define REG_SRAM_TRD_ADDR 0x1518
133 #define REG_SRAM_TRD_LEN 0x151C
134 #define REG_SRAM_RXF_ADDR 0x1520
135 #define REG_SRAM_RXF_LEN 0x1524
136 #define REG_SRAM_TXF_ADDR 0x1528
137 #define REG_SRAM_TXF_LEN 0x152C
138 #define REG_SRAM_TCPH_PATH_ADDR 0x1530
139 #define SRAM_TCPH_ADDR_MASK 0xFFF
140 #define SRAM_TCPH_ADDR_SHIFT 0
141 #define SRAM_PATH_ADDR_MASK 0xFFF
142 #define SRAM_PATH_ADDR_SHIFT 16
144 /* Load Ptr Register */
145 #define REG_LOAD_PTR 0x1534
147 /* Descriptor Control registers, low 32 bits */
148 #define REG_DESC_RFD_ADDR_LO 0x1544
149 #define REG_DESC_RRD_ADDR_LO 0x1548
150 #define REG_DESC_TPD_ADDR_LO 0x154C
151 #define REG_DESC_CMB_ADDR_LO 0x1550
152 #define REG_DESC_SMB_ADDR_LO 0x1554
153 #define REG_DESC_RFD_RRD_RING_SIZE 0x1558
154 #define DESC_RFD_RING_SIZE_MASK 0x7FF
155 #define DESC_RFD_RING_SIZE_SHIFT 0
156 #define DESC_RRD_RING_SIZE_MASK 0x7FF
157 #define DESC_RRD_RING_SIZE_SHIFT 16
158 #define REG_DESC_TPD_RING_SIZE 0x155C
159 #define DESC_TPD_RING_SIZE_MASK 0x3FF
160 #define DESC_TPD_RING_SIZE_SHIFT 0
162 /* TXQ Control Register */
163 #define REG_TXQ_CTRL 0x1580
164 #define TXQ_CTRL_TPD_BURST_NUM_SHIFT 0
165 #define TXQ_CTRL_TPD_BURST_NUM_MASK 0x1F
166 #define TXQ_CTRL_EN 0x20
167 #define TXQ_CTRL_ENH_MODE 0x40
168 #define TXQ_CTRL_TPD_FETCH_TH_SHIFT 8
169 #define TXQ_CTRL_TPD_FETCH_TH_MASK 0x3F
170 #define TXQ_CTRL_TXF_BURST_NUM_SHIFT 16
171 #define TXQ_CTRL_TXF_BURST_NUM_MASK 0xFFFF
173 /* Jumbo packet Threshold for task offload */
174 #define REG_TX_JUMBO_TASK_TH_TPD_IPG 0x1584
175 #define TX_JUMBO_TASK_TH_MASK 0x7FF
176 #define TX_JUMBO_TASK_TH_SHIFT 0
177 #define TX_TPD_MIN_IPG_MASK 0x1F
178 #define TX_TPD_MIN_IPG_SHIFT 16
180 /* RXQ Control Register */
181 #define REG_RXQ_CTRL 0x15A0
182 #define RXQ_CTRL_RFD_BURST_NUM_SHIFT 0
183 #define RXQ_CTRL_RFD_BURST_NUM_MASK 0xFF
184 #define RXQ_CTRL_RRD_BURST_THRESH_SHIFT 8
185 #define RXQ_CTRL_RRD_BURST_THRESH_MASK 0xFF
186 #define RXQ_CTRL_RFD_PREF_MIN_IPG_SHIFT 16
187 #define RXQ_CTRL_RFD_PREF_MIN_IPG_MASK 0x1F
188 #define RXQ_CTRL_CUT_THRU_EN 0x40000000
189 #define RXQ_CTRL_EN 0x80000000
191 /* Rx jumbo packet threshold and rrd retirement timer */
192 #define REG_RXQ_JMBOSZ_RRDTIM 0x15A4
193 #define RXQ_JMBOSZ_TH_MASK 0x7FF
194 #define RXQ_JMBOSZ_TH_SHIFT 0
195 #define RXQ_JMBO_LKAH_MASK 0xF
196 #define RXQ_JMBO_LKAH_SHIFT 11
197 #define RXQ_RRD_TIMER_MASK 0xFFFF
198 #define RXQ_RRD_TIMER_SHIFT 16
200 /* RFD flow control register */
201 #define REG_RXQ_RXF_PAUSE_THRESH 0x15A8
202 #define RXQ_RXF_PAUSE_TH_HI_SHIFT 16
203 #define RXQ_RXF_PAUSE_TH_HI_MASK 0xFFF
204 #define RXQ_RXF_PAUSE_TH_LO_SHIFT 0
205 #define RXQ_RXF_PAUSE_TH_LO_MASK 0xFFF
207 /* RRD flow control register */
208 #define REG_RXQ_RRD_PAUSE_THRESH 0x15AC
209 #define RXQ_RRD_PAUSE_TH_HI_SHIFT 0
210 #define RXQ_RRD_PAUSE_TH_HI_MASK 0xFFF
211 #define RXQ_RRD_PAUSE_TH_LO_SHIFT 16
212 #define RXQ_RRD_PAUSE_TH_LO_MASK 0xFFF
214 /* DMA Engine Control Register */
215 #define REG_DMA_CTRL 0x15C0
216 #define DMA_CTRL_DMAR_IN_ORDER 0x1
217 #define DMA_CTRL_DMAR_ENH_ORDER 0x2
218 #define DMA_CTRL_DMAR_OUT_ORDER 0x4
219 #define DMA_CTRL_RCB_VALUE 0x8
220 #define DMA_CTRL_DMAR_BURST_LEN_SHIFT 4
221 #define DMA_CTRL_DMAR_BURST_LEN_MASK 7
222 #define DMA_CTRL_DMAW_BURST_LEN_SHIFT 7
223 #define DMA_CTRL_DMAW_BURST_LEN_MASK 7
224 #define DMA_CTRL_DMAR_EN 0x400
225 #define DMA_CTRL_DMAW_EN 0x800
227 /* CMB/SMB Control Register */
228 #define REG_CSMB_CTRL 0x15D0
229 #define CSMB_CTRL_CMB_NOW 1
230 #define CSMB_CTRL_SMB_NOW 2
231 #define CSMB_CTRL_CMB_EN 4
232 #define CSMB_CTRL_SMB_EN 8
234 /* CMB DMA Write Threshold Register */
235 #define REG_CMB_WRITE_TH 0x15D4
236 #define CMB_RRD_TH_SHIFT 0
237 #define CMB_RRD_TH_MASK 0x7FF
238 #define CMB_TPD_TH_SHIFT 16
239 #define CMB_TPD_TH_MASK 0x7FF
241 /* RX/TX count-down timer to trigger CMB-write. 2us resolution. */
242 #define REG_CMB_WRITE_TIMER 0x15D8
243 #define CMB_RX_TM_SHIFT 0
244 #define CMB_RX_TM_MASK 0xFFFF
245 #define CMB_TX_TM_SHIFT 16
246 #define CMB_TX_TM_MASK 0xFFFF
248 /* Number of packet received since last CMB write */
249 #define REG_CMB_RX_PKT_CNT 0x15DC
251 /* Number of packet transmitted since last CMB write */
252 #define REG_CMB_TX_PKT_CNT 0x15E0
254 /* SMB auto DMA timer register */
255 #define REG_SMB_TIMER 0x15E4
257 /* Mailbox Register */
258 #define REG_MAILBOX 0x15F0
259 #define MB_RFD_PROD_INDX_SHIFT 0
260 #define MB_RFD_PROD_INDX_MASK 0x7FF
261 #define MB_RRD_CONS_INDX_SHIFT 11
262 #define MB_RRD_CONS_INDX_MASK 0x7FF
263 #define MB_TPD_PROD_INDX_SHIFT 22
264 #define MB_TPD_PROD_INDX_MASK 0x3FF
266 /* Interrupt Status Register */
268 #define ISR_TIMER 0x2
269 #define ISR_MANUAL 0x4
270 #define ISR_RXF_OV 0x8
271 #define ISR_RFD_UNRUN 0x10
272 #define ISR_RRD_OV 0x20
273 #define ISR_TXF_UNRUN 0x40
274 #define ISR_LINK 0x80
275 #define ISR_HOST_RFD_UNRUN 0x100
276 #define ISR_HOST_RRD_OV 0x200
277 #define ISR_DMAR_TO_RST 0x400
278 #define ISR_DMAW_TO_RST 0x800
279 #define ISR_GPHY 0x1000
280 #define ISR_RX_PKT 0x10000
281 #define ISR_TX_PKT 0x20000
282 #define ISR_TX_DMA 0x40000
283 #define ISR_RX_DMA 0x80000
284 #define ISR_CMB_RX 0x100000
285 #define ISR_CMB_TX 0x200000
286 #define ISR_MAC_RX 0x400000
287 #define ISR_MAC_TX 0x800000
288 #define ISR_DIS_SMB 0x20000000
289 #define ISR_DIS_DMA 0x40000000
291 /* Normal Interrupt mask */
292 #define IMR_NORMAL_MASK (\
301 /* Debug Interrupt Mask (enable all interrupt) */
302 #define IMR_DEBUG_MASK (\
318 #define MEDIA_TYPE_1000M_FULL 1
319 #define MEDIA_TYPE_100M_FULL 2
320 #define MEDIA_TYPE_100M_HALF 3
321 #define MEDIA_TYPE_10M_FULL 4
322 #define MEDIA_TYPE_10M_HALF 5
324 #define AUTONEG_ADVERTISE_SPEED_DEFAULT 0x002F /* All but 1000-Half */
326 #define MAX_JUMBO_FRAME_SIZE 10240
328 #define ATL1_EEDUMP_LEN 48
330 /* Statistics counters collected by the MAC */
331 struct stats_msg_block {
333 u32 rx_ok; /* good RX packets */
334 u32 rx_bcast; /* good RX broadcast packets */
335 u32 rx_mcast; /* good RX multicast packets */
336 u32 rx_pause; /* RX pause frames */
337 u32 rx_ctrl; /* RX control packets other than pause frames */
338 u32 rx_fcs_err; /* RX packets with bad FCS */
339 u32 rx_len_err; /* RX packets with length != actual size */
340 u32 rx_byte_cnt; /* good bytes received. FCS is NOT included */
341 u32 rx_runt; /* RX packets < 64 bytes with good FCS */
342 u32 rx_frag; /* RX packets < 64 bytes with bad FCS */
343 u32 rx_sz_64; /* 64 byte RX packets */
349 u32 rx_sz_1519_max; /* 1519 byte to MTU RX packets */
350 u32 rx_sz_ov; /* truncated RX packets > MTU */
351 u32 rx_rxf_ov; /* frames dropped due to RX FIFO overflow */
352 u32 rx_rrd_ov; /* frames dropped due to RRD overflow */
353 u32 rx_align_err; /* alignment errors */
354 u32 rx_bcast_byte_cnt; /* RX broadcast bytes, excluding FCS */
355 u32 rx_mcast_byte_cnt; /* RX multicast bytes, excluding FCS */
356 u32 rx_err_addr; /* packets dropped due to address filtering */
359 u32 tx_ok; /* good TX packets */
360 u32 tx_bcast; /* good TX broadcast packets */
361 u32 tx_mcast; /* good TX multicast packets */
362 u32 tx_pause; /* TX pause frames */
363 u32 tx_exc_defer; /* TX packets deferred excessively */
364 u32 tx_ctrl; /* TX control frames, excluding pause frames */
365 u32 tx_defer; /* TX packets deferred */
366 u32 tx_byte_cnt; /* bytes transmitted, FCS is NOT included */
367 u32 tx_sz_64; /* 64 byte TX packets */
373 u32 tx_sz_1519_max; /* 1519 byte to MTU TX packets */
374 u32 tx_1_col; /* packets TX after a single collision */
375 u32 tx_2_col; /* packets TX after multiple collisions */
376 u32 tx_late_col; /* TX packets with late collisions */
377 u32 tx_abort_col; /* TX packets aborted w/excessive collisions */
378 u32 tx_underrun; /* TX packets aborted due to TX FIFO underrun
379 * or TRD FIFO underrun */
380 u32 tx_rd_eop; /* reads beyond the EOP into the next frame
381 * when TRD was not written timely */
382 u32 tx_len_err; /* TX packets where length != actual size */
383 u32 tx_trunc; /* TX packets truncated due to size > MTU */
384 u32 tx_bcast_byte; /* broadcast bytes transmitted, excluding FCS */
385 u32 tx_mcast_byte; /* multicast bytes transmitted, excluding FCS */
386 u32 smb_updated; /* 1: SMB Updated. This is used by software to
387 * indicate the statistics update. Software
388 * should clear this bit after retrieving the
389 * statistics information. */
392 /* Coalescing Message Block */
393 struct coals_msg_block {
394 u32 int_stats; /* interrupt status */
395 u16 rrd_prod_idx; /* TRD Producer Index. */
396 u16 rfd_cons_idx; /* RFD Consumer Index. */
397 u16 update; /* Selene sets this bit every time it DMAs the
398 * CMB to host memory. Software should clear
399 * this bit when CMB info is processed. */
400 u16 tpd_cons_idx; /* TPD Consumer Index. */
404 struct rx_return_desc {
405 u8 num_buf; /* Number of RFD buffers used by the received packet */
407 u16 buf_indx; /* RFD Index of the first buffer */
416 u16 pkt_flg; /* Packet flags */
417 u16 err_flg; /* Error flags */
419 u16 vlan_tag; /* VLAN TAG */
422 #define PACKET_FLAG_ETH_TYPE 0x0080
423 #define PACKET_FLAG_VLAN_INS 0x0100
424 #define PACKET_FLAG_ERR 0x0200
425 #define PACKET_FLAG_IPV4 0x0400
426 #define PACKET_FLAG_UDP 0x0800
427 #define PACKET_FLAG_TCP 0x1000
428 #define PACKET_FLAG_BCAST 0x2000
429 #define PACKET_FLAG_MCAST 0x4000
430 #define PACKET_FLAG_PAUSE 0x8000
432 #define ERR_FLAG_CRC 0x0001
433 #define ERR_FLAG_CODE 0x0002
434 #define ERR_FLAG_DRIBBLE 0x0004
435 #define ERR_FLAG_RUNT 0x0008
436 #define ERR_FLAG_OV 0x0010
437 #define ERR_FLAG_TRUNC 0x0020
438 #define ERR_FLAG_IP_CHKSUM 0x0040
439 #define ERR_FLAG_L4_CHKSUM 0x0080
440 #define ERR_FLAG_LEN 0x0100
441 #define ERR_FLAG_DES_ADDR 0x0200
444 struct rx_free_desc {
445 __le64 buffer_addr; /* Address of the descriptor's data buffer */
446 __le16 buf_len; /* Size of the receive buffer in host memory */
447 u16 coalese; /* Update consumer index to host after the
448 * reception of this frame */
449 /* __attribute__ ((packed)) is required */
450 } __attribute__ ((packed));
453 * The L1 transmit packet descriptor is comprised of four 32-bit words.
456 * +---------------------------------------+
457 * | Word 0: Buffer addr lo |
458 * +---------------------------------------+
459 * | Word 1: Buffer addr hi |
460 * +---------------------------------------+
462 * +---------------------------------------+
464 * +---------------------------------------+
466 * Words 0 and 1 combine to form a 64-bit buffer address.
468 * Word 2 is self explanatory in the #define block below.
470 * Word 3 has two forms, depending upon the state of bits 3 and 4.
471 * If bits 3 and 4 are both zero, then bits 14:31 are unused by the
472 * hardware. Otherwise, if either bit 3 or 4 is set, the definition
473 * of bits 14:31 vary according to the following depiction.
475 * 0 End of packet 0 End of packet
476 * 1 Coalesce 1 Coalesce
477 * 2 Insert VLAN tag 2 Insert VLAN tag
478 * 3 Custom csum enable = 0 3 Custom csum enable = 1
479 * 4 Segment enable = 1 4 Segment enable = 0
480 * 5 Generate IP checksum 5 Generate IP checksum
481 * 6 Generate TCP checksum 6 Generate TCP checksum
482 * 7 Generate UDP checksum 7 Generate UDP checksum
483 * 8 VLAN tagged 8 VLAN tagged
484 * 9 Ethernet frame type 9 Ethernet frame type
486 * 11 | IP hdr length (10:13) 11 | IP hdr length (10:13)
487 * 12 | (num 32-bit words) 12 | (num 32-bit words)
490 * 15 | TCP hdr length (14:17) 15 Unused
491 * 16 | (num 32-bit words) 16-+
493 * 18 Header TPD flag 18 |
494 * 19-+ 19 | Payload offset
500 * 25 | MSS (19:31) 25 |
502 * 27 | 27 | Custom csum offset
510 #define TPD_BUFLEN_MASK 0x3FFF
511 #define TPD_BUFLEN_SHIFT 0
512 #define TPD_DMAINT_MASK 0x0001
513 #define TPD_DMAINT_SHIFT 14
514 #define TPD_PKTNT_MASK 0x0001
515 #define TPD_PKTINT_SHIFT 15
516 #define TPD_VLANTAG_MASK 0xFFFF
517 #define TPD_VLAN_SHIFT 16
519 /* tpd word 3 bits 0:13 */
520 #define TPD_EOP_MASK 0x0001
521 #define TPD_EOP_SHIFT 0
522 #define TPD_COALESCE_MASK 0x0001
523 #define TPD_COALESCE_SHIFT 1
524 #define TPD_INS_VL_TAG_MASK 0x0001
525 #define TPD_INS_VL_TAG_SHIFT 2
526 #define TPD_CUST_CSUM_EN_MASK 0x0001
527 #define TPD_CUST_CSUM_EN_SHIFT 3
528 #define TPD_SEGMENT_EN_MASK 0x0001
529 #define TPD_SEGMENT_EN_SHIFT 4
530 #define TPD_IP_CSUM_MASK 0x0001
531 #define TPD_IP_CSUM_SHIFT 5
532 #define TPD_TCP_CSUM_MASK 0x0001
533 #define TPD_TCP_CSUM_SHIFT 6
534 #define TPD_UDP_CSUM_MASK 0x0001
535 #define TPD_UDP_CSUM_SHIFT 7
536 #define TPD_VL_TAGGED_MASK 0x0001
537 #define TPD_VL_TAGGED_SHIFT 8
538 #define TPD_ETHTYPE_MASK 0x0001
539 #define TPD_ETHTYPE_SHIFT 9
540 #define TPD_IPHL_MASK 0x000F
541 #define TPD_IPHL_SHIFT 10
543 /* tpd word 3 bits 14:31 if segment enabled */
544 #define TPD_TCPHDRLEN_MASK 0x000F
545 #define TPD_TCPHDRLEN_SHIFT 14
546 #define TPD_HDRFLAG_MASK 0x0001
547 #define TPD_HDRFLAG_SHIFT 18
548 #define TPD_MSS_MASK 0x1FFF
549 #define TPD_MSS_SHIFT 19
551 /* tpd word 3 bits 16:31 if custom csum enabled */
552 #define TPD_PLOADOFFSET_MASK 0x00FF
553 #define TPD_PLOADOFFSET_SHIFT 16
554 #define TPD_CCSUMOFFSET_MASK 0x00FF
555 #define TPD_CCSUMOFFSET_SHIFT 24
557 struct tx_packet_desc {
563 /* DMA Order Settings */
564 enum atl1_dma_order {
566 atl1_dma_ord_enh = 2,
575 enum atl1_dma_req_block {
576 atl1_dma_req_128 = 0,
577 atl1_dma_req_256 = 1,
578 atl1_dma_req_512 = 2,
579 atl1_dma_req_1024 = 3,
580 atl1_dma_req_2048 = 4,
581 atl1_dma_req_4096 = 5
584 #define ATL1_MAX_INTR 3
585 #define ATL1_MAX_TX_BUF_LEN 0x3000 /* 12288 bytes */
587 #define ATL1_DEFAULT_TPD 256
588 #define ATL1_MAX_TPD 1024
589 #define ATL1_MIN_TPD 64
590 #define ATL1_DEFAULT_RFD 512
591 #define ATL1_MIN_RFD 128
592 #define ATL1_MAX_RFD 2048
593 #define ATL1_REG_COUNT 1538
595 #define ATL1_GET_DESC(R, i, type) (&(((type *)((R)->desc))[i]))
596 #define ATL1_RFD_DESC(R, i) ATL1_GET_DESC(R, i, struct rx_free_desc)
597 #define ATL1_TPD_DESC(R, i) ATL1_GET_DESC(R, i, struct tx_packet_desc)
598 #define ATL1_RRD_DESC(R, i) ATL1_GET_DESC(R, i, struct rx_return_desc)
601 * atl1_ring_header represents a single, contiguous block of DMA space
602 * mapped for the three descriptor rings (tpd, rfd, rrd) and the two
603 * message blocks (cmb, smb) described below
605 struct atl1_ring_header {
606 void *desc; /* virtual address */
607 dma_addr_t dma; /* physical address*/
608 unsigned int size; /* length in bytes */
612 * atl1_buffer is wrapper around a pointer to a socket buffer
613 * so a DMA handle can be stored along with the skb
616 struct sk_buff *skb; /* socket buffer */
617 u16 length; /* rx buffer length */
618 u16 alloced; /* 1 if skb allocated */
622 /* transmit packet descriptor (tpd) ring */
623 struct atl1_tpd_ring {
624 void *desc; /* descriptor ring virtual address */
625 dma_addr_t dma; /* descriptor ring physical address */
626 u16 size; /* descriptor ring length in bytes */
627 u16 count; /* number of descriptors in the ring */
628 u16 hw_idx; /* hardware index */
629 atomic_t next_to_clean;
630 atomic_t next_to_use;
631 struct atl1_buffer *buffer_info;
634 /* receive free descriptor (rfd) ring */
635 struct atl1_rfd_ring {
636 void *desc; /* descriptor ring virtual address */
637 dma_addr_t dma; /* descriptor ring physical address */
638 u16 size; /* descriptor ring length in bytes */
639 u16 count; /* number of descriptors in the ring */
640 atomic_t next_to_use;
642 struct atl1_buffer *buffer_info;
645 /* receive return descriptor (rrd) ring */
646 struct atl1_rrd_ring {
647 void *desc; /* descriptor ring virtual address */
648 dma_addr_t dma; /* descriptor ring physical address */
649 unsigned int size; /* descriptor ring length in bytes */
650 u16 count; /* number of descriptors in the ring */
652 atomic_t next_to_clean;
655 /* coalescing message block (cmb) */
657 struct coals_msg_block *cmb;
661 /* statistics message block (smb) */
663 struct stats_msg_block *smb;
667 /* Statistics counters */
668 struct atl1_sft_stats {
676 u64 rx_length_errors;
680 u64 rx_missed_errors;
683 u64 tx_aborted_errors;
684 u64 tx_window_errors;
685 u64 tx_carrier_errors;
686 u64 tx_pause; /* TX pause frames */
687 u64 excecol; /* TX packets w/ excessive collisions */
688 u64 deffer; /* TX packets deferred */
689 u64 scc; /* packets TX after a single collision */
690 u64 mcc; /* packets TX after multiple collisions */
691 u64 latecol; /* TX packets w/ late collisions */
692 u64 tx_underun; /* TX packets aborted due to TX FIFO underrun
693 * or TRD FIFO underrun */
694 u64 tx_trunc; /* TX packets truncated due to size > MTU */
695 u64 rx_pause; /* num Pause packets received. */
700 /* hardware structure */
703 struct atl1_adapter *back;
704 enum atl1_dma_order dma_ord;
705 enum atl1_dma_rcb rcb_value;
706 enum atl1_dma_req_block dmar_block;
707 enum atl1_dma_req_block dmaw_block;
710 u8 jam_ipg; /* IPG to start JAM for collision based flow
711 * control in half-duplex mode. In units of
713 u8 ipgt; /* Desired back to back inter-packet gap.
714 * The default is 96-bit time */
715 u8 min_ifg; /* Minimum number of IFG to enforce in between
716 * receive frames. Frame gap below such IFP
718 u8 ipgr1; /* 64bit Carrier-Sense window */
719 u8 ipgr2; /* 96-bit IPG window */
720 u8 tpd_burst; /* Number of TPD to prefetch in cache-aligned
721 * burst. Each TPD is 16 bytes long */
722 u8 rfd_burst; /* Number of RFD to prefetch in cache-aligned
723 * burst. Each RFD is 12 bytes long */
725 u8 rrd_burst; /* Threshold number of RRDs that can be retired
726 * in a burst. Each RRD is 16 bytes long */
729 u16 tx_jumbo_task_th;
730 u16 txf_burst; /* Number of data bytes to read in a cache-
731 * aligned burst. Each SRAM entry is 8 bytes */
732 u16 rx_jumbo_th; /* Jumbo packet size for non-VLAN packet. VLAN
733 * packets should add 4 bytes */
735 u16 rrd_ret_timer; /* RRD retirement timer. Decrement by 1 after
736 * every 512ns passes. */
737 u16 lcol; /* Collision Window */
745 u16 autoneg_advertised;
747 u16 mii_autoneg_adv_reg;
748 u16 mii_1000t_ctrl_reg;
758 u8 mac_addr[ETH_ALEN];
759 u8 perm_mac_addr[ETH_ALEN];
764 struct atl1_adapter {
765 struct net_device *netdev;
766 struct pci_dev *pdev;
767 struct net_device_stats net_stats;
768 struct atl1_sft_stats soft_stats;
769 struct vlan_group *vlgrp;
775 struct work_struct tx_timeout_task;
776 struct work_struct link_chg_task;
777 struct work_struct pcie_dma_to_rst_task;
778 struct timer_list watchdog_timer;
779 struct timer_list phy_config_timer;
780 bool phy_timer_pending;
782 /* all descriptor rings' memory */
783 struct atl1_ring_header ring_header;
786 struct atl1_tpd_ring tpd_ring;
790 struct atl1_rfd_ring rfd_ring;
791 struct atl1_rrd_ring rrd_ring;
795 u16 imt; /* interrupt moderator timer (2us resolution) */
796 u16 ict; /* interrupt clear timer (2us resolution */
797 struct mii_if_info mii; /* MII interface info */
799 u32 bd_number; /* board number */