2 * Copyright(c) 2005 - 2006 Attansic Corporation. All rights reserved.
3 * Copyright(c) 2006 - 2007 Chris Snook <csnook@redhat.com>
4 * Copyright(c) 2006 - 2008 Jay Cliburn <jcliburn@gmail.com>
6 * Derived from Intel e1000 driver
7 * Copyright(c) 1999 - 2005 Intel Corporation. All rights reserved.
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms of the GNU General Public License as published by the Free
11 * Software Foundation; either version 2 of the License, or (at your option)
14 * This program is distributed in the hope that it will be useful, but WITHOUT
15 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
16 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
19 * You should have received a copy of the GNU General Public License along with
20 * this program; if not, write to the Free Software Foundation, Inc., 59
21 * Temple Place - Suite 330, Boston, MA 02111-1307, USA.
23 * The full GNU General Public License is included in this distribution in the
24 * file called COPYING.
26 * Contact Information:
27 * Xiong Huang <xiong_huang@attansic.com>
28 * Attansic Technology Corp. 3F 147, Xianzheng 9th Road, Zhubei,
29 * Xinzhu 302, TAIWAN, REPUBLIC OF CHINA
31 * Chris Snook <csnook@redhat.com>
32 * Jay Cliburn <jcliburn@gmail.com>
34 * This version is adapted from the Attansic reference driver for
35 * inclusion in the Linux kernel. It is currently under heavy development.
36 * A very incomplete list of things that need to be dealt with:
39 * Add more ethtool functions.
40 * Fix abstruse irq enable/disable condition described here:
41 * http://marc.theaimsgroup.com/?l=linux-netdev&m=116398508500553&w=2
47 * interrupt coalescing
51 #include <asm/atomic.h>
52 #include <asm/byteorder.h>
54 #include <linux/compiler.h>
55 #include <linux/crc32.h>
56 #include <linux/delay.h>
57 #include <linux/dma-mapping.h>
58 #include <linux/etherdevice.h>
59 #include <linux/hardirq.h>
60 #include <linux/if_ether.h>
61 #include <linux/if_vlan.h>
63 #include <linux/interrupt.h>
65 #include <linux/irqflags.h>
66 #include <linux/irqreturn.h>
67 #include <linux/jiffies.h>
68 #include <linux/mii.h>
69 #include <linux/module.h>
70 #include <linux/moduleparam.h>
71 #include <linux/net.h>
72 #include <linux/netdevice.h>
73 #include <linux/pci.h>
74 #include <linux/pci_ids.h>
76 #include <linux/skbuff.h>
77 #include <linux/slab.h>
78 #include <linux/spinlock.h>
79 #include <linux/string.h>
80 #include <linux/tcp.h>
81 #include <linux/timer.h>
82 #include <linux/types.h>
83 #include <linux/workqueue.h>
85 #include <net/checksum.h>
89 /* Temporary hack for merging atl1 and atl2 */
93 * This is the only thing that needs to be changed to adjust the
94 * maximum number of ports that the driver can manage.
96 #define ATL1_MAX_NIC 4
98 #define OPTION_UNSET -1
99 #define OPTION_DISABLED 0
100 #define OPTION_ENABLED 1
102 #define ATL1_PARAM_INIT { [0 ... ATL1_MAX_NIC] = OPTION_UNSET }
105 * Interrupt Moderate Timer in units of 2 us
107 * Valid Range: 10-65535
109 * Default Value: 100 (200us)
111 static int __devinitdata int_mod_timer[ATL1_MAX_NIC+1] = ATL1_PARAM_INIT;
112 static int num_int_mod_timer;
113 module_param_array_named(int_mod_timer, int_mod_timer, int,
114 &num_int_mod_timer, 0);
115 MODULE_PARM_DESC(int_mod_timer, "Interrupt moderator timer");
117 #define DEFAULT_INT_MOD_CNT 100 /* 200us */
118 #define MAX_INT_MOD_CNT 65000
119 #define MIN_INT_MOD_CNT 50
122 enum { enable_option, range_option, list_option } type;
127 struct { /* range_option info */
131 struct { /* list_option info */
133 struct atl1_opt_list {
141 static int __devinit atl1_validate_option(int *value, struct atl1_option *opt,
142 struct pci_dev *pdev)
144 if (*value == OPTION_UNSET) {
153 dev_info(&pdev->dev, "%s enabled\n", opt->name);
155 case OPTION_DISABLED:
156 dev_info(&pdev->dev, "%s disabled\n", opt->name);
161 if (*value >= opt->arg.r.min && *value <= opt->arg.r.max) {
162 dev_info(&pdev->dev, "%s set to %i\n", opt->name,
169 struct atl1_opt_list *ent;
171 for (i = 0; i < opt->arg.l.nr; i++) {
172 ent = &opt->arg.l.p[i];
173 if (*value == ent->i) {
174 if (ent->str[0] != '\0')
175 dev_info(&pdev->dev, "%s\n",
187 dev_info(&pdev->dev, "invalid %s specified (%i) %s\n",
188 opt->name, *value, opt->err);
194 * atl1_check_options - Range Checking for Command Line Parameters
195 * @adapter: board private structure
197 * This routine checks all command line parameters for valid user
198 * input. If an invalid value is given, or if no user specified
199 * value exists, a default value is used. The final value is stored
200 * in a variable in the adapter structure.
202 void __devinit atl1_check_options(struct atl1_adapter *adapter)
204 struct pci_dev *pdev = adapter->pdev;
205 int bd = adapter->bd_number;
206 if (bd >= ATL1_MAX_NIC) {
207 dev_notice(&pdev->dev, "no configuration for board#%i\n", bd);
208 dev_notice(&pdev->dev, "using defaults for all values\n");
210 { /* Interrupt Moderate Timer */
211 struct atl1_option opt = {
212 .type = range_option,
213 .name = "Interrupt Moderator Timer",
214 .err = "using default of "
215 __MODULE_STRING(DEFAULT_INT_MOD_CNT),
216 .def = DEFAULT_INT_MOD_CNT,
217 .arg = {.r = {.min = MIN_INT_MOD_CNT,
218 .max = MAX_INT_MOD_CNT} }
221 if (num_int_mod_timer > bd) {
222 val = int_mod_timer[bd];
223 atl1_validate_option(&val, &opt, pdev);
224 adapter->imt = (u16) val;
226 adapter->imt = (u16) (opt.def);
231 * atl1_pci_tbl - PCI Device ID Table
233 static const struct pci_device_id atl1_pci_tbl[] = {
234 {PCI_DEVICE(PCI_VENDOR_ID_ATTANSIC, PCI_DEVICE_ID_ATTANSIC_L1)},
235 /* required last entry */
238 MODULE_DEVICE_TABLE(pci, atl1_pci_tbl);
240 static const u32 atl1_default_msg = NETIF_MSG_DRV | NETIF_MSG_PROBE |
241 NETIF_MSG_LINK | NETIF_MSG_TIMER | NETIF_MSG_IFDOWN | NETIF_MSG_IFUP;
243 static int debug = -1;
244 module_param(debug, int, 0);
245 MODULE_PARM_DESC(debug, "Message level (0=none,...,16=all)");
248 * Reset the transmit and receive units; mask and clear all interrupts.
249 * hw - Struct containing variables accessed by shared code
250 * return : 0 or idle status (if error)
252 static s32 atl1_reset_hw(struct atl1_hw *hw)
254 struct pci_dev *pdev = hw->back->pdev;
255 struct atl1_adapter *adapter = hw->back;
260 * Clear Interrupt mask to stop board from generating
261 * interrupts & Clear any pending interrupt events
264 * iowrite32(0, hw->hw_addr + REG_IMR);
265 * iowrite32(0xffffffff, hw->hw_addr + REG_ISR);
269 * Issue Soft Reset to the MAC. This will reset the chip's
270 * transmit, receive, DMA. It will not effect
271 * the current PCI configuration. The global reset bit is self-
272 * clearing, and should clear within a microsecond.
274 iowrite32(MASTER_CTRL_SOFT_RST, hw->hw_addr + REG_MASTER_CTRL);
275 ioread32(hw->hw_addr + REG_MASTER_CTRL);
277 iowrite16(1, hw->hw_addr + REG_PHY_ENABLE);
278 ioread16(hw->hw_addr + REG_PHY_ENABLE);
280 /* delay about 1ms */
283 /* Wait at least 10ms for All module to be Idle */
284 for (i = 0; i < 10; i++) {
285 icr = ioread32(hw->hw_addr + REG_IDLE_STATUS);
290 /* FIXME: still the right way to do this? */
295 if (netif_msg_hw(adapter))
296 dev_dbg(&pdev->dev, "ICR = 0x%x\n", icr);
303 /* function about EEPROM
306 * return 0 if eeprom exist
308 static int atl1_check_eeprom_exist(struct atl1_hw *hw)
311 value = ioread32(hw->hw_addr + REG_SPI_FLASH_CTRL);
312 if (value & SPI_FLASH_CTRL_EN_VPD) {
313 value &= ~SPI_FLASH_CTRL_EN_VPD;
314 iowrite32(value, hw->hw_addr + REG_SPI_FLASH_CTRL);
317 value = ioread16(hw->hw_addr + REG_PCIE_CAP_LIST);
318 return ((value & 0xFF00) == 0x6C00) ? 0 : 1;
321 static bool atl1_read_eeprom(struct atl1_hw *hw, u32 offset, u32 *p_value)
327 /* address do not align */
330 iowrite32(0, hw->hw_addr + REG_VPD_DATA);
331 control = (offset & VPD_CAP_VPD_ADDR_MASK) << VPD_CAP_VPD_ADDR_SHIFT;
332 iowrite32(control, hw->hw_addr + REG_VPD_CAP);
333 ioread32(hw->hw_addr + REG_VPD_CAP);
335 for (i = 0; i < 10; i++) {
337 control = ioread32(hw->hw_addr + REG_VPD_CAP);
338 if (control & VPD_CAP_VPD_FLAG)
341 if (control & VPD_CAP_VPD_FLAG) {
342 *p_value = ioread32(hw->hw_addr + REG_VPD_DATA);
350 * Reads the value from a PHY register
351 * hw - Struct containing variables accessed by shared code
352 * reg_addr - address of the PHY register to read
354 s32 atl1_read_phy_reg(struct atl1_hw *hw, u16 reg_addr, u16 *phy_data)
359 val = ((u32) (reg_addr & MDIO_REG_ADDR_MASK)) << MDIO_REG_ADDR_SHIFT |
360 MDIO_START | MDIO_SUP_PREAMBLE | MDIO_RW | MDIO_CLK_25_4 <<
362 iowrite32(val, hw->hw_addr + REG_MDIO_CTRL);
363 ioread32(hw->hw_addr + REG_MDIO_CTRL);
365 for (i = 0; i < MDIO_WAIT_TIMES; i++) {
367 val = ioread32(hw->hw_addr + REG_MDIO_CTRL);
368 if (!(val & (MDIO_START | MDIO_BUSY)))
371 if (!(val & (MDIO_START | MDIO_BUSY))) {
372 *phy_data = (u16) val;
378 #define CUSTOM_SPI_CS_SETUP 2
379 #define CUSTOM_SPI_CLK_HI 2
380 #define CUSTOM_SPI_CLK_LO 2
381 #define CUSTOM_SPI_CS_HOLD 2
382 #define CUSTOM_SPI_CS_HI 3
384 static bool atl1_spi_read(struct atl1_hw *hw, u32 addr, u32 *buf)
389 iowrite32(0, hw->hw_addr + REG_SPI_DATA);
390 iowrite32(addr, hw->hw_addr + REG_SPI_ADDR);
392 value = SPI_FLASH_CTRL_WAIT_READY |
393 (CUSTOM_SPI_CS_SETUP & SPI_FLASH_CTRL_CS_SETUP_MASK) <<
394 SPI_FLASH_CTRL_CS_SETUP_SHIFT | (CUSTOM_SPI_CLK_HI &
395 SPI_FLASH_CTRL_CLK_HI_MASK) <<
396 SPI_FLASH_CTRL_CLK_HI_SHIFT | (CUSTOM_SPI_CLK_LO &
397 SPI_FLASH_CTRL_CLK_LO_MASK) <<
398 SPI_FLASH_CTRL_CLK_LO_SHIFT | (CUSTOM_SPI_CS_HOLD &
399 SPI_FLASH_CTRL_CS_HOLD_MASK) <<
400 SPI_FLASH_CTRL_CS_HOLD_SHIFT | (CUSTOM_SPI_CS_HI &
401 SPI_FLASH_CTRL_CS_HI_MASK) <<
402 SPI_FLASH_CTRL_CS_HI_SHIFT | (1 & SPI_FLASH_CTRL_INS_MASK) <<
403 SPI_FLASH_CTRL_INS_SHIFT;
405 iowrite32(value, hw->hw_addr + REG_SPI_FLASH_CTRL);
407 value |= SPI_FLASH_CTRL_START;
408 iowrite32(value, hw->hw_addr + REG_SPI_FLASH_CTRL);
409 ioread32(hw->hw_addr + REG_SPI_FLASH_CTRL);
411 for (i = 0; i < 10; i++) {
413 value = ioread32(hw->hw_addr + REG_SPI_FLASH_CTRL);
414 if (!(value & SPI_FLASH_CTRL_START))
418 if (value & SPI_FLASH_CTRL_START)
421 *buf = ioread32(hw->hw_addr + REG_SPI_DATA);
427 * get_permanent_address
428 * return 0 if get valid mac address,
430 static int atl1_get_permanent_address(struct atl1_hw *hw)
435 u8 eth_addr[ETH_ALEN];
438 if (is_valid_ether_addr(hw->perm_mac_addr))
442 addr[0] = addr[1] = 0;
444 if (!atl1_check_eeprom_exist(hw)) {
447 /* Read out all EEPROM content */
450 if (atl1_read_eeprom(hw, i + 0x100, &control)) {
452 if (reg == REG_MAC_STA_ADDR)
454 else if (reg == (REG_MAC_STA_ADDR + 4))
457 } else if ((control & 0xff) == 0x5A) {
459 reg = (u16) (control >> 16);
468 *(u32 *) ð_addr[2] = swab32(addr[0]);
469 *(u16 *) ð_addr[0] = swab16(*(u16 *) &addr[1]);
470 if (is_valid_ether_addr(eth_addr)) {
471 memcpy(hw->perm_mac_addr, eth_addr, ETH_ALEN);
477 /* see if SPI FLAGS exist ? */
478 addr[0] = addr[1] = 0;
483 if (atl1_spi_read(hw, i + 0x1f000, &control)) {
485 if (reg == REG_MAC_STA_ADDR)
487 else if (reg == (REG_MAC_STA_ADDR + 4))
490 } else if ((control & 0xff) == 0x5A) {
492 reg = (u16) (control >> 16);
502 *(u32 *) ð_addr[2] = swab32(addr[0]);
503 *(u16 *) ð_addr[0] = swab16(*(u16 *) &addr[1]);
504 if (is_valid_ether_addr(eth_addr)) {
505 memcpy(hw->perm_mac_addr, eth_addr, ETH_ALEN);
510 * On some motherboards, the MAC address is written by the
511 * BIOS directly to the MAC register during POST, and is
512 * not stored in eeprom. If all else thus far has failed
513 * to fetch the permanent MAC address, try reading it directly.
515 addr[0] = ioread32(hw->hw_addr + REG_MAC_STA_ADDR);
516 addr[1] = ioread16(hw->hw_addr + (REG_MAC_STA_ADDR + 4));
517 *(u32 *) ð_addr[2] = swab32(addr[0]);
518 *(u16 *) ð_addr[0] = swab16(*(u16 *) &addr[1]);
519 if (is_valid_ether_addr(eth_addr)) {
520 memcpy(hw->perm_mac_addr, eth_addr, ETH_ALEN);
528 * Reads the adapter's MAC address from the EEPROM
529 * hw - Struct containing variables accessed by shared code
531 s32 atl1_read_mac_addr(struct atl1_hw *hw)
535 if (atl1_get_permanent_address(hw))
536 random_ether_addr(hw->perm_mac_addr);
538 for (i = 0; i < ETH_ALEN; i++)
539 hw->mac_addr[i] = hw->perm_mac_addr[i];
544 * Hashes an address to determine its location in the multicast table
545 * hw - Struct containing variables accessed by shared code
546 * mc_addr - the multicast address to hash
550 * set hash value for a multicast address
551 * hash calcu processing :
552 * 1. calcu 32bit CRC for multicast address
553 * 2. reverse crc with MSB to LSB
555 u32 atl1_hash_mc_addr(struct atl1_hw *hw, u8 *mc_addr)
557 u32 crc32, value = 0;
560 crc32 = ether_crc_le(6, mc_addr);
561 for (i = 0; i < 32; i++)
562 value |= (((crc32 >> i) & 1) << (31 - i));
568 * Sets the bit in the multicast table corresponding to the hash value.
569 * hw - Struct containing variables accessed by shared code
570 * hash_value - Multicast address hash value
572 void atl1_hash_set(struct atl1_hw *hw, u32 hash_value)
574 u32 hash_bit, hash_reg;
578 * The HASH Table is a register array of 2 32-bit registers.
579 * It is treated like an array of 64 bits. We want to set
580 * bit BitArray[hash_value]. So we figure out what register
581 * the bit is in, read it, OR in the new bit, then write
582 * back the new value. The register is determined by the
583 * upper 7 bits of the hash value and the bit within that
584 * register are determined by the lower 5 bits of the value.
586 hash_reg = (hash_value >> 31) & 0x1;
587 hash_bit = (hash_value >> 26) & 0x1F;
588 mta = ioread32((hw->hw_addr + REG_RX_HASH_TABLE) + (hash_reg << 2));
589 mta |= (1 << hash_bit);
590 iowrite32(mta, (hw->hw_addr + REG_RX_HASH_TABLE) + (hash_reg << 2));
594 * Writes a value to a PHY register
595 * hw - Struct containing variables accessed by shared code
596 * reg_addr - address of the PHY register to write
597 * data - data to write to the PHY
599 static s32 atl1_write_phy_reg(struct atl1_hw *hw, u32 reg_addr, u16 phy_data)
604 val = ((u32) (phy_data & MDIO_DATA_MASK)) << MDIO_DATA_SHIFT |
605 (reg_addr & MDIO_REG_ADDR_MASK) << MDIO_REG_ADDR_SHIFT |
607 MDIO_START | MDIO_CLK_25_4 << MDIO_CLK_SEL_SHIFT;
608 iowrite32(val, hw->hw_addr + REG_MDIO_CTRL);
609 ioread32(hw->hw_addr + REG_MDIO_CTRL);
611 for (i = 0; i < MDIO_WAIT_TIMES; i++) {
613 val = ioread32(hw->hw_addr + REG_MDIO_CTRL);
614 if (!(val & (MDIO_START | MDIO_BUSY)))
618 if (!(val & (MDIO_START | MDIO_BUSY)))
625 * Make L001's PHY out of Power Saving State (bug)
626 * hw - Struct containing variables accessed by shared code
627 * when power on, L001's PHY always on Power saving State
628 * (Gigabit Link forbidden)
630 static s32 atl1_phy_leave_power_saving(struct atl1_hw *hw)
633 ret = atl1_write_phy_reg(hw, 29, 0x0029);
636 return atl1_write_phy_reg(hw, 30, 0);
640 * Force the PHY into power saving mode using vendor magic.
643 static void atl1_phy_enter_power_saving(struct atl1_hw *hw)
645 atl1_write_phy_reg(hw, MII_DBG_ADDR, 0);
646 atl1_write_phy_reg(hw, MII_DBG_DATA, 0x124E);
647 atl1_write_phy_reg(hw, MII_DBG_ADDR, 2);
648 atl1_write_phy_reg(hw, MII_DBG_DATA, 0x3000);
649 atl1_write_phy_reg(hw, MII_DBG_ADDR, 3);
650 atl1_write_phy_reg(hw, MII_DBG_DATA, 0);
656 * Resets the PHY and make all config validate
657 * hw - Struct containing variables accessed by shared code
659 * Sets bit 15 and 12 of the MII Control regiser (for F001 bug)
661 static s32 atl1_phy_reset(struct atl1_hw *hw)
663 struct pci_dev *pdev = hw->back->pdev;
664 struct atl1_adapter *adapter = hw->back;
668 if (hw->media_type == MEDIA_TYPE_AUTO_SENSOR ||
669 hw->media_type == MEDIA_TYPE_1000M_FULL)
670 phy_data = MII_CR_RESET | MII_CR_AUTO_NEG_EN;
672 switch (hw->media_type) {
673 case MEDIA_TYPE_100M_FULL:
675 MII_CR_FULL_DUPLEX | MII_CR_SPEED_100 |
678 case MEDIA_TYPE_100M_HALF:
679 phy_data = MII_CR_SPEED_100 | MII_CR_RESET;
681 case MEDIA_TYPE_10M_FULL:
683 MII_CR_FULL_DUPLEX | MII_CR_SPEED_10 | MII_CR_RESET;
686 /* MEDIA_TYPE_10M_HALF: */
687 phy_data = MII_CR_SPEED_10 | MII_CR_RESET;
692 ret_val = atl1_write_phy_reg(hw, MII_BMCR, phy_data);
696 /* pcie serdes link may be down! */
697 if (netif_msg_hw(adapter))
698 dev_dbg(&pdev->dev, "pcie phy link down\n");
700 for (i = 0; i < 25; i++) {
702 val = ioread32(hw->hw_addr + REG_MDIO_CTRL);
703 if (!(val & (MDIO_START | MDIO_BUSY)))
707 if ((val & (MDIO_START | MDIO_BUSY)) != 0) {
708 if (netif_msg_hw(adapter))
710 "pcie link down at least 25ms\n");
718 * Configures PHY autoneg and flow control advertisement settings
719 * hw - Struct containing variables accessed by shared code
721 static s32 atl1_phy_setup_autoneg_adv(struct atl1_hw *hw)
724 s16 mii_autoneg_adv_reg;
725 s16 mii_1000t_ctrl_reg;
727 /* Read the MII Auto-Neg Advertisement Register (Address 4). */
728 mii_autoneg_adv_reg = MII_AR_DEFAULT_CAP_MASK;
730 /* Read the MII 1000Base-T Control Register (Address 9). */
731 mii_1000t_ctrl_reg = MII_ATLX_CR_1000T_DEFAULT_CAP_MASK;
734 * First we clear all the 10/100 mb speed bits in the Auto-Neg
735 * Advertisement Register (Address 4) and the 1000 mb speed bits in
736 * the 1000Base-T Control Register (Address 9).
738 mii_autoneg_adv_reg &= ~MII_AR_SPEED_MASK;
739 mii_1000t_ctrl_reg &= ~MII_ATLX_CR_1000T_SPEED_MASK;
742 * Need to parse media_type and set up
743 * the appropriate PHY registers.
745 switch (hw->media_type) {
746 case MEDIA_TYPE_AUTO_SENSOR:
747 mii_autoneg_adv_reg |= (MII_AR_10T_HD_CAPS |
749 MII_AR_100TX_HD_CAPS |
750 MII_AR_100TX_FD_CAPS);
751 mii_1000t_ctrl_reg |= MII_ATLX_CR_1000T_FD_CAPS;
754 case MEDIA_TYPE_1000M_FULL:
755 mii_1000t_ctrl_reg |= MII_ATLX_CR_1000T_FD_CAPS;
758 case MEDIA_TYPE_100M_FULL:
759 mii_autoneg_adv_reg |= MII_AR_100TX_FD_CAPS;
762 case MEDIA_TYPE_100M_HALF:
763 mii_autoneg_adv_reg |= MII_AR_100TX_HD_CAPS;
766 case MEDIA_TYPE_10M_FULL:
767 mii_autoneg_adv_reg |= MII_AR_10T_FD_CAPS;
771 mii_autoneg_adv_reg |= MII_AR_10T_HD_CAPS;
775 /* flow control fixed to enable all */
776 mii_autoneg_adv_reg |= (MII_AR_ASM_DIR | MII_AR_PAUSE);
778 hw->mii_autoneg_adv_reg = mii_autoneg_adv_reg;
779 hw->mii_1000t_ctrl_reg = mii_1000t_ctrl_reg;
781 ret_val = atl1_write_phy_reg(hw, MII_ADVERTISE, mii_autoneg_adv_reg);
785 ret_val = atl1_write_phy_reg(hw, MII_ATLX_CR, mii_1000t_ctrl_reg);
793 * Configures link settings.
794 * hw - Struct containing variables accessed by shared code
795 * Assumes the hardware has previously been reset and the
796 * transmitter and receiver are not enabled.
798 static s32 atl1_setup_link(struct atl1_hw *hw)
800 struct pci_dev *pdev = hw->back->pdev;
801 struct atl1_adapter *adapter = hw->back;
806 * PHY will advertise value(s) parsed from
807 * autoneg_advertised and fc
808 * no matter what autoneg is , We will not wait link result.
810 ret_val = atl1_phy_setup_autoneg_adv(hw);
812 if (netif_msg_link(adapter))
814 "error setting up autonegotiation\n");
817 /* SW.Reset , En-Auto-Neg if needed */
818 ret_val = atl1_phy_reset(hw);
820 if (netif_msg_link(adapter))
821 dev_dbg(&pdev->dev, "error resetting phy\n");
824 hw->phy_configured = true;
828 static void atl1_init_flash_opcode(struct atl1_hw *hw)
830 if (hw->flash_vendor >= ARRAY_SIZE(flash_table))
832 hw->flash_vendor = 0;
835 iowrite8(flash_table[hw->flash_vendor].cmd_program,
836 hw->hw_addr + REG_SPI_FLASH_OP_PROGRAM);
837 iowrite8(flash_table[hw->flash_vendor].cmd_sector_erase,
838 hw->hw_addr + REG_SPI_FLASH_OP_SC_ERASE);
839 iowrite8(flash_table[hw->flash_vendor].cmd_chip_erase,
840 hw->hw_addr + REG_SPI_FLASH_OP_CHIP_ERASE);
841 iowrite8(flash_table[hw->flash_vendor].cmd_rdid,
842 hw->hw_addr + REG_SPI_FLASH_OP_RDID);
843 iowrite8(flash_table[hw->flash_vendor].cmd_wren,
844 hw->hw_addr + REG_SPI_FLASH_OP_WREN);
845 iowrite8(flash_table[hw->flash_vendor].cmd_rdsr,
846 hw->hw_addr + REG_SPI_FLASH_OP_RDSR);
847 iowrite8(flash_table[hw->flash_vendor].cmd_wrsr,
848 hw->hw_addr + REG_SPI_FLASH_OP_WRSR);
849 iowrite8(flash_table[hw->flash_vendor].cmd_read,
850 hw->hw_addr + REG_SPI_FLASH_OP_READ);
854 * Performs basic configuration of the adapter.
855 * hw - Struct containing variables accessed by shared code
856 * Assumes that the controller has previously been reset and is in a
857 * post-reset uninitialized state. Initializes multicast table,
858 * and Calls routines to setup link
859 * Leaves the transmit and receive units disabled and uninitialized.
861 static s32 atl1_init_hw(struct atl1_hw *hw)
865 /* Zero out the Multicast HASH table */
866 iowrite32(0, hw->hw_addr + REG_RX_HASH_TABLE);
867 /* clear the old settings from the multicast hash table */
868 iowrite32(0, (hw->hw_addr + REG_RX_HASH_TABLE) + (1 << 2));
870 atl1_init_flash_opcode(hw);
872 if (!hw->phy_configured) {
873 /* enable GPHY LinkChange Interrrupt */
874 ret_val = atl1_write_phy_reg(hw, 18, 0xC00);
877 /* make PHY out of power-saving state */
878 ret_val = atl1_phy_leave_power_saving(hw);
881 /* Call a subroutine to configure the link */
882 ret_val = atl1_setup_link(hw);
888 * Detects the current speed and duplex settings of the hardware.
889 * hw - Struct containing variables accessed by shared code
890 * speed - Speed of the connection
891 * duplex - Duplex setting of the connection
893 static s32 atl1_get_speed_and_duplex(struct atl1_hw *hw, u16 *speed, u16 *duplex)
895 struct pci_dev *pdev = hw->back->pdev;
896 struct atl1_adapter *adapter = hw->back;
900 /* ; --- Read PHY Specific Status Register (17) */
901 ret_val = atl1_read_phy_reg(hw, MII_ATLX_PSSR, &phy_data);
905 if (!(phy_data & MII_ATLX_PSSR_SPD_DPLX_RESOLVED))
906 return ATLX_ERR_PHY_RES;
908 switch (phy_data & MII_ATLX_PSSR_SPEED) {
909 case MII_ATLX_PSSR_1000MBS:
912 case MII_ATLX_PSSR_100MBS:
915 case MII_ATLX_PSSR_10MBS:
919 if (netif_msg_hw(adapter))
920 dev_dbg(&pdev->dev, "error getting speed\n");
921 return ATLX_ERR_PHY_SPEED;
924 if (phy_data & MII_ATLX_PSSR_DPLX)
925 *duplex = FULL_DUPLEX;
927 *duplex = HALF_DUPLEX;
932 void atl1_set_mac_addr(struct atl1_hw *hw)
937 * 0: 6AF600DC 1: 000B
940 value = (((u32) hw->mac_addr[2]) << 24) |
941 (((u32) hw->mac_addr[3]) << 16) |
942 (((u32) hw->mac_addr[4]) << 8) | (((u32) hw->mac_addr[5]));
943 iowrite32(value, hw->hw_addr + REG_MAC_STA_ADDR);
945 value = (((u32) hw->mac_addr[0]) << 8) | (((u32) hw->mac_addr[1]));
946 iowrite32(value, (hw->hw_addr + REG_MAC_STA_ADDR) + (1 << 2));
950 * atl1_sw_init - Initialize general software structures (struct atl1_adapter)
951 * @adapter: board private structure to initialize
953 * atl1_sw_init initializes the Adapter private data structure.
954 * Fields are initialized based on PCI device information and
955 * OS network device settings (MTU size).
957 static int __devinit atl1_sw_init(struct atl1_adapter *adapter)
959 struct atl1_hw *hw = &adapter->hw;
960 struct net_device *netdev = adapter->netdev;
962 hw->max_frame_size = netdev->mtu + ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN;
963 hw->min_frame_size = ETH_ZLEN + ETH_FCS_LEN;
966 adapter->rx_buffer_len = (hw->max_frame_size + 7) & ~7;
967 adapter->ict = 50000; /* 100ms */
968 adapter->link_speed = SPEED_0; /* hardware init */
969 adapter->link_duplex = FULL_DUPLEX;
971 hw->phy_configured = false;
972 hw->preamble_len = 7;
982 hw->rfd_fetch_gap = 1;
983 hw->rx_jumbo_th = adapter->rx_buffer_len / 8;
984 hw->rx_jumbo_lkah = 1;
985 hw->rrd_ret_timer = 16;
987 hw->tpd_fetch_th = 16;
988 hw->txf_burst = 0x100;
989 hw->tx_jumbo_task_th = (hw->max_frame_size + 7) >> 3;
990 hw->tpd_fetch_gap = 1;
991 hw->rcb_value = atl1_rcb_64;
992 hw->dma_ord = atl1_dma_ord_enh;
993 hw->dmar_block = atl1_dma_req_256;
994 hw->dmaw_block = atl1_dma_req_256;
997 hw->cmb_rx_timer = 1; /* about 2us */
998 hw->cmb_tx_timer = 1; /* about 2us */
999 hw->smb_timer = 100000; /* about 200ms */
1001 spin_lock_init(&adapter->lock);
1002 spin_lock_init(&adapter->mb_lock);
1007 static int mdio_read(struct net_device *netdev, int phy_id, int reg_num)
1009 struct atl1_adapter *adapter = netdev_priv(netdev);
1012 atl1_read_phy_reg(&adapter->hw, reg_num & 0x1f, &result);
1017 static void mdio_write(struct net_device *netdev, int phy_id, int reg_num,
1020 struct atl1_adapter *adapter = netdev_priv(netdev);
1022 atl1_write_phy_reg(&adapter->hw, reg_num, val);
1031 static int atl1_mii_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
1033 struct atl1_adapter *adapter = netdev_priv(netdev);
1034 unsigned long flags;
1037 if (!netif_running(netdev))
1040 spin_lock_irqsave(&adapter->lock, flags);
1041 retval = generic_mii_ioctl(&adapter->mii, if_mii(ifr), cmd, NULL);
1042 spin_unlock_irqrestore(&adapter->lock, flags);
1048 * atl1_setup_mem_resources - allocate Tx / RX descriptor resources
1049 * @adapter: board private structure
1051 * Return 0 on success, negative on failure
1053 static s32 atl1_setup_ring_resources(struct atl1_adapter *adapter)
1055 struct atl1_tpd_ring *tpd_ring = &adapter->tpd_ring;
1056 struct atl1_rfd_ring *rfd_ring = &adapter->rfd_ring;
1057 struct atl1_rrd_ring *rrd_ring = &adapter->rrd_ring;
1058 struct atl1_ring_header *ring_header = &adapter->ring_header;
1059 struct pci_dev *pdev = adapter->pdev;
1063 size = sizeof(struct atl1_buffer) * (tpd_ring->count + rfd_ring->count);
1064 tpd_ring->buffer_info = kzalloc(size, GFP_KERNEL);
1065 if (unlikely(!tpd_ring->buffer_info)) {
1066 if (netif_msg_drv(adapter))
1067 dev_err(&pdev->dev, "kzalloc failed , size = D%d\n",
1071 rfd_ring->buffer_info =
1072 (struct atl1_buffer *)(tpd_ring->buffer_info + tpd_ring->count);
1075 * real ring DMA buffer
1076 * each ring/block may need up to 8 bytes for alignment, hence the
1077 * additional 40 bytes tacked onto the end.
1079 ring_header->size = size =
1080 sizeof(struct tx_packet_desc) * tpd_ring->count
1081 + sizeof(struct rx_free_desc) * rfd_ring->count
1082 + sizeof(struct rx_return_desc) * rrd_ring->count
1083 + sizeof(struct coals_msg_block)
1084 + sizeof(struct stats_msg_block)
1087 ring_header->desc = pci_alloc_consistent(pdev, ring_header->size,
1089 if (unlikely(!ring_header->desc)) {
1090 if (netif_msg_drv(adapter))
1091 dev_err(&pdev->dev, "pci_alloc_consistent failed\n");
1095 memset(ring_header->desc, 0, ring_header->size);
1098 tpd_ring->dma = ring_header->dma;
1099 offset = (tpd_ring->dma & 0x7) ? (8 - (ring_header->dma & 0x7)) : 0;
1100 tpd_ring->dma += offset;
1101 tpd_ring->desc = (u8 *) ring_header->desc + offset;
1102 tpd_ring->size = sizeof(struct tx_packet_desc) * tpd_ring->count;
1105 rfd_ring->dma = tpd_ring->dma + tpd_ring->size;
1106 offset = (rfd_ring->dma & 0x7) ? (8 - (rfd_ring->dma & 0x7)) : 0;
1107 rfd_ring->dma += offset;
1108 rfd_ring->desc = (u8 *) tpd_ring->desc + (tpd_ring->size + offset);
1109 rfd_ring->size = sizeof(struct rx_free_desc) * rfd_ring->count;
1113 rrd_ring->dma = rfd_ring->dma + rfd_ring->size;
1114 offset = (rrd_ring->dma & 0x7) ? (8 - (rrd_ring->dma & 0x7)) : 0;
1115 rrd_ring->dma += offset;
1116 rrd_ring->desc = (u8 *) rfd_ring->desc + (rfd_ring->size + offset);
1117 rrd_ring->size = sizeof(struct rx_return_desc) * rrd_ring->count;
1121 adapter->cmb.dma = rrd_ring->dma + rrd_ring->size;
1122 offset = (adapter->cmb.dma & 0x7) ? (8 - (adapter->cmb.dma & 0x7)) : 0;
1123 adapter->cmb.dma += offset;
1124 adapter->cmb.cmb = (struct coals_msg_block *)
1125 ((u8 *) rrd_ring->desc + (rrd_ring->size + offset));
1128 adapter->smb.dma = adapter->cmb.dma + sizeof(struct coals_msg_block);
1129 offset = (adapter->smb.dma & 0x7) ? (8 - (adapter->smb.dma & 0x7)) : 0;
1130 adapter->smb.dma += offset;
1131 adapter->smb.smb = (struct stats_msg_block *)
1132 ((u8 *) adapter->cmb.cmb +
1133 (sizeof(struct coals_msg_block) + offset));
1138 kfree(tpd_ring->buffer_info);
1142 static void atl1_init_ring_ptrs(struct atl1_adapter *adapter)
1144 struct atl1_tpd_ring *tpd_ring = &adapter->tpd_ring;
1145 struct atl1_rfd_ring *rfd_ring = &adapter->rfd_ring;
1146 struct atl1_rrd_ring *rrd_ring = &adapter->rrd_ring;
1148 atomic_set(&tpd_ring->next_to_use, 0);
1149 atomic_set(&tpd_ring->next_to_clean, 0);
1151 rfd_ring->next_to_clean = 0;
1152 atomic_set(&rfd_ring->next_to_use, 0);
1154 rrd_ring->next_to_use = 0;
1155 atomic_set(&rrd_ring->next_to_clean, 0);
1159 * atl1_clean_rx_ring - Free RFD Buffers
1160 * @adapter: board private structure
1162 static void atl1_clean_rx_ring(struct atl1_adapter *adapter)
1164 struct atl1_rfd_ring *rfd_ring = &adapter->rfd_ring;
1165 struct atl1_rrd_ring *rrd_ring = &adapter->rrd_ring;
1166 struct atl1_buffer *buffer_info;
1167 struct pci_dev *pdev = adapter->pdev;
1171 /* Free all the Rx ring sk_buffs */
1172 for (i = 0; i < rfd_ring->count; i++) {
1173 buffer_info = &rfd_ring->buffer_info[i];
1174 if (buffer_info->dma) {
1175 pci_unmap_page(pdev, buffer_info->dma,
1176 buffer_info->length, PCI_DMA_FROMDEVICE);
1177 buffer_info->dma = 0;
1179 if (buffer_info->skb) {
1180 dev_kfree_skb(buffer_info->skb);
1181 buffer_info->skb = NULL;
1185 size = sizeof(struct atl1_buffer) * rfd_ring->count;
1186 memset(rfd_ring->buffer_info, 0, size);
1188 /* Zero out the descriptor ring */
1189 memset(rfd_ring->desc, 0, rfd_ring->size);
1191 rfd_ring->next_to_clean = 0;
1192 atomic_set(&rfd_ring->next_to_use, 0);
1194 rrd_ring->next_to_use = 0;
1195 atomic_set(&rrd_ring->next_to_clean, 0);
1199 * atl1_clean_tx_ring - Free Tx Buffers
1200 * @adapter: board private structure
1202 static void atl1_clean_tx_ring(struct atl1_adapter *adapter)
1204 struct atl1_tpd_ring *tpd_ring = &adapter->tpd_ring;
1205 struct atl1_buffer *buffer_info;
1206 struct pci_dev *pdev = adapter->pdev;
1210 /* Free all the Tx ring sk_buffs */
1211 for (i = 0; i < tpd_ring->count; i++) {
1212 buffer_info = &tpd_ring->buffer_info[i];
1213 if (buffer_info->dma) {
1214 pci_unmap_page(pdev, buffer_info->dma,
1215 buffer_info->length, PCI_DMA_TODEVICE);
1216 buffer_info->dma = 0;
1220 for (i = 0; i < tpd_ring->count; i++) {
1221 buffer_info = &tpd_ring->buffer_info[i];
1222 if (buffer_info->skb) {
1223 dev_kfree_skb_any(buffer_info->skb);
1224 buffer_info->skb = NULL;
1228 size = sizeof(struct atl1_buffer) * tpd_ring->count;
1229 memset(tpd_ring->buffer_info, 0, size);
1231 /* Zero out the descriptor ring */
1232 memset(tpd_ring->desc, 0, tpd_ring->size);
1234 atomic_set(&tpd_ring->next_to_use, 0);
1235 atomic_set(&tpd_ring->next_to_clean, 0);
1239 * atl1_free_ring_resources - Free Tx / RX descriptor Resources
1240 * @adapter: board private structure
1242 * Free all transmit software resources
1244 static void atl1_free_ring_resources(struct atl1_adapter *adapter)
1246 struct pci_dev *pdev = adapter->pdev;
1247 struct atl1_tpd_ring *tpd_ring = &adapter->tpd_ring;
1248 struct atl1_rfd_ring *rfd_ring = &adapter->rfd_ring;
1249 struct atl1_rrd_ring *rrd_ring = &adapter->rrd_ring;
1250 struct atl1_ring_header *ring_header = &adapter->ring_header;
1252 atl1_clean_tx_ring(adapter);
1253 atl1_clean_rx_ring(adapter);
1255 kfree(tpd_ring->buffer_info);
1256 pci_free_consistent(pdev, ring_header->size, ring_header->desc,
1259 tpd_ring->buffer_info = NULL;
1260 tpd_ring->desc = NULL;
1263 rfd_ring->buffer_info = NULL;
1264 rfd_ring->desc = NULL;
1267 rrd_ring->desc = NULL;
1271 static void atl1_setup_mac_ctrl(struct atl1_adapter *adapter)
1274 struct atl1_hw *hw = &adapter->hw;
1275 struct net_device *netdev = adapter->netdev;
1276 /* Config MAC CTRL Register */
1277 value = MAC_CTRL_TX_EN | MAC_CTRL_RX_EN;
1279 if (FULL_DUPLEX == adapter->link_duplex)
1280 value |= MAC_CTRL_DUPLX;
1282 value |= ((u32) ((SPEED_1000 == adapter->link_speed) ?
1283 MAC_CTRL_SPEED_1000 : MAC_CTRL_SPEED_10_100) <<
1284 MAC_CTRL_SPEED_SHIFT);
1286 value |= (MAC_CTRL_TX_FLOW | MAC_CTRL_RX_FLOW);
1288 value |= (MAC_CTRL_ADD_CRC | MAC_CTRL_PAD);
1289 /* preamble length */
1290 value |= (((u32) adapter->hw.preamble_len
1291 & MAC_CTRL_PRMLEN_MASK) << MAC_CTRL_PRMLEN_SHIFT);
1294 value |= MAC_CTRL_RMV_VLAN;
1296 if (adapter->rx_csum)
1297 value |= MAC_CTRL_RX_CHKSUM_EN;
1300 value |= MAC_CTRL_BC_EN;
1301 if (netdev->flags & IFF_PROMISC)
1302 value |= MAC_CTRL_PROMIS_EN;
1303 else if (netdev->flags & IFF_ALLMULTI)
1304 value |= MAC_CTRL_MC_ALL_EN;
1305 /* value |= MAC_CTRL_LOOPBACK; */
1306 iowrite32(value, hw->hw_addr + REG_MAC_CTRL);
1309 static u32 atl1_check_link(struct atl1_adapter *adapter)
1311 struct atl1_hw *hw = &adapter->hw;
1312 struct net_device *netdev = adapter->netdev;
1314 u16 speed, duplex, phy_data;
1317 /* MII_BMSR must read twice */
1318 atl1_read_phy_reg(hw, MII_BMSR, &phy_data);
1319 atl1_read_phy_reg(hw, MII_BMSR, &phy_data);
1320 if (!(phy_data & BMSR_LSTATUS)) {
1322 if (netif_carrier_ok(netdev)) {
1323 /* old link state: Up */
1324 if (netif_msg_link(adapter))
1325 dev_info(&adapter->pdev->dev, "link is down\n");
1326 adapter->link_speed = SPEED_0;
1327 netif_carrier_off(netdev);
1328 netif_stop_queue(netdev);
1334 ret_val = atl1_get_speed_and_duplex(hw, &speed, &duplex);
1338 switch (hw->media_type) {
1339 case MEDIA_TYPE_1000M_FULL:
1340 if (speed != SPEED_1000 || duplex != FULL_DUPLEX)
1343 case MEDIA_TYPE_100M_FULL:
1344 if (speed != SPEED_100 || duplex != FULL_DUPLEX)
1347 case MEDIA_TYPE_100M_HALF:
1348 if (speed != SPEED_100 || duplex != HALF_DUPLEX)
1351 case MEDIA_TYPE_10M_FULL:
1352 if (speed != SPEED_10 || duplex != FULL_DUPLEX)
1355 case MEDIA_TYPE_10M_HALF:
1356 if (speed != SPEED_10 || duplex != HALF_DUPLEX)
1361 /* link result is our setting */
1363 if (adapter->link_speed != speed
1364 || adapter->link_duplex != duplex) {
1365 adapter->link_speed = speed;
1366 adapter->link_duplex = duplex;
1367 atl1_setup_mac_ctrl(adapter);
1368 if (netif_msg_link(adapter))
1369 dev_info(&adapter->pdev->dev,
1370 "%s link is up %d Mbps %s\n",
1371 netdev->name, adapter->link_speed,
1372 adapter->link_duplex == FULL_DUPLEX ?
1373 "full duplex" : "half duplex");
1375 if (!netif_carrier_ok(netdev)) {
1376 /* Link down -> Up */
1377 netif_carrier_on(netdev);
1378 netif_wake_queue(netdev);
1383 /* change original link status */
1384 if (netif_carrier_ok(netdev)) {
1385 adapter->link_speed = SPEED_0;
1386 netif_carrier_off(netdev);
1387 netif_stop_queue(netdev);
1390 if (hw->media_type != MEDIA_TYPE_AUTO_SENSOR &&
1391 hw->media_type != MEDIA_TYPE_1000M_FULL) {
1392 switch (hw->media_type) {
1393 case MEDIA_TYPE_100M_FULL:
1394 phy_data = MII_CR_FULL_DUPLEX | MII_CR_SPEED_100 |
1397 case MEDIA_TYPE_100M_HALF:
1398 phy_data = MII_CR_SPEED_100 | MII_CR_RESET;
1400 case MEDIA_TYPE_10M_FULL:
1402 MII_CR_FULL_DUPLEX | MII_CR_SPEED_10 | MII_CR_RESET;
1405 /* MEDIA_TYPE_10M_HALF: */
1406 phy_data = MII_CR_SPEED_10 | MII_CR_RESET;
1409 atl1_write_phy_reg(hw, MII_BMCR, phy_data);
1413 /* auto-neg, insert timer to re-config phy */
1414 if (!adapter->phy_timer_pending) {
1415 adapter->phy_timer_pending = true;
1416 mod_timer(&adapter->phy_config_timer, jiffies + 3 * HZ);
1422 static void set_flow_ctrl_old(struct atl1_adapter *adapter)
1426 /* RFD Flow Control */
1427 value = adapter->rfd_ring.count;
1433 value = ((hi & RXQ_RXF_PAUSE_TH_HI_MASK) << RXQ_RXF_PAUSE_TH_HI_SHIFT) |
1434 ((lo & RXQ_RXF_PAUSE_TH_LO_MASK) << RXQ_RXF_PAUSE_TH_LO_SHIFT);
1435 iowrite32(value, adapter->hw.hw_addr + REG_RXQ_RXF_PAUSE_THRESH);
1437 /* RRD Flow Control */
1438 value = adapter->rrd_ring.count;
1443 value = ((hi & RXQ_RRD_PAUSE_TH_HI_MASK) << RXQ_RRD_PAUSE_TH_HI_SHIFT) |
1444 ((lo & RXQ_RRD_PAUSE_TH_LO_MASK) << RXQ_RRD_PAUSE_TH_LO_SHIFT);
1445 iowrite32(value, adapter->hw.hw_addr + REG_RXQ_RRD_PAUSE_THRESH);
1448 static void set_flow_ctrl_new(struct atl1_hw *hw)
1452 /* RXF Flow Control */
1453 value = ioread32(hw->hw_addr + REG_SRAM_RXF_LEN);
1460 value = ((hi & RXQ_RXF_PAUSE_TH_HI_MASK) << RXQ_RXF_PAUSE_TH_HI_SHIFT) |
1461 ((lo & RXQ_RXF_PAUSE_TH_LO_MASK) << RXQ_RXF_PAUSE_TH_LO_SHIFT);
1462 iowrite32(value, hw->hw_addr + REG_RXQ_RXF_PAUSE_THRESH);
1464 /* RRD Flow Control */
1465 value = ioread32(hw->hw_addr + REG_SRAM_RRD_LEN);
1472 value = ((hi & RXQ_RRD_PAUSE_TH_HI_MASK) << RXQ_RRD_PAUSE_TH_HI_SHIFT) |
1473 ((lo & RXQ_RRD_PAUSE_TH_LO_MASK) << RXQ_RRD_PAUSE_TH_LO_SHIFT);
1474 iowrite32(value, hw->hw_addr + REG_RXQ_RRD_PAUSE_THRESH);
1478 * atl1_configure - Configure Transmit&Receive Unit after Reset
1479 * @adapter: board private structure
1481 * Configure the Tx /Rx unit of the MAC after a reset.
1483 static u32 atl1_configure(struct atl1_adapter *adapter)
1485 struct atl1_hw *hw = &adapter->hw;
1488 /* clear interrupt status */
1489 iowrite32(0xffffffff, adapter->hw.hw_addr + REG_ISR);
1491 /* set MAC Address */
1492 value = (((u32) hw->mac_addr[2]) << 24) |
1493 (((u32) hw->mac_addr[3]) << 16) |
1494 (((u32) hw->mac_addr[4]) << 8) |
1495 (((u32) hw->mac_addr[5]));
1496 iowrite32(value, hw->hw_addr + REG_MAC_STA_ADDR);
1497 value = (((u32) hw->mac_addr[0]) << 8) | (((u32) hw->mac_addr[1]));
1498 iowrite32(value, hw->hw_addr + (REG_MAC_STA_ADDR + 4));
1502 /* HI base address */
1503 iowrite32((u32) ((adapter->tpd_ring.dma & 0xffffffff00000000ULL) >> 32),
1504 hw->hw_addr + REG_DESC_BASE_ADDR_HI);
1505 /* LO base address */
1506 iowrite32((u32) (adapter->rfd_ring.dma & 0x00000000ffffffffULL),
1507 hw->hw_addr + REG_DESC_RFD_ADDR_LO);
1508 iowrite32((u32) (adapter->rrd_ring.dma & 0x00000000ffffffffULL),
1509 hw->hw_addr + REG_DESC_RRD_ADDR_LO);
1510 iowrite32((u32) (adapter->tpd_ring.dma & 0x00000000ffffffffULL),
1511 hw->hw_addr + REG_DESC_TPD_ADDR_LO);
1512 iowrite32((u32) (adapter->cmb.dma & 0x00000000ffffffffULL),
1513 hw->hw_addr + REG_DESC_CMB_ADDR_LO);
1514 iowrite32((u32) (adapter->smb.dma & 0x00000000ffffffffULL),
1515 hw->hw_addr + REG_DESC_SMB_ADDR_LO);
1518 value = adapter->rrd_ring.count;
1520 value += adapter->rfd_ring.count;
1521 iowrite32(value, hw->hw_addr + REG_DESC_RFD_RRD_RING_SIZE);
1522 iowrite32(adapter->tpd_ring.count, hw->hw_addr +
1523 REG_DESC_TPD_RING_SIZE);
1526 iowrite32(1, hw->hw_addr + REG_LOAD_PTR);
1528 /* config Mailbox */
1529 value = ((atomic_read(&adapter->tpd_ring.next_to_use)
1530 & MB_TPD_PROD_INDX_MASK) << MB_TPD_PROD_INDX_SHIFT) |
1531 ((atomic_read(&adapter->rrd_ring.next_to_clean)
1532 & MB_RRD_CONS_INDX_MASK) << MB_RRD_CONS_INDX_SHIFT) |
1533 ((atomic_read(&adapter->rfd_ring.next_to_use)
1534 & MB_RFD_PROD_INDX_MASK) << MB_RFD_PROD_INDX_SHIFT);
1535 iowrite32(value, hw->hw_addr + REG_MAILBOX);
1537 /* config IPG/IFG */
1538 value = (((u32) hw->ipgt & MAC_IPG_IFG_IPGT_MASK)
1539 << MAC_IPG_IFG_IPGT_SHIFT) |
1540 (((u32) hw->min_ifg & MAC_IPG_IFG_MIFG_MASK)
1541 << MAC_IPG_IFG_MIFG_SHIFT) |
1542 (((u32) hw->ipgr1 & MAC_IPG_IFG_IPGR1_MASK)
1543 << MAC_IPG_IFG_IPGR1_SHIFT) |
1544 (((u32) hw->ipgr2 & MAC_IPG_IFG_IPGR2_MASK)
1545 << MAC_IPG_IFG_IPGR2_SHIFT);
1546 iowrite32(value, hw->hw_addr + REG_MAC_IPG_IFG);
1548 /* config Half-Duplex Control */
1549 value = ((u32) hw->lcol & MAC_HALF_DUPLX_CTRL_LCOL_MASK) |
1550 (((u32) hw->max_retry & MAC_HALF_DUPLX_CTRL_RETRY_MASK)
1551 << MAC_HALF_DUPLX_CTRL_RETRY_SHIFT) |
1552 MAC_HALF_DUPLX_CTRL_EXC_DEF_EN |
1553 (0xa << MAC_HALF_DUPLX_CTRL_ABEBT_SHIFT) |
1554 (((u32) hw->jam_ipg & MAC_HALF_DUPLX_CTRL_JAMIPG_MASK)
1555 << MAC_HALF_DUPLX_CTRL_JAMIPG_SHIFT);
1556 iowrite32(value, hw->hw_addr + REG_MAC_HALF_DUPLX_CTRL);
1558 /* set Interrupt Moderator Timer */
1559 iowrite16(adapter->imt, hw->hw_addr + REG_IRQ_MODU_TIMER_INIT);
1560 iowrite32(MASTER_CTRL_ITIMER_EN, hw->hw_addr + REG_MASTER_CTRL);
1562 /* set Interrupt Clear Timer */
1563 iowrite16(adapter->ict, hw->hw_addr + REG_CMBDISDMA_TIMER);
1565 /* set max frame size hw will accept */
1566 iowrite32(hw->max_frame_size, hw->hw_addr + REG_MTU);
1568 /* jumbo size & rrd retirement timer */
1569 value = (((u32) hw->rx_jumbo_th & RXQ_JMBOSZ_TH_MASK)
1570 << RXQ_JMBOSZ_TH_SHIFT) |
1571 (((u32) hw->rx_jumbo_lkah & RXQ_JMBO_LKAH_MASK)
1572 << RXQ_JMBO_LKAH_SHIFT) |
1573 (((u32) hw->rrd_ret_timer & RXQ_RRD_TIMER_MASK)
1574 << RXQ_RRD_TIMER_SHIFT);
1575 iowrite32(value, hw->hw_addr + REG_RXQ_JMBOSZ_RRDTIM);
1578 switch (hw->dev_rev) {
1583 set_flow_ctrl_old(adapter);
1586 set_flow_ctrl_new(hw);
1591 value = (((u32) hw->tpd_burst & TXQ_CTRL_TPD_BURST_NUM_MASK)
1592 << TXQ_CTRL_TPD_BURST_NUM_SHIFT) |
1593 (((u32) hw->txf_burst & TXQ_CTRL_TXF_BURST_NUM_MASK)
1594 << TXQ_CTRL_TXF_BURST_NUM_SHIFT) |
1595 (((u32) hw->tpd_fetch_th & TXQ_CTRL_TPD_FETCH_TH_MASK)
1596 << TXQ_CTRL_TPD_FETCH_TH_SHIFT) | TXQ_CTRL_ENH_MODE |
1598 iowrite32(value, hw->hw_addr + REG_TXQ_CTRL);
1600 /* min tpd fetch gap & tx jumbo packet size threshold for taskoffload */
1601 value = (((u32) hw->tx_jumbo_task_th & TX_JUMBO_TASK_TH_MASK)
1602 << TX_JUMBO_TASK_TH_SHIFT) |
1603 (((u32) hw->tpd_fetch_gap & TX_TPD_MIN_IPG_MASK)
1604 << TX_TPD_MIN_IPG_SHIFT);
1605 iowrite32(value, hw->hw_addr + REG_TX_JUMBO_TASK_TH_TPD_IPG);
1608 value = (((u32) hw->rfd_burst & RXQ_CTRL_RFD_BURST_NUM_MASK)
1609 << RXQ_CTRL_RFD_BURST_NUM_SHIFT) |
1610 (((u32) hw->rrd_burst & RXQ_CTRL_RRD_BURST_THRESH_MASK)
1611 << RXQ_CTRL_RRD_BURST_THRESH_SHIFT) |
1612 (((u32) hw->rfd_fetch_gap & RXQ_CTRL_RFD_PREF_MIN_IPG_MASK)
1613 << RXQ_CTRL_RFD_PREF_MIN_IPG_SHIFT) | RXQ_CTRL_CUT_THRU_EN |
1615 iowrite32(value, hw->hw_addr + REG_RXQ_CTRL);
1617 /* config DMA Engine */
1618 value = ((((u32) hw->dmar_block) & DMA_CTRL_DMAR_BURST_LEN_MASK)
1619 << DMA_CTRL_DMAR_BURST_LEN_SHIFT) |
1620 ((((u32) hw->dmaw_block) & DMA_CTRL_DMAW_BURST_LEN_MASK)
1621 << DMA_CTRL_DMAW_BURST_LEN_SHIFT) | DMA_CTRL_DMAR_EN |
1623 value |= (u32) hw->dma_ord;
1624 if (atl1_rcb_128 == hw->rcb_value)
1625 value |= DMA_CTRL_RCB_VALUE;
1626 iowrite32(value, hw->hw_addr + REG_DMA_CTRL);
1628 /* config CMB / SMB */
1629 value = (hw->cmb_tpd > adapter->tpd_ring.count) ?
1630 hw->cmb_tpd : adapter->tpd_ring.count;
1632 value |= hw->cmb_rrd;
1633 iowrite32(value, hw->hw_addr + REG_CMB_WRITE_TH);
1634 value = hw->cmb_rx_timer | ((u32) hw->cmb_tx_timer << 16);
1635 iowrite32(value, hw->hw_addr + REG_CMB_WRITE_TIMER);
1636 iowrite32(hw->smb_timer, hw->hw_addr + REG_SMB_TIMER);
1638 /* --- enable CMB / SMB */
1639 value = CSMB_CTRL_CMB_EN | CSMB_CTRL_SMB_EN;
1640 iowrite32(value, hw->hw_addr + REG_CSMB_CTRL);
1642 value = ioread32(adapter->hw.hw_addr + REG_ISR);
1643 if (unlikely((value & ISR_PHY_LINKDOWN) != 0))
1644 value = 1; /* config failed */
1648 /* clear all interrupt status */
1649 iowrite32(0x3fffffff, adapter->hw.hw_addr + REG_ISR);
1650 iowrite32(0, adapter->hw.hw_addr + REG_ISR);
1655 * atl1_pcie_patch - Patch for PCIE module
1657 static void atl1_pcie_patch(struct atl1_adapter *adapter)
1661 /* much vendor magic here */
1663 iowrite32(value, adapter->hw.hw_addr + 0x12FC);
1664 /* pcie flow control mode change */
1665 value = ioread32(adapter->hw.hw_addr + 0x1008);
1667 iowrite32(value, adapter->hw.hw_addr + 0x1008);
1671 * When ACPI resume on some VIA MotherBoard, the Interrupt Disable bit/0x400
1672 * on PCI Command register is disable.
1673 * The function enable this bit.
1674 * Brackett, 2006/03/15
1676 static void atl1_via_workaround(struct atl1_adapter *adapter)
1678 unsigned long value;
1680 value = ioread16(adapter->hw.hw_addr + PCI_COMMAND);
1681 if (value & PCI_COMMAND_INTX_DISABLE)
1682 value &= ~PCI_COMMAND_INTX_DISABLE;
1683 iowrite32(value, adapter->hw.hw_addr + PCI_COMMAND);
1686 static void atl1_inc_smb(struct atl1_adapter *adapter)
1688 struct stats_msg_block *smb = adapter->smb.smb;
1690 /* Fill out the OS statistics structure */
1691 adapter->soft_stats.rx_packets += smb->rx_ok;
1692 adapter->soft_stats.tx_packets += smb->tx_ok;
1693 adapter->soft_stats.rx_bytes += smb->rx_byte_cnt;
1694 adapter->soft_stats.tx_bytes += smb->tx_byte_cnt;
1695 adapter->soft_stats.multicast += smb->rx_mcast;
1696 adapter->soft_stats.collisions += (smb->tx_1_col + smb->tx_2_col * 2 +
1697 smb->tx_late_col + smb->tx_abort_col * adapter->hw.max_retry);
1700 adapter->soft_stats.rx_errors += (smb->rx_frag + smb->rx_fcs_err +
1701 smb->rx_len_err + smb->rx_sz_ov + smb->rx_rxf_ov +
1702 smb->rx_rrd_ov + smb->rx_align_err);
1703 adapter->soft_stats.rx_fifo_errors += smb->rx_rxf_ov;
1704 adapter->soft_stats.rx_length_errors += smb->rx_len_err;
1705 adapter->soft_stats.rx_crc_errors += smb->rx_fcs_err;
1706 adapter->soft_stats.rx_frame_errors += smb->rx_align_err;
1707 adapter->soft_stats.rx_missed_errors += (smb->rx_rrd_ov +
1710 adapter->soft_stats.rx_pause += smb->rx_pause;
1711 adapter->soft_stats.rx_rrd_ov += smb->rx_rrd_ov;
1712 adapter->soft_stats.rx_trunc += smb->rx_sz_ov;
1715 adapter->soft_stats.tx_errors += (smb->tx_late_col +
1716 smb->tx_abort_col + smb->tx_underrun + smb->tx_trunc);
1717 adapter->soft_stats.tx_fifo_errors += smb->tx_underrun;
1718 adapter->soft_stats.tx_aborted_errors += smb->tx_abort_col;
1719 adapter->soft_stats.tx_window_errors += smb->tx_late_col;
1721 adapter->soft_stats.excecol += smb->tx_abort_col;
1722 adapter->soft_stats.deffer += smb->tx_defer;
1723 adapter->soft_stats.scc += smb->tx_1_col;
1724 adapter->soft_stats.mcc += smb->tx_2_col;
1725 adapter->soft_stats.latecol += smb->tx_late_col;
1726 adapter->soft_stats.tx_underun += smb->tx_underrun;
1727 adapter->soft_stats.tx_trunc += smb->tx_trunc;
1728 adapter->soft_stats.tx_pause += smb->tx_pause;
1730 adapter->net_stats.rx_packets = adapter->soft_stats.rx_packets;
1731 adapter->net_stats.tx_packets = adapter->soft_stats.tx_packets;
1732 adapter->net_stats.rx_bytes = adapter->soft_stats.rx_bytes;
1733 adapter->net_stats.tx_bytes = adapter->soft_stats.tx_bytes;
1734 adapter->net_stats.multicast = adapter->soft_stats.multicast;
1735 adapter->net_stats.collisions = adapter->soft_stats.collisions;
1736 adapter->net_stats.rx_errors = adapter->soft_stats.rx_errors;
1737 adapter->net_stats.rx_over_errors =
1738 adapter->soft_stats.rx_missed_errors;
1739 adapter->net_stats.rx_length_errors =
1740 adapter->soft_stats.rx_length_errors;
1741 adapter->net_stats.rx_crc_errors = adapter->soft_stats.rx_crc_errors;
1742 adapter->net_stats.rx_frame_errors =
1743 adapter->soft_stats.rx_frame_errors;
1744 adapter->net_stats.rx_fifo_errors = adapter->soft_stats.rx_fifo_errors;
1745 adapter->net_stats.rx_missed_errors =
1746 adapter->soft_stats.rx_missed_errors;
1747 adapter->net_stats.tx_errors = adapter->soft_stats.tx_errors;
1748 adapter->net_stats.tx_fifo_errors = adapter->soft_stats.tx_fifo_errors;
1749 adapter->net_stats.tx_aborted_errors =
1750 adapter->soft_stats.tx_aborted_errors;
1751 adapter->net_stats.tx_window_errors =
1752 adapter->soft_stats.tx_window_errors;
1753 adapter->net_stats.tx_carrier_errors =
1754 adapter->soft_stats.tx_carrier_errors;
1757 static void atl1_update_mailbox(struct atl1_adapter *adapter)
1759 unsigned long flags;
1760 u32 tpd_next_to_use;
1761 u32 rfd_next_to_use;
1762 u32 rrd_next_to_clean;
1765 spin_lock_irqsave(&adapter->mb_lock, flags);
1767 tpd_next_to_use = atomic_read(&adapter->tpd_ring.next_to_use);
1768 rfd_next_to_use = atomic_read(&adapter->rfd_ring.next_to_use);
1769 rrd_next_to_clean = atomic_read(&adapter->rrd_ring.next_to_clean);
1771 value = ((rfd_next_to_use & MB_RFD_PROD_INDX_MASK) <<
1772 MB_RFD_PROD_INDX_SHIFT) |
1773 ((rrd_next_to_clean & MB_RRD_CONS_INDX_MASK) <<
1774 MB_RRD_CONS_INDX_SHIFT) |
1775 ((tpd_next_to_use & MB_TPD_PROD_INDX_MASK) <<
1776 MB_TPD_PROD_INDX_SHIFT);
1777 iowrite32(value, adapter->hw.hw_addr + REG_MAILBOX);
1779 spin_unlock_irqrestore(&adapter->mb_lock, flags);
1782 static void atl1_clean_alloc_flag(struct atl1_adapter *adapter,
1783 struct rx_return_desc *rrd, u16 offset)
1785 struct atl1_rfd_ring *rfd_ring = &adapter->rfd_ring;
1787 while (rfd_ring->next_to_clean != (rrd->buf_indx + offset)) {
1788 rfd_ring->buffer_info[rfd_ring->next_to_clean].alloced = 0;
1789 if (++rfd_ring->next_to_clean == rfd_ring->count) {
1790 rfd_ring->next_to_clean = 0;
1795 static void atl1_update_rfd_index(struct atl1_adapter *adapter,
1796 struct rx_return_desc *rrd)
1800 num_buf = (rrd->xsz.xsum_sz.pkt_size + adapter->rx_buffer_len - 1) /
1801 adapter->rx_buffer_len;
1802 if (rrd->num_buf == num_buf)
1803 /* clean alloc flag for bad rrd */
1804 atl1_clean_alloc_flag(adapter, rrd, num_buf);
1807 static void atl1_rx_checksum(struct atl1_adapter *adapter,
1808 struct rx_return_desc *rrd, struct sk_buff *skb)
1810 struct pci_dev *pdev = adapter->pdev;
1812 skb->ip_summed = CHECKSUM_NONE;
1814 if (unlikely(rrd->pkt_flg & PACKET_FLAG_ERR)) {
1815 if (rrd->err_flg & (ERR_FLAG_CRC | ERR_FLAG_TRUNC |
1816 ERR_FLAG_CODE | ERR_FLAG_OV)) {
1817 adapter->hw_csum_err++;
1818 if (netif_msg_rx_err(adapter))
1819 dev_printk(KERN_DEBUG, &pdev->dev,
1820 "rx checksum error\n");
1826 if (!(rrd->pkt_flg & PACKET_FLAG_IPV4))
1827 /* checksum is invalid, but it's not an IPv4 pkt, so ok */
1831 if (likely(!(rrd->err_flg &
1832 (ERR_FLAG_IP_CHKSUM | ERR_FLAG_L4_CHKSUM)))) {
1833 skb->ip_summed = CHECKSUM_UNNECESSARY;
1834 adapter->hw_csum_good++;
1838 /* IPv4, but hardware thinks its checksum is wrong */
1839 if (netif_msg_rx_err(adapter))
1840 dev_printk(KERN_DEBUG, &pdev->dev,
1841 "hw csum wrong, pkt_flag:%x, err_flag:%x\n",
1842 rrd->pkt_flg, rrd->err_flg);
1843 skb->ip_summed = CHECKSUM_COMPLETE;
1844 skb->csum = htons(rrd->xsz.xsum_sz.rx_chksum);
1845 adapter->hw_csum_err++;
1850 * atl1_alloc_rx_buffers - Replace used receive buffers
1851 * @adapter: address of board private structure
1853 static u16 atl1_alloc_rx_buffers(struct atl1_adapter *adapter)
1855 struct atl1_rfd_ring *rfd_ring = &adapter->rfd_ring;
1856 struct pci_dev *pdev = adapter->pdev;
1858 unsigned long offset;
1859 struct atl1_buffer *buffer_info, *next_info;
1860 struct sk_buff *skb;
1862 u16 rfd_next_to_use, next_next;
1863 struct rx_free_desc *rfd_desc;
1865 next_next = rfd_next_to_use = atomic_read(&rfd_ring->next_to_use);
1866 if (++next_next == rfd_ring->count)
1868 buffer_info = &rfd_ring->buffer_info[rfd_next_to_use];
1869 next_info = &rfd_ring->buffer_info[next_next];
1871 while (!buffer_info->alloced && !next_info->alloced) {
1872 if (buffer_info->skb) {
1873 buffer_info->alloced = 1;
1877 rfd_desc = ATL1_RFD_DESC(rfd_ring, rfd_next_to_use);
1879 skb = dev_alloc_skb(adapter->rx_buffer_len + NET_IP_ALIGN);
1880 if (unlikely(!skb)) {
1881 /* Better luck next round */
1882 adapter->net_stats.rx_dropped++;
1887 * Make buffer alignment 2 beyond a 16 byte boundary
1888 * this will result in a 16 byte aligned IP header after
1889 * the 14 byte MAC header is removed
1891 skb_reserve(skb, NET_IP_ALIGN);
1893 buffer_info->alloced = 1;
1894 buffer_info->skb = skb;
1895 buffer_info->length = (u16) adapter->rx_buffer_len;
1896 page = virt_to_page(skb->data);
1897 offset = (unsigned long)skb->data & ~PAGE_MASK;
1898 buffer_info->dma = pci_map_page(pdev, page, offset,
1899 adapter->rx_buffer_len,
1900 PCI_DMA_FROMDEVICE);
1901 rfd_desc->buffer_addr = cpu_to_le64(buffer_info->dma);
1902 rfd_desc->buf_len = cpu_to_le16(adapter->rx_buffer_len);
1903 rfd_desc->coalese = 0;
1906 rfd_next_to_use = next_next;
1907 if (unlikely(++next_next == rfd_ring->count))
1910 buffer_info = &rfd_ring->buffer_info[rfd_next_to_use];
1911 next_info = &rfd_ring->buffer_info[next_next];
1917 * Force memory writes to complete before letting h/w
1918 * know there are new descriptors to fetch. (Only
1919 * applicable for weak-ordered memory model archs,
1923 atomic_set(&rfd_ring->next_to_use, (int)rfd_next_to_use);
1928 static void atl1_intr_rx(struct atl1_adapter *adapter)
1932 u16 rrd_next_to_clean;
1934 struct atl1_rfd_ring *rfd_ring = &adapter->rfd_ring;
1935 struct atl1_rrd_ring *rrd_ring = &adapter->rrd_ring;
1936 struct atl1_buffer *buffer_info;
1937 struct rx_return_desc *rrd;
1938 struct sk_buff *skb;
1942 rrd_next_to_clean = atomic_read(&rrd_ring->next_to_clean);
1945 rrd = ATL1_RRD_DESC(rrd_ring, rrd_next_to_clean);
1947 if (likely(rrd->xsz.valid)) { /* packet valid */
1949 /* check rrd status */
1950 if (likely(rrd->num_buf == 1))
1952 else if (netif_msg_rx_err(adapter)) {
1953 dev_printk(KERN_DEBUG, &adapter->pdev->dev,
1954 "unexpected RRD buffer count\n");
1955 dev_printk(KERN_DEBUG, &adapter->pdev->dev,
1956 "rx_buf_len = %d\n",
1957 adapter->rx_buffer_len);
1958 dev_printk(KERN_DEBUG, &adapter->pdev->dev,
1959 "RRD num_buf = %d\n",
1961 dev_printk(KERN_DEBUG, &adapter->pdev->dev,
1962 "RRD pkt_len = %d\n",
1963 rrd->xsz.xsum_sz.pkt_size);
1964 dev_printk(KERN_DEBUG, &adapter->pdev->dev,
1965 "RRD pkt_flg = 0x%08X\n",
1967 dev_printk(KERN_DEBUG, &adapter->pdev->dev,
1968 "RRD err_flg = 0x%08X\n",
1970 dev_printk(KERN_DEBUG, &adapter->pdev->dev,
1971 "RRD vlan_tag = 0x%08X\n",
1975 /* rrd seems to be bad */
1976 if (unlikely(i-- > 0)) {
1977 /* rrd may not be DMAed completely */
1982 if (netif_msg_rx_err(adapter))
1983 dev_printk(KERN_DEBUG, &adapter->pdev->dev,
1985 /* see if update RFD index */
1986 if (rrd->num_buf > 1)
1987 atl1_update_rfd_index(adapter, rrd);
1991 if (++rrd_next_to_clean == rrd_ring->count)
1992 rrd_next_to_clean = 0;
1995 } else { /* current rrd still not be updated */
2000 /* clean alloc flag for bad rrd */
2001 atl1_clean_alloc_flag(adapter, rrd, 0);
2003 buffer_info = &rfd_ring->buffer_info[rrd->buf_indx];
2004 if (++rfd_ring->next_to_clean == rfd_ring->count)
2005 rfd_ring->next_to_clean = 0;
2007 /* update rrd next to clean */
2008 if (++rrd_next_to_clean == rrd_ring->count)
2009 rrd_next_to_clean = 0;
2012 if (unlikely(rrd->pkt_flg & PACKET_FLAG_ERR)) {
2013 if (!(rrd->err_flg &
2014 (ERR_FLAG_IP_CHKSUM | ERR_FLAG_L4_CHKSUM
2016 /* packet error, don't need upstream */
2017 buffer_info->alloced = 0;
2024 pci_unmap_page(adapter->pdev, buffer_info->dma,
2025 buffer_info->length, PCI_DMA_FROMDEVICE);
2026 skb = buffer_info->skb;
2027 length = le16_to_cpu(rrd->xsz.xsum_sz.pkt_size);
2029 skb_put(skb, length - ETH_FCS_LEN);
2031 /* Receive Checksum Offload */
2032 atl1_rx_checksum(adapter, rrd, skb);
2033 skb->protocol = eth_type_trans(skb, adapter->netdev);
2035 if (adapter->vlgrp && (rrd->pkt_flg & PACKET_FLAG_VLAN_INS)) {
2036 u16 vlan_tag = (rrd->vlan_tag >> 4) |
2037 ((rrd->vlan_tag & 7) << 13) |
2038 ((rrd->vlan_tag & 8) << 9);
2039 vlan_hwaccel_rx(skb, adapter->vlgrp, vlan_tag);
2043 /* let protocol layer free skb */
2044 buffer_info->skb = NULL;
2045 buffer_info->alloced = 0;
2048 adapter->netdev->last_rx = jiffies;
2051 atomic_set(&rrd_ring->next_to_clean, rrd_next_to_clean);
2053 atl1_alloc_rx_buffers(adapter);
2055 /* update mailbox ? */
2057 u32 tpd_next_to_use;
2058 u32 rfd_next_to_use;
2060 spin_lock(&adapter->mb_lock);
2062 tpd_next_to_use = atomic_read(&adapter->tpd_ring.next_to_use);
2064 atomic_read(&adapter->rfd_ring.next_to_use);
2066 atomic_read(&adapter->rrd_ring.next_to_clean);
2067 value = ((rfd_next_to_use & MB_RFD_PROD_INDX_MASK) <<
2068 MB_RFD_PROD_INDX_SHIFT) |
2069 ((rrd_next_to_clean & MB_RRD_CONS_INDX_MASK) <<
2070 MB_RRD_CONS_INDX_SHIFT) |
2071 ((tpd_next_to_use & MB_TPD_PROD_INDX_MASK) <<
2072 MB_TPD_PROD_INDX_SHIFT);
2073 iowrite32(value, adapter->hw.hw_addr + REG_MAILBOX);
2074 spin_unlock(&adapter->mb_lock);
2078 static void atl1_intr_tx(struct atl1_adapter *adapter)
2080 struct atl1_tpd_ring *tpd_ring = &adapter->tpd_ring;
2081 struct atl1_buffer *buffer_info;
2082 u16 sw_tpd_next_to_clean;
2083 u16 cmb_tpd_next_to_clean;
2085 sw_tpd_next_to_clean = atomic_read(&tpd_ring->next_to_clean);
2086 cmb_tpd_next_to_clean = le16_to_cpu(adapter->cmb.cmb->tpd_cons_idx);
2088 while (cmb_tpd_next_to_clean != sw_tpd_next_to_clean) {
2089 struct tx_packet_desc *tpd;
2091 tpd = ATL1_TPD_DESC(tpd_ring, sw_tpd_next_to_clean);
2092 buffer_info = &tpd_ring->buffer_info[sw_tpd_next_to_clean];
2093 if (buffer_info->dma) {
2094 pci_unmap_page(adapter->pdev, buffer_info->dma,
2095 buffer_info->length, PCI_DMA_TODEVICE);
2096 buffer_info->dma = 0;
2099 if (buffer_info->skb) {
2100 dev_kfree_skb_irq(buffer_info->skb);
2101 buffer_info->skb = NULL;
2104 if (++sw_tpd_next_to_clean == tpd_ring->count)
2105 sw_tpd_next_to_clean = 0;
2107 atomic_set(&tpd_ring->next_to_clean, sw_tpd_next_to_clean);
2109 if (netif_queue_stopped(adapter->netdev)
2110 && netif_carrier_ok(adapter->netdev))
2111 netif_wake_queue(adapter->netdev);
2114 static u16 atl1_tpd_avail(struct atl1_tpd_ring *tpd_ring)
2116 u16 next_to_clean = atomic_read(&tpd_ring->next_to_clean);
2117 u16 next_to_use = atomic_read(&tpd_ring->next_to_use);
2118 return ((next_to_clean > next_to_use) ?
2119 next_to_clean - next_to_use - 1 :
2120 tpd_ring->count + next_to_clean - next_to_use - 1);
2123 static int atl1_tso(struct atl1_adapter *adapter, struct sk_buff *skb,
2124 struct tx_packet_desc *ptpd)
2131 if (skb_shinfo(skb)->gso_size) {
2132 if (skb_header_cloned(skb)) {
2133 err = pskb_expand_head(skb, 0, 0, GFP_ATOMIC);
2138 if (skb->protocol == htons(ETH_P_IP)) {
2139 struct iphdr *iph = ip_hdr(skb);
2141 real_len = (((unsigned char *)iph - skb->data) +
2142 ntohs(iph->tot_len));
2143 if (real_len < skb->len)
2144 pskb_trim(skb, real_len);
2145 hdr_len = (skb_transport_offset(skb) + tcp_hdrlen(skb));
2146 if (skb->len == hdr_len) {
2148 tcp_hdr(skb)->check =
2149 ~csum_tcpudp_magic(iph->saddr,
2150 iph->daddr, tcp_hdrlen(skb),
2152 ptpd->word3 |= (iph->ihl & TPD_IPHL_MASK) <<
2154 ptpd->word3 |= ((tcp_hdrlen(skb) >> 2) &
2155 TPD_TCPHDRLEN_MASK) <<
2156 TPD_TCPHDRLEN_SHIFT;
2157 ptpd->word3 |= 1 << TPD_IP_CSUM_SHIFT;
2158 ptpd->word3 |= 1 << TPD_TCP_CSUM_SHIFT;
2163 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
2164 iph->daddr, 0, IPPROTO_TCP, 0);
2165 ip_off = (unsigned char *)iph -
2166 (unsigned char *) skb_network_header(skb);
2167 if (ip_off == 8) /* 802.3-SNAP frame */
2168 ptpd->word3 |= 1 << TPD_ETHTYPE_SHIFT;
2169 else if (ip_off != 0)
2172 ptpd->word3 |= (iph->ihl & TPD_IPHL_MASK) <<
2174 ptpd->word3 |= ((tcp_hdrlen(skb) >> 2) &
2175 TPD_TCPHDRLEN_MASK) << TPD_TCPHDRLEN_SHIFT;
2176 ptpd->word3 |= (skb_shinfo(skb)->gso_size &
2177 TPD_MSS_MASK) << TPD_MSS_SHIFT;
2178 ptpd->word3 |= 1 << TPD_SEGMENT_EN_SHIFT;
2185 static int atl1_tx_csum(struct atl1_adapter *adapter, struct sk_buff *skb,
2186 struct tx_packet_desc *ptpd)
2190 if (likely(skb->ip_summed == CHECKSUM_PARTIAL)) {
2191 css = (u8) (skb->csum_start - skb_headroom(skb));
2192 cso = css + (u8) skb->csum_offset;
2193 if (unlikely(css & 0x1)) {
2194 /* L1 hardware requires an even number here */
2195 if (netif_msg_tx_err(adapter))
2196 dev_printk(KERN_DEBUG, &adapter->pdev->dev,
2197 "payload offset not an even number\n");
2200 ptpd->word3 |= (css & TPD_PLOADOFFSET_MASK) <<
2201 TPD_PLOADOFFSET_SHIFT;
2202 ptpd->word3 |= (cso & TPD_CCSUMOFFSET_MASK) <<
2203 TPD_CCSUMOFFSET_SHIFT;
2204 ptpd->word3 |= 1 << TPD_CUST_CSUM_EN_SHIFT;
2210 static void atl1_tx_map(struct atl1_adapter *adapter, struct sk_buff *skb,
2211 struct tx_packet_desc *ptpd)
2214 struct atl1_tpd_ring *tpd_ring = &adapter->tpd_ring;
2215 struct atl1_buffer *buffer_info;
2216 u16 buf_len = skb->len;
2218 unsigned long offset;
2219 unsigned int nr_frags;
2226 buf_len -= skb->data_len;
2227 nr_frags = skb_shinfo(skb)->nr_frags;
2228 next_to_use = atomic_read(&tpd_ring->next_to_use);
2229 buffer_info = &tpd_ring->buffer_info[next_to_use];
2230 if (unlikely(buffer_info->skb))
2232 /* put skb in last TPD */
2233 buffer_info->skb = NULL;
2235 retval = (ptpd->word3 >> TPD_SEGMENT_EN_SHIFT) & TPD_SEGMENT_EN_MASK;
2238 hdr_len = skb_transport_offset(skb) + tcp_hdrlen(skb);
2239 buffer_info->length = hdr_len;
2240 page = virt_to_page(skb->data);
2241 offset = (unsigned long)skb->data & ~PAGE_MASK;
2242 buffer_info->dma = pci_map_page(adapter->pdev, page,
2246 if (++next_to_use == tpd_ring->count)
2249 if (buf_len > hdr_len) {
2252 data_len = buf_len - hdr_len;
2253 nseg = (data_len + ATL1_MAX_TX_BUF_LEN - 1) /
2254 ATL1_MAX_TX_BUF_LEN;
2255 for (i = 0; i < nseg; i++) {
2257 &tpd_ring->buffer_info[next_to_use];
2258 buffer_info->skb = NULL;
2259 buffer_info->length =
2260 (ATL1_MAX_TX_BUF_LEN >=
2261 data_len) ? ATL1_MAX_TX_BUF_LEN : data_len;
2262 data_len -= buffer_info->length;
2263 page = virt_to_page(skb->data +
2264 (hdr_len + i * ATL1_MAX_TX_BUF_LEN));
2265 offset = (unsigned long)(skb->data +
2266 (hdr_len + i * ATL1_MAX_TX_BUF_LEN)) &
2268 buffer_info->dma = pci_map_page(adapter->pdev,
2269 page, offset, buffer_info->length,
2271 if (++next_to_use == tpd_ring->count)
2277 buffer_info->length = buf_len;
2278 page = virt_to_page(skb->data);
2279 offset = (unsigned long)skb->data & ~PAGE_MASK;
2280 buffer_info->dma = pci_map_page(adapter->pdev, page,
2281 offset, buf_len, PCI_DMA_TODEVICE);
2282 if (++next_to_use == tpd_ring->count)
2286 for (f = 0; f < nr_frags; f++) {
2287 struct skb_frag_struct *frag;
2290 frag = &skb_shinfo(skb)->frags[f];
2291 buf_len = frag->size;
2293 nseg = (buf_len + ATL1_MAX_TX_BUF_LEN - 1) /
2294 ATL1_MAX_TX_BUF_LEN;
2295 for (i = 0; i < nseg; i++) {
2296 buffer_info = &tpd_ring->buffer_info[next_to_use];
2297 if (unlikely(buffer_info->skb))
2299 buffer_info->skb = NULL;
2300 buffer_info->length = (buf_len > ATL1_MAX_TX_BUF_LEN) ?
2301 ATL1_MAX_TX_BUF_LEN : buf_len;
2302 buf_len -= buffer_info->length;
2303 buffer_info->dma = pci_map_page(adapter->pdev,
2305 frag->page_offset + (i * ATL1_MAX_TX_BUF_LEN),
2306 buffer_info->length, PCI_DMA_TODEVICE);
2308 if (++next_to_use == tpd_ring->count)
2313 /* last tpd's buffer-info */
2314 buffer_info->skb = skb;
2317 static void atl1_tx_queue(struct atl1_adapter *adapter, u16 count,
2318 struct tx_packet_desc *ptpd)
2321 struct atl1_tpd_ring *tpd_ring = &adapter->tpd_ring;
2322 struct atl1_buffer *buffer_info;
2323 struct tx_packet_desc *tpd;
2326 u16 next_to_use = (u16) atomic_read(&tpd_ring->next_to_use);
2328 for (j = 0; j < count; j++) {
2329 buffer_info = &tpd_ring->buffer_info[next_to_use];
2330 tpd = ATL1_TPD_DESC(&adapter->tpd_ring, next_to_use);
2332 memcpy(tpd, ptpd, sizeof(struct tx_packet_desc));
2333 tpd->buffer_addr = cpu_to_le64(buffer_info->dma);
2334 tpd->word2 = (cpu_to_le16(buffer_info->length) &
2335 TPD_BUFLEN_MASK) << TPD_BUFLEN_SHIFT;
2338 * if this is the first packet in a TSO chain, set
2339 * TPD_HDRFLAG, otherwise, clear it.
2341 val = (tpd->word3 >> TPD_SEGMENT_EN_SHIFT) &
2342 TPD_SEGMENT_EN_MASK;
2345 tpd->word3 |= 1 << TPD_HDRFLAG_SHIFT;
2347 tpd->word3 &= ~(1 << TPD_HDRFLAG_SHIFT);
2350 if (j == (count - 1))
2351 tpd->word3 |= 1 << TPD_EOP_SHIFT;
2353 if (++next_to_use == tpd_ring->count)
2357 * Force memory writes to complete before letting h/w
2358 * know there are new descriptors to fetch. (Only
2359 * applicable for weak-ordered memory model archs,
2364 atomic_set(&tpd_ring->next_to_use, next_to_use);
2367 static int atl1_xmit_frame(struct sk_buff *skb, struct net_device *netdev)
2369 struct atl1_adapter *adapter = netdev_priv(netdev);
2370 struct atl1_tpd_ring *tpd_ring = &adapter->tpd_ring;
2375 struct tx_packet_desc *ptpd;
2378 unsigned long flags;
2379 unsigned int nr_frags = 0;
2380 unsigned int mss = 0;
2382 unsigned int proto_hdr_len;
2384 len -= skb->data_len;
2386 if (unlikely(skb->len <= 0)) {
2387 dev_kfree_skb_any(skb);
2388 return NETDEV_TX_OK;
2391 nr_frags = skb_shinfo(skb)->nr_frags;
2392 for (f = 0; f < nr_frags; f++) {
2393 frag_size = skb_shinfo(skb)->frags[f].size;
2395 count += (frag_size + ATL1_MAX_TX_BUF_LEN - 1) /
2396 ATL1_MAX_TX_BUF_LEN;
2399 mss = skb_shinfo(skb)->gso_size;
2401 if (skb->protocol == ntohs(ETH_P_IP)) {
2402 proto_hdr_len = (skb_transport_offset(skb) +
2404 if (unlikely(proto_hdr_len > len)) {
2405 dev_kfree_skb_any(skb);
2406 return NETDEV_TX_OK;
2408 /* need additional TPD ? */
2409 if (proto_hdr_len != len)
2410 count += (len - proto_hdr_len +
2411 ATL1_MAX_TX_BUF_LEN - 1) /
2412 ATL1_MAX_TX_BUF_LEN;
2416 if (!spin_trylock_irqsave(&adapter->lock, flags)) {
2417 /* Can't get lock - tell upper layer to requeue */
2418 if (netif_msg_tx_queued(adapter))
2419 dev_printk(KERN_DEBUG, &adapter->pdev->dev,
2421 return NETDEV_TX_LOCKED;
2424 if (atl1_tpd_avail(&adapter->tpd_ring) < count) {
2425 /* not enough descriptors */
2426 netif_stop_queue(netdev);
2427 spin_unlock_irqrestore(&adapter->lock, flags);
2428 if (netif_msg_tx_queued(adapter))
2429 dev_printk(KERN_DEBUG, &adapter->pdev->dev,
2431 return NETDEV_TX_BUSY;
2434 ptpd = ATL1_TPD_DESC(tpd_ring,
2435 (u16) atomic_read(&tpd_ring->next_to_use));
2436 memset(ptpd, 0, sizeof(struct tx_packet_desc));
2438 if (adapter->vlgrp && vlan_tx_tag_present(skb)) {
2439 vlan_tag = vlan_tx_tag_get(skb);
2440 vlan_tag = (vlan_tag << 4) | (vlan_tag >> 13) |
2441 ((vlan_tag >> 9) & 0x8);
2442 ptpd->word3 |= 1 << TPD_INS_VL_TAG_SHIFT;
2443 ptpd->word3 |= (vlan_tag & TPD_VL_TAGGED_MASK) <<
2444 TPD_VL_TAGGED_SHIFT;
2447 tso = atl1_tso(adapter, skb, ptpd);
2449 spin_unlock_irqrestore(&adapter->lock, flags);
2450 dev_kfree_skb_any(skb);
2451 return NETDEV_TX_OK;
2455 ret_val = atl1_tx_csum(adapter, skb, ptpd);
2457 spin_unlock_irqrestore(&adapter->lock, flags);
2458 dev_kfree_skb_any(skb);
2459 return NETDEV_TX_OK;
2463 atl1_tx_map(adapter, skb, ptpd);
2464 atl1_tx_queue(adapter, count, ptpd);
2465 atl1_update_mailbox(adapter);
2466 spin_unlock_irqrestore(&adapter->lock, flags);
2467 netdev->trans_start = jiffies;
2468 return NETDEV_TX_OK;
2472 * atl1_intr - Interrupt Handler
2473 * @irq: interrupt number
2474 * @data: pointer to a network interface device structure
2475 * @pt_regs: CPU registers structure
2477 static irqreturn_t atl1_intr(int irq, void *data)
2479 struct atl1_adapter *adapter = netdev_priv(data);
2483 status = adapter->cmb.cmb->int_stats;
2488 /* clear CMB interrupt status at once */
2489 adapter->cmb.cmb->int_stats = 0;
2491 if (status & ISR_GPHY) /* clear phy status */
2492 atlx_clear_phy_int(adapter);
2494 /* clear ISR status, and Enable CMB DMA/Disable Interrupt */
2495 iowrite32(status | ISR_DIS_INT, adapter->hw.hw_addr + REG_ISR);
2497 /* check if SMB intr */
2498 if (status & ISR_SMB)
2499 atl1_inc_smb(adapter);
2501 /* check if PCIE PHY Link down */
2502 if (status & ISR_PHY_LINKDOWN) {
2503 if (netif_msg_intr(adapter))
2504 dev_printk(KERN_DEBUG, &adapter->pdev->dev,
2505 "pcie phy link down %x\n", status);
2506 if (netif_running(adapter->netdev)) { /* reset MAC */
2507 iowrite32(0, adapter->hw.hw_addr + REG_IMR);
2508 schedule_work(&adapter->pcie_dma_to_rst_task);
2513 /* check if DMA read/write error ? */
2514 if (status & (ISR_DMAR_TO_RST | ISR_DMAW_TO_RST)) {
2515 if (netif_msg_intr(adapter))
2516 dev_printk(KERN_DEBUG, &adapter->pdev->dev,
2517 "pcie DMA r/w error (status = 0x%x)\n",
2519 iowrite32(0, adapter->hw.hw_addr + REG_IMR);
2520 schedule_work(&adapter->pcie_dma_to_rst_task);
2525 if (status & ISR_GPHY) {
2526 adapter->soft_stats.tx_carrier_errors++;
2527 atl1_check_for_link(adapter);
2530 /* transmit event */
2531 if (status & ISR_CMB_TX)
2532 atl1_intr_tx(adapter);
2535 if (unlikely(status & (ISR_RXF_OV | ISR_RFD_UNRUN |
2536 ISR_RRD_OV | ISR_HOST_RFD_UNRUN |
2537 ISR_HOST_RRD_OV | ISR_CMB_RX))) {
2538 if (status & (ISR_RXF_OV | ISR_RFD_UNRUN |
2539 ISR_RRD_OV | ISR_HOST_RFD_UNRUN |
2541 if (netif_msg_intr(adapter))
2542 dev_printk(KERN_DEBUG,
2543 &adapter->pdev->dev,
2544 "rx exception, ISR = 0x%x\n",
2546 atl1_intr_rx(adapter);
2552 } while ((status = adapter->cmb.cmb->int_stats));
2554 /* re-enable Interrupt */
2555 iowrite32(ISR_DIS_SMB | ISR_DIS_DMA, adapter->hw.hw_addr + REG_ISR);
2560 * atl1_watchdog - Timer Call-back
2561 * @data: pointer to netdev cast into an unsigned long
2563 static void atl1_watchdog(unsigned long data)
2565 struct atl1_adapter *adapter = (struct atl1_adapter *)data;
2567 /* Reset the timer */
2568 mod_timer(&adapter->watchdog_timer, jiffies + 2 * HZ);
2572 * atl1_phy_config - Timer Call-back
2573 * @data: pointer to netdev cast into an unsigned long
2575 static void atl1_phy_config(unsigned long data)
2577 struct atl1_adapter *adapter = (struct atl1_adapter *)data;
2578 struct atl1_hw *hw = &adapter->hw;
2579 unsigned long flags;
2581 spin_lock_irqsave(&adapter->lock, flags);
2582 adapter->phy_timer_pending = false;
2583 atl1_write_phy_reg(hw, MII_ADVERTISE, hw->mii_autoneg_adv_reg);
2584 atl1_write_phy_reg(hw, MII_ATLX_CR, hw->mii_1000t_ctrl_reg);
2585 atl1_write_phy_reg(hw, MII_BMCR, MII_CR_RESET | MII_CR_AUTO_NEG_EN);
2586 spin_unlock_irqrestore(&adapter->lock, flags);
2590 * Orphaned vendor comment left intact here:
2592 * If TPD Buffer size equal to 0, PCIE DMAR_TO_INT
2593 * will assert. We do soft reset <0x1400=1> according
2594 * with the SPEC. BUT, it seemes that PCIE or DMA
2595 * state-machine will not be reset. DMAR_TO_INT will
2596 * assert again and again.
2600 static int atl1_reset(struct atl1_adapter *adapter)
2603 ret = atl1_reset_hw(&adapter->hw);
2606 return atl1_init_hw(&adapter->hw);
2609 static s32 atl1_up(struct atl1_adapter *adapter)
2611 struct net_device *netdev = adapter->netdev;
2613 int irq_flags = IRQF_SAMPLE_RANDOM;
2615 /* hardware has been reset, we need to reload some things */
2616 atlx_set_multi(netdev);
2617 atl1_init_ring_ptrs(adapter);
2618 atlx_restore_vlan(adapter);
2619 err = atl1_alloc_rx_buffers(adapter);
2621 /* no RX BUFFER allocated */
2624 if (unlikely(atl1_configure(adapter))) {
2629 err = pci_enable_msi(adapter->pdev);
2631 if (netif_msg_ifup(adapter))
2632 dev_info(&adapter->pdev->dev,
2633 "Unable to enable MSI: %d\n", err);
2634 irq_flags |= IRQF_SHARED;
2637 err = request_irq(adapter->pdev->irq, &atl1_intr, irq_flags,
2638 netdev->name, netdev);
2642 mod_timer(&adapter->watchdog_timer, jiffies);
2643 atlx_irq_enable(adapter);
2644 atl1_check_link(adapter);
2648 pci_disable_msi(adapter->pdev);
2649 /* free rx_buffers */
2650 atl1_clean_rx_ring(adapter);
2654 static void atl1_down(struct atl1_adapter *adapter)
2656 struct net_device *netdev = adapter->netdev;
2658 del_timer_sync(&adapter->watchdog_timer);
2659 del_timer_sync(&adapter->phy_config_timer);
2660 adapter->phy_timer_pending = false;
2662 atlx_irq_disable(adapter);
2663 free_irq(adapter->pdev->irq, netdev);
2664 pci_disable_msi(adapter->pdev);
2665 atl1_reset_hw(&adapter->hw);
2666 adapter->cmb.cmb->int_stats = 0;
2668 adapter->link_speed = SPEED_0;
2669 adapter->link_duplex = -1;
2670 netif_carrier_off(netdev);
2671 netif_stop_queue(netdev);
2673 atl1_clean_tx_ring(adapter);
2674 atl1_clean_rx_ring(adapter);
2677 static void atl1_tx_timeout_task(struct work_struct *work)
2679 struct atl1_adapter *adapter =
2680 container_of(work, struct atl1_adapter, tx_timeout_task);
2681 struct net_device *netdev = adapter->netdev;
2683 netif_device_detach(netdev);
2686 netif_device_attach(netdev);
2690 * atl1_change_mtu - Change the Maximum Transfer Unit
2691 * @netdev: network interface device structure
2692 * @new_mtu: new value for maximum frame size
2694 * Returns 0 on success, negative on failure
2696 static int atl1_change_mtu(struct net_device *netdev, int new_mtu)
2698 struct atl1_adapter *adapter = netdev_priv(netdev);
2699 int old_mtu = netdev->mtu;
2700 int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN;
2702 if ((max_frame < ETH_ZLEN + ETH_FCS_LEN) ||
2703 (max_frame > MAX_JUMBO_FRAME_SIZE)) {
2704 if (netif_msg_link(adapter))
2705 dev_warn(&adapter->pdev->dev, "invalid MTU setting\n");
2709 adapter->hw.max_frame_size = max_frame;
2710 adapter->hw.tx_jumbo_task_th = (max_frame + 7) >> 3;
2711 adapter->rx_buffer_len = (max_frame + 7) & ~7;
2712 adapter->hw.rx_jumbo_th = adapter->rx_buffer_len / 8;
2714 netdev->mtu = new_mtu;
2715 if ((old_mtu != new_mtu) && netif_running(netdev)) {
2724 * atl1_open - Called when a network interface is made active
2725 * @netdev: network interface device structure
2727 * Returns 0 on success, negative value on failure
2729 * The open entry point is called when a network interface is made
2730 * active by the system (IFF_UP). At this point all resources needed
2731 * for transmit and receive operations are allocated, the interrupt
2732 * handler is registered with the OS, the watchdog timer is started,
2733 * and the stack is notified that the interface is ready.
2735 static int atl1_open(struct net_device *netdev)
2737 struct atl1_adapter *adapter = netdev_priv(netdev);
2740 /* allocate transmit descriptors */
2741 err = atl1_setup_ring_resources(adapter);
2745 err = atl1_up(adapter);
2752 atl1_reset(adapter);
2757 * atl1_close - Disables a network interface
2758 * @netdev: network interface device structure
2760 * Returns 0, this is not allowed to fail
2762 * The close entry point is called when an interface is de-activated
2763 * by the OS. The hardware is still under the drivers control, but
2764 * needs to be disabled. A global MAC reset is issued to stop the
2765 * hardware, and all transmit and receive resources are freed.
2767 static int atl1_close(struct net_device *netdev)
2769 struct atl1_adapter *adapter = netdev_priv(netdev);
2771 atl1_free_ring_resources(adapter);
2776 static int atl1_suspend(struct pci_dev *pdev, pm_message_t state)
2778 struct net_device *netdev = pci_get_drvdata(pdev);
2779 struct atl1_adapter *adapter = netdev_priv(netdev);
2780 struct atl1_hw *hw = &adapter->hw;
2782 u32 wufc = adapter->wol;
2788 netif_device_detach(netdev);
2789 if (netif_running(netdev))
2792 retval = pci_save_state(pdev);
2796 atl1_read_phy_reg(hw, MII_BMSR, (u16 *) & ctrl);
2797 atl1_read_phy_reg(hw, MII_BMSR, (u16 *) & ctrl);
2798 val = ctrl & BMSR_LSTATUS;
2800 wufc &= ~ATLX_WUFC_LNKC;
2803 val = atl1_get_speed_and_duplex(hw, &speed, &duplex);
2805 if (netif_msg_ifdown(adapter))
2806 dev_printk(KERN_DEBUG, &pdev->dev,
2807 "error getting speed/duplex\n");
2813 /* enable magic packet WOL */
2814 if (wufc & ATLX_WUFC_MAG)
2815 ctrl |= (WOL_MAGIC_EN | WOL_MAGIC_PME_EN);
2816 iowrite32(ctrl, hw->hw_addr + REG_WOL_CTRL);
2817 ioread32(hw->hw_addr + REG_WOL_CTRL);
2819 /* configure the mac */
2820 ctrl = MAC_CTRL_RX_EN;
2821 ctrl |= ((u32)((speed == SPEED_1000) ? MAC_CTRL_SPEED_1000 :
2822 MAC_CTRL_SPEED_10_100) << MAC_CTRL_SPEED_SHIFT);
2823 if (duplex == FULL_DUPLEX)
2824 ctrl |= MAC_CTRL_DUPLX;
2825 ctrl |= (((u32)adapter->hw.preamble_len &
2826 MAC_CTRL_PRMLEN_MASK) << MAC_CTRL_PRMLEN_SHIFT);
2828 ctrl |= MAC_CTRL_RMV_VLAN;
2829 if (wufc & ATLX_WUFC_MAG)
2830 ctrl |= MAC_CTRL_BC_EN;
2831 iowrite32(ctrl, hw->hw_addr + REG_MAC_CTRL);
2832 ioread32(hw->hw_addr + REG_MAC_CTRL);
2835 ctrl = ioread32(hw->hw_addr + REG_PCIE_PHYMISC);
2836 ctrl |= PCIE_PHYMISC_FORCE_RCV_DET;
2837 iowrite32(ctrl, hw->hw_addr + REG_PCIE_PHYMISC);
2838 ioread32(hw->hw_addr + REG_PCIE_PHYMISC);
2840 pci_enable_wake(pdev, pci_choose_state(pdev, state), 1);
2845 ctrl |= (WOL_LINK_CHG_EN | WOL_LINK_CHG_PME_EN);
2846 iowrite32(ctrl, hw->hw_addr + REG_WOL_CTRL);
2847 ioread32(hw->hw_addr + REG_WOL_CTRL);
2848 iowrite32(0, hw->hw_addr + REG_MAC_CTRL);
2849 ioread32(hw->hw_addr + REG_MAC_CTRL);
2850 hw->phy_configured = false;
2851 pci_enable_wake(pdev, pci_choose_state(pdev, state), 1);
2856 iowrite32(0, hw->hw_addr + REG_WOL_CTRL);
2857 ioread32(hw->hw_addr + REG_WOL_CTRL);
2858 ctrl = ioread32(hw->hw_addr + REG_PCIE_PHYMISC);
2859 ctrl |= PCIE_PHYMISC_FORCE_RCV_DET;
2860 iowrite32(ctrl, hw->hw_addr + REG_PCIE_PHYMISC);
2861 ioread32(hw->hw_addr + REG_PCIE_PHYMISC);
2862 atl1_phy_enter_power_saving(hw);
2863 hw->phy_configured = false;
2864 pci_enable_wake(pdev, pci_choose_state(pdev, state), 0);
2866 if (netif_running(netdev))
2867 pci_disable_msi(adapter->pdev);
2868 pci_disable_device(pdev);
2869 pci_set_power_state(pdev, pci_choose_state(pdev, state));
2874 static int atl1_resume(struct pci_dev *pdev)
2876 struct net_device *netdev = pci_get_drvdata(pdev);
2877 struct atl1_adapter *adapter = netdev_priv(netdev);
2880 pci_set_power_state(pdev, PCI_D0);
2881 pci_restore_state(pdev);
2883 err = pci_enable_device(pdev);
2885 if (netif_msg_ifup(adapter))
2886 dev_printk(KERN_DEBUG, &pdev->dev,
2887 "error enabling pci device\n");
2891 pci_set_master(pdev);
2892 iowrite32(0, adapter->hw.hw_addr + REG_WOL_CTRL);
2893 pci_enable_wake(pdev, PCI_D3hot, 0);
2894 pci_enable_wake(pdev, PCI_D3cold, 0);
2896 atl1_reset_hw(&adapter->hw);
2897 adapter->cmb.cmb->int_stats = 0;
2899 if (netif_running(netdev))
2901 netif_device_attach(netdev);
2906 #define atl1_suspend NULL
2907 #define atl1_resume NULL
2910 static void atl1_shutdown(struct pci_dev *pdev)
2913 atl1_suspend(pdev, PMSG_SUSPEND);
2917 #ifdef CONFIG_NET_POLL_CONTROLLER
2918 static void atl1_poll_controller(struct net_device *netdev)
2920 disable_irq(netdev->irq);
2921 atl1_intr(netdev->irq, netdev);
2922 enable_irq(netdev->irq);
2927 * atl1_probe - Device Initialization Routine
2928 * @pdev: PCI device information struct
2929 * @ent: entry in atl1_pci_tbl
2931 * Returns 0 on success, negative on failure
2933 * atl1_probe initializes an adapter identified by a pci_dev structure.
2934 * The OS initialization, configuring of the adapter private structure,
2935 * and a hardware reset occur.
2937 static int __devinit atl1_probe(struct pci_dev *pdev,
2938 const struct pci_device_id *ent)
2940 struct net_device *netdev;
2941 struct atl1_adapter *adapter;
2942 static int cards_found = 0;
2945 err = pci_enable_device(pdev);
2950 * The atl1 chip can DMA to 64-bit addresses, but it uses a single
2951 * shared register for the high 32 bits, so only a single, aligned,
2952 * 4 GB physical address range can be used at a time.
2954 * Supporting 64-bit DMA on this hardware is more trouble than it's
2955 * worth. It is far easier to limit to 32-bit DMA than update
2956 * various kernel subsystems to support the mechanics required by a
2957 * fixed-high-32-bit system.
2959 err = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
2961 dev_err(&pdev->dev, "no usable DMA configuration\n");
2965 * Mark all PCI regions associated with PCI device
2966 * pdev as being reserved by owner atl1_driver_name
2968 err = pci_request_regions(pdev, ATLX_DRIVER_NAME);
2970 goto err_request_regions;
2973 * Enables bus-mastering on the device and calls
2974 * pcibios_set_master to do the needed arch specific settings
2976 pci_set_master(pdev);
2978 netdev = alloc_etherdev(sizeof(struct atl1_adapter));
2981 goto err_alloc_etherdev;
2983 SET_NETDEV_DEV(netdev, &pdev->dev);
2985 pci_set_drvdata(pdev, netdev);
2986 adapter = netdev_priv(netdev);
2987 adapter->netdev = netdev;
2988 adapter->pdev = pdev;
2989 adapter->hw.back = adapter;
2990 adapter->msg_enable = netif_msg_init(debug, atl1_default_msg);
2992 adapter->hw.hw_addr = pci_iomap(pdev, 0, 0);
2993 if (!adapter->hw.hw_addr) {
2997 /* get device revision number */
2998 adapter->hw.dev_rev = ioread16(adapter->hw.hw_addr +
2999 (REG_MASTER_CTRL + 2));
3000 if (netif_msg_probe(adapter))
3001 dev_info(&pdev->dev, "version %s\n", ATLX_DRIVER_VERSION);
3003 /* set default ring resource counts */
3004 adapter->rfd_ring.count = adapter->rrd_ring.count = ATL1_DEFAULT_RFD;
3005 adapter->tpd_ring.count = ATL1_DEFAULT_TPD;
3007 adapter->mii.dev = netdev;
3008 adapter->mii.mdio_read = mdio_read;
3009 adapter->mii.mdio_write = mdio_write;
3010 adapter->mii.phy_id_mask = 0x1f;
3011 adapter->mii.reg_num_mask = 0x1f;
3013 netdev->open = &atl1_open;
3014 netdev->stop = &atl1_close;
3015 netdev->hard_start_xmit = &atl1_xmit_frame;
3016 netdev->get_stats = &atlx_get_stats;
3017 netdev->set_multicast_list = &atlx_set_multi;
3018 netdev->set_mac_address = &atl1_set_mac;
3019 netdev->change_mtu = &atl1_change_mtu;
3020 netdev->do_ioctl = &atlx_ioctl;
3021 netdev->tx_timeout = &atlx_tx_timeout;
3022 netdev->watchdog_timeo = 5 * HZ;
3023 #ifdef CONFIG_NET_POLL_CONTROLLER
3024 netdev->poll_controller = atl1_poll_controller;
3026 netdev->vlan_rx_register = atlx_vlan_rx_register;
3028 netdev->ethtool_ops = &atl1_ethtool_ops;
3029 adapter->bd_number = cards_found;
3031 /* setup the private structure */
3032 err = atl1_sw_init(adapter);
3036 netdev->features = NETIF_F_HW_CSUM;
3037 netdev->features |= NETIF_F_SG;
3038 netdev->features |= (NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX);
3039 netdev->features |= NETIF_F_TSO;
3040 netdev->features |= NETIF_F_LLTX;
3043 * patch for some L1 of old version,
3044 * the final version of L1 may not need these
3047 /* atl1_pcie_patch(adapter); */
3049 /* really reset GPHY core */
3050 iowrite16(0, adapter->hw.hw_addr + REG_PHY_ENABLE);
3053 * reset the controller to
3054 * put the device in a known good starting state
3056 if (atl1_reset_hw(&adapter->hw)) {
3061 /* copy the MAC address out of the EEPROM */
3062 atl1_read_mac_addr(&adapter->hw);
3063 memcpy(netdev->dev_addr, adapter->hw.mac_addr, netdev->addr_len);
3065 if (!is_valid_ether_addr(netdev->dev_addr)) {
3070 atl1_check_options(adapter);
3072 /* pre-init the MAC, and setup link */
3073 err = atl1_init_hw(&adapter->hw);
3079 atl1_pcie_patch(adapter);
3080 /* assume we have no link for now */
3081 netif_carrier_off(netdev);
3082 netif_stop_queue(netdev);
3084 init_timer(&adapter->watchdog_timer);
3085 adapter->watchdog_timer.function = &atl1_watchdog;
3086 adapter->watchdog_timer.data = (unsigned long)adapter;
3088 init_timer(&adapter->phy_config_timer);
3089 adapter->phy_config_timer.function = &atl1_phy_config;
3090 adapter->phy_config_timer.data = (unsigned long)adapter;
3091 adapter->phy_timer_pending = false;
3093 INIT_WORK(&adapter->tx_timeout_task, atl1_tx_timeout_task);
3095 INIT_WORK(&adapter->link_chg_task, atlx_link_chg_task);
3097 INIT_WORK(&adapter->pcie_dma_to_rst_task, atl1_tx_timeout_task);
3099 err = register_netdev(netdev);
3104 atl1_via_workaround(adapter);
3108 pci_iounmap(pdev, adapter->hw.hw_addr);
3110 free_netdev(netdev);
3112 pci_release_regions(pdev);
3114 err_request_regions:
3115 pci_disable_device(pdev);
3120 * atl1_remove - Device Removal Routine
3121 * @pdev: PCI device information struct
3123 * atl1_remove is called by the PCI subsystem to alert the driver
3124 * that it should release a PCI device. The could be caused by a
3125 * Hot-Plug event, or because the driver is going to be removed from
3128 static void __devexit atl1_remove(struct pci_dev *pdev)
3130 struct net_device *netdev = pci_get_drvdata(pdev);
3131 struct atl1_adapter *adapter;
3132 /* Device not available. Return. */
3136 adapter = netdev_priv(netdev);
3139 * Some atl1 boards lack persistent storage for their MAC, and get it
3140 * from the BIOS during POST. If we've been messing with the MAC
3141 * address, we need to save the permanent one.
3143 if (memcmp(adapter->hw.mac_addr, adapter->hw.perm_mac_addr, ETH_ALEN)) {
3144 memcpy(adapter->hw.mac_addr, adapter->hw.perm_mac_addr,
3146 atl1_set_mac_addr(&adapter->hw);
3149 iowrite16(0, adapter->hw.hw_addr + REG_PHY_ENABLE);
3150 unregister_netdev(netdev);
3151 pci_iounmap(pdev, adapter->hw.hw_addr);
3152 pci_release_regions(pdev);
3153 free_netdev(netdev);
3154 pci_disable_device(pdev);
3157 static struct pci_driver atl1_driver = {
3158 .name = ATLX_DRIVER_NAME,
3159 .id_table = atl1_pci_tbl,
3160 .probe = atl1_probe,
3161 .remove = __devexit_p(atl1_remove),
3162 .suspend = atl1_suspend,
3163 .resume = atl1_resume,
3164 .shutdown = atl1_shutdown
3168 * atl1_exit_module - Driver Exit Cleanup Routine
3170 * atl1_exit_module is called just before the driver is removed
3173 static void __exit atl1_exit_module(void)
3175 pci_unregister_driver(&atl1_driver);
3179 * atl1_init_module - Driver Registration Routine
3181 * atl1_init_module is the first routine called when the driver is
3182 * loaded. All it does is register with the PCI subsystem.
3184 static int __init atl1_init_module(void)
3186 return pci_register_driver(&atl1_driver);
3189 module_init(atl1_init_module);
3190 module_exit(atl1_exit_module);
3193 char stat_string[ETH_GSTRING_LEN];
3198 #define ATL1_STAT(m) \
3199 sizeof(((struct atl1_adapter *)0)->m), offsetof(struct atl1_adapter, m)
3201 static struct atl1_stats atl1_gstrings_stats[] = {
3202 {"rx_packets", ATL1_STAT(soft_stats.rx_packets)},
3203 {"tx_packets", ATL1_STAT(soft_stats.tx_packets)},
3204 {"rx_bytes", ATL1_STAT(soft_stats.rx_bytes)},
3205 {"tx_bytes", ATL1_STAT(soft_stats.tx_bytes)},
3206 {"rx_errors", ATL1_STAT(soft_stats.rx_errors)},
3207 {"tx_errors", ATL1_STAT(soft_stats.tx_errors)},
3208 {"rx_dropped", ATL1_STAT(net_stats.rx_dropped)},
3209 {"tx_dropped", ATL1_STAT(net_stats.tx_dropped)},
3210 {"multicast", ATL1_STAT(soft_stats.multicast)},
3211 {"collisions", ATL1_STAT(soft_stats.collisions)},
3212 {"rx_length_errors", ATL1_STAT(soft_stats.rx_length_errors)},
3213 {"rx_over_errors", ATL1_STAT(soft_stats.rx_missed_errors)},
3214 {"rx_crc_errors", ATL1_STAT(soft_stats.rx_crc_errors)},
3215 {"rx_frame_errors", ATL1_STAT(soft_stats.rx_frame_errors)},
3216 {"rx_fifo_errors", ATL1_STAT(soft_stats.rx_fifo_errors)},
3217 {"rx_missed_errors", ATL1_STAT(soft_stats.rx_missed_errors)},
3218 {"tx_aborted_errors", ATL1_STAT(soft_stats.tx_aborted_errors)},
3219 {"tx_carrier_errors", ATL1_STAT(soft_stats.tx_carrier_errors)},
3220 {"tx_fifo_errors", ATL1_STAT(soft_stats.tx_fifo_errors)},
3221 {"tx_window_errors", ATL1_STAT(soft_stats.tx_window_errors)},
3222 {"tx_abort_exce_coll", ATL1_STAT(soft_stats.excecol)},
3223 {"tx_abort_late_coll", ATL1_STAT(soft_stats.latecol)},
3224 {"tx_deferred_ok", ATL1_STAT(soft_stats.deffer)},
3225 {"tx_single_coll_ok", ATL1_STAT(soft_stats.scc)},
3226 {"tx_multi_coll_ok", ATL1_STAT(soft_stats.mcc)},
3227 {"tx_underun", ATL1_STAT(soft_stats.tx_underun)},
3228 {"tx_trunc", ATL1_STAT(soft_stats.tx_trunc)},
3229 {"tx_pause", ATL1_STAT(soft_stats.tx_pause)},
3230 {"rx_pause", ATL1_STAT(soft_stats.rx_pause)},
3231 {"rx_rrd_ov", ATL1_STAT(soft_stats.rx_rrd_ov)},
3232 {"rx_trunc", ATL1_STAT(soft_stats.rx_trunc)}
3235 static void atl1_get_ethtool_stats(struct net_device *netdev,
3236 struct ethtool_stats *stats, u64 *data)
3238 struct atl1_adapter *adapter = netdev_priv(netdev);
3242 for (i = 0; i < ARRAY_SIZE(atl1_gstrings_stats); i++) {
3243 p = (char *)adapter+atl1_gstrings_stats[i].stat_offset;
3244 data[i] = (atl1_gstrings_stats[i].sizeof_stat ==
3245 sizeof(u64)) ? *(u64 *)p : *(u32 *)p;
3250 static int atl1_get_sset_count(struct net_device *netdev, int sset)
3254 return ARRAY_SIZE(atl1_gstrings_stats);
3260 static int atl1_get_settings(struct net_device *netdev,
3261 struct ethtool_cmd *ecmd)
3263 struct atl1_adapter *adapter = netdev_priv(netdev);
3264 struct atl1_hw *hw = &adapter->hw;
3266 ecmd->supported = (SUPPORTED_10baseT_Half |
3267 SUPPORTED_10baseT_Full |
3268 SUPPORTED_100baseT_Half |
3269 SUPPORTED_100baseT_Full |
3270 SUPPORTED_1000baseT_Full |
3271 SUPPORTED_Autoneg | SUPPORTED_TP);
3272 ecmd->advertising = ADVERTISED_TP;
3273 if (hw->media_type == MEDIA_TYPE_AUTO_SENSOR ||
3274 hw->media_type == MEDIA_TYPE_1000M_FULL) {
3275 ecmd->advertising |= ADVERTISED_Autoneg;
3276 if (hw->media_type == MEDIA_TYPE_AUTO_SENSOR) {
3277 ecmd->advertising |= ADVERTISED_Autoneg;
3278 ecmd->advertising |=
3279 (ADVERTISED_10baseT_Half |
3280 ADVERTISED_10baseT_Full |
3281 ADVERTISED_100baseT_Half |
3282 ADVERTISED_100baseT_Full |
3283 ADVERTISED_1000baseT_Full);
3285 ecmd->advertising |= (ADVERTISED_1000baseT_Full);
3287 ecmd->port = PORT_TP;
3288 ecmd->phy_address = 0;
3289 ecmd->transceiver = XCVR_INTERNAL;
3291 if (netif_carrier_ok(adapter->netdev)) {
3292 u16 link_speed, link_duplex;
3293 atl1_get_speed_and_duplex(hw, &link_speed, &link_duplex);
3294 ecmd->speed = link_speed;
3295 if (link_duplex == FULL_DUPLEX)
3296 ecmd->duplex = DUPLEX_FULL;
3298 ecmd->duplex = DUPLEX_HALF;
3303 if (hw->media_type == MEDIA_TYPE_AUTO_SENSOR ||
3304 hw->media_type == MEDIA_TYPE_1000M_FULL)
3305 ecmd->autoneg = AUTONEG_ENABLE;
3307 ecmd->autoneg = AUTONEG_DISABLE;
3312 static int atl1_set_settings(struct net_device *netdev,
3313 struct ethtool_cmd *ecmd)
3315 struct atl1_adapter *adapter = netdev_priv(netdev);
3316 struct atl1_hw *hw = &adapter->hw;
3319 u16 old_media_type = hw->media_type;
3321 if (netif_running(adapter->netdev)) {
3322 if (netif_msg_link(adapter))
3323 dev_dbg(&adapter->pdev->dev,
3324 "ethtool shutting down adapter\n");
3328 if (ecmd->autoneg == AUTONEG_ENABLE)
3329 hw->media_type = MEDIA_TYPE_AUTO_SENSOR;
3331 if (ecmd->speed == SPEED_1000) {
3332 if (ecmd->duplex != DUPLEX_FULL) {
3333 if (netif_msg_link(adapter))
3334 dev_warn(&adapter->pdev->dev,
3335 "1000M half is invalid\n");
3339 hw->media_type = MEDIA_TYPE_1000M_FULL;
3340 } else if (ecmd->speed == SPEED_100) {
3341 if (ecmd->duplex == DUPLEX_FULL)
3342 hw->media_type = MEDIA_TYPE_100M_FULL;
3344 hw->media_type = MEDIA_TYPE_100M_HALF;
3346 if (ecmd->duplex == DUPLEX_FULL)
3347 hw->media_type = MEDIA_TYPE_10M_FULL;
3349 hw->media_type = MEDIA_TYPE_10M_HALF;
3352 switch (hw->media_type) {
3353 case MEDIA_TYPE_AUTO_SENSOR:
3355 ADVERTISED_10baseT_Half |
3356 ADVERTISED_10baseT_Full |
3357 ADVERTISED_100baseT_Half |
3358 ADVERTISED_100baseT_Full |
3359 ADVERTISED_1000baseT_Full |
3360 ADVERTISED_Autoneg | ADVERTISED_TP;
3362 case MEDIA_TYPE_1000M_FULL:
3364 ADVERTISED_1000baseT_Full |
3365 ADVERTISED_Autoneg | ADVERTISED_TP;
3368 ecmd->advertising = 0;
3371 if (atl1_phy_setup_autoneg_adv(hw)) {
3373 if (netif_msg_link(adapter))
3374 dev_warn(&adapter->pdev->dev,
3375 "invalid ethtool speed/duplex setting\n");
3378 if (hw->media_type == MEDIA_TYPE_AUTO_SENSOR ||
3379 hw->media_type == MEDIA_TYPE_1000M_FULL)
3380 phy_data = MII_CR_RESET | MII_CR_AUTO_NEG_EN;
3382 switch (hw->media_type) {
3383 case MEDIA_TYPE_100M_FULL:
3385 MII_CR_FULL_DUPLEX | MII_CR_SPEED_100 |
3388 case MEDIA_TYPE_100M_HALF:
3389 phy_data = MII_CR_SPEED_100 | MII_CR_RESET;
3391 case MEDIA_TYPE_10M_FULL:
3393 MII_CR_FULL_DUPLEX | MII_CR_SPEED_10 | MII_CR_RESET;
3396 /* MEDIA_TYPE_10M_HALF: */
3397 phy_data = MII_CR_SPEED_10 | MII_CR_RESET;
3401 atl1_write_phy_reg(hw, MII_BMCR, phy_data);
3404 hw->media_type = old_media_type;
3406 if (netif_running(adapter->netdev)) {
3407 if (netif_msg_link(adapter))
3408 dev_dbg(&adapter->pdev->dev,
3409 "ethtool starting adapter\n");
3411 } else if (!ret_val) {
3412 if (netif_msg_link(adapter))
3413 dev_dbg(&adapter->pdev->dev,
3414 "ethtool resetting adapter\n");
3415 atl1_reset(adapter);
3420 static void atl1_get_drvinfo(struct net_device *netdev,
3421 struct ethtool_drvinfo *drvinfo)
3423 struct atl1_adapter *adapter = netdev_priv(netdev);
3425 strncpy(drvinfo->driver, ATLX_DRIVER_NAME, sizeof(drvinfo->driver));
3426 strncpy(drvinfo->version, ATLX_DRIVER_VERSION,
3427 sizeof(drvinfo->version));
3428 strncpy(drvinfo->fw_version, "N/A", sizeof(drvinfo->fw_version));
3429 strncpy(drvinfo->bus_info, pci_name(adapter->pdev),
3430 sizeof(drvinfo->bus_info));
3431 drvinfo->eedump_len = ATL1_EEDUMP_LEN;
3434 static void atl1_get_wol(struct net_device *netdev,
3435 struct ethtool_wolinfo *wol)
3437 struct atl1_adapter *adapter = netdev_priv(netdev);
3439 wol->supported = WAKE_UCAST | WAKE_MCAST | WAKE_BCAST | WAKE_MAGIC;
3441 if (adapter->wol & ATLX_WUFC_EX)
3442 wol->wolopts |= WAKE_UCAST;
3443 if (adapter->wol & ATLX_WUFC_MC)
3444 wol->wolopts |= WAKE_MCAST;
3445 if (adapter->wol & ATLX_WUFC_BC)
3446 wol->wolopts |= WAKE_BCAST;
3447 if (adapter->wol & ATLX_WUFC_MAG)
3448 wol->wolopts |= WAKE_MAGIC;
3452 static int atl1_set_wol(struct net_device *netdev,
3453 struct ethtool_wolinfo *wol)
3455 struct atl1_adapter *adapter = netdev_priv(netdev);
3457 if (wol->wolopts & (WAKE_PHY | WAKE_ARP | WAKE_MAGICSECURE))
3460 if (wol->wolopts & WAKE_UCAST)
3461 adapter->wol |= ATLX_WUFC_EX;
3462 if (wol->wolopts & WAKE_MCAST)
3463 adapter->wol |= ATLX_WUFC_MC;
3464 if (wol->wolopts & WAKE_BCAST)
3465 adapter->wol |= ATLX_WUFC_BC;
3466 if (wol->wolopts & WAKE_MAGIC)
3467 adapter->wol |= ATLX_WUFC_MAG;
3471 static u32 atl1_get_msglevel(struct net_device *netdev)
3473 struct atl1_adapter *adapter = netdev_priv(netdev);
3474 return adapter->msg_enable;
3477 static void atl1_set_msglevel(struct net_device *netdev, u32 value)
3479 struct atl1_adapter *adapter = netdev_priv(netdev);
3480 adapter->msg_enable = value;
3483 static int atl1_get_regs_len(struct net_device *netdev)
3485 return ATL1_REG_COUNT * sizeof(u32);
3488 static void atl1_get_regs(struct net_device *netdev, struct ethtool_regs *regs,
3491 struct atl1_adapter *adapter = netdev_priv(netdev);
3492 struct atl1_hw *hw = &adapter->hw;
3496 for (i = 0; i < ATL1_REG_COUNT; i++) {
3498 * This switch statement avoids reserved regions
3499 * of register space.
3524 /* reserved region; don't read it */
3528 /* unreserved region */
3529 regbuf[i] = ioread32(hw->hw_addr + (i * sizeof(u32)));
3534 static void atl1_get_ringparam(struct net_device *netdev,
3535 struct ethtool_ringparam *ring)
3537 struct atl1_adapter *adapter = netdev_priv(netdev);
3538 struct atl1_tpd_ring *txdr = &adapter->tpd_ring;
3539 struct atl1_rfd_ring *rxdr = &adapter->rfd_ring;
3541 ring->rx_max_pending = ATL1_MAX_RFD;
3542 ring->tx_max_pending = ATL1_MAX_TPD;
3543 ring->rx_mini_max_pending = 0;
3544 ring->rx_jumbo_max_pending = 0;
3545 ring->rx_pending = rxdr->count;
3546 ring->tx_pending = txdr->count;
3547 ring->rx_mini_pending = 0;
3548 ring->rx_jumbo_pending = 0;
3551 static int atl1_set_ringparam(struct net_device *netdev,
3552 struct ethtool_ringparam *ring)
3554 struct atl1_adapter *adapter = netdev_priv(netdev);
3555 struct atl1_tpd_ring *tpdr = &adapter->tpd_ring;
3556 struct atl1_rrd_ring *rrdr = &adapter->rrd_ring;
3557 struct atl1_rfd_ring *rfdr = &adapter->rfd_ring;
3559 struct atl1_tpd_ring tpd_old, tpd_new;
3560 struct atl1_rfd_ring rfd_old, rfd_new;
3561 struct atl1_rrd_ring rrd_old, rrd_new;
3562 struct atl1_ring_header rhdr_old, rhdr_new;
3565 tpd_old = adapter->tpd_ring;
3566 rfd_old = adapter->rfd_ring;
3567 rrd_old = adapter->rrd_ring;
3568 rhdr_old = adapter->ring_header;
3570 if (netif_running(adapter->netdev))
3573 rfdr->count = (u16) max(ring->rx_pending, (u32) ATL1_MIN_RFD);
3574 rfdr->count = rfdr->count > ATL1_MAX_RFD ? ATL1_MAX_RFD :
3576 rfdr->count = (rfdr->count + 3) & ~3;
3577 rrdr->count = rfdr->count;
3579 tpdr->count = (u16) max(ring->tx_pending, (u32) ATL1_MIN_TPD);
3580 tpdr->count = tpdr->count > ATL1_MAX_TPD ? ATL1_MAX_TPD :
3582 tpdr->count = (tpdr->count + 3) & ~3;
3584 if (netif_running(adapter->netdev)) {
3585 /* try to get new resources before deleting old */
3586 err = atl1_setup_ring_resources(adapter);
3588 goto err_setup_ring;
3591 * save the new, restore the old in order to free it,
3592 * then restore the new back again
3595 rfd_new = adapter->rfd_ring;
3596 rrd_new = adapter->rrd_ring;
3597 tpd_new = adapter->tpd_ring;
3598 rhdr_new = adapter->ring_header;
3599 adapter->rfd_ring = rfd_old;
3600 adapter->rrd_ring = rrd_old;
3601 adapter->tpd_ring = tpd_old;
3602 adapter->ring_header = rhdr_old;
3603 atl1_free_ring_resources(adapter);
3604 adapter->rfd_ring = rfd_new;
3605 adapter->rrd_ring = rrd_new;
3606 adapter->tpd_ring = tpd_new;
3607 adapter->ring_header = rhdr_new;
3609 err = atl1_up(adapter);
3616 adapter->rfd_ring = rfd_old;
3617 adapter->rrd_ring = rrd_old;
3618 adapter->tpd_ring = tpd_old;
3619 adapter->ring_header = rhdr_old;
3624 static void atl1_get_pauseparam(struct net_device *netdev,
3625 struct ethtool_pauseparam *epause)
3627 struct atl1_adapter *adapter = netdev_priv(netdev);
3628 struct atl1_hw *hw = &adapter->hw;
3630 if (hw->media_type == MEDIA_TYPE_AUTO_SENSOR ||
3631 hw->media_type == MEDIA_TYPE_1000M_FULL) {
3632 epause->autoneg = AUTONEG_ENABLE;
3634 epause->autoneg = AUTONEG_DISABLE;
3636 epause->rx_pause = 1;
3637 epause->tx_pause = 1;
3640 static int atl1_set_pauseparam(struct net_device *netdev,
3641 struct ethtool_pauseparam *epause)
3643 struct atl1_adapter *adapter = netdev_priv(netdev);
3644 struct atl1_hw *hw = &adapter->hw;
3646 if (hw->media_type == MEDIA_TYPE_AUTO_SENSOR ||
3647 hw->media_type == MEDIA_TYPE_1000M_FULL) {
3648 epause->autoneg = AUTONEG_ENABLE;
3650 epause->autoneg = AUTONEG_DISABLE;
3653 epause->rx_pause = 1;
3654 epause->tx_pause = 1;
3659 /* FIXME: is this right? -- CHS */
3660 static u32 atl1_get_rx_csum(struct net_device *netdev)
3665 static void atl1_get_strings(struct net_device *netdev, u32 stringset,
3671 switch (stringset) {
3673 for (i = 0; i < ARRAY_SIZE(atl1_gstrings_stats); i++) {
3674 memcpy(p, atl1_gstrings_stats[i].stat_string,
3676 p += ETH_GSTRING_LEN;
3682 static int atl1_nway_reset(struct net_device *netdev)
3684 struct atl1_adapter *adapter = netdev_priv(netdev);
3685 struct atl1_hw *hw = &adapter->hw;
3687 if (netif_running(netdev)) {
3691 if (hw->media_type == MEDIA_TYPE_AUTO_SENSOR ||
3692 hw->media_type == MEDIA_TYPE_1000M_FULL) {
3693 phy_data = MII_CR_RESET | MII_CR_AUTO_NEG_EN;
3695 switch (hw->media_type) {
3696 case MEDIA_TYPE_100M_FULL:
3697 phy_data = MII_CR_FULL_DUPLEX |
3698 MII_CR_SPEED_100 | MII_CR_RESET;
3700 case MEDIA_TYPE_100M_HALF:
3701 phy_data = MII_CR_SPEED_100 | MII_CR_RESET;
3703 case MEDIA_TYPE_10M_FULL:
3704 phy_data = MII_CR_FULL_DUPLEX |
3705 MII_CR_SPEED_10 | MII_CR_RESET;
3708 /* MEDIA_TYPE_10M_HALF */
3709 phy_data = MII_CR_SPEED_10 | MII_CR_RESET;
3712 atl1_write_phy_reg(hw, MII_BMCR, phy_data);
3718 const struct ethtool_ops atl1_ethtool_ops = {
3719 .get_settings = atl1_get_settings,
3720 .set_settings = atl1_set_settings,
3721 .get_drvinfo = atl1_get_drvinfo,
3722 .get_wol = atl1_get_wol,
3723 .set_wol = atl1_set_wol,
3724 .get_msglevel = atl1_get_msglevel,
3725 .set_msglevel = atl1_set_msglevel,
3726 .get_regs_len = atl1_get_regs_len,
3727 .get_regs = atl1_get_regs,
3728 .get_ringparam = atl1_get_ringparam,
3729 .set_ringparam = atl1_set_ringparam,
3730 .get_pauseparam = atl1_get_pauseparam,
3731 .set_pauseparam = atl1_set_pauseparam,
3732 .get_rx_csum = atl1_get_rx_csum,
3733 .set_tx_csum = ethtool_op_set_tx_hw_csum,
3734 .get_link = ethtool_op_get_link,
3735 .set_sg = ethtool_op_set_sg,
3736 .get_strings = atl1_get_strings,
3737 .nway_reset = atl1_nway_reset,
3738 .get_ethtool_stats = atl1_get_ethtool_stats,
3739 .get_sset_count = atl1_get_sset_count,
3740 .set_tso = ethtool_op_set_tso,