2 * Ethernet driver for the Atmel AT91RM9200 (Thunder)
4 * Copyright (C) 2003 SAN People (Pty) Ltd
6 * Based on an earlier Atmel EMAC macrocell driver by Atmel and Lineo Inc.
7 * Initial version by Rick Bronson 01/11/2003
9 * Intel LXT971A PHY support by Christopher Bahns & David Knickerbocker
10 * (Polaroid Corporation)
12 * Realtek RTL8201(B)L PHY support by Roman Avramenko <roman@imsystems.ru>
14 * This program is free software; you can redistribute it and/or
15 * modify it under the terms of the GNU General Public License
16 * as published by the Free Software Foundation; either version
17 * 2 of the License, or (at your option) any later version.
20 #include <linux/module.h>
21 #include <linux/init.h>
22 #include <linux/config.h>
23 #include <linux/mii.h>
24 #include <linux/netdevice.h>
25 #include <linux/etherdevice.h>
26 #include <linux/skbuff.h>
27 #include <linux/dma-mapping.h>
28 #include <linux/ethtool.h>
29 #include <linux/platform_device.h>
30 #include <linux/clk.h>
33 #include <asm/uaccess.h>
34 #include <asm/mach-types.h>
36 #include <asm/arch/at91rm9200_emac.h>
37 #include <asm/arch/gpio.h>
38 #include <asm/arch/board.h>
40 #include "at91_ether.h"
42 #define DRV_NAME "at91_ether"
43 #define DRV_VERSION "1.0"
45 static struct net_device *at91_dev;
46 static struct clk *ether_clk;
48 static struct timer_list check_timer;
49 #define LINK_POLL_INTERVAL (HZ)
51 /* ..................................................................... */
54 * Read from a EMAC register.
56 static inline unsigned long at91_emac_read(unsigned int reg)
58 void __iomem *emac_base = (void __iomem *)AT91_VA_BASE_EMAC;
60 return __raw_readl(emac_base + reg);
64 * Write to a EMAC register.
66 static inline void at91_emac_write(unsigned int reg, unsigned long value)
68 void __iomem *emac_base = (void __iomem *)AT91_VA_BASE_EMAC;
70 __raw_writel(value, emac_base + reg);
73 /* ........................... PHY INTERFACE ........................... */
76 * Enable the MDIO bit in MAC control register
77 * When not called from an interrupt-handler, access to the PHY must be
78 * protected by a spinlock.
80 static void enable_mdi(void)
84 ctl = at91_emac_read(AT91_EMAC_CTL);
85 at91_emac_write(AT91_EMAC_CTL, ctl | AT91_EMAC_MPE); /* enable management port */
89 * Disable the MDIO bit in the MAC control register
91 static void disable_mdi(void)
95 ctl = at91_emac_read(AT91_EMAC_CTL);
96 at91_emac_write(AT91_EMAC_CTL, ctl & ~AT91_EMAC_MPE); /* disable management port */
100 * Wait until the PHY operation is complete.
102 static inline void at91_phy_wait(void) {
103 unsigned long timeout = jiffies + 2;
105 while (!(at91_emac_read(AT91_EMAC_SR) & AT91_EMAC_SR_IDLE)) {
106 if (time_after(jiffies, timeout)) {
107 printk("at91_ether: MIO timeout\n");
115 * Write value to the a PHY register
116 * Note: MDI interface is assumed to already have been enabled.
118 static void write_phy(unsigned char phy_addr, unsigned char address, unsigned int value)
120 at91_emac_write(AT91_EMAC_MAN, AT91_EMAC_MAN_802_3 | AT91_EMAC_RW_W
121 | ((phy_addr & 0x1f) << 23) | (address << 18) | (value & AT91_EMAC_DATA));
123 /* Wait until IDLE bit in Network Status register is cleared */
128 * Read value stored in a PHY register.
129 * Note: MDI interface is assumed to already have been enabled.
131 static void read_phy(unsigned char phy_addr, unsigned char address, unsigned int *value)
133 at91_emac_write(AT91_EMAC_MAN, AT91_EMAC_MAN_802_3 | AT91_EMAC_RW_R
134 | ((phy_addr & 0x1f) << 23) | (address << 18));
136 /* Wait until IDLE bit in Network Status register is cleared */
139 *value = at91_emac_read(AT91_EMAC_MAN) & AT91_EMAC_DATA;
142 /* ........................... PHY MANAGEMENT .......................... */
145 * Access the PHY to determine the current link speed and mode, and update the
147 * If no link or auto-negotiation is busy, then no changes are made.
149 static void update_linkspeed(struct net_device *dev, int silent)
151 struct at91_private *lp = (struct at91_private *) dev->priv;
152 unsigned int bmsr, bmcr, lpa, mac_cfg;
153 unsigned int speed, duplex;
155 if (!mii_link_ok(&lp->mii)) { /* no link */
156 netif_carrier_off(dev);
158 printk(KERN_INFO "%s: Link down.\n", dev->name);
162 /* Link up, or auto-negotiation still in progress */
163 read_phy(lp->phy_address, MII_BMSR, &bmsr);
164 read_phy(lp->phy_address, MII_BMCR, &bmcr);
165 if (bmcr & BMCR_ANENABLE) { /* AutoNegotiation is enabled */
166 if (!(bmsr & BMSR_ANEGCOMPLETE))
167 return; /* Do nothing - another interrupt generated when negotiation complete */
169 read_phy(lp->phy_address, MII_LPA, &lpa);
170 if ((lpa & LPA_100FULL) || (lpa & LPA_100HALF)) speed = SPEED_100;
171 else speed = SPEED_10;
172 if ((lpa & LPA_100FULL) || (lpa & LPA_10FULL)) duplex = DUPLEX_FULL;
173 else duplex = DUPLEX_HALF;
175 speed = (bmcr & BMCR_SPEED100) ? SPEED_100 : SPEED_10;
176 duplex = (bmcr & BMCR_FULLDPLX) ? DUPLEX_FULL : DUPLEX_HALF;
180 mac_cfg = at91_emac_read(AT91_EMAC_CFG) & ~(AT91_EMAC_SPD | AT91_EMAC_FD);
181 if (speed == SPEED_100) {
182 if (duplex == DUPLEX_FULL) /* 100 Full Duplex */
183 mac_cfg |= AT91_EMAC_SPD | AT91_EMAC_FD;
184 else /* 100 Half Duplex */
185 mac_cfg |= AT91_EMAC_SPD;
187 if (duplex == DUPLEX_FULL) /* 10 Full Duplex */
188 mac_cfg |= AT91_EMAC_FD;
189 else {} /* 10 Half Duplex */
191 at91_emac_write(AT91_EMAC_CFG, mac_cfg);
194 printk(KERN_INFO "%s: Link now %i-%s\n", dev->name, speed, (duplex == DUPLEX_FULL) ? "FullDuplex" : "HalfDuplex");
195 netif_carrier_on(dev);
199 * Handle interrupts from the PHY
201 static irqreturn_t at91ether_phy_interrupt(int irq, void *dev_id, struct pt_regs *regs)
203 struct net_device *dev = (struct net_device *) dev_id;
204 struct at91_private *lp = (struct at91_private *) dev->priv;
208 * This hander is triggered on both edges, but the PHY chips expect
209 * level-triggering. We therefore have to check if the PHY actually has
213 if ((lp->phy_type == MII_DM9161_ID) || (lp->phy_type == MII_DM9161A_ID)) {
214 read_phy(lp->phy_address, MII_DSINTR_REG, &phy); /* ack interrupt in Davicom PHY */
215 if (!(phy & (1 << 0)))
218 else if (lp->phy_type == MII_LXT971A_ID) {
219 read_phy(lp->phy_address, MII_ISINTS_REG, &phy); /* ack interrupt in Intel PHY */
220 if (!(phy & (1 << 2)))
223 else if (lp->phy_type == MII_BCM5221_ID) {
224 read_phy(lp->phy_address, MII_BCMINTR_REG, &phy); /* ack interrupt in Broadcom PHY */
225 if (!(phy & (1 << 0)))
228 else if (lp->phy_type == MII_KS8721_ID) {
229 read_phy(lp->phy_address, MII_TPISTATUS, &phy); /* ack interrupt in Micrel PHY */
230 if (!(phy & ((1 << 2) | 1)))
234 update_linkspeed(dev, 0);
243 * Initialize and enable the PHY interrupt for link-state changes
245 static void enable_phyirq(struct net_device *dev)
247 struct at91_private *lp = (struct at91_private *) dev->priv;
248 unsigned int dsintr, irq_number;
251 irq_number = lp->board_data.phy_irq_pin;
254 * PHY doesn't have an IRQ pin (RTL8201, DP83847, AC101L),
255 * or board does not have it connected.
257 check_timer.expires = jiffies + LINK_POLL_INTERVAL;
258 add_timer(&check_timer);
262 status = request_irq(irq_number, at91ether_phy_interrupt, 0, dev->name, dev);
264 printk(KERN_ERR "at91_ether: PHY IRQ %d request failed - status %d!\n", irq_number, status);
268 spin_lock_irq(&lp->lock);
271 if ((lp->phy_type == MII_DM9161_ID) || (lp->phy_type == MII_DM9161A_ID)) { /* for Davicom PHY */
272 read_phy(lp->phy_address, MII_DSINTR_REG, &dsintr);
273 dsintr = dsintr & ~0xf00; /* clear bits 8..11 */
274 write_phy(lp->phy_address, MII_DSINTR_REG, dsintr);
276 else if (lp->phy_type == MII_LXT971A_ID) { /* for Intel PHY */
277 read_phy(lp->phy_address, MII_ISINTE_REG, &dsintr);
278 dsintr = dsintr | 0xf2; /* set bits 1, 4..7 */
279 write_phy(lp->phy_address, MII_ISINTE_REG, dsintr);
281 else if (lp->phy_type == MII_BCM5221_ID) { /* for Broadcom PHY */
282 dsintr = (1 << 15) | ( 1 << 14);
283 write_phy(lp->phy_address, MII_BCMINTR_REG, dsintr);
285 else if (lp->phy_type == MII_KS8721_ID) { /* for Micrel PHY */
286 dsintr = (1 << 10) | ( 1 << 8);
287 write_phy(lp->phy_address, MII_TPISTATUS, dsintr);
291 spin_unlock_irq(&lp->lock);
295 * Disable the PHY interrupt
297 static void disable_phyirq(struct net_device *dev)
299 struct at91_private *lp = (struct at91_private *) dev->priv;
301 unsigned int irq_number;
303 irq_number = lp->board_data.phy_irq_pin;
305 del_timer_sync(&check_timer);
309 spin_lock_irq(&lp->lock);
312 if ((lp->phy_type == MII_DM9161_ID) || (lp->phy_type == MII_DM9161A_ID)) { /* for Davicom PHY */
313 read_phy(lp->phy_address, MII_DSINTR_REG, &dsintr);
314 dsintr = dsintr | 0xf00; /* set bits 8..11 */
315 write_phy(lp->phy_address, MII_DSINTR_REG, dsintr);
317 else if (lp->phy_type == MII_LXT971A_ID) { /* for Intel PHY */
318 read_phy(lp->phy_address, MII_ISINTE_REG, &dsintr);
319 dsintr = dsintr & ~0xf2; /* clear bits 1, 4..7 */
320 write_phy(lp->phy_address, MII_ISINTE_REG, dsintr);
322 else if (lp->phy_type == MII_BCM5221_ID) { /* for Broadcom PHY */
323 read_phy(lp->phy_address, MII_BCMINTR_REG, &dsintr);
325 write_phy(lp->phy_address, MII_BCMINTR_REG, dsintr);
327 else if (lp->phy_type == MII_KS8721_ID) { /* for Micrel PHY */
328 read_phy(lp->phy_address, MII_TPISTATUS, &dsintr);
329 dsintr = ~((1 << 10) | (1 << 8));
330 write_phy(lp->phy_address, MII_TPISTATUS, dsintr);
334 spin_unlock_irq(&lp->lock);
336 free_irq(irq_number, dev); /* Free interrupt handler */
340 * Perform a software reset of the PHY.
343 static void reset_phy(struct net_device *dev)
345 struct at91_private *lp = (struct at91_private *) dev->priv;
348 spin_lock_irq(&lp->lock);
351 /* Perform PHY reset */
352 write_phy(lp->phy_address, MII_BMCR, BMCR_RESET);
354 /* Wait until PHY reset is complete */
356 read_phy(lp->phy_address, MII_BMCR, &bmcr);
357 } while (!(bmcr && BMCR_RESET));
360 spin_unlock_irq(&lp->lock);
364 static void at91ether_check_link(unsigned long dev_id)
366 struct net_device *dev = (struct net_device *) dev_id;
369 update_linkspeed(dev, 1);
372 check_timer.expires = jiffies + LINK_POLL_INTERVAL;
373 add_timer(&check_timer);
376 /* ......................... ADDRESS MANAGEMENT ........................ */
379 * NOTE: Your bootloader must always set the MAC address correctly before
380 * booting into Linux.
382 * - It must always set the MAC address after reset, even if it doesn't
383 * happen to access the Ethernet while it's booting. Some versions of
384 * U-Boot on the AT91RM9200-DK do not do this.
386 * - Likewise it must store the addresses in the correct byte order.
387 * MicroMonitor (uMon) on the CSB337 does this incorrectly (and
388 * continues to do so, for bug-compatibility).
391 static short __init unpack_mac_address(struct net_device *dev, unsigned int hi, unsigned int lo)
395 if (machine_is_csb337()) {
396 addr[5] = (lo & 0xff); /* The CSB337 bootloader stores the MAC the wrong-way around */
397 addr[4] = (lo & 0xff00) >> 8;
398 addr[3] = (lo & 0xff0000) >> 16;
399 addr[2] = (lo & 0xff000000) >> 24;
400 addr[1] = (hi & 0xff);
401 addr[0] = (hi & 0xff00) >> 8;
404 addr[0] = (lo & 0xff);
405 addr[1] = (lo & 0xff00) >> 8;
406 addr[2] = (lo & 0xff0000) >> 16;
407 addr[3] = (lo & 0xff000000) >> 24;
408 addr[4] = (hi & 0xff);
409 addr[5] = (hi & 0xff00) >> 8;
412 if (is_valid_ether_addr(addr)) {
413 memcpy(dev->dev_addr, &addr, 6);
420 * Set the ethernet MAC address in dev->dev_addr
422 static void __init get_mac_address(struct net_device *dev)
424 /* Check Specific-Address 1 */
425 if (unpack_mac_address(dev, at91_emac_read(AT91_EMAC_SA1H), at91_emac_read(AT91_EMAC_SA1L)))
427 /* Check Specific-Address 2 */
428 if (unpack_mac_address(dev, at91_emac_read(AT91_EMAC_SA2H), at91_emac_read(AT91_EMAC_SA2L)))
430 /* Check Specific-Address 3 */
431 if (unpack_mac_address(dev, at91_emac_read(AT91_EMAC_SA3H), at91_emac_read(AT91_EMAC_SA3L)))
433 /* Check Specific-Address 4 */
434 if (unpack_mac_address(dev, at91_emac_read(AT91_EMAC_SA4H), at91_emac_read(AT91_EMAC_SA4L)))
437 printk(KERN_ERR "at91_ether: Your bootloader did not configure a MAC address.\n");
441 * Program the hardware MAC address from dev->dev_addr.
443 static void update_mac_address(struct net_device *dev)
445 at91_emac_write(AT91_EMAC_SA1L, (dev->dev_addr[3] << 24) | (dev->dev_addr[2] << 16) | (dev->dev_addr[1] << 8) | (dev->dev_addr[0]));
446 at91_emac_write(AT91_EMAC_SA1H, (dev->dev_addr[5] << 8) | (dev->dev_addr[4]));
448 at91_emac_write(AT91_EMAC_SA2L, 0);
449 at91_emac_write(AT91_EMAC_SA2H, 0);
453 * Store the new hardware address in dev->dev_addr, and update the MAC.
455 static int set_mac_address(struct net_device *dev, void* addr)
457 struct sockaddr *address = addr;
459 if (!is_valid_ether_addr(address->sa_data))
460 return -EADDRNOTAVAIL;
462 memcpy(dev->dev_addr, address->sa_data, dev->addr_len);
463 update_mac_address(dev);
465 printk("%s: Setting MAC address to %02x:%02x:%02x:%02x:%02x:%02x\n", dev->name,
466 dev->dev_addr[0], dev->dev_addr[1], dev->dev_addr[2],
467 dev->dev_addr[3], dev->dev_addr[4], dev->dev_addr[5]);
472 static int inline hash_bit_value(int bitnr, __u8 *addr)
474 if (addr[bitnr / 8] & (1 << (bitnr % 8)))
480 * The hash address register is 64 bits long and takes up two locations in the memory map.
481 * The least significant bits are stored in EMAC_HSL and the most significant
484 * The unicast hash enable and the multicast hash enable bits in the network configuration
485 * register enable the reception of hash matched frames. The destination address is
486 * reduced to a 6 bit index into the 64 bit hash register using the following hash function.
487 * The hash function is an exclusive or of every sixth bit of the destination address.
488 * hash_index[5] = da[5] ^ da[11] ^ da[17] ^ da[23] ^ da[29] ^ da[35] ^ da[41] ^ da[47]
489 * hash_index[4] = da[4] ^ da[10] ^ da[16] ^ da[22] ^ da[28] ^ da[34] ^ da[40] ^ da[46]
490 * hash_index[3] = da[3] ^ da[09] ^ da[15] ^ da[21] ^ da[27] ^ da[33] ^ da[39] ^ da[45]
491 * hash_index[2] = da[2] ^ da[08] ^ da[14] ^ da[20] ^ da[26] ^ da[32] ^ da[38] ^ da[44]
492 * hash_index[1] = da[1] ^ da[07] ^ da[13] ^ da[19] ^ da[25] ^ da[31] ^ da[37] ^ da[43]
493 * hash_index[0] = da[0] ^ da[06] ^ da[12] ^ da[18] ^ da[24] ^ da[30] ^ da[36] ^ da[42]
494 * da[0] represents the least significant bit of the first byte received, that is, the multicast/
495 * unicast indicator, and da[47] represents the most significant bit of the last byte
497 * If the hash index points to a bit that is set in the hash register then the frame will be
498 * matched according to whether the frame is multicast or unicast.
499 * A multicast match will be signalled if the multicast hash enable bit is set, da[0] is 1 and
500 * the hash index points to a bit set in the hash register.
501 * A unicast match will be signalled if the unicast hash enable bit is set, da[0] is 0 and the
502 * hash index points to a bit set in the hash register.
503 * To receive all multicast frames, the hash register should be set with all ones and the
504 * multicast hash enable bit should be set in the network configuration register.
508 * Return the hash index value for the specified address.
510 static int hash_get_index(__u8 *addr)
515 for (j = 0; j < 6; j++) {
516 for (i = 0, bitval = 0; i < 8; i++)
517 bitval ^= hash_bit_value(i*6 + j, addr);
519 hash_index |= (bitval << j);
526 * Add multicast addresses to the internal multicast-hash table.
528 static void at91ether_sethashtable(struct net_device *dev)
530 struct dev_mc_list *curr;
531 unsigned long mc_filter[2];
532 unsigned int i, bitnr;
534 mc_filter[0] = mc_filter[1] = 0;
537 for (i = 0; i < dev->mc_count; i++, curr = curr->next) {
538 if (!curr) break; /* unexpected end of list */
540 bitnr = hash_get_index(curr->dmi_addr);
541 mc_filter[bitnr >> 5] |= 1 << (bitnr & 31);
544 at91_emac_write(AT91_EMAC_HSH, mc_filter[0]);
545 at91_emac_write(AT91_EMAC_HSL, mc_filter[1]);
549 * Enable/Disable promiscuous and multicast modes.
551 static void at91ether_set_rx_mode(struct net_device *dev)
555 cfg = at91_emac_read(AT91_EMAC_CFG);
557 if (dev->flags & IFF_PROMISC) /* Enable promiscuous mode */
558 cfg |= AT91_EMAC_CAF;
559 else if (dev->flags & (~IFF_PROMISC)) /* Disable promiscuous mode */
560 cfg &= ~AT91_EMAC_CAF;
562 if (dev->flags & IFF_ALLMULTI) { /* Enable all multicast mode */
563 at91_emac_write(AT91_EMAC_HSH, -1);
564 at91_emac_write(AT91_EMAC_HSL, -1);
565 cfg |= AT91_EMAC_MTI;
566 } else if (dev->mc_count > 0) { /* Enable specific multicasts */
567 at91ether_sethashtable(dev);
568 cfg |= AT91_EMAC_MTI;
569 } else if (dev->flags & (~IFF_ALLMULTI)) { /* Disable all multicast mode */
570 at91_emac_write(AT91_EMAC_HSH, 0);
571 at91_emac_write(AT91_EMAC_HSL, 0);
572 cfg &= ~AT91_EMAC_MTI;
575 at91_emac_write(AT91_EMAC_CFG, cfg);
579 /* ......................... ETHTOOL SUPPORT ........................... */
582 static int mdio_read(struct net_device *dev, int phy_id, int location)
586 read_phy(phy_id, location, &value);
590 static void mdio_write(struct net_device *dev, int phy_id, int location, int value)
592 write_phy(phy_id, location, value);
595 static int at91ether_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
597 struct at91_private *lp = (struct at91_private *) dev->priv;
600 spin_lock_irq(&lp->lock);
603 ret = mii_ethtool_gset(&lp->mii, cmd);
606 spin_unlock_irq(&lp->lock);
608 if (lp->phy_media == PORT_FIBRE) { /* override media type since mii.c doesn't know */
609 cmd->supported = SUPPORTED_FIBRE;
610 cmd->port = PORT_FIBRE;
616 static int at91ether_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
618 struct at91_private *lp = (struct at91_private *) dev->priv;
621 spin_lock_irq(&lp->lock);
624 ret = mii_ethtool_sset(&lp->mii, cmd);
627 spin_unlock_irq(&lp->lock);
632 static int at91ether_nwayreset(struct net_device *dev)
634 struct at91_private *lp = (struct at91_private *) dev->priv;
637 spin_lock_irq(&lp->lock);
640 ret = mii_nway_restart(&lp->mii);
643 spin_unlock_irq(&lp->lock);
648 static void at91ether_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
650 strlcpy(info->driver, DRV_NAME, sizeof(info->driver));
651 strlcpy(info->version, DRV_VERSION, sizeof(info->version));
652 strlcpy(info->bus_info, dev->class_dev.dev->bus_id, sizeof(info->bus_info));
655 static struct ethtool_ops at91ether_ethtool_ops = {
656 .get_settings = at91ether_get_settings,
657 .set_settings = at91ether_set_settings,
658 .get_drvinfo = at91ether_get_drvinfo,
659 .nway_reset = at91ether_nwayreset,
660 .get_link = ethtool_op_get_link,
663 static int at91ether_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
665 struct at91_private *lp = (struct at91_private *) dev->priv;
668 if (!netif_running(dev))
671 spin_lock_irq(&lp->lock);
673 res = generic_mii_ioctl(&lp->mii, if_mii(rq), cmd, NULL);
675 spin_unlock_irq(&lp->lock);
680 /* ................................ MAC ................................ */
683 * Initialize and start the Receiver and Transmit subsystems
685 static void at91ether_start(struct net_device *dev)
687 struct at91_private *lp = (struct at91_private *) dev->priv;
688 struct recv_desc_bufs *dlist, *dlist_phys;
693 dlist_phys = lp->dlist_phys;
695 for (i = 0; i < MAX_RX_DESCR; i++) {
696 dlist->descriptors[i].addr = (unsigned int) &dlist_phys->recv_buf[i][0];
697 dlist->descriptors[i].size = 0;
700 /* Set the Wrap bit on the last descriptor */
701 dlist->descriptors[i-1].addr |= EMAC_DESC_WRAP;
703 /* Reset buffer index */
706 /* Program address of descriptor list in Rx Buffer Queue register */
707 at91_emac_write(AT91_EMAC_RBQP, (unsigned long) dlist_phys);
709 /* Enable Receive and Transmit */
710 ctl = at91_emac_read(AT91_EMAC_CTL);
711 at91_emac_write(AT91_EMAC_CTL, ctl | AT91_EMAC_RE | AT91_EMAC_TE);
715 * Open the ethernet interface
717 static int at91ether_open(struct net_device *dev)
719 struct at91_private *lp = (struct at91_private *) dev->priv;
722 if (!is_valid_ether_addr(dev->dev_addr))
723 return -EADDRNOTAVAIL;
725 clk_enable(ether_clk); /* Re-enable Peripheral clock */
727 /* Clear internal statistics */
728 ctl = at91_emac_read(AT91_EMAC_CTL);
729 at91_emac_write(AT91_EMAC_CTL, ctl | AT91_EMAC_CSR);
731 /* Update the MAC address (incase user has changed it) */
732 update_mac_address(dev);
734 /* Enable PHY interrupt */
737 /* Enable MAC interrupts */
738 at91_emac_write(AT91_EMAC_IER, AT91_EMAC_RCOM | AT91_EMAC_RBNA
739 | AT91_EMAC_TUND | AT91_EMAC_RTRY | AT91_EMAC_TCOM
740 | AT91_EMAC_ROVR | AT91_EMAC_ABT);
742 /* Determine current link speed */
743 spin_lock_irq(&lp->lock);
745 update_linkspeed(dev, 0);
747 spin_unlock_irq(&lp->lock);
749 at91ether_start(dev);
750 netif_start_queue(dev);
755 * Close the interface
757 static int at91ether_close(struct net_device *dev)
761 /* Disable Receiver and Transmitter */
762 ctl = at91_emac_read(AT91_EMAC_CTL);
763 at91_emac_write(AT91_EMAC_CTL, ctl & ~(AT91_EMAC_TE | AT91_EMAC_RE));
765 /* Disable PHY interrupt */
768 /* Disable MAC interrupts */
769 at91_emac_write(AT91_EMAC_IDR, AT91_EMAC_RCOM | AT91_EMAC_RBNA
770 | AT91_EMAC_TUND | AT91_EMAC_RTRY | AT91_EMAC_TCOM
771 | AT91_EMAC_ROVR | AT91_EMAC_ABT);
773 netif_stop_queue(dev);
775 clk_disable(ether_clk); /* Disable Peripheral clock */
783 static int at91ether_tx(struct sk_buff *skb, struct net_device *dev)
785 struct at91_private *lp = (struct at91_private *) dev->priv;
787 if (at91_emac_read(AT91_EMAC_TSR) & AT91_EMAC_TSR_BNQ) {
788 netif_stop_queue(dev);
790 /* Store packet information (to free when Tx completed) */
792 lp->skb_length = skb->len;
793 lp->skb_physaddr = dma_map_single(NULL, skb->data, skb->len, DMA_TO_DEVICE);
794 lp->stats.tx_bytes += skb->len;
796 /* Set address of the data in the Transmit Address register */
797 at91_emac_write(AT91_EMAC_TAR, lp->skb_physaddr);
798 /* Set length of the packet in the Transmit Control register */
799 at91_emac_write(AT91_EMAC_TCR, skb->len);
801 dev->trans_start = jiffies;
803 printk(KERN_ERR "at91_ether.c: at91ether_tx() called, but device is busy!\n");
804 return 1; /* if we return anything but zero, dev.c:1055 calls kfree_skb(skb)
805 on this skb, he also reports -ENETDOWN and printk's, so either
806 we free and return(0) or don't free and return 1 */
813 * Update the current statistics from the internal statistics registers.
815 static struct net_device_stats *at91ether_stats(struct net_device *dev)
817 struct at91_private *lp = (struct at91_private *) dev->priv;
818 int ale, lenerr, seqe, lcol, ecol;
820 if (netif_running(dev)) {
821 lp->stats.rx_packets += at91_emac_read(AT91_EMAC_OK); /* Good frames received */
822 ale = at91_emac_read(AT91_EMAC_ALE);
823 lp->stats.rx_frame_errors += ale; /* Alignment errors */
824 lenerr = at91_emac_read(AT91_EMAC_ELR) + at91_emac_read(AT91_EMAC_USF);
825 lp->stats.rx_length_errors += lenerr; /* Excessive Length or Undersize Frame error */
826 seqe = at91_emac_read(AT91_EMAC_SEQE);
827 lp->stats.rx_crc_errors += seqe; /* CRC error */
828 lp->stats.rx_fifo_errors += at91_emac_read(AT91_EMAC_DRFC); /* Receive buffer not available */
829 lp->stats.rx_errors += (ale + lenerr + seqe
830 + at91_emac_read(AT91_EMAC_CDE) + at91_emac_read(AT91_EMAC_RJB));
832 lp->stats.tx_packets += at91_emac_read(AT91_EMAC_FRA); /* Frames successfully transmitted */
833 lp->stats.tx_fifo_errors += at91_emac_read(AT91_EMAC_TUE); /* Transmit FIFO underruns */
834 lp->stats.tx_carrier_errors += at91_emac_read(AT91_EMAC_CSE); /* Carrier Sense errors */
835 lp->stats.tx_heartbeat_errors += at91_emac_read(AT91_EMAC_SQEE);/* Heartbeat error */
837 lcol = at91_emac_read(AT91_EMAC_LCOL);
838 ecol = at91_emac_read(AT91_EMAC_ECOL);
839 lp->stats.tx_window_errors += lcol; /* Late collisions */
840 lp->stats.tx_aborted_errors += ecol; /* 16 collisions */
842 lp->stats.collisions += (at91_emac_read(AT91_EMAC_SCOL) + at91_emac_read(AT91_EMAC_MCOL) + lcol + ecol);
848 * Extract received frame from buffer descriptors and sent to upper layers.
849 * (Called from interrupt context)
851 static void at91ether_rx(struct net_device *dev)
853 struct at91_private *lp = (struct at91_private *) dev->priv;
854 struct recv_desc_bufs *dlist;
855 unsigned char *p_recv;
860 while (dlist->descriptors[lp->rxBuffIndex].addr & EMAC_DESC_DONE) {
861 p_recv = dlist->recv_buf[lp->rxBuffIndex];
862 pktlen = dlist->descriptors[lp->rxBuffIndex].size & 0x7ff; /* Length of frame including FCS */
863 skb = alloc_skb(pktlen + 2, GFP_ATOMIC);
866 memcpy(skb_put(skb, pktlen), p_recv, pktlen);
869 skb->protocol = eth_type_trans(skb, dev);
871 dev->last_rx = jiffies;
872 lp->stats.rx_bytes += pktlen;
876 lp->stats.rx_dropped += 1;
877 printk(KERN_NOTICE "%s: Memory squeeze, dropping packet.\n", dev->name);
880 if (dlist->descriptors[lp->rxBuffIndex].size & EMAC_MULTICAST)
881 lp->stats.multicast++;
883 dlist->descriptors[lp->rxBuffIndex].addr &= ~EMAC_DESC_DONE; /* reset ownership bit */
884 if (lp->rxBuffIndex == MAX_RX_DESCR-1) /* wrap after last buffer */
892 * MAC interrupt handler
894 static irqreturn_t at91ether_interrupt(int irq, void *dev_id, struct pt_regs *regs)
896 struct net_device *dev = (struct net_device *) dev_id;
897 struct at91_private *lp = (struct at91_private *) dev->priv;
898 unsigned long intstatus, ctl;
900 /* MAC Interrupt Status register indicates what interrupts are pending.
901 It is automatically cleared once read. */
902 intstatus = at91_emac_read(AT91_EMAC_ISR);
904 if (intstatus & AT91_EMAC_RCOM) /* Receive complete */
907 if (intstatus & AT91_EMAC_TCOM) { /* Transmit complete */
908 /* The TCOM bit is set even if the transmission failed. */
909 if (intstatus & (AT91_EMAC_TUND | AT91_EMAC_RTRY))
910 lp->stats.tx_errors += 1;
913 dev_kfree_skb_irq(lp->skb);
915 dma_unmap_single(NULL, lp->skb_physaddr, lp->skb_length, DMA_TO_DEVICE);
917 netif_wake_queue(dev);
920 /* Work-around for Errata #11 */
921 if (intstatus & AT91_EMAC_RBNA) {
922 ctl = at91_emac_read(AT91_EMAC_CTL);
923 at91_emac_write(AT91_EMAC_CTL, ctl & ~AT91_EMAC_RE);
924 at91_emac_write(AT91_EMAC_CTL, ctl | AT91_EMAC_RE);
927 if (intstatus & AT91_EMAC_ROVR)
928 printk("%s: ROVR error\n", dev->name);
934 * Initialize the ethernet interface
936 static int __init at91ether_setup(unsigned long phy_type, unsigned short phy_address, struct platform_device *pdev)
938 struct at91_eth_data *board_data = pdev->dev.platform_data;
939 struct net_device *dev;
940 struct at91_private *lp;
944 if (at91_dev) /* already initialized */
947 dev = alloc_etherdev(sizeof(struct at91_private));
951 dev->base_addr = AT91_VA_BASE_EMAC;
952 dev->irq = AT91_ID_EMAC;
953 SET_MODULE_OWNER(dev);
955 /* Install the interrupt handler */
956 if (request_irq(dev->irq, at91ether_interrupt, 0, dev->name, dev)) {
961 /* Allocate memory for DMA Receive descriptors */
962 lp = (struct at91_private *)dev->priv;
963 lp->dlist = (struct recv_desc_bufs *) dma_alloc_coherent(NULL, sizeof(struct recv_desc_bufs), (dma_addr_t *) &lp->dlist_phys, GFP_KERNEL);
964 if (lp->dlist == NULL) {
965 free_irq(dev->irq, dev);
969 lp->board_data = *board_data;
970 platform_set_drvdata(pdev, dev);
972 spin_lock_init(&lp->lock);
975 dev->open = at91ether_open;
976 dev->stop = at91ether_close;
977 dev->hard_start_xmit = at91ether_tx;
978 dev->get_stats = at91ether_stats;
979 dev->set_multicast_list = at91ether_set_rx_mode;
980 dev->set_mac_address = set_mac_address;
981 dev->ethtool_ops = &at91ether_ethtool_ops;
982 dev->do_ioctl = at91ether_ioctl;
984 SET_NETDEV_DEV(dev, &pdev->dev);
986 get_mac_address(dev); /* Get ethernet address and store it in dev->dev_addr */
987 update_mac_address(dev); /* Program ethernet address into MAC */
989 at91_emac_write(AT91_EMAC_CTL, 0);
991 if (lp->board_data.is_rmii)
992 at91_emac_write(AT91_EMAC_CFG, AT91_EMAC_CLK_DIV32 | AT91_EMAC_BIG | AT91_EMAC_RMII);
994 at91_emac_write(AT91_EMAC_CFG, AT91_EMAC_CLK_DIV32 | AT91_EMAC_BIG);
996 /* Perform PHY-specific initialization */
997 spin_lock_irq(&lp->lock);
999 if ((phy_type == MII_DM9161_ID) || (lp->phy_type == MII_DM9161A_ID)) {
1000 read_phy(phy_address, MII_DSCR_REG, &val);
1001 if ((val & (1 << 10)) == 0) /* DSCR bit 10 is 0 -- fiber mode */
1002 lp->phy_media = PORT_FIBRE;
1003 } else if (machine_is_csb337()) {
1004 /* mix link activity status into LED2 link state */
1005 write_phy(phy_address, MII_LEDCTRL_REG, 0x0d22);
1008 spin_unlock_irq(&lp->lock);
1010 lp->mii.dev = dev; /* Support for ethtool */
1011 lp->mii.mdio_read = mdio_read;
1012 lp->mii.mdio_write = mdio_write;
1013 lp->mii.phy_id = phy_address;
1014 lp->mii.phy_id_mask = 0x1f;
1015 lp->mii.reg_num_mask = 0x1f;
1017 lp->phy_type = phy_type; /* Type of PHY connected */
1018 lp->phy_address = phy_address; /* MDI address of PHY */
1020 /* Register the network interface */
1021 res = register_netdev(dev);
1023 free_irq(dev->irq, dev);
1025 dma_free_coherent(NULL, sizeof(struct recv_desc_bufs), lp->dlist, (dma_addr_t)lp->dlist_phys);
1030 /* Determine current link speed */
1031 spin_lock_irq(&lp->lock);
1033 update_linkspeed(dev, 0);
1035 spin_unlock_irq(&lp->lock);
1036 netif_carrier_off(dev); /* will be enabled in open() */
1038 /* If board has no PHY IRQ, use a timer to poll the PHY */
1039 if (!lp->board_data.phy_irq_pin) {
1040 init_timer(&check_timer);
1041 check_timer.data = (unsigned long)dev;
1042 check_timer.function = at91ether_check_link;
1045 /* Display ethernet banner */
1046 printk(KERN_INFO "%s: AT91 ethernet at 0x%08x int=%d %s%s (%02x:%02x:%02x:%02x:%02x:%02x)\n",
1047 dev->name, (uint) dev->base_addr, dev->irq,
1048 at91_emac_read(AT91_EMAC_CFG) & AT91_EMAC_SPD ? "100-" : "10-",
1049 at91_emac_read(AT91_EMAC_CFG) & AT91_EMAC_FD ? "FullDuplex" : "HalfDuplex",
1050 dev->dev_addr[0], dev->dev_addr[1], dev->dev_addr[2],
1051 dev->dev_addr[3], dev->dev_addr[4], dev->dev_addr[5]);
1052 if ((phy_type == MII_DM9161_ID) || (lp->phy_type == MII_DM9161A_ID))
1053 printk(KERN_INFO "%s: Davicom 9196 PHY %s\n", dev->name, (lp->phy_media == PORT_FIBRE) ? "(Fiber)" : "(Copper)");
1054 else if (phy_type == MII_LXT971A_ID)
1055 printk(KERN_INFO "%s: Intel LXT971A PHY\n", dev->name);
1056 else if (phy_type == MII_RTL8201_ID)
1057 printk(KERN_INFO "%s: Realtek RTL8201(B)L PHY\n", dev->name);
1058 else if (phy_type == MII_BCM5221_ID)
1059 printk(KERN_INFO "%s: Broadcom BCM5221 PHY\n", dev->name);
1060 else if (phy_type == MII_DP83847_ID)
1061 printk(KERN_INFO "%s: National Semiconductor DP83847 PHY\n", dev->name);
1062 else if (phy_type == MII_AC101L_ID)
1063 printk(KERN_INFO "%s: Altima AC101L PHY\n", dev->name);
1064 else if (phy_type == MII_KS8721_ID)
1065 printk(KERN_INFO "%s: Micrel KS8721 PHY\n", dev->name);
1071 * Detect MAC and PHY and perform initialization
1073 static int __init at91ether_probe(struct platform_device *pdev)
1075 unsigned int phyid1, phyid2;
1077 unsigned long phy_id;
1078 unsigned short phy_address = 0;
1080 ether_clk = clk_get(&pdev->dev, "ether_clk");
1082 printk(KERN_ERR "at91_ether: no clock defined\n");
1085 clk_enable(ether_clk); /* Enable Peripheral clock */
1087 while ((detected != 0) && (phy_address < 32)) {
1088 /* Read the PHY ID registers */
1090 read_phy(phy_address, MII_PHYSID1, &phyid1);
1091 read_phy(phy_address, MII_PHYSID2, &phyid2);
1094 phy_id = (phyid1 << 16) | (phyid2 & 0xfff0);
1096 case MII_DM9161_ID: /* Davicom 9161: PHY_ID1 = 0x181, PHY_ID2 = B881 */
1097 case MII_DM9161A_ID: /* Davicom 9161A: PHY_ID1 = 0x181, PHY_ID2 = B8A0 */
1098 case MII_LXT971A_ID: /* Intel LXT971A: PHY_ID1 = 0x13, PHY_ID2 = 78E0 */
1099 case MII_RTL8201_ID: /* Realtek RTL8201: PHY_ID1 = 0, PHY_ID2 = 0x8201 */
1100 case MII_BCM5221_ID: /* Broadcom BCM5221: PHY_ID1 = 0x40, PHY_ID2 = 0x61e0 */
1101 case MII_DP83847_ID: /* National Semiconductor DP83847: */
1102 case MII_AC101L_ID: /* Altima AC101L: PHY_ID1 = 0x22, PHY_ID2 = 0x5520 */
1103 case MII_KS8721_ID: /* Micrel KS8721: PHY_ID1 = 0x22, PHY_ID2 = 0x1610 */
1104 detected = at91ether_setup(phy_id, phy_address, pdev);
1111 clk_disable(ether_clk); /* Disable Peripheral clock */
1116 static int __devexit at91ether_remove(struct platform_device *pdev)
1118 struct at91_private *lp = (struct at91_private *) at91_dev->priv;
1120 unregister_netdev(at91_dev);
1121 free_irq(at91_dev->irq, at91_dev);
1122 dma_free_coherent(NULL, sizeof(struct recv_desc_bufs), lp->dlist, (dma_addr_t)lp->dlist_phys);
1125 free_netdev(at91_dev);
1130 static struct platform_driver at91ether_driver = {
1131 .probe = at91ether_probe,
1132 .remove = __devexit_p(at91ether_remove),
1133 /* FIXME: support suspend and resume */
1136 .owner = THIS_MODULE,
1140 static int __init at91ether_init(void)
1142 return platform_driver_register(&at91ether_driver);
1145 static void __exit at91ether_exit(void)
1147 platform_driver_unregister(&at91ether_driver);
1150 module_init(at91ether_init)
1151 module_exit(at91ether_exit)
1153 MODULE_LICENSE("GPL");
1154 MODULE_DESCRIPTION("AT91RM9200 EMAC Ethernet driver");
1155 MODULE_AUTHOR("Andrew Victor");