1 /* 8139cp.c: A Linux PCI Ethernet driver for the RealTek 8139C+ chips. */
3 Copyright 2001-2004 Jeff Garzik <jgarzik@pobox.com>
5 Copyright (C) 2001, 2002 David S. Miller (davem@redhat.com) [tg3.c]
6 Copyright (C) 2000, 2001 David S. Miller (davem@redhat.com) [sungem.c]
7 Copyright 2001 Manfred Spraul [natsemi.c]
8 Copyright 1999-2001 by Donald Becker. [natsemi.c]
9 Written 1997-2001 by Donald Becker. [8139too.c]
10 Copyright 1998-2001 by Jes Sorensen, <jes@trained-monkey.org>. [acenic.c]
12 This software may be used and distributed according to the terms of
13 the GNU General Public License (GPL), incorporated herein by reference.
14 Drivers based on or derived from this code fall under the GPL and must
15 retain the authorship, copyright and license notice. This file is not
16 a complete program and may only be used when the entire operating
17 system is licensed under the GPL.
19 See the file COPYING in this distribution for more information.
23 Wake-on-LAN support - Felipe Damasio <felipewd@terra.com.br>
24 PCI suspend/resume - Felipe Damasio <felipewd@terra.com.br>
25 LinkChg interrupt - Felipe Damasio <felipewd@terra.com.br>
28 * Test Tx checksumming thoroughly
31 * Complete reset on PciErr
32 * Consider Rx interrupt mitigation using TimerIntr
33 * Investigate using skb->priority with h/w VLAN priority
34 * Investigate using High Priority Tx Queue with skb->priority
35 * Adjust Rx FIFO threshold and Max Rx DMA burst on Rx FIFO error
36 * Adjust Tx FIFO threshold and Max Tx DMA burst on Tx FIFO error
37 * Implement Tx software interrupt mitigation via
39 * The real minimum of CP_MIN_MTU is 4 bytes. However,
40 for this to be supported, one must(?) turn on packet padding.
41 * Support external MII transceivers (patch available)
44 * TX checksumming is considered experimental. It is off by
45 default, use ethtool to turn it on.
49 #define DRV_NAME "8139cp"
50 #define DRV_VERSION "1.3"
51 #define DRV_RELDATE "Mar 22, 2004"
54 #include <linux/module.h>
55 #include <linux/moduleparam.h>
56 #include <linux/kernel.h>
57 #include <linux/compiler.h>
58 #include <linux/netdevice.h>
59 #include <linux/etherdevice.h>
60 #include <linux/init.h>
61 #include <linux/pci.h>
62 #include <linux/dma-mapping.h>
63 #include <linux/delay.h>
64 #include <linux/ethtool.h>
65 #include <linux/mii.h>
66 #include <linux/if_vlan.h>
67 #include <linux/crc32.h>
70 #include <linux/tcp.h>
71 #include <linux/udp.h>
72 #include <linux/cache.h>
75 #include <asm/uaccess.h>
77 /* VLAN tagging feature enable/disable */
78 #if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
79 #define CP_VLAN_TAG_USED 1
80 #define CP_VLAN_TX_TAG(tx_desc,vlan_tag_value) \
81 do { (tx_desc)->opts2 = (vlan_tag_value); } while (0)
83 #define CP_VLAN_TAG_USED 0
84 #define CP_VLAN_TX_TAG(tx_desc,vlan_tag_value) \
85 do { (tx_desc)->opts2 = 0; } while (0)
88 /* These identify the driver base version and may not be removed. */
89 static char version[] =
90 KERN_INFO DRV_NAME ": 10/100 PCI Ethernet driver v" DRV_VERSION " (" DRV_RELDATE ")\n";
92 MODULE_AUTHOR("Jeff Garzik <jgarzik@pobox.com>");
93 MODULE_DESCRIPTION("RealTek RTL-8139C+ series 10/100 PCI Ethernet driver");
94 MODULE_VERSION(DRV_VERSION);
95 MODULE_LICENSE("GPL");
97 static int debug = -1;
98 module_param(debug, int, 0);
99 MODULE_PARM_DESC (debug, "8139cp: bitmapped message enable number");
101 /* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).
102 The RTL chips use a 64 element hash table based on the Ethernet CRC. */
103 static int multicast_filter_limit = 32;
104 module_param(multicast_filter_limit, int, 0);
105 MODULE_PARM_DESC (multicast_filter_limit, "8139cp: maximum number of filtered multicast addresses");
107 #define PFX DRV_NAME ": "
109 #define CP_DEF_MSG_ENABLE (NETIF_MSG_DRV | \
112 #define CP_NUM_STATS 14 /* struct cp_dma_stats, plus one */
113 #define CP_STATS_SIZE 64 /* size in bytes of DMA stats block */
114 #define CP_REGS_SIZE (0xff + 1)
115 #define CP_REGS_VER 1 /* version 1 */
116 #define CP_RX_RING_SIZE 64
117 #define CP_TX_RING_SIZE 64
118 #define CP_RING_BYTES \
119 ((sizeof(struct cp_desc) * CP_RX_RING_SIZE) + \
120 (sizeof(struct cp_desc) * CP_TX_RING_SIZE) + \
122 #define NEXT_TX(N) (((N) + 1) & (CP_TX_RING_SIZE - 1))
123 #define NEXT_RX(N) (((N) + 1) & (CP_RX_RING_SIZE - 1))
124 #define TX_BUFFS_AVAIL(CP) \
125 (((CP)->tx_tail <= (CP)->tx_head) ? \
126 (CP)->tx_tail + (CP_TX_RING_SIZE - 1) - (CP)->tx_head : \
127 (CP)->tx_tail - (CP)->tx_head - 1)
129 #define PKT_BUF_SZ 1536 /* Size of each temporary Rx buffer.*/
131 #define CP_INTERNAL_PHY 32
133 /* The following settings are log_2(bytes)-4: 0 == 16 bytes .. 6==1024, 7==end of packet. */
134 #define RX_FIFO_THRESH 5 /* Rx buffer level before first PCI xfer. */
135 #define RX_DMA_BURST 4 /* Maximum PCI burst, '4' is 256 */
136 #define TX_DMA_BURST 6 /* Maximum PCI burst, '6' is 1024 */
137 #define TX_EARLY_THRESH 256 /* Early Tx threshold, in bytes */
139 /* Time in jiffies before concluding the transmitter is hung. */
140 #define TX_TIMEOUT (6*HZ)
142 /* hardware minimum and maximum for a single frame's data payload */
143 #define CP_MIN_MTU 60 /* TODO: allow lower, but pad */
144 #define CP_MAX_MTU 4096
147 /* NIC register offsets */
148 MAC0 = 0x00, /* Ethernet hardware address. */
149 MAR0 = 0x08, /* Multicast filter. */
150 StatsAddr = 0x10, /* 64-bit start addr of 64-byte DMA stats blk */
151 TxRingAddr = 0x20, /* 64-bit start addr of Tx ring */
152 HiTxRingAddr = 0x28, /* 64-bit start addr of high priority Tx ring */
153 Cmd = 0x37, /* Command register */
154 IntrMask = 0x3C, /* Interrupt mask */
155 IntrStatus = 0x3E, /* Interrupt status */
156 TxConfig = 0x40, /* Tx configuration */
157 ChipVersion = 0x43, /* 8-bit chip version, inside TxConfig */
158 RxConfig = 0x44, /* Rx configuration */
159 RxMissed = 0x4C, /* 24 bits valid, write clears */
160 Cfg9346 = 0x50, /* EEPROM select/control; Cfg reg [un]lock */
161 Config1 = 0x52, /* Config1 */
162 Config3 = 0x59, /* Config3 */
163 Config4 = 0x5A, /* Config4 */
164 MultiIntr = 0x5C, /* Multiple interrupt select */
165 BasicModeCtrl = 0x62, /* MII BMCR */
166 BasicModeStatus = 0x64, /* MII BMSR */
167 NWayAdvert = 0x66, /* MII ADVERTISE */
168 NWayLPAR = 0x68, /* MII LPA */
169 NWayExpansion = 0x6A, /* MII Expansion */
170 Config5 = 0xD8, /* Config5 */
171 TxPoll = 0xD9, /* Tell chip to check Tx descriptors for work */
172 RxMaxSize = 0xDA, /* Max size of an Rx packet (8169 only) */
173 CpCmd = 0xE0, /* C+ Command register (C+ mode only) */
174 IntrMitigate = 0xE2, /* rx/tx interrupt mitigation control */
175 RxRingAddr = 0xE4, /* 64-bit start addr of Rx ring */
176 TxThresh = 0xEC, /* Early Tx threshold */
177 OldRxBufAddr = 0x30, /* DMA address of Rx ring buffer (C mode) */
178 OldTSD0 = 0x10, /* DMA address of first Tx desc (C mode) */
180 /* Tx and Rx status descriptors */
181 DescOwn = (1 << 31), /* Descriptor is owned by NIC */
182 RingEnd = (1 << 30), /* End of descriptor ring */
183 FirstFrag = (1 << 29), /* First segment of a packet */
184 LastFrag = (1 << 28), /* Final segment of a packet */
185 LargeSend = (1 << 27), /* TCP Large Send Offload (TSO) */
186 MSSShift = 16, /* MSS value position */
187 MSSMask = 0xfff, /* MSS value: 11 bits */
188 TxError = (1 << 23), /* Tx error summary */
189 RxError = (1 << 20), /* Rx error summary */
190 IPCS = (1 << 18), /* Calculate IP checksum */
191 UDPCS = (1 << 17), /* Calculate UDP/IP checksum */
192 TCPCS = (1 << 16), /* Calculate TCP/IP checksum */
193 TxVlanTag = (1 << 17), /* Add VLAN tag */
194 RxVlanTagged = (1 << 16), /* Rx VLAN tag available */
195 IPFail = (1 << 15), /* IP checksum failed */
196 UDPFail = (1 << 14), /* UDP/IP checksum failed */
197 TCPFail = (1 << 13), /* TCP/IP checksum failed */
198 NormalTxPoll = (1 << 6), /* One or more normal Tx packets to send */
199 PID1 = (1 << 17), /* 2 protocol id bits: 0==non-IP, */
200 PID0 = (1 << 16), /* 1==UDP/IP, 2==TCP/IP, 3==IP */
204 TxFIFOUnder = (1 << 25), /* Tx FIFO underrun */
205 TxOWC = (1 << 22), /* Tx Out-of-window collision */
206 TxLinkFail = (1 << 21), /* Link failed during Tx of packet */
207 TxMaxCol = (1 << 20), /* Tx aborted due to excessive collisions */
208 TxColCntShift = 16, /* Shift, to get 4-bit Tx collision cnt */
209 TxColCntMask = 0x01 | 0x02 | 0x04 | 0x08, /* 4-bit collision count */
210 RxErrFrame = (1 << 27), /* Rx frame alignment error */
211 RxMcast = (1 << 26), /* Rx multicast packet rcv'd */
212 RxErrCRC = (1 << 18), /* Rx CRC error */
213 RxErrRunt = (1 << 19), /* Rx error, packet < 64 bytes */
214 RxErrLong = (1 << 21), /* Rx error, packet > 4096 bytes */
215 RxErrFIFO = (1 << 22), /* Rx error, FIFO overflowed, pkt bad */
217 /* StatsAddr register */
218 DumpStats = (1 << 3), /* Begin stats dump */
220 /* RxConfig register */
221 RxCfgFIFOShift = 13, /* Shift, to get Rx FIFO thresh value */
222 RxCfgDMAShift = 8, /* Shift, to get Rx Max DMA value */
223 AcceptErr = 0x20, /* Accept packets with CRC errors */
224 AcceptRunt = 0x10, /* Accept runt (<64 bytes) packets */
225 AcceptBroadcast = 0x08, /* Accept broadcast packets */
226 AcceptMulticast = 0x04, /* Accept multicast packets */
227 AcceptMyPhys = 0x02, /* Accept pkts with our MAC as dest */
228 AcceptAllPhys = 0x01, /* Accept all pkts w/ physical dest */
230 /* IntrMask / IntrStatus registers */
231 PciErr = (1 << 15), /* System error on the PCI bus */
232 TimerIntr = (1 << 14), /* Asserted when TCTR reaches TimerInt value */
233 LenChg = (1 << 13), /* Cable length change */
234 SWInt = (1 << 8), /* Software-requested interrupt */
235 TxEmpty = (1 << 7), /* No Tx descriptors available */
236 RxFIFOOvr = (1 << 6), /* Rx FIFO Overflow */
237 LinkChg = (1 << 5), /* Packet underrun, or link change */
238 RxEmpty = (1 << 4), /* No Rx descriptors available */
239 TxErr = (1 << 3), /* Tx error */
240 TxOK = (1 << 2), /* Tx packet sent */
241 RxErr = (1 << 1), /* Rx error */
242 RxOK = (1 << 0), /* Rx packet received */
243 IntrResvd = (1 << 10), /* reserved, according to RealTek engineers,
244 but hardware likes to raise it */
246 IntrAll = PciErr | TimerIntr | LenChg | SWInt | TxEmpty |
247 RxFIFOOvr | LinkChg | RxEmpty | TxErr | TxOK |
248 RxErr | RxOK | IntrResvd,
250 /* C mode command register */
251 CmdReset = (1 << 4), /* Enable to reset; self-clearing */
252 RxOn = (1 << 3), /* Rx mode enable */
253 TxOn = (1 << 2), /* Tx mode enable */
255 /* C+ mode command register */
256 RxVlanOn = (1 << 6), /* Rx VLAN de-tagging enable */
257 RxChkSum = (1 << 5), /* Rx checksum offload enable */
258 PCIDAC = (1 << 4), /* PCI Dual Address Cycle (64-bit PCI) */
259 PCIMulRW = (1 << 3), /* Enable PCI read/write multiple */
260 CpRxOn = (1 << 1), /* Rx mode enable */
261 CpTxOn = (1 << 0), /* Tx mode enable */
263 /* Cfg9436 EEPROM control register */
264 Cfg9346_Lock = 0x00, /* Lock ConfigX/MII register access */
265 Cfg9346_Unlock = 0xC0, /* Unlock ConfigX/MII register access */
267 /* TxConfig register */
268 IFG = (1 << 25) | (1 << 24), /* standard IEEE interframe gap */
269 TxDMAShift = 8, /* DMA burst value (0-7) is shift this many bits */
271 /* Early Tx Threshold register */
272 TxThreshMask = 0x3f, /* Mask bits 5-0 */
273 TxThreshMax = 2048, /* Max early Tx threshold */
275 /* Config1 register */
276 DriverLoaded = (1 << 5), /* Software marker, driver is loaded */
277 LWACT = (1 << 4), /* LWAKE active mode */
278 PMEnable = (1 << 0), /* Enable various PM features of chip */
280 /* Config3 register */
281 PARMEnable = (1 << 6), /* Enable auto-loading of PHY parms */
282 MagicPacket = (1 << 5), /* Wake up when receives a Magic Packet */
283 LinkUp = (1 << 4), /* Wake up when the cable connection is re-established */
285 /* Config4 register */
286 LWPTN = (1 << 1), /* LWAKE Pattern */
287 LWPME = (1 << 4), /* LANWAKE vs PMEB */
289 /* Config5 register */
290 BWF = (1 << 6), /* Accept Broadcast wakeup frame */
291 MWF = (1 << 5), /* Accept Multicast wakeup frame */
292 UWF = (1 << 4), /* Accept Unicast wakeup frame */
293 LANWake = (1 << 1), /* Enable LANWake signal */
294 PMEStatus = (1 << 0), /* PME status can be reset by PCI RST# */
296 cp_norx_intr_mask = PciErr | LinkChg | TxOK | TxErr | TxEmpty,
297 cp_rx_intr_mask = RxOK | RxErr | RxEmpty | RxFIFOOvr,
298 cp_intr_mask = cp_rx_intr_mask | cp_norx_intr_mask,
301 static const unsigned int cp_rx_config =
302 (RX_FIFO_THRESH << RxCfgFIFOShift) |
303 (RX_DMA_BURST << RxCfgDMAShift);
311 struct cp_dma_stats {
325 } __attribute__((packed));
327 struct cp_extra_stats {
328 unsigned long rx_frags;
333 struct net_device *dev;
337 struct napi_struct napi;
339 struct pci_dev *pdev;
343 struct net_device_stats net_stats;
344 struct cp_extra_stats cp_stats;
346 unsigned rx_head ____cacheline_aligned;
348 struct cp_desc *rx_ring;
349 struct sk_buff *rx_skb[CP_RX_RING_SIZE];
351 unsigned tx_head ____cacheline_aligned;
353 struct cp_desc *tx_ring;
354 struct sk_buff *tx_skb[CP_TX_RING_SIZE];
357 unsigned wol_enabled : 1; /* Is Wake-on-LAN enabled? */
360 struct vlan_group *vlgrp;
364 struct mii_if_info mii_if;
367 #define cpr8(reg) readb(cp->regs + (reg))
368 #define cpr16(reg) readw(cp->regs + (reg))
369 #define cpr32(reg) readl(cp->regs + (reg))
370 #define cpw8(reg,val) writeb((val), cp->regs + (reg))
371 #define cpw16(reg,val) writew((val), cp->regs + (reg))
372 #define cpw32(reg,val) writel((val), cp->regs + (reg))
373 #define cpw8_f(reg,val) do { \
374 writeb((val), cp->regs + (reg)); \
375 readb(cp->regs + (reg)); \
377 #define cpw16_f(reg,val) do { \
378 writew((val), cp->regs + (reg)); \
379 readw(cp->regs + (reg)); \
381 #define cpw32_f(reg,val) do { \
382 writel((val), cp->regs + (reg)); \
383 readl(cp->regs + (reg)); \
387 static void __cp_set_rx_mode (struct net_device *dev);
388 static void cp_tx (struct cp_private *cp);
389 static void cp_clean_rings (struct cp_private *cp);
390 #ifdef CONFIG_NET_POLL_CONTROLLER
391 static void cp_poll_controller(struct net_device *dev);
393 static int cp_get_eeprom_len(struct net_device *dev);
394 static int cp_get_eeprom(struct net_device *dev,
395 struct ethtool_eeprom *eeprom, u8 *data);
396 static int cp_set_eeprom(struct net_device *dev,
397 struct ethtool_eeprom *eeprom, u8 *data);
399 static struct pci_device_id cp_pci_tbl[] = {
400 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, PCI_DEVICE_ID_REALTEK_8139), },
401 { PCI_DEVICE(PCI_VENDOR_ID_TTTECH, PCI_DEVICE_ID_TTTECH_MC322), },
404 MODULE_DEVICE_TABLE(pci, cp_pci_tbl);
407 const char str[ETH_GSTRING_LEN];
408 } ethtool_stats_keys[] = {
427 static void cp_vlan_rx_register(struct net_device *dev, struct vlan_group *grp)
429 struct cp_private *cp = netdev_priv(dev);
432 spin_lock_irqsave(&cp->lock, flags);
435 cp->cpcmd |= RxVlanOn;
437 cp->cpcmd &= ~RxVlanOn;
439 cpw16(CpCmd, cp->cpcmd);
440 spin_unlock_irqrestore(&cp->lock, flags);
442 #endif /* CP_VLAN_TAG_USED */
444 static inline void cp_set_rxbufsize (struct cp_private *cp)
446 unsigned int mtu = cp->dev->mtu;
448 if (mtu > ETH_DATA_LEN)
449 /* MTU + ethernet header + FCS + optional VLAN tag */
450 cp->rx_buf_sz = mtu + ETH_HLEN + 8;
452 cp->rx_buf_sz = PKT_BUF_SZ;
455 static inline void cp_rx_skb (struct cp_private *cp, struct sk_buff *skb,
456 struct cp_desc *desc)
458 skb->protocol = eth_type_trans (skb, cp->dev);
460 cp->net_stats.rx_packets++;
461 cp->net_stats.rx_bytes += skb->len;
462 cp->dev->last_rx = jiffies;
465 if (cp->vlgrp && (desc->opts2 & RxVlanTagged)) {
466 vlan_hwaccel_receive_skb(skb, cp->vlgrp,
467 be16_to_cpu(desc->opts2 & 0xffff));
470 netif_receive_skb(skb);
473 static void cp_rx_err_acct (struct cp_private *cp, unsigned rx_tail,
476 if (netif_msg_rx_err (cp))
478 "%s: rx err, slot %d status 0x%x len %d\n",
479 cp->dev->name, rx_tail, status, len);
480 cp->net_stats.rx_errors++;
481 if (status & RxErrFrame)
482 cp->net_stats.rx_frame_errors++;
483 if (status & RxErrCRC)
484 cp->net_stats.rx_crc_errors++;
485 if ((status & RxErrRunt) || (status & RxErrLong))
486 cp->net_stats.rx_length_errors++;
487 if ((status & (FirstFrag | LastFrag)) != (FirstFrag | LastFrag))
488 cp->net_stats.rx_length_errors++;
489 if (status & RxErrFIFO)
490 cp->net_stats.rx_fifo_errors++;
493 static inline unsigned int cp_rx_csum_ok (u32 status)
495 unsigned int protocol = (status >> 16) & 0x3;
497 if (likely((protocol == RxProtoTCP) && (!(status & TCPFail))))
499 else if ((protocol == RxProtoUDP) && (!(status & UDPFail)))
501 else if ((protocol == RxProtoIP) && (!(status & IPFail)))
506 static int cp_rx_poll(struct napi_struct *napi, int budget)
508 struct cp_private *cp = container_of(napi, struct cp_private, napi);
509 struct net_device *dev = cp->dev;
510 unsigned int rx_tail = cp->rx_tail;
515 cpw16(IntrStatus, cp_rx_intr_mask);
520 struct sk_buff *skb, *new_skb;
521 struct cp_desc *desc;
524 skb = cp->rx_skb[rx_tail];
527 desc = &cp->rx_ring[rx_tail];
528 status = le32_to_cpu(desc->opts1);
529 if (status & DescOwn)
532 len = (status & 0x1fff) - 4;
533 mapping = le64_to_cpu(desc->addr);
535 if ((status & (FirstFrag | LastFrag)) != (FirstFrag | LastFrag)) {
536 /* we don't support incoming fragmented frames.
537 * instead, we attempt to ensure that the
538 * pre-allocated RX skbs are properly sized such
539 * that RX fragments are never encountered
541 cp_rx_err_acct(cp, rx_tail, status, len);
542 cp->net_stats.rx_dropped++;
543 cp->cp_stats.rx_frags++;
547 if (status & (RxError | RxErrFIFO)) {
548 cp_rx_err_acct(cp, rx_tail, status, len);
552 if (netif_msg_rx_status(cp))
553 printk(KERN_DEBUG "%s: rx slot %d status 0x%x len %d\n",
554 dev->name, rx_tail, status, len);
556 buflen = cp->rx_buf_sz + RX_OFFSET;
557 new_skb = dev_alloc_skb (buflen);
559 cp->net_stats.rx_dropped++;
563 skb_reserve(new_skb, RX_OFFSET);
565 pci_unmap_single(cp->pdev, mapping,
566 buflen, PCI_DMA_FROMDEVICE);
568 /* Handle checksum offloading for incoming packets. */
569 if (cp_rx_csum_ok(status))
570 skb->ip_summed = CHECKSUM_UNNECESSARY;
572 skb->ip_summed = CHECKSUM_NONE;
576 mapping = pci_map_single(cp->pdev, new_skb->data, buflen,
578 cp->rx_skb[rx_tail] = new_skb;
580 cp_rx_skb(cp, skb, desc);
584 cp->rx_ring[rx_tail].opts2 = 0;
585 cp->rx_ring[rx_tail].addr = cpu_to_le64(mapping);
586 if (rx_tail == (CP_RX_RING_SIZE - 1))
587 desc->opts1 = cpu_to_le32(DescOwn | RingEnd |
590 desc->opts1 = cpu_to_le32(DescOwn | cp->rx_buf_sz);
591 rx_tail = NEXT_RX(rx_tail);
597 cp->rx_tail = rx_tail;
599 /* if we did not reach work limit, then we're done with
600 * this round of polling
605 if (cpr16(IntrStatus) & cp_rx_intr_mask)
608 spin_lock_irqsave(&cp->lock, flags);
609 cpw16_f(IntrMask, cp_intr_mask);
610 __netif_rx_complete(dev, napi);
611 spin_unlock_irqrestore(&cp->lock, flags);
617 static irqreturn_t cp_interrupt (int irq, void *dev_instance)
619 struct net_device *dev = dev_instance;
620 struct cp_private *cp;
623 if (unlikely(dev == NULL))
625 cp = netdev_priv(dev);
627 status = cpr16(IntrStatus);
628 if (!status || (status == 0xFFFF))
631 if (netif_msg_intr(cp))
632 printk(KERN_DEBUG "%s: intr, status %04x cmd %02x cpcmd %04x\n",
633 dev->name, status, cpr8(Cmd), cpr16(CpCmd));
635 cpw16(IntrStatus, status & ~cp_rx_intr_mask);
637 spin_lock(&cp->lock);
639 /* close possible race's with dev_close */
640 if (unlikely(!netif_running(dev))) {
642 spin_unlock(&cp->lock);
646 if (status & (RxOK | RxErr | RxEmpty | RxFIFOOvr))
647 if (netif_rx_schedule_prep(dev, &cp->napi)) {
648 cpw16_f(IntrMask, cp_norx_intr_mask);
649 __netif_rx_schedule(dev, &cp->napi);
652 if (status & (TxOK | TxErr | TxEmpty | SWInt))
654 if (status & LinkChg)
655 mii_check_media(&cp->mii_if, netif_msg_link(cp), false);
657 spin_unlock(&cp->lock);
659 if (status & PciErr) {
662 pci_read_config_word(cp->pdev, PCI_STATUS, &pci_status);
663 pci_write_config_word(cp->pdev, PCI_STATUS, pci_status);
664 printk(KERN_ERR "%s: PCI bus error, status=%04x, PCI status=%04x\n",
665 dev->name, status, pci_status);
667 /* TODO: reset hardware */
673 #ifdef CONFIG_NET_POLL_CONTROLLER
675 * Polling receive - used by netconsole and other diagnostic tools
676 * to allow network i/o with interrupts disabled.
678 static void cp_poll_controller(struct net_device *dev)
680 disable_irq(dev->irq);
681 cp_interrupt(dev->irq, dev);
682 enable_irq(dev->irq);
686 static void cp_tx (struct cp_private *cp)
688 unsigned tx_head = cp->tx_head;
689 unsigned tx_tail = cp->tx_tail;
691 while (tx_tail != tx_head) {
692 struct cp_desc *txd = cp->tx_ring + tx_tail;
697 status = le32_to_cpu(txd->opts1);
698 if (status & DescOwn)
701 skb = cp->tx_skb[tx_tail];
704 pci_unmap_single(cp->pdev, le64_to_cpu(txd->addr),
705 le32_to_cpu(txd->opts1) & 0xffff,
708 if (status & LastFrag) {
709 if (status & (TxError | TxFIFOUnder)) {
710 if (netif_msg_tx_err(cp))
711 printk(KERN_DEBUG "%s: tx err, status 0x%x\n",
712 cp->dev->name, status);
713 cp->net_stats.tx_errors++;
715 cp->net_stats.tx_window_errors++;
716 if (status & TxMaxCol)
717 cp->net_stats.tx_aborted_errors++;
718 if (status & TxLinkFail)
719 cp->net_stats.tx_carrier_errors++;
720 if (status & TxFIFOUnder)
721 cp->net_stats.tx_fifo_errors++;
723 cp->net_stats.collisions +=
724 ((status >> TxColCntShift) & TxColCntMask);
725 cp->net_stats.tx_packets++;
726 cp->net_stats.tx_bytes += skb->len;
727 if (netif_msg_tx_done(cp))
728 printk(KERN_DEBUG "%s: tx done, slot %d\n", cp->dev->name, tx_tail);
730 dev_kfree_skb_irq(skb);
733 cp->tx_skb[tx_tail] = NULL;
735 tx_tail = NEXT_TX(tx_tail);
738 cp->tx_tail = tx_tail;
740 if (TX_BUFFS_AVAIL(cp) > (MAX_SKB_FRAGS + 1))
741 netif_wake_queue(cp->dev);
744 static int cp_start_xmit (struct sk_buff *skb, struct net_device *dev)
746 struct cp_private *cp = netdev_priv(dev);
749 unsigned long intr_flags;
755 spin_lock_irqsave(&cp->lock, intr_flags);
757 /* This is a hard error, log it. */
758 if (TX_BUFFS_AVAIL(cp) <= (skb_shinfo(skb)->nr_frags + 1)) {
759 netif_stop_queue(dev);
760 spin_unlock_irqrestore(&cp->lock, intr_flags);
761 printk(KERN_ERR PFX "%s: BUG! Tx Ring full when queue awake!\n",
767 if (cp->vlgrp && vlan_tx_tag_present(skb))
768 vlan_tag = TxVlanTag | cpu_to_be16(vlan_tx_tag_get(skb));
772 eor = (entry == (CP_TX_RING_SIZE - 1)) ? RingEnd : 0;
773 if (dev->features & NETIF_F_TSO)
774 mss = skb_shinfo(skb)->gso_size;
776 if (skb_shinfo(skb)->nr_frags == 0) {
777 struct cp_desc *txd = &cp->tx_ring[entry];
782 mapping = pci_map_single(cp->pdev, skb->data, len, PCI_DMA_TODEVICE);
783 CP_VLAN_TX_TAG(txd, vlan_tag);
784 txd->addr = cpu_to_le64(mapping);
787 flags = eor | len | DescOwn | FirstFrag | LastFrag;
790 flags |= LargeSend | ((mss & MSSMask) << MSSShift);
791 else if (skb->ip_summed == CHECKSUM_PARTIAL) {
792 const struct iphdr *ip = ip_hdr(skb);
793 if (ip->protocol == IPPROTO_TCP)
794 flags |= IPCS | TCPCS;
795 else if (ip->protocol == IPPROTO_UDP)
796 flags |= IPCS | UDPCS;
798 WARN_ON(1); /* we need a WARN() */
801 txd->opts1 = cpu_to_le32(flags);
804 cp->tx_skb[entry] = skb;
805 entry = NEXT_TX(entry);
808 u32 first_len, first_eor;
809 dma_addr_t first_mapping;
810 int frag, first_entry = entry;
811 const struct iphdr *ip = ip_hdr(skb);
813 /* We must give this initial chunk to the device last.
814 * Otherwise we could race with the device.
817 first_len = skb_headlen(skb);
818 first_mapping = pci_map_single(cp->pdev, skb->data,
819 first_len, PCI_DMA_TODEVICE);
820 cp->tx_skb[entry] = skb;
821 entry = NEXT_TX(entry);
823 for (frag = 0; frag < skb_shinfo(skb)->nr_frags; frag++) {
824 skb_frag_t *this_frag = &skb_shinfo(skb)->frags[frag];
829 len = this_frag->size;
830 mapping = pci_map_single(cp->pdev,
831 ((void *) page_address(this_frag->page) +
832 this_frag->page_offset),
833 len, PCI_DMA_TODEVICE);
834 eor = (entry == (CP_TX_RING_SIZE - 1)) ? RingEnd : 0;
836 ctrl = eor | len | DescOwn;
840 ((mss & MSSMask) << MSSShift);
841 else if (skb->ip_summed == CHECKSUM_PARTIAL) {
842 if (ip->protocol == IPPROTO_TCP)
843 ctrl |= IPCS | TCPCS;
844 else if (ip->protocol == IPPROTO_UDP)
845 ctrl |= IPCS | UDPCS;
850 if (frag == skb_shinfo(skb)->nr_frags - 1)
853 txd = &cp->tx_ring[entry];
854 CP_VLAN_TX_TAG(txd, vlan_tag);
855 txd->addr = cpu_to_le64(mapping);
858 txd->opts1 = cpu_to_le32(ctrl);
861 cp->tx_skb[entry] = skb;
862 entry = NEXT_TX(entry);
865 txd = &cp->tx_ring[first_entry];
866 CP_VLAN_TX_TAG(txd, vlan_tag);
867 txd->addr = cpu_to_le64(first_mapping);
870 if (skb->ip_summed == CHECKSUM_PARTIAL) {
871 if (ip->protocol == IPPROTO_TCP)
872 txd->opts1 = cpu_to_le32(first_eor | first_len |
873 FirstFrag | DescOwn |
875 else if (ip->protocol == IPPROTO_UDP)
876 txd->opts1 = cpu_to_le32(first_eor | first_len |
877 FirstFrag | DescOwn |
882 txd->opts1 = cpu_to_le32(first_eor | first_len |
883 FirstFrag | DescOwn);
887 if (netif_msg_tx_queued(cp))
888 printk(KERN_DEBUG "%s: tx queued, slot %d, skblen %d\n",
889 dev->name, entry, skb->len);
890 if (TX_BUFFS_AVAIL(cp) <= (MAX_SKB_FRAGS + 1))
891 netif_stop_queue(dev);
893 spin_unlock_irqrestore(&cp->lock, intr_flags);
895 cpw8(TxPoll, NormalTxPoll);
896 dev->trans_start = jiffies;
901 /* Set or clear the multicast filter for this adaptor.
902 This routine is not state sensitive and need not be SMP locked. */
904 static void __cp_set_rx_mode (struct net_device *dev)
906 struct cp_private *cp = netdev_priv(dev);
907 u32 mc_filter[2]; /* Multicast hash filter */
911 /* Note: do not reorder, GCC is clever about common statements. */
912 if (dev->flags & IFF_PROMISC) {
913 /* Unconditionally log net taps. */
915 AcceptBroadcast | AcceptMulticast | AcceptMyPhys |
917 mc_filter[1] = mc_filter[0] = 0xffffffff;
918 } else if ((dev->mc_count > multicast_filter_limit)
919 || (dev->flags & IFF_ALLMULTI)) {
920 /* Too many to filter perfectly -- accept all multicasts. */
921 rx_mode = AcceptBroadcast | AcceptMulticast | AcceptMyPhys;
922 mc_filter[1] = mc_filter[0] = 0xffffffff;
924 struct dev_mc_list *mclist;
925 rx_mode = AcceptBroadcast | AcceptMyPhys;
926 mc_filter[1] = mc_filter[0] = 0;
927 for (i = 0, mclist = dev->mc_list; mclist && i < dev->mc_count;
928 i++, mclist = mclist->next) {
929 int bit_nr = ether_crc(ETH_ALEN, mclist->dmi_addr) >> 26;
931 mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31);
932 rx_mode |= AcceptMulticast;
936 /* We can safely update without stopping the chip. */
937 tmp = cp_rx_config | rx_mode;
938 if (cp->rx_config != tmp) {
939 cpw32_f (RxConfig, tmp);
942 cpw32_f (MAR0 + 0, mc_filter[0]);
943 cpw32_f (MAR0 + 4, mc_filter[1]);
946 static void cp_set_rx_mode (struct net_device *dev)
949 struct cp_private *cp = netdev_priv(dev);
951 spin_lock_irqsave (&cp->lock, flags);
952 __cp_set_rx_mode(dev);
953 spin_unlock_irqrestore (&cp->lock, flags);
956 static void __cp_get_stats(struct cp_private *cp)
958 /* only lower 24 bits valid; write any value to clear */
959 cp->net_stats.rx_missed_errors += (cpr32 (RxMissed) & 0xffffff);
963 static struct net_device_stats *cp_get_stats(struct net_device *dev)
965 struct cp_private *cp = netdev_priv(dev);
968 /* The chip only need report frame silently dropped. */
969 spin_lock_irqsave(&cp->lock, flags);
970 if (netif_running(dev) && netif_device_present(dev))
972 spin_unlock_irqrestore(&cp->lock, flags);
974 return &cp->net_stats;
977 static void cp_stop_hw (struct cp_private *cp)
979 cpw16(IntrStatus, ~(cpr16(IntrStatus)));
980 cpw16_f(IntrMask, 0);
983 cpw16_f(IntrStatus, ~(cpr16(IntrStatus)));
986 cp->tx_head = cp->tx_tail = 0;
989 static void cp_reset_hw (struct cp_private *cp)
991 unsigned work = 1000;
996 if (!(cpr8(Cmd) & CmdReset))
999 schedule_timeout_uninterruptible(10);
1002 printk(KERN_ERR "%s: hardware reset timeout\n", cp->dev->name);
1005 static inline void cp_start_hw (struct cp_private *cp)
1007 cpw16(CpCmd, cp->cpcmd);
1008 cpw8(Cmd, RxOn | TxOn);
1011 static void cp_init_hw (struct cp_private *cp)
1013 struct net_device *dev = cp->dev;
1014 dma_addr_t ring_dma;
1018 cpw8_f (Cfg9346, Cfg9346_Unlock);
1020 /* Restore our idea of the MAC address. */
1021 cpw32_f (MAC0 + 0, cpu_to_le32 (*(u32 *) (dev->dev_addr + 0)));
1022 cpw32_f (MAC0 + 4, cpu_to_le32 (*(u32 *) (dev->dev_addr + 4)));
1025 cpw8(TxThresh, 0x06); /* XXX convert magic num to a constant */
1027 __cp_set_rx_mode(dev);
1028 cpw32_f (TxConfig, IFG | (TX_DMA_BURST << TxDMAShift));
1030 cpw8(Config1, cpr8(Config1) | DriverLoaded | PMEnable);
1031 /* Disable Wake-on-LAN. Can be turned on with ETHTOOL_SWOL */
1032 cpw8(Config3, PARMEnable);
1033 cp->wol_enabled = 0;
1035 cpw8(Config5, cpr8(Config5) & PMEStatus);
1037 cpw32_f(HiTxRingAddr, 0);
1038 cpw32_f(HiTxRingAddr + 4, 0);
1040 ring_dma = cp->ring_dma;
1041 cpw32_f(RxRingAddr, ring_dma & 0xffffffff);
1042 cpw32_f(RxRingAddr + 4, (ring_dma >> 16) >> 16);
1044 ring_dma += sizeof(struct cp_desc) * CP_RX_RING_SIZE;
1045 cpw32_f(TxRingAddr, ring_dma & 0xffffffff);
1046 cpw32_f(TxRingAddr + 4, (ring_dma >> 16) >> 16);
1048 cpw16(MultiIntr, 0);
1050 cpw16_f(IntrMask, cp_intr_mask);
1052 cpw8_f(Cfg9346, Cfg9346_Lock);
1055 static int cp_refill_rx (struct cp_private *cp)
1059 for (i = 0; i < CP_RX_RING_SIZE; i++) {
1060 struct sk_buff *skb;
1063 skb = dev_alloc_skb(cp->rx_buf_sz + RX_OFFSET);
1067 skb_reserve(skb, RX_OFFSET);
1069 mapping = pci_map_single(cp->pdev, skb->data, cp->rx_buf_sz,
1070 PCI_DMA_FROMDEVICE);
1071 cp->rx_skb[i] = skb;
1073 cp->rx_ring[i].opts2 = 0;
1074 cp->rx_ring[i].addr = cpu_to_le64(mapping);
1075 if (i == (CP_RX_RING_SIZE - 1))
1076 cp->rx_ring[i].opts1 =
1077 cpu_to_le32(DescOwn | RingEnd | cp->rx_buf_sz);
1079 cp->rx_ring[i].opts1 =
1080 cpu_to_le32(DescOwn | cp->rx_buf_sz);
1090 static void cp_init_rings_index (struct cp_private *cp)
1093 cp->tx_head = cp->tx_tail = 0;
1096 static int cp_init_rings (struct cp_private *cp)
1098 memset(cp->tx_ring, 0, sizeof(struct cp_desc) * CP_TX_RING_SIZE);
1099 cp->tx_ring[CP_TX_RING_SIZE - 1].opts1 = cpu_to_le32(RingEnd);
1101 cp_init_rings_index(cp);
1103 return cp_refill_rx (cp);
1106 static int cp_alloc_rings (struct cp_private *cp)
1110 mem = pci_alloc_consistent(cp->pdev, CP_RING_BYTES, &cp->ring_dma);
1115 cp->tx_ring = &cp->rx_ring[CP_RX_RING_SIZE];
1117 return cp_init_rings(cp);
1120 static void cp_clean_rings (struct cp_private *cp)
1122 struct cp_desc *desc;
1125 for (i = 0; i < CP_RX_RING_SIZE; i++) {
1126 if (cp->rx_skb[i]) {
1127 desc = cp->rx_ring + i;
1128 pci_unmap_single(cp->pdev, le64_to_cpu(desc->addr),
1129 cp->rx_buf_sz, PCI_DMA_FROMDEVICE);
1130 dev_kfree_skb(cp->rx_skb[i]);
1134 for (i = 0; i < CP_TX_RING_SIZE; i++) {
1135 if (cp->tx_skb[i]) {
1136 struct sk_buff *skb = cp->tx_skb[i];
1138 desc = cp->tx_ring + i;
1139 pci_unmap_single(cp->pdev, le64_to_cpu(desc->addr),
1140 le32_to_cpu(desc->opts1) & 0xffff,
1142 if (le32_to_cpu(desc->opts1) & LastFrag)
1144 cp->net_stats.tx_dropped++;
1148 memset(cp->rx_ring, 0, sizeof(struct cp_desc) * CP_RX_RING_SIZE);
1149 memset(cp->tx_ring, 0, sizeof(struct cp_desc) * CP_TX_RING_SIZE);
1151 memset(cp->rx_skb, 0, sizeof(struct sk_buff *) * CP_RX_RING_SIZE);
1152 memset(cp->tx_skb, 0, sizeof(struct sk_buff *) * CP_TX_RING_SIZE);
1155 static void cp_free_rings (struct cp_private *cp)
1158 pci_free_consistent(cp->pdev, CP_RING_BYTES, cp->rx_ring, cp->ring_dma);
1163 static int cp_open (struct net_device *dev)
1165 struct cp_private *cp = netdev_priv(dev);
1168 if (netif_msg_ifup(cp))
1169 printk(KERN_DEBUG "%s: enabling interface\n", dev->name);
1171 rc = cp_alloc_rings(cp);
1175 napi_enable(&cp->napi);
1179 rc = request_irq(dev->irq, cp_interrupt, IRQF_SHARED, dev->name, dev);
1183 netif_carrier_off(dev);
1184 mii_check_media(&cp->mii_if, netif_msg_link(cp), true);
1185 netif_start_queue(dev);
1190 napi_disable(&cp->napi);
1196 static int cp_close (struct net_device *dev)
1198 struct cp_private *cp = netdev_priv(dev);
1199 unsigned long flags;
1201 napi_disable(&cp->napi);
1203 if (netif_msg_ifdown(cp))
1204 printk(KERN_DEBUG "%s: disabling interface\n", dev->name);
1206 spin_lock_irqsave(&cp->lock, flags);
1208 netif_stop_queue(dev);
1209 netif_carrier_off(dev);
1213 spin_unlock_irqrestore(&cp->lock, flags);
1215 synchronize_irq(dev->irq);
1216 free_irq(dev->irq, dev);
1222 static void cp_tx_timeout(struct net_device *dev)
1224 struct cp_private *cp = netdev_priv(dev);
1225 unsigned long flags;
1228 printk(KERN_WARNING "%s: Transmit timeout, status %2x %4x %4x %4x\n",
1229 dev->name, cpr8(Cmd), cpr16(CpCmd),
1230 cpr16(IntrStatus), cpr16(IntrMask));
1232 spin_lock_irqsave(&cp->lock, flags);
1236 rc = cp_init_rings(cp);
1239 netif_wake_queue(dev);
1241 spin_unlock_irqrestore(&cp->lock, flags);
1247 static int cp_change_mtu(struct net_device *dev, int new_mtu)
1249 struct cp_private *cp = netdev_priv(dev);
1251 unsigned long flags;
1253 /* check for invalid MTU, according to hardware limits */
1254 if (new_mtu < CP_MIN_MTU || new_mtu > CP_MAX_MTU)
1257 /* if network interface not up, no need for complexity */
1258 if (!netif_running(dev)) {
1260 cp_set_rxbufsize(cp); /* set new rx buf size */
1264 spin_lock_irqsave(&cp->lock, flags);
1266 cp_stop_hw(cp); /* stop h/w and free rings */
1270 cp_set_rxbufsize(cp); /* set new rx buf size */
1272 rc = cp_init_rings(cp); /* realloc and restart h/w */
1275 spin_unlock_irqrestore(&cp->lock, flags);
1281 static const char mii_2_8139_map[8] = {
1292 static int mdio_read(struct net_device *dev, int phy_id, int location)
1294 struct cp_private *cp = netdev_priv(dev);
1296 return location < 8 && mii_2_8139_map[location] ?
1297 readw(cp->regs + mii_2_8139_map[location]) : 0;
1301 static void mdio_write(struct net_device *dev, int phy_id, int location,
1304 struct cp_private *cp = netdev_priv(dev);
1306 if (location == 0) {
1307 cpw8(Cfg9346, Cfg9346_Unlock);
1308 cpw16(BasicModeCtrl, value);
1309 cpw8(Cfg9346, Cfg9346_Lock);
1310 } else if (location < 8 && mii_2_8139_map[location])
1311 cpw16(mii_2_8139_map[location], value);
1314 /* Set the ethtool Wake-on-LAN settings */
1315 static int netdev_set_wol (struct cp_private *cp,
1316 const struct ethtool_wolinfo *wol)
1320 options = cpr8 (Config3) & ~(LinkUp | MagicPacket);
1321 /* If WOL is being disabled, no need for complexity */
1323 if (wol->wolopts & WAKE_PHY) options |= LinkUp;
1324 if (wol->wolopts & WAKE_MAGIC) options |= MagicPacket;
1327 cpw8 (Cfg9346, Cfg9346_Unlock);
1328 cpw8 (Config3, options);
1329 cpw8 (Cfg9346, Cfg9346_Lock);
1331 options = 0; /* Paranoia setting */
1332 options = cpr8 (Config5) & ~(UWF | MWF | BWF);
1333 /* If WOL is being disabled, no need for complexity */
1335 if (wol->wolopts & WAKE_UCAST) options |= UWF;
1336 if (wol->wolopts & WAKE_BCAST) options |= BWF;
1337 if (wol->wolopts & WAKE_MCAST) options |= MWF;
1340 cpw8 (Config5, options);
1342 cp->wol_enabled = (wol->wolopts) ? 1 : 0;
1347 /* Get the ethtool Wake-on-LAN settings */
1348 static void netdev_get_wol (struct cp_private *cp,
1349 struct ethtool_wolinfo *wol)
1353 wol->wolopts = 0; /* Start from scratch */
1354 wol->supported = WAKE_PHY | WAKE_BCAST | WAKE_MAGIC |
1355 WAKE_MCAST | WAKE_UCAST;
1356 /* We don't need to go on if WOL is disabled */
1357 if (!cp->wol_enabled) return;
1359 options = cpr8 (Config3);
1360 if (options & LinkUp) wol->wolopts |= WAKE_PHY;
1361 if (options & MagicPacket) wol->wolopts |= WAKE_MAGIC;
1363 options = 0; /* Paranoia setting */
1364 options = cpr8 (Config5);
1365 if (options & UWF) wol->wolopts |= WAKE_UCAST;
1366 if (options & BWF) wol->wolopts |= WAKE_BCAST;
1367 if (options & MWF) wol->wolopts |= WAKE_MCAST;
1370 static void cp_get_drvinfo (struct net_device *dev, struct ethtool_drvinfo *info)
1372 struct cp_private *cp = netdev_priv(dev);
1374 strcpy (info->driver, DRV_NAME);
1375 strcpy (info->version, DRV_VERSION);
1376 strcpy (info->bus_info, pci_name(cp->pdev));
1379 static int cp_get_regs_len(struct net_device *dev)
1381 return CP_REGS_SIZE;
1384 static int cp_get_stats_count (struct net_device *dev)
1386 return CP_NUM_STATS;
1389 static int cp_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1391 struct cp_private *cp = netdev_priv(dev);
1393 unsigned long flags;
1395 spin_lock_irqsave(&cp->lock, flags);
1396 rc = mii_ethtool_gset(&cp->mii_if, cmd);
1397 spin_unlock_irqrestore(&cp->lock, flags);
1402 static int cp_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1404 struct cp_private *cp = netdev_priv(dev);
1406 unsigned long flags;
1408 spin_lock_irqsave(&cp->lock, flags);
1409 rc = mii_ethtool_sset(&cp->mii_if, cmd);
1410 spin_unlock_irqrestore(&cp->lock, flags);
1415 static int cp_nway_reset(struct net_device *dev)
1417 struct cp_private *cp = netdev_priv(dev);
1418 return mii_nway_restart(&cp->mii_if);
1421 static u32 cp_get_msglevel(struct net_device *dev)
1423 struct cp_private *cp = netdev_priv(dev);
1424 return cp->msg_enable;
1427 static void cp_set_msglevel(struct net_device *dev, u32 value)
1429 struct cp_private *cp = netdev_priv(dev);
1430 cp->msg_enable = value;
1433 static u32 cp_get_rx_csum(struct net_device *dev)
1435 struct cp_private *cp = netdev_priv(dev);
1436 return (cpr16(CpCmd) & RxChkSum) ? 1 : 0;
1439 static int cp_set_rx_csum(struct net_device *dev, u32 data)
1441 struct cp_private *cp = netdev_priv(dev);
1442 u16 cmd = cp->cpcmd, newcmd;
1449 newcmd &= ~RxChkSum;
1451 if (newcmd != cmd) {
1452 unsigned long flags;
1454 spin_lock_irqsave(&cp->lock, flags);
1456 cpw16_f(CpCmd, newcmd);
1457 spin_unlock_irqrestore(&cp->lock, flags);
1463 static void cp_get_regs(struct net_device *dev, struct ethtool_regs *regs,
1466 struct cp_private *cp = netdev_priv(dev);
1467 unsigned long flags;
1469 if (regs->len < CP_REGS_SIZE)
1470 return /* -EINVAL */;
1472 regs->version = CP_REGS_VER;
1474 spin_lock_irqsave(&cp->lock, flags);
1475 memcpy_fromio(p, cp->regs, CP_REGS_SIZE);
1476 spin_unlock_irqrestore(&cp->lock, flags);
1479 static void cp_get_wol (struct net_device *dev, struct ethtool_wolinfo *wol)
1481 struct cp_private *cp = netdev_priv(dev);
1482 unsigned long flags;
1484 spin_lock_irqsave (&cp->lock, flags);
1485 netdev_get_wol (cp, wol);
1486 spin_unlock_irqrestore (&cp->lock, flags);
1489 static int cp_set_wol (struct net_device *dev, struct ethtool_wolinfo *wol)
1491 struct cp_private *cp = netdev_priv(dev);
1492 unsigned long flags;
1495 spin_lock_irqsave (&cp->lock, flags);
1496 rc = netdev_set_wol (cp, wol);
1497 spin_unlock_irqrestore (&cp->lock, flags);
1502 static void cp_get_strings (struct net_device *dev, u32 stringset, u8 *buf)
1504 switch (stringset) {
1506 memcpy(buf, ðtool_stats_keys, sizeof(ethtool_stats_keys));
1514 static void cp_get_ethtool_stats (struct net_device *dev,
1515 struct ethtool_stats *estats, u64 *tmp_stats)
1517 struct cp_private *cp = netdev_priv(dev);
1518 struct cp_dma_stats *nic_stats;
1522 nic_stats = pci_alloc_consistent(cp->pdev, sizeof(*nic_stats), &dma);
1526 /* begin NIC statistics dump */
1527 cpw32(StatsAddr + 4, (u64)dma >> 32);
1528 cpw32(StatsAddr, ((u64)dma & DMA_32BIT_MASK) | DumpStats);
1531 for (i = 0; i < 1000; i++) {
1532 if ((cpr32(StatsAddr) & DumpStats) == 0)
1536 cpw32(StatsAddr, 0);
1537 cpw32(StatsAddr + 4, 0);
1541 tmp_stats[i++] = le64_to_cpu(nic_stats->tx_ok);
1542 tmp_stats[i++] = le64_to_cpu(nic_stats->rx_ok);
1543 tmp_stats[i++] = le64_to_cpu(nic_stats->tx_err);
1544 tmp_stats[i++] = le32_to_cpu(nic_stats->rx_err);
1545 tmp_stats[i++] = le16_to_cpu(nic_stats->rx_fifo);
1546 tmp_stats[i++] = le16_to_cpu(nic_stats->frame_align);
1547 tmp_stats[i++] = le32_to_cpu(nic_stats->tx_ok_1col);
1548 tmp_stats[i++] = le32_to_cpu(nic_stats->tx_ok_mcol);
1549 tmp_stats[i++] = le64_to_cpu(nic_stats->rx_ok_phys);
1550 tmp_stats[i++] = le64_to_cpu(nic_stats->rx_ok_bcast);
1551 tmp_stats[i++] = le32_to_cpu(nic_stats->rx_ok_mcast);
1552 tmp_stats[i++] = le16_to_cpu(nic_stats->tx_abort);
1553 tmp_stats[i++] = le16_to_cpu(nic_stats->tx_underrun);
1554 tmp_stats[i++] = cp->cp_stats.rx_frags;
1555 BUG_ON(i != CP_NUM_STATS);
1557 pci_free_consistent(cp->pdev, sizeof(*nic_stats), nic_stats, dma);
1560 static const struct ethtool_ops cp_ethtool_ops = {
1561 .get_drvinfo = cp_get_drvinfo,
1562 .get_regs_len = cp_get_regs_len,
1563 .get_stats_count = cp_get_stats_count,
1564 .get_settings = cp_get_settings,
1565 .set_settings = cp_set_settings,
1566 .nway_reset = cp_nway_reset,
1567 .get_link = ethtool_op_get_link,
1568 .get_msglevel = cp_get_msglevel,
1569 .set_msglevel = cp_set_msglevel,
1570 .get_rx_csum = cp_get_rx_csum,
1571 .set_rx_csum = cp_set_rx_csum,
1572 .get_tx_csum = ethtool_op_get_tx_csum,
1573 .set_tx_csum = ethtool_op_set_tx_csum, /* local! */
1574 .get_sg = ethtool_op_get_sg,
1575 .set_sg = ethtool_op_set_sg,
1576 .get_tso = ethtool_op_get_tso,
1577 .set_tso = ethtool_op_set_tso,
1578 .get_regs = cp_get_regs,
1579 .get_wol = cp_get_wol,
1580 .set_wol = cp_set_wol,
1581 .get_strings = cp_get_strings,
1582 .get_ethtool_stats = cp_get_ethtool_stats,
1583 .get_eeprom_len = cp_get_eeprom_len,
1584 .get_eeprom = cp_get_eeprom,
1585 .set_eeprom = cp_set_eeprom,
1588 static int cp_ioctl (struct net_device *dev, struct ifreq *rq, int cmd)
1590 struct cp_private *cp = netdev_priv(dev);
1592 unsigned long flags;
1594 if (!netif_running(dev))
1597 spin_lock_irqsave(&cp->lock, flags);
1598 rc = generic_mii_ioctl(&cp->mii_if, if_mii(rq), cmd, NULL);
1599 spin_unlock_irqrestore(&cp->lock, flags);
1603 /* Serial EEPROM section. */
1605 /* EEPROM_Ctrl bits. */
1606 #define EE_SHIFT_CLK 0x04 /* EEPROM shift clock. */
1607 #define EE_CS 0x08 /* EEPROM chip select. */
1608 #define EE_DATA_WRITE 0x02 /* EEPROM chip data in. */
1609 #define EE_WRITE_0 0x00
1610 #define EE_WRITE_1 0x02
1611 #define EE_DATA_READ 0x01 /* EEPROM chip data out. */
1612 #define EE_ENB (0x80 | EE_CS)
1614 /* Delay between EEPROM clock transitions.
1615 No extra delay is needed with 33Mhz PCI, but 66Mhz may change this.
1618 #define eeprom_delay() readl(ee_addr)
1620 /* The EEPROM commands include the alway-set leading bit. */
1621 #define EE_EXTEND_CMD (4)
1622 #define EE_WRITE_CMD (5)
1623 #define EE_READ_CMD (6)
1624 #define EE_ERASE_CMD (7)
1626 #define EE_EWDS_ADDR (0)
1627 #define EE_WRAL_ADDR (1)
1628 #define EE_ERAL_ADDR (2)
1629 #define EE_EWEN_ADDR (3)
1631 #define CP_EEPROM_MAGIC PCI_DEVICE_ID_REALTEK_8139
1633 static void eeprom_cmd_start(void __iomem *ee_addr)
1635 writeb (EE_ENB & ~EE_CS, ee_addr);
1636 writeb (EE_ENB, ee_addr);
1640 static void eeprom_cmd(void __iomem *ee_addr, int cmd, int cmd_len)
1644 /* Shift the command bits out. */
1645 for (i = cmd_len - 1; i >= 0; i--) {
1646 int dataval = (cmd & (1 << i)) ? EE_DATA_WRITE : 0;
1647 writeb (EE_ENB | dataval, ee_addr);
1649 writeb (EE_ENB | dataval | EE_SHIFT_CLK, ee_addr);
1652 writeb (EE_ENB, ee_addr);
1656 static void eeprom_cmd_end(void __iomem *ee_addr)
1658 writeb (~EE_CS, ee_addr);
1662 static void eeprom_extend_cmd(void __iomem *ee_addr, int extend_cmd,
1665 int cmd = (EE_EXTEND_CMD << addr_len) | (extend_cmd << (addr_len - 2));
1667 eeprom_cmd_start(ee_addr);
1668 eeprom_cmd(ee_addr, cmd, 3 + addr_len);
1669 eeprom_cmd_end(ee_addr);
1672 static u16 read_eeprom (void __iomem *ioaddr, int location, int addr_len)
1676 void __iomem *ee_addr = ioaddr + Cfg9346;
1677 int read_cmd = location | (EE_READ_CMD << addr_len);
1679 eeprom_cmd_start(ee_addr);
1680 eeprom_cmd(ee_addr, read_cmd, 3 + addr_len);
1682 for (i = 16; i > 0; i--) {
1683 writeb (EE_ENB | EE_SHIFT_CLK, ee_addr);
1686 (retval << 1) | ((readb (ee_addr) & EE_DATA_READ) ? 1 :
1688 writeb (EE_ENB, ee_addr);
1692 eeprom_cmd_end(ee_addr);
1697 static void write_eeprom(void __iomem *ioaddr, int location, u16 val,
1701 void __iomem *ee_addr = ioaddr + Cfg9346;
1702 int write_cmd = location | (EE_WRITE_CMD << addr_len);
1704 eeprom_extend_cmd(ee_addr, EE_EWEN_ADDR, addr_len);
1706 eeprom_cmd_start(ee_addr);
1707 eeprom_cmd(ee_addr, write_cmd, 3 + addr_len);
1708 eeprom_cmd(ee_addr, val, 16);
1709 eeprom_cmd_end(ee_addr);
1711 eeprom_cmd_start(ee_addr);
1712 for (i = 0; i < 20000; i++)
1713 if (readb(ee_addr) & EE_DATA_READ)
1715 eeprom_cmd_end(ee_addr);
1717 eeprom_extend_cmd(ee_addr, EE_EWDS_ADDR, addr_len);
1720 static int cp_get_eeprom_len(struct net_device *dev)
1722 struct cp_private *cp = netdev_priv(dev);
1725 spin_lock_irq(&cp->lock);
1726 size = read_eeprom(cp->regs, 0, 8) == 0x8129 ? 256 : 128;
1727 spin_unlock_irq(&cp->lock);
1732 static int cp_get_eeprom(struct net_device *dev,
1733 struct ethtool_eeprom *eeprom, u8 *data)
1735 struct cp_private *cp = netdev_priv(dev);
1736 unsigned int addr_len;
1738 u32 offset = eeprom->offset >> 1;
1739 u32 len = eeprom->len;
1742 eeprom->magic = CP_EEPROM_MAGIC;
1744 spin_lock_irq(&cp->lock);
1746 addr_len = read_eeprom(cp->regs, 0, 8) == 0x8129 ? 8 : 6;
1748 if (eeprom->offset & 1) {
1749 val = read_eeprom(cp->regs, offset, addr_len);
1750 data[i++] = (u8)(val >> 8);
1754 while (i < len - 1) {
1755 val = read_eeprom(cp->regs, offset, addr_len);
1756 data[i++] = (u8)val;
1757 data[i++] = (u8)(val >> 8);
1762 val = read_eeprom(cp->regs, offset, addr_len);
1766 spin_unlock_irq(&cp->lock);
1770 static int cp_set_eeprom(struct net_device *dev,
1771 struct ethtool_eeprom *eeprom, u8 *data)
1773 struct cp_private *cp = netdev_priv(dev);
1774 unsigned int addr_len;
1776 u32 offset = eeprom->offset >> 1;
1777 u32 len = eeprom->len;
1780 if (eeprom->magic != CP_EEPROM_MAGIC)
1783 spin_lock_irq(&cp->lock);
1785 addr_len = read_eeprom(cp->regs, 0, 8) == 0x8129 ? 8 : 6;
1787 if (eeprom->offset & 1) {
1788 val = read_eeprom(cp->regs, offset, addr_len) & 0xff;
1789 val |= (u16)data[i++] << 8;
1790 write_eeprom(cp->regs, offset, val, addr_len);
1794 while (i < len - 1) {
1795 val = (u16)data[i++];
1796 val |= (u16)data[i++] << 8;
1797 write_eeprom(cp->regs, offset, val, addr_len);
1802 val = read_eeprom(cp->regs, offset, addr_len) & 0xff00;
1803 val |= (u16)data[i];
1804 write_eeprom(cp->regs, offset, val, addr_len);
1807 spin_unlock_irq(&cp->lock);
1811 /* Put the board into D3cold state and wait for WakeUp signal */
1812 static void cp_set_d3_state (struct cp_private *cp)
1814 pci_enable_wake (cp->pdev, 0, 1); /* Enable PME# generation */
1815 pci_set_power_state (cp->pdev, PCI_D3hot);
1818 static int cp_init_one (struct pci_dev *pdev, const struct pci_device_id *ent)
1820 struct net_device *dev;
1821 struct cp_private *cp;
1824 resource_size_t pciaddr;
1825 unsigned int addr_len, i, pci_using_dac;
1828 static int version_printed;
1829 if (version_printed++ == 0)
1830 printk("%s", version);
1833 if (pdev->vendor == PCI_VENDOR_ID_REALTEK &&
1834 pdev->device == PCI_DEVICE_ID_REALTEK_8139 && pdev->revision < 0x20) {
1836 "This (id %04x:%04x rev %02x) is not an 8139C+ compatible chip\n",
1837 pdev->vendor, pdev->device, pdev->revision);
1838 dev_err(&pdev->dev, "Try the \"8139too\" driver instead.\n");
1842 dev = alloc_etherdev(sizeof(struct cp_private));
1845 SET_MODULE_OWNER(dev);
1846 SET_NETDEV_DEV(dev, &pdev->dev);
1848 cp = netdev_priv(dev);
1851 cp->msg_enable = (debug < 0 ? CP_DEF_MSG_ENABLE : debug);
1852 spin_lock_init (&cp->lock);
1853 cp->mii_if.dev = dev;
1854 cp->mii_if.mdio_read = mdio_read;
1855 cp->mii_if.mdio_write = mdio_write;
1856 cp->mii_if.phy_id = CP_INTERNAL_PHY;
1857 cp->mii_if.phy_id_mask = 0x1f;
1858 cp->mii_if.reg_num_mask = 0x1f;
1859 cp_set_rxbufsize(cp);
1861 rc = pci_enable_device(pdev);
1865 rc = pci_set_mwi(pdev);
1867 goto err_out_disable;
1869 rc = pci_request_regions(pdev, DRV_NAME);
1873 pciaddr = pci_resource_start(pdev, 1);
1876 dev_err(&pdev->dev, "no MMIO resource\n");
1879 if (pci_resource_len(pdev, 1) < CP_REGS_SIZE) {
1881 dev_err(&pdev->dev, "MMIO resource (%llx) too small\n",
1882 (unsigned long long)pci_resource_len(pdev, 1));
1886 /* Configure DMA attributes. */
1887 if ((sizeof(dma_addr_t) > 4) &&
1888 !pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK) &&
1889 !pci_set_dma_mask(pdev, DMA_64BIT_MASK)) {
1894 rc = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
1897 "No usable DMA configuration, aborting.\n");
1900 rc = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
1903 "No usable consistent DMA configuration, "
1909 cp->cpcmd = (pci_using_dac ? PCIDAC : 0) |
1910 PCIMulRW | RxChkSum | CpRxOn | CpTxOn;
1912 regs = ioremap(pciaddr, CP_REGS_SIZE);
1915 dev_err(&pdev->dev, "Cannot map PCI MMIO (%Lx@%Lx)\n",
1916 (unsigned long long)pci_resource_len(pdev, 1),
1917 (unsigned long long)pciaddr);
1920 dev->base_addr = (unsigned long) regs;
1925 /* read MAC address from EEPROM */
1926 addr_len = read_eeprom (regs, 0, 8) == 0x8129 ? 8 : 6;
1927 for (i = 0; i < 3; i++)
1928 ((u16 *) (dev->dev_addr))[i] =
1929 le16_to_cpu (read_eeprom (regs, i + 7, addr_len));
1930 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
1932 dev->open = cp_open;
1933 dev->stop = cp_close;
1934 dev->set_multicast_list = cp_set_rx_mode;
1935 dev->hard_start_xmit = cp_start_xmit;
1936 dev->get_stats = cp_get_stats;
1937 dev->do_ioctl = cp_ioctl;
1938 #ifdef CONFIG_NET_POLL_CONTROLLER
1939 dev->poll_controller = cp_poll_controller;
1941 netif_napi_add(dev, &cp->napi, cp_rx_poll, 16);
1943 dev->change_mtu = cp_change_mtu;
1945 dev->ethtool_ops = &cp_ethtool_ops;
1946 dev->tx_timeout = cp_tx_timeout;
1947 dev->watchdog_timeo = TX_TIMEOUT;
1949 #if CP_VLAN_TAG_USED
1950 dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
1951 dev->vlan_rx_register = cp_vlan_rx_register;
1955 dev->features |= NETIF_F_HIGHDMA;
1957 #if 0 /* disabled by default until verified */
1958 dev->features |= NETIF_F_TSO;
1961 dev->irq = pdev->irq;
1963 rc = register_netdev(dev);
1967 printk (KERN_INFO "%s: RTL-8139C+ at 0x%lx, "
1968 "%02x:%02x:%02x:%02x:%02x:%02x, "
1972 dev->dev_addr[0], dev->dev_addr[1],
1973 dev->dev_addr[2], dev->dev_addr[3],
1974 dev->dev_addr[4], dev->dev_addr[5],
1977 pci_set_drvdata(pdev, dev);
1979 /* enable busmastering and memory-write-invalidate */
1980 pci_set_master(pdev);
1982 if (cp->wol_enabled)
1983 cp_set_d3_state (cp);
1990 pci_release_regions(pdev);
1992 pci_clear_mwi(pdev);
1994 pci_disable_device(pdev);
2000 static void cp_remove_one (struct pci_dev *pdev)
2002 struct net_device *dev = pci_get_drvdata(pdev);
2003 struct cp_private *cp = netdev_priv(dev);
2005 unregister_netdev(dev);
2007 if (cp->wol_enabled)
2008 pci_set_power_state (pdev, PCI_D0);
2009 pci_release_regions(pdev);
2010 pci_clear_mwi(pdev);
2011 pci_disable_device(pdev);
2012 pci_set_drvdata(pdev, NULL);
2017 static int cp_suspend (struct pci_dev *pdev, pm_message_t state)
2019 struct net_device *dev = pci_get_drvdata(pdev);
2020 struct cp_private *cp = netdev_priv(dev);
2021 unsigned long flags;
2023 if (!netif_running(dev))
2026 netif_device_detach (dev);
2027 netif_stop_queue (dev);
2029 spin_lock_irqsave (&cp->lock, flags);
2031 /* Disable Rx and Tx */
2032 cpw16 (IntrMask, 0);
2033 cpw8 (Cmd, cpr8 (Cmd) & (~RxOn | ~TxOn));
2035 spin_unlock_irqrestore (&cp->lock, flags);
2037 pci_save_state(pdev);
2038 pci_enable_wake(pdev, pci_choose_state(pdev, state), cp->wol_enabled);
2039 pci_set_power_state(pdev, pci_choose_state(pdev, state));
2044 static int cp_resume (struct pci_dev *pdev)
2046 struct net_device *dev = pci_get_drvdata (pdev);
2047 struct cp_private *cp = netdev_priv(dev);
2048 unsigned long flags;
2050 if (!netif_running(dev))
2053 netif_device_attach (dev);
2055 pci_set_power_state(pdev, PCI_D0);
2056 pci_restore_state(pdev);
2057 pci_enable_wake(pdev, PCI_D0, 0);
2059 /* FIXME: sh*t may happen if the Rx ring buffer is depleted */
2060 cp_init_rings_index (cp);
2062 netif_start_queue (dev);
2064 spin_lock_irqsave (&cp->lock, flags);
2066 mii_check_media(&cp->mii_if, netif_msg_link(cp), false);
2068 spin_unlock_irqrestore (&cp->lock, flags);
2072 #endif /* CONFIG_PM */
2074 static struct pci_driver cp_driver = {
2076 .id_table = cp_pci_tbl,
2077 .probe = cp_init_one,
2078 .remove = cp_remove_one,
2080 .resume = cp_resume,
2081 .suspend = cp_suspend,
2085 static int __init cp_init (void)
2088 printk("%s", version);
2090 return pci_register_driver(&cp_driver);
2093 static void __exit cp_exit (void)
2095 pci_unregister_driver (&cp_driver);
2098 module_init(cp_init);
2099 module_exit(cp_exit);