1 /* 8139cp.c: A Linux PCI Ethernet driver for the RealTek 8139C+ chips. */
3 Copyright 2001-2004 Jeff Garzik <jgarzik@pobox.com>
5 Copyright (C) 2001, 2002 David S. Miller (davem@redhat.com) [tg3.c]
6 Copyright (C) 2000, 2001 David S. Miller (davem@redhat.com) [sungem.c]
7 Copyright 2001 Manfred Spraul [natsemi.c]
8 Copyright 1999-2001 by Donald Becker. [natsemi.c]
9 Written 1997-2001 by Donald Becker. [8139too.c]
10 Copyright 1998-2001 by Jes Sorensen, <jes@trained-monkey.org>. [acenic.c]
12 This software may be used and distributed according to the terms of
13 the GNU General Public License (GPL), incorporated herein by reference.
14 Drivers based on or derived from this code fall under the GPL and must
15 retain the authorship, copyright and license notice. This file is not
16 a complete program and may only be used when the entire operating
17 system is licensed under the GPL.
19 See the file COPYING in this distribution for more information.
23 Wake-on-LAN support - Felipe Damasio <felipewd@terra.com.br>
24 PCI suspend/resume - Felipe Damasio <felipewd@terra.com.br>
25 LinkChg interrupt - Felipe Damasio <felipewd@terra.com.br>
28 * Test Tx checksumming thoroughly
29 * Implement dev->tx_timeout
32 * Complete reset on PciErr
33 * Consider Rx interrupt mitigation using TimerIntr
34 * Investigate using skb->priority with h/w VLAN priority
35 * Investigate using High Priority Tx Queue with skb->priority
36 * Adjust Rx FIFO threshold and Max Rx DMA burst on Rx FIFO error
37 * Adjust Tx FIFO threshold and Max Tx DMA burst on Tx FIFO error
38 * Implement Tx software interrupt mitigation via
40 * The real minimum of CP_MIN_MTU is 4 bytes. However,
41 for this to be supported, one must(?) turn on packet padding.
42 * Support external MII transceivers (patch available)
45 * TX checksumming is considered experimental. It is off by
46 default, use ethtool to turn it on.
50 #define DRV_NAME "8139cp"
51 #define DRV_VERSION "1.3"
52 #define DRV_RELDATE "Mar 22, 2004"
55 #include <linux/module.h>
56 #include <linux/moduleparam.h>
57 #include <linux/kernel.h>
58 #include <linux/compiler.h>
59 #include <linux/netdevice.h>
60 #include <linux/etherdevice.h>
61 #include <linux/init.h>
62 #include <linux/pci.h>
63 #include <linux/dma-mapping.h>
64 #include <linux/delay.h>
65 #include <linux/ethtool.h>
66 #include <linux/mii.h>
67 #include <linux/if_vlan.h>
68 #include <linux/crc32.h>
71 #include <linux/tcp.h>
72 #include <linux/udp.h>
73 #include <linux/cache.h>
76 #include <asm/uaccess.h>
78 /* VLAN tagging feature enable/disable */
79 #if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
80 #define CP_VLAN_TAG_USED 1
81 #define CP_VLAN_TX_TAG(tx_desc,vlan_tag_value) \
82 do { (tx_desc)->opts2 = (vlan_tag_value); } while (0)
84 #define CP_VLAN_TAG_USED 0
85 #define CP_VLAN_TX_TAG(tx_desc,vlan_tag_value) \
86 do { (tx_desc)->opts2 = 0; } while (0)
89 /* These identify the driver base version and may not be removed. */
90 static char version[] =
91 KERN_INFO DRV_NAME ": 10/100 PCI Ethernet driver v" DRV_VERSION " (" DRV_RELDATE ")\n";
93 MODULE_AUTHOR("Jeff Garzik <jgarzik@pobox.com>");
94 MODULE_DESCRIPTION("RealTek RTL-8139C+ series 10/100 PCI Ethernet driver");
95 MODULE_VERSION(DRV_VERSION);
96 MODULE_LICENSE("GPL");
98 static int debug = -1;
99 module_param(debug, int, 0);
100 MODULE_PARM_DESC (debug, "8139cp: bitmapped message enable number");
102 /* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).
103 The RTL chips use a 64 element hash table based on the Ethernet CRC. */
104 static int multicast_filter_limit = 32;
105 module_param(multicast_filter_limit, int, 0);
106 MODULE_PARM_DESC (multicast_filter_limit, "8139cp: maximum number of filtered multicast addresses");
108 #define PFX DRV_NAME ": "
112 #define TRUE (!FALSE)
115 #define CP_DEF_MSG_ENABLE (NETIF_MSG_DRV | \
118 #define CP_NUM_STATS 14 /* struct cp_dma_stats, plus one */
119 #define CP_STATS_SIZE 64 /* size in bytes of DMA stats block */
120 #define CP_REGS_SIZE (0xff + 1)
121 #define CP_REGS_VER 1 /* version 1 */
122 #define CP_RX_RING_SIZE 64
123 #define CP_TX_RING_SIZE 64
124 #define CP_RING_BYTES \
125 ((sizeof(struct cp_desc) * CP_RX_RING_SIZE) + \
126 (sizeof(struct cp_desc) * CP_TX_RING_SIZE) + \
128 #define NEXT_TX(N) (((N) + 1) & (CP_TX_RING_SIZE - 1))
129 #define NEXT_RX(N) (((N) + 1) & (CP_RX_RING_SIZE - 1))
130 #define TX_BUFFS_AVAIL(CP) \
131 (((CP)->tx_tail <= (CP)->tx_head) ? \
132 (CP)->tx_tail + (CP_TX_RING_SIZE - 1) - (CP)->tx_head : \
133 (CP)->tx_tail - (CP)->tx_head - 1)
135 #define PKT_BUF_SZ 1536 /* Size of each temporary Rx buffer.*/
137 #define CP_INTERNAL_PHY 32
139 /* The following settings are log_2(bytes)-4: 0 == 16 bytes .. 6==1024, 7==end of packet. */
140 #define RX_FIFO_THRESH 5 /* Rx buffer level before first PCI xfer. */
141 #define RX_DMA_BURST 4 /* Maximum PCI burst, '4' is 256 */
142 #define TX_DMA_BURST 6 /* Maximum PCI burst, '6' is 1024 */
143 #define TX_EARLY_THRESH 256 /* Early Tx threshold, in bytes */
145 /* Time in jiffies before concluding the transmitter is hung. */
146 #define TX_TIMEOUT (6*HZ)
148 /* hardware minimum and maximum for a single frame's data payload */
149 #define CP_MIN_MTU 60 /* TODO: allow lower, but pad */
150 #define CP_MAX_MTU 4096
153 /* NIC register offsets */
154 MAC0 = 0x00, /* Ethernet hardware address. */
155 MAR0 = 0x08, /* Multicast filter. */
156 StatsAddr = 0x10, /* 64-bit start addr of 64-byte DMA stats blk */
157 TxRingAddr = 0x20, /* 64-bit start addr of Tx ring */
158 HiTxRingAddr = 0x28, /* 64-bit start addr of high priority Tx ring */
159 Cmd = 0x37, /* Command register */
160 IntrMask = 0x3C, /* Interrupt mask */
161 IntrStatus = 0x3E, /* Interrupt status */
162 TxConfig = 0x40, /* Tx configuration */
163 ChipVersion = 0x43, /* 8-bit chip version, inside TxConfig */
164 RxConfig = 0x44, /* Rx configuration */
165 RxMissed = 0x4C, /* 24 bits valid, write clears */
166 Cfg9346 = 0x50, /* EEPROM select/control; Cfg reg [un]lock */
167 Config1 = 0x52, /* Config1 */
168 Config3 = 0x59, /* Config3 */
169 Config4 = 0x5A, /* Config4 */
170 MultiIntr = 0x5C, /* Multiple interrupt select */
171 BasicModeCtrl = 0x62, /* MII BMCR */
172 BasicModeStatus = 0x64, /* MII BMSR */
173 NWayAdvert = 0x66, /* MII ADVERTISE */
174 NWayLPAR = 0x68, /* MII LPA */
175 NWayExpansion = 0x6A, /* MII Expansion */
176 Config5 = 0xD8, /* Config5 */
177 TxPoll = 0xD9, /* Tell chip to check Tx descriptors for work */
178 RxMaxSize = 0xDA, /* Max size of an Rx packet (8169 only) */
179 CpCmd = 0xE0, /* C+ Command register (C+ mode only) */
180 IntrMitigate = 0xE2, /* rx/tx interrupt mitigation control */
181 RxRingAddr = 0xE4, /* 64-bit start addr of Rx ring */
182 TxThresh = 0xEC, /* Early Tx threshold */
183 OldRxBufAddr = 0x30, /* DMA address of Rx ring buffer (C mode) */
184 OldTSD0 = 0x10, /* DMA address of first Tx desc (C mode) */
186 /* Tx and Rx status descriptors */
187 DescOwn = (1 << 31), /* Descriptor is owned by NIC */
188 RingEnd = (1 << 30), /* End of descriptor ring */
189 FirstFrag = (1 << 29), /* First segment of a packet */
190 LastFrag = (1 << 28), /* Final segment of a packet */
191 LargeSend = (1 << 27), /* TCP Large Send Offload (TSO) */
192 MSSShift = 16, /* MSS value position */
193 MSSMask = 0xfff, /* MSS value: 11 bits */
194 TxError = (1 << 23), /* Tx error summary */
195 RxError = (1 << 20), /* Rx error summary */
196 IPCS = (1 << 18), /* Calculate IP checksum */
197 UDPCS = (1 << 17), /* Calculate UDP/IP checksum */
198 TCPCS = (1 << 16), /* Calculate TCP/IP checksum */
199 TxVlanTag = (1 << 17), /* Add VLAN tag */
200 RxVlanTagged = (1 << 16), /* Rx VLAN tag available */
201 IPFail = (1 << 15), /* IP checksum failed */
202 UDPFail = (1 << 14), /* UDP/IP checksum failed */
203 TCPFail = (1 << 13), /* TCP/IP checksum failed */
204 NormalTxPoll = (1 << 6), /* One or more normal Tx packets to send */
205 PID1 = (1 << 17), /* 2 protocol id bits: 0==non-IP, */
206 PID0 = (1 << 16), /* 1==UDP/IP, 2==TCP/IP, 3==IP */
210 TxFIFOUnder = (1 << 25), /* Tx FIFO underrun */
211 TxOWC = (1 << 22), /* Tx Out-of-window collision */
212 TxLinkFail = (1 << 21), /* Link failed during Tx of packet */
213 TxMaxCol = (1 << 20), /* Tx aborted due to excessive collisions */
214 TxColCntShift = 16, /* Shift, to get 4-bit Tx collision cnt */
215 TxColCntMask = 0x01 | 0x02 | 0x04 | 0x08, /* 4-bit collision count */
216 RxErrFrame = (1 << 27), /* Rx frame alignment error */
217 RxMcast = (1 << 26), /* Rx multicast packet rcv'd */
218 RxErrCRC = (1 << 18), /* Rx CRC error */
219 RxErrRunt = (1 << 19), /* Rx error, packet < 64 bytes */
220 RxErrLong = (1 << 21), /* Rx error, packet > 4096 bytes */
221 RxErrFIFO = (1 << 22), /* Rx error, FIFO overflowed, pkt bad */
223 /* StatsAddr register */
224 DumpStats = (1 << 3), /* Begin stats dump */
226 /* RxConfig register */
227 RxCfgFIFOShift = 13, /* Shift, to get Rx FIFO thresh value */
228 RxCfgDMAShift = 8, /* Shift, to get Rx Max DMA value */
229 AcceptErr = 0x20, /* Accept packets with CRC errors */
230 AcceptRunt = 0x10, /* Accept runt (<64 bytes) packets */
231 AcceptBroadcast = 0x08, /* Accept broadcast packets */
232 AcceptMulticast = 0x04, /* Accept multicast packets */
233 AcceptMyPhys = 0x02, /* Accept pkts with our MAC as dest */
234 AcceptAllPhys = 0x01, /* Accept all pkts w/ physical dest */
236 /* IntrMask / IntrStatus registers */
237 PciErr = (1 << 15), /* System error on the PCI bus */
238 TimerIntr = (1 << 14), /* Asserted when TCTR reaches TimerInt value */
239 LenChg = (1 << 13), /* Cable length change */
240 SWInt = (1 << 8), /* Software-requested interrupt */
241 TxEmpty = (1 << 7), /* No Tx descriptors available */
242 RxFIFOOvr = (1 << 6), /* Rx FIFO Overflow */
243 LinkChg = (1 << 5), /* Packet underrun, or link change */
244 RxEmpty = (1 << 4), /* No Rx descriptors available */
245 TxErr = (1 << 3), /* Tx error */
246 TxOK = (1 << 2), /* Tx packet sent */
247 RxErr = (1 << 1), /* Rx error */
248 RxOK = (1 << 0), /* Rx packet received */
249 IntrResvd = (1 << 10), /* reserved, according to RealTek engineers,
250 but hardware likes to raise it */
252 IntrAll = PciErr | TimerIntr | LenChg | SWInt | TxEmpty |
253 RxFIFOOvr | LinkChg | RxEmpty | TxErr | TxOK |
254 RxErr | RxOK | IntrResvd,
256 /* C mode command register */
257 CmdReset = (1 << 4), /* Enable to reset; self-clearing */
258 RxOn = (1 << 3), /* Rx mode enable */
259 TxOn = (1 << 2), /* Tx mode enable */
261 /* C+ mode command register */
262 RxVlanOn = (1 << 6), /* Rx VLAN de-tagging enable */
263 RxChkSum = (1 << 5), /* Rx checksum offload enable */
264 PCIDAC = (1 << 4), /* PCI Dual Address Cycle (64-bit PCI) */
265 PCIMulRW = (1 << 3), /* Enable PCI read/write multiple */
266 CpRxOn = (1 << 1), /* Rx mode enable */
267 CpTxOn = (1 << 0), /* Tx mode enable */
269 /* Cfg9436 EEPROM control register */
270 Cfg9346_Lock = 0x00, /* Lock ConfigX/MII register access */
271 Cfg9346_Unlock = 0xC0, /* Unlock ConfigX/MII register access */
273 /* TxConfig register */
274 IFG = (1 << 25) | (1 << 24), /* standard IEEE interframe gap */
275 TxDMAShift = 8, /* DMA burst value (0-7) is shift this many bits */
277 /* Early Tx Threshold register */
278 TxThreshMask = 0x3f, /* Mask bits 5-0 */
279 TxThreshMax = 2048, /* Max early Tx threshold */
281 /* Config1 register */
282 DriverLoaded = (1 << 5), /* Software marker, driver is loaded */
283 LWACT = (1 << 4), /* LWAKE active mode */
284 PMEnable = (1 << 0), /* Enable various PM features of chip */
286 /* Config3 register */
287 PARMEnable = (1 << 6), /* Enable auto-loading of PHY parms */
288 MagicPacket = (1 << 5), /* Wake up when receives a Magic Packet */
289 LinkUp = (1 << 4), /* Wake up when the cable connection is re-established */
291 /* Config4 register */
292 LWPTN = (1 << 1), /* LWAKE Pattern */
293 LWPME = (1 << 4), /* LANWAKE vs PMEB */
295 /* Config5 register */
296 BWF = (1 << 6), /* Accept Broadcast wakeup frame */
297 MWF = (1 << 5), /* Accept Multicast wakeup frame */
298 UWF = (1 << 4), /* Accept Unicast wakeup frame */
299 LANWake = (1 << 1), /* Enable LANWake signal */
300 PMEStatus = (1 << 0), /* PME status can be reset by PCI RST# */
302 cp_norx_intr_mask = PciErr | LinkChg | TxOK | TxErr | TxEmpty,
303 cp_rx_intr_mask = RxOK | RxErr | RxEmpty | RxFIFOOvr,
304 cp_intr_mask = cp_rx_intr_mask | cp_norx_intr_mask,
307 static const unsigned int cp_rx_config =
308 (RX_FIFO_THRESH << RxCfgFIFOShift) |
309 (RX_DMA_BURST << RxCfgDMAShift);
323 struct cp_dma_stats {
337 } __attribute__((packed));
339 struct cp_extra_stats {
340 unsigned long rx_frags;
345 struct net_device *dev;
349 struct pci_dev *pdev;
353 struct net_device_stats net_stats;
354 struct cp_extra_stats cp_stats;
356 unsigned rx_tail ____cacheline_aligned;
357 struct cp_desc *rx_ring;
358 struct ring_info rx_skb[CP_RX_RING_SIZE];
361 unsigned tx_head ____cacheline_aligned;
364 struct cp_desc *tx_ring;
365 struct ring_info tx_skb[CP_TX_RING_SIZE];
369 struct vlan_group *vlgrp;
372 unsigned int wol_enabled : 1; /* Is Wake-on-LAN enabled? */
374 struct mii_if_info mii_if;
377 #define cpr8(reg) readb(cp->regs + (reg))
378 #define cpr16(reg) readw(cp->regs + (reg))
379 #define cpr32(reg) readl(cp->regs + (reg))
380 #define cpw8(reg,val) writeb((val), cp->regs + (reg))
381 #define cpw16(reg,val) writew((val), cp->regs + (reg))
382 #define cpw32(reg,val) writel((val), cp->regs + (reg))
383 #define cpw8_f(reg,val) do { \
384 writeb((val), cp->regs + (reg)); \
385 readb(cp->regs + (reg)); \
387 #define cpw16_f(reg,val) do { \
388 writew((val), cp->regs + (reg)); \
389 readw(cp->regs + (reg)); \
391 #define cpw32_f(reg,val) do { \
392 writel((val), cp->regs + (reg)); \
393 readl(cp->regs + (reg)); \
397 static void __cp_set_rx_mode (struct net_device *dev);
398 static void cp_tx (struct cp_private *cp);
399 static void cp_clean_rings (struct cp_private *cp);
400 #ifdef CONFIG_NET_POLL_CONTROLLER
401 static void cp_poll_controller(struct net_device *dev);
403 static int cp_get_eeprom_len(struct net_device *dev);
404 static int cp_get_eeprom(struct net_device *dev,
405 struct ethtool_eeprom *eeprom, u8 *data);
406 static int cp_set_eeprom(struct net_device *dev,
407 struct ethtool_eeprom *eeprom, u8 *data);
409 static struct pci_device_id cp_pci_tbl[] = {
410 { PCI_VENDOR_ID_REALTEK, PCI_DEVICE_ID_REALTEK_8139,
411 PCI_ANY_ID, PCI_ANY_ID, 0, 0, },
412 { PCI_VENDOR_ID_TTTECH, PCI_DEVICE_ID_TTTECH_MC322,
413 PCI_ANY_ID, PCI_ANY_ID, 0, 0, },
416 MODULE_DEVICE_TABLE(pci, cp_pci_tbl);
419 const char str[ETH_GSTRING_LEN];
420 } ethtool_stats_keys[] = {
439 static void cp_vlan_rx_register(struct net_device *dev, struct vlan_group *grp)
441 struct cp_private *cp = netdev_priv(dev);
444 spin_lock_irqsave(&cp->lock, flags);
446 cp->cpcmd |= RxVlanOn;
447 cpw16(CpCmd, cp->cpcmd);
448 spin_unlock_irqrestore(&cp->lock, flags);
451 static void cp_vlan_rx_kill_vid(struct net_device *dev, unsigned short vid)
453 struct cp_private *cp = netdev_priv(dev);
456 spin_lock_irqsave(&cp->lock, flags);
457 cp->cpcmd &= ~RxVlanOn;
458 cpw16(CpCmd, cp->cpcmd);
460 cp->vlgrp->vlan_devices[vid] = NULL;
461 spin_unlock_irqrestore(&cp->lock, flags);
463 #endif /* CP_VLAN_TAG_USED */
465 static inline void cp_set_rxbufsize (struct cp_private *cp)
467 unsigned int mtu = cp->dev->mtu;
469 if (mtu > ETH_DATA_LEN)
470 /* MTU + ethernet header + FCS + optional VLAN tag */
471 cp->rx_buf_sz = mtu + ETH_HLEN + 8;
473 cp->rx_buf_sz = PKT_BUF_SZ;
476 static inline void cp_rx_skb (struct cp_private *cp, struct sk_buff *skb,
477 struct cp_desc *desc)
479 skb->protocol = eth_type_trans (skb, cp->dev);
481 cp->net_stats.rx_packets++;
482 cp->net_stats.rx_bytes += skb->len;
483 cp->dev->last_rx = jiffies;
486 if (cp->vlgrp && (desc->opts2 & RxVlanTagged)) {
487 vlan_hwaccel_receive_skb(skb, cp->vlgrp,
488 be16_to_cpu(desc->opts2 & 0xffff));
491 netif_receive_skb(skb);
494 static void cp_rx_err_acct (struct cp_private *cp, unsigned rx_tail,
497 if (netif_msg_rx_err (cp))
499 "%s: rx err, slot %d status 0x%x len %d\n",
500 cp->dev->name, rx_tail, status, len);
501 cp->net_stats.rx_errors++;
502 if (status & RxErrFrame)
503 cp->net_stats.rx_frame_errors++;
504 if (status & RxErrCRC)
505 cp->net_stats.rx_crc_errors++;
506 if ((status & RxErrRunt) || (status & RxErrLong))
507 cp->net_stats.rx_length_errors++;
508 if ((status & (FirstFrag | LastFrag)) != (FirstFrag | LastFrag))
509 cp->net_stats.rx_length_errors++;
510 if (status & RxErrFIFO)
511 cp->net_stats.rx_fifo_errors++;
514 static inline unsigned int cp_rx_csum_ok (u32 status)
516 unsigned int protocol = (status >> 16) & 0x3;
518 if (likely((protocol == RxProtoTCP) && (!(status & TCPFail))))
520 else if ((protocol == RxProtoUDP) && (!(status & UDPFail)))
522 else if ((protocol == RxProtoIP) && (!(status & IPFail)))
527 static int cp_rx_poll (struct net_device *dev, int *budget)
529 struct cp_private *cp = netdev_priv(dev);
530 unsigned rx_tail = cp->rx_tail;
531 unsigned rx_work = dev->quota;
536 cpw16(IntrStatus, cp_rx_intr_mask);
541 struct sk_buff *skb, *new_skb;
542 struct cp_desc *desc;
545 skb = cp->rx_skb[rx_tail].skb;
548 desc = &cp->rx_ring[rx_tail];
549 status = le32_to_cpu(desc->opts1);
550 if (status & DescOwn)
553 len = (status & 0x1fff) - 4;
554 mapping = cp->rx_skb[rx_tail].mapping;
556 if ((status & (FirstFrag | LastFrag)) != (FirstFrag | LastFrag)) {
557 /* we don't support incoming fragmented frames.
558 * instead, we attempt to ensure that the
559 * pre-allocated RX skbs are properly sized such
560 * that RX fragments are never encountered
562 cp_rx_err_acct(cp, rx_tail, status, len);
563 cp->net_stats.rx_dropped++;
564 cp->cp_stats.rx_frags++;
568 if (status & (RxError | RxErrFIFO)) {
569 cp_rx_err_acct(cp, rx_tail, status, len);
573 if (netif_msg_rx_status(cp))
574 printk(KERN_DEBUG "%s: rx slot %d status 0x%x len %d\n",
575 cp->dev->name, rx_tail, status, len);
577 buflen = cp->rx_buf_sz + RX_OFFSET;
578 new_skb = dev_alloc_skb (buflen);
580 cp->net_stats.rx_dropped++;
584 skb_reserve(new_skb, RX_OFFSET);
585 new_skb->dev = cp->dev;
587 pci_unmap_single(cp->pdev, mapping,
588 buflen, PCI_DMA_FROMDEVICE);
590 /* Handle checksum offloading for incoming packets. */
591 if (cp_rx_csum_ok(status))
592 skb->ip_summed = CHECKSUM_UNNECESSARY;
594 skb->ip_summed = CHECKSUM_NONE;
599 cp->rx_skb[rx_tail].mapping =
600 pci_map_single(cp->pdev, new_skb->data,
601 buflen, PCI_DMA_FROMDEVICE);
602 cp->rx_skb[rx_tail].skb = new_skb;
604 cp_rx_skb(cp, skb, desc);
608 cp->rx_ring[rx_tail].opts2 = 0;
609 cp->rx_ring[rx_tail].addr = cpu_to_le64(mapping);
610 if (rx_tail == (CP_RX_RING_SIZE - 1))
611 desc->opts1 = cpu_to_le32(DescOwn | RingEnd |
614 desc->opts1 = cpu_to_le32(DescOwn | cp->rx_buf_sz);
615 rx_tail = NEXT_RX(rx_tail);
621 cp->rx_tail = rx_tail;
626 /* if we did not reach work limit, then we're done with
627 * this round of polling
630 if (cpr16(IntrStatus) & cp_rx_intr_mask)
634 cpw16_f(IntrMask, cp_intr_mask);
635 __netif_rx_complete(dev);
641 return 1; /* not done */
645 cp_interrupt (int irq, void *dev_instance, struct pt_regs *regs)
647 struct net_device *dev = dev_instance;
648 struct cp_private *cp;
651 if (unlikely(dev == NULL))
653 cp = netdev_priv(dev);
655 status = cpr16(IntrStatus);
656 if (!status || (status == 0xFFFF))
659 if (netif_msg_intr(cp))
660 printk(KERN_DEBUG "%s: intr, status %04x cmd %02x cpcmd %04x\n",
661 dev->name, status, cpr8(Cmd), cpr16(CpCmd));
663 cpw16(IntrStatus, status & ~cp_rx_intr_mask);
665 spin_lock(&cp->lock);
667 /* close possible race's with dev_close */
668 if (unlikely(!netif_running(dev))) {
670 spin_unlock(&cp->lock);
674 if (status & (RxOK | RxErr | RxEmpty | RxFIFOOvr))
675 if (netif_rx_schedule_prep(dev)) {
676 cpw16_f(IntrMask, cp_norx_intr_mask);
677 __netif_rx_schedule(dev);
680 if (status & (TxOK | TxErr | TxEmpty | SWInt))
682 if (status & LinkChg)
683 mii_check_media(&cp->mii_if, netif_msg_link(cp), FALSE);
685 spin_unlock(&cp->lock);
687 if (status & PciErr) {
690 pci_read_config_word(cp->pdev, PCI_STATUS, &pci_status);
691 pci_write_config_word(cp->pdev, PCI_STATUS, pci_status);
692 printk(KERN_ERR "%s: PCI bus error, status=%04x, PCI status=%04x\n",
693 dev->name, status, pci_status);
695 /* TODO: reset hardware */
701 #ifdef CONFIG_NET_POLL_CONTROLLER
703 * Polling receive - used by netconsole and other diagnostic tools
704 * to allow network i/o with interrupts disabled.
706 static void cp_poll_controller(struct net_device *dev)
708 disable_irq(dev->irq);
709 cp_interrupt(dev->irq, dev, NULL);
710 enable_irq(dev->irq);
714 static void cp_tx (struct cp_private *cp)
716 unsigned tx_head = cp->tx_head;
717 unsigned tx_tail = cp->tx_tail;
719 while (tx_tail != tx_head) {
724 status = le32_to_cpu(cp->tx_ring[tx_tail].opts1);
725 if (status & DescOwn)
728 skb = cp->tx_skb[tx_tail].skb;
731 pci_unmap_single(cp->pdev, cp->tx_skb[tx_tail].mapping,
732 cp->tx_skb[tx_tail].len, PCI_DMA_TODEVICE);
734 if (status & LastFrag) {
735 if (status & (TxError | TxFIFOUnder)) {
736 if (netif_msg_tx_err(cp))
737 printk(KERN_DEBUG "%s: tx err, status 0x%x\n",
738 cp->dev->name, status);
739 cp->net_stats.tx_errors++;
741 cp->net_stats.tx_window_errors++;
742 if (status & TxMaxCol)
743 cp->net_stats.tx_aborted_errors++;
744 if (status & TxLinkFail)
745 cp->net_stats.tx_carrier_errors++;
746 if (status & TxFIFOUnder)
747 cp->net_stats.tx_fifo_errors++;
749 cp->net_stats.collisions +=
750 ((status >> TxColCntShift) & TxColCntMask);
751 cp->net_stats.tx_packets++;
752 cp->net_stats.tx_bytes += skb->len;
753 if (netif_msg_tx_done(cp))
754 printk(KERN_DEBUG "%s: tx done, slot %d\n", cp->dev->name, tx_tail);
756 dev_kfree_skb_irq(skb);
759 cp->tx_skb[tx_tail].skb = NULL;
761 tx_tail = NEXT_TX(tx_tail);
764 cp->tx_tail = tx_tail;
766 if (TX_BUFFS_AVAIL(cp) > (MAX_SKB_FRAGS + 1))
767 netif_wake_queue(cp->dev);
770 static int cp_start_xmit (struct sk_buff *skb, struct net_device *dev)
772 struct cp_private *cp = netdev_priv(dev);
780 spin_lock_irq(&cp->lock);
782 /* This is a hard error, log it. */
783 if (TX_BUFFS_AVAIL(cp) <= (skb_shinfo(skb)->nr_frags + 1)) {
784 netif_stop_queue(dev);
785 spin_unlock_irq(&cp->lock);
786 printk(KERN_ERR PFX "%s: BUG! Tx Ring full when queue awake!\n",
792 if (cp->vlgrp && vlan_tx_tag_present(skb))
793 vlan_tag = TxVlanTag | cpu_to_be16(vlan_tx_tag_get(skb));
797 eor = (entry == (CP_TX_RING_SIZE - 1)) ? RingEnd : 0;
798 if (dev->features & NETIF_F_TSO)
799 mss = skb_shinfo(skb)->gso_size;
801 if (skb_shinfo(skb)->nr_frags == 0) {
802 struct cp_desc *txd = &cp->tx_ring[entry];
807 mapping = pci_map_single(cp->pdev, skb->data, len, PCI_DMA_TODEVICE);
808 CP_VLAN_TX_TAG(txd, vlan_tag);
809 txd->addr = cpu_to_le64(mapping);
812 flags = eor | len | DescOwn | FirstFrag | LastFrag;
815 flags |= LargeSend | ((mss & MSSMask) << MSSShift);
816 else if (skb->ip_summed == CHECKSUM_HW) {
817 const struct iphdr *ip = skb->nh.iph;
818 if (ip->protocol == IPPROTO_TCP)
819 flags |= IPCS | TCPCS;
820 else if (ip->protocol == IPPROTO_UDP)
821 flags |= IPCS | UDPCS;
823 WARN_ON(1); /* we need a WARN() */
826 txd->opts1 = cpu_to_le32(flags);
829 cp->tx_skb[entry].skb = skb;
830 cp->tx_skb[entry].mapping = mapping;
831 cp->tx_skb[entry].len = len;
832 entry = NEXT_TX(entry);
835 u32 first_len, first_eor;
836 dma_addr_t first_mapping;
837 int frag, first_entry = entry;
838 const struct iphdr *ip = skb->nh.iph;
840 /* We must give this initial chunk to the device last.
841 * Otherwise we could race with the device.
844 first_len = skb_headlen(skb);
845 first_mapping = pci_map_single(cp->pdev, skb->data,
846 first_len, PCI_DMA_TODEVICE);
847 cp->tx_skb[entry].skb = skb;
848 cp->tx_skb[entry].mapping = first_mapping;
849 cp->tx_skb[entry].len = first_len;
850 entry = NEXT_TX(entry);
852 for (frag = 0; frag < skb_shinfo(skb)->nr_frags; frag++) {
853 skb_frag_t *this_frag = &skb_shinfo(skb)->frags[frag];
858 len = this_frag->size;
859 mapping = pci_map_single(cp->pdev,
860 ((void *) page_address(this_frag->page) +
861 this_frag->page_offset),
862 len, PCI_DMA_TODEVICE);
863 eor = (entry == (CP_TX_RING_SIZE - 1)) ? RingEnd : 0;
865 ctrl = eor | len | DescOwn;
869 ((mss & MSSMask) << MSSShift);
870 else if (skb->ip_summed == CHECKSUM_HW) {
871 if (ip->protocol == IPPROTO_TCP)
872 ctrl |= IPCS | TCPCS;
873 else if (ip->protocol == IPPROTO_UDP)
874 ctrl |= IPCS | UDPCS;
879 if (frag == skb_shinfo(skb)->nr_frags - 1)
882 txd = &cp->tx_ring[entry];
883 CP_VLAN_TX_TAG(txd, vlan_tag);
884 txd->addr = cpu_to_le64(mapping);
887 txd->opts1 = cpu_to_le32(ctrl);
890 cp->tx_skb[entry].skb = skb;
891 cp->tx_skb[entry].mapping = mapping;
892 cp->tx_skb[entry].len = len;
893 entry = NEXT_TX(entry);
896 txd = &cp->tx_ring[first_entry];
897 CP_VLAN_TX_TAG(txd, vlan_tag);
898 txd->addr = cpu_to_le64(first_mapping);
901 if (skb->ip_summed == CHECKSUM_HW) {
902 if (ip->protocol == IPPROTO_TCP)
903 txd->opts1 = cpu_to_le32(first_eor | first_len |
904 FirstFrag | DescOwn |
906 else if (ip->protocol == IPPROTO_UDP)
907 txd->opts1 = cpu_to_le32(first_eor | first_len |
908 FirstFrag | DescOwn |
913 txd->opts1 = cpu_to_le32(first_eor | first_len |
914 FirstFrag | DescOwn);
918 if (netif_msg_tx_queued(cp))
919 printk(KERN_DEBUG "%s: tx queued, slot %d, skblen %d\n",
920 dev->name, entry, skb->len);
921 if (TX_BUFFS_AVAIL(cp) <= (MAX_SKB_FRAGS + 1))
922 netif_stop_queue(dev);
924 spin_unlock_irq(&cp->lock);
926 cpw8(TxPoll, NormalTxPoll);
927 dev->trans_start = jiffies;
932 /* Set or clear the multicast filter for this adaptor.
933 This routine is not state sensitive and need not be SMP locked. */
935 static void __cp_set_rx_mode (struct net_device *dev)
937 struct cp_private *cp = netdev_priv(dev);
938 u32 mc_filter[2]; /* Multicast hash filter */
942 /* Note: do not reorder, GCC is clever about common statements. */
943 if (dev->flags & IFF_PROMISC) {
944 /* Unconditionally log net taps. */
946 AcceptBroadcast | AcceptMulticast | AcceptMyPhys |
948 mc_filter[1] = mc_filter[0] = 0xffffffff;
949 } else if ((dev->mc_count > multicast_filter_limit)
950 || (dev->flags & IFF_ALLMULTI)) {
951 /* Too many to filter perfectly -- accept all multicasts. */
952 rx_mode = AcceptBroadcast | AcceptMulticast | AcceptMyPhys;
953 mc_filter[1] = mc_filter[0] = 0xffffffff;
955 struct dev_mc_list *mclist;
956 rx_mode = AcceptBroadcast | AcceptMyPhys;
957 mc_filter[1] = mc_filter[0] = 0;
958 for (i = 0, mclist = dev->mc_list; mclist && i < dev->mc_count;
959 i++, mclist = mclist->next) {
960 int bit_nr = ether_crc(ETH_ALEN, mclist->dmi_addr) >> 26;
962 mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31);
963 rx_mode |= AcceptMulticast;
967 /* We can safely update without stopping the chip. */
968 tmp = cp_rx_config | rx_mode;
969 if (cp->rx_config != tmp) {
970 cpw32_f (RxConfig, tmp);
973 cpw32_f (MAR0 + 0, mc_filter[0]);
974 cpw32_f (MAR0 + 4, mc_filter[1]);
977 static void cp_set_rx_mode (struct net_device *dev)
980 struct cp_private *cp = netdev_priv(dev);
982 spin_lock_irqsave (&cp->lock, flags);
983 __cp_set_rx_mode(dev);
984 spin_unlock_irqrestore (&cp->lock, flags);
987 static void __cp_get_stats(struct cp_private *cp)
989 /* only lower 24 bits valid; write any value to clear */
990 cp->net_stats.rx_missed_errors += (cpr32 (RxMissed) & 0xffffff);
994 static struct net_device_stats *cp_get_stats(struct net_device *dev)
996 struct cp_private *cp = netdev_priv(dev);
999 /* The chip only need report frame silently dropped. */
1000 spin_lock_irqsave(&cp->lock, flags);
1001 if (netif_running(dev) && netif_device_present(dev))
1003 spin_unlock_irqrestore(&cp->lock, flags);
1005 return &cp->net_stats;
1008 static void cp_stop_hw (struct cp_private *cp)
1010 cpw16(IntrStatus, ~(cpr16(IntrStatus)));
1011 cpw16_f(IntrMask, 0);
1014 cpw16_f(IntrStatus, ~(cpr16(IntrStatus)));
1017 cp->tx_head = cp->tx_tail = 0;
1020 static void cp_reset_hw (struct cp_private *cp)
1022 unsigned work = 1000;
1024 cpw8(Cmd, CmdReset);
1027 if (!(cpr8(Cmd) & CmdReset))
1030 schedule_timeout_uninterruptible(10);
1033 printk(KERN_ERR "%s: hardware reset timeout\n", cp->dev->name);
1036 static inline void cp_start_hw (struct cp_private *cp)
1038 cpw16(CpCmd, cp->cpcmd);
1039 cpw8(Cmd, RxOn | TxOn);
1042 static void cp_init_hw (struct cp_private *cp)
1044 struct net_device *dev = cp->dev;
1045 dma_addr_t ring_dma;
1049 cpw8_f (Cfg9346, Cfg9346_Unlock);
1051 /* Restore our idea of the MAC address. */
1052 cpw32_f (MAC0 + 0, cpu_to_le32 (*(u32 *) (dev->dev_addr + 0)));
1053 cpw32_f (MAC0 + 4, cpu_to_le32 (*(u32 *) (dev->dev_addr + 4)));
1056 cpw8(TxThresh, 0x06); /* XXX convert magic num to a constant */
1058 __cp_set_rx_mode(dev);
1059 cpw32_f (TxConfig, IFG | (TX_DMA_BURST << TxDMAShift));
1061 cpw8(Config1, cpr8(Config1) | DriverLoaded | PMEnable);
1062 /* Disable Wake-on-LAN. Can be turned on with ETHTOOL_SWOL */
1063 cpw8(Config3, PARMEnable);
1064 cp->wol_enabled = 0;
1066 cpw8(Config5, cpr8(Config5) & PMEStatus);
1068 cpw32_f(HiTxRingAddr, 0);
1069 cpw32_f(HiTxRingAddr + 4, 0);
1071 ring_dma = cp->ring_dma;
1072 cpw32_f(RxRingAddr, ring_dma & 0xffffffff);
1073 cpw32_f(RxRingAddr + 4, (ring_dma >> 16) >> 16);
1075 ring_dma += sizeof(struct cp_desc) * CP_RX_RING_SIZE;
1076 cpw32_f(TxRingAddr, ring_dma & 0xffffffff);
1077 cpw32_f(TxRingAddr + 4, (ring_dma >> 16) >> 16);
1079 cpw16(MultiIntr, 0);
1081 cpw16_f(IntrMask, cp_intr_mask);
1083 cpw8_f(Cfg9346, Cfg9346_Lock);
1086 static int cp_refill_rx (struct cp_private *cp)
1090 for (i = 0; i < CP_RX_RING_SIZE; i++) {
1091 struct sk_buff *skb;
1093 skb = dev_alloc_skb(cp->rx_buf_sz + RX_OFFSET);
1098 skb_reserve(skb, RX_OFFSET);
1100 cp->rx_skb[i].mapping = pci_map_single(cp->pdev,
1101 skb->data, cp->rx_buf_sz, PCI_DMA_FROMDEVICE);
1102 cp->rx_skb[i].skb = skb;
1104 cp->rx_ring[i].opts2 = 0;
1105 cp->rx_ring[i].addr = cpu_to_le64(cp->rx_skb[i].mapping);
1106 if (i == (CP_RX_RING_SIZE - 1))
1107 cp->rx_ring[i].opts1 =
1108 cpu_to_le32(DescOwn | RingEnd | cp->rx_buf_sz);
1110 cp->rx_ring[i].opts1 =
1111 cpu_to_le32(DescOwn | cp->rx_buf_sz);
1121 static void cp_init_rings_index (struct cp_private *cp)
1124 cp->tx_head = cp->tx_tail = 0;
1127 static int cp_init_rings (struct cp_private *cp)
1129 memset(cp->tx_ring, 0, sizeof(struct cp_desc) * CP_TX_RING_SIZE);
1130 cp->tx_ring[CP_TX_RING_SIZE - 1].opts1 = cpu_to_le32(RingEnd);
1132 cp_init_rings_index(cp);
1134 return cp_refill_rx (cp);
1137 static int cp_alloc_rings (struct cp_private *cp)
1141 mem = pci_alloc_consistent(cp->pdev, CP_RING_BYTES, &cp->ring_dma);
1146 cp->tx_ring = &cp->rx_ring[CP_RX_RING_SIZE];
1148 return cp_init_rings(cp);
1151 static void cp_clean_rings (struct cp_private *cp)
1155 for (i = 0; i < CP_RX_RING_SIZE; i++) {
1156 if (cp->rx_skb[i].skb) {
1157 pci_unmap_single(cp->pdev, cp->rx_skb[i].mapping,
1158 cp->rx_buf_sz, PCI_DMA_FROMDEVICE);
1159 dev_kfree_skb(cp->rx_skb[i].skb);
1163 for (i = 0; i < CP_TX_RING_SIZE; i++) {
1164 if (cp->tx_skb[i].skb) {
1165 struct sk_buff *skb = cp->tx_skb[i].skb;
1167 pci_unmap_single(cp->pdev, cp->tx_skb[i].mapping,
1168 cp->tx_skb[i].len, PCI_DMA_TODEVICE);
1169 if (le32_to_cpu(cp->tx_ring[i].opts1) & LastFrag)
1171 cp->net_stats.tx_dropped++;
1175 memset(cp->rx_ring, 0, sizeof(struct cp_desc) * CP_RX_RING_SIZE);
1176 memset(cp->tx_ring, 0, sizeof(struct cp_desc) * CP_TX_RING_SIZE);
1178 memset(&cp->rx_skb, 0, sizeof(struct ring_info) * CP_RX_RING_SIZE);
1179 memset(&cp->tx_skb, 0, sizeof(struct ring_info) * CP_TX_RING_SIZE);
1182 static void cp_free_rings (struct cp_private *cp)
1185 pci_free_consistent(cp->pdev, CP_RING_BYTES, cp->rx_ring, cp->ring_dma);
1190 static int cp_open (struct net_device *dev)
1192 struct cp_private *cp = netdev_priv(dev);
1195 if (netif_msg_ifup(cp))
1196 printk(KERN_DEBUG "%s: enabling interface\n", dev->name);
1198 rc = cp_alloc_rings(cp);
1204 rc = request_irq(dev->irq, cp_interrupt, IRQF_SHARED, dev->name, dev);
1208 netif_carrier_off(dev);
1209 mii_check_media(&cp->mii_if, netif_msg_link(cp), TRUE);
1210 netif_start_queue(dev);
1220 static int cp_close (struct net_device *dev)
1222 struct cp_private *cp = netdev_priv(dev);
1223 unsigned long flags;
1225 if (netif_msg_ifdown(cp))
1226 printk(KERN_DEBUG "%s: disabling interface\n", dev->name);
1228 spin_lock_irqsave(&cp->lock, flags);
1230 netif_stop_queue(dev);
1231 netif_carrier_off(dev);
1235 spin_unlock_irqrestore(&cp->lock, flags);
1237 synchronize_irq(dev->irq);
1238 free_irq(dev->irq, dev);
1245 static int cp_change_mtu(struct net_device *dev, int new_mtu)
1247 struct cp_private *cp = netdev_priv(dev);
1249 unsigned long flags;
1251 /* check for invalid MTU, according to hardware limits */
1252 if (new_mtu < CP_MIN_MTU || new_mtu > CP_MAX_MTU)
1255 /* if network interface not up, no need for complexity */
1256 if (!netif_running(dev)) {
1258 cp_set_rxbufsize(cp); /* set new rx buf size */
1262 spin_lock_irqsave(&cp->lock, flags);
1264 cp_stop_hw(cp); /* stop h/w and free rings */
1268 cp_set_rxbufsize(cp); /* set new rx buf size */
1270 rc = cp_init_rings(cp); /* realloc and restart h/w */
1273 spin_unlock_irqrestore(&cp->lock, flags);
1279 static const char mii_2_8139_map[8] = {
1290 static int mdio_read(struct net_device *dev, int phy_id, int location)
1292 struct cp_private *cp = netdev_priv(dev);
1294 return location < 8 && mii_2_8139_map[location] ?
1295 readw(cp->regs + mii_2_8139_map[location]) : 0;
1299 static void mdio_write(struct net_device *dev, int phy_id, int location,
1302 struct cp_private *cp = netdev_priv(dev);
1304 if (location == 0) {
1305 cpw8(Cfg9346, Cfg9346_Unlock);
1306 cpw16(BasicModeCtrl, value);
1307 cpw8(Cfg9346, Cfg9346_Lock);
1308 } else if (location < 8 && mii_2_8139_map[location])
1309 cpw16(mii_2_8139_map[location], value);
1312 /* Set the ethtool Wake-on-LAN settings */
1313 static int netdev_set_wol (struct cp_private *cp,
1314 const struct ethtool_wolinfo *wol)
1318 options = cpr8 (Config3) & ~(LinkUp | MagicPacket);
1319 /* If WOL is being disabled, no need for complexity */
1321 if (wol->wolopts & WAKE_PHY) options |= LinkUp;
1322 if (wol->wolopts & WAKE_MAGIC) options |= MagicPacket;
1325 cpw8 (Cfg9346, Cfg9346_Unlock);
1326 cpw8 (Config3, options);
1327 cpw8 (Cfg9346, Cfg9346_Lock);
1329 options = 0; /* Paranoia setting */
1330 options = cpr8 (Config5) & ~(UWF | MWF | BWF);
1331 /* If WOL is being disabled, no need for complexity */
1333 if (wol->wolopts & WAKE_UCAST) options |= UWF;
1334 if (wol->wolopts & WAKE_BCAST) options |= BWF;
1335 if (wol->wolopts & WAKE_MCAST) options |= MWF;
1338 cpw8 (Config5, options);
1340 cp->wol_enabled = (wol->wolopts) ? 1 : 0;
1345 /* Get the ethtool Wake-on-LAN settings */
1346 static void netdev_get_wol (struct cp_private *cp,
1347 struct ethtool_wolinfo *wol)
1351 wol->wolopts = 0; /* Start from scratch */
1352 wol->supported = WAKE_PHY | WAKE_BCAST | WAKE_MAGIC |
1353 WAKE_MCAST | WAKE_UCAST;
1354 /* We don't need to go on if WOL is disabled */
1355 if (!cp->wol_enabled) return;
1357 options = cpr8 (Config3);
1358 if (options & LinkUp) wol->wolopts |= WAKE_PHY;
1359 if (options & MagicPacket) wol->wolopts |= WAKE_MAGIC;
1361 options = 0; /* Paranoia setting */
1362 options = cpr8 (Config5);
1363 if (options & UWF) wol->wolopts |= WAKE_UCAST;
1364 if (options & BWF) wol->wolopts |= WAKE_BCAST;
1365 if (options & MWF) wol->wolopts |= WAKE_MCAST;
1368 static void cp_get_drvinfo (struct net_device *dev, struct ethtool_drvinfo *info)
1370 struct cp_private *cp = netdev_priv(dev);
1372 strcpy (info->driver, DRV_NAME);
1373 strcpy (info->version, DRV_VERSION);
1374 strcpy (info->bus_info, pci_name(cp->pdev));
1377 static int cp_get_regs_len(struct net_device *dev)
1379 return CP_REGS_SIZE;
1382 static int cp_get_stats_count (struct net_device *dev)
1384 return CP_NUM_STATS;
1387 static int cp_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1389 struct cp_private *cp = netdev_priv(dev);
1391 unsigned long flags;
1393 spin_lock_irqsave(&cp->lock, flags);
1394 rc = mii_ethtool_gset(&cp->mii_if, cmd);
1395 spin_unlock_irqrestore(&cp->lock, flags);
1400 static int cp_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1402 struct cp_private *cp = netdev_priv(dev);
1404 unsigned long flags;
1406 spin_lock_irqsave(&cp->lock, flags);
1407 rc = mii_ethtool_sset(&cp->mii_if, cmd);
1408 spin_unlock_irqrestore(&cp->lock, flags);
1413 static int cp_nway_reset(struct net_device *dev)
1415 struct cp_private *cp = netdev_priv(dev);
1416 return mii_nway_restart(&cp->mii_if);
1419 static u32 cp_get_msglevel(struct net_device *dev)
1421 struct cp_private *cp = netdev_priv(dev);
1422 return cp->msg_enable;
1425 static void cp_set_msglevel(struct net_device *dev, u32 value)
1427 struct cp_private *cp = netdev_priv(dev);
1428 cp->msg_enable = value;
1431 static u32 cp_get_rx_csum(struct net_device *dev)
1433 struct cp_private *cp = netdev_priv(dev);
1434 return (cpr16(CpCmd) & RxChkSum) ? 1 : 0;
1437 static int cp_set_rx_csum(struct net_device *dev, u32 data)
1439 struct cp_private *cp = netdev_priv(dev);
1440 u16 cmd = cp->cpcmd, newcmd;
1447 newcmd &= ~RxChkSum;
1449 if (newcmd != cmd) {
1450 unsigned long flags;
1452 spin_lock_irqsave(&cp->lock, flags);
1454 cpw16_f(CpCmd, newcmd);
1455 spin_unlock_irqrestore(&cp->lock, flags);
1461 static void cp_get_regs(struct net_device *dev, struct ethtool_regs *regs,
1464 struct cp_private *cp = netdev_priv(dev);
1465 unsigned long flags;
1467 if (regs->len < CP_REGS_SIZE)
1468 return /* -EINVAL */;
1470 regs->version = CP_REGS_VER;
1472 spin_lock_irqsave(&cp->lock, flags);
1473 memcpy_fromio(p, cp->regs, CP_REGS_SIZE);
1474 spin_unlock_irqrestore(&cp->lock, flags);
1477 static void cp_get_wol (struct net_device *dev, struct ethtool_wolinfo *wol)
1479 struct cp_private *cp = netdev_priv(dev);
1480 unsigned long flags;
1482 spin_lock_irqsave (&cp->lock, flags);
1483 netdev_get_wol (cp, wol);
1484 spin_unlock_irqrestore (&cp->lock, flags);
1487 static int cp_set_wol (struct net_device *dev, struct ethtool_wolinfo *wol)
1489 struct cp_private *cp = netdev_priv(dev);
1490 unsigned long flags;
1493 spin_lock_irqsave (&cp->lock, flags);
1494 rc = netdev_set_wol (cp, wol);
1495 spin_unlock_irqrestore (&cp->lock, flags);
1500 static void cp_get_strings (struct net_device *dev, u32 stringset, u8 *buf)
1502 switch (stringset) {
1504 memcpy(buf, ðtool_stats_keys, sizeof(ethtool_stats_keys));
1512 static void cp_get_ethtool_stats (struct net_device *dev,
1513 struct ethtool_stats *estats, u64 *tmp_stats)
1515 struct cp_private *cp = netdev_priv(dev);
1516 struct cp_dma_stats *nic_stats;
1520 nic_stats = pci_alloc_consistent(cp->pdev, sizeof(*nic_stats), &dma);
1524 /* begin NIC statistics dump */
1525 cpw32(StatsAddr + 4, (u64)dma >> 32);
1526 cpw32(StatsAddr, ((u64)dma & DMA_32BIT_MASK) | DumpStats);
1529 for (i = 0; i < 1000; i++) {
1530 if ((cpr32(StatsAddr) & DumpStats) == 0)
1534 cpw32(StatsAddr, 0);
1535 cpw32(StatsAddr + 4, 0);
1539 tmp_stats[i++] = le64_to_cpu(nic_stats->tx_ok);
1540 tmp_stats[i++] = le64_to_cpu(nic_stats->rx_ok);
1541 tmp_stats[i++] = le64_to_cpu(nic_stats->tx_err);
1542 tmp_stats[i++] = le32_to_cpu(nic_stats->rx_err);
1543 tmp_stats[i++] = le16_to_cpu(nic_stats->rx_fifo);
1544 tmp_stats[i++] = le16_to_cpu(nic_stats->frame_align);
1545 tmp_stats[i++] = le32_to_cpu(nic_stats->tx_ok_1col);
1546 tmp_stats[i++] = le32_to_cpu(nic_stats->tx_ok_mcol);
1547 tmp_stats[i++] = le64_to_cpu(nic_stats->rx_ok_phys);
1548 tmp_stats[i++] = le64_to_cpu(nic_stats->rx_ok_bcast);
1549 tmp_stats[i++] = le32_to_cpu(nic_stats->rx_ok_mcast);
1550 tmp_stats[i++] = le16_to_cpu(nic_stats->tx_abort);
1551 tmp_stats[i++] = le16_to_cpu(nic_stats->tx_underrun);
1552 tmp_stats[i++] = cp->cp_stats.rx_frags;
1553 BUG_ON(i != CP_NUM_STATS);
1555 pci_free_consistent(cp->pdev, sizeof(*nic_stats), nic_stats, dma);
1558 static struct ethtool_ops cp_ethtool_ops = {
1559 .get_drvinfo = cp_get_drvinfo,
1560 .get_regs_len = cp_get_regs_len,
1561 .get_stats_count = cp_get_stats_count,
1562 .get_settings = cp_get_settings,
1563 .set_settings = cp_set_settings,
1564 .nway_reset = cp_nway_reset,
1565 .get_link = ethtool_op_get_link,
1566 .get_msglevel = cp_get_msglevel,
1567 .set_msglevel = cp_set_msglevel,
1568 .get_rx_csum = cp_get_rx_csum,
1569 .set_rx_csum = cp_set_rx_csum,
1570 .get_tx_csum = ethtool_op_get_tx_csum,
1571 .set_tx_csum = ethtool_op_set_tx_csum, /* local! */
1572 .get_sg = ethtool_op_get_sg,
1573 .set_sg = ethtool_op_set_sg,
1574 .get_tso = ethtool_op_get_tso,
1575 .set_tso = ethtool_op_set_tso,
1576 .get_regs = cp_get_regs,
1577 .get_wol = cp_get_wol,
1578 .set_wol = cp_set_wol,
1579 .get_strings = cp_get_strings,
1580 .get_ethtool_stats = cp_get_ethtool_stats,
1581 .get_perm_addr = ethtool_op_get_perm_addr,
1582 .get_eeprom_len = cp_get_eeprom_len,
1583 .get_eeprom = cp_get_eeprom,
1584 .set_eeprom = cp_set_eeprom,
1587 static int cp_ioctl (struct net_device *dev, struct ifreq *rq, int cmd)
1589 struct cp_private *cp = netdev_priv(dev);
1591 unsigned long flags;
1593 if (!netif_running(dev))
1596 spin_lock_irqsave(&cp->lock, flags);
1597 rc = generic_mii_ioctl(&cp->mii_if, if_mii(rq), cmd, NULL);
1598 spin_unlock_irqrestore(&cp->lock, flags);
1602 /* Serial EEPROM section. */
1604 /* EEPROM_Ctrl bits. */
1605 #define EE_SHIFT_CLK 0x04 /* EEPROM shift clock. */
1606 #define EE_CS 0x08 /* EEPROM chip select. */
1607 #define EE_DATA_WRITE 0x02 /* EEPROM chip data in. */
1608 #define EE_WRITE_0 0x00
1609 #define EE_WRITE_1 0x02
1610 #define EE_DATA_READ 0x01 /* EEPROM chip data out. */
1611 #define EE_ENB (0x80 | EE_CS)
1613 /* Delay between EEPROM clock transitions.
1614 No extra delay is needed with 33Mhz PCI, but 66Mhz may change this.
1617 #define eeprom_delay() readl(ee_addr)
1619 /* The EEPROM commands include the alway-set leading bit. */
1620 #define EE_EXTEND_CMD (4)
1621 #define EE_WRITE_CMD (5)
1622 #define EE_READ_CMD (6)
1623 #define EE_ERASE_CMD (7)
1625 #define EE_EWDS_ADDR (0)
1626 #define EE_WRAL_ADDR (1)
1627 #define EE_ERAL_ADDR (2)
1628 #define EE_EWEN_ADDR (3)
1630 #define CP_EEPROM_MAGIC PCI_DEVICE_ID_REALTEK_8139
1632 static void eeprom_cmd_start(void __iomem *ee_addr)
1634 writeb (EE_ENB & ~EE_CS, ee_addr);
1635 writeb (EE_ENB, ee_addr);
1639 static void eeprom_cmd(void __iomem *ee_addr, int cmd, int cmd_len)
1643 /* Shift the command bits out. */
1644 for (i = cmd_len - 1; i >= 0; i--) {
1645 int dataval = (cmd & (1 << i)) ? EE_DATA_WRITE : 0;
1646 writeb (EE_ENB | dataval, ee_addr);
1648 writeb (EE_ENB | dataval | EE_SHIFT_CLK, ee_addr);
1651 writeb (EE_ENB, ee_addr);
1655 static void eeprom_cmd_end(void __iomem *ee_addr)
1657 writeb (~EE_CS, ee_addr);
1661 static void eeprom_extend_cmd(void __iomem *ee_addr, int extend_cmd,
1664 int cmd = (EE_EXTEND_CMD << addr_len) | (extend_cmd << (addr_len - 2));
1666 eeprom_cmd_start(ee_addr);
1667 eeprom_cmd(ee_addr, cmd, 3 + addr_len);
1668 eeprom_cmd_end(ee_addr);
1671 static u16 read_eeprom (void __iomem *ioaddr, int location, int addr_len)
1675 void __iomem *ee_addr = ioaddr + Cfg9346;
1676 int read_cmd = location | (EE_READ_CMD << addr_len);
1678 eeprom_cmd_start(ee_addr);
1679 eeprom_cmd(ee_addr, read_cmd, 3 + addr_len);
1681 for (i = 16; i > 0; i--) {
1682 writeb (EE_ENB | EE_SHIFT_CLK, ee_addr);
1685 (retval << 1) | ((readb (ee_addr) & EE_DATA_READ) ? 1 :
1687 writeb (EE_ENB, ee_addr);
1691 eeprom_cmd_end(ee_addr);
1696 static void write_eeprom(void __iomem *ioaddr, int location, u16 val,
1700 void __iomem *ee_addr = ioaddr + Cfg9346;
1701 int write_cmd = location | (EE_WRITE_CMD << addr_len);
1703 eeprom_extend_cmd(ee_addr, EE_EWEN_ADDR, addr_len);
1705 eeprom_cmd_start(ee_addr);
1706 eeprom_cmd(ee_addr, write_cmd, 3 + addr_len);
1707 eeprom_cmd(ee_addr, val, 16);
1708 eeprom_cmd_end(ee_addr);
1710 eeprom_cmd_start(ee_addr);
1711 for (i = 0; i < 20000; i++)
1712 if (readb(ee_addr) & EE_DATA_READ)
1714 eeprom_cmd_end(ee_addr);
1716 eeprom_extend_cmd(ee_addr, EE_EWDS_ADDR, addr_len);
1719 static int cp_get_eeprom_len(struct net_device *dev)
1721 struct cp_private *cp = netdev_priv(dev);
1724 spin_lock_irq(&cp->lock);
1725 size = read_eeprom(cp->regs, 0, 8) == 0x8129 ? 256 : 128;
1726 spin_unlock_irq(&cp->lock);
1731 static int cp_get_eeprom(struct net_device *dev,
1732 struct ethtool_eeprom *eeprom, u8 *data)
1734 struct cp_private *cp = netdev_priv(dev);
1735 unsigned int addr_len;
1737 u32 offset = eeprom->offset >> 1;
1738 u32 len = eeprom->len;
1741 eeprom->magic = CP_EEPROM_MAGIC;
1743 spin_lock_irq(&cp->lock);
1745 addr_len = read_eeprom(cp->regs, 0, 8) == 0x8129 ? 8 : 6;
1747 if (eeprom->offset & 1) {
1748 val = read_eeprom(cp->regs, offset, addr_len);
1749 data[i++] = (u8)(val >> 8);
1753 while (i < len - 1) {
1754 val = read_eeprom(cp->regs, offset, addr_len);
1755 data[i++] = (u8)val;
1756 data[i++] = (u8)(val >> 8);
1761 val = read_eeprom(cp->regs, offset, addr_len);
1765 spin_unlock_irq(&cp->lock);
1769 static int cp_set_eeprom(struct net_device *dev,
1770 struct ethtool_eeprom *eeprom, u8 *data)
1772 struct cp_private *cp = netdev_priv(dev);
1773 unsigned int addr_len;
1775 u32 offset = eeprom->offset >> 1;
1776 u32 len = eeprom->len;
1779 if (eeprom->magic != CP_EEPROM_MAGIC)
1782 spin_lock_irq(&cp->lock);
1784 addr_len = read_eeprom(cp->regs, 0, 8) == 0x8129 ? 8 : 6;
1786 if (eeprom->offset & 1) {
1787 val = read_eeprom(cp->regs, offset, addr_len) & 0xff;
1788 val |= (u16)data[i++] << 8;
1789 write_eeprom(cp->regs, offset, val, addr_len);
1793 while (i < len - 1) {
1794 val = (u16)data[i++];
1795 val |= (u16)data[i++] << 8;
1796 write_eeprom(cp->regs, offset, val, addr_len);
1801 val = read_eeprom(cp->regs, offset, addr_len) & 0xff00;
1802 val |= (u16)data[i];
1803 write_eeprom(cp->regs, offset, val, addr_len);
1806 spin_unlock_irq(&cp->lock);
1810 /* Put the board into D3cold state and wait for WakeUp signal */
1811 static void cp_set_d3_state (struct cp_private *cp)
1813 pci_enable_wake (cp->pdev, 0, 1); /* Enable PME# generation */
1814 pci_set_power_state (cp->pdev, PCI_D3hot);
1817 static int cp_init_one (struct pci_dev *pdev, const struct pci_device_id *ent)
1819 struct net_device *dev;
1820 struct cp_private *cp;
1823 resource_size_t pciaddr;
1824 unsigned int addr_len, i, pci_using_dac;
1828 static int version_printed;
1829 if (version_printed++ == 0)
1830 printk("%s", version);
1833 pci_read_config_byte(pdev, PCI_REVISION_ID, &pci_rev);
1835 if (pdev->vendor == PCI_VENDOR_ID_REALTEK &&
1836 pdev->device == PCI_DEVICE_ID_REALTEK_8139 && pci_rev < 0x20) {
1838 "This (id %04x:%04x rev %02x) is not an 8139C+ compatible chip\n",
1839 pdev->vendor, pdev->device, pci_rev);
1840 dev_err(&pdev->dev, "Try the \"8139too\" driver instead.\n");
1844 dev = alloc_etherdev(sizeof(struct cp_private));
1847 SET_MODULE_OWNER(dev);
1848 SET_NETDEV_DEV(dev, &pdev->dev);
1850 cp = netdev_priv(dev);
1853 cp->msg_enable = (debug < 0 ? CP_DEF_MSG_ENABLE : debug);
1854 spin_lock_init (&cp->lock);
1855 cp->mii_if.dev = dev;
1856 cp->mii_if.mdio_read = mdio_read;
1857 cp->mii_if.mdio_write = mdio_write;
1858 cp->mii_if.phy_id = CP_INTERNAL_PHY;
1859 cp->mii_if.phy_id_mask = 0x1f;
1860 cp->mii_if.reg_num_mask = 0x1f;
1861 cp_set_rxbufsize(cp);
1863 rc = pci_enable_device(pdev);
1867 rc = pci_set_mwi(pdev);
1869 goto err_out_disable;
1871 rc = pci_request_regions(pdev, DRV_NAME);
1875 pciaddr = pci_resource_start(pdev, 1);
1878 dev_err(&pdev->dev, "no MMIO resource\n");
1881 if (pci_resource_len(pdev, 1) < CP_REGS_SIZE) {
1883 dev_err(&pdev->dev, "MMIO resource (%llx) too small\n",
1884 (unsigned long long)pci_resource_len(pdev, 1));
1888 /* Configure DMA attributes. */
1889 if ((sizeof(dma_addr_t) > 4) &&
1890 !pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK) &&
1891 !pci_set_dma_mask(pdev, DMA_64BIT_MASK)) {
1896 rc = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
1899 "No usable DMA configuration, aborting.\n");
1902 rc = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
1905 "No usable consistent DMA configuration, "
1911 cp->cpcmd = (pci_using_dac ? PCIDAC : 0) |
1912 PCIMulRW | RxChkSum | CpRxOn | CpTxOn;
1914 regs = ioremap(pciaddr, CP_REGS_SIZE);
1917 dev_err(&pdev->dev, "Cannot map PCI MMIO (%Lx@%Lx)\n",
1918 (unsigned long long)pci_resource_len(pdev, 1),
1919 (unsigned long long)pciaddr);
1922 dev->base_addr = (unsigned long) regs;
1927 /* read MAC address from EEPROM */
1928 addr_len = read_eeprom (regs, 0, 8) == 0x8129 ? 8 : 6;
1929 for (i = 0; i < 3; i++)
1930 ((u16 *) (dev->dev_addr))[i] =
1931 le16_to_cpu (read_eeprom (regs, i + 7, addr_len));
1932 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
1934 dev->open = cp_open;
1935 dev->stop = cp_close;
1936 dev->set_multicast_list = cp_set_rx_mode;
1937 dev->hard_start_xmit = cp_start_xmit;
1938 dev->get_stats = cp_get_stats;
1939 dev->do_ioctl = cp_ioctl;
1940 dev->poll = cp_rx_poll;
1941 #ifdef CONFIG_NET_POLL_CONTROLLER
1942 dev->poll_controller = cp_poll_controller;
1944 dev->weight = 16; /* arbitrary? from NAPI_HOWTO.txt. */
1946 dev->change_mtu = cp_change_mtu;
1948 dev->ethtool_ops = &cp_ethtool_ops;
1950 dev->tx_timeout = cp_tx_timeout;
1951 dev->watchdog_timeo = TX_TIMEOUT;
1954 #if CP_VLAN_TAG_USED
1955 dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
1956 dev->vlan_rx_register = cp_vlan_rx_register;
1957 dev->vlan_rx_kill_vid = cp_vlan_rx_kill_vid;
1961 dev->features |= NETIF_F_HIGHDMA;
1963 #if 0 /* disabled by default until verified */
1964 dev->features |= NETIF_F_TSO;
1967 dev->irq = pdev->irq;
1969 rc = register_netdev(dev);
1973 printk (KERN_INFO "%s: RTL-8139C+ at 0x%lx, "
1974 "%02x:%02x:%02x:%02x:%02x:%02x, "
1978 dev->dev_addr[0], dev->dev_addr[1],
1979 dev->dev_addr[2], dev->dev_addr[3],
1980 dev->dev_addr[4], dev->dev_addr[5],
1983 pci_set_drvdata(pdev, dev);
1985 /* enable busmastering and memory-write-invalidate */
1986 pci_set_master(pdev);
1988 if (cp->wol_enabled)
1989 cp_set_d3_state (cp);
1996 pci_release_regions(pdev);
1998 pci_clear_mwi(pdev);
2000 pci_disable_device(pdev);
2006 static void cp_remove_one (struct pci_dev *pdev)
2008 struct net_device *dev = pci_get_drvdata(pdev);
2009 struct cp_private *cp = netdev_priv(dev);
2012 unregister_netdev(dev);
2014 if (cp->wol_enabled)
2015 pci_set_power_state (pdev, PCI_D0);
2016 pci_release_regions(pdev);
2017 pci_clear_mwi(pdev);
2018 pci_disable_device(pdev);
2019 pci_set_drvdata(pdev, NULL);
2024 static int cp_suspend (struct pci_dev *pdev, pm_message_t state)
2026 struct net_device *dev;
2027 struct cp_private *cp;
2028 unsigned long flags;
2030 dev = pci_get_drvdata (pdev);
2031 cp = netdev_priv(dev);
2033 if (!dev || !netif_running (dev)) return 0;
2035 netif_device_detach (dev);
2036 netif_stop_queue (dev);
2038 spin_lock_irqsave (&cp->lock, flags);
2040 /* Disable Rx and Tx */
2041 cpw16 (IntrMask, 0);
2042 cpw8 (Cmd, cpr8 (Cmd) & (~RxOn | ~TxOn));
2044 spin_unlock_irqrestore (&cp->lock, flags);
2046 pci_save_state(pdev);
2047 pci_enable_wake(pdev, pci_choose_state(pdev, state), cp->wol_enabled);
2048 pci_set_power_state(pdev, pci_choose_state(pdev, state));
2053 static int cp_resume (struct pci_dev *pdev)
2055 struct net_device *dev = pci_get_drvdata (pdev);
2056 struct cp_private *cp = netdev_priv(dev);
2057 unsigned long flags;
2059 if (!netif_running(dev))
2062 netif_device_attach (dev);
2064 pci_set_power_state(pdev, PCI_D0);
2065 pci_restore_state(pdev);
2066 pci_enable_wake(pdev, PCI_D0, 0);
2068 /* FIXME: sh*t may happen if the Rx ring buffer is depleted */
2069 cp_init_rings_index (cp);
2071 netif_start_queue (dev);
2073 spin_lock_irqsave (&cp->lock, flags);
2075 mii_check_media(&cp->mii_if, netif_msg_link(cp), FALSE);
2077 spin_unlock_irqrestore (&cp->lock, flags);
2081 #endif /* CONFIG_PM */
2083 static struct pci_driver cp_driver = {
2085 .id_table = cp_pci_tbl,
2086 .probe = cp_init_one,
2087 .remove = cp_remove_one,
2089 .resume = cp_resume,
2090 .suspend = cp_suspend,
2094 static int __init cp_init (void)
2097 printk("%s", version);
2099 return pci_module_init (&cp_driver);
2102 static void __exit cp_exit (void)
2104 pci_unregister_driver (&cp_driver);
2107 module_init(cp_init);
2108 module_exit(cp_exit);