2 * drivers/mtd/nand/rtc_from4.c
4 * Copyright (C) 2004 Red Hat, Inc.
6 * Derived from drivers/mtd/nand/spia.c
7 * Copyright (C) 2000 Steven J. Hill (sjhill@realitydiluted.com)
9 * $Id: rtc_from4.c,v 1.8 2005/01/17 19:44:36 dmarlin Exp $
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License version 2 as
13 * published by the Free Software Foundation.
16 * This is a device driver for the AG-AND flash device found on the
17 * Renesas Technology Corp. Flash ROM 4-slot interface board (FROM_BOARD4),
18 * which utilizes the Renesas HN29V1G91T-30 part.
19 * This chip is a 1 GBibit (128MiB x 8 bits) AG-AND flash device.
22 #include <linux/delay.h>
23 #include <linux/kernel.h>
24 #include <linux/init.h>
25 #include <linux/slab.h>
26 #include <linux/rslib.h>
27 #include <linux/module.h>
28 #include <linux/mtd/compatmac.h>
29 #include <linux/mtd/mtd.h>
30 #include <linux/mtd/nand.h>
31 #include <linux/mtd/partitions.h>
35 * MTD structure for Renesas board
37 static struct mtd_info *rtc_from4_mtd = NULL;
39 #define RTC_FROM4_MAX_CHIPS 2
41 /* HS77x9 processor register defines */
42 #define SH77X9_BCR1 ((volatile unsigned short *)(0xFFFFFF60))
43 #define SH77X9_BCR2 ((volatile unsigned short *)(0xFFFFFF62))
44 #define SH77X9_WCR1 ((volatile unsigned short *)(0xFFFFFF64))
45 #define SH77X9_WCR2 ((volatile unsigned short *)(0xFFFFFF66))
46 #define SH77X9_MCR ((volatile unsigned short *)(0xFFFFFF68))
47 #define SH77X9_PCR ((volatile unsigned short *)(0xFFFFFF6C))
48 #define SH77X9_FRQCR ((volatile unsigned short *)(0xFFFFFF80))
51 * Values specific to the Renesas Technology Corp. FROM_BOARD4 (used with HS77x9 processor)
53 /* Address where flash is mapped */
54 #define RTC_FROM4_FIO_BASE 0x14000000
56 /* CLE and ALE are tied to address lines 5 & 4, respectively */
57 #define RTC_FROM4_CLE (1 << 5)
58 #define RTC_FROM4_ALE (1 << 4)
60 /* address lines A24-A22 used for chip selection */
61 #define RTC_FROM4_NAND_ADDR_SLOT3 (0x00800000)
62 #define RTC_FROM4_NAND_ADDR_SLOT4 (0x00C00000)
63 #define RTC_FROM4_NAND_ADDR_FPGA (0x01000000)
64 /* mask address lines A24-A22 used for chip selection */
65 #define RTC_FROM4_NAND_ADDR_MASK (RTC_FROM4_NAND_ADDR_SLOT3 | RTC_FROM4_NAND_ADDR_SLOT4 | RTC_FROM4_NAND_ADDR_FPGA)
67 /* FPGA status register for checking device ready (bit zero) */
68 #define RTC_FROM4_FPGA_SR (RTC_FROM4_NAND_ADDR_FPGA | 0x00000002)
69 #define RTC_FROM4_DEVICE_READY 0x0001
71 /* FPGA Reed-Solomon ECC Control register */
73 #define RTC_FROM4_RS_ECC_CTL (RTC_FROM4_NAND_ADDR_FPGA | 0x00000050)
74 #define RTC_FROM4_RS_ECC_CTL_CLR (1 << 7)
75 #define RTC_FROM4_RS_ECC_CTL_GEN (1 << 6)
76 #define RTC_FROM4_RS_ECC_CTL_FD_E (1 << 5)
78 /* FPGA Reed-Solomon ECC code base */
79 #define RTC_FROM4_RS_ECC (RTC_FROM4_NAND_ADDR_FPGA | 0x00000060)
80 #define RTC_FROM4_RS_ECCN (RTC_FROM4_NAND_ADDR_FPGA | 0x00000080)
82 /* FPGA Reed-Solomon ECC check register */
83 #define RTC_FROM4_RS_ECC_CHK (RTC_FROM4_NAND_ADDR_FPGA | 0x00000070)
84 #define RTC_FROM4_RS_ECC_CHK_ERROR (1 << 7)
86 /* Undefine for software ECC */
87 #define RTC_FROM4_HWECC 1
92 static void __iomem *rtc_from4_fio_base = (void *)P2SEGADDR(RTC_FROM4_FIO_BASE);
94 const static struct mtd_partition partition_info[] = {
96 .name = "Renesas flash partition 1",
98 .size = MTDPART_SIZ_FULL
101 #define NUM_PARTITIONS 1
104 * hardware specific flash bbt decriptors
105 * Note: this is to allow debugging by disabling
106 * NAND_BBT_CREATE and/or NAND_BBT_WRITE
109 static uint8_t bbt_pattern[] = {'B', 'b', 't', '0' };
110 static uint8_t mirror_pattern[] = {'1', 't', 'b', 'B' };
112 static struct nand_bbt_descr rtc_from4_bbt_main_descr = {
113 .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE
114 | NAND_BBT_2BIT | NAND_BBT_VERSION | NAND_BBT_PERCHIP,
119 .pattern = bbt_pattern
122 static struct nand_bbt_descr rtc_from4_bbt_mirror_descr = {
123 .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE
124 | NAND_BBT_2BIT | NAND_BBT_VERSION | NAND_BBT_PERCHIP,
129 .pattern = mirror_pattern
134 #ifdef RTC_FROM4_HWECC
136 /* the Reed Solomon control structure */
137 static struct rs_control *rs_decoder;
140 * hardware specific Out Of Band information
142 static struct nand_oobinfo rtc_from4_nand_oobinfo = {
143 .useecc = MTD_NANDECC_AUTOPLACE,
146 0, 1, 2, 3, 4, 5, 6, 7,
147 8, 9, 10, 11, 12, 13, 14, 15,
148 16, 17, 18, 19, 20, 21, 22, 23,
149 24, 25, 26, 27, 28, 29, 30, 31},
150 .oobfree = { {32, 32} }
153 /* Aargh. I missed the reversed bit order, when I
154 * was talking to Renesas about the FPGA.
156 * The table is used for bit reordering and inversion
157 * of the ecc byte which we get from the FPGA
159 static uint8_t revbits[256] = {
160 0x00, 0x80, 0x40, 0xc0, 0x20, 0xa0, 0x60, 0xe0,
161 0x10, 0x90, 0x50, 0xd0, 0x30, 0xb0, 0x70, 0xf0,
162 0x08, 0x88, 0x48, 0xc8, 0x28, 0xa8, 0x68, 0xe8,
163 0x18, 0x98, 0x58, 0xd8, 0x38, 0xb8, 0x78, 0xf8,
164 0x04, 0x84, 0x44, 0xc4, 0x24, 0xa4, 0x64, 0xe4,
165 0x14, 0x94, 0x54, 0xd4, 0x34, 0xb4, 0x74, 0xf4,
166 0x0c, 0x8c, 0x4c, 0xcc, 0x2c, 0xac, 0x6c, 0xec,
167 0x1c, 0x9c, 0x5c, 0xdc, 0x3c, 0xbc, 0x7c, 0xfc,
168 0x02, 0x82, 0x42, 0xc2, 0x22, 0xa2, 0x62, 0xe2,
169 0x12, 0x92, 0x52, 0xd2, 0x32, 0xb2, 0x72, 0xf2,
170 0x0a, 0x8a, 0x4a, 0xca, 0x2a, 0xaa, 0x6a, 0xea,
171 0x1a, 0x9a, 0x5a, 0xda, 0x3a, 0xba, 0x7a, 0xfa,
172 0x06, 0x86, 0x46, 0xc6, 0x26, 0xa6, 0x66, 0xe6,
173 0x16, 0x96, 0x56, 0xd6, 0x36, 0xb6, 0x76, 0xf6,
174 0x0e, 0x8e, 0x4e, 0xce, 0x2e, 0xae, 0x6e, 0xee,
175 0x1e, 0x9e, 0x5e, 0xde, 0x3e, 0xbe, 0x7e, 0xfe,
176 0x01, 0x81, 0x41, 0xc1, 0x21, 0xa1, 0x61, 0xe1,
177 0x11, 0x91, 0x51, 0xd1, 0x31, 0xb1, 0x71, 0xf1,
178 0x09, 0x89, 0x49, 0xc9, 0x29, 0xa9, 0x69, 0xe9,
179 0x19, 0x99, 0x59, 0xd9, 0x39, 0xb9, 0x79, 0xf9,
180 0x05, 0x85, 0x45, 0xc5, 0x25, 0xa5, 0x65, 0xe5,
181 0x15, 0x95, 0x55, 0xd5, 0x35, 0xb5, 0x75, 0xf5,
182 0x0d, 0x8d, 0x4d, 0xcd, 0x2d, 0xad, 0x6d, 0xed,
183 0x1d, 0x9d, 0x5d, 0xdd, 0x3d, 0xbd, 0x7d, 0xfd,
184 0x03, 0x83, 0x43, 0xc3, 0x23, 0xa3, 0x63, 0xe3,
185 0x13, 0x93, 0x53, 0xd3, 0x33, 0xb3, 0x73, 0xf3,
186 0x0b, 0x8b, 0x4b, 0xcb, 0x2b, 0xab, 0x6b, 0xeb,
187 0x1b, 0x9b, 0x5b, 0xdb, 0x3b, 0xbb, 0x7b, 0xfb,
188 0x07, 0x87, 0x47, 0xc7, 0x27, 0xa7, 0x67, 0xe7,
189 0x17, 0x97, 0x57, 0xd7, 0x37, 0xb7, 0x77, 0xf7,
190 0x0f, 0x8f, 0x4f, 0xcf, 0x2f, 0xaf, 0x6f, 0xef,
191 0x1f, 0x9f, 0x5f, 0xdf, 0x3f, 0xbf, 0x7f, 0xff,
199 * rtc_from4_hwcontrol - hardware specific access to control-lines
200 * @mtd: MTD device structure
201 * @cmd: hardware control command
203 * Address lines (A5 and A4) are used to control Command and Address Latch
204 * Enable on this board, so set the read/write address appropriately.
206 * Chip Enable is also controlled by the Chip Select (CS5) and
207 * Address lines (A24-A22), so no action is required here.
210 static void rtc_from4_hwcontrol(struct mtd_info *mtd, int cmd)
212 struct nand_chip* this = (struct nand_chip *) (mtd->priv);
216 case NAND_CTL_SETCLE:
217 this->IO_ADDR_W = (void __iomem *)((unsigned long)this->IO_ADDR_W | RTC_FROM4_CLE);
219 case NAND_CTL_CLRCLE:
220 this->IO_ADDR_W = (void __iomem *)((unsigned long)this->IO_ADDR_W & ~RTC_FROM4_CLE);
223 case NAND_CTL_SETALE:
224 this->IO_ADDR_W = (void __iomem *)((unsigned long)this->IO_ADDR_W | RTC_FROM4_ALE);
226 case NAND_CTL_CLRALE:
227 this->IO_ADDR_W = (void __iomem *)((unsigned long)this->IO_ADDR_W & ~RTC_FROM4_ALE);
230 case NAND_CTL_SETNCE:
232 case NAND_CTL_CLRNCE:
240 * rtc_from4_nand_select_chip - hardware specific chip select
241 * @mtd: MTD device structure
242 * @chip: Chip to select (0 == slot 3, 1 == slot 4)
244 * The chip select is based on address lines A24-A22.
245 * This driver uses flash slots 3 and 4 (A23-A22).
248 static void rtc_from4_nand_select_chip(struct mtd_info *mtd, int chip)
250 struct nand_chip *this = mtd->priv;
252 this->IO_ADDR_R = (void __iomem *)((unsigned long)this->IO_ADDR_R & ~RTC_FROM4_NAND_ADDR_MASK);
253 this->IO_ADDR_W = (void __iomem *)((unsigned long)this->IO_ADDR_W & ~RTC_FROM4_NAND_ADDR_MASK);
257 case 0: /* select slot 3 chip */
258 this->IO_ADDR_R = (void __iomem *)((unsigned long)this->IO_ADDR_R | RTC_FROM4_NAND_ADDR_SLOT3);
259 this->IO_ADDR_W = (void __iomem *)((unsigned long)this->IO_ADDR_W | RTC_FROM4_NAND_ADDR_SLOT3);
261 case 1: /* select slot 4 chip */
262 this->IO_ADDR_R = (void __iomem *)((unsigned long)this->IO_ADDR_R | RTC_FROM4_NAND_ADDR_SLOT4);
263 this->IO_ADDR_W = (void __iomem *)((unsigned long)this->IO_ADDR_W | RTC_FROM4_NAND_ADDR_SLOT4);
272 * rtc_from4_nand_device_ready - hardware specific ready/busy check
273 * @mtd: MTD device structure
275 * This board provides the Ready/Busy state in the status register
276 * of the FPGA. Bit zero indicates the RDY(1)/BSY(0) signal.
279 static int rtc_from4_nand_device_ready(struct mtd_info *mtd)
281 unsigned short status;
283 status = *((volatile unsigned short *)(rtc_from4_fio_base + RTC_FROM4_FPGA_SR));
285 return (status & RTC_FROM4_DEVICE_READY);
291 * deplete - code to perform device recovery in case there was a power loss
292 * @mtd: MTD device structure
293 * @chip: Chip to select (0 == slot 3, 1 == slot 4)
295 * If there was a sudden loss of power during an erase operation, a
296 * "device recovery" operation must be performed when power is restored
297 * to ensure correct operation. This routine performs the required steps
298 * for the requested chip.
300 * See page 86 of the data sheet for details.
303 static void deplete(struct mtd_info *mtd, int chip)
305 struct nand_chip *this = mtd->priv;
307 /* wait until device is ready */
308 while (!this->dev_ready(mtd));
310 this->select_chip(mtd, chip);
312 /* Send the commands for device recovery, phase 1 */
313 this->cmdfunc (mtd, NAND_CMD_DEPLETE1, 0x0000, 0x0000);
314 this->cmdfunc (mtd, NAND_CMD_DEPLETE2, -1, -1);
316 /* Send the commands for device recovery, phase 2 */
317 this->cmdfunc (mtd, NAND_CMD_DEPLETE1, 0x0000, 0x0004);
318 this->cmdfunc (mtd, NAND_CMD_DEPLETE2, -1, -1);
323 #ifdef RTC_FROM4_HWECC
325 * rtc_from4_enable_hwecc - hardware specific hardware ECC enable function
326 * @mtd: MTD device structure
327 * @mode: I/O mode; read or write
329 * enable hardware ECC for data read or write
332 static void rtc_from4_enable_hwecc(struct mtd_info *mtd, int mode)
334 volatile unsigned short * rs_ecc_ctl = (volatile unsigned short *)(rtc_from4_fio_base + RTC_FROM4_RS_ECC_CTL);
335 unsigned short status;
339 status = RTC_FROM4_RS_ECC_CTL_CLR
340 | RTC_FROM4_RS_ECC_CTL_FD_E;
342 *rs_ecc_ctl = status;
345 case NAND_ECC_READSYN :
348 *rs_ecc_ctl = status;
351 case NAND_ECC_WRITE :
352 status = RTC_FROM4_RS_ECC_CTL_CLR
353 | RTC_FROM4_RS_ECC_CTL_GEN
354 | RTC_FROM4_RS_ECC_CTL_FD_E;
356 *rs_ecc_ctl = status;
367 * rtc_from4_calculate_ecc - hardware specific code to read ECC code
368 * @mtd: MTD device structure
369 * @dat: buffer containing the data to generate ECC codes
370 * @ecc_code ECC codes calculated
372 * The ECC code is calculated by the FPGA. All we have to do is read the values
373 * from the FPGA registers.
375 * Note: We read from the inverted registers, since data is inverted before
376 * the code is calculated. So all 0xff data (blank page) results in all 0xff rs code
379 static void rtc_from4_calculate_ecc(struct mtd_info *mtd, const u_char *dat, u_char *ecc_code)
381 volatile unsigned short * rs_eccn = (volatile unsigned short *)(rtc_from4_fio_base + RTC_FROM4_RS_ECCN);
382 unsigned short value;
385 for (i = 0; i < 8; i++) {
387 ecc_code[i] = (unsigned char)value;
390 ecc_code[7] |= 0x0f; /* set the last four bits (not used) */
394 * rtc_from4_correct_data - hardware specific code to correct data using ECC code
395 * @mtd: MTD device structure
396 * @buf: buffer containing the data to generate ECC codes
397 * @ecc1 ECC codes read
398 * @ecc2 ECC codes calculated
400 * The FPGA tells us fast, if there's an error or not. If no, we go back happy
401 * else we read the ecc results from the fpga and call the rs library to decode
402 * and hopefully correct the error
404 * For now I use the code, which we read from the FLASH to use the RS lib,
405 * as the syndrom conversion has a unresolved issue.
407 static int rtc_from4_correct_data(struct mtd_info *mtd, const u_char *buf, u_char *ecc1, u_char *ecc2)
410 unsigned short status;
411 uint16_t par[6], syn[6];
413 volatile unsigned short *rs_ecc;
415 status = *((volatile unsigned short *)(rtc_from4_fio_base + RTC_FROM4_RS_ECC_CHK));
417 if (!(status & RTC_FROM4_RS_ECC_CHK_ERROR)) {
421 /* Read the syndrom pattern from the FPGA and correct the bitorder */
422 rs_ecc = (volatile unsigned short *)(rtc_from4_fio_base + RTC_FROM4_RS_ECC);
423 for (i = 0; i < 8; i++) {
424 ecc[i] = revbits[(*rs_ecc) & 0xFF];
428 /* convert into 6 10bit syndrome fields */
429 par[5] = rs_decoder->index_of[(((uint16_t)ecc[0] >> 0) & 0x0ff) |
430 (((uint16_t)ecc[1] << 8) & 0x300)];
431 par[4] = rs_decoder->index_of[(((uint16_t)ecc[1] >> 2) & 0x03f) |
432 (((uint16_t)ecc[2] << 6) & 0x3c0)];
433 par[3] = rs_decoder->index_of[(((uint16_t)ecc[2] >> 4) & 0x00f) |
434 (((uint16_t)ecc[3] << 4) & 0x3f0)];
435 par[2] = rs_decoder->index_of[(((uint16_t)ecc[3] >> 6) & 0x003) |
436 (((uint16_t)ecc[4] << 2) & 0x3fc)];
437 par[1] = rs_decoder->index_of[(((uint16_t)ecc[5] >> 0) & 0x0ff) |
438 (((uint16_t)ecc[6] << 8) & 0x300)];
439 par[0] = (((uint16_t)ecc[6] >> 2) & 0x03f) | (((uint16_t)ecc[7] << 6) & 0x3c0);
441 /* Convert to computable syndrome */
442 for (i = 0; i < 6; i++) {
444 for (j = 1; j < 6; j++)
445 if (par[j] != rs_decoder->nn)
446 syn[i] ^= rs_decoder->alpha_to[rs_modnn(rs_decoder, par[j] + i * j)];
448 /* Convert to index form */
449 syn[i] = rs_decoder->index_of[syn[i]];
452 /* Let the library code do its magic.*/
453 res = decode_rs8(rs_decoder, (uint8_t *)buf, par, 512, syn, 0, NULL, 0xff, NULL);
455 DEBUG (MTD_DEBUG_LEVEL0, "rtc_from4_correct_data: "
456 "ECC corrected %d errors on read\n", res);
463 * Main initialization routine
465 int __init rtc_from4_init (void)
467 struct nand_chip *this;
468 unsigned short bcr1, bcr2, wcr2;
471 /* Allocate memory for MTD device structure and private data */
472 rtc_from4_mtd = kmalloc(sizeof(struct mtd_info) + sizeof (struct nand_chip),
474 if (!rtc_from4_mtd) {
475 printk ("Unable to allocate Renesas NAND MTD device structure.\n");
479 /* Get pointer to private data */
480 this = (struct nand_chip *) (&rtc_from4_mtd[1]);
482 /* Initialize structures */
483 memset((char *) rtc_from4_mtd, 0, sizeof(struct mtd_info));
484 memset((char *) this, 0, sizeof(struct nand_chip));
486 /* Link the private data with the MTD structure */
487 rtc_from4_mtd->priv = this;
489 /* set area 5 as PCMCIA mode to clear the spec of tDH(Data hold time;9ns min) */
490 bcr1 = *SH77X9_BCR1 & ~0x0002;
495 bcr2 = *SH77X9_BCR2 & ~0x0c00;
499 /* set area 5 wait states */
500 wcr2 = *SH77X9_WCR2 & ~0x1c00;
504 /* Set address of NAND IO lines */
505 this->IO_ADDR_R = rtc_from4_fio_base;
506 this->IO_ADDR_W = rtc_from4_fio_base;
507 /* Set address of hardware control function */
508 this->hwcontrol = rtc_from4_hwcontrol;
509 /* Set address of chip select function */
510 this->select_chip = rtc_from4_nand_select_chip;
511 /* command delay time (in us) */
512 this->chip_delay = 100;
513 /* return the status of the Ready/Busy line */
514 this->dev_ready = rtc_from4_nand_device_ready;
516 #ifdef RTC_FROM4_HWECC
517 printk(KERN_INFO "rtc_from4_init: using hardware ECC detection.\n");
519 this->eccmode = NAND_ECC_HW8_512;
520 this->options |= NAND_HWECC_SYNDROME;
521 /* set the nand_oobinfo to support FPGA H/W error detection */
522 this->autooob = &rtc_from4_nand_oobinfo;
523 this->enable_hwecc = rtc_from4_enable_hwecc;
524 this->calculate_ecc = rtc_from4_calculate_ecc;
525 this->correct_data = rtc_from4_correct_data;
527 printk(KERN_INFO "rtc_from4_init: using software ECC detection.\n");
529 this->eccmode = NAND_ECC_SOFT;
532 /* set the bad block tables to support debugging */
533 this->bbt_td = &rtc_from4_bbt_main_descr;
534 this->bbt_md = &rtc_from4_bbt_mirror_descr;
536 /* Scan to find existence of the device */
537 if (nand_scan(rtc_from4_mtd, RTC_FROM4_MAX_CHIPS)) {
538 kfree(rtc_from4_mtd);
542 /* Perform 'device recovery' for each chip in case there was a power loss. */
543 for (i=0; i < this->numchips; i++) {
544 deplete(rtc_from4_mtd, i);
547 /* Register the partitions */
548 add_mtd_partitions(rtc_from4_mtd, partition_info, NUM_PARTITIONS);
550 #ifdef RTC_FROM4_HWECC
551 /* We could create the decoder on demand, if memory is a concern.
552 * This way we have it handy, if an error happens
554 * Symbolsize is 10 (bits)
555 * Primitve polynomial is x^10+x^3+1
556 * first consecutive root is 0
557 * primitve element to generate roots = 1
558 * generator polinomial degree = 6
560 rs_decoder = init_rs(10, 0x409, 0, 1, 6);
562 printk (KERN_ERR "Could not create a RS decoder\n");
563 nand_release(rtc_from4_mtd);
564 kfree(rtc_from4_mtd);
571 module_init(rtc_from4_init);
578 static void __exit rtc_from4_cleanup (void)
580 /* Release resource, unregister partitions */
581 nand_release(rtc_from4_mtd);
583 /* Free the MTD device structure */
584 kfree (rtc_from4_mtd);
586 #ifdef RTC_FROM4_HWECC
587 /* Free the reed solomon resources */
593 module_exit(rtc_from4_cleanup);
596 MODULE_LICENSE("GPL");
597 MODULE_AUTHOR("d.marlin <dmarlin@redhat.com");
598 MODULE_DESCRIPTION("Board-specific glue layer for AG-AND flash on Renesas FROM_BOARD4");