err.no Git - linux-2.6/blob - drivers/mtd/nand/nand_base.c

   1 /*
   2  *  drivers/mtd/nand.c
   3  *
   4  *  Overview:
   5  *   This is the generic MTD driver for NAND flash devices. It should be
   6  *   capable of working with almost all NAND chips currently available.
   7  *   Basic support for AG-AND chips is provided.
   8  *
   9  *      Additional technical information is available on
  10  *      http://www.linux-mtd.infradead.org/tech/nand.html
  11  *
  12  *  Copyright (C) 2000 Steven J. Hill (sjhill@realitydiluted.com)
  13  *                2002-2006 Thomas Gleixner (tglx@linutronix.de)
  14  *
  15  *  Credits:
  16  *      David Woodhouse for adding multichip support
  17  *
  18  *      Aleph One Ltd. and Toby Churchill Ltd. for supporting the
  19  *      rework for 2K page size chips
  20  *
  21  *  TODO:
  22  *      Enable cached programming for 2k page size chips
  23  *      Check, if mtd->ecctype should be set to MTD_ECC_HW
  24  *      if we have HW ecc support.
  25  *      The AG-AND chips have nice features for speed improvement,
  26  *      which are not supported yet. Read / program 4 pages in one go.
  27  *
  28  * This program is free software; you can redistribute it and/or modify
  29  * it under the terms of the GNU General Public License version 2 as
  30  * published by the Free Software Foundation.
  31  *
  32  */
  33
  34 #include <linux/module.h>
  35 #include <linux/delay.h>
  36 #include <linux/errno.h>
  37 #include <linux/err.h>
  38 #include <linux/sched.h>
  39 #include <linux/slab.h>
  40 #include <linux/types.h>
  41 #include <linux/mtd/mtd.h>
  42 #include <linux/mtd/nand.h>
  43 #include <linux/mtd/nand_ecc.h>
  44 #include <linux/mtd/compatmac.h>
  45 #include <linux/interrupt.h>
  46 #include <linux/bitops.h>
  47 #include <linux/leds.h>
  48 #include <asm/io.h>
  49
  50 #ifdef CONFIG_MTD_PARTITIONS
  51 #include <linux/mtd/partitions.h>
  52 #endif
  53
  54 /* Define default oob placement schemes for large and small page devices */
  55 static struct nand_oobinfo nand_oob_8 = {
  56         .useecc = MTD_NANDECC_AUTOPLACE,
  57         .eccbytes = 3,
  58         .eccpos = {0, 1, 2},
  59         .oobfree = {{3, 2}, {6, 2}}
  60 };
  61
  62 static struct nand_oobinfo nand_oob_16 = {
  63         .useecc = MTD_NANDECC_AUTOPLACE,
  64         .eccbytes = 6,
  65         .eccpos = {0, 1, 2, 3, 6, 7},
  66         .oobfree = {{8, 8}}
  67 };
  68
  69 static struct nand_oobinfo nand_oob_64 = {
  70         .useecc = MTD_NANDECC_AUTOPLACE,
  71         .eccbytes = 24,
  72         .eccpos = {
  73                    40, 41, 42, 43, 44, 45, 46, 47,
  74                    48, 49, 50, 51, 52, 53, 54, 55,
  75                    56, 57, 58, 59, 60, 61, 62, 63},
  76         .oobfree = {{2, 38}}
  77 };
  78
  79 /* This is used for padding purposes in nand_write_oob */
  80 static uint8_t ffchars[] = {
  81         0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
  82         0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
  83         0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
  84         0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
  85         0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
  86         0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
  87         0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
  88         0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
  89 };
  90
  91 static int nand_write_oob(struct mtd_info *mtd, loff_t to, size_t len,
  92                           size_t *retlen, const uint8_t *buf);
  93 static int nand_get_device(struct nand_chip *chip, struct mtd_info *mtd,
  94                            int new_state);
  95
  96 /*
  97  * For devices which display every fart in the system on a seperate LED. Is
  98  * compiled away when LED support is disabled.
  99  */
 100 DEFINE_LED_TRIGGER(nand_led_trigger);
 101
 102 /**
 103  * nand_release_device - [GENERIC] release chip
 104  * @mtd:        MTD device structure
 105  *
 106  * Deselect, release chip lock and wake up anyone waiting on the device
 107  */
 108 static void nand_release_device(struct mtd_info *mtd)
 109 {
 110         struct nand_chip *chip = mtd->priv;
 111
 112         /* De-select the NAND device */
 113         chip->select_chip(mtd, -1);
 114
 115         /* Release the controller and the chip */
 116         spin_lock(&chip->controller->lock);
 117         chip->controller->active = NULL;
 118         chip->state = FL_READY;
 119         wake_up(&chip->controller->wq);
 120         spin_unlock(&chip->controller->lock);
 121 }
 122
 123 /**
 124  * nand_read_byte - [DEFAULT] read one byte from the chip
 125  * @mtd:        MTD device structure
 126  *
 127  * Default read function for 8bit buswith
 128  */
 129 static uint8_t nand_read_byte(struct mtd_info *mtd)
 130 {
 131         struct nand_chip *chip = mtd->priv;
 132         return readb(chip->IO_ADDR_R);
 133 }
 134
 135 /**
 136  * nand_read_byte16 - [DEFAULT] read one byte endianess aware from the chip
 137  * @mtd:        MTD device structure
 138  *
 139  * Default read function for 16bit buswith with
 140  * endianess conversion
 141  */
 142 static uint8_t nand_read_byte16(struct mtd_info *mtd)
 143 {
 144         struct nand_chip *chip = mtd->priv;
 145         return (uint8_t) cpu_to_le16(readw(chip->IO_ADDR_R));
 146 }
 147
 148 /**
 149  * nand_read_word - [DEFAULT] read one word from the chip
 150  * @mtd:        MTD device structure
 151  *
 152  * Default read function for 16bit buswith without
 153  * endianess conversion
 154  */
 155 static u16 nand_read_word(struct mtd_info *mtd)
 156 {
 157         struct nand_chip *chip = mtd->priv;
 158         return readw(chip->IO_ADDR_R);
 159 }
 160
 161 /**
 162  * nand_select_chip - [DEFAULT] control CE line
 163  * @mtd:        MTD device structure
 164  * @chip:       chipnumber to select, -1 for deselect
 165  *
 166  * Default select function for 1 chip devices.
 167  */
 168 static void nand_select_chip(struct mtd_info *mtd, int chipnr)
 169 {
 170         struct nand_chip *chip = mtd->priv;
 171
 172         switch (chipnr) {
 173         case -1:
 174                 chip->cmd_ctrl(mtd, NAND_CMD_NONE, 0 | NAND_CTRL_CHANGE);
 175                 break;
 176         case 0:
 177                 chip->cmd_ctrl(mtd, NAND_CMD_NONE,
 178                                NAND_NCE | NAND_CTRL_CHANGE);
 179                 break;
 180
 181         default:
 182                 BUG();
 183         }
 184 }
 185
 186 /**
 187  * nand_write_buf - [DEFAULT] write buffer to chip
 188  * @mtd:        MTD device structure
 189  * @buf:        data buffer
 190  * @len:        number of bytes to write
 191  *
 192  * Default write function for 8bit buswith
 193  */
 194 static void nand_write_buf(struct mtd_info *mtd, const uint8_t *buf, int len)
 195 {
 196         int i;
 197         struct nand_chip *chip = mtd->priv;
 198
 199         for (i = 0; i < len; i++)
 200                 writeb(buf[i], chip->IO_ADDR_W);
 201 }
 202
 203 /**
 204  * nand_read_buf - [DEFAULT] read chip data into buffer
 205  * @mtd:        MTD device structure
 206  * @buf:        buffer to store date
 207  * @len:        number of bytes to read
 208  *
 209  * Default read function for 8bit buswith
 210  */
 211 static void nand_read_buf(struct mtd_info *mtd, uint8_t *buf, int len)
 212 {
 213         int i;
 214         struct nand_chip *chip = mtd->priv;
 215
 216         for (i = 0; i < len; i++)
 217                 buf[i] = readb(chip->IO_ADDR_R);
 218 }
 219
 220 /**
 221  * nand_verify_buf - [DEFAULT] Verify chip data against buffer
 222  * @mtd:        MTD device structure
 223  * @buf:        buffer containing the data to compare
 224  * @len:        number of bytes to compare
 225  *
 226  * Default verify function for 8bit buswith
 227  */
 228 static int nand_verify_buf(struct mtd_info *mtd, const uint8_t *buf, int len)
 229 {
 230         int i;
 231         struct nand_chip *chip = mtd->priv;
 232
 233         for (i = 0; i < len; i++)
 234                 if (buf[i] != readb(chip->IO_ADDR_R))
 235                         return -EFAULT;
 236         return 0;
 237 }
 238
 239 /**
 240  * nand_write_buf16 - [DEFAULT] write buffer to chip
 241  * @mtd:        MTD device structure
 242  * @buf:        data buffer
 243  * @len:        number of bytes to write
 244  *
 245  * Default write function for 16bit buswith
 246  */
 247 static void nand_write_buf16(struct mtd_info *mtd, const uint8_t *buf, int len)
 248 {
 249         int i;
 250         struct nand_chip *chip = mtd->priv;
 251         u16 *p = (u16 *) buf;
 252         len >>= 1;
 253
 254         for (i = 0; i < len; i++)
 255                 writew(p[i], chip->IO_ADDR_W);
 256
 257 }
 258
 259 /**
 260  * nand_read_buf16 - [DEFAULT] read chip data into buffer
 261  * @mtd:        MTD device structure
 262  * @buf:        buffer to store date
 263  * @len:        number of bytes to read
 264  *
 265  * Default read function for 16bit buswith
 266  */
 267 static void nand_read_buf16(struct mtd_info *mtd, uint8_t *buf, int len)
 268 {
 269         int i;
 270         struct nand_chip *chip = mtd->priv;
 271         u16 *p = (u16 *) buf;
 272         len >>= 1;
 273
 274         for (i = 0; i < len; i++)
 275                 p[i] = readw(chip->IO_ADDR_R);
 276 }
 277
 278 /**
 279  * nand_verify_buf16 - [DEFAULT] Verify chip data against buffer
 280  * @mtd:        MTD device structure
 281  * @buf:        buffer containing the data to compare
 282  * @len:        number of bytes to compare
 283  *
 284  * Default verify function for 16bit buswith
 285  */
 286 static int nand_verify_buf16(struct mtd_info *mtd, const uint8_t *buf, int len)
 287 {
 288         int i;
 289         struct nand_chip *chip = mtd->priv;
 290         u16 *p = (u16 *) buf;
 291         len >>= 1;
 292
 293         for (i = 0; i < len; i++)
 294                 if (p[i] != readw(chip->IO_ADDR_R))
 295                         return -EFAULT;
 296
 297         return 0;
 298 }
 299
 300 /**
 301  * nand_block_bad - [DEFAULT] Read bad block marker from the chip
 302  * @mtd:        MTD device structure
 303  * @ofs:        offset from device start
 304  * @getchip:    0, if the chip is already selected
 305  *
 306  * Check, if the block is bad.
 307  */
 308 static int nand_block_bad(struct mtd_info *mtd, loff_t ofs, int getchip)
 309 {
 310         int page, chipnr, res = 0;
 311         struct nand_chip *chip = mtd->priv;
 312         u16 bad;
 313
 314         if (getchip) {
 315                 page = (int)(ofs >> chip->page_shift);
 316                 chipnr = (int)(ofs >> chip->chip_shift);
 317
 318                 nand_get_device(chip, mtd, FL_READING);
 319
 320                 /* Select the NAND device */
 321                 chip->select_chip(mtd, chipnr);
 322         } else
 323                 page = (int)ofs;
 324
 325         if (chip->options & NAND_BUSWIDTH_16) {
 326                 chip->cmdfunc(mtd, NAND_CMD_READOOB, chip->badblockpos & 0xFE,
 327                               page & chip->pagemask);
 328                 bad = cpu_to_le16(chip->read_word(mtd));
 329                 if (chip->badblockpos & 0x1)
 330                         bad >>= 8;
 331                 if ((bad & 0xFF) != 0xff)
 332                         res = 1;
 333         } else {
 334                 chip->cmdfunc(mtd, NAND_CMD_READOOB, chip->badblockpos,
 335                               page & chip->pagemask);
 336                 if (chip->read_byte(mtd) != 0xff)
 337                         res = 1;
 338         }
 339
 340         if (getchip)
 341                 nand_release_device(mtd);
 342
 343         return res;
 344 }
 345
 346 /**
 347  * nand_default_block_markbad - [DEFAULT] mark a block bad
 348  * @mtd:        MTD device structure
 349  * @ofs:        offset from device start
 350  *
 351  * This is the default implementation, which can be overridden by
 352  * a hardware specific driver.
 353 */
 354 static int nand_default_block_markbad(struct mtd_info *mtd, loff_t ofs)
 355 {
 356         struct nand_chip *chip = mtd->priv;
 357         uint8_t buf[2] = { 0, 0 };
 358         size_t retlen;
 359         int block;
 360
 361         /* Get block number */
 362         block = ((int)ofs) >> chip->bbt_erase_shift;
 363         if (chip->bbt)
 364                 chip->bbt[block >> 2] |= 0x01 << ((block & 0x03) << 1);
 365
 366         /* Do we have a flash based bad block table ? */
 367         if (chip->options & NAND_USE_FLASH_BBT)
 368                 return nand_update_bbt(mtd, ofs);
 369
 370         /* We write two bytes, so we dont have to mess with 16 bit access */
 371         ofs += mtd->oobsize + (chip->badblockpos & ~0x01);
 372         return nand_write_oob(mtd, ofs, 2, &retlen, buf);
 373 }
 374
 375 /**
 376  * nand_check_wp - [GENERIC] check if the chip is write protected
 377  * @mtd:        MTD device structure
 378  * Check, if the device is write protected
 379  *
 380  * The function expects, that the device is already selected
 381  */
 382 static int nand_check_wp(struct mtd_info *mtd)
 383 {
 384         struct nand_chip *chip = mtd->priv;
 385         /* Check the WP bit */
 386         chip->cmdfunc(mtd, NAND_CMD_STATUS, -1, -1);
 387         return (chip->read_byte(mtd) & NAND_STATUS_WP) ? 0 : 1;
 388 }
 389
 390 /**
 391  * nand_block_checkbad - [GENERIC] Check if a block is marked bad
 392  * @mtd:        MTD device structure
 393  * @ofs:        offset from device start
 394  * @getchip:    0, if the chip is already selected
 395  * @allowbbt:   1, if its allowed to access the bbt area
 396  *
 397  * Check, if the block is bad. Either by reading the bad block table or
 398  * calling of the scan function.
 399  */
 400 static int nand_block_checkbad(struct mtd_info *mtd, loff_t ofs, int getchip,
 401                                int allowbbt)
 402 {
 403         struct nand_chip *chip = mtd->priv;
 404
 405         if (!chip->bbt)
 406                 return chip->block_bad(mtd, ofs, getchip);
 407
 408         /* Return info from the table */
 409         return nand_isbad_bbt(mtd, ofs, allowbbt);
 410 }
 411
 412 /*
 413  * Wait for the ready pin, after a command
 414  * The timeout is catched later.
 415  */
 416 static void nand_wait_ready(struct mtd_info *mtd)
 417 {
 418         struct nand_chip *chip = mtd->priv;
 419         unsigned long timeo = jiffies + 2;
 420
 421         led_trigger_event(nand_led_trigger, LED_FULL);
 422         /* wait until command is processed or timeout occures */
 423         do {
 424                 if (chip->dev_ready(mtd))
 425                         break;
 426                 touch_softlockup_watchdog();
 427         } while (time_before(jiffies, timeo));
 428         led_trigger_event(nand_led_trigger, LED_OFF);
 429 }
 430
 431 /**
 432  * nand_command - [DEFAULT] Send command to NAND device
 433  * @mtd:        MTD device structure
 434  * @command:    the command to be sent
 435  * @column:     the column address for this command, -1 if none
 436  * @page_addr:  the page address for this command, -1 if none
 437  *
 438  * Send command to NAND device. This function is used for small page
 439  * devices (256/512 Bytes per page)
 440  */
 441 static void nand_command(struct mtd_info *mtd, unsigned int command,
 442                          int column, int page_addr)
 443 {
 444         register struct nand_chip *chip = mtd->priv;
 445         int ctrl = NAND_CTRL_CLE | NAND_CTRL_CHANGE;
 446
 447         /*
 448          * Write out the command to the device.
 449          */
 450         if (command == NAND_CMD_SEQIN) {
 451                 int readcmd;
 452
 453                 if (column >= mtd->writesize) {
 454                         /* OOB area */
 455                         column -= mtd->writesize;
 456                         readcmd = NAND_CMD_READOOB;
 457                 } else if (column < 256) {
 458                         /* First 256 bytes --> READ0 */
 459                         readcmd = NAND_CMD_READ0;
 460                 } else {
 461                         column -= 256;
 462                         readcmd = NAND_CMD_READ1;
 463                 }
 464                 chip->cmd_ctrl(mtd, readcmd, ctrl);
 465                 ctrl &= ~NAND_CTRL_CHANGE;
 466         }
 467         chip->cmd_ctrl(mtd, command, ctrl);
 468
 469         /*
 470          * Address cycle, when necessary
 471          */
 472         ctrl = NAND_CTRL_ALE | NAND_CTRL_CHANGE;
 473         /* Serially input address */
 474         if (column != -1) {
 475                 /* Adjust columns for 16 bit buswidth */
 476                 if (chip->options & NAND_BUSWIDTH_16)
 477                         column >>= 1;
 478                 chip->cmd_ctrl(mtd, column, ctrl);
 479                 ctrl &= ~NAND_CTRL_CHANGE;
 480         }
 481         if (page_addr != -1) {
 482                 chip->cmd_ctrl(mtd, page_addr, ctrl);
 483                 ctrl &= ~NAND_CTRL_CHANGE;
 484                 chip->cmd_ctrl(mtd, page_addr >> 8, ctrl);
 485                 /* One more address cycle for devices > 32MiB */
 486                 if (chip->chipsize > (32 << 20))
 487                         chip->cmd_ctrl(mtd, page_addr >> 16, ctrl);
 488         }
 489         chip->cmd_ctrl(mtd, NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
 490
 491         /*
 492          * program and erase have their own busy handlers
 493          * status and sequential in needs no delay
 494          */
 495         switch (command) {
 496
 497         case NAND_CMD_PAGEPROG:
 498         case NAND_CMD_ERASE1:
 499         case NAND_CMD_ERASE2:
 500         case NAND_CMD_SEQIN:
 501         case NAND_CMD_STATUS:
 502                 chip->cmd_ctrl(mtd, NAND_CMD_NONE, NAND_NCE);
 503                 return;
 504
 505         case NAND_CMD_RESET:
 506                 if (chip->dev_ready)
 507                         break;
 508                 udelay(chip->chip_delay);
 509                 chip->cmd_ctrl(mtd, NAND_CMD_STATUS,
 510                                NAND_CTRL_CLE | NAND_CTRL_CHANGE);
 511                 chip->cmd_ctrl(mtd,
 512                                NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
 513                 while (!(chip->read_byte(mtd) & NAND_STATUS_READY)) ;
 514                 return;
 515
 516                 /* This applies to read commands */
 517         default:
 518                 /*
 519                  * If we don't have access to the busy pin, we apply the given
 520                  * command delay
 521                  */
 522                 if (!chip->dev_ready) {
 523                         udelay(chip->chip_delay);
 524                         return;
 525                 }
 526         }
 527         /* Apply this short delay always to ensure that we do wait tWB in
 528          * any case on any machine. */
 529         ndelay(100);
 530
 531         nand_wait_ready(mtd);
 532 }
 533
 534 /**
 535  * nand_command_lp - [DEFAULT] Send command to NAND large page device
 536  * @mtd:        MTD device structure
 537  * @command:    the command to be sent
 538  * @column:     the column address for this command, -1 if none
 539  * @page_addr:  the page address for this command, -1 if none
 540  *
 541  * Send command to NAND device. This is the version for the new large page
 542  * devices We dont have the separate regions as we have in the small page
 543  * devices.  We must emulate NAND_CMD_READOOB to keep the code compatible.
 544  *
 545  */
 546 static void nand_command_lp(struct mtd_info *mtd, unsigned int command,
 547                             int column, int page_addr)
 548 {
 549         register struct nand_chip *chip = mtd->priv;
 550
 551         /* Emulate NAND_CMD_READOOB */
 552         if (command == NAND_CMD_READOOB) {
 553                 column += mtd->writesize;
 554                 command = NAND_CMD_READ0;
 555         }
 556
 557         /* Command latch cycle */
 558         chip->cmd_ctrl(mtd, command & 0xff,
 559                        NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE);
 560
 561         if (column != -1 || page_addr != -1) {
 562                 int ctrl = NAND_CTRL_CHANGE | NAND_NCE | NAND_ALE;
 563
 564                 /* Serially input address */
 565                 if (column != -1) {
 566                         /* Adjust columns for 16 bit buswidth */
 567                         if (chip->options & NAND_BUSWIDTH_16)
 568                                 column >>= 1;
 569                         chip->cmd_ctrl(mtd, column, ctrl);
 570                         ctrl &= ~NAND_CTRL_CHANGE;
 571                         chip->cmd_ctrl(mtd, column >> 8, ctrl);
 572                 }
 573                 if (page_addr != -1) {
 574                         chip->cmd_ctrl(mtd, page_addr, ctrl);
 575                         chip->cmd_ctrl(mtd, page_addr >> 8,
 576                                        NAND_NCE | NAND_ALE);
 577                         /* One more address cycle for devices > 128MiB */
 578                         if (chip->chipsize > (128 << 20))
 579                                 chip->cmd_ctrl(mtd, page_addr >> 16,
 580                                                NAND_NCE | NAND_ALE);
 581                 }
 582         }
 583         chip->cmd_ctrl(mtd, NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
 584
 585         /*
 586          * program and erase have their own busy handlers
 587          * status, sequential in, and deplete1 need no delay
 588          */
 589         switch (command) {
 590
 591         case NAND_CMD_CACHEDPROG:
 592         case NAND_CMD_PAGEPROG:
 593         case NAND_CMD_ERASE1:
 594         case NAND_CMD_ERASE2:
 595         case NAND_CMD_SEQIN:
 596         case NAND_CMD_STATUS:
 597         case NAND_CMD_DEPLETE1:
 598                 return;
 599
 600                 /*
 601                  * read error status commands require only a short delay
 602                  */
 603         case NAND_CMD_STATUS_ERROR:
 604         case NAND_CMD_STATUS_ERROR0:
 605         case NAND_CMD_STATUS_ERROR1:
 606         case NAND_CMD_STATUS_ERROR2:
 607         case NAND_CMD_STATUS_ERROR3:
 608                 udelay(chip->chip_delay);
 609                 return;
 610
 611         case NAND_CMD_RESET:
 612                 if (chip->dev_ready)
 613                         break;
 614                 udelay(chip->chip_delay);
 615                 chip->cmd_ctrl(mtd, NAND_CMD_STATUS,
 616                                NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE);
 617                 chip->cmd_ctrl(mtd, NAND_CMD_NONE,
 618                                NAND_NCE | NAND_CTRL_CHANGE);
 619                 while (!(chip->read_byte(mtd) & NAND_STATUS_READY)) ;
 620                 return;
 621
 622         case NAND_CMD_READ0:
 623                 chip->cmd_ctrl(mtd, NAND_CMD_READSTART,
 624                                NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE);
 625                 chip->cmd_ctrl(mtd, NAND_CMD_NONE,
 626                                NAND_NCE | NAND_CTRL_CHANGE);
 627
 628                 /* This applies to read commands */
 629         default:
 630                 /*
 631                  * If we don't have access to the busy pin, we apply the given
 632                  * command delay
 633                  */
 634                 if (!chip->dev_ready) {
 635                         udelay(chip->chip_delay);
 636                         return;
 637                 }
 638         }
 639
 640         /* Apply this short delay always to ensure that we do wait tWB in
 641          * any case on any machine. */
 642         ndelay(100);
 643
 644         nand_wait_ready(mtd);
 645 }
 646
 647 /**
 648  * nand_get_device - [GENERIC] Get chip for selected access
 649  * @this:       the nand chip descriptor
 650  * @mtd:        MTD device structure
 651  * @new_state:  the state which is requested
 652  *
 653  * Get the device and lock it for exclusive access
 654  */
 655 static int
 656 nand_get_device(struct nand_chip *chip, struct mtd_info *mtd, int new_state)
 657 {
 658         spinlock_t *lock = &chip->controller->lock;
 659         wait_queue_head_t *wq = &chip->controller->wq;
 660         DECLARE_WAITQUEUE(wait, current);
 661  retry:
 662         spin_lock(lock);
 663
 664         /* Hardware controller shared among independend devices */
 665         /* Hardware controller shared among independend devices */
 666         if (!chip->controller->active)
 667                 chip->controller->active = chip;
 668
 669         if (chip->controller->active == chip && chip->state == FL_READY) {
 670                 chip->state = new_state;
 671                 spin_unlock(lock);
 672                 return 0;
 673         }
 674         if (new_state == FL_PM_SUSPENDED) {
 675                 spin_unlock(lock);
 676                 return (chip->state == FL_PM_SUSPENDED) ? 0 : -EAGAIN;
 677         }
 678         set_current_state(TASK_UNINTERRUPTIBLE);
 679         add_wait_queue(wq, &wait);
 680         spin_unlock(lock);
 681         schedule();
 682         remove_wait_queue(wq, &wait);
 683         goto retry;
 684 }
 685
 686 /**
 687  * nand_wait - [DEFAULT]  wait until the command is done
 688  * @mtd:        MTD device structure
 689  * @this:       NAND chip structure
 690  * @state:      state to select the max. timeout value
 691  *
 692  * Wait for command done. This applies to erase and program only
 693  * Erase can take up to 400ms and program up to 20ms according to
 694  * general NAND and SmartMedia specs
 695  *
 696 */
 697 static int nand_wait(struct mtd_info *mtd, struct nand_chip *chip, int state)
 698 {
 699
 700         unsigned long timeo = jiffies;
 701         int status;
 702
 703         if (state == FL_ERASING)
 704                 timeo += (HZ * 400) / 1000;
 705         else
 706                 timeo += (HZ * 20) / 1000;
 707
 708         led_trigger_event(nand_led_trigger, LED_FULL);
 709
 710         /* Apply this short delay always to ensure that we do wait tWB in
 711          * any case on any machine. */
 712         ndelay(100);
 713
 714         if ((state == FL_ERASING) && (chip->options & NAND_IS_AND))
 715                 chip->cmdfunc(mtd, NAND_CMD_STATUS_MULTI, -1, -1);
 716         else
 717                 chip->cmdfunc(mtd, NAND_CMD_STATUS, -1, -1);
 718
 719         while (time_before(jiffies, timeo)) {
 720                 /* Check, if we were interrupted */
 721                 if (chip->state != state)
 722                         return 0;
 723
 724                 if (chip->dev_ready) {
 725                         if (chip->dev_ready(mtd))
 726                                 break;
 727                 } else {
 728                         if (chip->read_byte(mtd) & NAND_STATUS_READY)
 729                                 break;
 730                 }
 731                 cond_resched();
 732         }
 733         led_trigger_event(nand_led_trigger, LED_OFF);
 734
 735         status = (int)chip->read_byte(mtd);
 736         return status;
 737 }
 738
 739 /**
 740  * nand_read_page_swecc - {REPLACABLE] software ecc based page read function
 741  * @mtd:        mtd info structure
 742  * @chip:       nand chip info structure
 743  * @buf:        buffer to store read data
 744  */
 745 static int nand_read_page_swecc(struct mtd_info *mtd, struct nand_chip *chip,
 746                                 uint8_t *buf)
 747 {
 748         int i, eccsize = chip->ecc.size;
 749         int eccbytes = chip->ecc.bytes;
 750         int eccsteps = chip->ecc.steps;
 751         uint8_t *p = buf;
 752         uint8_t *ecc_calc = chip->buffers.ecccalc;
 753         uint8_t *ecc_code = chip->buffers.ecccode;
 754         int *eccpos = chip->autooob->eccpos;
 755
 756         chip->read_buf(mtd, buf, mtd->writesize);
 757         chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
 758
 759         if (chip->ecc.mode == NAND_ECC_NONE)
 760                 return 0;
 761
 762         for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize)
 763                 chip->ecc.calculate(mtd, p, &ecc_calc[i]);
 764
 765         for (i = 0; i < chip->ecc.total; i++)
 766                 ecc_code[i] = chip->oob_poi[eccpos[i]];
 767
 768         eccsteps = chip->ecc.steps;
 769         p = buf;
 770
 771         for (i = 0 ; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
 772                 int stat;
 773
 774                 stat = chip->ecc.correct(mtd, p, &ecc_code[i], &ecc_calc[i]);
 775                 if (stat == -1)
 776                         mtd->ecc_stats.failed++;
 777                 else
 778                         mtd->ecc_stats.corrected += stat;
 779         }
 780         return 0;
 781 }
 782
 783 /**
 784  * nand_read_page_hwecc - {REPLACABLE] hardware ecc based page read function
 785  * @mtd:        mtd info structure
 786  * @chip:       nand chip info structure
 787  * @buf:        buffer to store read data
 788  *
 789  * Not for syndrome calculating ecc controllers which need a special oob layout
 790  */
 791 static int nand_read_page_hwecc(struct mtd_info *mtd, struct nand_chip *chip,
 792                                 uint8_t *buf)
 793 {
 794         int i, eccsize = chip->ecc.size;
 795         int eccbytes = chip->ecc.bytes;
 796         int eccsteps = chip->ecc.steps;
 797         uint8_t *p = buf;
 798         uint8_t *ecc_calc = chip->buffers.ecccalc;
 799         uint8_t *ecc_code = chip->buffers.ecccode;
 800         int *eccpos = chip->autooob->eccpos;
 801
 802         for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
 803                 chip->ecc.hwctl(mtd, NAND_ECC_READ);
 804                 chip->read_buf(mtd, p, eccsize);
 805                 chip->ecc.calculate(mtd, p, &ecc_calc[i]);
 806         }
 807         chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
 808
 809         for (i = 0; i < chip->ecc.total; i++)
 810                 ecc_code[i] = chip->oob_poi[eccpos[i]];
 811
 812         eccsteps = chip->ecc.steps;
 813         p = buf;
 814
 815         for (i = 0 ; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
 816                 int stat;
 817
 818                 stat = chip->ecc.correct(mtd, p, &ecc_code[i], &ecc_calc[i]);
 819                 if (stat == -1)
 820                         mtd->ecc_stats.failed++;
 821                 else
 822                         mtd->ecc_stats.corrected += stat;
 823         }
 824         return 0;
 825 }
 826
 827 /**
 828  * nand_read_page_syndrome - {REPLACABLE] hardware ecc syndrom based page read
 829  * @mtd:        mtd info structure
 830  * @chip:       nand chip info structure
 831  * @buf:        buffer to store read data
 832  *
 833  * The hw generator calculates the error syndrome automatically. Therefor
 834  * we need a special oob layout and handling.
 835  */
 836 static int nand_read_page_syndrome(struct mtd_info *mtd, struct nand_chip *chip,
 837                                    uint8_t *buf)
 838 {
 839         int i, eccsize = chip->ecc.size;
 840         int eccbytes = chip->ecc.bytes;
 841         int eccsteps = chip->ecc.steps;
 842         uint8_t *p = buf;
 843         uint8_t *oob = chip->oob_poi;
 844
 845         for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
 846                 int stat;
 847
 848                 chip->ecc.hwctl(mtd, NAND_ECC_READ);
 849                 chip->read_buf(mtd, p, eccsize);
 850
 851                 if (chip->ecc.prepad) {
 852                         chip->read_buf(mtd, oob, chip->ecc.prepad);
 853                         oob += chip->ecc.prepad;
 854                 }
 855
 856                 chip->ecc.hwctl(mtd, NAND_ECC_READSYN);
 857                 chip->read_buf(mtd, oob, eccbytes);
 858                 stat = chip->ecc.correct(mtd, p, oob, NULL);
 859
 860                 if (stat == -1)
 861                         mtd->ecc_stats.failed++;
 862                 else
 863                         mtd->ecc_stats.corrected += stat;
 864
 865                 oob += eccbytes;
 866
 867                 if (chip->ecc.postpad) {
 868                         chip->read_buf(mtd, oob, chip->ecc.postpad);
 869                         oob += chip->ecc.postpad;
 870                 }
 871         }
 872
 873         /* Calculate remaining oob bytes */
 874         i = oob - chip->oob_poi;
 875         if (i)
 876                 chip->read_buf(mtd, oob, i);
 877
 878         return 0;
 879 }
 880
 881 /**
 882  * nand_do_read - [Internal] Read data with ECC
 883  *
 884  * @mtd:        MTD device structure
 885  * @from:       offset to read from
 886  * @len:        number of bytes to read
 887  * @retlen:     pointer to variable to store the number of read bytes
 888  * @buf:        the databuffer to put data
 889  *
 890  * Internal function. Called with chip held.
 891  */
 892 int nand_do_read(struct mtd_info *mtd, loff_t from, size_t len,
 893                  size_t *retlen, uint8_t *buf)
 894 {
 895         int chipnr, page, realpage, col, bytes, aligned;
 896         struct nand_chip *chip = mtd->priv;
 897         struct mtd_ecc_stats stats;
 898         int blkcheck = (1 << (chip->phys_erase_shift - chip->page_shift)) - 1;
 899         int sndcmd = 1;
 900         int ret = 0;
 901         uint32_t readlen = len;
 902         uint8_t *bufpoi;
 903
 904         stats = mtd->ecc_stats;
 905
 906         chipnr = (int)(from >> chip->chip_shift);
 907         chip->select_chip(mtd, chipnr);
 908
 909         realpage = (int)(from >> chip->page_shift);
 910         page = realpage & chip->pagemask;
 911
 912         col = (int)(from & (mtd->writesize - 1));
 913         chip->oob_poi = chip->buffers.oobrbuf;
 914
 915         while(1) {
 916                 bytes = min(mtd->writesize - col, readlen);
 917                 aligned = (bytes == mtd->writesize);
 918
 919                 /* Is the current page in the buffer ? */
 920                 if (realpage != chip->pagebuf) {
 921                         bufpoi = aligned ? buf : chip->buffers.databuf;
 922
 923                         if (likely(sndcmd)) {
 924                                 chip->cmdfunc(mtd, NAND_CMD_READ0, 0x00, page);
 925                                 sndcmd = 0;
 926                         }
 927
 928                         /* Now read the page into the buffer */
 929                         ret = chip->ecc.read_page(mtd, chip, bufpoi);
 930                         if (ret < 0)
 931                                 break;
 932
 933                         /* Transfer not aligned data */
 934                         if (!aligned) {
 935                                 chip->pagebuf = realpage;
 936                                 memcpy(buf, chip->buffers.databuf + col, bytes);
 937                         }
 938
 939                         if (!(chip->options & NAND_NO_READRDY)) {
 940                                 /*
 941                                  * Apply delay or wait for ready/busy pin. Do
 942                                  * this before the AUTOINCR check, so no
 943                                  * problems arise if a chip which does auto
 944                                  * increment is marked as NOAUTOINCR by the
 945                                  * board driver.
 946                                  */
 947                                 if (!chip->dev_ready)
 948                                         udelay(chip->chip_delay);
 949                                 else
 950                                         nand_wait_ready(mtd);
 951                         }
 952                 } else
 953                         memcpy(buf, chip->buffers.databuf + col, bytes);
 954
 955                 buf += bytes;
 956                 readlen -= bytes;
 957
 958                 if (!readlen)
 959                         break;
 960
 961                 /* For subsequent reads align to page boundary. */
 962                 col = 0;
 963                 /* Increment page address */
 964                 realpage++;
 965
 966                 page = realpage & chip->pagemask;
 967                 /* Check, if we cross a chip boundary */
 968                 if (!page) {
 969                         chipnr++;
 970                         chip->select_chip(mtd, -1);
 971                         chip->select_chip(mtd, chipnr);
 972                 }
 973
 974                 /* Check, if the chip supports auto page increment
 975                  * or if we have hit a block boundary.
 976                  */
 977                 if (!NAND_CANAUTOINCR(chip) || !(page & blkcheck))
 978                         sndcmd = 1;
 979         }
 980
 981         *retlen = len - (size_t) readlen;
 982
 983         if (ret)
 984                 return ret;
 985
 986         return mtd->ecc_stats.failed - stats.failed ? -EBADMSG : 0;
 987 }
 988
 989 /**
 990  * nand_read - [MTD Interface] MTD compability function for nand_do_read_ecc
 991  * @mtd:        MTD device structure
 992  * @from:       offset to read from
 993  * @len:        number of bytes to read
 994  * @retlen:     pointer to variable to store the number of read bytes
 995  * @buf:        the databuffer to put data
 996  *
 997  * Get hold of the chip and call nand_do_read
 998  */
 999 static int nand_read(struct mtd_info *mtd, loff_t from, size_t len,
1000                      size_t *retlen, uint8_t *buf)
1001 {
1002         int ret;
1003
1004         *retlen = 0;
1005         /* Do not allow reads past end of device */
1006         if ((from + len) > mtd->size)
1007                 return -EINVAL;
1008         if (!len)
1009                 return 0;
1010
1011         nand_get_device(mtd->priv, mtd, FL_READING);
1012
1013         ret = nand_do_read(mtd, from, len, retlen, buf);
1014
1015         nand_release_device(mtd);
1016
1017         return ret;
1018 }
1019
1020 /**
1021  * nand_read_oob - [MTD Interface] NAND read out-of-band
1022  * @mtd:        MTD device structure
1023  * @from:       offset to read from
1024  * @len:        number of bytes to read
1025  * @retlen:     pointer to variable to store the number of read bytes
1026  * @buf:        the databuffer to put data
1027  *
1028  * NAND read out-of-band data from the spare area
1029  */
1030 static int nand_read_oob(struct mtd_info *mtd, loff_t from, size_t len,
1031                          size_t *retlen, uint8_t *buf)
1032 {
1033         int col, page, realpage, chipnr, sndcmd = 1;
1034         struct nand_chip *chip = mtd->priv;
1035         int blkcheck = (1 << (chip->phys_erase_shift - chip->page_shift)) - 1;
1036         int readlen = len;
1037
1038         DEBUG(MTD_DEBUG_LEVEL3, "nand_read_oob: from = 0x%08x, len = %i\n",
1039               (unsigned int)from, (int)len);
1040
1041         /* Initialize return length value */
1042         *retlen = 0;
1043
1044         /* Do not allow reads past end of device */
1045         if ((from + len) > mtd->size) {
1046                 DEBUG(MTD_DEBUG_LEVEL0, "nand_read_oob: "
1047                       "Attempt read beyond end of device\n");
1048                 return -EINVAL;
1049         }
1050
1051         nand_get_device(chip, mtd, FL_READING);
1052
1053         chipnr = (int)(from >> chip->chip_shift);
1054         chip->select_chip(mtd, chipnr);
1055
1056         /* Shift to get page */
1057         realpage = (int)(from >> chip->page_shift);
1058         page = realpage & chip->pagemask;
1059
1060         /* Mask to get column */
1061         col = from & (mtd->oobsize - 1);
1062
1063         while(1) {
1064                 int bytes = min((int)(mtd->oobsize - col), readlen);
1065
1066                 if (likely(sndcmd)) {
1067                         chip->cmdfunc(mtd, NAND_CMD_READOOB, col, page);
1068                         sndcmd = 0;
1069                 }
1070
1071                 chip->read_buf(mtd, buf, bytes);
1072
1073                 readlen -= bytes;
1074                 if (!readlen)
1075                         break;
1076
1077                 if (!(chip->options & NAND_NO_READRDY)) {
1078                         /*
1079                          * Apply delay or wait for ready/busy pin. Do this
1080                          * before the AUTOINCR check, so no problems arise if a
1081                          * chip which does auto increment is marked as
1082                          * NOAUTOINCR by the board driver.
1083                          */
1084                         if (!chip->dev_ready)
1085                                 udelay(chip->chip_delay);
1086                         else
1087                                 nand_wait_ready(mtd);
1088                 }
1089
1090                 buf += bytes;
1091                 bytes = mtd->oobsize;
1092                 col = 0;
1093
1094                 /* Increment page address */
1095                 realpage++;
1096
1097                 page = realpage & chip->pagemask;
1098                 /* Check, if we cross a chip boundary */
1099                 if (!page) {
1100                         chipnr++;
1101                         chip->select_chip(mtd, -1);
1102                         chip->select_chip(mtd, chipnr);
1103                 }
1104
1105                 /* Check, if the chip supports auto page increment
1106                  * or if we have hit a block boundary.
1107                  */
1108                 if (!NAND_CANAUTOINCR(chip) || !(page & blkcheck))
1109                         sndcmd = 1;
1110         }
1111
1112         /* Deselect and wake up anyone waiting on the device */
1113         nand_release_device(mtd);
1114
1115         *retlen = len;
1116         return 0;
1117 }
1118
1119 /**
1120  * nand_read_raw - [GENERIC] Read raw data including oob into buffer
1121  * @mtd:        MTD device structure
1122  * @buf:        temporary buffer
1123  * @from:       offset to read from
1124  * @len:        number of bytes to read
1125  * @ooblen:     number of oob data bytes to read
1126  *
1127  * Read raw data including oob into buffer
1128  */
1129 int nand_read_raw(struct mtd_info *mtd, uint8_t *buf, loff_t from, size_t len,
1130                   size_t ooblen)
1131 {
1132         struct nand_chip *chip = mtd->priv;
1133         int page = (int)(from >> chip->page_shift);
1134         int chipnr = (int)(from >> chip->chip_shift);
1135         int sndcmd = 1;
1136         int cnt = 0;
1137         int pagesize = mtd->writesize + mtd->oobsize;
1138         int blockcheck;
1139
1140         /* Do not allow reads past end of device */
1141         if ((from + len) > mtd->size) {
1142                 DEBUG(MTD_DEBUG_LEVEL0, "nand_read_raw: "
1143                       "Attempt read beyond end of device\n");
1144                 return -EINVAL;
1145         }
1146
1147         /* Grab the lock and see if the device is available */
1148         nand_get_device(chip, mtd, FL_READING);
1149
1150         chip->select_chip(mtd, chipnr);
1151
1152         /* Add requested oob length */
1153         len += ooblen;
1154         blockcheck = (1 << (chip->phys_erase_shift - chip->page_shift)) - 1;
1155
1156         while (len) {
1157                 if (likely(sndcmd)) {
1158                         chip->cmdfunc(mtd, NAND_CMD_READ0, 0,
1159                                       page & chip->pagemask);
1160                         sndcmd = 0;
1161                 }
1162
1163                 chip->read_buf(mtd, &buf[cnt], pagesize);
1164
1165                 len -= pagesize;
1166                 cnt += pagesize;
1167                 page++;
1168
1169                 if (!(chip->options & NAND_NO_READRDY)) {
1170                         if (!chip->dev_ready)
1171                                 udelay(chip->chip_delay);
1172                         else
1173                                 nand_wait_ready(mtd);
1174                 }
1175
1176                 /*
1177                  * Check, if the chip supports auto page increment or if we
1178                  * cross a block boundary.
1179                  */
1180                 if (!NAND_CANAUTOINCR(chip) || !(page & blockcheck))
1181                         sndcmd = 1;
1182         }
1183
1184         /* Deselect and wake up anyone waiting on the device */
1185         nand_release_device(mtd);
1186         return 0;
1187 }
1188
1189 /**
1190  * nand_write_page_swecc - {REPLACABLE] software ecc based page write function
1191  * @mtd:        mtd info structure
1192  * @chip:       nand chip info structure
1193  * @buf:        data buffer
1194  */
1195 static void nand_write_page_swecc(struct mtd_info *mtd, struct nand_chip *chip,
1196                                   const uint8_t *buf)
1197 {
1198         int i, eccsize = chip->ecc.size;
1199         int eccbytes = chip->ecc.bytes;
1200         int eccsteps = chip->ecc.steps;
1201         uint8_t *ecc_calc = chip->buffers.ecccalc;
1202         const uint8_t *p = buf;
1203         int *eccpos = chip->autooob->eccpos;
1204
1205         if (chip->ecc.mode != NAND_ECC_NONE) {
1206                 /* Software ecc calculation */
1207                 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize)
1208                         chip->ecc.calculate(mtd, p, &ecc_calc[i]);
1209
1210                 for (i = 0; i < chip->ecc.total; i++)
1211                         chip->oob_poi[eccpos[i]] = ecc_calc[i];
1212         }
1213
1214         chip->write_buf(mtd, buf, mtd->writesize);
1215         chip->write_buf(mtd, chip->oob_poi, mtd->oobsize);
1216 }
1217
1218 /**
1219  * nand_write_page_hwecc - {REPLACABLE] hardware ecc based page write function
1220  * @mtd:        mtd info structure
1221  * @chip:       nand chip info structure
1222  * @buf:        data buffer
1223  */
1224 static void nand_write_page_hwecc(struct mtd_info *mtd, struct nand_chip *chip,
1225                                   const uint8_t *buf)
1226 {
1227         int i, eccsize = chip->ecc.size;
1228         int eccbytes = chip->ecc.bytes;
1229         int eccsteps = chip->ecc.steps;
1230         uint8_t *ecc_calc = chip->buffers.ecccalc;
1231         const uint8_t *p = buf;
1232         int *eccpos = chip->autooob->eccpos;
1233
1234         for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
1235                 chip->ecc.hwctl(mtd, NAND_ECC_WRITE);
1236                 chip->write_buf(mtd, p, mtd->writesize);
1237                 chip->ecc.calculate(mtd, p, &ecc_calc[i]);
1238         }
1239
1240         for (i = 0; i < chip->ecc.total; i++)
1241                 chip->oob_poi[eccpos[i]] = ecc_calc[i];
1242
1243         chip->write_buf(mtd, chip->oob_poi, mtd->oobsize);
1244 }
1245
1246 /**
1247  * nand_write_page_syndrome - {REPLACABLE] hardware ecc syndrom based page write
1248  * @mtd:        mtd info structure
1249  * @chip:       nand chip info structure
1250  * @buf:        data buffer
1251  *
1252  * The hw generator calculates the error syndrome automatically. Therefor
1253  * we need a special oob layout and handling.
1254  */
1255 static void nand_write_page_syndrome(struct mtd_info *mtd,
1256                                     struct nand_chip *chip, const uint8_t *buf)
1257 {
1258         int i, eccsize = chip->ecc.size;
1259         int eccbytes = chip->ecc.bytes;
1260         int eccsteps = chip->ecc.steps;
1261         const uint8_t *p = buf;
1262         uint8_t *oob = chip->oob_poi;
1263
1264         for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
1265
1266                 chip->ecc.hwctl(mtd, NAND_ECC_WRITE);
1267                 chip->write_buf(mtd, p, eccsize);
1268
1269                 if (chip->ecc.prepad) {
1270                         chip->write_buf(mtd, oob, chip->ecc.prepad);
1271                         oob += chip->ecc.prepad;
1272                 }
1273
1274                 chip->ecc.calculate(mtd, p, oob);
1275                 chip->write_buf(mtd, oob, eccbytes);
1276                 oob += eccbytes;
1277
1278                 if (chip->ecc.postpad) {
1279                         chip->write_buf(mtd, oob, chip->ecc.postpad);
1280                         oob += chip->ecc.postpad;
1281                 }
1282         }
1283
1284         /* Calculate remaining oob bytes */
1285         i = oob - chip->oob_poi;
1286         if (i)
1287                 chip->write_buf(mtd, oob, i);
1288 }
1289
1290 /**
1291  * nand_write_page - [INTERNAL] write one page
1292  * @mtd:        MTD device structure
1293  * @chip:       NAND chip descriptor
1294  * @buf:        the data to write
1295  * @page:       page number to write
1296  * @cached:     cached programming
1297  */
1298 static int nand_write_page(struct mtd_info *mtd, struct nand_chip *chip,
1299                            const uint8_t *buf, int page, int cached)
1300 {
1301         int status;
1302
1303         chip->cmdfunc(mtd, NAND_CMD_SEQIN, 0x00, page);
1304
1305         chip->ecc.write_page(mtd, chip, buf);
1306
1307         /*
1308          * Cached progamming disabled for now, Not sure if its worth the
1309          * trouble. The speed gain is not very impressive. (2.3->2.6Mib/s)
1310          */
1311         cached = 0;
1312
1313         if (!cached || !(chip->options & NAND_CACHEPRG)) {
1314
1315                 chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1);
1316                 status = chip->waitfunc(mtd, chip, FL_WRITING);
1317                 /*
1318                  * See if operation failed and additional status checks are
1319                  * available
1320                  */
1321                 if ((status & NAND_STATUS_FAIL) && (chip->errstat))
1322                         status = chip->errstat(mtd, chip, FL_WRITING, status,
1323                                                page);
1324
1325                 if (status & NAND_STATUS_FAIL)
1326                         return -EIO;
1327         } else {
1328                 chip->cmdfunc(mtd, NAND_CMD_CACHEDPROG, -1, -1);
1329                 status = chip->waitfunc(mtd, chip, FL_WRITING);
1330         }
1331
1332 #ifdef CONFIG_MTD_NAND_VERIFY_WRITE
1333         /* Send command to read back the data */
1334         chip->cmdfunc(mtd, NAND_CMD_READ0, 0, page);
1335
1336         if (chip->verify_buf(mtd, buf, mtd->writesize))
1337                 return -EIO;
1338 #endif
1339         return 0;
1340 }
1341
1342 #define NOTALIGNED(x) (x & (mtd->writesize-1)) != 0
1343
1344 /**
1345  * nand_write - [MTD Interface] NAND write with ECC
1346  * @mtd:        MTD device structure
1347  * @to:         offset to write to
1348  * @len:        number of bytes to write
1349  * @retlen:     pointer to variable to store the number of written bytes
1350  * @buf:        the data to write
1351  *
1352  * NAND write with ECC
1353  */
1354 static int nand_write(struct mtd_info *mtd, loff_t to, size_t len,
1355                           size_t *retlen, const uint8_t *buf)
1356 {
1357         int chipnr, realpage, page, blockmask;
1358         struct nand_chip *chip = mtd->priv;
1359         uint32_t writelen = len;
1360         int bytes = mtd->writesize;
1361         int ret = -EIO;
1362
1363         *retlen = 0;
1364
1365         /* Do not allow write past end of device */
1366         if ((to + len) > mtd->size) {
1367                 DEBUG(MTD_DEBUG_LEVEL0, "nand_write: "
1368                       "Attempt to write past end of page\n");
1369                 return -EINVAL;
1370         }
1371
1372         /* reject writes, which are not page aligned */
1373         if (NOTALIGNED(to) || NOTALIGNED(len)) {
1374                 printk(KERN_NOTICE "nand_write: "
1375                        "Attempt to write not page aligned data\n");
1376                 return -EINVAL;
1377         }
1378
1379         if (!len)
1380                 return 0;
1381
1382         nand_get_device(chip, mtd, FL_WRITING);
1383
1384         /* Check, if it is write protected */
1385         if (nand_check_wp(mtd))
1386                 goto out;
1387
1388         chipnr = (int)(to >> chip->chip_shift);
1389         chip->select_chip(mtd, chipnr);
1390
1391         realpage = (int)(to >> chip->page_shift);
1392         page = realpage & chip->pagemask;
1393         blockmask = (1 << (chip->phys_erase_shift - chip->page_shift)) - 1;
1394
1395         /* Invalidate the page cache, when we write to the cached page */
1396         if (to <= (chip->pagebuf << chip->page_shift) &&
1397             (chip->pagebuf << chip->page_shift) < (to + len))
1398                 chip->pagebuf = -1;
1399
1400         chip->oob_poi = chip->buffers.oobwbuf;
1401
1402         while(1) {
1403                 int cached = writelen > bytes && page != blockmask;
1404
1405                 ret = nand_write_page(mtd, chip, buf, page, cached);
1406                 if (ret)
1407                         break;
1408
1409                 writelen -= bytes;
1410                 if (!writelen)
1411                         break;
1412
1413                 buf += bytes;
1414                 realpage++;
1415
1416                 page = realpage & chip->pagemask;
1417                 /* Check, if we cross a chip boundary */
1418                 if (!page) {
1419                         chipnr++;
1420                         chip->select_chip(mtd, -1);
1421                         chip->select_chip(mtd, chipnr);
1422                 }
1423         }
1424  out:
1425         *retlen = len - writelen;
1426         nand_release_device(mtd);
1427         return ret;
1428 }
1429
1430 /**
1431  * nand_write_raw - [GENERIC] Write raw data including oob
1432  * @mtd:        MTD device structure
1433  * @buf:        source buffer
1434  * @to:         offset to write to
1435  * @len:        number of bytes to write
1436  * @buf:        source buffer
1437  * @oob:        oob buffer
1438  *
1439  * Write raw data including oob
1440  */
1441 int nand_write_raw(struct mtd_info *mtd, loff_t to, size_t len, size_t *retlen,
1442                    const uint8_t *buf, uint8_t *oob)
1443 {
1444         struct nand_chip *chip = mtd->priv;
1445         int page = (int)(to >> chip->page_shift);
1446         int chipnr = (int)(to >> chip->chip_shift);
1447         int ret;
1448
1449         *retlen = 0;
1450
1451         /* Do not allow writes past end of device */
1452         if ((to + len) > mtd->size) {
1453                 DEBUG(MTD_DEBUG_LEVEL0, "nand_read_raw: Attempt write "
1454                       "beyond end of device\n");
1455                 return -EINVAL;
1456         }
1457
1458         /* Grab the lock and see if the device is available */
1459         nand_get_device(chip, mtd, FL_WRITING);
1460
1461         chip->select_chip(mtd, chipnr);
1462         chip->oob_poi = oob;
1463
1464         while (len != *retlen) {
1465                 ret = nand_write_page(mtd, chip, buf, page, 0);
1466                 if (ret)
1467                         return ret;
1468                 page++;
1469                 *retlen += mtd->writesize;
1470                 buf += mtd->writesize;
1471                 chip->oob_poi += mtd->oobsize;
1472         }
1473
1474         /* Deselect and wake up anyone waiting on the device */
1475         nand_release_device(mtd);
1476         return 0;
1477 }
1478 EXPORT_SYMBOL_GPL(nand_write_raw);
1479
1480 /**
1481  * nand_write_oob - [MTD Interface] NAND write out-of-band
1482  * @mtd:        MTD device structure
1483  * @to:         offset to write to
1484  * @len:        number of bytes to write
1485  * @retlen:     pointer to variable to store the number of written bytes
1486  * @buf:        the data to write
1487  *
1488  * NAND write out-of-band
1489  */
1490 static int nand_write_oob(struct mtd_info *mtd, loff_t to, size_t len,
1491                           size_t *retlen, const uint8_t *buf)
1492 {
1493         int column, page, status, ret = -EIO, chipnr;
1494         struct nand_chip *chip = mtd->priv;
1495
1496         DEBUG(MTD_DEBUG_LEVEL3, "nand_write_oob: to = 0x%08x, len = %i\n",
1497               (unsigned int)to, (int)len);
1498
1499         /* Initialize return length value */
1500         *retlen = 0;
1501
1502         /* Do not allow write past end of page */
1503         column = to & (mtd->oobsize - 1);
1504         if ((column + len) > mtd->oobsize) {
1505                 DEBUG(MTD_DEBUG_LEVEL0, "nand_write_oob: "
1506                       "Attempt to write past end of page\n");
1507                 return -EINVAL;
1508         }
1509
1510         nand_get_device(chip, mtd, FL_WRITING);
1511
1512         chipnr = (int)(to >> chip->chip_shift);
1513         chip->select_chip(mtd, chipnr);
1514
1515         /* Shift to get page */
1516         page = (int)(to >> chip->page_shift);
1517
1518         /*
1519          * Reset the chip. Some chips (like the Toshiba TC5832DC found in one
1520          * of my DiskOnChip 2000 test units) will clear the whole data page too
1521          * if we don't do this. I have no clue why, but I seem to have 'fixed'
1522          * it in the doc2000 driver in August 1999.  dwmw2.
1523          */
1524         chip->cmdfunc(mtd, NAND_CMD_RESET, -1, -1);
1525
1526         /* Check, if it is write protected */
1527         if (nand_check_wp(mtd))
1528                 goto out;
1529
1530         /* Invalidate the page cache, if we write to the cached page */
1531         if (page == chip->pagebuf)
1532                 chip->pagebuf = -1;
1533
1534         if (NAND_MUST_PAD(chip)) {
1535                 chip->cmdfunc(mtd, NAND_CMD_SEQIN, mtd->writesize,
1536                               page & chip->pagemask);
1537                 /* prepad 0xff for partial programming */
1538                 chip->write_buf(mtd, ffchars, column);
1539                 /* write data */
1540                 chip->write_buf(mtd, buf, len);
1541                 /* postpad 0xff for partial programming */
1542                 chip->write_buf(mtd, ffchars, mtd->oobsize - (len + column));
1543         } else {
1544                 chip->cmdfunc(mtd, NAND_CMD_SEQIN, mtd->writesize + column,
1545                               page & chip->pagemask);
1546                 chip->write_buf(mtd, buf, len);
1547         }
1548         /* Send command to program the OOB data */
1549         chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1);
1550
1551         status = chip->waitfunc(mtd, chip, FL_WRITING);
1552
1553         /* See if device thinks it succeeded */
1554         if (status & NAND_STATUS_FAIL) {
1555                 DEBUG(MTD_DEBUG_LEVEL0, "nand_write_oob: "
1556                       "Failed write, page 0x%08x\n", page);
1557                 ret = -EIO;
1558                 goto out;
1559         }
1560         *retlen = len;
1561
1562 #ifdef CONFIG_MTD_NAND_VERIFY_WRITE
1563         /* Send command to read back the data */
1564         chip->cmdfunc(mtd, NAND_CMD_READOOB, column, page & chip->pagemask);
1565
1566         if (chip->verify_buf(mtd, buf, len)) {
1567                 DEBUG(MTD_DEBUG_LEVEL0, "nand_write_oob: "
1568                       "Failed write verify, page 0x%08x\n", page);
1569                 ret = -EIO;
1570                 goto out;
1571         }
1572 #endif
1573         ret = 0;
1574  out:
1575         /* Deselect and wake up anyone waiting on the device */
1576         nand_release_device(mtd);
1577
1578         return ret;
1579 }
1580
1581 /**
1582  * single_erease_cmd - [GENERIC] NAND standard block erase command function
1583  * @mtd:        MTD device structure
1584  * @page:       the page address of the block which will be erased
1585  *
1586  * Standard erase command for NAND chips
1587  */
1588 static void single_erase_cmd(struct mtd_info *mtd, int page)
1589 {
1590         struct nand_chip *chip = mtd->priv;
1591         /* Send commands to erase a block */
1592         chip->cmdfunc(mtd, NAND_CMD_ERASE1, -1, page);
1593         chip->cmdfunc(mtd, NAND_CMD_ERASE2, -1, -1);
1594 }
1595
1596 /**
1597  * multi_erease_cmd - [GENERIC] AND specific block erase command function
1598  * @mtd:        MTD device structure
1599  * @page:       the page address of the block which will be erased
1600  *
1601  * AND multi block erase command function
1602  * Erase 4 consecutive blocks
1603  */
1604 static void multi_erase_cmd(struct mtd_info *mtd, int page)
1605 {
1606         struct nand_chip *chip = mtd->priv;
1607         /* Send commands to erase a block */
1608         chip->cmdfunc(mtd, NAND_CMD_ERASE1, -1, page++);
1609         chip->cmdfunc(mtd, NAND_CMD_ERASE1, -1, page++);
1610         chip->cmdfunc(mtd, NAND_CMD_ERASE1, -1, page++);
1611         chip->cmdfunc(mtd, NAND_CMD_ERASE1, -1, page);
1612         chip->cmdfunc(mtd, NAND_CMD_ERASE2, -1, -1);
1613 }
1614
1615 /**
1616  * nand_erase - [MTD Interface] erase block(s)
1617  * @mtd:        MTD device structure
1618  * @instr:      erase instruction
1619  *
1620  * Erase one ore more blocks
1621  */
1622 static int nand_erase(struct mtd_info *mtd, struct erase_info *instr)
1623 {
1624         return nand_erase_nand(mtd, instr, 0);
1625 }
1626
1627 #define BBT_PAGE_MASK   0xffffff3f
1628 /**
1629  * nand_erase_nand - [Internal] erase block(s)
1630  * @mtd:        MTD device structure
1631  * @instr:      erase instruction
1632  * @allowbbt:   allow erasing the bbt area
1633  *
1634  * Erase one ore more blocks
1635  */
1636 int nand_erase_nand(struct mtd_info *mtd, struct erase_info *instr,
1637                     int allowbbt)
1638 {
1639         int page, len, status, pages_per_block, ret, chipnr;
1640         struct nand_chip *chip = mtd->priv;
1641         int rewrite_bbt[NAND_MAX_CHIPS]={0};
1642         unsigned int bbt_masked_page = 0xffffffff;
1643
1644         DEBUG(MTD_DEBUG_LEVEL3, "nand_erase: start = 0x%08x, len = %i\n",
1645               (unsigned int)instr->addr, (unsigned int)instr->len);
1646
1647         /* Start address must align on block boundary */
1648         if (instr->addr & ((1 << chip->phys_erase_shift) - 1)) {
1649                 DEBUG(MTD_DEBUG_LEVEL0, "nand_erase: Unaligned address\n");
1650                 return -EINVAL;
1651         }
1652
1653         /* Length must align on block boundary */
1654         if (instr->len & ((1 << chip->phys_erase_shift) - 1)) {
1655                 DEBUG(MTD_DEBUG_LEVEL0, "nand_erase: "
1656                       "Length not block aligned\n");
1657                 return -EINVAL;
1658         }
1659
1660         /* Do not allow erase past end of device */
1661         if ((instr->len + instr->addr) > mtd->size) {
1662                 DEBUG(MTD_DEBUG_LEVEL0, "nand_erase: "
1663                       "Erase past end of device\n");
1664                 return -EINVAL;
1665         }
1666
1667         instr->fail_addr = 0xffffffff;
1668
1669         /* Grab the lock and see if the device is available */
1670         nand_get_device(chip, mtd, FL_ERASING);
1671
1672         /* Shift to get first page */
1673         page = (int)(instr->addr >> chip->page_shift);
1674         chipnr = (int)(instr->addr >> chip->chip_shift);
1675
1676         /* Calculate pages in each block */
1677         pages_per_block = 1 << (chip->phys_erase_shift - chip->page_shift);
1678
1679         /* Select the NAND device */
1680         chip->select_chip(mtd, chipnr);
1681
1682         /* Check, if it is write protected */
1683         if (nand_check_wp(mtd)) {
1684                 DEBUG(MTD_DEBUG_LEVEL0, "nand_erase: "
1685                       "Device is write protected!!!\n");
1686                 instr->state = MTD_ERASE_FAILED;
1687                 goto erase_exit;
1688         }
1689
1690         /*
1691          * If BBT requires refresh, set the BBT page mask to see if the BBT
1692          * should be rewritten. Otherwise the mask is set to 0xffffffff which
1693          * can not be matched. This is also done when the bbt is actually
1694          * erased to avoid recusrsive updates
1695          */
1696         if (chip->options & BBT_AUTO_REFRESH && !allowbbt)
1697                 bbt_masked_page = chip->bbt_td->pages[chipnr] & BBT_PAGE_MASK;
1698
1699         /* Loop through the pages */
1700         len = instr->len;
1701
1702         instr->state = MTD_ERASING;
1703
1704         while (len) {
1705                 /*
1706                  * heck if we have a bad block, we do not erase bad blocks !
1707                  */
1708                 if (nand_block_checkbad(mtd, ((loff_t) page) <<
1709                                         chip->page_shift, 0, allowbbt)) {
1710                         printk(KERN_WARNING "nand_erase: attempt to erase a "
1711                                "bad block at page 0x%08x\n", page);
1712                         instr->state = MTD_ERASE_FAILED;
1713                         goto erase_exit;
1714                 }
1715
1716                 /*
1717                  * Invalidate the page cache, if we erase the block which
1718                  * contains the current cached page
1719                  */
1720                 if (page <= chip->pagebuf && chip->pagebuf <
1721                     (page + pages_per_block))
1722                         chip->pagebuf = -1;
1723
1724                 chip->erase_cmd(mtd, page & chip->pagemask);
1725
1726                 status = chip->waitfunc(mtd, chip, FL_ERASING);
1727
1728                 /*
1729                  * See if operation failed and additional status checks are
1730                  * available
1731                  */
1732                 if ((status & NAND_STATUS_FAIL) && (chip->errstat))
1733                         status = chip->errstat(mtd, chip, FL_ERASING,
1734                                                status, page);
1735
1736                 /* See if block erase succeeded */
1737                 if (status & NAND_STATUS_FAIL) {
1738                         DEBUG(MTD_DEBUG_LEVEL0, "nand_erase: "
1739                               "Failed erase, page 0x%08x\n", page);
1740                         instr->state = MTD_ERASE_FAILED;
1741                         instr->fail_addr = (page << chip->page_shift);
1742                         goto erase_exit;
1743                 }
1744
1745                 /*
1746                  * If BBT requires refresh, set the BBT rewrite flag to the
1747                  * page being erased
1748                  */
1749                 if (bbt_masked_page != 0xffffffff &&
1750                     (page & BBT_PAGE_MASK) == bbt_masked_page)
1751                             rewrite_bbt[chipnr] = (page << chip->page_shift);
1752
1753                 /* Increment page address and decrement length */
1754                 len -= (1 << chip->phys_erase_shift);
1755                 page += pages_per_block;
1756
1757                 /* Check, if we cross a chip boundary */
1758                 if (len && !(page & chip->pagemask)) {
1759                         chipnr++;
1760                         chip->select_chip(mtd, -1);
1761                         chip->select_chip(mtd, chipnr);
1762
1763                         /*
1764                          * If BBT requires refresh and BBT-PERCHIP, set the BBT
1765                          * page mask to see if this BBT should be rewritten
1766                          */
1767                         if (bbt_masked_page != 0xffffffff &&
1768                             (chip->bbt_td->options & NAND_BBT_PERCHIP))
1769                                 bbt_masked_page = chip->bbt_td->pages[chipnr] &
1770                                         BBT_PAGE_MASK;
1771                 }
1772         }
1773         instr->state = MTD_ERASE_DONE;
1774
1775  erase_exit:
1776
1777         ret = instr->state == MTD_ERASE_DONE ? 0 : -EIO;
1778         /* Do call back function */
1779         if (!ret)
1780                 mtd_erase_callback(instr);
1781
1782         /* Deselect and wake up anyone waiting on the device */
1783         nand_release_device(mtd);
1784
1785         /*
1786          * If BBT requires refresh and erase was successful, rewrite any
1787          * selected bad block tables
1788          */
1789         if (bbt_masked_page == 0xffffffff || ret)
1790                 return ret;
1791
1792         for (chipnr = 0; chipnr < chip->numchips; chipnr++) {
1793                 if (!rewrite_bbt[chipnr])
1794                         continue;
1795                 /* update the BBT for chip */
1796                 DEBUG(MTD_DEBUG_LEVEL0, "nand_erase_nand: nand_update_bbt "
1797                       "(%d:0x%0x 0x%0x)\n", chipnr, rewrite_bbt[chipnr],
1798                       chip->bbt_td->pages[chipnr]);
1799                 nand_update_bbt(mtd, rewrite_bbt[chipnr]);
1800         }
1801
1802         /* Return more or less happy */
1803         return ret;
1804 }
1805
1806 /**
1807  * nand_sync - [MTD Interface] sync
1808  * @mtd:        MTD device structure
1809  *
1810  * Sync is actually a wait for chip ready function
1811  */
1812 static void nand_sync(struct mtd_info *mtd)
1813 {
1814         struct nand_chip *chip = mtd->priv;
1815
1816         DEBUG(MTD_DEBUG_LEVEL3, "nand_sync: called\n");
1817
1818         /* Grab the lock and see if the device is available */
1819         nand_get_device(chip, mtd, FL_SYNCING);
1820         /* Release it and go back */
1821         nand_release_device(mtd);
1822 }
1823
1824 /**
1825  * nand_block_isbad - [MTD Interface] Check if block at offset is bad
1826  * @mtd:        MTD device structure
1827  * @ofs:        offset relative to mtd start
1828  */
1829 static int nand_block_isbad(struct mtd_info *mtd, loff_t offs)
1830 {
1831         /* Check for invalid offset */
1832         if (offs > mtd->size)
1833                 return -EINVAL;
1834
1835         return nand_block_checkbad(mtd, offs, 1, 0);
1836 }
1837
1838 /**
1839  * nand_block_markbad - [MTD Interface] Mark block at the given offset as bad
1840  * @mtd:        MTD device structure
1841  * @ofs:        offset relative to mtd start
1842  */
1843 static int nand_block_markbad(struct mtd_info *mtd, loff_t ofs)
1844 {
1845         struct nand_chip *chip = mtd->priv;
1846         int ret;
1847
1848         if ((ret = nand_block_isbad(mtd, ofs))) {
1849                 /* If it was bad already, return success and do nothing. */
1850                 if (ret > 0)
1851                         return 0;
1852                 return ret;
1853         }
1854
1855         return chip->block_markbad(mtd, ofs);
1856 }
1857
1858 /**
1859  * nand_suspend - [MTD Interface] Suspend the NAND flash
1860  * @mtd:        MTD device structure
1861  */
1862 static int nand_suspend(struct mtd_info *mtd)
1863 {
1864         struct nand_chip *chip = mtd->priv;
1865
1866         return nand_get_device(chip, mtd, FL_PM_SUSPENDED);
1867 }
1868
1869 /**
1870  * nand_resume - [MTD Interface] Resume the NAND flash
1871  * @mtd:        MTD device structure
1872  */
1873 static void nand_resume(struct mtd_info *mtd)
1874 {
1875         struct nand_chip *chip = mtd->priv;
1876
1877         if (chip->state == FL_PM_SUSPENDED)
1878                 nand_release_device(mtd);
1879         else
1880                 printk(KERN_ERR "nand_resume() called for a chip which is not "
1881                        "in suspended state\n");
1882 }
1883
1884 /*
1885  * Set default functions
1886  */
1887 static void nand_set_defaults(struct nand_chip *chip, int busw)
1888 {
1889         /* check for proper chip_delay setup, set 20us if not */
1890         if (!chip->chip_delay)
1891                 chip->chip_delay = 20;
1892
1893         /* check, if a user supplied command function given */
1894         if (chip->cmdfunc == NULL)
1895                 chip->cmdfunc = nand_command;
1896
1897         /* check, if a user supplied wait function given */
1898         if (chip->waitfunc == NULL)
1899                 chip->waitfunc = nand_wait;
1900
1901         if (!chip->select_chip)
1902                 chip->select_chip = nand_select_chip;
1903         if (!chip->read_byte)
1904                 chip->read_byte = busw ? nand_read_byte16 : nand_read_byte;
1905         if (!chip->read_word)
1906                 chip->read_word = nand_read_word;
1907         if (!chip->block_bad)
1908                 chip->block_bad = nand_block_bad;
1909         if (!chip->block_markbad)
1910                 chip->block_markbad = nand_default_block_markbad;
1911         if (!chip->write_buf)
1912                 chip->write_buf = busw ? nand_write_buf16 : nand_write_buf;
1913         if (!chip->read_buf)
1914                 chip->read_buf = busw ? nand_read_buf16 : nand_read_buf;
1915         if (!chip->verify_buf)
1916                 chip->verify_buf = busw ? nand_verify_buf16 : nand_verify_buf;
1917         if (!chip->scan_bbt)
1918                 chip->scan_bbt = nand_default_bbt;
1919
1920         if (!chip->controller) {
1921                 chip->controller = &chip->hwcontrol;
1922                 spin_lock_init(&chip->controller->lock);
1923                 init_waitqueue_head(&chip->controller->wq);
1924         }
1925
1926 }
1927
1928 /*
1929  * Get the flash and manufacturer id and lookup if the type is supported
1930  */
1931 static struct nand_flash_dev *nand_get_flash_type(struct mtd_info *mtd,
1932                                                   struct nand_chip *chip,
1933                                                   int busw, int *maf_id)
1934 {
1935         struct nand_flash_dev *type = NULL;
1936         int i, dev_id, maf_idx;
1937
1938         /* Select the device */
1939         chip->select_chip(mtd, 0);
1940
1941         /* Send the command for reading device ID */
1942         chip->cmdfunc(mtd, NAND_CMD_READID, 0x00, -1);
1943
1944         /* Read manufacturer and device IDs */
1945         *maf_id = chip->read_byte(mtd);
1946         dev_id = chip->read_byte(mtd);
1947
1948         /* Lookup the flash id */
1949         for (i = 0; nand_flash_ids[i].name != NULL; i++) {
1950                 if (dev_id == nand_flash_ids[i].id) {
1951                         type =  &nand_flash_ids[i];
1952                         break;
1953                 }
1954         }
1955
1956         if (!type)
1957                 return ERR_PTR(-ENODEV);
1958
1959         chip->chipsize = nand_flash_ids[i].chipsize << 20;
1960
1961         /* Newer devices have all the information in additional id bytes */
1962         if (!nand_flash_ids[i].pagesize) {
1963                 int extid;
1964                 /* The 3rd id byte contains non relevant data ATM */
1965                 extid = chip->read_byte(mtd);
1966                 /* The 4th id byte is the important one */
1967                 extid = chip->read_byte(mtd);
1968                 /* Calc pagesize */
1969                 mtd->writesize = 1024 << (extid & 0x3);
1970                 extid >>= 2;
1971                 /* Calc oobsize */
1972                 mtd->oobsize = (8 << (extid & 0x01)) * (mtd->writesize >> 9);
1973                 extid >>= 2;
1974                 /* Calc blocksize. Blocksize is multiples of 64KiB */
1975                 mtd->erasesize = (64 * 1024) << (extid & 0x03);
1976                 extid >>= 2;
1977                 /* Get buswidth information */
1978                 busw = (extid & 0x01) ? NAND_BUSWIDTH_16 : 0;
1979
1980         } else {
1981                 /*
1982                  * Old devices have chip data hardcoded in the device id table
1983                  */
1984                 mtd->erasesize = nand_flash_ids[i].erasesize;
1985                 mtd->writesize = nand_flash_ids[i].pagesize;
1986                 mtd->oobsize = mtd->writesize / 32;
1987                 busw = nand_flash_ids[i].options & NAND_BUSWIDTH_16;
1988         }
1989
1990         /* Try to identify manufacturer */
1991         for (maf_idx = 0; nand_manuf_ids[maf_idx].id != 0x0; maf_id++) {
1992                 if (nand_manuf_ids[maf_idx].id == *maf_id)
1993                         break;
1994         }
1995
1996         /*
1997          * Check, if buswidth is correct. Hardware drivers should set
1998          * chip correct !
1999          */
2000         if (busw != (chip->options & NAND_BUSWIDTH_16)) {
2001                 printk(KERN_INFO "NAND device: Manufacturer ID:"
2002                        " 0x%02x, Chip ID: 0x%02x (%s %s)\n", *maf_id,
2003                        dev_id, nand_manuf_ids[maf_idx].name, mtd->name);
2004                 printk(KERN_WARNING "NAND bus width %d instead %d bit\n",
2005                        (chip->options & NAND_BUSWIDTH_16) ? 16 : 8,
2006                        busw ? 16 : 8);
2007                 return ERR_PTR(-EINVAL);
2008         }
2009
2010         /* Calculate the address shift from the page size */
2011         chip->page_shift = ffs(mtd->writesize) - 1;
2012         /* Convert chipsize to number of pages per chip -1. */
2013         chip->pagemask = (chip->chipsize >> chip->page_shift) - 1;
2014
2015         chip->bbt_erase_shift = chip->phys_erase_shift =
2016                 ffs(mtd->erasesize) - 1;
2017         chip->chip_shift = ffs(chip->chipsize) - 1;
2018
2019         /* Set the bad block position */
2020         chip->badblockpos = mtd->writesize > 512 ?
2021                 NAND_LARGE_BADBLOCK_POS : NAND_SMALL_BADBLOCK_POS;
2022
2023         /* Get chip options, preserve non chip based options */
2024         chip->options &= ~NAND_CHIPOPTIONS_MSK;
2025         chip->options |= nand_flash_ids[i].options & NAND_CHIPOPTIONS_MSK;
2026
2027         /*
2028          * Set chip as a default. Board drivers can override it, if necessary
2029          */
2030         chip->options |= NAND_NO_AUTOINCR;
2031
2032         /* Check if chip is a not a samsung device. Do not clear the
2033          * options for chips which are not having an extended id.
2034          */
2035         if (*maf_id != NAND_MFR_SAMSUNG && !nand_flash_ids[i].pagesize)
2036                 chip->options &= ~NAND_SAMSUNG_LP_OPTIONS;
2037
2038         /* Check for AND chips with 4 page planes */
2039         if (chip->options & NAND_4PAGE_ARRAY)
2040                 chip->erase_cmd = multi_erase_cmd;
2041         else
2042                 chip->erase_cmd = single_erase_cmd;
2043
2044         /* Do not replace user supplied command function ! */
2045         if (mtd->writesize > 512 && chip->cmdfunc == nand_command)
2046                 chip->cmdfunc = nand_command_lp;
2047
2048         printk(KERN_INFO "NAND device: Manufacturer ID:"
2049                " 0x%02x, Chip ID: 0x%02x (%s %s)\n", *maf_id, dev_id,
2050                nand_manuf_ids[maf_idx].name, type->name);
2051
2052         return type;
2053 }
2054
2055 /* module_text_address() isn't exported, and it's mostly a pointless
2056    test if this is a module _anyway_ -- they'd have to try _really_ hard
2057    to call us from in-kernel code if the core NAND support is modular. */
2058 #ifdef MODULE
2059 #define caller_is_module() (1)
2060 #else
2061 #define caller_is_module() \
2062         module_text_address((unsigned long)__builtin_return_address(0))
2063 #endif
2064
2065 /**
2066  * nand_scan - [NAND Interface] Scan for the NAND device
2067  * @mtd:        MTD device structure
2068  * @maxchips:   Number of chips to scan for
2069  *
2070  * This fills out all the uninitialized function pointers
2071  * with the defaults.
2072  * The flash ID is read and the mtd/chip structures are
2073  * filled with the appropriate values.
2074  * The mtd->owner field must be set to the module of the caller
2075  *
2076  */
2077 int nand_scan(struct mtd_info *mtd, int maxchips)
2078 {
2079         int i, busw, nand_maf_id;
2080         struct nand_chip *chip = mtd->priv;
2081         struct nand_flash_dev *type;
2082
2083         /* Many callers got this wrong, so check for it for a while... */
2084         if (!mtd->owner && caller_is_module()) {
2085                 printk(KERN_CRIT "nand_scan() called with NULL mtd->owner!\n");
2086                 BUG();
2087         }
2088
2089         /* Get buswidth to select the correct functions */
2090         busw = chip->options & NAND_BUSWIDTH_16;
2091         /* Set the default functions */
2092         nand_set_defaults(chip, busw);
2093
2094         /* Read the flash type */
2095         type = nand_get_flash_type(mtd, chip, busw, &nand_maf_id);
2096
2097         if (IS_ERR(type)) {
2098                 printk(KERN_WARNING "No NAND device found!!!\n");
2099                 chip->select_chip(mtd, -1);
2100                 return PTR_ERR(type);
2101         }
2102
2103         /* Check for a chip array */
2104         for (i = 1; i < maxchips; i++) {
2105                 chip->select_chip(mtd, i);
2106                 /* Send the command for reading device ID */
2107                 chip->cmdfunc(mtd, NAND_CMD_READID, 0x00, -1);
2108                 /* Read manufacturer and device IDs */
2109                 if (nand_maf_id != chip->read_byte(mtd) ||
2110                     type->id != chip->read_byte(mtd))
2111                         break;
2112         }
2113         if (i > 1)
2114                 printk(KERN_INFO "%d NAND chips detected\n", i);
2115
2116         /* Store the number of chips and calc total size for mtd */
2117         chip->numchips = i;
2118         mtd->size = i * chip->chipsize;
2119
2120         /* Preset the internal oob write buffer */
2121         memset(chip->buffers.oobwbuf, 0xff, mtd->oobsize);
2122
2123         /*
2124          * If no default placement scheme is given, select an appropriate one
2125          */
2126         if (!chip->autooob) {
2127                 switch (mtd->oobsize) {
2128                 case 8:
2129                         chip->autooob = &nand_oob_8;
2130                         break;
2131                 case 16:
2132                         chip->autooob = &nand_oob_16;
2133                         break;
2134                 case 64:
2135                         chip->autooob = &nand_oob_64;
2136                         break;
2137                 default:
2138                         printk(KERN_WARNING "No oob scheme defined for "
2139                                "oobsize %d\n", mtd->oobsize);
2140                         BUG();
2141                 }
2142         }
2143
2144         /*
2145          * The number of bytes available for the filesystem to place fs
2146          * dependend oob data
2147          */
2148         mtd->oobavail = 0;
2149         for (i = 0; chip->autooob->oobfree[i][1]; i++)
2150                 mtd->oobavail += chip->autooob->oobfree[i][1];
2151
2152         /*
2153          * check ECC mode, default to software if 3byte/512byte hardware ECC is
2154          * selected and we have 256 byte pagesize fallback to software ECC
2155          */
2156         switch (chip->ecc.mode) {
2157         case NAND_ECC_HW:
2158                 /* Use standard hwecc read page function ? */
2159                 if (!chip->ecc.read_page)
2160                         chip->ecc.read_page = nand_read_page_hwecc;
2161                 if (!chip->ecc.write_page)
2162                         chip->ecc.write_page = nand_write_page_hwecc;
2163
2164         case NAND_ECC_HW_SYNDROME:
2165                 if (!chip->ecc.calculate || !chip->ecc.correct ||
2166                     !chip->ecc.hwctl) {
2167                         printk(KERN_WARNING "No ECC functions supplied, "
2168                                "Hardware ECC not possible\n");
2169                         BUG();
2170                 }
2171                 /* Use standard syndrome read/write page function ? */
2172                 if (!chip->ecc.read_page)
2173                         chip->ecc.read_page = nand_read_page_syndrome;
2174                 if (!chip->ecc.write_page)
2175                         chip->ecc.write_page = nand_write_page_syndrome;
2176
2177                 if (mtd->writesize >= chip->ecc.size)
2178                         break;
2179                 printk(KERN_WARNING "%d byte HW ECC not possible on "
2180                        "%d byte page size, fallback to SW ECC\n",
2181                        chip->ecc.size, mtd->writesize);
2182                 chip->ecc.mode = NAND_ECC_SOFT;
2183
2184         case NAND_ECC_SOFT:
2185                 chip->ecc.calculate = nand_calculate_ecc;
2186                 chip->ecc.correct = nand_correct_data;
2187                 chip->ecc.read_page = nand_read_page_swecc;
2188                 chip->ecc.write_page = nand_write_page_swecc;
2189                 chip->ecc.size = 256;
2190                 chip->ecc.bytes = 3;
2191                 break;
2192
2193         case NAND_ECC_NONE:
2194                 printk(KERN_WARNING "NAND_ECC_NONE selected by board driver. "
2195                        "This is not recommended !!\n");
2196                 chip->ecc.read_page = nand_read_page_swecc;
2197                 chip->ecc.write_page = nand_write_page_swecc;
2198                 chip->ecc.size = mtd->writesize;
2199                 chip->ecc.bytes = 0;
2200                 break;
2201         default:
2202                 printk(KERN_WARNING "Invalid NAND_ECC_MODE %d\n",
2203                        chip->ecc.mode);
2204                 BUG();
2205         }
2206
2207         /*
2208          * Set the number of read / write steps for one page depending on ECC
2209          * mode
2210          */
2211         chip->ecc.steps = mtd->writesize / chip->ecc.size;
2212         if(chip->ecc.steps * chip->ecc.size != mtd->writesize) {
2213                 printk(KERN_WARNING "Invalid ecc parameters\n");
2214                 BUG();
2215         }
2216         chip->ecc.total = chip->ecc.steps * chip->ecc.bytes;
2217
2218         /* Initialize state */
2219         chip->state = FL_READY;
2220
2221         /* De-select the device */
2222         chip->select_chip(mtd, -1);
2223
2224         /* Invalidate the pagebuffer reference */
2225         chip->pagebuf = -1;
2226
2227         /* Fill in remaining MTD driver data */
2228         mtd->type = MTD_NANDFLASH;
2229         mtd->flags = MTD_CAP_NANDFLASH;
2230         mtd->ecctype = MTD_ECC_SW;
2231         mtd->erase = nand_erase;
2232         mtd->point = NULL;
2233         mtd->unpoint = NULL;
2234         mtd->read = nand_read;
2235         mtd->write = nand_write;
2236         mtd->read_oob = nand_read_oob;
2237         mtd->write_oob = nand_write_oob;
2238         mtd->sync = nand_sync;
2239         mtd->lock = NULL;
2240         mtd->unlock = NULL;
2241         mtd->suspend = nand_suspend;
2242         mtd->resume = nand_resume;
2243         mtd->block_isbad = nand_block_isbad;
2244         mtd->block_markbad = nand_block_markbad;
2245
2246         /* and make the autooob the default one */
2247         memcpy(&mtd->oobinfo, chip->autooob, sizeof(mtd->oobinfo));
2248
2249         /* Check, if we should skip the bad block table scan */
2250         if (chip->options & NAND_SKIP_BBTSCAN)
2251                 return 0;
2252
2253         /* Build bad block table */
2254         return chip->scan_bbt(mtd);
2255 }
2256
2257 /**
2258  * nand_release - [NAND Interface] Free resources held by the NAND device
2259  * @mtd:        MTD device structure
2260 */
2261 void nand_release(struct mtd_info *mtd)
2262 {
2263         struct nand_chip *chip = mtd->priv;
2264
2265 #ifdef CONFIG_MTD_PARTITIONS
2266         /* Deregister partitions */
2267         del_mtd_partitions(mtd);
2268 #endif
2269         /* Deregister the device */
2270         del_mtd_device(mtd);
2271
2272         /* Free bad block table memory */
2273         kfree(chip->bbt);
2274 }
2275
2276 EXPORT_SYMBOL_GPL(nand_scan);
2277 EXPORT_SYMBOL_GPL(nand_release);
2278
2279 static int __init nand_base_init(void)
2280 {
2281         led_trigger_register_simple("nand-disk", &nand_led_trigger);
2282         return 0;
2283 }
2284
2285 static void __exit nand_base_exit(void)
2286 {
2287         led_trigger_unregister_simple(nand_led_trigger);
2288 }
2289
2290 module_init(nand_base_init);
2291 module_exit(nand_base_exit);
2292
2293 MODULE_LICENSE("GPL");
2294 MODULE_AUTHOR("Steven J. Hill <sjhill@realitydiluted.com>, Thomas Gleixner <tglx@linutronix.de>");
2295 MODULE_DESCRIPTION("Generic NAND flash driver code");